diff options
Diffstat (limited to 'snapshots/coq')
27 files changed, 58791 insertions, 3376 deletions
diff --git a/snapshots/coq/README b/snapshots/coq/README deleted file mode 100644 index bd7f12d0..00000000 --- a/snapshots/coq/README +++ /dev/null @@ -1,2 +0,0 @@ -Check out a copy of https://github.com/mit-plv/bbv in the parent directory and -build it. Then run ./build. diff --git a/snapshots/coq/README.md b/snapshots/coq/README.md new file mode 100644 index 00000000..8cc69d7f --- /dev/null +++ b/snapshots/coq/README.md @@ -0,0 +1,7 @@ +Check out a copy of <https://github.com/mit-plv/bbv> in the parent directory and +build it. Then run `./build`. + +The model was built with +* `sail` commit `1c80d84c` +* `sail-cheri-mips` commit `17deb9f2` +and checked against bbv commit `8f5aece` and coq 8.8.2. diff --git a/snapshots/coq/build b/snapshots/coq/build index e672912e..a4afcd95 100755 --- a/snapshots/coq/build +++ b/snapshots/coq/build @@ -1,7 +1,7 @@ #!/bin/bash -if [ ! -d mips ]; then - echo Run clean from the coq directory +if [ ! -d cheri-mips ]; then + echo Run build from the coq directory exit 1 fi @@ -13,7 +13,13 @@ fi set -ex cd lib/coq make -cd ../../mips +cd ../../cheri-mips coqc -R ../../bbv/theories bbv -R ../lib/coq Sail mips_extras.v coqc -R ../../bbv/theories bbv -R ../lib/coq Sail mips_types.v coqc -R ../../bbv/theories bbv -R ../lib/coq Sail mips.v +coqc -R ../../bbv/theories bbv -R ../lib/coq Sail cheri_types.v +coqc -R ../../bbv/theories bbv -R ../lib/coq Sail cheri.v +cd ../riscv +coqc -R ../../bbv/theories bbv -R ../lib/coq Sail riscv_extras.v +coqc -R ../../bbv/theories bbv -R ../lib/coq Sail riscv_types.v +coqc -R ../../bbv/theories bbv -R ../lib/coq Sail riscv.v diff --git a/snapshots/coq/mips/_CoqProject b/snapshots/coq/cheri-mips/_CoqProject index ad38d28d..ad38d28d 100644 --- a/snapshots/coq/mips/_CoqProject +++ b/snapshots/coq/cheri-mips/_CoqProject diff --git a/snapshots/coq/cheri-mips/cheri.v b/snapshots/coq/cheri-mips/cheri.v new file mode 100644 index 00000000..3a5b0ce6 --- /dev/null +++ b/snapshots/coq/cheri-mips/cheri.v @@ -0,0 +1,12167 @@ +(*Generated by Sail from cheri.*) +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_string. +Require Import Sail2_real. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import Sail2_state. +Require Import cheri_types. +Require Import mips_extras. +Import ListNotations. +Open Scope string. +Open Scope bool. +Section Content. + +Definition cap_size := 32. +Hint Unfold cap_size : sail. +Definition trace : bool := false. +Hint Unfold trace : sail. +Definition eq_unit (g__19 : unit) (g__20 : unit) : bool := true. + +Definition neq_int (x : Z) (y : Z) : bool := negb (Z.eqb x y). + +Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y). + +Definition undefined_option {a : Type} (typ_a : a) +: M (option a) := + + (undefined_unit tt) >>= fun u_0 : unit => + let u_1 : a := typ_a in + (internal_pick [Some (u_1);None]) + : M (option a). + +Definition is_none {a : Type} (opt : option a) +: bool := + + match opt with | Some (_) => false | None => true end. + +Definition is_some {a : Type} (opt : option a) +: bool := + + match opt with | Some (_) => true | None => false end. + +Definition sail_mask {v0 : Z} (len : Z) (v : mword v0) `{ArithFact (len >= 0 /\ v0 >= 0)} +: mword len := + + if sumbool_of_bool ((Z.leb len (length_mword v))) then vector_truncate v len + else zero_extend v len. + +Definition neq_vec {n : Z} (x : mword n) (y : mword n) : bool := negb (eq_vec x y). + + + +Definition cast_unit_vec (b : bitU) +: mword 1 := + + match b with | B0 => (vec_of_bits [B0] : mword 1) | _ => (vec_of_bits [B1] : mword 1) end. + +Definition __MIPS_write (addr : mword 64) (width : Z) (data : mword (8 * width)) +: M (unit) := + + (write_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr data) >> + returnm (tt + : unit). + +Definition __MIPS_read (addr : mword 64) (width : Z) `{ArithFact (width >= 0)} +: M (mword (8 * width)) := + + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) + : M (mword (8 * width)). + +Definition zopz0zQzQ {n0 : Z} (bs : mword n0) (n : Z) `{ArithFact (n >= 0)} +: mword (n0 * n) := + + replicate_bits bs n. + +Definition undefined_exception '(tt : unit) +: M (exception) := + + (undefined_string tt) >>= fun u_0 : string => + (undefined_unit tt) >>= fun u_1 : unit => + (internal_pick + [ISAException + (u_1);Error_not_implemented + (u_0);Error_misaligned_access + (u_1);Error_EBREAK + (u_1);Error_internal_error + (u_1)]) + : M (exception). + +Definition mips_sign_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} +: mword m__tv := + + sign_extend v m__tv. + +Definition mips_zero_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} +: mword m__tv := + + zero_extend v m__tv. + +Axiom sign_extend : forall {n : Z} {m : Z} (_ : mword n) `{ArithFact (m >= n)}, mword m. + +Axiom zero_extend : forall {n : Z} {m : Z} (_ : mword n) `{ArithFact (m >= n)}, mword m. + +Definition zeros_implicit (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} +: mword n__tv := + + zeros n__tv. +Arguments zeros_implicit _ _ {_}. + +Definition ones_n (n : Z) `{ArithFact (n >= 0)} +: mword n := + + autocast (replicate_bits (vec_of_bits [B1] : mword 1) n). + +Definition ones_implicit (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} +: mword n__tv := + + ones_n n__tv. +Arguments ones_implicit _ _ {_}. + +Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} +: bool := + + Z.ltb (projT1 (sint x)) (projT1 (sint y)). + +Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} +: bool := + + Z.geb (projT1 (sint x)) (projT1 (sint y)). + +Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} +: bool := + + Z.ltb (projT1 (uint x)) (projT1 (uint y)). + +Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} +: bool := + + Z.geb (projT1 (uint x)) (projT1 (uint y)). + +Definition bool_to_bits (x : bool) +: mword 1 := + + if (x) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bool_to_bit (x : bool) : bitU := if (x) then B1 else B0. + +Definition bit_to_bool (b : bitU) : bool := match b with | B1 => true | _ => false end. + +Definition bits_to_bool (x : mword 1) : bool := bit_to_bool (access_vec_dec x 0). + +Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} : mword l := get_slice_int l n 0. + +Definition mask {m : Z} (n__tv : Z) (bs : mword m) `{ArithFact (m >= n__tv /\ n__tv >= (0 + 1))} +: mword n__tv := + + autocast (subrange_vec_dec bs (Z.sub n__tv 1) 0). + +Definition undefined_CauseReg '(tt : unit) +: M (CauseReg) := + + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + returnm (({| CauseReg_CauseReg_chunk_0 := w__0 |}) + : CauseReg). + +Definition Mk_CauseReg (v : mword 32) +: CauseReg := + + {| CauseReg_CauseReg_chunk_0 := (subrange_vec_dec v 31 0) |}. + +Definition _get_CauseReg_bits (v : CauseReg) +: mword 32 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0. + +Definition _set_CauseReg_bits (r_ref : register_ref regstate register_value CauseReg) (v : mword 32) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_bits (v : CauseReg) (x : mword 32) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. + +Definition _get_CauseReg_BD (v : CauseReg) +: mword 1 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31. + +Definition _set_CauseReg_BD (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_BD (v : CauseReg) (x : mword 1) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_CauseReg_CE (v : CauseReg) +: mword 2 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28. + +Definition _set_CauseReg_CE (r_ref : register_ref regstate register_value CauseReg) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec v 1 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_CE (v : CauseReg) (x : mword 2) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_CauseReg_IV (v : CauseReg) +: mword 1 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23. + +Definition _set_CauseReg_IV (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec v 0 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_IV (v : CauseReg) (x : mword 1) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_CauseReg_WP (v : CauseReg) +: mword 1 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22. + +Definition _set_CauseReg_WP (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_WP (v : CauseReg) (x : mword 1) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_CauseReg_IP (v : CauseReg) +: mword 8 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8. + +Definition _set_CauseReg_IP (r_ref : register_ref regstate register_value CauseReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_IP (v : CauseReg) (x : mword 8) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_CauseReg_ExcCode (v : CauseReg) +: mword 5 := + + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2. + +Definition _set_CauseReg_ExcCode +(r_ref : register_ref regstate register_value CauseReg) (v : mword 5) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec r.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec v 4 0)) ]} + : CauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CauseReg_ExcCode (v : CauseReg) (x : mword 5) +: CauseReg := + + {[ v with + CauseReg_CauseReg_chunk_0 := + (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec x 4 0)) ]}. + +Definition undefined_TLBEntryLoReg '(tt : unit) +: M (TLBEntryLoReg) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + returnm (({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := w__0 |}) + : TLBEntryLoReg). + +Definition Mk_TLBEntryLoReg (v : mword 64) +: TLBEntryLoReg := + + {| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_TLBEntryLoReg_bits (v : TLBEntryLoReg) +: mword 64 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0. + +Definition _set_TLBEntryLoReg_bits +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0 + (subrange_vec_dec v 63 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_bits (v : TLBEntryLoReg) (x : mword 64) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0 + (subrange_vec_dec x 63 0)) ]}. + +Definition _get_TLBEntryLoReg_CapS (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63. + +Definition _set_TLBEntryLoReg_CapS +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_CapS (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63 + (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntryLoReg_CapL (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62. + +Definition _set_TLBEntryLoReg_CapL +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_CapL (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62 + (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntryLoReg_PFN (v : TLBEntryLoReg) +: mword 24 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6. + +Definition _set_TLBEntryLoReg_PFN +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 24) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6 + (subrange_vec_dec v 23 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_PFN (v : TLBEntryLoReg) (x : mword 24) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6 + (subrange_vec_dec x 23 0)) ]}. + +Definition _get_TLBEntryLoReg_C (v : TLBEntryLoReg) +: mword 3 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3. + +Definition _set_TLBEntryLoReg_C +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 3) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3 + (subrange_vec_dec v 2 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_C (v : TLBEntryLoReg) (x : mword 3) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3 (subrange_vec_dec x 2 0)) ]}. + +Definition _get_TLBEntryLoReg_D (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2. + +Definition _set_TLBEntryLoReg_D +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_D (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntryLoReg_V (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1. + +Definition _set_TLBEntryLoReg_V +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_V (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntryLoReg_G (v : TLBEntryLoReg) +: mword 1 := + + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0. + +Definition _set_TLBEntryLoReg_G +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0 + (subrange_vec_dec v 0 0)) ]} + : TLBEntryLoReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryLoReg_G (v : TLBEntryLoReg) (x : mword 1) +: TLBEntryLoReg := + + {[ v with + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition undefined_TLBEntryHiReg '(tt : unit) +: M (TLBEntryHiReg) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + returnm (({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := w__0 |}) + : TLBEntryHiReg). + +Definition Mk_TLBEntryHiReg (v : mword 64) +: TLBEntryHiReg := + + {| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_TLBEntryHiReg_bits (v : TLBEntryHiReg) +: mword 64 := + + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0. + +Definition _set_TLBEntryHiReg_bits +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0 + (subrange_vec_dec v 63 0)) ]} + : TLBEntryHiReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryHiReg_bits (v : TLBEntryHiReg) (x : mword 64) +: TLBEntryHiReg := + + {[ v with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0 + (subrange_vec_dec x 63 0)) ]}. + +Definition _get_TLBEntryHiReg_R (v : TLBEntryHiReg) +: mword 2 := + + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62. + +Definition _set_TLBEntryHiReg_R +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62 + (subrange_vec_dec v 1 0)) ]} + : TLBEntryHiReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryHiReg_R (v : TLBEntryHiReg) (x : mword 2) +: TLBEntryHiReg := + + {[ v with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62 + (subrange_vec_dec x 1 0)) ]}. + +Definition _get_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) +: mword 27 := + + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13. + +Definition _set_TLBEntryHiReg_VPN2 +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 27) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13 + (subrange_vec_dec v 26 0)) ]} + : TLBEntryHiReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) (x : mword 27) +: TLBEntryHiReg := + + {[ v with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13 + (subrange_vec_dec x 26 0)) ]}. + +Definition _get_TLBEntryHiReg_ASID (v : TLBEntryHiReg) +: mword 8 := + + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0. + +Definition _set_TLBEntryHiReg_ASID +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec r.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0 + (subrange_vec_dec v 7 0)) ]} + : TLBEntryHiReg in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntryHiReg_ASID (v : TLBEntryHiReg) (x : mword 8) +: TLBEntryHiReg := + + {[ v with + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. + +Definition undefined_ContextReg '(tt : unit) +: M (ContextReg) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + returnm (({| ContextReg_ContextReg_chunk_0 := w__0 |}) + : ContextReg). + +Definition Mk_ContextReg (v : mword 64) +: ContextReg := + + {| ContextReg_ContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_ContextReg_bits (v : ContextReg) +: mword 64 := + + subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0. + +Definition _set_ContextReg_bits +(r_ref : register_ref regstate register_value ContextReg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : ContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_ContextReg_bits (v : ContextReg) (x : mword 64) +: ContextReg := + + {[ v with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_ContextReg_PTEBase (v : ContextReg) +: mword 41 := + + subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23. + +Definition _set_ContextReg_PTEBase +(r_ref : register_ref regstate register_value ContextReg) (v : mword 41) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec v 40 0)) ]} + : ContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_ContextReg_PTEBase (v : ContextReg) (x : mword 41) +: ContextReg := + + {[ v with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec x 40 0)) ]}. + +Definition _get_ContextReg_BadVPN2 (v : ContextReg) +: mword 19 := + + subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4. + +Definition _set_ContextReg_BadVPN2 +(r_ref : register_ref regstate register_value ContextReg) (v : mword 19) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec r.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec v 18 0)) ]} + : ContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_ContextReg_BadVPN2 (v : ContextReg) (x : mword 19) +: ContextReg := + + {[ v with + ContextReg_ContextReg_chunk_0 := + (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec x 18 0)) ]}. + +Definition undefined_XContextReg '(tt : unit) +: M (XContextReg) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + returnm (({| XContextReg_XContextReg_chunk_0 := w__0 |}) + : XContextReg). + +Definition Mk_XContextReg (v : mword 64) +: XContextReg := + + {| XContextReg_XContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_XContextReg_bits (v : XContextReg) +: mword 64 := + + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0. + +Definition _set_XContextReg_bits +(r_ref : register_ref regstate register_value XContextReg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : XContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_XContextReg_bits (v : XContextReg) (x : mword 64) +: XContextReg := + + {[ v with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_XContextReg_XPTEBase (v : XContextReg) +: mword 31 := + + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33. + +Definition _set_XContextReg_XPTEBase +(r_ref : register_ref regstate register_value XContextReg) (v : mword 31) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 63 33 + (subrange_vec_dec v 30 0)) ]} + : XContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_XContextReg_XPTEBase (v : XContextReg) (x : mword 31) +: XContextReg := + + {[ v with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33 (subrange_vec_dec x 30 0)) ]}. + +Definition _get_XContextReg_XR (v : XContextReg) +: mword 2 := + + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31. + +Definition _set_XContextReg_XR +(r_ref : register_ref regstate register_value XContextReg) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec v 1 0)) ]} + : XContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_XContextReg_XR (v : XContextReg) (x : mword 2) +: XContextReg := + + {[ v with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_XContextReg_XBadVPN2 (v : XContextReg) +: mword 27 := + + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4. + +Definition _set_XContextReg_XBadVPN2 +(r_ref : register_ref regstate register_value XContextReg) (v : mword 27) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec r.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec v 26 0)) ]} + : XContextReg in + write_reg r_ref r + : M (unit). + +Definition _update_XContextReg_XBadVPN2 (v : XContextReg) (x : mword 27) +: XContextReg := + + {[ v with + XContextReg_XContextReg_chunk_0 := + (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec x 26 0)) ]}. + +Definition TLBNumEntries := 64. +Hint Unfold TLBNumEntries : sail. +Definition TLBIndexMax : TLBIndexT := (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword 6). +Hint Unfold TLBIndexMax : sail. +Definition MAX (n : Z) `{ArithFact (n >= 0)} +: {_retval : Z & ArithFact (_retval = (2 ^ n - 1))} := + + build_ex(Z.sub (projT1 (pow2 n)) 1). + +Definition MAX_U64 := projT1 (MAX 64). +Hint Unfold MAX_U64 : sail. +Definition MAX_VA := projT1 (MAX 40). +Hint Unfold MAX_VA : sail. +Definition MAX_PA := projT1 (MAX 36). +Hint Unfold MAX_PA : sail. +Definition undefined_TLBEntry '(tt : unit) +: M (TLBEntry) := + + (undefined_bitvector 53) >>= fun w__0 : mword 53 => + (undefined_bitvector 64) >>= fun w__1 : mword 64 => + returnm (({| TLBEntry_TLBEntry_chunk_1 := w__0; + TLBEntry_TLBEntry_chunk_0 := w__1 |}) + : TLBEntry). + +Definition Mk_TLBEntry (v : mword 117) +: TLBEntry := + + {| TLBEntry_TLBEntry_chunk_1 := (subrange_vec_dec v 116 64); + TLBEntry_TLBEntry_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_TLBEntry_bits (v : TLBEntry) +: mword 117 := + + concat_vec (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0) + (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0). + +Definition _set_TLBEntry_bits +(r_ref : register_ref regstate register_value TLBEntry) (v : mword 117) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 52 0 (subrange_vec_dec v 116 64)) ]} + : TLBEntry in + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_bits (v : TLBEntry) (x : mword 117) +: TLBEntry := + + let v := + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0 (subrange_vec_dec x 116 64)) ]} in + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_TLBEntry_pagemask (v : TLBEntry) +: mword 16 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37. + +Definition _set_TLBEntry_pagemask +(r_ref : register_ref regstate register_value TLBEntry) (v : mword 16) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec v 15 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_pagemask (v : TLBEntry) (x : mword 16) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec x 15 0)) ]}. + +Definition _get_TLBEntry_r (v : TLBEntry) +: mword 2 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35. + +Definition _set_TLBEntry_r (r_ref : register_ref regstate register_value TLBEntry) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec v 1 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_r (v : TLBEntry) (x : mword 2) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_TLBEntry_vpn2 (v : TLBEntry) +: mword 27 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8. + +Definition _set_TLBEntry_vpn2 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 27) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec v 26 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_vpn2 (v : TLBEntry) (x : mword 27) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec x 26 0)) ]}. + +Definition _get_TLBEntry_asid (v : TLBEntry) +: mword 8 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0. + +Definition _set_TLBEntry_asid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec v 7 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_asid (v : TLBEntry) (x : mword 8) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_1 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_TLBEntry_g (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63. + +Definition _set_TLBEntry_g (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_g (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_valid (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62. + +Definition _set_TLBEntry_valid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_valid (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_caps1 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61. + +Definition _set_TLBEntry_caps1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_caps1 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_capl1 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60. + +Definition _set_TLBEntry_capl1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_capl1 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_pfn1 (v : TLBEntry) +: mword 24 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36. + +Definition _set_TLBEntry_pfn1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec v 23 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_pfn1 (v : TLBEntry) (x : mword 24) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec x 23 0)) ]}. + +Definition _get_TLBEntry_c1 (v : TLBEntry) +: mword 3 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33. + +Definition _set_TLBEntry_c1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec v 2 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_c1 (v : TLBEntry) (x : mword 3) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec x 2 0)) ]}. + +Definition _get_TLBEntry_d1 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32. + +Definition _set_TLBEntry_d1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_d1 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_v1 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31. + +Definition _set_TLBEntry_v1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_v1 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_caps0 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30. + +Definition _set_TLBEntry_caps0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_caps0 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_capl0 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29. + +Definition _set_TLBEntry_capl0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_capl0 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_pfn0 (v : TLBEntry) +: mword 24 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5. + +Definition _set_TLBEntry_pfn0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec v 23 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_pfn0 (v : TLBEntry) (x : mword 24) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec x 23 0)) ]}. + +Definition _get_TLBEntry_c0 (v : TLBEntry) +: mword 3 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2. + +Definition _set_TLBEntry_c0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec v 2 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_c0 (v : TLBEntry) (x : mword 3) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec x 2 0)) ]}. + +Definition _get_TLBEntry_d0 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1. + +Definition _set_TLBEntry_d0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_d0 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_TLBEntry_v0 (v : TLBEntry) +: mword 1 := + + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0. + +Definition _set_TLBEntry_v0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec r.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : TLBEntry in + write_reg r_ref r + : M (unit). + +Definition _update_TLBEntry_v0 (v : TLBEntry) (x : mword 1) +: TLBEntry := + + {[ v with + TLBEntry_TLBEntry_chunk_0 := + (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition TLBEntries : vec (register_ref regstate register_value TLBEntry) 64 := +vec_of_list_len [TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLBEntry59_ref;TLBEntry58_ref;TLBEntry57_ref;TLBEntry56_ref;TLBEntry55_ref;TLBEntry54_ref;TLBEntry53_ref;TLBEntry52_ref;TLBEntry51_ref;TLBEntry50_ref;TLBEntry49_ref;TLBEntry48_ref;TLBEntry47_ref;TLBEntry46_ref;TLBEntry45_ref;TLBEntry44_ref;TLBEntry43_ref; + TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref;TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref;TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref;TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref; + TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref;TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref;TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref;TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref; + TLBEntry00_ref]. +Hint Unfold TLBEntries : sail. +Definition undefined_StatusReg '(tt : unit) +: M (StatusReg) := + + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + returnm (({| StatusReg_StatusReg_chunk_0 := w__0 |}) + : StatusReg). + +Definition Mk_StatusReg (v : mword 32) +: StatusReg := + + {| StatusReg_StatusReg_chunk_0 := (subrange_vec_dec v 31 0) |}. + +Definition _get_StatusReg_bits (v : StatusReg) +: mword 32 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0. + +Definition _set_StatusReg_bits +(r_ref : register_ref regstate register_value StatusReg) (v : mword 32) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_bits (v : StatusReg) (x : mword 32) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. + +Definition _get_StatusReg_CU (v : StatusReg) +: mword 4 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28. + +Definition _set_StatusReg_CU (r_ref : register_ref regstate register_value StatusReg) (v : mword 4) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec v 3 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_CU (v : StatusReg) (x : mword 4) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec x 3 0)) ]}. + +Definition _get_StatusReg_BEV (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22. + +Definition _set_StatusReg_BEV (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_BEV (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_IM (v : StatusReg) +: mword 8 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8. + +Definition _set_StatusReg_IM (r_ref : register_ref regstate register_value StatusReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_IM (v : StatusReg) (x : mword 8) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_StatusReg_KX (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7. + +Definition _set_StatusReg_KX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_KX (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_SX (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6. + +Definition _set_StatusReg_SX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_SX (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_UX (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5. + +Definition _set_StatusReg_UX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_UX (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_KSU (v : StatusReg) +: mword 2 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3. + +Definition _set_StatusReg_KSU (r_ref : register_ref regstate register_value StatusReg) (v : mword 2) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec v 1 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_KSU (v : StatusReg) (x : mword 2) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_StatusReg_ERL (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2. + +Definition _set_StatusReg_ERL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_ERL (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_EXL (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1. + +Definition _set_StatusReg_EXL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_EXL (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_StatusReg_IE (v : StatusReg) +: mword 1 := + + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0. + +Definition _set_StatusReg_IE (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec r.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : StatusReg in + write_reg r_ref r + : M (unit). + +Definition _update_StatusReg_IE (v : StatusReg) (x : mword 1) +: StatusReg := + + {[ v with + StatusReg_StatusReg_chunk_0 := + (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition execute_branch_mips (pc : mword 64) +: M (unit) := + + write_reg DelayedPC_ref pc >> + write_reg BranchPending_ref (vec_of_bits [B1] : mword 1) >> + write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) + : M (unit). + +Definition NotWordVal (word : mword 64) +: bool := + + neq_vec (zopz0zQzQ (cast_unit_vec (access_vec_dec word 31)) 32) (subrange_vec_dec word 63 32). + +Definition rGPR (idx : mword 5) +: M (mword 64) := + + let 'i := projT1 (uint idx) in + (if sumbool_of_bool ((Z.eqb i 0)) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else + read_reg GPR_ref >>= fun w__0 : vec (bits 64) 32 => + returnm ((vec_access_dec w__0 i) + : mword 64)) + : M (mword 64). + +Definition wGPR (idx : mword 5) (v : mword 64) +: M (unit) := + + let 'i := projT1 (uint idx) in + (if ((neq_int i 0)) then + let '_ := + (if (trace) then + let '_ := (prerr (string_of_int i)) : unit in + prerr_bits " <- " v + else tt) + : unit in + read_reg GPR_ref >>= fun w__0 : vec (bits 64) 32 => + write_reg GPR_ref (vec_update_dec w__0 i v) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition MEMr (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} +: M (mword (8 * size)) := + + (__MIPS_read addr size) + : M (mword (8 * size)). + +Definition MEMr_reserve (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} +: M (mword (8 * size)) := + + (__MIPS_read addr size) + : M (mword (8 * size)). + +Definition MEM_sync '(tt : unit) : M (unit) := (skip tt) : M (unit). + +Definition MEMea (addr : mword 64) (size : Z) : M (unit) := (skip tt) : M (unit). + +Definition MEMea_conditional (addr : mword 64) (size : Z) : M (unit) := (skip tt) : M (unit). + +Definition MEMval (addr : mword 64) (size : Z) (data : mword (8 * size)) +: M (unit) := + + (__MIPS_write addr size data) + : M (unit). + +Definition MEMval_conditional (addr : mword 64) (size : Z) (data : mword (8 * size)) +: M (bool) := + + (__MIPS_write addr size data) >> returnm (true : bool). + +Definition Exception_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 18)} +: Exception := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Interrupt + else if sumbool_of_bool ((Z.eqb p0_ 1)) then TLBMod + else if sumbool_of_bool ((Z.eqb p0_ 2)) then TLBL + else if sumbool_of_bool ((Z.eqb p0_ 3)) then TLBS + else if sumbool_of_bool ((Z.eqb p0_ 4)) then AdEL + else if sumbool_of_bool ((Z.eqb p0_ 5)) then AdES + else if sumbool_of_bool ((Z.eqb p0_ 6)) then Sys + else if sumbool_of_bool ((Z.eqb p0_ 7)) then Bp + else if sumbool_of_bool ((Z.eqb p0_ 8)) then ResI + else if sumbool_of_bool ((Z.eqb p0_ 9)) then CpU + else if sumbool_of_bool ((Z.eqb p0_ 10)) then Ov + else if sumbool_of_bool ((Z.eqb p0_ 11)) then Tr + else if sumbool_of_bool ((Z.eqb p0_ 12)) then C2E + else if sumbool_of_bool ((Z.eqb p0_ 13)) then C2Trap + else if sumbool_of_bool ((Z.eqb p0_ 14)) then XTLBRefillL + else if sumbool_of_bool ((Z.eqb p0_ 15)) then XTLBRefillS + else if sumbool_of_bool ((Z.eqb p0_ 16)) then XTLBInvL + else if sumbool_of_bool ((Z.eqb p0_ 17)) then XTLBInvS + else MCheck. + +Definition num_of_Exception (arg_ : Exception) +: {e : Z & ArithFact (0 <= e /\ e <= 18)} := + + build_ex(match arg_ with + | Interrupt => 0 + | TLBMod => 1 + | TLBL => 2 + | TLBS => 3 + | AdEL => 4 + | AdES => 5 + | Sys => 6 + | Bp => 7 + | ResI => 8 + | CpU => 9 + | Ov => 10 + | Tr => 11 + | C2E => 12 + | C2Trap => 13 + | XTLBRefillL => 14 + | XTLBRefillS => 15 + | XTLBInvL => 16 + | XTLBInvS => 17 + | MCheck => 18 + end). + +Definition undefined_Exception '(tt : unit) +: M (Exception) := + + (internal_pick + [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]) + : M (Exception). + +Definition ExceptionCode (ex : Exception) +: mword 5 := + + let x : bits 8 := + match ex with + | Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) + | TLBMod => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8) + | TLBL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) + | TLBS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) + | AdEL => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : mword 8) + | AdES => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : mword 8) + | Sys => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : mword 8) + | Bp => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : mword 8) + | ResI => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : mword 8) + | CpU => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1] : mword 8) + | Ov => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0] : mword 8) + | Tr => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1] : mword 8) + | C2E => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : mword 8) + | C2Trap => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : mword 8) + | XTLBRefillL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) + | XTLBRefillS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) + | XTLBInvL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) + | XTLBInvS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) + | MCheck => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : mword 8) + end in + subrange_vec_dec x 4 0. + +Definition string_of_exception (ex : Exception) +: string := + + match ex with + | Interrupt => "Interrupt" + | TLBMod => "TLBMod" + | TLBL => "TLBL" + | TLBS => "TLBS" + | AdEL => "AdEL" + | AdES => "AdES" + | Sys => "Sys" + | Bp => "Bp " + | ResI => "ResI" + | CpU => "CpU" + | Ov => "Ov" + | Tr => "Tr" + | C2E => "C2E" + | C2Trap => "C2Trap" + | XTLBRefillL => "XTLBRefillL" + | XTLBRefillS => "XTLBRefillS" + | XTLBInvL => "XTLBInvL" + | XTLBInvS => "XTLBInvS" + | MCheck => "MCheck" + end. + +Definition SignalExceptionMIPS {o : Type} (ex : Exception) (kccBase : mword 64) +: M (o) := + + let '_ := + (if (trace) then + let '_ := (prerr " EXCEPTION ") : unit in + prerr_endline (string_of_exception ex) + else tt) + : unit in + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + (if ((negb ((bits_to_bool (_get_StatusReg_EXL w__0)) : bool))) then + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__1 0)) : bool)) then + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + write_reg CP0EPC_ref (sub_vec_int w__2 4) >> + (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] : mword 1)) + : M (unit) + else + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : bits 64 => + write_reg CP0EPC_ref w__3 >> + (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] : mword 1)) + : M (unit)) + : M (unit) + else returnm (tt : unit)) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__4 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__4 0)) : bool)) then + ((read_reg LastInstrBits_ref) : M (mword 32)) >>= fun w__5 : bits 32 => + write_reg CP0BadInstrP_ref w__5 + : M (unit) + else returnm (tt : unit)) >> + ((read_reg CurrentInstrBits_ref) : M (mword 32)) >>= fun w__6 : bits 32 => + write_reg CP0BadInstr_ref w__6 >> + read_reg CP0Status_ref >>= fun w__7 : StatusReg => + let vectorOffset := + if (((bits_to_bool (_get_StatusReg_EXL w__7)) : bool)) then + (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((orb (generic_eq ex XTLBRefillL) (generic_eq ex XTLBRefillS))) then + (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq ex C2Trap)) then + (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) in + read_reg CP0Status_ref >>= fun w__8 : StatusReg => + let vectorBase : bits 64 := + if (((bits_to_bool (_get_StatusReg_BEV w__8)) : bool)) then + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + else + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) in + write_reg NextPC_ref (sub_vec (add_vec vectorBase (mips_sign_extend 64 vectorOffset)) kccBase) >> + (_set_CauseReg_ExcCode CP0Cause_ref (ExceptionCode ex)) >> + (_set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] : mword 1)) >> + (throw (ISAException + (tt))) + : M (o). + +Definition undefined_Capability '(tt : unit) +: M (Capability) := + + (undefined_bool tt) >>= fun w__0 : bool => + (undefined_bitvector 8) >>= fun w__1 : mword 8 => + (undefined_bitvector 24) >>= fun w__2 : mword 24 => + (undefined_bitvector 16) >>= fun w__3 : mword 16 => + (undefined_bitvector 3) >>= fun w__4 : mword 3 => + (undefined_bool tt) >>= fun w__5 : bool => + (undefined_bool tt) >>= fun w__6 : bool => + (undefined_bool tt) >>= fun w__7 : bool => + (undefined_bool tt) >>= fun w__8 : bool => + (undefined_bool tt) >>= fun w__9 : bool => + (undefined_bool tt) >>= fun w__10 : bool => + (undefined_bool tt) >>= fun w__11 : bool => + (undefined_bool tt) >>= fun w__12 : bool => + (undefined_bool tt) >>= fun w__13 : bool => + (undefined_bool tt) >>= fun w__14 : bool => + (undefined_bool tt) >>= fun w__15 : bool => + (undefined_bool tt) >>= fun w__16 : bool => + (undefined_bool tt) >>= fun w__17 : bool => + (undefined_bitvector 64) >>= fun w__18 : mword 64 => + (undefined_bitvector 64) >>= fun w__19 : mword 64 => + (undefined_bitvector 64) >>= fun w__20 : mword 64 => + returnm (({| Capability_tag := w__0; + Capability_padding := w__1; + Capability_otype := w__2; + Capability_uperms := w__3; + Capability_perm_reserved12_14 := w__4; + Capability_permit_set_CID := w__5; + Capability_access_system_regs := w__6; + Capability_permit_unseal := w__7; + Capability_permit_ccall := w__8; + Capability_permit_seal := w__9; + Capability_permit_store_local_cap := w__10; + Capability_permit_store_cap := w__11; + Capability_permit_load_cap := w__12; + Capability_permit_store := w__13; + Capability_permit_load := w__14; + Capability_permit_execute := w__15; + Capability_global := w__16; + Capability_sealed := w__17; + Capability_address := w__18; + Capability_base := w__19; + Capability_length := w__20 |}) + : Capability). + +Definition getCapBase (c : Capability) +: {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 64 - 1))} := + + build_ex(projT1 (uint c.(Capability_base))). + +Definition set_next_pcc (newPCC : Capability) +: M (unit) := + + write_reg NextPCC_ref newPCC >> write_reg DelayedPCC_ref newPCC : M (unit). + +Definition SignalException {o : Type} (ex : Exception) +: M (o) := + + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + (if ((negb ((bits_to_bool (_get_StatusReg_EXL w__0)) : bool))) then + read_reg PCC_ref >>= fun w__1 : Capability => write_reg EPCC_ref w__1 : M (unit) + else returnm (tt : unit)) >> + read_reg KCC_ref >>= fun w__2 : Capability => + (set_next_pcc w__2) >> + read_reg KCC_ref >>= fun w__3 : Capability => + let 'base := projT1 (getCapBase w__3) in + (SignalExceptionMIPS ex (to_bits 64 base)) + : M (o). + +Definition SignalExceptionBadAddr {o : Type} (ex : Exception) (badAddr : mword 64) +: M (o) := + + write_reg CP0BadVAddr_ref badAddr >> (SignalException ex) : M (o). + +Definition SignalExceptionTLB {o : Type} (ex : Exception) (badAddr : mword 64) +: M (o) := + + write_reg CP0BadVAddr_ref badAddr >> + (_set_ContextReg_BadVPN2 TLBContext_ref (subrange_vec_dec badAddr 31 13)) >> + (_set_XContextReg_XBadVPN2 TLBXContext_ref (subrange_vec_dec badAddr 39 13)) >> + (_set_XContextReg_XR TLBXContext_ref (subrange_vec_dec badAddr 63 62)) >> + (_set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec badAddr 63 62)) >> + (_set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec badAddr 39 13)) >> + (SignalException ex) + : M (o). + +Definition MemAccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: MemAccessType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Instruction + else if sumbool_of_bool ((Z.eqb p0_ 1)) then LoadData + else StoreData. + +Definition num_of_MemAccessType (arg_ : MemAccessType) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | Instruction => 0 | LoadData => 1 | StoreData => 2 end). + +Definition undefined_MemAccessType '(tt : unit) +: M (MemAccessType) := + + (internal_pick [Instruction;LoadData;StoreData]) + : M (MemAccessType). + +Definition AccessLevel_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: AccessLevel := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then User + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Supervisor + else Kernel. + +Definition num_of_AccessLevel (arg_ : AccessLevel) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | User => 0 | Supervisor => 1 | Kernel => 2 end). + +Definition undefined_AccessLevel '(tt : unit) +: M (AccessLevel) := + + (internal_pick [User;Supervisor;Kernel]) + : M (AccessLevel). + +Definition int_of_AccessLevel (level : AccessLevel) +: {n : Z & ArithFact (In n [0; 1; 2])} := + + build_ex(match level with | User => 0 | Supervisor => 1 | Kernel => 2 end). + +Definition grantsAccess (currentLevel : AccessLevel) (requiredLevel : AccessLevel) +: bool := + + Z.geb (projT1 (int_of_AccessLevel currentLevel)) (projT1 (int_of_AccessLevel requiredLevel)). + +Definition getAccessLevel '(tt : unit) +: M (AccessLevel) := + + (or_boolM + (read_reg CP0Status_ref >>= fun w__0 : StatusReg => + returnm ((bits_to_bool (_get_StatusReg_EXL w__0)) + : bool)) + (read_reg CP0Status_ref >>= fun w__1 : StatusReg => + returnm ((bits_to_bool (_get_StatusReg_ERL w__1)) + : bool))) >>= fun w__2 : bool => + (if (w__2) then returnm (Kernel : AccessLevel) + else + read_reg CP0Status_ref >>= fun w__3 : StatusReg => + let p__18 := _get_StatusReg_KSU w__3 in + let b__0 := p__18 in + returnm ((if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then Kernel + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Supervisor + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then User + else User) + : AccessLevel)) + : M (AccessLevel). + +Definition checkCP0Access '(tt : unit) +: M (unit) := + + (getAccessLevel tt) >>= fun accessLevel => + (and_boolM (returnm ((generic_neq accessLevel Kernel) : bool)) + (read_reg CP0Status_ref >>= fun w__0 : StatusReg => + returnm ((negb ((bit_to_bool (access_vec_dec (_get_StatusReg_CU w__0) 0)) : bool)) + : bool))) >>= fun w__1 : bool => + (if (w__1) then + (_set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0] : mword 2)) >> + (SignalException CpU) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition incrementCP0Count '(tt : unit) +: M (unit) := + + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + ((read_reg TLBWired_ref) : M (mword 6)) >>= fun w__1 : TLBIndexT => + (if ((eq_vec w__0 w__1)) then returnm (TLBIndexMax : TLBIndexT) + else + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__2 : TLBIndexT => + returnm ((sub_vec_int w__2 1) + : mword 6)) >>= fun w__3 : mword 6 => + write_reg TLBRandom_ref w__3 >> + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__4 : bits 32 => + write_reg CP0Count_ref (add_vec_int w__4 1) >> + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__5 : bits 32 => + ((read_reg CP0Compare_ref) : M (mword 32)) >>= fun w__6 : bits 32 => + (if ((eq_vec w__5 w__6)) then + read_reg CP0Cause_ref >>= fun w__7 : CauseReg => + (_set_CauseReg_IP CP0Cause_ref + (or_vec (_get_CauseReg_IP w__7) (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0] : mword 8))) + : M (unit) + else returnm (tt : unit)) >> + read_reg CP0Status_ref >>= fun w__8 : StatusReg => + let ims := _get_StatusReg_IM w__8 in + read_reg CP0Cause_ref >>= fun w__9 : CauseReg => + let ips := _get_CauseReg_IP w__9 in + read_reg CP0Status_ref >>= fun w__10 : StatusReg => + let ie := _get_StatusReg_IE w__10 in + read_reg CP0Status_ref >>= fun w__11 : StatusReg => + let exl := _get_StatusReg_EXL w__11 in + read_reg CP0Status_ref >>= fun w__12 : StatusReg => + let erl := _get_StatusReg_ERL w__12 in + (if ((andb (negb ((bits_to_bool exl) : bool)) + (andb (negb ((bits_to_bool erl) : bool)) + (andb ((bits_to_bool ie) : bool) + (neq_vec (and_vec ips ims) (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)))))) + then + (SignalException Interrupt) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition decode_failure_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: decode_failure := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then no_matching_pattern + else if sumbool_of_bool ((Z.eqb p0_ 1)) then unsupported_instruction + else if sumbool_of_bool ((Z.eqb p0_ 2)) then illegal_instruction + else internal_error. + +Definition num_of_decode_failure (arg_ : decode_failure) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with + | no_matching_pattern => 0 + | unsupported_instruction => 1 + | illegal_instruction => 2 + | internal_error => 3 + end). + +Definition undefined_decode_failure '(tt : unit) +: M (decode_failure) := + + (internal_pick [no_matching_pattern;unsupported_instruction;illegal_instruction;internal_error]) + : M (decode_failure). + +Definition Comparison_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 7)} +: Comparison := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then EQ' + else if sumbool_of_bool ((Z.eqb p0_ 1)) then NE + else if sumbool_of_bool ((Z.eqb p0_ 2)) then GE + else if sumbool_of_bool ((Z.eqb p0_ 3)) then GEU + else if sumbool_of_bool ((Z.eqb p0_ 4)) then GT' + else if sumbool_of_bool ((Z.eqb p0_ 5)) then LE + else if sumbool_of_bool ((Z.eqb p0_ 6)) then LT' + else LTU. + +Definition num_of_Comparison (arg_ : Comparison) +: {e : Z & ArithFact (0 <= e /\ e <= 7)} := + + build_ex(match arg_ with + | EQ' => 0 + | NE => 1 + | GE => 2 + | GEU => 3 + | GT' => 4 + | LE => 5 + | LT' => 6 + | LTU => 7 + end). + +Definition undefined_Comparison '(tt : unit) +: M (Comparison) := + + (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU]) + : M (Comparison). + +Definition compare (cmp : Comparison) (valA : mword 64) (valB : mword 64) +: bool := + + match cmp with + | EQ' => eq_vec valA valB + | NE => neq_vec valA valB + | GE => zopz0zKzJ_s valA valB + | GEU => zopz0zKzJ_u valA valB + | GT' => zopz0zI_s valB valA + | LE => zopz0zKzJ_s valB valA + | LT' => zopz0zI_s valA valB + | LTU => zopz0zI_u valA valB + end. + +Definition WordType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: WordType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then B + else if sumbool_of_bool ((Z.eqb p0_ 1)) then H + else if sumbool_of_bool ((Z.eqb p0_ 2)) then W + else D. + +Definition num_of_WordType (arg_ : WordType) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | B => 0 | H => 1 | W => 2 | D => 3 end). + +Definition undefined_WordType '(tt : unit) +: M (WordType) := + + (internal_pick [B;H;W;D]) + : M (WordType). + +Definition WordTypeUnaligned_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: WordTypeUnaligned := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then WL + else if sumbool_of_bool ((Z.eqb p0_ 1)) then WR + else if sumbool_of_bool ((Z.eqb p0_ 2)) then DL + else DR. + +Definition num_of_WordTypeUnaligned (arg_ : WordTypeUnaligned) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | WL => 0 | WR => 1 | DL => 2 | DR => 3 end). + +Definition undefined_WordTypeUnaligned '(tt : unit) +: M (WordTypeUnaligned) := + + (internal_pick [WL;WR;DL;DR]) + : M (WordTypeUnaligned). + +Definition wordWidthBytes (w : WordType) +: {rangevar : Z & ArithFact (1 <= rangevar /\ rangevar <= 8)} := + + build_ex(match w with | B => 1 | H => 2 | W => 4 | D => 8 end). + +Definition alignment_width := 16. +Hint Unfold alignment_width : sail. +Definition isAddressAligned (addr : mword 64) (wordType : WordType) +: bool := + + let 'a := projT1 (uint addr) in + Z.eqb (projT1 (ediv_with_eq a alignment_width)) + (projT1 (ediv_with_eq (Z.sub (Z.add a (projT1 (wordWidthBytes wordType))) 1) alignment_width)). + +Definition extendLoad {sz : Z} (memResult : mword sz) (sign : bool) `{ArithFact (sz <= 64)} +: mword 64 := + + if (sign) then mips_sign_extend 64 memResult + else mips_zero_extend 64 memResult. + +Definition MEMr_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} +: M (mword (8 * size)) := + + (if ((eq_vec addr + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + ((read_reg UART_RVALID_ref) : M (mword 1)) >>= fun rvalid => + write_reg UART_RVALID_ref (vec_of_bits [B0] : mword 1) >> + ((read_reg UART_RDATA_ref) : M (mword 8)) >>= fun w__0 : bits 8 => + returnm ((mask (Z.mul 8 size) + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) + (concat_vec w__0 + (concat_vec rvalid + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 16)))))) + : mword (8 * size)) + else if ((eq_vec addr + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0; + B0] + : mword 64))) then + returnm ((mask (Z.mul 8 size) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : mword 64)) + : mword (8 * size)) + else + (MEMr addr size) >>= fun w__1 : mword (8 * size) => + returnm ((reverse_endianness w__1) + : mword (8 * size))) + : M (mword (8 * size)). + +Definition MEMr_reserve_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} +: M (mword (8 * size)) := + + (MEMr_reserve addr size) >>= fun w__0 : mword (8 * size) => + returnm ((reverse_endianness w__0) + : mword (8 * size)). + +Definition init_cp0_state '(tt : unit) +: M (unit) := + + (_set_StatusReg_BEV CP0Status_ref ((cast_unit_vec B1) : mword 1)) + : M (unit). + +Definition tlbEntryMatch (r : mword 2) (vpn2 : mword 27) (asid : mword 8) (entry : TLBEntry) +: bool := + + let entryValid := _get_TLBEntry_valid entry in + let entryR := _get_TLBEntry_r entry in + let entryMask := _get_TLBEntry_pagemask entry in + let entryVPN := _get_TLBEntry_vpn2 entry in + let entryASID := _get_TLBEntry_asid entry in + let entryG := _get_TLBEntry_g entry in + let vpnMask : bits 27 := not_vec (mips_zero_extend 27 entryMask) in + andb ((bits_to_bool entryValid) : bool) + (andb (eq_vec r entryR) + (andb (eq_vec (and_vec vpn2 vpnMask) (and_vec entryVPN vpnMask)) + (orb (eq_vec asid entryASID) ((bits_to_bool entryG) : bool)))). + +Definition tlbSearch (VAddr : mword 64) +: M (option (mword 6)) := + + catch_early_return + (let r := subrange_vec_dec VAddr 63 62 in + let vpn2 := subrange_vec_dec VAddr 39 13 in + liftR (read_reg TLBEntryHi_ref) >>= fun w__0 : TLBEntryHiReg => + let asid := _get_TLBEntryHiReg_ASID w__0 in + (foreach_ZM_up 0 63 1 tt + (fun idx _ unit_var => + liftR ((reg_deref (vec_access_dec TLBEntries idx))) >>= fun w__1 : TLBEntry => + (if ((tlbEntryMatch r vpn2 asid w__1)) then + (early_return ((Some + (to_bits 6 idx)) + : option (mword 6))) + : MR (unit) _ + else returnm (tt : unit)) + : MR (unit) _)) >> + returnm (None + : option (mword 6))). + +Definition TLBTranslate2 (vAddr : mword 64) (accessType : MemAccessType) +: M ((mword 64 * bool)) := + + (tlbSearch vAddr) >>= fun idx => + (match idx with + | Some (idx) => + let 'i := projT1 (uint idx) in + (reg_deref (vec_access_dec TLBEntries i)) >>= fun entry => + let entryMask := _get_TLBEntry_pagemask entry in + let b__0 := entryMask in + (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16))) + then + returnm (build_ex (12 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 16))) + then + returnm (build_ex (14 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (16 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (18 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (20 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (22 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (24 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (26 + : Z)) + else if ((eq_vec b__0 + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) + then + returnm (build_ex (28 + : Z)) + else + (undefined_range 12 28) + : M ({rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})) >>= fun '(existT _ evenOddBit _ : {rangevar : Z & ArithFact (12 <= + rangevar /\ + rangevar <= 28)}) => + let isOdd := access_vec_dec vAddr evenOddBit in + let '(caps, capl, pfn, d, v) := + if (((bit_to_bool isOdd) : bool)) then + (_get_TLBEntry_caps1 entry, _get_TLBEntry_capl1 entry, _get_TLBEntry_pfn1 entry, _get_TLBEntry_d1 + entry, _get_TLBEntry_v1 + entry) + else + (_get_TLBEntry_caps0 entry, _get_TLBEntry_capl0 entry, _get_TLBEntry_pfn0 entry, _get_TLBEntry_d0 + entry, _get_TLBEntry_v0 + entry) in + (if ((negb ((bits_to_bool v) : bool))) then + (SignalExceptionTLB (if ((generic_eq accessType StoreData)) then XTLBInvS else XTLBInvL) + vAddr) + : M ((mword 64 * bool)) + else if ((andb (generic_eq accessType StoreData) (negb ((bits_to_bool d) : bool)))) then + (SignalExceptionTLB TLBMod vAddr) + : M ((mword 64 * bool)) + else + let res : bits 64 := + mips_zero_extend 64 + (concat_vec (subrange_vec_dec pfn 23 (Z.sub evenOddBit 12)) + (subrange_vec_dec vAddr (Z.sub evenOddBit 1) 0)) in + returnm (res, bits_to_bool (if ((generic_eq accessType StoreData)) then caps else capl))) + : M ((mword 64 * bool)) + | None => + (SignalExceptionTLB + (if ((generic_eq accessType StoreData)) then XTLBRefillS + else XTLBRefillL) vAddr) + : M ((mword 64 * bool)) + end) + : M ((mword 64 * bool)). + +Definition TLBTranslateC (vAddr : mword 64) (accessType : MemAccessType) +: M ((mword 64 * bool)) := + + (getAccessLevel tt) >>= fun currentAccessLevel => + let compat32 := + eq_vec (subrange_vec_dec vAddr 61 31) + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (61 - 31 + 1)) in + let b__0 := subrange_vec_dec vAddr 63 62 in + let '(requiredLevel, addr) := + (if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword (63 - 62 + 1)))) then + match (compat32, subrange_vec_dec vAddr 30 29) with + | (true, b__1) => + if ((eq_vec b__1 (vec_of_bits [B1;B1] : mword (30 - 29 + 1)))) then + (Kernel, None + : option (bits 64)) + else if ((eq_vec b__1 (vec_of_bits [B1;B0] : mword (30 - 29 + 1)))) then + (Supervisor, None + : option (bits 64)) + else if ((eq_vec b__1 (vec_of_bits [B0;B1] : mword (30 - 29 + 1)))) then + (Kernel, Some + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (subrange_vec_dec vAddr 28 0)))) + else if ((eq_vec b__1 (vec_of_bits [B0;B0] : mword (30 - 29 + 1)))) then + (Kernel, Some + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (subrange_vec_dec vAddr 28 0)))) + else match (true, b__1) with | (g__16, g__17) => (Kernel, None : option (bits 64)) end + | (g__16, g__17) => (Kernel, None : option (bits 64)) + end + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword (63 - 62 + 1)))) then + (Kernel, Some + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (subrange_vec_dec vAddr 58 0))) + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword (63 - 62 + 1)))) then + (Supervisor, None + : option (bits 64)) + else (User, None : option (bits 64))) + : (AccessLevel * option (bits 64)) in + (if ((negb (grantsAccess currentAccessLevel requiredLevel))) then + (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr) + : M ((mword 64 * bool)) + else + (match addr with + | Some (a) => returnm (a, false) + | None => + (if sumbool_of_bool ((andb (negb compat32) + (Z.gtb (projT1 (uint (subrange_vec_dec vAddr 61 0))) MAX_VA))) + then + (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) + vAddr) + : M ((mword 64 * bool)) + else (TLBTranslate2 vAddr accessType) : M ((mword 64 * bool))) + : M ((mword 64 * bool)) + end) >>= fun '(pa, c) => + (if sumbool_of_bool ((Z.gtb (projT1 (uint pa)) MAX_PA)) then + (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr) + : M ((mword 64 * bool)) + else returnm (pa, c)) + : M ((mword 64 * bool))) + : M ((mword 64 * bool)). + +Definition TLBTranslate (vAddr : mword 64) (accessType : MemAccessType) +: M (mword 64) := + + (TLBTranslateC vAddr accessType) >>= fun '(addr, c) => returnm (addr : mword 64). + +Definition CPtrCmpOp_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 7)} +: CPtrCmpOp := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then CEQ + else if sumbool_of_bool ((Z.eqb p0_ 1)) then CNE + else if sumbool_of_bool ((Z.eqb p0_ 2)) then CLT + else if sumbool_of_bool ((Z.eqb p0_ 3)) then CLE + else if sumbool_of_bool ((Z.eqb p0_ 4)) then CLTU + else if sumbool_of_bool ((Z.eqb p0_ 5)) then CLEU + else if sumbool_of_bool ((Z.eqb p0_ 6)) then CEXEQ + else CNEXEQ. + +Definition num_of_CPtrCmpOp (arg_ : CPtrCmpOp) +: {e : Z & ArithFact (0 <= e /\ e <= 7)} := + + build_ex(match arg_ with + | CEQ => 0 + | CNE => 1 + | CLT => 2 + | CLE => 3 + | CLTU => 4 + | CLEU => 5 + | CEXEQ => 6 + | CNEXEQ => 7 + end). + +Definition undefined_CPtrCmpOp '(tt : unit) +: M (CPtrCmpOp) := + + (internal_pick [CEQ;CNE;CLT;CLE;CLTU;CLEU;CEXEQ;CNEXEQ]) + : M (CPtrCmpOp). + +Definition ClearRegSet_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: ClearRegSet := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then GPLo + else if sumbool_of_bool ((Z.eqb p0_ 1)) then GPHi + else if sumbool_of_bool ((Z.eqb p0_ 2)) then CLo + else CHi. + +Definition num_of_ClearRegSet (arg_ : ClearRegSet) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | GPLo => 0 | GPHi => 1 | CLo => 2 | CHi => 3 end). + +Definition undefined_ClearRegSet '(tt : unit) +: M (ClearRegSet) := + + (internal_pick [GPLo;GPHi;CLo;CHi]) + : M (ClearRegSet). + +Definition max_otype := projT1 (MAX 24). +Hint Unfold max_otype : sail. +Definition null_cap : Capability := +{| Capability_tag := false; + Capability_padding := (zeros_implicit 8 tt); + Capability_otype := (zeros_implicit 24 tt); + Capability_uperms := (zeros_implicit 16 tt); + Capability_perm_reserved12_14 := (zeros_implicit 3 tt); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := (zeros_implicit 64 tt); + Capability_base := (zeros_implicit 64 tt); + Capability_length := + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : mword 64) |}. +Hint Unfold null_cap : sail. +Definition default_cap : Capability := +{| Capability_tag := true; + Capability_padding := (zeros_implicit 8 tt); + Capability_otype := (zeros_implicit 24 tt); + Capability_uperms := (ones_implicit 16 tt); + Capability_perm_reserved12_14 := (zeros_implicit 3 tt); + Capability_permit_set_CID := true; + Capability_access_system_regs := true; + Capability_permit_unseal := true; + Capability_permit_ccall := true; + Capability_permit_seal := true; + Capability_permit_store_local_cap := true; + Capability_permit_store_cap := true; + Capability_permit_load_cap := true; + Capability_permit_store := true; + Capability_permit_load := true; + Capability_permit_execute := true; + Capability_global := true; + Capability_sealed := false; + Capability_address := (zeros_implicit 64 tt); + Capability_base := (zeros_implicit 64 tt); + Capability_length := + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : mword 64) |}. +Hint Unfold default_cap : sail. +Definition capBitsToCapability (tag : bool) (capBits : mword 256) +: Capability := + + {| Capability_tag := tag; + Capability_padding := (subrange_vec_dec capBits 255 248); + Capability_otype := (subrange_vec_dec capBits 247 224); + Capability_uperms := (subrange_vec_dec capBits 223 208); + Capability_perm_reserved12_14 := (subrange_vec_dec capBits 207 205); + Capability_permit_set_CID := ((bit_to_bool (access_vec_dec capBits 204)) : bool); + Capability_access_system_regs := ((bit_to_bool (access_vec_dec capBits 203)) : bool); + Capability_permit_unseal := ((bit_to_bool (access_vec_dec capBits 202)) : bool); + Capability_permit_ccall := ((bit_to_bool (access_vec_dec capBits 201)) : bool); + Capability_permit_seal := ((bit_to_bool (access_vec_dec capBits 200)) : bool); + Capability_permit_store_local_cap := ((bit_to_bool (access_vec_dec capBits 199)) : bool); + Capability_permit_store_cap := ((bit_to_bool (access_vec_dec capBits 198)) : bool); + Capability_permit_load_cap := ((bit_to_bool (access_vec_dec capBits 197)) : bool); + Capability_permit_store := ((bit_to_bool (access_vec_dec capBits 196)) : bool); + Capability_permit_load := ((bit_to_bool (access_vec_dec capBits 195)) : bool); + Capability_permit_execute := ((bit_to_bool (access_vec_dec capBits 194)) : bool); + Capability_global := ((bit_to_bool (access_vec_dec capBits 193)) : bool); + Capability_sealed := ((bit_to_bool (access_vec_dec capBits 192)) : bool); + Capability_address := (subrange_vec_dec capBits 191 128); + Capability_base := (subrange_vec_dec capBits 127 64); + Capability_length := (subrange_vec_dec capBits 63 0) |}. + +Definition getCapPerms (cap : Capability) +: mword 31 := + + concat_vec cap.(Capability_uperms) + (concat_vec cap.(Capability_perm_reserved12_14) + (concat_vec (bool_to_bits cap.(Capability_permit_set_CID)) + (concat_vec (bool_to_bits cap.(Capability_access_system_regs)) + (concat_vec (bool_to_bits cap.(Capability_permit_unseal)) + (concat_vec (bool_to_bits cap.(Capability_permit_ccall)) + (concat_vec (bool_to_bits cap.(Capability_permit_seal)) + (concat_vec (bool_to_bits cap.(Capability_permit_store_local_cap)) + (concat_vec (bool_to_bits cap.(Capability_permit_store_cap)) + (concat_vec (bool_to_bits cap.(Capability_permit_load_cap)) + (concat_vec (bool_to_bits cap.(Capability_permit_store)) + (concat_vec (bool_to_bits cap.(Capability_permit_load)) + (concat_vec (bool_to_bits cap.(Capability_permit_execute)) + (bool_to_bits cap.(Capability_global)))))))))))))). + +Definition capToBits (cap : Capability) +: mword 256 := + + concat_vec cap.(Capability_padding) + (concat_vec cap.(Capability_otype) + (concat_vec (getCapPerms cap) + (concat_vec (bool_to_bits cap.(Capability_sealed)) + (concat_vec cap.(Capability_address) + (concat_vec cap.(Capability_base) cap.(Capability_length)))))). + +Definition null_cap_bits : CapBits := capToBits null_cap. +Hint Unfold null_cap_bits : sail. +Definition capToMemBits (cap : Capability) : mword 256 := xor_vec (capToBits cap) null_cap_bits. + +Definition memBitsToCapability (tag : bool) (b : mword 256) +: Capability := + + capBitsToCapability tag (xor_vec b null_cap_bits). + +Definition setCapPerms (cap : Capability) (perms : mword 31) +: Capability := + + {| Capability_tag := cap.(Capability_tag); + Capability_padding := cap.(Capability_padding); + Capability_otype := cap.(Capability_otype); + Capability_uperms := (subrange_vec_dec perms 30 15); + Capability_perm_reserved12_14 := cap.(Capability_perm_reserved12_14); + Capability_permit_set_CID := ((bit_to_bool (access_vec_dec perms 11)) : bool); + Capability_access_system_regs := ((bit_to_bool (access_vec_dec perms 10)) : bool); + Capability_permit_unseal := ((bit_to_bool (access_vec_dec perms 9)) : bool); + Capability_permit_ccall := ((bit_to_bool (access_vec_dec perms 8)) : bool); + Capability_permit_seal := ((bit_to_bool (access_vec_dec perms 7)) : bool); + Capability_permit_store_local_cap := ((bit_to_bool (access_vec_dec perms 6)) : bool); + Capability_permit_store_cap := ((bit_to_bool (access_vec_dec perms 5)) : bool); + Capability_permit_load_cap := ((bit_to_bool (access_vec_dec perms 4)) : bool); + Capability_permit_store := ((bit_to_bool (access_vec_dec perms 3)) : bool); + Capability_permit_load := ((bit_to_bool (access_vec_dec perms 2)) : bool); + Capability_permit_execute := ((bit_to_bool (access_vec_dec perms 1)) : bool); + Capability_global := ((bit_to_bool (access_vec_dec perms 0)) : bool); + Capability_sealed := cap.(Capability_sealed); + Capability_address := cap.(Capability_address); + Capability_base := cap.(Capability_base); + Capability_length := cap.(Capability_length) |}. + +Definition sealCap (cap : Capability) (otype : mword 24) +: (bool * Capability) := + + (true, {| Capability_tag := cap.(Capability_tag); + Capability_padding := cap.(Capability_padding); + Capability_otype := otype; + Capability_uperms := cap.(Capability_uperms); + Capability_perm_reserved12_14 := cap.(Capability_perm_reserved12_14); + Capability_permit_set_CID := cap.(Capability_permit_set_CID); + Capability_access_system_regs := cap.(Capability_access_system_regs); + Capability_permit_unseal := cap.(Capability_permit_unseal); + Capability_permit_ccall := cap.(Capability_permit_ccall); + Capability_permit_seal := cap.(Capability_permit_seal); + Capability_permit_store_local_cap := cap.(Capability_permit_store_local_cap); + Capability_permit_store_cap := cap.(Capability_permit_store_cap); + Capability_permit_load_cap := cap.(Capability_permit_load_cap); + Capability_permit_store := cap.(Capability_permit_store); + Capability_permit_load := cap.(Capability_permit_load); + Capability_permit_execute := cap.(Capability_permit_execute); + Capability_global := cap.(Capability_global); + Capability_sealed := true; + Capability_address := cap.(Capability_address); + Capability_base := cap.(Capability_base); + Capability_length := cap.(Capability_length) |}). + +Definition getCapTop (c : Capability) +: {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 65))} := + + build_ex(Z.add (projT1 (uint c.(Capability_base))) (projT1 (uint c.(Capability_length)))). + +Definition getCapBounds (c : Capability) +: +({rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 64 - 1))} * {rangevar : Z & ArithFact (0 <= + rangevar /\ + rangevar <= (2 ^ 65))}) := + + (build_ex (projT1 (getCapBase c)), build_ex (projT1 (getCapTop c))). + +Definition getCapOffset (c : Capability) +: {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 64 - 1))} := + + build_ex(projT1 (emod_with_eq + (Z.sub (projT1 (uint c.(Capability_address))) + (projT1 (uint c.(Capability_base)))) (projT1 (pow2 64)))). + +Definition getCapLength (c : Capability) +: {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 65))} := + + build_ex(projT1 (uint c.(Capability_length))). + +Definition getCapCursor (c : Capability) +: {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 64 - 1))} := + + build_ex(projT1 (uint c.(Capability_address))). + +Definition setCapOffset (c : Capability) (offset : mword 64) +: (bool * Capability) := + + (true, {[ c with Capability_address := (add_vec c.(Capability_base) offset) ]}). + +Definition incCapOffset (c : Capability) (delta : mword 64) +: (bool * Capability) := + + let newAddr : bits 64 := add_vec c.(Capability_address) delta in + (true, {[ c with Capability_address := newAddr ]}). + +Definition setCapBounds (cap : Capability) (base : mword 64) (top : mword 65) +: (bool * Capability) := + + let length : bits 65 := sub_vec top (concat_vec (vec_of_bits [B0] : mword 1) base) in + (true, {| Capability_tag := cap.(Capability_tag); + Capability_padding := cap.(Capability_padding); + Capability_otype := cap.(Capability_otype); + Capability_uperms := cap.(Capability_uperms); + Capability_perm_reserved12_14 := cap.(Capability_perm_reserved12_14); + Capability_permit_set_CID := cap.(Capability_permit_set_CID); + Capability_access_system_regs := cap.(Capability_access_system_regs); + Capability_permit_unseal := cap.(Capability_permit_unseal); + Capability_permit_ccall := cap.(Capability_permit_ccall); + Capability_permit_seal := cap.(Capability_permit_seal); + Capability_permit_store_local_cap := cap.(Capability_permit_store_local_cap); + Capability_permit_store_cap := cap.(Capability_permit_store_cap); + Capability_permit_load_cap := cap.(Capability_permit_load_cap); + Capability_permit_store := cap.(Capability_permit_store); + Capability_permit_load := cap.(Capability_permit_load); + Capability_permit_execute := cap.(Capability_permit_execute); + Capability_global := cap.(Capability_global); + Capability_sealed := cap.(Capability_sealed); + Capability_address := base; + Capability_base := base; + Capability_length := (subrange_vec_dec length 63 0) |}). + +Definition int_to_cap (address : mword 64) +: Capability := + + {[ null_cap with Capability_address := address ]}. + +Definition CapRegs : vec (register_ref regstate register_value Capability) 32 := +vec_of_list_len [C31_ref;C30_ref;C29_ref;C28_ref;C27_ref;C26_ref;C25_ref;C24_ref;C23_ref;C22_ref;C21_ref;C20_ref;C19_ref;C18_ref;C17_ref;C16_ref;C15_ref;C14_ref;C13_ref;C12_ref;C11_ref; + C10_ref;C09_ref;C08_ref;C07_ref;C06_ref;C05_ref;C04_ref;C03_ref;C02_ref;C01_ref;DDC_ref]. +Hint Unfold CapRegs : sail. +Definition have_cp2 := true. +Hint Unfold have_cp2 : sail. +Definition readCapReg (n : mword 5) +: M (Capability) := + + (if ((eq_vec n (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then returnm (null_cap : Capability) + else + let 'i := projT1 (uint n) in + (reg_deref (vec_access_dec CapRegs i)) + : M (Capability)) + : M (Capability). + +Definition readCapRegDDC (n : mword 5) +: M (Capability) := + + let 'i := projT1 (uint n) in + (reg_deref (vec_access_dec CapRegs i)) + : M (Capability). + +Definition capToString (cap : Capability) (fixlen : bool) +: M (string) := + + (skip tt) >> + let 'len := projT1 (getCapLength cap) in + let len_str := + if (fixlen) then string_of_bits (to_bits 64 (projT1 (min_atom len (projT1 (MAX 64))))) + else string_of_bits (to_bits 68 len) in + let otype24 : bits 24 := + if sumbool_of_bool ((Z.eqb (projT1 (sint cap.(Capability_otype))) (-1))) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24) + else mips_zero_extend 24 cap.(Capability_otype) in + returnm ((String.append " t:" + (String.append (if (cap.(Capability_tag)) then "1" else "0") + (String.append " s:" + (String.append (if (cap.(Capability_sealed)) then "1" else "0") + (String.append " perms:" + (String.append + (string_of_bits + (concat_vec (vec_of_bits [B0] : mword 1) (getCapPerms cap))) + (String.append " type:" + (String.append (string_of_bits otype24) + (String.append " offset:" + (String.append + (string_of_bits (to_bits 64 (projT1 (getCapOffset cap)))) + (String.append " base:" + (String.append + (string_of_bits + (to_bits 64 (projT1 (getCapBase cap)))) + (String.append " length:" len_str))))))))))))) + : string). + +Definition writeCapReg (n : mword 5) (cap : Capability) +: M (unit) := + + (if ((eq_vec n (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then returnm (tt : unit) + else + let 'i := projT1 (uint n) in + (if (trace) then + let '_ := (prerr (string_of_int i)) : unit in + let '_ := (prerr " <- ") : unit in + (capToString cap false) >>= fun w__0 : string => + let '_ := (prerr_endline w__0) : unit in + let cap2 := capBitsToCapability cap.(Capability_tag) (capToBits cap) in + (if ((generic_neq cap cap2)) then + let '_ := (prerr_endline "Wrote non-normal cap:") : unit in + (capToString cap false) >>= fun w__1 : string => + let '_ := (prerr_endline w__1) : unit in + (capToString cap2 false) >>= fun w__2 : string => + let '_ := (prerr_endline w__2) : unit in + (assert_exp false "wrote non-normal capability") + : M (unit) + else returnm (tt : unit)) + : M (unit) + else (skip tt) : M (unit)) >> + write_reg (vec_access_dec CapRegs i) cap + : M (unit)) + : M (unit). + +Definition CapEx_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 23)} +: CapEx := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then CapEx_None + else if sumbool_of_bool ((Z.eqb p0_ 1)) then CapEx_LengthViolation + else if sumbool_of_bool ((Z.eqb p0_ 2)) then CapEx_TagViolation + else if sumbool_of_bool ((Z.eqb p0_ 3)) then CapEx_SealViolation + else if sumbool_of_bool ((Z.eqb p0_ 4)) then CapEx_TypeViolation + else if sumbool_of_bool ((Z.eqb p0_ 5)) then CapEx_CallTrap + else if sumbool_of_bool ((Z.eqb p0_ 6)) then CapEx_ReturnTrap + else if sumbool_of_bool ((Z.eqb p0_ 7)) then CapEx_TSSUnderFlow + else if sumbool_of_bool ((Z.eqb p0_ 8)) then CapEx_UserDefViolation + else if sumbool_of_bool ((Z.eqb p0_ 9)) then CapEx_TLBNoStoreCap + else if sumbool_of_bool ((Z.eqb p0_ 10)) then CapEx_InexactBounds + else if sumbool_of_bool ((Z.eqb p0_ 11)) then CapEx_GlobalViolation + else if sumbool_of_bool ((Z.eqb p0_ 12)) then CapEx_PermitExecuteViolation + else if sumbool_of_bool ((Z.eqb p0_ 13)) then CapEx_PermitLoadViolation + else if sumbool_of_bool ((Z.eqb p0_ 14)) then CapEx_PermitStoreViolation + else if sumbool_of_bool ((Z.eqb p0_ 15)) then CapEx_PermitLoadCapViolation + else if sumbool_of_bool ((Z.eqb p0_ 16)) then CapEx_PermitStoreCapViolation + else if sumbool_of_bool ((Z.eqb p0_ 17)) then CapEx_PermitStoreLocalCapViolation + else if sumbool_of_bool ((Z.eqb p0_ 18)) then CapEx_PermitSealViolation + else if sumbool_of_bool ((Z.eqb p0_ 19)) then CapEx_AccessSystemRegsViolation + else if sumbool_of_bool ((Z.eqb p0_ 20)) then CapEx_PermitCCallViolation + else if sumbool_of_bool ((Z.eqb p0_ 21)) then CapEx_AccessCCallIDCViolation + else if sumbool_of_bool ((Z.eqb p0_ 22)) then CapEx_PermitUnsealViolation + else CapEx_PermitSetCIDViolation. + +Definition num_of_CapEx (arg_ : CapEx) +: {e : Z & ArithFact (0 <= e /\ e <= 23)} := + + build_ex(match arg_ with + | CapEx_None => 0 + | CapEx_LengthViolation => 1 + | CapEx_TagViolation => 2 + | CapEx_SealViolation => 3 + | CapEx_TypeViolation => 4 + | CapEx_CallTrap => 5 + | CapEx_ReturnTrap => 6 + | CapEx_TSSUnderFlow => 7 + | CapEx_UserDefViolation => 8 + | CapEx_TLBNoStoreCap => 9 + | CapEx_InexactBounds => 10 + | CapEx_GlobalViolation => 11 + | CapEx_PermitExecuteViolation => 12 + | CapEx_PermitLoadViolation => 13 + | CapEx_PermitStoreViolation => 14 + | CapEx_PermitLoadCapViolation => 15 + | CapEx_PermitStoreCapViolation => 16 + | CapEx_PermitStoreLocalCapViolation => 17 + | CapEx_PermitSealViolation => 18 + | CapEx_AccessSystemRegsViolation => 19 + | CapEx_PermitCCallViolation => 20 + | CapEx_AccessCCallIDCViolation => 21 + | CapEx_PermitUnsealViolation => 22 + | CapEx_PermitSetCIDViolation => 23 + end). + +Definition undefined_CapEx '(tt : unit) +: M (CapEx) := + + (internal_pick + [CapEx_None;CapEx_LengthViolation;CapEx_TagViolation;CapEx_SealViolation;CapEx_TypeViolation;CapEx_CallTrap;CapEx_ReturnTrap;CapEx_TSSUnderFlow;CapEx_UserDefViolation;CapEx_TLBNoStoreCap;CapEx_InexactBounds;CapEx_GlobalViolation;CapEx_PermitExecuteViolation;CapEx_PermitLoadViolation;CapEx_PermitStoreViolation;CapEx_PermitLoadCapViolation;CapEx_PermitStoreCapViolation;CapEx_PermitStoreLocalCapViolation;CapEx_PermitSealViolation;CapEx_AccessSystemRegsViolation;CapEx_PermitCCallViolation;CapEx_AccessCCallIDCViolation;CapEx_PermitUnsealViolation;CapEx_PermitSetCIDViolation]) + : M (CapEx). + +Definition CapExCode (ex : CapEx) +: mword 8 := + + match ex with + | CapEx_None => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) + | CapEx_LengthViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8) + | CapEx_TagViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0] : mword 8) + | CapEx_SealViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1] : mword 8) + | CapEx_TypeViolation => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0] : mword 8) + | CapEx_CallTrap => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1] : mword 8) + | CapEx_ReturnTrap => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B0] : mword 8) + | CapEx_TSSUnderFlow => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1] : mword 8) + | CapEx_UserDefViolation => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0] : mword 8) + | CapEx_TLBNoStoreCap => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1] : mword 8) + | CapEx_InexactBounds => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0] : mword 8) + | CapEx_GlobalViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0] : mword 8) + | CapEx_PermitExecuteViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B1] : mword 8) + | CapEx_PermitLoadViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0] : mword 8) + | CapEx_PermitStoreViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B1] : mword 8) + | CapEx_PermitLoadCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0] : mword 8) + | CapEx_PermitStoreCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B1] : mword 8) + | CapEx_PermitStoreLocalCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B0] : mword 8) + | CapEx_PermitSealViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1] : mword 8) + | CapEx_AccessSystemRegsViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0] : mword 8) + | CapEx_PermitCCallViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B1] : mword 8) + | CapEx_AccessCCallIDCViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B1;B0] : mword 8) + | CapEx_PermitUnsealViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B1;B1] : mword 8) + | CapEx_PermitSetCIDViolation => (vec_of_bits [B0;B0;B0;B1;B1;B1;B0;B0] : mword 8) + end. + +Definition string_of_capex (ex : CapEx) +: string := + + match ex with + | CapEx_None => "None" + | CapEx_LengthViolation => "LengthViolation" + | CapEx_TagViolation => "TagViolation" + | CapEx_SealViolation => "SealViolation" + | CapEx_TypeViolation => "TypeViolation" + | CapEx_CallTrap => "CallTrap" + | CapEx_ReturnTrap => "ReturnTrap" + | CapEx_TSSUnderFlow => "TSSUnderFlow" + | CapEx_UserDefViolation => "UserDefViolation" + | CapEx_TLBNoStoreCap => "TLBNoStoreCap" + | CapEx_InexactBounds => "InexactBounds" + | CapEx_GlobalViolation => "GlobalViolation" + | CapEx_PermitExecuteViolation => "PermitExecuteViolation" + | CapEx_PermitLoadViolation => "PermitLoadViolation" + | CapEx_PermitStoreViolation => "PermitStoreViolation" + | CapEx_PermitLoadCapViolation => "PermitLoadCapViolation" + | CapEx_PermitStoreCapViolation => "PermitStoreCapViolation" + | CapEx_PermitStoreLocalCapViolation => "PermitStoreLocalCapViolation" + | CapEx_PermitSealViolation => "PermitSealViolation" + | CapEx_AccessSystemRegsViolation => "AccessSystemRegsViolation" + | CapEx_PermitCCallViolation => "PermitCCallViolation" + | CapEx_AccessCCallIDCViolation => "AccessCCallIDCViolation" + | CapEx_PermitUnsealViolation => "PermitUnsealViolation" + | CapEx_PermitSetCIDViolation => "PermitSetCIDViolation" + end. + +Definition undefined_CapCauseReg '(tt : unit) +: M (CapCauseReg) := + + (undefined_bitvector 16) >>= fun w__0 : mword 16 => + returnm (({| CapCauseReg_CapCauseReg_chunk_0 := w__0 |}) + : CapCauseReg). + +Definition Mk_CapCauseReg (v : mword 16) +: CapCauseReg := + + {| CapCauseReg_CapCauseReg_chunk_0 := (subrange_vec_dec v 15 0) |}. + +Definition _get_CapCauseReg_bits (v : CapCauseReg) +: mword 16 := + + subrange_vec_dec v.(CapCauseReg_CapCauseReg_chunk_0) 15 0. + +Definition _set_CapCauseReg_bits +(r_ref : register_ref regstate register_value CapCauseReg) (v : mword 16) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CapCauseReg_CapCauseReg_chunk_0 := + (update_subrange_vec_dec r.(CapCauseReg_CapCauseReg_chunk_0) 15 0 (subrange_vec_dec v 15 0)) ]} + : CapCauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CapCauseReg_bits (v : CapCauseReg) (x : mword 16) +: CapCauseReg := + + {[ v with + CapCauseReg_CapCauseReg_chunk_0 := + (update_subrange_vec_dec v.(CapCauseReg_CapCauseReg_chunk_0) 15 0 (subrange_vec_dec x 15 0)) ]}. + +Definition _get_CapCauseReg_ExcCode (v : CapCauseReg) +: mword 8 := + + subrange_vec_dec v.(CapCauseReg_CapCauseReg_chunk_0) 15 8. + +Definition _set_CapCauseReg_ExcCode +(r_ref : register_ref regstate register_value CapCauseReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CapCauseReg_CapCauseReg_chunk_0 := + (update_subrange_vec_dec r.(CapCauseReg_CapCauseReg_chunk_0) 15 8 (subrange_vec_dec v 7 0)) ]} + : CapCauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CapCauseReg_ExcCode (v : CapCauseReg) (x : mword 8) +: CapCauseReg := + + {[ v with + CapCauseReg_CapCauseReg_chunk_0 := + (update_subrange_vec_dec v.(CapCauseReg_CapCauseReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_CapCauseReg_RegNum (v : CapCauseReg) +: mword 8 := + + subrange_vec_dec v.(CapCauseReg_CapCauseReg_chunk_0) 7 0. + +Definition _set_CapCauseReg_RegNum +(r_ref : register_ref regstate register_value CapCauseReg) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + CapCauseReg_CapCauseReg_chunk_0 := + (update_subrange_vec_dec r.(CapCauseReg_CapCauseReg_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]} + : CapCauseReg in + write_reg r_ref r + : M (unit). + +Definition _update_CapCauseReg_RegNum (v : CapCauseReg) (x : mword 8) +: CapCauseReg := + + {[ v with + CapCauseReg_CapCauseReg_chunk_0 := + (update_subrange_vec_dec v.(CapCauseReg_CapCauseReg_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. + +Definition execute_branch_pcc (newPCC : Capability) +: M (unit) := + + write_reg DelayedPC_ref (to_bits 64 (projT1 (getCapOffset newPCC))) >> + write_reg DelayedPCC_ref newPCC >> + write_reg BranchPending_ref (vec_of_bits [B1] : mword 1) >> + write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) + : M (unit). + +Definition ERETHook '(tt : unit) +: M (unit) := + + read_reg EPCC_ref >>= fun w__0 : Capability => (set_next_pcc w__0) : M (unit). + +Definition raise_c2_exception8 {o : Type} (capEx : CapEx) (regnum : mword 8) +: M (o) := + + let '_ := + (if (trace) then + let '_ := (prerr " C2Ex ") : unit in + let '_ := (prerr (string_of_capex capEx)) : unit in + let '_ := (prerr " reg: ") : unit in + prerr_endline (string_of_bits regnum) + else tt) + : unit in + (_set_CapCauseReg_ExcCode CapCause_ref (CapExCode capEx)) >> + (_set_CapCauseReg_RegNum CapCause_ref regnum) >> + let mipsEx := + if ((orb (generic_eq capEx CapEx_CallTrap) (generic_eq capEx CapEx_ReturnTrap))) then C2Trap + else C2E in + (SignalException mipsEx) + : M (o). + +Definition raise_c2_exception {o : Type} (capEx : CapEx) (regnum : mword 5) +: M (o) := + + let reg8 := concat_vec (vec_of_bits [B0;B0;B0] : mword 3) regnum in + (raise_c2_exception8 capEx reg8) + : M (o). + +Definition raise_c2_exception_noreg {o : Type} (capEx : CapEx) +: M (o) := + + (raise_c2_exception8 capEx (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1] : mword 8)) + : M (o). + +Definition pcc_access_system_regs '(tt : unit) +: M (bool) := + + read_reg PCC_ref >>= fun w__0 : Capability => + returnm (w__0.(Capability_access_system_regs) + : bool). + +Definition MEMr_tagged (addr : mword 64) +: M ((bool * mword (32 * 8))) := + + assert_exp' (Z.eqb (projT1 (emod_with_eq (projT1 (uint addr)) cap_size)) 0) "file ""cheri_prelude_common.sail"", line 357, character 40 to line 357, character 40: ((unsigned(addr) % cap_size) == 0)" >>= fun _ => + (read_tag_bool addr) >>= fun tag => + (MEMr addr cap_size) >>= fun data => returnm (tag, reverse_endianness data). + +Definition MEMr_tagged_reserve (addr : mword 64) +: M ((bool * mword (32 * 8))) := + + assert_exp' (Z.eqb (projT1 (emod_with_eq (projT1 (uint addr)) cap_size)) 0) "file ""cheri_prelude_common.sail"", line 370, character 40 to line 370, character 40: ((unsigned(addr) % cap_size) == 0)" >>= fun _ => + (read_tag_bool addr) >>= fun tag => + (MEMr_reserve addr cap_size) >>= fun data => returnm (tag, reverse_endianness data). + +Definition MEMw_tagged (addr : mword 64) (tag : bool) (data : mword (32 * 8)) +: M (unit) := + + assert_exp' (Z.eqb (projT1 (emod_with_eq (projT1 (uint addr)) cap_size)) 0) "file ""cheri_prelude_common.sail"", line 383, character 40 to line 383, character 40: ((unsigned(addr) % cap_size) == 0)" >>= fun _ => + (MEMea addr cap_size) >> + (MEMval addr cap_size (reverse_endianness data)) >> (write_tag_bool addr tag) : M (unit). + +Definition MEMw_tagged_conditional (addr : mword 64) (tag : bool) (data : mword (32 * 8)) +: M (bool) := + + assert_exp' (Z.eqb (projT1 (emod_with_eq (projT1 (uint addr)) cap_size)) 0) "file ""cheri_prelude_common.sail"", line 396, character 40 to line 396, character 40: ((unsigned(addr) % cap_size) == 0)" >>= fun _ => + (MEMea_conditional addr cap_size) >> + (MEMval_conditional addr cap_size (reverse_endianness data)) >>= fun success => + (if (success) then (write_tag_bool addr tag) : M (unit) + else returnm (tt : unit)) >> + returnm (success + : bool). + +Definition cap_addr_mask := to_bits 64 (Z.sub (projT1 (pow2 64)) cap_size). +Hint Unfold cap_addr_mask : sail. +Definition MEMw_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) +`{ArithFact (size >= 1)} +: M (unit) := + + let ledata := reverse_endianness data in + (if ((eq_vec addr + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + write_reg UART_WDATA_ref (subrange_vec_dec ledata 7 0) >> + write_reg UART_WRITTEN_ref (vec_of_bits [B1] : mword 1) + : M (unit) + else + assert_exp' (eq_vec (and_vec addr cap_addr_mask) + (and_vec (add_vec addr (to_bits 64 (Z.sub size 1))) cap_addr_mask)) "file ""cheri_prelude_common.sail"", line 420, character 86 to line 420, character 86: ((addr & cap_addr_mask) == ((addr + to_bits(64, (size - 1))) & cap_addr_mask))" >>= fun _ => + (MEMea addr size) >> + (MEMval addr size ledata) >> (write_tag_bool (and_vec addr cap_addr_mask) false) : M (unit)) + : M (unit). + +Definition MEMw_conditional_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) +`{ArithFact (size >= 1)} +: M (bool) := + + assert_exp' (eq_vec (and_vec addr cap_addr_mask) + (and_vec (add_vec addr (to_bits 64 (Z.sub size 1))) cap_addr_mask)) "file ""cheri_prelude_common.sail"", line 434, character 86 to line 434, character 86: ((addr & cap_addr_mask) == ((addr + to_bits(64, (size - 1))) & cap_addr_mask))" >>= fun _ => + (MEMea_conditional addr size) >> + (MEMval_conditional addr size (reverse_endianness data)) >>= fun success => + (if (success) then (write_tag_bool (and_vec addr cap_addr_mask) false) : M (unit) + else returnm (tt : unit)) >> + returnm (success + : bool). + +Definition checkDDCPerms (ddc : Capability) (accessType : MemAccessType) +: M (unit) := + + (if ((negb ddc.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (unit) + else if (ddc.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (unit) + else returnm (tt : unit)) >> + (match accessType with + | Instruction => + (assert_exp false "file ""cheri_prelude_common.sail"", line 451, character 35 to line 451, character 35: false") + : M (unit) + | LoadData => + (if ((negb ddc.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (unit) + else returnm (tt : unit)) + : M (unit) + | StoreData => + (if ((negb ddc.(Capability_permit_store))) then + (raise_c2_exception CapEx_PermitStoreViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (unit) + else returnm (tt : unit)) + : M (unit) + end) + : M (unit). + +Definition addrWrapper (addr : mword 64) (accessType : MemAccessType) (width : WordType) +: M (mword 64) := + + read_reg DDC_ref >>= fun ddc => + (checkDDCPerms ddc accessType) >> + let 'cursor := projT1 (getCapCursor ddc) in + let 'vAddr := projT1 (emod_with_eq (Z.add cursor (projT1 (uint addr))) (projT1 (pow2 64))) in + let 'size := projT1 (wordWidthBytes width) in + let '(existT _ base _, existT _ top _) := getCapBounds ddc in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr size) top)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (mword 64) + else if sumbool_of_bool ((Z.ltb vAddr base)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (mword 64) + else returnm ((to_bits 64 vAddr) : mword 64)) + : M (mword 64). + +Definition addrWrapperUnaligned +(addr : mword 64) (accessType : MemAccessType) (width : WordTypeUnaligned) +: M (mword 64) := + + read_reg DDC_ref >>= fun ddc => + (checkDDCPerms ddc accessType) >> + let 'cursor := projT1 (getCapCursor ddc) in + let 'vAddr := projT1 (emod_with_eq (Z.add cursor (projT1 (uint addr))) (projT1 (pow2 64))) in + let 'woffset := projT1 (emod_with_eq vAddr 4) in + let 'doffset := projT1 (emod_with_eq vAddr 8) in + let '(waddr, size) := + (match width with + | WL => (vAddr, Z.sub 4 woffset) + | WR => (Z.sub vAddr woffset, Z.add woffset 1) + | DL => (vAddr, Z.sub 8 doffset) + | DR => (Z.sub vAddr doffset, Z.add doffset 1) + end) + : (Z * Z) in + let '(existT _ base _, existT _ top _) := getCapBounds ddc in + (if sumbool_of_bool ((Z.gtb (Z.add waddr size) top)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (mword 64) + else if sumbool_of_bool ((Z.ltb waddr base)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + : M (mword 64) + else returnm ((to_bits 64 vAddr) : mword 64)) + : M (mword 64). + +Definition execute_branch (pc : mword 64) +: M (unit) := + + read_reg PCC_ref >>= fun w__0 : Capability => + let 'len := projT1 (getCapLength w__0) in + (if sumbool_of_bool ((Z.gtb (Z.add (projT1 (uint pc)) 4) len)) then + (raise_c2_exception_noreg CapEx_LengthViolation) + : M (unit) + else returnm (tt : unit)) >> + (execute_branch_mips pc) + : M (unit). + +Definition TranslatePC (vAddr : mword 64) +: M (mword 64) := + + (incrementCP0Count tt) >> + read_reg PCC_ref >>= fun pcc => + let '(existT _ base _, existT _ top _) := getCapBounds pcc in + let 'absPC := Z.add base (projT1 (uint vAddr)) in + (if ((neq_int (projT1 (emod_with_eq absPC 4)) 0)) then + (SignalExceptionBadAddr AdEL (to_bits 64 absPC)) + : M (mword 64) + else if ((negb pcc.(Capability_tag))) then + (raise_c2_exception_noreg CapEx_TagViolation) + : M (mword 64) + else if (pcc.(Capability_sealed)) then + (raise_c2_exception_noreg CapEx_SealViolation) + : M (mword 64) + else if ((negb pcc.(Capability_permit_execute))) then + (raise_c2_exception_noreg CapEx_PermitExecuteViolation) + : M (mword 64) + else if sumbool_of_bool ((Z.gtb (Z.add absPC 4) top)) then + (raise_c2_exception_noreg CapEx_LengthViolation) + : M (mword 64) + else (TLBTranslate (to_bits 64 absPC) Instruction) : M (mword 64)) + : M (mword 64). + +Definition checkCP2usable '(tt : unit) +: M (unit) := + + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + (if ((negb ((bit_to_bool (access_vec_dec (_get_StatusReg_CU w__0) 2)) : bool))) then + (_set_CauseReg_CE CP0Cause_ref (vec_of_bits [B1;B0] : mword 2)) >> + (SignalException CpU) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition init_cp2_state '(tt : unit) +: M (unit) := + + write_reg PCC_ref default_cap >> + write_reg NextPCC_ref default_cap >> + write_reg DelayedPCC_ref default_cap >> + write_reg DDC_ref default_cap >> + write_reg KCC_ref default_cap >> + write_reg EPCC_ref default_cap >> + write_reg KDC_ref null_cap >> + write_reg KR1C_ref null_cap >> + write_reg KR2C_ref null_cap >> + write_reg CTLSP_ref null_cap >> + write_reg CTLSU_ref null_cap >> + (foreach_ZM_up 1 31 1 tt + (fun i _ unit_var => + let idx := to_bits 5 i in + (writeCapReg idx null_cap) + : M (unit))) + : M (unit). + +Definition cp2_next_pc '(tt : unit) +: M (unit) := + + read_reg NextPCC_ref >>= fun w__0 : Capability => + write_reg PCC_ref w__0 >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + (if (((bits_to_bool w__1) : bool)) then + read_reg DelayedPCC_ref >>= fun w__2 : Capability => write_reg NextPCC_ref w__2 : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition readEPCC '(tt : unit) +: M (Capability) := + + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + (if ((Bool.eqb ((bits_to_bool (_get_StatusReg_ERL w__0)) : bool) ((bit_to_bool B1) : bool))) + then + ((read_reg CP0ErrorEPC_ref) : M (mword 64)) + : M (bits 64) + else ((read_reg CP0EPC_ref) : M (mword 64)) : M (bits 64)) >>= fun epccOffset => + read_reg EPCC_ref >>= fun epcc => + let '(success, epcc2) := setCapOffset epcc epccOffset in + returnm ((if (success) then epcc2 + else + int_to_cap + (add_vec_int (to_bits 64 (projT1 (getCapBase epcc))) (projT1 (uint epccOffset)))) + : Capability). + +Definition dump_cp2_state '(tt : unit) +: M (unit) := + + read_reg PCC_ref >>= fun w__0 : Capability => + (capToString w__0 true) >>= fun w__1 : string => + let '_ := (print_endline (String.append "DEBUG CAP PCC" w__1)) : unit in + (foreach_ZM_up 0 31 1 tt + (fun i _ unit_var => + (readCapReg (to_bits 5 i)) >>= fun w__2 : Capability => + (capToString w__2 true) >>= fun w__3 : string => + returnm (let '_ := + (print_endline (String.append "DEBUG CAP REG " (String.append (string_of_int i) w__3))) + : unit in + tt))) >> + read_reg DDC_ref >>= fun w__4 : Capability => + (capToString w__4 true) >>= fun w__5 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 00" w__5)) : unit in + read_reg CTLSU_ref >>= fun w__6 : Capability => + (capToString w__6 true) >>= fun w__7 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 01" w__7)) : unit in + read_reg CTLSP_ref >>= fun w__8 : Capability => + (capToString w__8 true) >>= fun w__9 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 08" w__9)) : unit in + read_reg KR1C_ref >>= fun w__10 : Capability => + (capToString w__10 true) >>= fun w__11 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 22" w__11)) : unit in + read_reg KR2C_ref >>= fun w__12 : Capability => + (capToString w__12 true) >>= fun w__13 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 23" w__13)) : unit in + read_reg KCC_ref >>= fun w__14 : Capability => + (capToString w__14 true) >>= fun w__15 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 29" w__15)) : unit in + read_reg KDC_ref >>= fun w__16 : Capability => + (capToString w__16 true) >>= fun w__17 : string => + let '_ := (print_endline (String.append "DEBUG CAP HWREG 30" w__17)) : unit in + (readEPCC tt) >>= fun w__18 : Capability => + (capToString w__18 true) >>= fun w__19 : string => + returnm ((print_endline (String.append "DEBUG CAP HWREG 31" w__19)) + : unit). + +Definition TLBWriteEntry (idx : mword 6) +: M (unit) := + + ((read_reg TLBPageMask_ref) : M (mword 16)) >>= fun pagemask => + let b__0 := pagemask in + (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16))) + then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else if ((eq_vec b__0 + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then + returnm (tt + : unit) + else (SignalException MCheck) : M (unit)) >> + let 'i := projT1 (uint idx) in + let entry := vec_access_dec TLBEntries i in + (_set_TLBEntry_pagemask entry pagemask) >> + read_reg TLBEntryHi_ref >>= fun w__0 : TLBEntryHiReg => + (_set_TLBEntry_r entry (_get_TLBEntryHiReg_R w__0)) >> + read_reg TLBEntryHi_ref >>= fun w__1 : TLBEntryHiReg => + (_set_TLBEntry_vpn2 entry (_get_TLBEntryHiReg_VPN2 w__1)) >> + read_reg TLBEntryHi_ref >>= fun w__2 : TLBEntryHiReg => + (_set_TLBEntry_asid entry (_get_TLBEntryHiReg_ASID w__2)) >> + (and_boolM + (read_reg TLBEntryLo0_ref >>= fun w__3 : TLBEntryLoReg => + returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__3)) + : bool)) + (read_reg TLBEntryLo1_ref >>= fun w__4 : TLBEntryLoReg => + returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__4)) + : bool))) >>= fun w__5 : bool => + (_set_TLBEntry_g entry ((bool_to_bits w__5) : mword 1)) >> + (_set_TLBEntry_valid entry ((cast_unit_vec B1) : mword 1)) >> + read_reg TLBEntryLo0_ref >>= fun w__6 : TLBEntryLoReg => + (_set_TLBEntry_caps0 entry (_get_TLBEntryLoReg_CapS w__6)) >> + read_reg TLBEntryLo0_ref >>= fun w__7 : TLBEntryLoReg => + (_set_TLBEntry_capl0 entry (_get_TLBEntryLoReg_CapL w__7)) >> + read_reg TLBEntryLo0_ref >>= fun w__8 : TLBEntryLoReg => + (_set_TLBEntry_pfn0 entry (_get_TLBEntryLoReg_PFN w__8)) >> + read_reg TLBEntryLo0_ref >>= fun w__9 : TLBEntryLoReg => + (_set_TLBEntry_c0 entry (_get_TLBEntryLoReg_C w__9)) >> + read_reg TLBEntryLo0_ref >>= fun w__10 : TLBEntryLoReg => + (_set_TLBEntry_d0 entry (_get_TLBEntryLoReg_D w__10)) >> + read_reg TLBEntryLo0_ref >>= fun w__11 : TLBEntryLoReg => + (_set_TLBEntry_v0 entry (_get_TLBEntryLoReg_V w__11)) >> + read_reg TLBEntryLo1_ref >>= fun w__12 : TLBEntryLoReg => + (_set_TLBEntry_caps1 entry (_get_TLBEntryLoReg_CapS w__12)) >> + read_reg TLBEntryLo1_ref >>= fun w__13 : TLBEntryLoReg => + (_set_TLBEntry_capl1 entry (_get_TLBEntryLoReg_CapL w__13)) >> + read_reg TLBEntryLo1_ref >>= fun w__14 : TLBEntryLoReg => + (_set_TLBEntry_pfn1 entry (_get_TLBEntryLoReg_PFN w__14)) >> + read_reg TLBEntryLo1_ref >>= fun w__15 : TLBEntryLoReg => + (_set_TLBEntry_c1 entry (_get_TLBEntryLoReg_C w__15)) >> + read_reg TLBEntryLo1_ref >>= fun w__16 : TLBEntryLoReg => + (_set_TLBEntry_d1 entry (_get_TLBEntryLoReg_D w__16)) >> + read_reg TLBEntryLo1_ref >>= fun w__17 : TLBEntryLoReg => + (_set_TLBEntry_v1 entry (_get_TLBEntryLoReg_V w__17)) + : M (unit). + +Definition decode (v__0 : mword 32) +: option ast := + + if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (DADDIU + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DADDU + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (DADDI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DADD + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (ADD + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (ADDI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (ADDU + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (ADDIU + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSUBU + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSUB + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SUB + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SUBU + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (AND + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (ANDI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (OR + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (ORI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (NOR + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (XOR + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (XORI + ((rs, rt, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword (31 - 21 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (LUI + ((rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B0;B0;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSLL + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B1;B0;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSLL32 + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSLLV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B0;B1;B1] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRA + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRA32 + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRAV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRL + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B1;B1;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRL32 + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DSRLV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let sa : regno := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLL + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLLV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let sa : regno := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SRA + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SRAV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let sa : regno := subrange_vec_dec v__0 10 6 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SRL + ((rt, rd, sa))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SRLV + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLT + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (SLTI + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLTU + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (SLTIU + ((rs, rt, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MOVN + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MOVZ + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 16 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MFHI + (rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 16 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MFLO + (rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1] + : mword (20 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MTHI + (rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1] + : mword (20 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MTLO + (rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MUL + ((rs, rt, rd))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MULT + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MULTU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DMULT + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DMULTU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MADD + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MADDU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MSUB + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MSUBU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DIV + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DIVU + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DDIV + ((rs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DDIVU + ((rs, rt))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword (31 - 26 + 1)))) then + let offset : bits 26 := subrange_vec_dec v__0 25 0 in + Some + (J + (offset)) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword (31 - 26 + 1)))) then + let offset : bits 26 := subrange_vec_dec v__0 25 0 in + Some + (JAL + (offset)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__0 20 11) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (20 - 11 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword (5 - 0 + 1)))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (JR + (rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword (5 - 0 + 1)))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (JALR + ((rs, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, false, false))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, false, true))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, true, false))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, true, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LT', false, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LT', true, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B1;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LT', false, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B1;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LT', true, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GE, false, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B0;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GE, true, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B1;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GE, false, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B1;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GE, true, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B1;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GT', false, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B1;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, GT', false, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LE, false, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BCMPZ + ((rs, imm, LE, false, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword (5 - 0 + 1))))) then + Some + (SYSCALL + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword (5 - 0 + 1))))) then + Some + (BREAK + (tt)) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] + : mword 32))) then + Some + (WAIT + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, GE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, GEU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, LT'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, LTU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B1;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, EQ'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B1;B1;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, NE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B1;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, EQ'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B1;B1;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, NE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B0;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, GE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B0;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, GEU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B1;B0] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, LT'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B1;B1] : mword (20 - 16 + 1))))) then + let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (TRAPIMM + ((rs, imm, LTU))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((B, true, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((B, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((H, true, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((H, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((W, true, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((W, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B1;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((D, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((W, true, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((D, false, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((B, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((H, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((W, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((D, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((W, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((D, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LWL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LWR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SWL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SWR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LDL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B1;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LDR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B0;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SDL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let offset : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SDR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B1;B1] : mword (31 - 26 + 1)))) then + let op : regno := subrange_vec_dec v__0 20 16 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (CACHE + ((base, op, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 11) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 11 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B1;B1] : mword (5 - 0 + 1))))) then + Some + (SYNC + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 3) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MFC0 + ((rt, rd, sel, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 3) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MFC0 + ((rt, rd, sel, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (15 - 0 + 1))))) then + Some + (HCF + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (15 - 0 + 1))))) then + Some + (HCF + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 3) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MTC0 + ((rt, rd, sel, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 3) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (MTC0 + ((rt, rd, sel, true))) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] + : mword 32))) then + Some + ((TLBWI + (tt)) + : ast) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] + : mword 32))) then + Some + ((TLBWR + (tt)) + : ast) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] + : mword 32))) then + Some + ((TLBR + (tt)) + : ast) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0] + : mword 32))) then + Some + ((TLBP + (tt)) + : ast) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (RDHWR + ((rt, rd))) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] + : mword 32))) then + Some + (ERET + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetPerm + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetType + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetBase + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetLen + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetTag + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetSealed + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] + : mword (15 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + Some + (CGetCause + (rd)) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32))) then + Some + (CReturn + (tt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetOffset + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 11) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 11 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + Some + (CSetCause + (rt)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CAndPerm + ((cd, cb, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CToPtr + ((rd, cb, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CEQ))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CNE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CLT))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CLE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B0;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CLTU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B0;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CLEU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B1;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CEXEQ))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B1;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, ct, CNEXEQ))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CIncOffset + ((cd, cb, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CSetOffset + ((cd, cb, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CSetBounds + ((cd, cb, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword (10 - 0 + 1))))) then + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CClearTag + ((cd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B1;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CFromPtr + ((cd, cb, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B1] : mword (31 - 21 + 1))) + (andb + (eq_vec (subrange_vec_dec v__0 15 11) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (15 - 11 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1)))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 20 16 in + Some + (CCheckPerm + ((cs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword (10 - 0 + 1))))) then + let cs : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CCheckType + ((cs, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CSeal + ((cd, cs, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CUnseal + ((cd, cs, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B1;B1] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CJALR + ((cd, cb, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 16 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CJALR + (((vec_of_bits [B0;B0;B0;B0;B0] : mword 5), cb, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + Some + (CGetCause + (rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 20 16 in + Some + (CSetCause + (rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CGetPCC + (cd)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CJALR + (((vec_of_bits [B0;B0;B0;B0;B0] : mword 5), cb, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + Some + (CGetCID + (rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CSetCID + (cb)) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 15 11 in + let cs : regno := subrange_vec_dec v__0 20 16 in + Some + (CCheckPerm + ((cs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let cs : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CCheckType + ((cs, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CClearTag + ((cd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B0;B1;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CMOVX + ((cd, cs, (vec_of_bits [B0;B0;B0;B0;B0] : mword 5), false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CJALR + ((cd, cb, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadTags + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetPerm + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetType + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetBase + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetLen + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetTag + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetSealed + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CGetOffset + ((rd, cb))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CGetPCCSetOffset + ((cd, rs))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let sel : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CReadHwr + ((cd, sel))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let sel : regno := subrange_vec_dec v__0 15 11 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CWriteHwr + ((cb, sel))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let sel : regno := subrange_vec_dec v__0 15 11 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CGetAddr + ((cb, sel))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B1;B1] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CSeal + ((cd, cs, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CUnseal + ((cd, cs, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CAndPerm + ((cd, cs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B1;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CSetOffset + ((cd, cs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CSetBounds + ((cd, cs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CSetBoundsExact + ((cd, cs, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CIncOffset + ((cd, cb, rt))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CBuildCap + ((cd, cb, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B1;B1;B0] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CCopyType + ((cd, cb, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B1;B1;B1] : mword (5 - 0 + 1))))) then + let ct : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CCSeal + ((cd, cs, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CToPtr + ((rd, cb, ct))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 10 6 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CFromPtr + ((cd, cb, rs))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CSub + ((rt, cb, cs))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B0;B1;B1] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CMOVX + ((cd, cs, rs, false))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 15 11 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CMOVX + ((cd, cs, rs, true))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B1;B0;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CEQ))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B1;B0;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CNE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B1;B1;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CLT))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CLE))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CLTU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CLEU))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B1;B1;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CEXEQ))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B0;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cs : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CPtrCmp + ((rd, cb, cs, CNEXEQ))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let ct : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CTestSubset + ((rd, cb, ct))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B0;B1] : mword (31 - 21 + 1)))) then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CBX + ((cd, imm, true))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B0] : mword (31 - 21 + 1)))) then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CBX + ((cd, imm, false))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B1] : mword (31 - 21 + 1)))) then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CBZ + ((cd, imm, false))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B1;B0] : mword (31 - 21 + 1)))) then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + let cd : regno := subrange_vec_dec v__0 20 16 in + Some + (CBZ + ((cd, imm, true))) + else if ((eq_vec v__0 + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] + : mword 32))) then + Some + (CReturn + (tt)) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B1] : mword (31 - 21 + 1)))) then + let selector : bits 11 := subrange_vec_dec v__0 10 0 in + let cs : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CCall + ((cs, cb, selector))) + else if ((eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword (31 - 16 + 1)))) + then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + Some + (ClearRegs + ((GPLo, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B1] : mword (31 - 16 + 1)))) + then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + Some + (ClearRegs + ((GPHi, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B1;B0] : mword (31 - 16 + 1)))) + then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + Some + (ClearRegs + ((CLo, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 16) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B1;B1] : mword (31 - 16 + 1)))) + then + let imm : bits 16 := subrange_vec_dec v__0 15 0 in + Some + (ClearRegs + ((CHi, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B1;B1] : mword (31 - 21 + 1)))) then + let imm : bits 11 := subrange_vec_dec v__0 10 0 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CIncOffsetImmediate + ((cd, cb, imm))) + else if ((eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B1;B0;B0] : mword (31 - 21 + 1)))) then + let imm : bits 11 := subrange_vec_dec v__0 10 0 in + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CSetBoundsImmediate + ((cd, cb, imm))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, false, B))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, true, B))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, false, H))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, true, H))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, false, W))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, true, W))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rd : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLoad + ((rd, cb, rt, offset, false, D))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, false, B))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, true, B))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, false, H))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, true, H))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, false, W))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, true, W))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLoadLinked + ((rd, cb, false, D))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CStore + ((rs, cb, rt, offset, B))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CStore + ((rs, cb, rt, offset, H))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CStore + ((rs, cb, rt, offset, W))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 2 0) (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1))))) + then + let rt : regno := subrange_vec_dec v__0 15 11 in + let rs : regno := subrange_vec_dec v__0 25 21 in + let offset : bits 8 := subrange_vec_dec v__0 10 3 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CStore + ((rs, cb, rt, offset, D))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CStoreConditional + ((rs, cb, rd, B))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CStoreConditional + ((rs, cb, rd, H))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CStoreConditional + ((rs, cb, rd, W))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let rs : regno := subrange_vec_dec v__0 20 16 in + let rd : regno := subrange_vec_dec v__0 10 6 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CStoreConditional + ((rs, cb, rd, D))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 15 11 in + let offset : bits 11 := subrange_vec_dec v__0 10 0 in + let cs : regno := subrange_vec_dec v__0 25 21 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CSC + ((cs, cb, rt, offset))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B1;B1;B1] : mword (5 - 0 + 1))))) then + let rd : regno := subrange_vec_dec v__0 10 6 in + let cs : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CSCC + ((cs, cb, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B1;B1;B0] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 15 11 in + let offset : bits 11 := subrange_vec_dec v__0 10 0 in + let cd : regno := subrange_vec_dec v__0 25 21 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLC + ((cd, cb, rt, offset))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 10 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then + let cd : regno := subrange_vec_dec v__0 20 16 in + let cb : regno := subrange_vec_dec v__0 15 11 in + Some + (CLLC + ((cd, cb))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B1] : mword (31 - 26 + 1)))) then + let offset : bits 16 := subrange_vec_dec v__0 15 0 in + let cd : regno := subrange_vec_dec v__0 25 21 in + let cb : regno := subrange_vec_dec v__0 20 16 in + Some + (CLCBI + ((cd, cb, offset))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 21) + (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 15 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] + : mword (15 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in + Some + (C2Dump + (rt)) + else Some (RI (tt)). + +Definition execute_XORI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (xor_vec w__0 (mips_zero_extend 64 imm))) + : M (unit). + +Definition execute_XOR (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (xor_vec w__0 w__1)) : M (unit). + +Definition execute_WAIT '(tt : unit) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + write_reg NextPC_ref w__1 + : M (unit). + +Definition execute_TRAPREG (rs : mword 5) (rt : mword 5) (cmp : Comparison) +: M (unit) := + + (rGPR rs) >>= fun rs_val => + (rGPR rt) >>= fun rt_val => + let condition := compare cmp rs_val rt_val in + (if (condition) then (SignalException Tr) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_TRAPIMM (rs : mword 5) (imm : mword 16) (cmp : Comparison) +: M (unit) := + + (rGPR rs) >>= fun rs_val => + let imm_val : bits 64 := mips_sign_extend 64 imm in + let condition := compare cmp rs_val imm_val in + (if (condition) then (SignalException Tr) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_TLBWR '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + (TLBWriteEntry w__0) + : M (unit). + +Definition execute_TLBWI '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + ((read_reg TLBIndex_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + (TLBWriteEntry w__0) + : M (unit). + +Definition execute_TLBR '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + ((read_reg TLBIndex_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + let 'i := projT1 (uint w__0) in + (reg_deref (vec_access_dec TLBEntries i)) >>= fun entry => + write_reg TLBPageMask_ref (_get_TLBEntry_pagemask entry) >> + (_set_TLBEntryHiReg_R TLBEntryHi_ref (_get_TLBEntry_r entry)) >> + (_set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (_get_TLBEntry_vpn2 entry)) >> + (_set_TLBEntryHiReg_ASID TLBEntryHi_ref (_get_TLBEntry_asid entry)) >> + (_set_TLBEntryLoReg_CapS TLBEntryLo0_ref (_get_TLBEntry_caps0 entry)) >> + (_set_TLBEntryLoReg_CapL TLBEntryLo0_ref (_get_TLBEntry_capl0 entry)) >> + (_set_TLBEntryLoReg_PFN TLBEntryLo0_ref (_get_TLBEntry_pfn0 entry)) >> + (_set_TLBEntryLoReg_C TLBEntryLo0_ref (_get_TLBEntry_c0 entry)) >> + (_set_TLBEntryLoReg_D TLBEntryLo0_ref (_get_TLBEntry_d0 entry)) >> + (_set_TLBEntryLoReg_V TLBEntryLo0_ref (_get_TLBEntry_v0 entry)) >> + (_set_TLBEntryLoReg_G TLBEntryLo0_ref (_get_TLBEntry_g entry)) >> + (_set_TLBEntryLoReg_CapS TLBEntryLo1_ref (_get_TLBEntry_caps1 entry)) >> + (_set_TLBEntryLoReg_CapL TLBEntryLo1_ref (_get_TLBEntry_capl1 entry)) >> + (_set_TLBEntryLoReg_PFN TLBEntryLo1_ref (_get_TLBEntry_pfn1 entry)) >> + (_set_TLBEntryLoReg_C TLBEntryLo1_ref (_get_TLBEntry_c1 entry)) >> + (_set_TLBEntryLoReg_D TLBEntryLo1_ref (_get_TLBEntry_d1 entry)) >> + (_set_TLBEntryLoReg_V TLBEntryLo1_ref (_get_TLBEntry_v1 entry)) >> + (_set_TLBEntryLoReg_G TLBEntryLo1_ref (_get_TLBEntry_g entry)) + : M (unit). + +Definition execute_TLBP '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + read_reg TLBEntryHi_ref >>= fun w__0 : TLBEntryHiReg => + (tlbSearch (_get_TLBEntryHiReg_bits w__0)) >>= fun result => + (match result with + | Some (idx) => + write_reg TLBProbe_ref (vec_of_bits [B0] : mword 1) >> + write_reg TLBIndex_ref idx + : M (unit) + | None => + write_reg TLBProbe_ref (vec_of_bits [B1] : mword 1) >> + write_reg TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6) + : M (unit) + end) + : M (unit). + +Definition execute_Store +(width : WordType) (conditional : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) StoreData width) >>= fun vAddr : bits 64 => + (rGPR rt) >>= fun rt_val => + (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdES vAddr) : M (unit) + else + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (if (conditional) then + ((read_reg CP0LLBit_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__1 0)) : bool)) then + (match width with + | W => (MEMw_conditional_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0)) : M (bool) + | D => (MEMw_conditional_wrapper pAddr 8 rt_val) : M (bool) + | _ => (throw (Error_internal_error (tt))) : M (bool) + end) + : M (bool) + else returnm (false : bool)) >>= fun success : bool => + (wGPR rt (mips_zero_extend 64 (bool_to_bits success))) + : M (unit) + else + (match width with + | B => (MEMw_wrapper pAddr 1 (subrange_vec_dec rt_val 7 0)) : M (unit) + | H => (MEMw_wrapper pAddr 2 (subrange_vec_dec rt_val 15 0)) : M (unit) + | W => (MEMw_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0)) : M (unit) + | D => (MEMw_wrapper pAddr 8 rt_val) : M (unit) + end) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_SYSCALL '(tt : unit) : M (unit) := (SignalException Sys) : M (unit). + +Definition execute_SYNC '(tt : unit) : M (unit) := (MEM_sync tt) : M (unit). + +Definition execute_SWR (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WR) >>= fun vAddr => + (TLBTranslate vAddr StoreData) >>= fun pAddr => + let wordAddr := concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2) in + (rGPR rt) >>= fun reg_val => + let b__12 := subrange_vec_dec vAddr 1 0 in + (if ((eq_vec b__12 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then + (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0)) + : M (unit) + else if ((eq_vec b__12 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then + (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0)) + : M (unit) + else if ((eq_vec b__12 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then + (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0)) + : M (unit) + else (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0)) : M (unit)) + : M (unit). + +Definition execute_SWL (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WL) >>= fun vAddr => + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (rGPR rt) >>= fun reg_val => + let b__8 := subrange_vec_dec vAddr 1 0 in + (if ((eq_vec b__8 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then + (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 31 0)) + : M (unit) + else if ((eq_vec b__8 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then + (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 31 8)) + : M (unit) + else if ((eq_vec b__8 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then + (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 31 16)) + : M (unit) + else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 31 24)) : M (unit)) + : M (unit). + +Definition execute_SUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun opA => + (rGPR rt) >>= fun opB => + (if ((orb (NotWordVal opA) (NotWordVal opB))) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + (wGPR rd + (mips_sign_extend 64 (sub_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0)))) + : M (unit)) + : M (unit). + +Definition execute_SUB (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun opA => + (rGPR rt) >>= fun opB => + (if ((orb (NotWordVal opA) (NotWordVal opB))) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + let temp33 : bits 33 := + sub_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) + (mips_sign_extend 33 (subrange_vec_dec opB 31 0)) in + (if ((neq_bool ((bit_to_bool (access_vec_dec temp33 32)) : bool) + ((bit_to_bool (access_vec_dec temp33 31)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rd (mips_sign_extend 64 (subrange_vec_dec temp33 31 0))) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_SRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 4 0 in + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) + else + let rt32 := subrange_vec_dec temp 31 0 in + (shift_bits_right rt32 sa) >>= fun w__2 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__2)) + : M (unit)) + : M (unit). + +Definition execute_SRL (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + let rt32 := subrange_vec_dec temp 31 0 in + (shift_bits_right rt32 sa) >>= fun w__1 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__1)) + : M (unit)) + : M (unit). + +Definition execute_SRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 4 0 in + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) + else + let rt32 := subrange_vec_dec temp 31 0 in + (shift_bits_right_arith rt32 sa) >>= fun w__2 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__2)) + : M (unit)) + : M (unit). + +Definition execute_SRA (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + let rt32 := subrange_vec_dec temp 31 0 in + (shift_bits_right_arith rt32 sa) >>= fun w__1 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__1)) + : M (unit)) + : M (unit). + +Definition execute_SLTU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rs_val => + (rGPR rt) >>= fun rt_val => + (wGPR rd + (mips_zero_extend 64 + (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1)))) + : M (unit). + +Definition execute_SLTIU (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun rs_val => + let immext : bits 64 := mips_sign_extend 64 imm in + (wGPR rt + (mips_zero_extend 64 + (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1)))) + : M (unit). + +Definition execute_SLTI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + let 'imm_val := projT1 (sint imm) in + (rGPR rs) >>= fun w__0 : mword 64 => + let 'rs_val := projT1 (sint w__0) in + (wGPR rt + (mips_zero_extend 64 + (if sumbool_of_bool ((Z.ltb rs_val imm_val)) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1)))) + : M (unit). + +Definition execute_SLT (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + (wGPR rd + (mips_zero_extend 64 + (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1)))) + : M (unit). + +Definition execute_SLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 4 0 in + (rGPR rt) >>= fun w__1 : mword 64 => + let rt32 := subrange_vec_dec w__1 31 0 in + (shift_bits_left rt32 sa) >>= fun w__2 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__2)) + : M (unit). + +Definition execute_SLL (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + let rt32 := subrange_vec_dec w__0 31 0 in + (shift_bits_left rt32 sa) >>= fun w__1 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__1)) + : M (unit). + +Definition execute_SDR (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DR) >>= fun vAddr => + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (rGPR rt) >>= fun reg_val => + let wordAddr := concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3) in + let b__40 := subrange_vec_dec vAddr 2 0 in + (if ((eq_vec b__40 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 5 (subrange_vec_dec reg_val 39 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 6 (subrange_vec_dec reg_val 47 0)) + : M (unit) + else if ((eq_vec b__40 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper wordAddr 7 (subrange_vec_dec reg_val 55 0)) + : M (unit) + else (MEMw_wrapper wordAddr 8 (subrange_vec_dec reg_val 63 0)) : M (unit)) + : M (unit). + +Definition execute_SDL (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DL) >>= fun vAddr => + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (rGPR rt) >>= fun reg_val => + let b__32 := subrange_vec_dec vAddr 2 0 in + (if ((eq_vec b__32 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 8 (subrange_vec_dec reg_val 63 0)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 7 (subrange_vec_dec reg_val 63 8)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 6 (subrange_vec_dec reg_val 63 16)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 5 (subrange_vec_dec reg_val 63 24)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 63 32)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 63 40)) + : M (unit) + else if ((eq_vec b__32 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then + (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 63 48)) + : M (unit) + else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 63 56)) : M (unit)) + : M (unit). + +Definition execute_RI '(tt : unit) : M (unit) := (skip tt) >> (SignalException ResI) : M (unit). + +Definition execute_RDHWR (rt : mword 5) (rd : mword 5) +: M (unit) := + + (getAccessLevel tt) >>= fun accessLevel => + let haveAccessLevel : bool := generic_eq accessLevel Kernel in + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + let haveCU0 : bool := eq_bit B1 (access_vec_dec (_get_StatusReg_CU w__0) 0) in + let 'rdi := projT1 (uint rd) in + ((read_reg CP0HWREna_ref) : M (mword 32)) >>= fun w__1 : bits 32 => + let haveHWREna : bool := eq_bit B1 (access_vec_dec w__1 rdi) in + (if ((negb (orb haveAccessLevel (orb haveCU0 haveHWREna)))) then + (SignalException ResI) + : M (unit) + else returnm (tt : unit)) >> + let b__150 := rd in + (if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))) then + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__2 : bits 32 => + returnm ((mips_zero_extend 64 w__2) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B1] : mword 1)) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))) then + ((read_reg CP0UserLocal_ref) : M (mword 64)) + : M (bits 64) + else (SignalException ResI) : M (mword 64)) >>= fun temp : bits 64 => + (wGPR rt temp) + : M (unit). + +Definition execute_ORI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (or_vec w__0 (mips_zero_extend 64 imm))) + : M (unit). + +Definition execute_OR (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (or_vec w__0 w__1)) : M (unit). + +Definition execute_NOR (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (not_vec (or_vec w__0 w__1))) : M (unit). + +Definition execute_MULTU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun result : bits 64 => + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MULT (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun result : bits 64 => + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MUL (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + let result : bits 64 := + mips_sign_extend 64 (mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) in + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else returnm ((mips_sign_extend 64 (subrange_vec_dec result 31 0)) : mword 64)) >>= fun w__1 : mword 64 => + (wGPR rd w__1) + : M (unit). + +Definition execute_MTLO (rs : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => write_reg LO_ref w__0 : M (unit). + +Definition execute_MTHI (rs : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => write_reg HI_ref w__0 : M (unit). + +Definition execute_MTC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) +: M (unit) := + + (checkCP0Access tt) >> + (rGPR rt) >>= fun reg_val => + (match (rd, sel) with + | (b__112, b__113) => + (if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg TLBIndex_ref (mask 6 reg_val) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm (tt + : unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_ContextReg_PTEBase TLBContext_ref (subrange_vec_dec reg_val 63 23)) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B1;B0] : mword 3)))) then + write_reg CP0UserLocal_ref reg_val + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg TLBPageMask_ref (subrange_vec_dec reg_val 28 13) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg TLBWired_ref (mask 6 reg_val) >> write_reg TLBRandom_ref TLBIndexMax : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg + CP0HWREna_ref + (concat_vec (subrange_vec_dec reg_val 31 29) + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0] + : mword 25) (subrange_vec_dec reg_val 3 0))) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm (tt + : unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0Count_ref (subrange_vec_dec reg_val 31 0) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec reg_val 63 62)) >> + (_set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec reg_val 39 13)) >> + (_set_TLBEntryHiReg_ASID TLBEntryHi_ref (subrange_vec_dec reg_val 7 0)) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0Compare_ref (subrange_vec_dec reg_val 31 0) >> + read_reg CP0Cause_ref >>= fun w__0 : CauseReg => + (_set_CauseReg_IP CP0Cause_ref + (and_vec (_get_CauseReg_IP w__0) (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : mword 8))) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_StatusReg_CU CP0Status_ref + (and_vec (subrange_vec_dec reg_val 31 28) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (bool_to_bits have_cp2) (vec_of_bits [B0;B1] : mword 2))))) >> + (_set_StatusReg_BEV CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 22)) : mword 1)) >> + (_set_StatusReg_IM CP0Status_ref (subrange_vec_dec reg_val 15 8)) >> + (_set_StatusReg_KX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 7)) : mword 1)) >> + (_set_StatusReg_SX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 6)) : mword 1)) >> + (_set_StatusReg_UX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 5)) : mword 1)) >> + (_set_StatusReg_KSU CP0Status_ref (subrange_vec_dec reg_val 4 3)) >> + (_set_StatusReg_ERL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 2)) : mword 1)) >> + (_set_StatusReg_EXL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 1)) : mword 1)) >> + (_set_StatusReg_IE CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 0)) : mword 1)) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_CauseReg_IV CP0Cause_ref ((cast_unit_vec (access_vec_dec reg_val 23)) : mword 1)) >> + read_reg CP0Cause_ref >>= fun w__1 : CauseReg => + let ip := _get_CauseReg_IP w__1 in + (_set_CauseReg_IP CP0Cause_ref + (concat_vec (subrange_vec_dec ip 7 2) (subrange_vec_dec reg_val 9 8))) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0EPC_ref reg_val + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0ConfigK0_ref (subrange_vec_dec reg_val 2 0) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_XContextReg_XPTEBase TLBXContext_ref (subrange_vec_dec reg_val 63 33)) + : M (unit) + else if ((andb (eq_vec b__112 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + write_reg CP0ErrorEPC_ref reg_val + : M (unit) + else (SignalException ResI) : M (unit)) + : M (unit) + end) + : M (unit). + +Definition execute_MSUBU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let result := + sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MSUB (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let result := + sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MOVZ (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (if ((eq_vec w__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + (rGPR rs) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_MOVN (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (if ((neq_vec w__0 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + (rGPR rs) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_MFLO (rd : mword 5) +: M (unit) := + + ((read_reg LO_ref) : M (mword 64)) >>= fun w__0 : bits 64 => (wGPR rd w__0) : M (unit). + +Definition execute_MFHI (rd : mword 5) +: M (unit) := + + ((read_reg HI_ref) : M (mword 64)) >>= fun w__0 : bits 64 => (wGPR rd w__0) : M (unit). + +Definition execute_MFC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) +: M (unit) := + + (checkCP0Access tt) >> + (match (rd, sel) with + | (b__48, b__49) => + (if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBIndex_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + let idx : bits 31 := mips_zero_extend 31 w__0 in + ((read_reg TLBProbe_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + returnm ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) (concat_vec w__1 idx)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__2 : TLBIndexT => + returnm ((mips_zero_extend 64 w__2) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBEntryLo0_ref >>= fun w__3 : TLBEntryLoReg => + returnm ((_get_TLBEntryLoReg_bits w__3) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBEntryLo1_ref >>= fun w__4 : TLBEntryLoReg => + returnm ((_get_TLBEntryLoReg_bits w__4) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBContext_ref >>= fun w__5 : ContextReg => + returnm ((_get_ContextReg_bits w__5) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then + ((read_reg CP0UserLocal_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBPageMask_ref) : M (mword 16)) >>= fun w__7 : bits 16 => + returnm ((mips_zero_extend 64 + (concat_vec w__7 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBWired_ref) : M (mword 6)) >>= fun w__8 : TLBIndexT => + returnm ((mips_zero_extend 64 w__8) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0HWREna_ref) : M (mword 32)) >>= fun w__9 : bits 32 => + returnm ((mips_zero_extend 64 w__9) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0BadVAddr_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B1] : mword 3)))) then + ((read_reg CP0BadInstr_ref) : M (mword 32)) >>= fun w__11 : bits 32 => + returnm ((mips_zero_extend 64 w__11) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then + ((read_reg CP0BadInstrP_ref) : M (mword 32)) >>= fun w__12 : bits 32 => + returnm ((mips_zero_extend 64 w__12) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__13 : bits 32 => + returnm ((mips_zero_extend 64 w__13) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBEntryHi_ref >>= fun w__14 : TLBEntryHiReg => + returnm ((_get_TLBEntryHiReg_bits w__14) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0Compare_ref) : M (mword 32)) >>= fun w__15 : bits 32 => + returnm ((mips_zero_extend 64 w__15) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg CP0Status_ref >>= fun w__16 : StatusReg => + returnm ((mips_zero_extend 64 (_get_StatusReg_bits w__16)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg CP0Cause_ref >>= fun w__17 : CauseReg => + returnm ((mips_zero_extend 64 (_get_CauseReg_bits w__17)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0EPC_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B1;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B1;B1] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0ConfigK0_ref) : M (mword 3)) >>= fun w__19 : bits 3 => + returnm ((mips_zero_extend 64 + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 15) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B1;B0] : mword 2) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) w__19)))))))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B1] : mword 3)))) then + returnm ((mips_zero_extend 64 + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec TLBIndexMax + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (bool_to_bits have_cp2) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec + (vec_of_bits [B0] : mword 1) + (vec_of_bits [B0] : mword 1)))))))))))))))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (vec_of_bits [B0;B0;B0;B0] : mword 4)))))))))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B1] : mword 3)))) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B0;B1] : mword 3)))) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B1;B0] : mword 3)))) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0LLAddr_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBXContext_ref >>= fun w__21 : XContextReg => + returnm ((_get_XContextReg_bits w__21) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0ErrorEPC_ref) : M (mword 64)) + : M (bits 64) + else (SignalException ResI) : M (mword 64)) + : M (mword 64) + end) >>= fun result : bits 64 => + (wGPR rt (if (double) then result else mips_sign_extend 64 (subrange_vec_dec result 31 0))) + : M (unit). + +Definition execute_MADDU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let result := + add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_MADD (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let result := + add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in + write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> + write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) + : M (unit). + +Definition execute_Load +(width : WordType) (sign : bool) (linked : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) + +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) LoadData width) >>= fun vAddr : bits 64 => + (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdEL vAddr) : M (unit) + else + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (if (linked) then + write_reg CP0LLBit_ref (vec_of_bits [B1] : mword 1) >> + write_reg CP0LLAddr_ref pAddr >> + (match width with + | W => + (MEMr_reserve_wrapper pAddr 4) >>= fun w__1 : mword (8 * 4) => + returnm ((extendLoad w__1 sign) + : mword 64) + | D => + (MEMr_reserve_wrapper pAddr 8) >>= fun w__2 : mword (8 * 8) => + returnm ((extendLoad w__2 sign) + : mword 64) + | _ => (throw (Error_internal_error (tt))) : M (mword 64) + end) + : M (mword 64) + else + (match width with + | B => + (MEMr_wrapper pAddr 1) >>= fun w__5 : mword (8 * 1) => + returnm ((extendLoad w__5 sign) + : mword 64) + | H => + (MEMr_wrapper pAddr 2) >>= fun w__6 : mword (8 * 2) => + returnm ((extendLoad w__6 sign) + : mword 64) + | W => + (MEMr_wrapper pAddr 4) >>= fun w__7 : mword (8 * 4) => + returnm ((extendLoad w__7 sign) + : mword 64) + | D => + (MEMr_wrapper pAddr 8) >>= fun w__8 : mword (8 * 8) => + returnm ((extendLoad w__8 sign) + : mword 64) + end) + : M (mword 64)) >>= fun memResult : bits 64 => + (wGPR rt memResult) + : M (unit)) + : M (unit). + +Definition execute_LWR (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WR) >>= fun vAddr => + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2)) 4) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => + let b__4 := subrange_vec_dec vAddr 1 0 in + let result : bits 32 := + if ((eq_vec b__4 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 31 8) (subrange_vec_dec mem_val 31 24) + else if ((eq_vec b__4 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 31 16) (subrange_vec_dec mem_val 31 16) + else if ((eq_vec b__4 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 31 24) (subrange_vec_dec mem_val 31 8) + else mem_val in + (wGPR rt (mips_sign_extend 64 result)) + : M (unit). + +Definition execute_LWL (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WL) >>= fun vAddr => + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2)) 4) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => + let b__0 := subrange_vec_dec vAddr 1 0 in + let result : bits 32 := + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then mem_val + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 7 0) + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 15 0) + else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 23 0) in + (wGPR rt (mips_sign_extend 64 result)) + : M (unit). + +Definition execute_LUI (rt : mword 5) (imm : mword 16) +: M (unit) := + + (wGPR rt + (mips_sign_extend 64 + (concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)))) + : M (unit). + +Definition execute_LDR (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DR) >>= fun vAddr => + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3)) 8) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => + let b__24 := subrange_vec_dec vAddr 2 0 in + (wGPR rt + (if ((eq_vec b__24 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 8) (subrange_vec_dec mem_val 63 56) + else if ((eq_vec b__24 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 16) (subrange_vec_dec mem_val 63 48) + else if ((eq_vec b__24 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 24) (subrange_vec_dec mem_val 63 40) + else if ((eq_vec b__24 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 32) (subrange_vec_dec mem_val 63 32) + else if ((eq_vec b__24 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 40) (subrange_vec_dec mem_val 63 24) + else if ((eq_vec b__24 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 48) (subrange_vec_dec mem_val 63 16) + else if ((eq_vec b__24 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec reg_val 63 56) (subrange_vec_dec mem_val 63 8) + else mem_val)) + : M (unit). + +Definition execute_LDL (base : mword 5) (rt : mword 5) (offset : mword 16) +: M (unit) := + + (rGPR base) >>= fun w__0 : mword 64 => + (addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DL) >>= fun vAddr => + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3)) 8) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => + let b__16 := subrange_vec_dec vAddr 2 0 in + (wGPR rt + (if ((eq_vec b__16 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then mem_val + else if ((eq_vec b__16 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 55 0) (subrange_vec_dec reg_val 7 0) + else if ((eq_vec b__16 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 47 0) (subrange_vec_dec reg_val 15 0) + else if ((eq_vec b__16 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 39 0) (subrange_vec_dec reg_val 23 0) + else if ((eq_vec b__16 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 31 0) (subrange_vec_dec reg_val 31 0) + else if ((eq_vec b__16 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 39 0) + else if ((eq_vec b__16 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then + concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 47 0) + else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 55 0))) + : M (unit). + +Definition execute_JR (rs : mword 5) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (rGPR rs) >>= fun w__1 : mword 64 => (execute_branch w__1) : M (unit). + +Definition execute_JALR (rs : mword 5) (rd : mword 5) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (rGPR rs) >>= fun w__1 : mword 64 => + (execute_branch w__1) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + (wGPR rd (add_vec_int w__2 8)) + : M (unit). + +Definition execute_JAL (offset : mword 26) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + (execute_branch + (concat_vec (subrange_vec_dec (add_vec_int w__1 4) 63 28) + (concat_vec offset (vec_of_bits [B0;B0] : mword 2)))) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + (wGPR (vec_of_bits [B1;B1;B1;B1;B1] : mword 5) (add_vec_int w__2 8)) + : M (unit). + +Definition execute_J (offset : mword 26) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + (execute_branch + (concat_vec (subrange_vec_dec (add_vec_int w__1 4) 63 28) + (concat_vec offset (vec_of_bits [B0;B0] : mword 2)))) + : M (unit). + +Definition execute_HCF '(tt : unit) : unit := tt. + +Definition execute_ERET '(tt : unit) +: M (unit) := + + (checkCP0Access tt) >> + (ERETHook tt) >> + write_reg CP0LLBit_ref (vec_of_bits [B0] : mword 1) >> + read_reg CP0Status_ref >>= fun w__0 : StatusReg => + (if ((Bool.eqb ((bits_to_bool (_get_StatusReg_ERL w__0)) : bool) ((bit_to_bool B1) : bool))) + then + ((read_reg CP0ErrorEPC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + write_reg NextPC_ref w__1 >> + (_set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] : mword 1)) + : M (unit) + else + ((read_reg CP0EPC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + write_reg NextPC_ref w__2 >> + (_set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] : mword 1)) + : M (unit)) + : M (unit). + +Definition execute_DSUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (sub_vec w__0 w__1)) : M (unit). + +Definition execute_DSUB (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + let temp65 : bits 65 := sub_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in + (if ((neq_bool ((bit_to_bool (access_vec_dec temp65 64)) : bool) + ((bit_to_bool (access_vec_dec temp65 63)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rd (subrange_vec_dec temp65 63 0)) : M (unit)) + : M (unit). + +Definition execute_DSRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 5 0 in + (shift_bits_right temp sa) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). + +Definition execute_DSRL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + let sa32 := concat_vec (vec_of_bits [B1] : mword 1) sa in + (shift_bits_right temp sa32) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). + +Definition execute_DSRL (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (shift_bits_right temp sa) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). + +Definition execute_DSRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => + let sa := subrange_vec_dec w__0 5 0 in + (shift_bits_right_arith temp sa) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). + +Definition execute_DSRA32 (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + let sa32 := concat_vec (vec_of_bits [B1] : mword 1) sa in + (shift_bits_right_arith temp sa32) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). + +Definition execute_DSRA (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun temp => + (shift_bits_right_arith temp sa) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). + +Definition execute_DSLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (rGPR rs) >>= fun w__1 : mword 64 => + (shift_bits_left w__0 (subrange_vec_dec w__1 5 0)) >>= fun w__2 : mword 64 => + (wGPR rd w__2) + : M (unit). + +Definition execute_DSLL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (shift_bits_left w__0 (concat_vec (vec_of_bits [B1] : mword 1) sa)) >>= fun w__1 : mword 64 => + (wGPR rd w__1) + : M (unit). + +Definition execute_DSLL (rt : mword 5) (rd : mword 5) (sa : mword 5) +: M (unit) := + + (rGPR rt) >>= fun w__0 : mword 64 => + (shift_bits_left w__0 sa) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). + +Definition execute_DMULTU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + let result := mult_vec w__0 w__1 in + write_reg HI_ref (subrange_vec_dec result 127 64) >> + write_reg LO_ref (subrange_vec_dec result 63 0) + : M (unit). + +Definition execute_DMULT (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + let result := mults_vec w__0 w__1 in + write_reg HI_ref (subrange_vec_dec result 127 64) >> + write_reg LO_ref (subrange_vec_dec result 63 0) + : M (unit). + +Definition execute_DIVU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) + (orb (NotWordVal rtVal) + (eq_vec rtVal + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))))) then + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + (undefined_bitvector 32) >>= fun w__1 : mword 32 => returnm (w__0 : bits 32, w__1 : bits 32) + else + let 'si := projT1 (uint (subrange_vec_dec rsVal 31 0)) in + let 'ti := projT1 (uint (subrange_vec_dec rtVal 31 0)) in + let qi := Z.quot si ti in + let ri := Z.rem si ti in + returnm (to_bits 32 qi, to_bits 32 ri)) >>= fun '(q, r) => + write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q) : M (unit). + +Definition execute_DIV (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) + (orb (NotWordVal rtVal) + (eq_vec rtVal + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))))) then + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + (undefined_bitvector 32) >>= fun w__1 : mword 32 => returnm (w__0 : bits 32, w__1 : bits 32) + else + let 'si := projT1 (sint (subrange_vec_dec rsVal 31 0)) in + let 'ti := projT1 (sint (subrange_vec_dec rtVal 31 0)) in + let qi := Z.quot si ti in + let ri := Z.sub si (Z.mul ti qi) in + returnm (to_bits 32 qi, to_bits 32 ri)) >>= fun '(q, r) => + write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q) : M (unit). + +Definition execute_DDIVU (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + let 'rsVal := projT1 (uint w__0) in + (rGPR rt) >>= fun w__1 : mword 64 => + let 'rtVal := projT1 (uint w__1) in + (if sumbool_of_bool ((Z.eqb rtVal 0)) then + (undefined_bitvector 64) >>= fun w__2 : mword 64 => + (undefined_bitvector 64) >>= fun w__3 : mword 64 => returnm (w__2 : bits 64, w__3 : bits 64) + else + let qi := Z.quot rsVal rtVal in + let ri := Z.rem rsVal rtVal in + returnm (to_bits 64 qi, to_bits 64 ri)) >>= fun '(q, r) => + write_reg LO_ref q >> write_reg HI_ref r : M (unit). + +Definition execute_DDIV (rs : mword 5) (rt : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + let 'rsVal := projT1 (sint w__0) in + (rGPR rt) >>= fun w__1 : mword 64 => + let 'rtVal := projT1 (sint w__1) in + (if sumbool_of_bool ((Z.eqb rtVal 0)) then + (undefined_bitvector 64) >>= fun w__2 : mword 64 => + (undefined_bitvector 64) >>= fun w__3 : mword 64 => returnm (w__2 : bits 64, w__3 : bits 64) + else + let qi := Z.quot rsVal rtVal in + let ri := Z.sub rsVal (Z.mul qi rtVal) in + returnm (to_bits 64 qi, to_bits 64 ri)) >>= fun '(q, r) => + write_reg LO_ref q >> write_reg HI_ref r : M (unit). + +Definition execute_DADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (add_vec w__0 w__1)) : M (unit). + +Definition execute_DADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (add_vec w__0 (mips_sign_extend 64 imm))) + : M (unit). + +Definition execute_DADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 imm) in + (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64)) : bool) + ((bit_to_bool (access_vec_dec sum65 63)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rt (subrange_vec_dec sum65 63 0)) : M (unit)) + : M (unit). + +Definition execute_DADD (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => + let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in + (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64)) : bool) + ((bit_to_bool (access_vec_dec sum65 63)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rd (subrange_vec_dec sum65 63 0)) : M (unit)) + : M (unit). + +Definition execute_ClearRegs (regset : ClearRegSet) (m : mword 16) +: M (unit) := + + (if ((orb (generic_eq regset CLo) (generic_eq regset CHi))) then (checkCP2usable tt) : M (unit) + else returnm (tt : unit)) >> + (foreach_ZM_up 0 15 1 tt + (fun i _ unit_var => + (if (((bit_to_bool (access_vec_dec m i)) : bool)) then + (match regset with + | GPLo => (wGPR (to_bits 5 i) (zeros_implicit 64 tt)) : M (unit) + | GPHi => (wGPR (to_bits 5 (Z.add i 16)) (zeros_implicit 64 tt)) : M (unit) + | CLo => + (if sumbool_of_bool ((Z.eqb i 0)) then write_reg DDC_ref null_cap : M (unit) + else (writeCapReg (to_bits 5 i) null_cap) : M (unit)) + : M (unit) + | CHi => (writeCapReg (to_bits 5 (Z.add i 16)) null_cap) : M (unit) + end) + : M (unit) + else returnm (tt : unit)) + : M (unit))) + : M (unit). + +Definition execute_CWriteHwr (cb : mword 5) (sel : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + let 'p0_ := projT1 (uint sel) in + (if sumbool_of_bool ((Z.eqb p0_ 0)) then returnm (false, false) + else if sumbool_of_bool ((Z.eqb p0_ 1)) then returnm (false, false) + else if sumbool_of_bool ((Z.eqb p0_ 8)) then returnm (false, true) + else if sumbool_of_bool ((Z.eqb p0_ 22)) then returnm (true, false) + else if sumbool_of_bool ((Z.eqb p0_ 23)) then returnm (true, false) + else if sumbool_of_bool ((Z.eqb p0_ 29)) then returnm (true, true) + else if sumbool_of_bool ((Z.eqb p0_ 30)) then returnm (true, true) + else if sumbool_of_bool ((Z.eqb p0_ 31)) then returnm (true, true) + else (SignalException ResI) : M ((bool * bool))) >>= fun '(needSup, needAccessSys) => + (and_boolM (returnm (needAccessSys : bool)) + ((pcc_access_system_regs tt) >>= fun w__8 : bool => returnm ((negb w__8) : bool))) >>= fun w__9 : bool => + (if (w__9) then (raise_c2_exception CapEx_AccessSystemRegsViolation sel) : M (unit) + else + (and_boolM (returnm (needSup : bool)) + ((getAccessLevel tt) >>= fun w__10 : AccessLevel => + returnm ((negb (grantsAccess w__10 Supervisor)) + : bool))) >>= fun w__11 : bool => + (if (w__11) then (raise_c2_exception CapEx_AccessSystemRegsViolation sel) : M (unit) + else + (readCapReg cb) >>= fun capVal => + let 'p0_ := projT1 (uint sel) in + (if sumbool_of_bool ((Z.eqb p0_ 0)) then write_reg DDC_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 1)) then write_reg CTLSU_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 8)) then write_reg CTLSP_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 22)) then write_reg KR1C_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 23)) then write_reg KR2C_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 29)) then write_reg KCC_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 30)) then write_reg KDC_ref capVal : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 31)) then + write_reg EPCC_ref capVal >> + read_reg CP0Status_ref >>= fun w__12 : StatusReg => + (if (((bits_to_bool (_get_StatusReg_ERL w__12)) : bool)) then + write_reg CP0ErrorEPC_ref (to_bits 64 (projT1 (getCapOffset capVal))) + : M (unit) + else write_reg CP0EPC_ref (to_bits 64 (projT1 (getCapOffset capVal))) : M (unit)) + : M (unit) + else (assert_exp false "CWriteHwr: should be unreachable code") : M (unit)) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CUnseal (cd : mword 5) (cs : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (readCapReg ct) >>= fun ct_val => + let 'ct_cursor := projT1 (getCapCursor ct_val) in + (if ((negb cs_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cs) : M (unit) + else if ((negb ct_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation ct) + : M (unit) + else if ((negb cs_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cs) + : M (unit) + else if (ct_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation ct) + : M (unit) + else if ((neq_int ct_cursor (projT1 (uint cs_val.(Capability_otype))))) then + (raise_c2_exception CapEx_TypeViolation ct) + : M (unit) + else if ((negb ct_val.(Capability_permit_unseal))) then + (raise_c2_exception CapEx_PermitUnsealViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.ltb ct_cursor (projT1 (getCapBase ct_val)))) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.geb ct_cursor (projT1 (getCapTop ct_val)))) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else + (writeCapReg cd + {| Capability_tag := cs_val.(Capability_tag); + Capability_padding := cs_val.(Capability_padding); + Capability_otype := (zeros_implicit 24 tt); + Capability_uperms := cs_val.(Capability_uperms); + Capability_perm_reserved12_14 := cs_val.(Capability_perm_reserved12_14); + Capability_permit_set_CID := cs_val.(Capability_permit_set_CID); + Capability_access_system_regs := cs_val.(Capability_access_system_regs); + Capability_permit_unseal := cs_val.(Capability_permit_unseal); + Capability_permit_ccall := cs_val.(Capability_permit_ccall); + Capability_permit_seal := cs_val.(Capability_permit_seal); + Capability_permit_store_local_cap := cs_val.(Capability_permit_store_local_cap); + Capability_permit_store_cap := cs_val.(Capability_permit_store_cap); + Capability_permit_load_cap := cs_val.(Capability_permit_load_cap); + Capability_permit_store := cs_val.(Capability_permit_store); + Capability_permit_load := cs_val.(Capability_permit_load); + Capability_permit_execute := cs_val.(Capability_permit_execute); + Capability_global := (andb cs_val.(Capability_global) ct_val.(Capability_global)); + Capability_sealed := false; + Capability_address := cs_val.(Capability_address); + Capability_base := cs_val.(Capability_base); + Capability_length := cs_val.(Capability_length) |}) + : M (unit)) + : M (unit). + +Definition execute_CToPtr (rd : mword 5) (cb : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC ct) >>= fun ct_val => + (readCapReg cb) >>= fun cb_val => + (if ((negb ct_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation ct) : M (unit) + else if ((andb cb_val.(Capability_tag) cb_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else + let 'ctBase := projT1 (getCapBase ct_val) in + (wGPR rd + (if ((negb cb_val.(Capability_tag))) then zeros_implicit 64 tt + else to_bits 64 (Z.sub (projT1 (getCapCursor cb_val)) ctBase))) + : M (unit)) + : M (unit). + +Definition execute_CTestSubset (rd : mword 5) (cb : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (readCapReg ct) >>= fun ct_val => + let 'ct_top := projT1 (getCapTop ct_val) in + let 'ct_base := projT1 (getCapBase ct_val) in + let ct_perms := getCapPerms ct_val in + let 'cb_top := projT1 (getCapTop cb_val) in + let 'cb_base := projT1 (getCapBase cb_val) in + let cb_perms := getCapPerms cb_val in + let result := + if ((neq_bool cb_val.(Capability_tag) ct_val.(Capability_tag))) then + (vec_of_bits [B0] : mword 1) + else if sumbool_of_bool ((Z.ltb ct_base cb_base)) then (vec_of_bits [B0] : mword 1) + else if sumbool_of_bool ((Z.gtb ct_top cb_top)) then (vec_of_bits [B0] : mword 1) + else if ((neq_vec (and_vec ct_perms cb_perms) ct_perms)) then (vec_of_bits [B0] : mword 1) + else (vec_of_bits [B1] : mword 1) in + (wGPR rd (mips_zero_extend 64 result)) + : M (unit). + +Definition execute_CSub (rd : mword 5) (cb : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg ct) >>= fun ct_val => + (readCapReg cb) >>= fun cb_val => + (wGPR rd (to_bits 64 (Z.sub (projT1 (getCapCursor cb_val)) (projT1 (getCapCursor ct_val))))) + : M (unit). + +Definition execute_CStoreConditional (rs : mword 5) (cb : mword 5) (rd : mword 5) (width : WordType) + +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_store))) then + (raise_c2_exception CapEx_PermitStoreViolation cb) + : M (unit) + else + let 'size := projT1 (wordWidthBytes width) in + let 'vAddr := projT1 (getCapCursor cb_val) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((negb (isAddressAligned vAddr64 width))) then + (SignalExceptionBadAddr AdES vAddr64) + : M (unit) + else + (TLBTranslate vAddr64 StoreData) >>= fun pAddr => + (rGPR rs) >>= fun rs_val => + ((read_reg CP0LLBit_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__0 0)) : bool)) then + (match width with + | B => (MEMw_conditional_wrapper pAddr 1 (subrange_vec_dec rs_val 7 0)) : M (bool) + | H => (MEMw_conditional_wrapper pAddr 2 (subrange_vec_dec rs_val 15 0)) : M (bool) + | W => (MEMw_conditional_wrapper pAddr 4 (subrange_vec_dec rs_val 31 0)) : M (bool) + | D => (MEMw_conditional_wrapper pAddr 8 rs_val) : M (bool) + end) + : M (bool) + else returnm (false : bool)) >>= fun success : bool => + (wGPR rd (mips_zero_extend 64 (bool_to_bits success))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CStore +(rs : mword 5) (cb : mword 5) (rt : mword 5) (offset : mword 8) (width : WordType) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_store))) then + (raise_c2_exception CapEx_PermitStoreViolation cb) + : M (unit) + else + let 'size := projT1 (wordWidthBytes width) in + let 'cursor := projT1 (getCapCursor cb_val) in + (rGPR rt) >>= fun w__0 : mword 64 => + let 'vAddr := + projT1 (emod_with_eq + (Z.add (Z.add cursor (projT1 (uint w__0))) (Z.mul size (projT1 (sint offset)))) + (projT1 (pow2 64))) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((negb (isAddressAligned vAddr64 width))) then + (SignalExceptionBadAddr AdES vAddr64) + : M (unit) + else + (TLBTranslate vAddr64 StoreData) >>= fun pAddr => + (rGPR rs) >>= fun rs_val => + (match width with + | B => (MEMw_wrapper pAddr 1 (subrange_vec_dec rs_val 7 0)) : M (unit) + | H => (MEMw_wrapper pAddr 2 (subrange_vec_dec rs_val 15 0)) : M (unit) + | W => (MEMw_wrapper pAddr 4 (subrange_vec_dec rs_val 31 0)) : M (unit) + | D => (MEMw_wrapper pAddr 8 rs_val) : M (unit) + end) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CSetOffset (cd : mword 5) (cb : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (rGPR rt) >>= fun rt_val => + (if ((andb cb_val.(Capability_tag) cb_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else + let '(success, newCap) := setCapOffset cb_val rt_val in + (if (success) then (writeCapReg cd newCap) : M (unit) + else + (writeCapReg cd (int_to_cap (add_vec (to_bits 64 (projT1 (getCapBase cb_val))) rt_val))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CSetCause (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (pcc_access_system_regs tt) >>= fun w__0 : bool => + (if ((negb w__0)) then (raise_c2_exception_noreg CapEx_AccessSystemRegsViolation) : M (unit) + else + (rGPR rt) >>= fun rt_val => + (_set_CapCauseReg_ExcCode CapCause_ref (subrange_vec_dec rt_val 15 8)) >> + (_set_CapCauseReg_RegNum CapCause_ref (subrange_vec_dec rt_val 7 0)) + : M (unit)) + : M (unit). + +Definition execute_CSetCID (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_set_CID))) then + (raise_c2_exception CapEx_PermitSetCIDViolation cb) + : M (unit) + else + let 'addr := projT1 (getCapCursor cb_val) in + (if sumbool_of_bool ((Z.ltb addr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.geb addr (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else write_reg CID_ref (to_bits 64 addr) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CSetBoundsImmediate (cd : mword 5) (cb : mword 5) (imm : mword 11) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + let 'immU := projT1 (uint imm) in + let 'cursor := projT1 (getCapCursor cb_val) in + let 'base := projT1 (getCapBase cb_val) in + let 'top := projT1 (getCapTop cb_val) in + let newTop := Z.add cursor immU in + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb cursor base)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.gtb newTop top)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else + let '(_, newCap) := setCapBounds cb_val (to_bits 64 cursor) (to_bits 65 newTop) in + (writeCapReg cd newCap) + : M (unit)) + : M (unit). + +Definition execute_CSetBoundsExact (cd : mword 5) (cb : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (rGPR rt) >>= fun w__0 : mword 64 => + let 'rt_val := projT1 (uint w__0) in + let 'cursor := projT1 (getCapCursor cb_val) in + let 'base := projT1 (getCapBase cb_val) in + let 'top := projT1 (getCapTop cb_val) in + let newTop := Z.add cursor rt_val in + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb cursor base)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.gtb newTop top)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else + let '(exact, newCap) := setCapBounds cb_val (to_bits 64 cursor) (to_bits 65 newTop) in + (if ((negb exact)) then (raise_c2_exception CapEx_InexactBounds cb) : M (unit) + else (writeCapReg cd newCap) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CSetBounds (cd : mword 5) (cb : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (rGPR rt) >>= fun w__0 : mword 64 => + let 'rt_val := projT1 (uint w__0) in + let 'cursor := projT1 (getCapCursor cb_val) in + let 'base := projT1 (getCapBase cb_val) in + let 'top := projT1 (getCapTop cb_val) in + let newTop := Z.add cursor rt_val in + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb cursor base)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.gtb newTop top)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else + let '(_, newCap) := setCapBounds cb_val (to_bits 64 cursor) (to_bits 65 newTop) in + (writeCapReg cd newCap) + : M (unit)) + : M (unit). + +Definition execute_CSeal (cd : mword 5) (cs : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (readCapReg ct) >>= fun ct_val => + let 'ct_cursor := projT1 (getCapCursor ct_val) in + let 'ct_top := projT1 (getCapTop ct_val) in + let 'ct_base := projT1 (getCapBase ct_val) in + (if ((negb cs_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cs) : M (unit) + else if ((negb ct_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation ct) + : M (unit) + else if (cs_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cs) + : M (unit) + else if (ct_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation ct) + : M (unit) + else if ((negb ct_val.(Capability_permit_seal))) then + (raise_c2_exception CapEx_PermitSealViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.ltb ct_cursor ct_base)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.geb ct_cursor ct_top)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.gtb ct_cursor max_otype)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else + let '(success, newCap) := sealCap cs_val (to_bits 24 ct_cursor) in + (if ((negb success)) then (raise_c2_exception CapEx_InexactBounds cs) : M (unit) + else (writeCapReg cd newCap) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CSCC (cs : mword 5) (cb : mword 5) (rd : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_store))) then + (raise_c2_exception CapEx_PermitStoreViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_store_cap))) then + (raise_c2_exception CapEx_PermitStoreCapViolation cb) + : M (unit) + else if ((andb (negb cb_val.(Capability_permit_store_local_cap)) + (andb cs_val.(Capability_tag) (negb cs_val.(Capability_global))))) then + (raise_c2_exception CapEx_PermitStoreLocalCapViolation cb) + : M (unit) + else + let 'vAddr := projT1 (getCapCursor cb_val) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr cap_size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((neq_int (projT1 (emod_with_eq vAddr cap_size)) 0)) then + (SignalExceptionBadAddr AdES vAddr64) + : M (unit) + else + (TLBTranslateC vAddr64 StoreData) >>= fun '(pAddr, noStoreCap) => + (if ((andb cs_val.(Capability_tag) noStoreCap)) then + (raise_c2_exception CapEx_TLBNoStoreCap cs) + : M (unit) + else + ((read_reg CP0LLBit_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__0 0)) : bool)) then + (MEMw_tagged_conditional pAddr cs_val.(Capability_tag) (capToMemBits cs_val)) + : M (bool) + else returnm (false : bool)) >>= fun success => + (wGPR rd (mips_zero_extend 64 (bool_to_bits success))) + : M (unit)) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CSC (cs : mword 5) (cb : mword 5) (rt : mword 5) (offset : mword 11) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_store))) then + (raise_c2_exception CapEx_PermitStoreViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_store_cap))) then + (raise_c2_exception CapEx_PermitStoreCapViolation cb) + : M (unit) + else if ((andb (negb cb_val.(Capability_permit_store_local_cap)) + (andb cs_val.(Capability_tag) (negb cs_val.(Capability_global))))) then + (raise_c2_exception CapEx_PermitStoreLocalCapViolation cb) + : M (unit) + else + let 'cursor := projT1 (getCapCursor cb_val) in + (rGPR rt) >>= fun w__0 : mword 64 => + let 'vAddr := + projT1 (emod_with_eq + (Z.add (Z.add cursor (projT1 (uint w__0))) (Z.mul 16 (projT1 (sint offset)))) + (projT1 (pow2 64))) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr cap_size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((neq_int (projT1 (emod_with_eq vAddr cap_size)) 0)) then + (SignalExceptionBadAddr AdES vAddr64) + : M (unit) + else + (TLBTranslateC vAddr64 StoreData) >>= fun '(pAddr, noStoreCap) => + (if ((andb cs_val.(Capability_tag) noStoreCap)) then + (raise_c2_exception CapEx_TLBNoStoreCap cs) + : M (unit) + else (MEMw_tagged pAddr cs_val.(Capability_tag) (capToMemBits cs_val)) : M (unit)) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CReturn '(tt : unit) +: M (unit) := + + (checkCP2usable tt) >> (raise_c2_exception_noreg CapEx_ReturnTrap) : M (unit). + +Definition execute_CReadHwr (cd : mword 5) (sel : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + let 'p0_ := projT1 (uint sel) in + (if sumbool_of_bool ((Z.eqb p0_ 0)) then returnm (false, false) + else if sumbool_of_bool ((Z.eqb p0_ 1)) then returnm (false, false) + else if sumbool_of_bool ((Z.eqb p0_ 8)) then returnm (false, true) + else if sumbool_of_bool ((Z.eqb p0_ 22)) then returnm (true, false) + else if sumbool_of_bool ((Z.eqb p0_ 23)) then returnm (true, false) + else if sumbool_of_bool ((Z.eqb p0_ 29)) then returnm (true, true) + else if sumbool_of_bool ((Z.eqb p0_ 30)) then returnm (true, true) + else if sumbool_of_bool ((Z.eqb p0_ 31)) then returnm (true, true) + else (SignalException ResI) : M ((bool * bool))) >>= fun '(needSup, needAccessSys) => + (and_boolM (returnm (needAccessSys : bool)) + ((pcc_access_system_regs tt) >>= fun w__8 : bool => returnm ((negb w__8) : bool))) >>= fun w__9 : bool => + (if (w__9) then (raise_c2_exception CapEx_AccessSystemRegsViolation sel) : M (unit) + else + (and_boolM (returnm (needSup : bool)) + ((getAccessLevel tt) >>= fun w__10 : AccessLevel => + returnm ((negb (grantsAccess w__10 Supervisor)) + : bool))) >>= fun w__11 : bool => + (if (w__11) then (raise_c2_exception CapEx_AccessSystemRegsViolation sel) : M (unit) + else + let 'p0_ := projT1 (uint sel) in + (if sumbool_of_bool ((Z.eqb p0_ 0)) then read_reg DDC_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 1)) then read_reg CTLSU_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 8)) then read_reg CTLSP_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 22)) then read_reg KR1C_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 23)) then read_reg KR2C_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 29)) then read_reg KCC_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 30)) then read_reg KDC_ref : M (Capability) + else if sumbool_of_bool ((Z.eqb p0_ 31)) then (readEPCC tt) : M (Capability) + else + assert_exp' false "CReadHwr: should be unreachable code" >>= fun _ => + (undefined_Capability tt) + : M (Capability)) >>= fun capVal : Capability => + (writeCapReg cd capVal) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CPtrCmp (rd : mword 5) (cb : mword 5) (ct : mword 5) (op : CPtrCmpOp) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (readCapReg ct) >>= fun ct_val => + let equal := false in + let ltu := false in + let lts := false in + let '(equal, lts, ltu) := + (if ((neq_bool cb_val.(Capability_tag) ct_val.(Capability_tag))) then + let '(lts, ltu) := + (if ((negb cb_val.(Capability_tag))) then + let ltu : bool := true in + let lts : bool := true in + (lts, ltu) + else (lts, ltu)) + : (bool * bool) in + (equal, lts, ltu) + else + let 'cursor1 := projT1 (getCapCursor cb_val) in + let 'cursor2 := projT1 (getCapCursor ct_val) in + let equal : bool := Z.eqb cursor1 cursor2 in + let ltu : bool := Z.ltb cursor1 cursor2 in + let lts : bool := zopz0zI_s (to_bits 64 cursor1) (to_bits 64 cursor2) in + (equal, lts, ltu)) + : (bool * bool * bool) in + let cmp : bool := + match op with + | CEQ => equal + | CNE => negb equal + | CLT => lts + | CLE => orb lts equal + | CLTU => ltu + | CLEU => orb ltu equal + | CEXEQ => generic_eq cb_val ct_val + | CNEXEQ => generic_neq cb_val ct_val + end in + (wGPR rd (mips_zero_extend 64 (bool_to_bits cmp))) + : M (unit). + +Definition execute_CMOVX (cd : mword 5) (cb : mword 5) (rt : mword 5) (ismovn : bool) +: M (unit) := + + (checkCP2usable tt) >> + (rGPR rt) >>= fun w__0 : mword 64 => + (if (((bits_to_bool + (xor_vec (bool_to_bits (eq_vec w__0 (zeros_implicit 64 tt))) + ((bool_to_bits ismovn) + : mword 1))) + : bool)) then + (readCapReg cb) >>= fun w__1 : Capability => (writeCapReg cd w__1) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_CLoadTags (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load_cap))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else + let 'vAddr := projT1 (getCapCursor cb_val) in + let vAddr64 := to_bits 64 (projT1 (getCapCursor cb_val)) in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr (Z.mul 8 cap_size)) (projT1 (getCapTop cb_val)))) + then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((negb + (eq_vec (subrange_vec_dec vAddr64 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + (SignalExceptionBadAddr AdEL vAddr64) + : M (unit) + else + (TLBTranslate vAddr64 LoadData) >>= fun pAddr => + (read_tag_bool (add_vec_int pAddr (Z.mul 0 cap_size))) >>= fun tag0 => + (read_tag_bool (add_vec_int pAddr (Z.mul 1 cap_size))) >>= fun tag1 => + (read_tag_bool (add_vec_int pAddr (Z.mul 2 cap_size))) >>= fun tag2 => + (read_tag_bool (add_vec_int pAddr (Z.mul 3 cap_size))) >>= fun tag3 => + (read_tag_bool (add_vec_int pAddr (Z.mul 4 cap_size))) >>= fun tag4 => + (read_tag_bool (add_vec_int pAddr (Z.mul 5 cap_size))) >>= fun tag5 => + (read_tag_bool (add_vec_int pAddr (Z.mul 6 cap_size))) >>= fun tag6 => + (read_tag_bool (add_vec_int pAddr (Z.mul 7 cap_size))) >>= fun tag7 => + (wGPR rd + (mips_zero_extend 64 + (concat_vec (bool_to_bits tag7) + (concat_vec (bool_to_bits tag6) + (concat_vec (bool_to_bits tag5) + (concat_vec (bool_to_bits tag4) + (concat_vec (bool_to_bits tag3) + (concat_vec (bool_to_bits tag2) + (concat_vec (bool_to_bits tag1) (bool_to_bits tag0)))))))))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CLoadLinked (rd : mword 5) (cb : mword 5) (signext : bool) (width : WordType) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else + let 'size := projT1 (wordWidthBytes width) in + let 'vAddr := projT1 (getCapCursor cb_val) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((negb (isAddressAligned vAddr64 width))) then + (SignalExceptionBadAddr AdEL vAddr64) + : M (unit) + else + (TLBTranslate vAddr64 LoadData) >>= fun pAddr => + (MEMr_reserve_wrapper pAddr size) >>= fun w__0 : mword (8 * size) => + let memResult : bits 64 := extendLoad w__0 signext in + write_reg CP0LLBit_ref (vec_of_bits [B1] : mword 1) >> + write_reg CP0LLAddr_ref pAddr >> (wGPR rd memResult) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CLoad +(rd : mword 5) (cb : mword 5) (rt : mword 5) (offset : mword 8) (signext : bool) (width : WordType) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else + let 'size := projT1 (wordWidthBytes width) in + let 'cursor := projT1 (getCapCursor cb_val) in + (rGPR rt) >>= fun w__0 : mword 64 => + let 'vAddr := + projT1 (emod_with_eq + (Z.add (Z.add cursor (projT1 (uint w__0))) (Z.mul size (projT1 (sint offset)))) + (projT1 (pow2 64))) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((negb (isAddressAligned vAddr64 width))) then + (SignalExceptionBadAddr AdEL vAddr64) + : M (unit) + else + (TLBTranslate vAddr64 LoadData) >>= fun pAddr => + (MEMr_wrapper pAddr size) >>= fun w__1 : mword (8 * size) => + let memResult : bits 64 := extendLoad w__1 signext in + (wGPR rd memResult) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CLLC (cd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else + let 'vAddr := projT1 (getCapCursor cb_val) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr cap_size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((neq_int (projT1 (emod_with_eq vAddr cap_size)) 0)) then + (SignalExceptionBadAddr AdEL vAddr64) + : M (unit) + else + (TLBTranslateC vAddr64 LoadData) >>= fun '(pAddr, suppressTag) => + (MEMr_tagged_reserve pAddr) >>= fun '(tag, mem) => + let cap := + memBitsToCapability + (andb tag (andb cb_val.(Capability_permit_load_cap) (negb suppressTag))) mem in + (writeCapReg cd cap) >> + write_reg CP0LLBit_ref (vec_of_bits [B1] : mword 1) >> + write_reg CP0LLAddr_ref pAddr + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CLCBI (cd : mword 5) (cb : mword 5) (offset : mword 16) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else + let 'cursor := projT1 (getCapCursor cb_val) in + let 'vAddr := + projT1 (emod_with_eq (Z.add cursor (Z.mul 16 (projT1 (sint offset)))) (projT1 (pow2 64))) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr cap_size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((neq_int (projT1 (emod_with_eq vAddr cap_size)) 0)) then + (SignalExceptionBadAddr AdEL vAddr64) + : M (unit) + else + (TLBTranslateC vAddr64 LoadData) >>= fun '(pAddr, suppressTag) => + (MEMr_tagged pAddr) >>= fun '(tag, mem) => + let cap := + memBitsToCapability + (andb tag (andb cb_val.(Capability_permit_load_cap) (negb suppressTag))) mem in + (writeCapReg cd cap) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CLC (cd : mword 5) (cb : mword 5) (rt : mword 5) (offset : mword 11) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_load))) then + (raise_c2_exception CapEx_PermitLoadViolation cb) + : M (unit) + else + let 'cursor := projT1 (getCapCursor cb_val) in + (rGPR rt) >>= fun w__0 : mword 64 => + let 'vAddr := + projT1 (emod_with_eq + (Z.add (Z.add cursor (projT1 (uint w__0))) (Z.mul 16 (projT1 (sint offset)))) + (projT1 (pow2 64))) in + let vAddr64 := to_bits 64 vAddr in + (if sumbool_of_bool ((Z.gtb (Z.add vAddr cap_size) (projT1 (getCapTop cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb vAddr (projT1 (getCapBase cb_val)))) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((neq_int (projT1 (emod_with_eq vAddr cap_size)) 0)) then + (SignalExceptionBadAddr AdEL vAddr64) + : M (unit) + else + (TLBTranslateC vAddr64 LoadData) >>= fun '(pAddr, suppressTag) => + (MEMr_tagged pAddr) >>= fun '(tag, mem) => + let cap := + memBitsToCapability + (andb tag (andb cb_val.(Capability_permit_load_cap) (negb suppressTag))) mem in + (writeCapReg cd cap) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CJALR (cd : mword 5) (cb : mword 5) (link : bool) +: M (unit) := + + (checkCP2usable tt) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (readCapReg cb) >>= fun cb_val => + let 'cb_ptr := projT1 (getCapCursor cb_val) in + let 'cb_top := projT1 (getCapTop cb_val) in + let 'cb_base := projT1 (getCapBase cb_val) in + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((negb cb_val.(Capability_permit_execute))) then + (raise_c2_exception CapEx_PermitExecuteViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb cb_ptr cb_base)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.gtb (Z.add cb_ptr 4) cb_top)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if ((neq_int (projT1 (emod_with_eq cb_ptr 4)) 0)) then (SignalException AdEL) : M (unit) + else + (if (link) then + read_reg PCC_ref >>= fun w__1 : Capability => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + let '(success, linkCap) := setCapOffset w__1 (add_vec_int w__2 8) in + assert_exp' success "Link cap should always be representable." >>= fun _ => + (writeCapReg cd linkCap) + : M (unit) + else returnm (tt : unit)) >> + (execute_branch_pcc cb_val) + : M (unit)) >> + write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) + : M (unit). + +Definition execute_CIncOffsetImmediate (cd : mword 5) (cb : mword 5) (imm : mword 11) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + let imm64 : bits 64 := mips_sign_extend 64 imm in + (if ((andb cb_val.(Capability_tag) cb_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else + let '(success, newCap) := incCapOffset cb_val imm64 in + (if (success) then (writeCapReg cd newCap) : M (unit) + else + (writeCapReg cd (int_to_cap (add_vec (to_bits 64 (projT1 (getCapBase cb_val))) imm64))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CIncOffset (cd : mword 5) (cb : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (rGPR rt) >>= fun rt_val => + (if ((andb cb_val.(Capability_tag) + (andb cb_val.(Capability_sealed) + (neq_vec rt_val + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else + let '(success, newCap) := incCapOffset cb_val rt_val in + (if (success) then (writeCapReg cd newCap) : M (unit) + else + (writeCapReg cd (int_to_cap (add_vec (to_bits 64 (projT1 (getCapBase cb_val))) rt_val))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CGetType (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + (wGPR rd + (if (capVal.(Capability_sealed)) then mips_zero_extend 64 capVal.(Capability_otype) + else + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : mword 64))) + : M (unit). + +Definition execute_CGetTag (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + (wGPR rd (mips_zero_extend 64 (bool_to_bits capVal.(Capability_tag)))) + : M (unit). + +Definition execute_CGetSealed (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + (wGPR rd (mips_zero_extend 64 (bool_to_bits capVal.(Capability_sealed)))) + : M (unit). + +Definition execute_CGetPerm (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + (wGPR rd (mips_zero_extend 64 (getCapPerms capVal))) + : M (unit). + +Definition execute_CGetPCCSetOffset (cd : mword 5) (rs : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (rGPR rs) >>= fun rs_val => + read_reg PCC_ref >>= fun w__0 : Capability => + let '(success, newPCC) := setCapOffset w__0 rs_val in + (if (success) then (writeCapReg cd newPCC) : M (unit) + else (writeCapReg cd (int_to_cap rs_val)) : M (unit)) + : M (unit). + +Definition execute_CGetPCC (cd : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + read_reg PCC_ref >>= fun w__0 : Capability => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + let '(success, pcc) := setCapOffset w__0 w__1 in + assert_exp' success "PCC with offset PC should always be representable" >>= fun _ => + (writeCapReg cd pcc) + : M (unit). + +Definition execute_CGetOffset (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + (wGPR rd (to_bits 64 (projT1 (getCapOffset capVal)))) + : M (unit). + +Definition execute_CGetLen (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + let 'len65 := projT1 (getCapLength capVal) in + (wGPR rd (to_bits 64 (if sumbool_of_bool ((Z.gtb len65 MAX_U64)) then MAX_U64 else len65))) + : M (unit). + +Definition execute_CGetCause (rd : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (pcc_access_system_regs tt) >>= fun w__0 : bool => + (if ((negb w__0)) then (raise_c2_exception_noreg CapEx_AccessSystemRegsViolation) : M (unit) + else + read_reg CapCause_ref >>= fun w__1 : CapCauseReg => + (wGPR rd (mips_zero_extend 64 (_get_CapCauseReg_bits w__1))) + : M (unit)) + : M (unit). + +Definition execute_CGetCID (rd : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + ((read_reg CID_ref) : M (mword 64)) >>= fun w__0 : bits 64 => (wGPR rd w__0) : M (unit). + +Definition execute_CGetBase (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => (wGPR rd (to_bits 64 (projT1 (getCapBase capVal)))) : M (unit). + +Definition execute_CGetAddr (rd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun capVal => + (wGPR rd (to_bits 64 (projT1 (getCapCursor capVal)))) + : M (unit). + +Definition execute_CFromPtr (cd : mword 5) (cb : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (rGPR rt) >>= fun rt_val => + (if ((eq_vec rt_val + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64))) then + (writeCapReg cd null_cap) + : M (unit) + else if ((negb cb_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation cb) + : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else + let '(success, newCap) := setCapOffset cb_val rt_val in + (if (success) then (writeCapReg cd newCap) : M (unit) + else + (writeCapReg cd (int_to_cap (add_vec (to_bits 64 (projT1 (getCapBase cb_val))) rt_val))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CCopyType (cd : mword 5) (cb : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (readCapReg ct) >>= fun ct_val => + let 'cb_base := projT1 (getCapBase cb_val) in + let 'cb_top := projT1 (getCapTop cb_val) in + let 'ct_otype := projT1 (uint ct_val.(Capability_otype)) in + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if (ct_val.(Capability_sealed)) then + (if sumbool_of_bool ((Z.ltb ct_otype cb_base)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.geb ct_otype cb_top)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else + let '(success, cap) := setCapOffset cb_val (to_bits 64 (Z.sub ct_otype cb_base)) in + assert_exp' success "CopyType: offset is in bounds so should be representable" >>= fun _ => + (writeCapReg cd cap) + : M (unit)) + : M (unit) + else + (writeCapReg cd + (int_to_cap + (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; + B1] + : mword 64))) + : M (unit)) + : M (unit). + +Definition execute_CClearTag (cd : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (writeCapReg cd {[ cb_val with Capability_tag := false ]}) + : M (unit). + +Definition execute_CCheckType (cs : mword 5) (cb : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (readCapReg cb) >>= fun cb_val => + (if ((negb cs_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cs) : M (unit) + else if ((negb cb_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation cb) + : M (unit) + else if ((negb cs_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cs) + : M (unit) + else if ((negb cb_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((neq_vec cs_val.(Capability_otype) cb_val.(Capability_otype))) then + (raise_c2_exception CapEx_TypeViolation cs) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_CCheckTag (cs : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (if ((negb cs_val.(Capability_tag))) then (raise_c2_exception CapEx_TypeViolation cs) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_CCheckPerm (cs : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + let cs_perms : bits 64 := mips_zero_extend 64 (getCapPerms cs_val) in + (rGPR rt) >>= fun rt_perms => + (if ((negb cs_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cs) : M (unit) + else if ((neq_vec (and_vec cs_perms rt_perms) rt_perms)) then + (raise_c2_exception CapEx_UserDefViolation cs) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_CCall (cs : mword 5) (cb : mword 5) (b__155 : mword 11) +: M (unit) := + + (if ((eq_vec b__155 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11))) then + (checkCP2usable tt) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (readCapReg cs) >>= fun cs_val => + (readCapReg cb) >>= fun cb_val => + let 'cs_cursor := projT1 (getCapCursor cs_val) in + (if ((negb cs_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation cs) + : M (unit) + else if ((negb cb_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation cb) + : M (unit) + else if ((negb cs_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cs) + : M (unit) + else if ((negb cb_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((neq_vec cs_val.(Capability_otype) cb_val.(Capability_otype))) then + (raise_c2_exception CapEx_TypeViolation cs) + : M (unit) + else if ((negb cs_val.(Capability_permit_execute))) then + (raise_c2_exception CapEx_PermitExecuteViolation cs) + : M (unit) + else if (cb_val.(Capability_permit_execute)) then + (raise_c2_exception CapEx_PermitExecuteViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb cs_cursor (projT1 (getCapBase cs_val)))) then + (raise_c2_exception CapEx_LengthViolation cs) + : M (unit) + else if sumbool_of_bool ((Z.geb cs_cursor (projT1 (getCapTop cs_val)))) then + (raise_c2_exception CapEx_LengthViolation cs) + : M (unit) + else (raise_c2_exception CapEx_CallTrap cs) : M (unit)) + : M (unit) + else + (checkCP2usable tt) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + (if (((bits_to_bool w__1) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (readCapReg cs) >>= fun cs_val => + (readCapReg cb) >>= fun cb_val => + let 'cs_cursor := projT1 (getCapCursor cs_val) in + (if ((negb cs_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation cs) + : M (unit) + else if ((negb cb_val.(Capability_tag))) then + (raise_c2_exception CapEx_TagViolation cb) + : M (unit) + else if ((negb cs_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cs) + : M (unit) + else if ((negb cb_val.(Capability_sealed))) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if ((neq_vec cs_val.(Capability_otype) cb_val.(Capability_otype))) then + (raise_c2_exception CapEx_TypeViolation cs) + : M (unit) + else if ((negb cs_val.(Capability_permit_ccall))) then + (raise_c2_exception CapEx_PermitCCallViolation cs) + : M (unit) + else if ((negb cb_val.(Capability_permit_ccall))) then + (raise_c2_exception CapEx_PermitCCallViolation cb) + : M (unit) + else if ((negb cs_val.(Capability_permit_execute))) then + (raise_c2_exception CapEx_PermitExecuteViolation cs) + : M (unit) + else if (cb_val.(Capability_permit_execute)) then + (raise_c2_exception CapEx_PermitExecuteViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb cs_cursor (projT1 (getCapBase cs_val)))) then + (raise_c2_exception CapEx_LengthViolation cs) + : M (unit) + else if sumbool_of_bool ((Z.geb cs_cursor (projT1 (getCapTop cs_val)))) then + (raise_c2_exception CapEx_LengthViolation cs) + : M (unit) + else + (set_next_pcc + {| Capability_tag := cs_val.(Capability_tag); + Capability_padding := cs_val.(Capability_padding); + Capability_otype := (zeros_implicit 24 tt); + Capability_uperms := cs_val.(Capability_uperms); + Capability_perm_reserved12_14 := cs_val.(Capability_perm_reserved12_14); + Capability_permit_set_CID := cs_val.(Capability_permit_set_CID); + Capability_access_system_regs := cs_val.(Capability_access_system_regs); + Capability_permit_unseal := cs_val.(Capability_permit_unseal); + Capability_permit_ccall := cs_val.(Capability_permit_ccall); + Capability_permit_seal := cs_val.(Capability_permit_seal); + Capability_permit_store_local_cap := cs_val.(Capability_permit_store_local_cap); + Capability_permit_store_cap := cs_val.(Capability_permit_store_cap); + Capability_permit_load_cap := cs_val.(Capability_permit_load_cap); + Capability_permit_store := cs_val.(Capability_permit_store); + Capability_permit_load := cs_val.(Capability_permit_load); + Capability_permit_execute := cs_val.(Capability_permit_execute); + Capability_global := cs_val.(Capability_global); + Capability_sealed := false; + Capability_address := cs_val.(Capability_address); + Capability_base := cs_val.(Capability_base); + Capability_length := cs_val.(Capability_length) |}) >> + write_reg + C26_ref + {| Capability_tag := cb_val.(Capability_tag); + Capability_padding := cb_val.(Capability_padding); + Capability_otype := (zeros_implicit 24 tt); + Capability_uperms := cb_val.(Capability_uperms); + Capability_perm_reserved12_14 := cb_val.(Capability_perm_reserved12_14); + Capability_permit_set_CID := cb_val.(Capability_permit_set_CID); + Capability_access_system_regs := cb_val.(Capability_access_system_regs); + Capability_permit_unseal := cb_val.(Capability_permit_unseal); + Capability_permit_ccall := cb_val.(Capability_permit_ccall); + Capability_permit_seal := cb_val.(Capability_permit_seal); + Capability_permit_store_local_cap := cb_val.(Capability_permit_store_local_cap); + Capability_permit_store_cap := cb_val.(Capability_permit_store_cap); + Capability_permit_load_cap := cb_val.(Capability_permit_load_cap); + Capability_permit_store := cb_val.(Capability_permit_store); + Capability_permit_load := cb_val.(Capability_permit_load); + Capability_permit_execute := cb_val.(Capability_permit_execute); + Capability_global := cb_val.(Capability_global); + Capability_sealed := false; + Capability_address := cb_val.(Capability_address); + Capability_base := cb_val.(Capability_base); + Capability_length := cb_val.(Capability_length) |} >> + write_reg NextPC_ref (to_bits 64 (projT1 (getCapOffset cs_val))) + : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CCSeal (cd : mword 5) (cs : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cs) >>= fun cs_val => + (readCapReg ct) >>= fun ct_val => + let 'ct_cursor := projT1 (getCapCursor ct_val) in + let 'ct_top := projT1 (getCapTop ct_val) in + let 'ct_base := projT1 (getCapBase ct_val) in + (if ((negb cs_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cs) : M (unit) + else if sumbool_of_bool ((orb (negb ct_val.(Capability_tag)) + (Z.eqb (projT1 (getCapCursor ct_val)) MAX_U64))) then + (writeCapReg cd cs_val) + : M (unit) + else if (cs_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cs) + : M (unit) + else if (ct_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation ct) + : M (unit) + else if ((negb ct_val.(Capability_permit_seal))) then + (raise_c2_exception CapEx_PermitSealViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.ltb ct_cursor ct_base)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.geb ct_cursor ct_top)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else if sumbool_of_bool ((Z.gtb ct_cursor max_otype)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else + let '(success, newCap) := sealCap cs_val (to_bits 24 ct_cursor) in + (if ((negb success)) then (raise_c2_exception CapEx_InexactBounds cs) : M (unit) + else (writeCapReg cd newCap) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_CBuildCap (cd : mword 5) (cb : mword 5) (ct : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapRegDDC cb) >>= fun cb_val => + (readCapReg ct) >>= fun ct_val => + let 'cb_base := projT1 (getCapBase cb_val) in + let 'ct_base := projT1 (getCapBase ct_val) in + let 'cb_top := projT1 (getCapTop cb_val) in + let 'ct_top := projT1 (getCapTop ct_val) in + let cb_perms := getCapPerms cb_val in + let ct_perms := getCapPerms ct_val in + let 'ct_offset := projT1 (getCapOffset ct_val) in + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.ltb ct_base cb_base)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.gtb ct_top cb_top)) then + (raise_c2_exception CapEx_LengthViolation cb) + : M (unit) + else if sumbool_of_bool ((Z.gtb ct_base ct_top)) then + (raise_c2_exception CapEx_LengthViolation ct) + : M (unit) + else if ((neq_vec (and_vec ct_perms cb_perms) ct_perms)) then + (raise_c2_exception CapEx_UserDefViolation cb) + : M (unit) + else + let '(exact, cd1) := setCapBounds cb_val (to_bits 64 ct_base) (to_bits 65 ct_top) in + let '(representable, cd2) := setCapOffset cd1 (to_bits 64 ct_offset) in + let cd3 := setCapPerms cd2 ct_perms in + assert_exp' exact "CBuildCap: setCapBounds was not exact" >>= fun _ => + assert_exp' representable "CBuildCap: offset was not representable" >>= fun _ => + (writeCapReg cd cd3) + : M (unit)) + : M (unit). + +Definition execute_CBZ (cb : mword 5) (imm : mword 16) (notzero : bool) +: M (unit) := + + (checkCP2usable tt) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (readCapReg cb) >>= fun cb_val => + (if (((bits_to_bool + (xor_vec (bool_to_bits (generic_eq cb_val null_cap)) ((bool_to_bits notzero) : mword 1))) + : bool)) then + let offset : bits 64 := + add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + (execute_branch (add_vec w__1 offset)) + : M (unit) + else returnm (tt : unit)) >> + write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) + : M (unit). + +Definition execute_CBX (cb : mword 5) (imm : mword 16) (notset : bool) +: M (unit) := + + (checkCP2usable tt) >> + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (readCapReg cb) >>= fun cb_val => + (if (((bits_to_bool + (xor_vec (bool_to_bits cb_val.(Capability_tag)) ((bool_to_bits notset) : mword 1))) + : bool)) then + let offset : bits 64 := + add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + (execute_branch (add_vec w__1 offset)) + : M (unit) + else returnm (tt : unit)) >> + write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) + : M (unit). + +Definition execute_CAndPerm (cd : mword 5) (cb : mword 5) (rt : mword 5) +: M (unit) := + + (checkCP2usable tt) >> + (readCapReg cb) >>= fun cb_val => + (rGPR rt) >>= fun rt_val => + (if ((negb cb_val.(Capability_tag))) then (raise_c2_exception CapEx_TagViolation cb) : M (unit) + else if (cb_val.(Capability_sealed)) then + (raise_c2_exception CapEx_SealViolation cb) + : M (unit) + else + let perms := getCapPerms cb_val in + let newCap := setCapPerms cb_val (and_vec perms (subrange_vec_dec rt_val 30 0)) in + (writeCapReg cd newCap) + : M (unit)) + : M (unit). + +Definition execute_CACHE (base : mword 5) (op : mword 5) (imm : mword 16) +: M (unit) := + + (checkCP0Access tt) + : M (unit). + +Definition execute_C2Dump (rt : mword 5) : unit := tt. + +Definition execute_BREAK '(tt : unit) : M (unit) := (SignalException Bp) : M (unit). + +Definition execute_BEQ (rs : mword 5) (rd : mword 5) (imm : mword 16) (ne : bool) (likely : bool) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (rGPR rs) >>= fun w__1 : mword 64 => + (rGPR rd) >>= fun w__2 : mword 64 => + (if (((bits_to_bool (xor_vec (bool_to_bits (eq_vec w__1 w__2)) ((bool_to_bits ne) : mword 1))) + : bool)) then + let offset : bits 64 := + add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : bits 64 => + (execute_branch (add_vec w__3 offset)) + : M (unit) + else if (likely) then + ((read_reg PC_ref) : M (mword 64)) >>= fun w__4 : bits 64 => + write_reg NextPC_ref (add_vec_int w__4 8) + : M (unit) + else write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) : M (unit)) + : M (unit). + +Definition execute_BCMPZ +(rs : mword 5) (imm : mword 16) (cmp : Comparison) (link : bool) (likely : bool) +: M (unit) := + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + let linkVal := add_vec_int w__1 8 in + (rGPR rs) >>= fun regVal => + let condition := compare cmp regVal (mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) in + (if (condition) then + let offset : bits 64 := + add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + (execute_branch (add_vec w__2 offset)) + : M (unit) + else if (likely) then + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : bits 64 => + write_reg NextPC_ref (add_vec_int w__3 8) + : M (unit) + else write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) : M (unit)) >> + (if (link) then (wGPR (vec_of_bits [B1;B1;B1;B1;B1] : mword 5) linkVal) : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition execute_ANDI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (and_vec w__0 (mips_zero_extend 64 imm))) + : M (unit). + +Definition execute_AND (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (and_vec w__0 w__1)) : M (unit). + +Definition execute_ADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun opA => + (rGPR rt) >>= fun opB => + (if ((orb (NotWordVal opA) (NotWordVal opB))) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + (wGPR rd + (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0)))) + : M (unit)) + : M (unit). + +Definition execute_ADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun opA => + (if ((NotWordVal opA)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rt w__0) : M (unit) + else + (wGPR rt (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (mips_sign_extend 32 imm)))) + : M (unit)) + : M (unit). + +Definition execute_ADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) +: M (unit) := + + (rGPR rs) >>= fun opA => + (if ((NotWordVal opA)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rt w__0) : M (unit) + else + let sum33 : bits 33 := + add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) (mips_sign_extend 33 imm) in + (if ((neq_bool ((bit_to_bool (access_vec_dec sum33 32)) : bool) + ((bit_to_bool (access_vec_dec sum33 31)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rt (mips_sign_extend 64 (subrange_vec_dec sum33 31 0))) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute_ADD (rs : mword 5) (rt : mword 5) (rd : mword 5) +: M (unit) := + + (rGPR rs) >>= fun opA : bits 64 => + (rGPR rt) >>= fun opB : bits 64 => + (if ((orb (NotWordVal opA) (NotWordVal opB))) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) + else + let sum33 : bits 33 := + add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) + (mips_sign_extend 33 (subrange_vec_dec opB 31 0)) in + (if ((neq_bool ((bit_to_bool (access_vec_dec sum33 32)) : bool) + ((bit_to_bool (access_vec_dec sum33 31)) + : bool))) then + (SignalException Ov) + : M (unit) + else (wGPR rd (mips_sign_extend 64 (subrange_vec_dec sum33 31 0))) : M (unit)) + : M (unit)) + : M (unit). + +Definition execute (merge_var : ast) +: M (unit) := + + (match merge_var with + | DADDIU (rs,rt,imm) => (execute_DADDIU rs rt imm) : M (unit) + | DADDU (rs,rt,rd) => (execute_DADDU rs rt rd) : M (unit) + | DADDI (rs,rt,imm) => (execute_DADDI rs rt imm) : M (unit) + | DADD (rs,rt,rd) => (execute_DADD rs rt rd) : M (unit) + | ADD (rs,rt,rd) => (execute_ADD rs rt rd) : M (unit) + | ADDI (rs,rt,imm) => (execute_ADDI rs rt imm) : M (unit) + | ADDU (rs,rt,rd) => (execute_ADDU rs rt rd) : M (unit) + | ADDIU (rs,rt,imm) => (execute_ADDIU rs rt imm) : M (unit) + | DSUBU (rs,rt,rd) => (execute_DSUBU rs rt rd) : M (unit) + | DSUB (rs,rt,rd) => (execute_DSUB rs rt rd) : M (unit) + | SUB (rs,rt,rd) => (execute_SUB rs rt rd) : M (unit) + | SUBU (rs,rt,rd) => (execute_SUBU rs rt rd) : M (unit) + | AND (rs,rt,rd) => (execute_AND rs rt rd) : M (unit) + | ANDI (rs,rt,imm) => (execute_ANDI rs rt imm) : M (unit) + | OR (rs,rt,rd) => (execute_OR rs rt rd) : M (unit) + | ORI (rs,rt,imm) => (execute_ORI rs rt imm) : M (unit) + | NOR (rs,rt,rd) => (execute_NOR rs rt rd) : M (unit) + | XOR (rs,rt,rd) => (execute_XOR rs rt rd) : M (unit) + | XORI (rs,rt,imm) => (execute_XORI rs rt imm) : M (unit) + | LUI (rt,imm) => (execute_LUI rt imm) : M (unit) + | DSLL (rt,rd,sa) => (execute_DSLL rt rd sa) : M (unit) + | DSLL32 (rt,rd,sa) => (execute_DSLL32 rt rd sa) : M (unit) + | DSLLV (rs,rt,rd) => (execute_DSLLV rs rt rd) : M (unit) + | DSRA (rt,rd,sa) => (execute_DSRA rt rd sa) : M (unit) + | DSRA32 (rt,rd,sa) => (execute_DSRA32 rt rd sa) : M (unit) + | DSRAV (rs,rt,rd) => (execute_DSRAV rs rt rd) : M (unit) + | DSRL (rt,rd,sa) => (execute_DSRL rt rd sa) : M (unit) + | DSRL32 (rt,rd,sa) => (execute_DSRL32 rt rd sa) : M (unit) + | DSRLV (rs,rt,rd) => (execute_DSRLV rs rt rd) : M (unit) + | SLL (rt,rd,sa) => (execute_SLL rt rd sa) : M (unit) + | SLLV (rs,rt,rd) => (execute_SLLV rs rt rd) : M (unit) + | SRA (rt,rd,sa) => (execute_SRA rt rd sa) : M (unit) + | SRAV (rs,rt,rd) => (execute_SRAV rs rt rd) : M (unit) + | SRL (rt,rd,sa) => (execute_SRL rt rd sa) : M (unit) + | SRLV (rs,rt,rd) => (execute_SRLV rs rt rd) : M (unit) + | SLT (rs,rt,rd) => (execute_SLT rs rt rd) : M (unit) + | SLTI (rs,rt,imm) => (execute_SLTI rs rt imm) : M (unit) + | SLTU (rs,rt,rd) => (execute_SLTU rs rt rd) : M (unit) + | SLTIU (rs,rt,imm) => (execute_SLTIU rs rt imm) : M (unit) + | MOVN (rs,rt,rd) => (execute_MOVN rs rt rd) : M (unit) + | MOVZ (rs,rt,rd) => (execute_MOVZ rs rt rd) : M (unit) + | MFHI (rd) => (execute_MFHI rd) : M (unit) + | MFLO (rd) => (execute_MFLO rd) : M (unit) + | MTHI (rs) => (execute_MTHI rs) : M (unit) + | MTLO (rs) => (execute_MTLO rs) : M (unit) + | MUL (rs,rt,rd) => (execute_MUL rs rt rd) : M (unit) + | MULT (rs,rt) => (execute_MULT rs rt) : M (unit) + | MULTU (rs,rt) => (execute_MULTU rs rt) : M (unit) + | DMULT (rs,rt) => (execute_DMULT rs rt) : M (unit) + | DMULTU (rs,rt) => (execute_DMULTU rs rt) : M (unit) + | MADD (rs,rt) => (execute_MADD rs rt) : M (unit) + | MADDU (rs,rt) => (execute_MADDU rs rt) : M (unit) + | MSUB (rs,rt) => (execute_MSUB rs rt) : M (unit) + | MSUBU (rs,rt) => (execute_MSUBU rs rt) : M (unit) + | DIV (rs,rt) => (execute_DIV rs rt) : M (unit) + | DIVU (rs,rt) => (execute_DIVU rs rt) : M (unit) + | DDIV (rs,rt) => (execute_DDIV rs rt) : M (unit) + | DDIVU (rs,rt) => (execute_DDIVU rs rt) : M (unit) + | J (offset) => (execute_J offset) : M (unit) + | JAL (offset) => (execute_JAL offset) : M (unit) + | JR (rs) => (execute_JR rs) : M (unit) + | JALR (rs,rd) => (execute_JALR rs rd) : M (unit) + | BEQ (rs,rd,imm,ne,likely) => (execute_BEQ rs rd imm ne likely) : M (unit) + | BCMPZ (rs,imm,cmp,link,likely) => (execute_BCMPZ rs imm cmp link likely) : M (unit) + | SYSCALL (arg0) => (execute_SYSCALL arg0) : M (unit) + | BREAK (arg0) => (execute_BREAK arg0) : M (unit) + | WAIT (arg0) => (execute_WAIT arg0) : M (unit) + | TRAPREG (rs,rt,cmp) => (execute_TRAPREG rs rt cmp) : M (unit) + | TRAPIMM (rs,imm,cmp) => (execute_TRAPIMM rs imm cmp) : M (unit) + | Load (width,sign,linked,base,rt,offset) => + (execute_Load width sign linked base rt offset) : M (unit) + | Store (width,conditional,base,rt,offset) => + (execute_Store width conditional base rt offset) : M (unit) + | LWL (base,rt,offset) => (execute_LWL base rt offset) : M (unit) + | LWR (base,rt,offset) => (execute_LWR base rt offset) : M (unit) + | SWL (base,rt,offset) => (execute_SWL base rt offset) : M (unit) + | SWR (base,rt,offset) => (execute_SWR base rt offset) : M (unit) + | LDL (base,rt,offset) => (execute_LDL base rt offset) : M (unit) + | LDR (base,rt,offset) => (execute_LDR base rt offset) : M (unit) + | SDL (base,rt,offset) => (execute_SDL base rt offset) : M (unit) + | SDR (base,rt,offset) => (execute_SDR base rt offset) : M (unit) + | CACHE (base,op,imm) => (execute_CACHE base op imm) : M (unit) + | SYNC (arg0) => (execute_SYNC arg0) : M (unit) + | MFC0 (rt,rd,sel,double) => (execute_MFC0 rt rd sel double) : M (unit) + | HCF (arg0) => returnm ((execute_HCF arg0) : unit) + | MTC0 (rt,rd,sel,double) => (execute_MTC0 rt rd sel double) : M (unit) + | TLBWI (arg0) => (execute_TLBWI arg0) : M (unit) + | TLBWR (arg0) => (execute_TLBWR arg0) : M (unit) + | TLBR (arg0) => (execute_TLBR arg0) : M (unit) + | TLBP (arg0) => (execute_TLBP arg0) : M (unit) + | RDHWR (rt,rd) => (execute_RDHWR rt rd) : M (unit) + | ERET (arg0) => (execute_ERET arg0) : M (unit) + | CGetPerm (rd,cb) => (execute_CGetPerm rd cb) : M (unit) + | CGetType (rd,cb) => (execute_CGetType rd cb) : M (unit) + | CGetBase (rd,cb) => (execute_CGetBase rd cb) : M (unit) + | CGetOffset (rd,cb) => (execute_CGetOffset rd cb) : M (unit) + | CGetLen (rd,cb) => (execute_CGetLen rd cb) : M (unit) + | CGetTag (rd,cb) => (execute_CGetTag rd cb) : M (unit) + | CGetSealed (rd,cb) => (execute_CGetSealed rd cb) : M (unit) + | CGetAddr (rd,cb) => (execute_CGetAddr rd cb) : M (unit) + | CGetPCC (cd) => (execute_CGetPCC cd) : M (unit) + | CGetPCCSetOffset (cd,rs) => (execute_CGetPCCSetOffset cd rs) : M (unit) + | CGetCause (rd) => (execute_CGetCause rd) : M (unit) + | CSetCause (rt) => (execute_CSetCause rt) : M (unit) + | CGetCID (rd) => (execute_CGetCID rd) : M (unit) + | CSetCID (cb) => (execute_CSetCID cb) : M (unit) + | CReadHwr (cd,sel) => (execute_CReadHwr cd sel) : M (unit) + | CWriteHwr (cb,sel) => (execute_CWriteHwr cb sel) : M (unit) + | CAndPerm (cd,cb,rt) => (execute_CAndPerm cd cb rt) : M (unit) + | CToPtr (rd,cb,ct) => (execute_CToPtr rd cb ct) : M (unit) + | CSub (rd,cb,ct) => (execute_CSub rd cb ct) : M (unit) + | CPtrCmp (rd,cb,ct,op) => (execute_CPtrCmp rd cb ct op) : M (unit) + | CIncOffset (cd,cb,rt) => (execute_CIncOffset cd cb rt) : M (unit) + | CIncOffsetImmediate (cd,cb,imm) => (execute_CIncOffsetImmediate cd cb imm) : M (unit) + | CSetOffset (cd,cb,rt) => (execute_CSetOffset cd cb rt) : M (unit) + | CSetBounds (cd,cb,rt) => (execute_CSetBounds cd cb rt) : M (unit) + | CSetBoundsImmediate (cd,cb,imm) => (execute_CSetBoundsImmediate cd cb imm) : M (unit) + | CSetBoundsExact (cd,cb,rt) => (execute_CSetBoundsExact cd cb rt) : M (unit) + | CClearTag (cd,cb) => (execute_CClearTag cd cb) : M (unit) + | CMOVX (cd,cb,rt,ismovn) => (execute_CMOVX cd cb rt ismovn) : M (unit) + | ClearRegs (regset,m) => (execute_ClearRegs regset m) : M (unit) + | CFromPtr (cd,cb,rt) => (execute_CFromPtr cd cb rt) : M (unit) + | CBuildCap (cd,cb,ct) => (execute_CBuildCap cd cb ct) : M (unit) + | CCopyType (cd,cb,ct) => (execute_CCopyType cd cb ct) : M (unit) + | CCheckPerm (cs,rt) => (execute_CCheckPerm cs rt) : M (unit) + | CCheckType (cs,cb) => (execute_CCheckType cs cb) : M (unit) + | CCheckTag (cs) => (execute_CCheckTag cs) : M (unit) + | CTestSubset (rd,cb,ct) => (execute_CTestSubset rd cb ct) : M (unit) + | CSeal (cd,cs,ct) => (execute_CSeal cd cs ct) : M (unit) + | CCSeal (cd,cs,ct) => (execute_CCSeal cd cs ct) : M (unit) + | CUnseal (cd,cs,ct) => (execute_CUnseal cd cs ct) : M (unit) + | CCall (cs,cb,b__155) => (execute_CCall cs cb b__155) : M (unit) + | CReturn (arg0) => (execute_CReturn arg0) : M (unit) + | CBX (cb,imm,notset) => (execute_CBX cb imm notset) : M (unit) + | CBZ (cb,imm,notzero) => (execute_CBZ cb imm notzero) : M (unit) + | CJALR (cd,cb,link) => (execute_CJALR cd cb link) : M (unit) + | CLoad (rd,cb,rt,offset,signext,width) => + (execute_CLoad rd cb rt offset signext width) : M (unit) + | CLoadLinked (rd,cb,signext,width) => (execute_CLoadLinked rd cb signext width) : M (unit) + | CLoadTags (rd,cb) => (execute_CLoadTags rd cb) : M (unit) + | CStore (rs,cb,rt,offset,width) => (execute_CStore rs cb rt offset width) : M (unit) + | CStoreConditional (rs,cb,rd,width) => (execute_CStoreConditional rs cb rd width) : M (unit) + | CSC (cs,cb,rt,offset) => (execute_CSC cs cb rt offset) : M (unit) + | CSCC (cs,cb,rd) => (execute_CSCC cs cb rd) : M (unit) + | CLC (cd,cb,rt,offset) => (execute_CLC cd cb rt offset) : M (unit) + | CLCBI (cd,cb,offset) => (execute_CLCBI cd cb offset) : M (unit) + | CLLC (cd,cb) => (execute_CLLC cd cb) : M (unit) + | C2Dump (rt) => returnm ((execute_C2Dump rt) : unit) + | RI (arg0) => (execute_RI arg0) : M (unit) + end) + : M (unit). + +Definition supported_instructions (instr : ast) : option ast := Some (instr). + +Definition initialize_registers '(tt : unit) +: M (unit) := + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => + write_reg PC_ref w__0 >> + (undefined_bitvector 64) >>= fun w__1 : mword 64 => + write_reg NextPC_ref w__1 >> + (undefined_bitvector 1) >>= fun w__2 : mword 1 => + write_reg TLBProbe_ref w__2 >> + (undefined_bitvector 6) >>= fun w__3 : mword 6 => + write_reg TLBIndex_ref w__3 >> + (undefined_bitvector 6) >>= fun w__4 : mword 6 => + write_reg TLBRandom_ref w__4 >> + (undefined_TLBEntryLoReg tt) >>= fun w__5 : TLBEntryLoReg => + write_reg TLBEntryLo0_ref w__5 >> + (undefined_TLBEntryLoReg tt) >>= fun w__6 : TLBEntryLoReg => + write_reg TLBEntryLo1_ref w__6 >> + (undefined_ContextReg tt) >>= fun w__7 : ContextReg => + write_reg TLBContext_ref w__7 >> + (undefined_bitvector 16) >>= fun w__8 : mword 16 => + write_reg TLBPageMask_ref w__8 >> + (undefined_bitvector 6) >>= fun w__9 : mword 6 => + write_reg TLBWired_ref w__9 >> + (undefined_TLBEntryHiReg tt) >>= fun w__10 : TLBEntryHiReg => + write_reg TLBEntryHi_ref w__10 >> + (undefined_XContextReg tt) >>= fun w__11 : XContextReg => + write_reg TLBXContext_ref w__11 >> + (undefined_TLBEntry tt) >>= fun w__12 : TLBEntry => + write_reg TLBEntry00_ref w__12 >> + (undefined_TLBEntry tt) >>= fun w__13 : TLBEntry => + write_reg TLBEntry01_ref w__13 >> + (undefined_TLBEntry tt) >>= fun w__14 : TLBEntry => + write_reg TLBEntry02_ref w__14 >> + (undefined_TLBEntry tt) >>= fun w__15 : TLBEntry => + write_reg TLBEntry03_ref w__15 >> + (undefined_TLBEntry tt) >>= fun w__16 : TLBEntry => + write_reg TLBEntry04_ref w__16 >> + (undefined_TLBEntry tt) >>= fun w__17 : TLBEntry => + write_reg TLBEntry05_ref w__17 >> + (undefined_TLBEntry tt) >>= fun w__18 : TLBEntry => + write_reg TLBEntry06_ref w__18 >> + (undefined_TLBEntry tt) >>= fun w__19 : TLBEntry => + write_reg TLBEntry07_ref w__19 >> + (undefined_TLBEntry tt) >>= fun w__20 : TLBEntry => + write_reg TLBEntry08_ref w__20 >> + (undefined_TLBEntry tt) >>= fun w__21 : TLBEntry => + write_reg TLBEntry09_ref w__21 >> + (undefined_TLBEntry tt) >>= fun w__22 : TLBEntry => + write_reg TLBEntry10_ref w__22 >> + (undefined_TLBEntry tt) >>= fun w__23 : TLBEntry => + write_reg TLBEntry11_ref w__23 >> + (undefined_TLBEntry tt) >>= fun w__24 : TLBEntry => + write_reg TLBEntry12_ref w__24 >> + (undefined_TLBEntry tt) >>= fun w__25 : TLBEntry => + write_reg TLBEntry13_ref w__25 >> + (undefined_TLBEntry tt) >>= fun w__26 : TLBEntry => + write_reg TLBEntry14_ref w__26 >> + (undefined_TLBEntry tt) >>= fun w__27 : TLBEntry => + write_reg TLBEntry15_ref w__27 >> + (undefined_TLBEntry tt) >>= fun w__28 : TLBEntry => + write_reg TLBEntry16_ref w__28 >> + (undefined_TLBEntry tt) >>= fun w__29 : TLBEntry => + write_reg TLBEntry17_ref w__29 >> + (undefined_TLBEntry tt) >>= fun w__30 : TLBEntry => + write_reg TLBEntry18_ref w__30 >> + (undefined_TLBEntry tt) >>= fun w__31 : TLBEntry => + write_reg TLBEntry19_ref w__31 >> + (undefined_TLBEntry tt) >>= fun w__32 : TLBEntry => + write_reg TLBEntry20_ref w__32 >> + (undefined_TLBEntry tt) >>= fun w__33 : TLBEntry => + write_reg TLBEntry21_ref w__33 >> + (undefined_TLBEntry tt) >>= fun w__34 : TLBEntry => + write_reg TLBEntry22_ref w__34 >> + (undefined_TLBEntry tt) >>= fun w__35 : TLBEntry => + write_reg TLBEntry23_ref w__35 >> + (undefined_TLBEntry tt) >>= fun w__36 : TLBEntry => + write_reg TLBEntry24_ref w__36 >> + (undefined_TLBEntry tt) >>= fun w__37 : TLBEntry => + write_reg TLBEntry25_ref w__37 >> + (undefined_TLBEntry tt) >>= fun w__38 : TLBEntry => + write_reg TLBEntry26_ref w__38 >> + (undefined_TLBEntry tt) >>= fun w__39 : TLBEntry => + write_reg TLBEntry27_ref w__39 >> + (undefined_TLBEntry tt) >>= fun w__40 : TLBEntry => + write_reg TLBEntry28_ref w__40 >> + (undefined_TLBEntry tt) >>= fun w__41 : TLBEntry => + write_reg TLBEntry29_ref w__41 >> + (undefined_TLBEntry tt) >>= fun w__42 : TLBEntry => + write_reg TLBEntry30_ref w__42 >> + (undefined_TLBEntry tt) >>= fun w__43 : TLBEntry => + write_reg TLBEntry31_ref w__43 >> + (undefined_TLBEntry tt) >>= fun w__44 : TLBEntry => + write_reg TLBEntry32_ref w__44 >> + (undefined_TLBEntry tt) >>= fun w__45 : TLBEntry => + write_reg TLBEntry33_ref w__45 >> + (undefined_TLBEntry tt) >>= fun w__46 : TLBEntry => + write_reg TLBEntry34_ref w__46 >> + (undefined_TLBEntry tt) >>= fun w__47 : TLBEntry => + write_reg TLBEntry35_ref w__47 >> + (undefined_TLBEntry tt) >>= fun w__48 : TLBEntry => + write_reg TLBEntry36_ref w__48 >> + (undefined_TLBEntry tt) >>= fun w__49 : TLBEntry => + write_reg TLBEntry37_ref w__49 >> + (undefined_TLBEntry tt) >>= fun w__50 : TLBEntry => + write_reg TLBEntry38_ref w__50 >> + (undefined_TLBEntry tt) >>= fun w__51 : TLBEntry => + write_reg TLBEntry39_ref w__51 >> + (undefined_TLBEntry tt) >>= fun w__52 : TLBEntry => + write_reg TLBEntry40_ref w__52 >> + (undefined_TLBEntry tt) >>= fun w__53 : TLBEntry => + write_reg TLBEntry41_ref w__53 >> + (undefined_TLBEntry tt) >>= fun w__54 : TLBEntry => + write_reg TLBEntry42_ref w__54 >> + (undefined_TLBEntry tt) >>= fun w__55 : TLBEntry => + write_reg TLBEntry43_ref w__55 >> + (undefined_TLBEntry tt) >>= fun w__56 : TLBEntry => + write_reg TLBEntry44_ref w__56 >> + (undefined_TLBEntry tt) >>= fun w__57 : TLBEntry => + write_reg TLBEntry45_ref w__57 >> + (undefined_TLBEntry tt) >>= fun w__58 : TLBEntry => + write_reg TLBEntry46_ref w__58 >> + (undefined_TLBEntry tt) >>= fun w__59 : TLBEntry => + write_reg TLBEntry47_ref w__59 >> + (undefined_TLBEntry tt) >>= fun w__60 : TLBEntry => + write_reg TLBEntry48_ref w__60 >> + (undefined_TLBEntry tt) >>= fun w__61 : TLBEntry => + write_reg TLBEntry49_ref w__61 >> + (undefined_TLBEntry tt) >>= fun w__62 : TLBEntry => + write_reg TLBEntry50_ref w__62 >> + (undefined_TLBEntry tt) >>= fun w__63 : TLBEntry => + write_reg TLBEntry51_ref w__63 >> + (undefined_TLBEntry tt) >>= fun w__64 : TLBEntry => + write_reg TLBEntry52_ref w__64 >> + (undefined_TLBEntry tt) >>= fun w__65 : TLBEntry => + write_reg TLBEntry53_ref w__65 >> + (undefined_TLBEntry tt) >>= fun w__66 : TLBEntry => + write_reg TLBEntry54_ref w__66 >> + (undefined_TLBEntry tt) >>= fun w__67 : TLBEntry => + write_reg TLBEntry55_ref w__67 >> + (undefined_TLBEntry tt) >>= fun w__68 : TLBEntry => + write_reg TLBEntry56_ref w__68 >> + (undefined_TLBEntry tt) >>= fun w__69 : TLBEntry => + write_reg TLBEntry57_ref w__69 >> + (undefined_TLBEntry tt) >>= fun w__70 : TLBEntry => + write_reg TLBEntry58_ref w__70 >> + (undefined_TLBEntry tt) >>= fun w__71 : TLBEntry => + write_reg TLBEntry59_ref w__71 >> + (undefined_TLBEntry tt) >>= fun w__72 : TLBEntry => + write_reg TLBEntry60_ref w__72 >> + (undefined_TLBEntry tt) >>= fun w__73 : TLBEntry => + write_reg TLBEntry61_ref w__73 >> + (undefined_TLBEntry tt) >>= fun w__74 : TLBEntry => + write_reg TLBEntry62_ref w__74 >> + (undefined_TLBEntry tt) >>= fun w__75 : TLBEntry => + write_reg TLBEntry63_ref w__75 >> + (undefined_bitvector 32) >>= fun w__76 : mword 32 => + write_reg CP0Compare_ref w__76 >> + (undefined_CauseReg tt) >>= fun w__77 : CauseReg => + write_reg CP0Cause_ref w__77 >> + (undefined_bitvector 64) >>= fun w__78 : mword 64 => + write_reg CP0EPC_ref w__78 >> + (undefined_bitvector 64) >>= fun w__79 : mword 64 => + write_reg CP0ErrorEPC_ref w__79 >> + (undefined_bitvector 1) >>= fun w__80 : mword 1 => + write_reg CP0LLBit_ref w__80 >> + (undefined_bitvector 64) >>= fun w__81 : mword 64 => + write_reg CP0LLAddr_ref w__81 >> + (undefined_bitvector 64) >>= fun w__82 : mword 64 => + write_reg CP0BadVAddr_ref w__82 >> + (undefined_bitvector 32) >>= fun w__83 : mword 32 => + write_reg CurrentInstrBits_ref w__83 >> + (undefined_bitvector 32) >>= fun w__84 : mword 32 => + write_reg LastInstrBits_ref w__84 >> + (undefined_bitvector 32) >>= fun w__85 : mword 32 => + write_reg CP0BadInstr_ref w__85 >> + (undefined_bitvector 32) >>= fun w__86 : mword 32 => + write_reg CP0BadInstrP_ref w__86 >> + (undefined_bitvector 32) >>= fun w__87 : mword 32 => + write_reg CP0Count_ref w__87 >> + (undefined_bitvector 32) >>= fun w__88 : mword 32 => + write_reg CP0HWREna_ref w__88 >> + (undefined_bitvector 64) >>= fun w__89 : mword 64 => + write_reg CP0UserLocal_ref w__89 >> + (undefined_bitvector 3) >>= fun w__90 : mword 3 => + write_reg CP0ConfigK0_ref w__90 >> + (undefined_StatusReg tt) >>= fun w__91 : StatusReg => + write_reg CP0Status_ref w__91 >> + (undefined_bitvector 1) >>= fun w__92 : mword 1 => + write_reg NextInBranchDelay_ref w__92 >> + (undefined_bitvector 1) >>= fun w__93 : mword 1 => + write_reg InBranchDelay_ref w__93 >> + (undefined_bitvector 1) >>= fun w__94 : mword 1 => + write_reg BranchPending_ref w__94 >> + (undefined_bitvector 64) >>= fun w__95 : mword 64 => + write_reg DelayedPC_ref w__95 >> + (undefined_bitvector 64) >>= fun w__96 : mword 64 => + write_reg HI_ref w__96 >> + (undefined_bitvector 64) >>= fun w__97 : mword 64 => + write_reg LO_ref w__97 >> + (undefined_bitvector 64) >>= fun w__98 : mword 64 => + (undefined_vector 32 w__98) >>= fun w__99 : vec (mword 64) 32 => + write_reg GPR_ref w__99 >> + (undefined_bitvector 8) >>= fun w__100 : mword 8 => + write_reg UART_WDATA_ref w__100 >> + (undefined_bitvector 1) >>= fun w__101 : mword 1 => + write_reg UART_WRITTEN_ref w__101 >> + (undefined_bitvector 8) >>= fun w__102 : mword 8 => + write_reg UART_RDATA_ref w__102 >> + (undefined_bitvector 1) >>= fun w__103 : mword 1 => + write_reg UART_RVALID_ref w__103 >> + (undefined_Capability tt) >>= fun w__104 : Capability => + write_reg PCC_ref w__104 >> + (undefined_Capability tt) >>= fun w__105 : Capability => + write_reg NextPCC_ref w__105 >> + (undefined_Capability tt) >>= fun w__106 : Capability => + write_reg DelayedPCC_ref w__106 >> + (undefined_Capability tt) >>= fun w__107 : Capability => + write_reg DDC_ref w__107 >> + (undefined_Capability tt) >>= fun w__108 : Capability => + write_reg C01_ref w__108 >> + (undefined_Capability tt) >>= fun w__109 : Capability => + write_reg C02_ref w__109 >> + (undefined_Capability tt) >>= fun w__110 : Capability => + write_reg C03_ref w__110 >> + (undefined_Capability tt) >>= fun w__111 : Capability => + write_reg C04_ref w__111 >> + (undefined_Capability tt) >>= fun w__112 : Capability => + write_reg C05_ref w__112 >> + (undefined_Capability tt) >>= fun w__113 : Capability => + write_reg C06_ref w__113 >> + (undefined_Capability tt) >>= fun w__114 : Capability => + write_reg C07_ref w__114 >> + (undefined_Capability tt) >>= fun w__115 : Capability => + write_reg C08_ref w__115 >> + (undefined_Capability tt) >>= fun w__116 : Capability => + write_reg C09_ref w__116 >> + (undefined_Capability tt) >>= fun w__117 : Capability => + write_reg C10_ref w__117 >> + (undefined_Capability tt) >>= fun w__118 : Capability => + write_reg C11_ref w__118 >> + (undefined_Capability tt) >>= fun w__119 : Capability => + write_reg C12_ref w__119 >> + (undefined_Capability tt) >>= fun w__120 : Capability => + write_reg C13_ref w__120 >> + (undefined_Capability tt) >>= fun w__121 : Capability => + write_reg C14_ref w__121 >> + (undefined_Capability tt) >>= fun w__122 : Capability => + write_reg C15_ref w__122 >> + (undefined_Capability tt) >>= fun w__123 : Capability => + write_reg C16_ref w__123 >> + (undefined_Capability tt) >>= fun w__124 : Capability => + write_reg C17_ref w__124 >> + (undefined_Capability tt) >>= fun w__125 : Capability => + write_reg C18_ref w__125 >> + (undefined_Capability tt) >>= fun w__126 : Capability => + write_reg C19_ref w__126 >> + (undefined_Capability tt) >>= fun w__127 : Capability => + write_reg C20_ref w__127 >> + (undefined_Capability tt) >>= fun w__128 : Capability => + write_reg C21_ref w__128 >> + (undefined_Capability tt) >>= fun w__129 : Capability => + write_reg C22_ref w__129 >> + (undefined_Capability tt) >>= fun w__130 : Capability => + write_reg C23_ref w__130 >> + (undefined_Capability tt) >>= fun w__131 : Capability => + write_reg C24_ref w__131 >> + (undefined_Capability tt) >>= fun w__132 : Capability => + write_reg C25_ref w__132 >> + (undefined_Capability tt) >>= fun w__133 : Capability => + write_reg C26_ref w__133 >> + (undefined_Capability tt) >>= fun w__134 : Capability => + write_reg C27_ref w__134 >> + (undefined_Capability tt) >>= fun w__135 : Capability => + write_reg C28_ref w__135 >> + (undefined_Capability tt) >>= fun w__136 : Capability => + write_reg C29_ref w__136 >> + (undefined_Capability tt) >>= fun w__137 : Capability => + write_reg C30_ref w__137 >> + (undefined_Capability tt) >>= fun w__138 : Capability => + write_reg C31_ref w__138 >> + (undefined_Capability tt) >>= fun w__139 : Capability => + write_reg CTLSU_ref w__139 >> + (undefined_Capability tt) >>= fun w__140 : Capability => + write_reg CTLSP_ref w__140 >> + (undefined_Capability tt) >>= fun w__141 : Capability => + write_reg KR1C_ref w__141 >> + (undefined_Capability tt) >>= fun w__142 : Capability => + write_reg KR2C_ref w__142 >> + (undefined_Capability tt) >>= fun w__143 : Capability => + write_reg KCC_ref w__143 >> + (undefined_Capability tt) >>= fun w__144 : Capability => + write_reg KDC_ref w__144 >> + (undefined_Capability tt) >>= fun w__145 : Capability => + write_reg EPCC_ref w__145 >> + (undefined_CapCauseReg tt) >>= fun w__146 : CapCauseReg => + write_reg CapCause_ref w__146 >> + (undefined_bitvector 64) >>= fun w__147 : mword 64 => write_reg CID_ref w__147 : M (unit). + +Definition initial_regstate : regstate := +{| CID := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CapCause := + ({| CapCauseReg_CapCauseReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16) |}); + EPCC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + KDC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + KCC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + KR2C := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + KR1C := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + CTLSP := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + CTLSU := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C31 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C30 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C29 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C28 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C27 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C26 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C25 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C24 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C23 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C22 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C21 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C20 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C19 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C18 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C17 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C16 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C15 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C14 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C13 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C12 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C11 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C10 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C09 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C08 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C07 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C06 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C05 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C04 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C03 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C02 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + C01 := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + DDC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + DelayedPCC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + NextPCC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + PCC := + ({| Capability_tag := false; + Capability_padding := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + Capability_otype := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 24); + Capability_uperms := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + Capability_perm_reserved12_14 := (vec_of_bits [B0;B0;B0] : mword 3); + Capability_permit_set_CID := false; + Capability_access_system_regs := false; + Capability_permit_unseal := false; + Capability_permit_ccall := false; + Capability_permit_seal := false; + Capability_permit_store_local_cap := false; + Capability_permit_store_cap := false; + Capability_permit_load_cap := false; + Capability_permit_store := false; + Capability_permit_load := false; + Capability_permit_execute := false; + Capability_global := false; + Capability_sealed := false; + Capability_address := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_base := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Capability_length := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + UART_RVALID := (vec_of_bits [B0] : mword 1); + UART_RDATA := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + UART_WRITTEN := (vec_of_bits [B0] : mword 1); + UART_WDATA := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8); + GPR := + (vec_of_list_len [(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64)]); + LO := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + HI := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + DelayedPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + BranchPending := (vec_of_bits [B0] : mword 1); + InBranchDelay := (vec_of_bits [B0] : mword 1); + NextInBranchDelay := (vec_of_bits [B0] : mword 1); + CP0Status := + ({| StatusReg_StatusReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) |}); + CP0ConfigK0 := (vec_of_bits [B0;B0;B0] : mword 3); + CP0UserLocal := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0HWREna := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0Count := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0BadInstrP := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0BadInstr := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + LastInstrBits := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CurrentInstrBits := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0BadVAddr := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0LLAddr := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0LLBit := (vec_of_bits [B0] : mword 1); + CP0ErrorEPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0EPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + CP0Cause := + ({| CauseReg_CauseReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) |}); + CP0Compare := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + TLBEntry63 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry62 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry61 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry60 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry59 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry58 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry57 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry56 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry55 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry54 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry53 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry52 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry51 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry50 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry49 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry48 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry47 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry46 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry45 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry44 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry43 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry42 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry41 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry40 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry39 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry38 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry37 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry36 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry35 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry34 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry33 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry32 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry31 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry30 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry29 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry28 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry27 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry26 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry25 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry24 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry23 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry22 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry21 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry20 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry19 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry18 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry17 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry16 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry15 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry14 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry13 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry12 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry11 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry10 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry09 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry08 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry07 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry06 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry05 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry04 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry03 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry02 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry01 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntry00 := + ({| TLBEntry_TLBEntry_chunk_1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 53); + TLBEntry_TLBEntry_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBXContext := + ({| XContextReg_XContextReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntryHi := + ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBWired := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); + TLBPageMask := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16); + TLBContext := + ({| ContextReg_ContextReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntryLo1 := + ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBEntryLo0 := + ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + TLBRandom := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); + TLBIndex := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); + TLBProbe := (vec_of_bits [B0] : mword 1); + NextPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + PC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}. +Hint Unfold initial_regstate : sail. + +End Content. diff --git a/snapshots/coq/cheri-mips/cheri_types.v b/snapshots/coq/cheri-mips/cheri_types.v new file mode 100644 index 00000000..07e4bc80 --- /dev/null +++ b/snapshots/coq/cheri-mips/cheri_types.v @@ -0,0 +1,2229 @@ +(*Generated by Sail from cheri.*) +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_string. +Require Import Sail2_real. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import Sail2_state. + + +Definition bits (n : Z) : Type := mword n. + +Inductive exception := + ISAException : unit -> exception + | Error_not_implemented : string -> exception + | Error_misaligned_access : unit -> exception + | Error_EBREAK : unit -> exception + | Error_internal_error : unit -> exception. +Arguments exception : clear implicits. + + + +Record CauseReg := { CauseReg_CauseReg_chunk_0 : mword 32; }. +Notation "{[ r 'with' 'CauseReg_CauseReg_chunk_0' := e ]}" := ({| CauseReg_CauseReg_chunk_0 := e |}). + +Record CapCauseReg := { CapCauseReg_CapCauseReg_chunk_0 : mword 16; }. +Notation "{[ r 'with' 'CapCauseReg_CapCauseReg_chunk_0' := e ]}" := ({| CapCauseReg_CapCauseReg_chunk_0 := e |}). + +Record TLBEntryLoReg := { TLBEntryLoReg_TLBEntryLoReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'TLBEntryLoReg_TLBEntryLoReg_chunk_0' := e ]}" := ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := e |}). + +Record TLBEntryHiReg := { TLBEntryHiReg_TLBEntryHiReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'TLBEntryHiReg_TLBEntryHiReg_chunk_0' := e ]}" := ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := e |}). + +Record ContextReg := { ContextReg_ContextReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'ContextReg_ContextReg_chunk_0' := e ]}" := ({| ContextReg_ContextReg_chunk_0 := e |}). + +Record XContextReg := { XContextReg_XContextReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'XContextReg_XContextReg_chunk_0' := e ]}" := ({| XContextReg_XContextReg_chunk_0 := e |}). + +Definition TLBIndexT : Type := bits 6. + +Record TLBEntry := { TLBEntry_TLBEntry_chunk_1 : mword 53; TLBEntry_TLBEntry_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_1' := e ]}" := ({| TLBEntry_TLBEntry_chunk_1 := e; TLBEntry_TLBEntry_chunk_0 := TLBEntry_TLBEntry_chunk_0 r |}). +Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_0' := e ]}" := ({| TLBEntry_TLBEntry_chunk_0 := e; TLBEntry_TLBEntry_chunk_1 := TLBEntry_TLBEntry_chunk_1 r |}). + +Record StatusReg := { StatusReg_StatusReg_chunk_0 : mword 32; }. +Notation "{[ r 'with' 'StatusReg_StatusReg_chunk_0' := e ]}" := ({| StatusReg_StatusReg_chunk_0 := e |}). + +Inductive Exception := + Interrupt + | TLBMod + | TLBL + | TLBS + | AdEL + | AdES + | Sys + | Bp + | ResI + | CpU + | Ov + | Tr + | C2E + | C2Trap + | XTLBRefillL + | XTLBRefillS + | XTLBInvL + | XTLBInvS + | MCheck. +Scheme Equality for Exception. +Instance Decidable_eq_Exception : +forall (x y : Exception), Decidable (x = y) := +Decidable_eq_from_dec Exception_eq_dec. + + +Record Capability := + { Capability_tag : bool; + Capability_padding : bits 8; + Capability_otype : bits 24; + Capability_uperms : bits 16; + Capability_perm_reserved12_14 : bits 3; + Capability_permit_set_CID : bool; + Capability_access_system_regs : bool; + Capability_permit_unseal : bool; + Capability_permit_ccall : bool; + Capability_permit_seal : bool; + Capability_permit_store_local_cap : bool; + Capability_permit_store_cap : bool; + Capability_permit_load_cap : bool; + Capability_permit_store : bool; + Capability_permit_load : bool; + Capability_permit_execute : bool; + Capability_global : bool; + Capability_sealed : bool; + Capability_address : bits 64; + Capability_base : bits 64; + Capability_length : bits 64; }. +Instance Decidable_eq_Capability : +forall (x y : Capability), Decidable (x = y). + intros [x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x17 x18 x19 x20]. + intros [y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20]. +cmp_record_field x0 y0. +cmp_record_field x1 y1. +cmp_record_field x2 y2. +cmp_record_field x3 y3. +cmp_record_field x4 y4. +cmp_record_field x5 y5. +cmp_record_field x6 y6. +cmp_record_field x7 y7. +cmp_record_field x8 y8. +cmp_record_field x9 y9. +cmp_record_field x10 y10. +cmp_record_field x11 y11. +cmp_record_field x12 y12. +cmp_record_field x13 y13. +cmp_record_field x14 y14. +cmp_record_field x15 y15. +cmp_record_field x16 y16. +cmp_record_field x17 y17. +cmp_record_field x18 y18. +cmp_record_field x19 y19. +cmp_record_field x20 y20. +refine (Build_Decidable _ true _). subst. split; reflexivity. +Defined. +Notation "{[ r 'with' 'Capability_tag' := e ]}" := ({| Capability_tag := e; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_padding' := e ]}" := ({| Capability_padding := e; Capability_tag := Capability_tag r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_otype' := e ]}" := ({| Capability_otype := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_uperms' := e ]}" := ({| Capability_uperms := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_perm_reserved12_14' := e ]}" := ({| Capability_perm_reserved12_14 := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_set_CID' := e ]}" := ({| Capability_permit_set_CID := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_access_system_regs' := e ]}" := ({| Capability_access_system_regs := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_unseal' := e ]}" := ({| Capability_permit_unseal := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_ccall' := e ]}" := ({| Capability_permit_ccall := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_seal' := e ]}" := ({| Capability_permit_seal := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_store_local_cap' := e ]}" := ({| Capability_permit_store_local_cap := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_store_cap' := e ]}" := ({| Capability_permit_store_cap := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_load_cap' := e ]}" := ({| Capability_permit_load_cap := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_store' := e ]}" := ({| Capability_permit_store := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_load' := e ]}" := ({| Capability_permit_load := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_permit_execute' := e ]}" := ({| Capability_permit_execute := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_global' := e ]}" := ({| Capability_global := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_sealed' := e ]}" := ({| Capability_sealed := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_address := Capability_address r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_address' := e ]}" := ({| Capability_address := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_base := Capability_base r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_base' := e ]}" := ({| Capability_base := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_length := Capability_length r |}). +Notation "{[ r 'with' 'Capability_length' := e ]}" := ({| Capability_length := e; Capability_tag := Capability_tag r; Capability_padding := Capability_padding r; Capability_otype := Capability_otype r; Capability_uperms := Capability_uperms r; Capability_perm_reserved12_14 := Capability_perm_reserved12_14 r; Capability_permit_set_CID := Capability_permit_set_CID r; Capability_access_system_regs := Capability_access_system_regs r; Capability_permit_unseal := Capability_permit_unseal r; Capability_permit_ccall := Capability_permit_ccall r; Capability_permit_seal := Capability_permit_seal r; Capability_permit_store_local_cap := Capability_permit_store_local_cap r; Capability_permit_store_cap := Capability_permit_store_cap r; Capability_permit_load_cap := Capability_permit_load_cap r; Capability_permit_store := Capability_permit_store r; Capability_permit_load := Capability_permit_load r; Capability_permit_execute := Capability_permit_execute r; Capability_global := Capability_global r; Capability_sealed := Capability_sealed r; Capability_address := Capability_address r; Capability_base := Capability_base r |}). + +Inductive MemAccessType := Instruction | LoadData | StoreData. +Scheme Equality for MemAccessType. +Instance Decidable_eq_MemAccessType : +forall (x y : MemAccessType), Decidable (x = y) := +Decidable_eq_from_dec MemAccessType_eq_dec. + + +Inductive AccessLevel := User | Supervisor | Kernel. +Scheme Equality for AccessLevel. +Instance Decidable_eq_AccessLevel : +forall (x y : AccessLevel), Decidable (x = y) := +Decidable_eq_from_dec AccessLevel_eq_dec. + + +Definition regno : Type := bits 5. + +Definition imm16 : Type := bits 16. + +Definition regregreg : Type := (regno * regno * regno). + +Definition regregimm16 : Type := (regno * regno * imm16). + +Inductive decode_failure := + no_matching_pattern | unsupported_instruction | illegal_instruction | internal_error. +Scheme Equality for decode_failure. +Instance Decidable_eq_decode_failure : +forall (x y : decode_failure), Decidable (x = y) := +Decidable_eq_from_dec decode_failure_eq_dec. + + +Inductive Comparison := EQ' | NE | GE | GEU | GT' | LE | LT' | LTU. +Scheme Equality for Comparison. +Instance Decidable_eq_Comparison : +forall (x y : Comparison), Decidable (x = y) := +Decidable_eq_from_dec Comparison_eq_dec. + + +Inductive WordType := B | H | W | D. +Scheme Equality for WordType. +Instance Decidable_eq_WordType : +forall (x y : WordType), Decidable (x = y) := +Decidable_eq_from_dec WordType_eq_dec. + + +Inductive WordTypeUnaligned := WL | WR | DL | DR. +Scheme Equality for WordTypeUnaligned. +Instance Decidable_eq_WordTypeUnaligned : +forall (x y : WordTypeUnaligned), Decidable (x = y) := +Decidable_eq_from_dec WordTypeUnaligned_eq_dec. + + +Definition CapLen : Type := {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 65))}. + +Definition uint64 : Type := {rangevar : Z & ArithFact (0 <= rangevar /\ rangevar <= (2 ^ 64 - 1))}. + +Inductive CPtrCmpOp := CEQ | CNE | CLT | CLE | CLTU | CLEU | CEXEQ | CNEXEQ. +Scheme Equality for CPtrCmpOp. +Instance Decidable_eq_CPtrCmpOp : +forall (x y : CPtrCmpOp), Decidable (x = y) := +Decidable_eq_from_dec CPtrCmpOp_eq_dec. + + +Inductive ClearRegSet := GPLo | GPHi | CLo | CHi. +Scheme Equality for ClearRegSet. +Instance Decidable_eq_ClearRegSet : +forall (x y : ClearRegSet), Decidable (x = y) := +Decidable_eq_from_dec ClearRegSet_eq_dec. + + +Definition CapBits : Type := bits 256. + +Inductive ast := + DADDIU : (regno * regno * imm16) -> ast + | DADDU : (regno * regno * regno) -> ast + | DADDI : (regno * regno * bits 16) -> ast + | DADD : (regno * regno * regno) -> ast + | ADD : (regno * regno * regno) -> ast + | ADDI : (regno * regno * bits 16) -> ast + | ADDU : (regno * regno * regno) -> ast + | ADDIU : (regno * regno * bits 16) -> ast + | DSUBU : (regno * regno * regno) -> ast + | DSUB : (regno * regno * regno) -> ast + | SUB : (regno * regno * regno) -> ast + | SUBU : (regno * regno * regno) -> ast + | AND : (regno * regno * regno) -> ast + | ANDI : (regno * regno * bits 16) -> ast + | OR : (regno * regno * regno) -> ast + | ORI : (regno * regno * bits 16) -> ast + | NOR : (regno * regno * regno) -> ast + | XOR : (regno * regno * regno) -> ast + | XORI : (regno * regno * bits 16) -> ast + | LUI : (regno * imm16) -> ast + | DSLL : (regno * regno * regno) -> ast + | DSLL32 : (regno * regno * regno) -> ast + | DSLLV : (regno * regno * regno) -> ast + | DSRA : (regno * regno * regno) -> ast + | DSRA32 : (regno * regno * regno) -> ast + | DSRAV : (regno * regno * regno) -> ast + | DSRL : (regno * regno * regno) -> ast + | DSRL32 : (regno * regno * regno) -> ast + | DSRLV : (regno * regno * regno) -> ast + | SLL : (regno * regno * regno) -> ast + | SLLV : (regno * regno * regno) -> ast + | SRA : (regno * regno * regno) -> ast + | SRAV : (regno * regno * regno) -> ast + | SRL : (regno * regno * regno) -> ast + | SRLV : (regno * regno * regno) -> ast + | SLT : (regno * regno * regno) -> ast + | SLTI : (regno * regno * bits 16) -> ast + | SLTU : (regno * regno * regno) -> ast + | SLTIU : (regno * regno * bits 16) -> ast + | MOVN : (regno * regno * regno) -> ast + | MOVZ : (regno * regno * regno) -> ast + | MFHI : regno -> ast + | MFLO : regno -> ast + | MTHI : regno -> ast + | MTLO : regno -> ast + | MUL : (regno * regno * regno) -> ast + | MULT : (regno * regno) -> ast + | MULTU : (regno * regno) -> ast + | DMULT : (regno * regno) -> ast + | DMULTU : (regno * regno) -> ast + | MADD : (regno * regno) -> ast + | MADDU : (regno * regno) -> ast + | MSUB : (regno * regno) -> ast + | MSUBU : (regno * regno) -> ast + | DIV : (regno * regno) -> ast + | DIVU : (regno * regno) -> ast + | DDIV : (regno * regno) -> ast + | DDIVU : (regno * regno) -> ast + | J : bits 26 -> ast + | JAL : bits 26 -> ast + | JR : regno -> ast + | JALR : (regno * regno) -> ast + | BEQ : (regno * regno * imm16 * bool * bool) -> ast + | BCMPZ : (regno * imm16 * Comparison * bool * bool) -> ast + | SYSCALL : unit -> ast + | BREAK : unit -> ast + | WAIT : unit -> ast + | TRAPREG : (regno * regno * Comparison) -> ast + | TRAPIMM : (regno * imm16 * Comparison) -> ast + | Load : (WordType * bool * bool * regno * regno * imm16) -> ast + | Store : (WordType * bool * regno * regno * imm16) -> ast + | LWL : (regno * regno * bits 16) -> ast + | LWR : (regno * regno * bits 16) -> ast + | SWL : (regno * regno * bits 16) -> ast + | SWR : (regno * regno * bits 16) -> ast + | LDL : (regno * regno * bits 16) -> ast + | LDR : (regno * regno * bits 16) -> ast + | SDL : (regno * regno * bits 16) -> ast + | SDR : (regno * regno * bits 16) -> ast + | CACHE : (regno * regno * bits 16) -> ast + | SYNC : unit -> ast + | MFC0 : (regno * regno * bits 3 * bool) -> ast + | HCF : unit -> ast + | MTC0 : (regno * regno * bits 3 * bool) -> ast + | TLBWI : unit -> ast + | TLBWR : unit -> ast + | TLBR : unit -> ast + | TLBP : unit -> ast + | RDHWR : (regno * regno) -> ast + | ERET : unit -> ast + | CGetPerm : (regno * regno) -> ast + | CGetType : (regno * regno) -> ast + | CGetBase : (regno * regno) -> ast + | CGetLen : (regno * regno) -> ast + | CGetTag : (regno * regno) -> ast + | CGetSealed : (regno * regno) -> ast + | CGetOffset : (regno * regno) -> ast + | CGetAddr : (regno * regno) -> ast + | CGetPCC : regno -> ast + | CGetPCCSetOffset : (regno * regno) -> ast + | CGetCause : regno -> ast + | CSetCause : regno -> ast + | CGetCID : regno -> ast + | CSetCID : regno -> ast + | CReadHwr : (regno * regno) -> ast + | CWriteHwr : (regno * regno) -> ast + | CAndPerm : (regno * regno * regno) -> ast + | CToPtr : (regno * regno * regno) -> ast + | CSub : (regno * regno * regno) -> ast + | CPtrCmp : (regno * regno * regno * CPtrCmpOp) -> ast + | CIncOffset : (regno * regno * regno) -> ast + | CIncOffsetImmediate : (regno * regno * bits 11) -> ast + | CSetOffset : (regno * regno * regno) -> ast + | CSetBounds : (regno * regno * regno) -> ast + | CSetBoundsImmediate : (regno * regno * bits 11) -> ast + | CSetBoundsExact : (regno * regno * regno) -> ast + | CClearTag : (regno * regno) -> ast + | CMOVX : (regno * regno * regno * bool) -> ast + | ClearRegs : (ClearRegSet * bits 16) -> ast + | CFromPtr : (regno * regno * regno) -> ast + | CBuildCap : (regno * regno * regno) -> ast + | CCopyType : (regno * regno * regno) -> ast + | CCheckPerm : (regno * regno) -> ast + | CCheckType : (regno * regno) -> ast + | CCheckTag : regno -> ast + | CTestSubset : (regno * regno * regno) -> ast + | CSeal : (regno * regno * regno) -> ast + | CCSeal : (regno * regno * regno) -> ast + | CUnseal : (regno * regno * regno) -> ast + | CCall : (regno * regno * bits 11) -> ast + | CReturn : unit -> ast + | CBX : (regno * bits 16 * bool) -> ast + | CBZ : (regno * bits 16 * bool) -> ast + | CJALR : (regno * regno * bool) -> ast + | CLoad : (regno * regno * regno * bits 8 * bool * WordType) -> ast + | CLoadLinked : (regno * regno * bool * WordType) -> ast + | CLoadTags : (regno * regno) -> ast + | CStore : (regno * regno * regno * bits 8 * WordType) -> ast + | CStoreConditional : (regno * regno * regno * WordType) -> ast + | CSC : (regno * regno * regno * bits 11) -> ast + | CSCC : (regno * regno * regno) -> ast + | CLC : (regno * regno * regno * bits 11) -> ast + | CLCBI : (regno * regno * bits 16) -> ast + | CLLC : (regno * regno) -> ast + | C2Dump : regno -> ast + | RI : unit -> ast. +Arguments ast : clear implicits. + + + +Inductive CapEx := + CapEx_None + | CapEx_LengthViolation + | CapEx_TagViolation + | CapEx_SealViolation + | CapEx_TypeViolation + | CapEx_CallTrap + | CapEx_ReturnTrap + | CapEx_TSSUnderFlow + | CapEx_UserDefViolation + | CapEx_TLBNoStoreCap + | CapEx_InexactBounds + | CapEx_GlobalViolation + | CapEx_PermitExecuteViolation + | CapEx_PermitLoadViolation + | CapEx_PermitStoreViolation + | CapEx_PermitLoadCapViolation + | CapEx_PermitStoreCapViolation + | CapEx_PermitStoreLocalCapViolation + | CapEx_PermitSealViolation + | CapEx_AccessSystemRegsViolation + | CapEx_PermitCCallViolation + | CapEx_AccessCCallIDCViolation + | CapEx_PermitUnsealViolation + | CapEx_PermitSetCIDViolation. +Scheme Equality for CapEx. +Instance Decidable_eq_CapEx : +forall (x y : CapEx), Decidable (x = y) := +Decidable_eq_from_dec CapEx_eq_dec. + + +Inductive register_value := + Regval_vector : (Z * bool * list register_value) -> register_value + | Regval_list : list register_value -> register_value + | Regval_option : option register_value -> register_value + | Regval_CapCauseReg : CapCauseReg -> register_value + | Regval_Capability : Capability -> register_value + | Regval_CauseReg : CauseReg -> register_value + | Regval_ContextReg : ContextReg -> register_value + | Regval_StatusReg : StatusReg -> register_value + | Regval_TLBEntry : TLBEntry -> register_value + | Regval_TLBEntryHiReg : TLBEntryHiReg -> register_value + | Regval_TLBEntryLoReg : TLBEntryLoReg -> register_value + | Regval_XContextReg : XContextReg -> register_value + | Regval_vector_16_dec_bit : mword 16 -> register_value + | Regval_vector_1_dec_bit : mword 1 -> register_value + | Regval_vector_32_dec_bit : mword 32 -> register_value + | Regval_vector_3_dec_bit : mword 3 -> register_value + | Regval_vector_64_dec_bit : mword 64 -> register_value + | Regval_vector_6_dec_bit : mword 6 -> register_value + | Regval_vector_8_dec_bit : mword 8 -> register_value. +Arguments register_value : clear implicits. + + + +Record regstate := + { CID : mword 64; + CapCause : CapCauseReg; + EPCC : Capability; + KDC : Capability; + KCC : Capability; + KR2C : Capability; + KR1C : Capability; + CTLSP : Capability; + CTLSU : Capability; + C31 : Capability; + C30 : Capability; + C29 : Capability; + C28 : Capability; + C27 : Capability; + C26 : Capability; + C25 : Capability; + C24 : Capability; + C23 : Capability; + C22 : Capability; + C21 : Capability; + C20 : Capability; + C19 : Capability; + C18 : Capability; + C17 : Capability; + C16 : Capability; + C15 : Capability; + C14 : Capability; + C13 : Capability; + C12 : Capability; + C11 : Capability; + C10 : Capability; + C09 : Capability; + C08 : Capability; + C07 : Capability; + C06 : Capability; + C05 : Capability; + C04 : Capability; + C03 : Capability; + C02 : Capability; + C01 : Capability; + DDC : Capability; + DelayedPCC : Capability; + NextPCC : Capability; + PCC : Capability; + UART_RVALID : mword 1; + UART_RDATA : mword 8; + UART_WRITTEN : mword 1; + UART_WDATA : mword 8; + GPR : vec (mword 64) 32; + LO : mword 64; + HI : mword 64; + DelayedPC : mword 64; + BranchPending : mword 1; + InBranchDelay : mword 1; + NextInBranchDelay : mword 1; + CP0Status : StatusReg; + CP0ConfigK0 : mword 3; + CP0UserLocal : mword 64; + CP0HWREna : mword 32; + CP0Count : mword 32; + CP0BadInstrP : mword 32; + CP0BadInstr : mword 32; + LastInstrBits : mword 32; + CurrentInstrBits : mword 32; + CP0BadVAddr : mword 64; + CP0LLAddr : mword 64; + CP0LLBit : mword 1; + CP0ErrorEPC : mword 64; + CP0EPC : mword 64; + CP0Cause : CauseReg; + CP0Compare : mword 32; + TLBEntry63 : TLBEntry; + TLBEntry62 : TLBEntry; + TLBEntry61 : TLBEntry; + TLBEntry60 : TLBEntry; + TLBEntry59 : TLBEntry; + TLBEntry58 : TLBEntry; + TLBEntry57 : TLBEntry; + TLBEntry56 : TLBEntry; + TLBEntry55 : TLBEntry; + TLBEntry54 : TLBEntry; + TLBEntry53 : TLBEntry; + TLBEntry52 : TLBEntry; + TLBEntry51 : TLBEntry; + TLBEntry50 : TLBEntry; + TLBEntry49 : TLBEntry; + TLBEntry48 : TLBEntry; + TLBEntry47 : TLBEntry; + TLBEntry46 : TLBEntry; + TLBEntry45 : TLBEntry; + TLBEntry44 : TLBEntry; + TLBEntry43 : TLBEntry; + TLBEntry42 : TLBEntry; + TLBEntry41 : TLBEntry; + TLBEntry40 : TLBEntry; + TLBEntry39 : TLBEntry; + TLBEntry38 : TLBEntry; + TLBEntry37 : TLBEntry; + TLBEntry36 : TLBEntry; + TLBEntry35 : TLBEntry; + TLBEntry34 : TLBEntry; + TLBEntry33 : TLBEntry; + TLBEntry32 : TLBEntry; + TLBEntry31 : TLBEntry; + TLBEntry30 : TLBEntry; + TLBEntry29 : TLBEntry; + TLBEntry28 : TLBEntry; + TLBEntry27 : TLBEntry; + TLBEntry26 : TLBEntry; + TLBEntry25 : TLBEntry; + TLBEntry24 : TLBEntry; + TLBEntry23 : TLBEntry; + TLBEntry22 : TLBEntry; + TLBEntry21 : TLBEntry; + TLBEntry20 : TLBEntry; + TLBEntry19 : TLBEntry; + TLBEntry18 : TLBEntry; + TLBEntry17 : TLBEntry; + TLBEntry16 : TLBEntry; + TLBEntry15 : TLBEntry; + TLBEntry14 : TLBEntry; + TLBEntry13 : TLBEntry; + TLBEntry12 : TLBEntry; + TLBEntry11 : TLBEntry; + TLBEntry10 : TLBEntry; + TLBEntry09 : TLBEntry; + TLBEntry08 : TLBEntry; + TLBEntry07 : TLBEntry; + TLBEntry06 : TLBEntry; + TLBEntry05 : TLBEntry; + TLBEntry04 : TLBEntry; + TLBEntry03 : TLBEntry; + TLBEntry02 : TLBEntry; + TLBEntry01 : TLBEntry; + TLBEntry00 : TLBEntry; + TLBXContext : XContextReg; + TLBEntryHi : TLBEntryHiReg; + TLBWired : mword 6; + TLBPageMask : mword 16; + TLBContext : ContextReg; + TLBEntryLo1 : TLBEntryLoReg; + TLBEntryLo0 : TLBEntryLoReg; + TLBRandom : mword 6; + TLBIndex : mword 6; + TLBProbe : mword 1; + NextPC : mword 64; + PC : mword 64; }. +Notation "{[ r 'with' 'CID' := e ]}" := ({| CID := e; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CapCause' := e ]}" := ({| CapCause := e; CID := CID r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'EPCC' := e ]}" := ({| EPCC := e; CID := CID r; CapCause := CapCause r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'KDC' := e ]}" := ({| KDC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'KCC' := e ]}" := ({| KCC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'KR2C' := e ]}" := ({| KR2C := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'KR1C' := e ]}" := ({| KR1C := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CTLSP' := e ]}" := ({| CTLSP := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CTLSU' := e ]}" := ({| CTLSU := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C31' := e ]}" := ({| C31 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C30' := e ]}" := ({| C30 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C29' := e ]}" := ({| C29 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C28' := e ]}" := ({| C28 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C27' := e ]}" := ({| C27 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C26' := e ]}" := ({| C26 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C25' := e ]}" := ({| C25 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C24' := e ]}" := ({| C24 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C23' := e ]}" := ({| C23 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C22' := e ]}" := ({| C22 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C21' := e ]}" := ({| C21 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C20' := e ]}" := ({| C20 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C19' := e ]}" := ({| C19 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C18' := e ]}" := ({| C18 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C17' := e ]}" := ({| C17 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C16' := e ]}" := ({| C16 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C15' := e ]}" := ({| C15 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C14' := e ]}" := ({| C14 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C13' := e ]}" := ({| C13 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C12' := e ]}" := ({| C12 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C11' := e ]}" := ({| C11 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C10' := e ]}" := ({| C10 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C09' := e ]}" := ({| C09 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C08' := e ]}" := ({| C08 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C07' := e ]}" := ({| C07 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C06' := e ]}" := ({| C06 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C05' := e ]}" := ({| C05 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C04' := e ]}" := ({| C04 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C03' := e ]}" := ({| C03 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C02' := e ]}" := ({| C02 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'C01' := e ]}" := ({| C01 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'DDC' := e ]}" := ({| DDC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'DelayedPCC' := e ]}" := ({| DelayedPCC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'NextPCC' := e ]}" := ({| NextPCC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'PCC' := e ]}" := ({| PCC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_RVALID' := e ]}" := ({| UART_RVALID := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_RDATA' := e ]}" := ({| UART_RDATA := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_WRITTEN' := e ]}" := ({| UART_WRITTEN := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_WDATA' := e ]}" := ({| UART_WDATA := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'GPR' := e ]}" := ({| GPR := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'LO' := e ]}" := ({| LO := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'HI' := e ]}" := ({| HI := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'DelayedPC' := e ]}" := ({| DelayedPC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'BranchPending' := e ]}" := ({| BranchPending := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'InBranchDelay' := e ]}" := ({| InBranchDelay := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'NextInBranchDelay' := e ]}" := ({| NextInBranchDelay := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Status' := e ]}" := ({| CP0Status := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0ConfigK0' := e ]}" := ({| CP0ConfigK0 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0UserLocal' := e ]}" := ({| CP0UserLocal := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0HWREna' := e ]}" := ({| CP0HWREna := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Count' := e ]}" := ({| CP0Count := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0BadInstrP' := e ]}" := ({| CP0BadInstrP := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0BadInstr' := e ]}" := ({| CP0BadInstr := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'LastInstrBits' := e ]}" := ({| LastInstrBits := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CurrentInstrBits' := e ]}" := ({| CurrentInstrBits := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0BadVAddr' := e ]}" := ({| CP0BadVAddr := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0LLAddr' := e ]}" := ({| CP0LLAddr := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0LLBit' := e ]}" := ({| CP0LLBit := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0ErrorEPC' := e ]}" := ({| CP0ErrorEPC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0EPC' := e ]}" := ({| CP0EPC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Cause' := e ]}" := ({| CP0Cause := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Compare' := e ]}" := ({| CP0Compare := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry63' := e ]}" := ({| TLBEntry63 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry62' := e ]}" := ({| TLBEntry62 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry61' := e ]}" := ({| TLBEntry61 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry60' := e ]}" := ({| TLBEntry60 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry59' := e ]}" := ({| TLBEntry59 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry58' := e ]}" := ({| TLBEntry58 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry57' := e ]}" := ({| TLBEntry57 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry56' := e ]}" := ({| TLBEntry56 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry55' := e ]}" := ({| TLBEntry55 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry54' := e ]}" := ({| TLBEntry54 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry53' := e ]}" := ({| TLBEntry53 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry52' := e ]}" := ({| TLBEntry52 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry51' := e ]}" := ({| TLBEntry51 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry50' := e ]}" := ({| TLBEntry50 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry49' := e ]}" := ({| TLBEntry49 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry48' := e ]}" := ({| TLBEntry48 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry47' := e ]}" := ({| TLBEntry47 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry46' := e ]}" := ({| TLBEntry46 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry45' := e ]}" := ({| TLBEntry45 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry44' := e ]}" := ({| TLBEntry44 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry43' := e ]}" := ({| TLBEntry43 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry42' := e ]}" := ({| TLBEntry42 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry41' := e ]}" := ({| TLBEntry41 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry40' := e ]}" := ({| TLBEntry40 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry39' := e ]}" := ({| TLBEntry39 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry38' := e ]}" := ({| TLBEntry38 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry37' := e ]}" := ({| TLBEntry37 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry36' := e ]}" := ({| TLBEntry36 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry35' := e ]}" := ({| TLBEntry35 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry34' := e ]}" := ({| TLBEntry34 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry33' := e ]}" := ({| TLBEntry33 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry32' := e ]}" := ({| TLBEntry32 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry31' := e ]}" := ({| TLBEntry31 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry30' := e ]}" := ({| TLBEntry30 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry29' := e ]}" := ({| TLBEntry29 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry28' := e ]}" := ({| TLBEntry28 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry27' := e ]}" := ({| TLBEntry27 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry26' := e ]}" := ({| TLBEntry26 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry25' := e ]}" := ({| TLBEntry25 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry24' := e ]}" := ({| TLBEntry24 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry23' := e ]}" := ({| TLBEntry23 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry22' := e ]}" := ({| TLBEntry22 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry21' := e ]}" := ({| TLBEntry21 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry20' := e ]}" := ({| TLBEntry20 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry19' := e ]}" := ({| TLBEntry19 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry18' := e ]}" := ({| TLBEntry18 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry17' := e ]}" := ({| TLBEntry17 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry16' := e ]}" := ({| TLBEntry16 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry15' := e ]}" := ({| TLBEntry15 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry14' := e ]}" := ({| TLBEntry14 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry13' := e ]}" := ({| TLBEntry13 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry12' := e ]}" := ({| TLBEntry12 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry11' := e ]}" := ({| TLBEntry11 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry10' := e ]}" := ({| TLBEntry10 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry09' := e ]}" := ({| TLBEntry09 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry08' := e ]}" := ({| TLBEntry08 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry07' := e ]}" := ({| TLBEntry07 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry06' := e ]}" := ({| TLBEntry06 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry05' := e ]}" := ({| TLBEntry05 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry04' := e ]}" := ({| TLBEntry04 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry03' := e ]}" := ({| TLBEntry03 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry02' := e ]}" := ({| TLBEntry02 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry01' := e ]}" := ({| TLBEntry01 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry00' := e ]}" := ({| TLBEntry00 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBXContext' := e ]}" := ({| TLBXContext := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntryHi' := e ]}" := ({| TLBEntryHi := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBWired' := e ]}" := ({| TLBWired := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBPageMask' := e ]}" := ({| TLBPageMask := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBContext' := e ]}" := ({| TLBContext := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntryLo1' := e ]}" := ({| TLBEntryLo1 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntryLo0' := e ]}" := ({| TLBEntryLo0 := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBRandom' := e ]}" := ({| TLBRandom := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBIndex' := e ]}" := ({| TLBIndex := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBProbe' := e ]}" := ({| TLBProbe := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'NextPC' := e ]}" := ({| NextPC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; PC := PC r |}). +Notation "{[ r 'with' 'PC' := e ]}" := ({| PC := e; CID := CID r; CapCause := CapCause r; EPCC := EPCC r; KDC := KDC r; KCC := KCC r; KR2C := KR2C r; KR1C := KR1C r; CTLSP := CTLSP r; CTLSU := CTLSU r; C31 := C31 r; C30 := C30 r; C29 := C29 r; C28 := C28 r; C27 := C27 r; C26 := C26 r; C25 := C25 r; C24 := C24 r; C23 := C23 r; C22 := C22 r; C21 := C21 r; C20 := C20 r; C19 := C19 r; C18 := C18 r; C17 := C17 r; C16 := C16 r; C15 := C15 r; C14 := C14 r; C13 := C13 r; C12 := C12 r; C11 := C11 r; C10 := C10 r; C09 := C09 r; C08 := C08 r; C07 := C07 r; C06 := C06 r; C05 := C05 r; C04 := C04 r; C03 := C03 r; C02 := C02 r; C01 := C01 r; DDC := DDC r; DelayedPCC := DelayedPCC r; NextPCC := NextPCC r; PCC := PCC r; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r |}). + + + +Definition CapCauseReg_of_regval (merge_var : register_value) +: option CapCauseReg := + + match merge_var with | Regval_CapCauseReg (v) => Some (v) | g__15 => None end. + +Definition regval_of_CapCauseReg (v : CapCauseReg) : register_value := Regval_CapCauseReg (v). + +Definition Capability_of_regval (merge_var : register_value) +: option Capability := + + match merge_var with | Regval_Capability (v) => Some (v) | g__14 => None end. + +Definition regval_of_Capability (v : Capability) : register_value := Regval_Capability (v). + +Definition CauseReg_of_regval (merge_var : register_value) +: option CauseReg := + + match merge_var with | Regval_CauseReg (v) => Some (v) | g__13 => None end. + +Definition regval_of_CauseReg (v : CauseReg) : register_value := Regval_CauseReg (v). + +Definition ContextReg_of_regval (merge_var : register_value) +: option ContextReg := + + match merge_var with | Regval_ContextReg (v) => Some (v) | g__12 => None end. + +Definition regval_of_ContextReg (v : ContextReg) : register_value := Regval_ContextReg (v). + +Definition StatusReg_of_regval (merge_var : register_value) +: option StatusReg := + + match merge_var with | Regval_StatusReg (v) => Some (v) | g__11 => None end. + +Definition regval_of_StatusReg (v : StatusReg) : register_value := Regval_StatusReg (v). + +Definition TLBEntry_of_regval (merge_var : register_value) +: option TLBEntry := + + match merge_var with | Regval_TLBEntry (v) => Some (v) | g__10 => None end. + +Definition regval_of_TLBEntry (v : TLBEntry) : register_value := Regval_TLBEntry (v). + +Definition TLBEntryHiReg_of_regval (merge_var : register_value) +: option TLBEntryHiReg := + + match merge_var with | Regval_TLBEntryHiReg (v) => Some (v) | g__9 => None end. + +Definition regval_of_TLBEntryHiReg (v : TLBEntryHiReg) +: register_value := + + Regval_TLBEntryHiReg + (v). + +Definition TLBEntryLoReg_of_regval (merge_var : register_value) +: option TLBEntryLoReg := + + match merge_var with | Regval_TLBEntryLoReg (v) => Some (v) | g__8 => None end. + +Definition regval_of_TLBEntryLoReg (v : TLBEntryLoReg) +: register_value := + + Regval_TLBEntryLoReg + (v). + +Definition XContextReg_of_regval (merge_var : register_value) +: option XContextReg := + + match merge_var with | Regval_XContextReg (v) => Some (v) | g__7 => None end. + +Definition regval_of_XContextReg (v : XContextReg) : register_value := Regval_XContextReg (v). + +Definition vector_16_dec_bit_of_regval (merge_var : register_value) +: option (mword 16) := + + match merge_var with | Regval_vector_16_dec_bit (v) => Some (v) | g__6 => None end. + +Definition regval_of_vector_16_dec_bit (v : mword 16) +: register_value := + + Regval_vector_16_dec_bit + (v). + +Definition vector_1_dec_bit_of_regval (merge_var : register_value) +: option (mword 1) := + + match merge_var with | Regval_vector_1_dec_bit (v) => Some (v) | g__5 => None end. + +Definition regval_of_vector_1_dec_bit (v : mword 1) +: register_value := + + Regval_vector_1_dec_bit + (v). + +Definition vector_32_dec_bit_of_regval (merge_var : register_value) +: option (mword 32) := + + match merge_var with | Regval_vector_32_dec_bit (v) => Some (v) | g__4 => None end. + +Definition regval_of_vector_32_dec_bit (v : mword 32) +: register_value := + + Regval_vector_32_dec_bit + (v). + +Definition vector_3_dec_bit_of_regval (merge_var : register_value) +: option (mword 3) := + + match merge_var with | Regval_vector_3_dec_bit (v) => Some (v) | g__3 => None end. + +Definition regval_of_vector_3_dec_bit (v : mword 3) +: register_value := + + Regval_vector_3_dec_bit + (v). + +Definition vector_64_dec_bit_of_regval (merge_var : register_value) +: option (mword 64) := + + match merge_var with | Regval_vector_64_dec_bit (v) => Some (v) | g__2 => None end. + +Definition regval_of_vector_64_dec_bit (v : mword 64) +: register_value := + + Regval_vector_64_dec_bit + (v). + +Definition vector_6_dec_bit_of_regval (merge_var : register_value) +: option (mword 6) := + + match merge_var with | Regval_vector_6_dec_bit (v) => Some (v) | g__1 => None end. + +Definition regval_of_vector_6_dec_bit (v : mword 6) +: register_value := + + Regval_vector_6_dec_bit + (v). + +Definition vector_8_dec_bit_of_regval (merge_var : register_value) +: option (mword 8) := + + match merge_var with | Regval_vector_8_dec_bit (v) => Some (v) | g__0 => None end. + +Definition regval_of_vector_8_dec_bit (v : mword 8) +: register_value := + + Regval_vector_8_dec_bit + (v). + + + +Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with + | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None + | _ => None +end. + +Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)). + +Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with + | Regval_list v => just_list (List.map of_regval v) + | _ => None +end. + +Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs). + +Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with + | Regval_option v => option_map of_regval v + | _ => None +end. + +Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v). + + +Definition CID_ref := {| + name := "CID"; + read_from := (fun s => s.(CID)); + write_to := (fun v s => ({[ s with CID := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CapCause_ref := {| + name := "CapCause"; + read_from := (fun s => s.(CapCause)); + write_to := (fun v s => ({[ s with CapCause := v ]})); + of_regval := (fun v => CapCauseReg_of_regval v); + regval_of := (fun v => regval_of_CapCauseReg v) |}. + +Definition KDC_ref := {| + name := "KDC"; + read_from := (fun s => s.(KDC)); + write_to := (fun v s => ({[ s with KDC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition KR2C_ref := {| + name := "KR2C"; + read_from := (fun s => s.(KR2C)); + write_to := (fun v s => ({[ s with KR2C := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition KR1C_ref := {| + name := "KR1C"; + read_from := (fun s => s.(KR1C)); + write_to := (fun v s => ({[ s with KR1C := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition CTLSP_ref := {| + name := "CTLSP"; + read_from := (fun s => s.(CTLSP)); + write_to := (fun v s => ({[ s with CTLSP := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition CTLSU_ref := {| + name := "CTLSU"; + read_from := (fun s => s.(CTLSU)); + write_to := (fun v s => ({[ s with CTLSU := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C31_ref := {| + name := "C31"; + read_from := (fun s => s.(C31)); + write_to := (fun v s => ({[ s with C31 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C30_ref := {| + name := "C30"; + read_from := (fun s => s.(C30)); + write_to := (fun v s => ({[ s with C30 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C29_ref := {| + name := "C29"; + read_from := (fun s => s.(C29)); + write_to := (fun v s => ({[ s with C29 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C28_ref := {| + name := "C28"; + read_from := (fun s => s.(C28)); + write_to := (fun v s => ({[ s with C28 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C27_ref := {| + name := "C27"; + read_from := (fun s => s.(C27)); + write_to := (fun v s => ({[ s with C27 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C26_ref := {| + name := "C26"; + read_from := (fun s => s.(C26)); + write_to := (fun v s => ({[ s with C26 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C25_ref := {| + name := "C25"; + read_from := (fun s => s.(C25)); + write_to := (fun v s => ({[ s with C25 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C24_ref := {| + name := "C24"; + read_from := (fun s => s.(C24)); + write_to := (fun v s => ({[ s with C24 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C23_ref := {| + name := "C23"; + read_from := (fun s => s.(C23)); + write_to := (fun v s => ({[ s with C23 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C22_ref := {| + name := "C22"; + read_from := (fun s => s.(C22)); + write_to := (fun v s => ({[ s with C22 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C21_ref := {| + name := "C21"; + read_from := (fun s => s.(C21)); + write_to := (fun v s => ({[ s with C21 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C20_ref := {| + name := "C20"; + read_from := (fun s => s.(C20)); + write_to := (fun v s => ({[ s with C20 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C19_ref := {| + name := "C19"; + read_from := (fun s => s.(C19)); + write_to := (fun v s => ({[ s with C19 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C18_ref := {| + name := "C18"; + read_from := (fun s => s.(C18)); + write_to := (fun v s => ({[ s with C18 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C17_ref := {| + name := "C17"; + read_from := (fun s => s.(C17)); + write_to := (fun v s => ({[ s with C17 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C16_ref := {| + name := "C16"; + read_from := (fun s => s.(C16)); + write_to := (fun v s => ({[ s with C16 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C15_ref := {| + name := "C15"; + read_from := (fun s => s.(C15)); + write_to := (fun v s => ({[ s with C15 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C14_ref := {| + name := "C14"; + read_from := (fun s => s.(C14)); + write_to := (fun v s => ({[ s with C14 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C13_ref := {| + name := "C13"; + read_from := (fun s => s.(C13)); + write_to := (fun v s => ({[ s with C13 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C12_ref := {| + name := "C12"; + read_from := (fun s => s.(C12)); + write_to := (fun v s => ({[ s with C12 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C11_ref := {| + name := "C11"; + read_from := (fun s => s.(C11)); + write_to := (fun v s => ({[ s with C11 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C10_ref := {| + name := "C10"; + read_from := (fun s => s.(C10)); + write_to := (fun v s => ({[ s with C10 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C09_ref := {| + name := "C09"; + read_from := (fun s => s.(C09)); + write_to := (fun v s => ({[ s with C09 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C08_ref := {| + name := "C08"; + read_from := (fun s => s.(C08)); + write_to := (fun v s => ({[ s with C08 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C07_ref := {| + name := "C07"; + read_from := (fun s => s.(C07)); + write_to := (fun v s => ({[ s with C07 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C06_ref := {| + name := "C06"; + read_from := (fun s => s.(C06)); + write_to := (fun v s => ({[ s with C06 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C05_ref := {| + name := "C05"; + read_from := (fun s => s.(C05)); + write_to := (fun v s => ({[ s with C05 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C04_ref := {| + name := "C04"; + read_from := (fun s => s.(C04)); + write_to := (fun v s => ({[ s with C04 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C03_ref := {| + name := "C03"; + read_from := (fun s => s.(C03)); + write_to := (fun v s => ({[ s with C03 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C02_ref := {| + name := "C02"; + read_from := (fun s => s.(C02)); + write_to := (fun v s => ({[ s with C02 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition C01_ref := {| + name := "C01"; + read_from := (fun s => s.(C01)); + write_to := (fun v s => ({[ s with C01 := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition DDC_ref := {| + name := "DDC"; + read_from := (fun s => s.(DDC)); + write_to := (fun v s => ({[ s with DDC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition NextPCC_ref := {| + name := "NextPCC"; + read_from := (fun s => s.(NextPCC)); + write_to := (fun v s => ({[ s with NextPCC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition DelayedPCC_ref := {| + name := "DelayedPCC"; + read_from := (fun s => s.(DelayedPCC)); + write_to := (fun v s => ({[ s with DelayedPCC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition PCC_ref := {| + name := "PCC"; + read_from := (fun s => s.(PCC)); + write_to := (fun v s => ({[ s with PCC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition KCC_ref := {| + name := "KCC"; + read_from := (fun s => s.(KCC)); + write_to := (fun v s => ({[ s with KCC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition EPCC_ref := {| + name := "EPCC"; + read_from := (fun s => s.(EPCC)); + write_to := (fun v s => ({[ s with EPCC := v ]})); + of_regval := (fun v => Capability_of_regval v); + regval_of := (fun v => regval_of_Capability v) |}. + +Definition UART_RVALID_ref := {| + name := "UART_RVALID"; + read_from := (fun s => s.(UART_RVALID)); + write_to := (fun v s => ({[ s with UART_RVALID := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition UART_RDATA_ref := {| + name := "UART_RDATA"; + read_from := (fun s => s.(UART_RDATA)); + write_to := (fun v s => ({[ s with UART_RDATA := v ]})); + of_regval := (fun v => vector_8_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_8_dec_bit v) |}. + +Definition UART_WRITTEN_ref := {| + name := "UART_WRITTEN"; + read_from := (fun s => s.(UART_WRITTEN)); + write_to := (fun v s => ({[ s with UART_WRITTEN := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition UART_WDATA_ref := {| + name := "UART_WDATA"; + read_from := (fun s => s.(UART_WDATA)); + write_to := (fun v s => ({[ s with UART_WDATA := v ]})); + of_regval := (fun v => vector_8_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_8_dec_bit v) |}. + +Definition GPR_ref := {| + name := "GPR"; + read_from := (fun s => s.(GPR)); + write_to := (fun v s => ({[ s with GPR := v ]})); + of_regval := (fun v => vector_of_regval 32 (fun v => vector_64_dec_bit_of_regval v) v); + regval_of := (fun v => regval_of_vector (fun v => regval_of_vector_64_dec_bit v) 32 false v) |}. + +Definition LO_ref := {| + name := "LO"; + read_from := (fun s => s.(LO)); + write_to := (fun v s => ({[ s with LO := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition HI_ref := {| + name := "HI"; + read_from := (fun s => s.(HI)); + write_to := (fun v s => ({[ s with HI := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition DelayedPC_ref := {| + name := "DelayedPC"; + read_from := (fun s => s.(DelayedPC)); + write_to := (fun v s => ({[ s with DelayedPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition BranchPending_ref := {| + name := "BranchPending"; + read_from := (fun s => s.(BranchPending)); + write_to := (fun v s => ({[ s with BranchPending := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition InBranchDelay_ref := {| + name := "InBranchDelay"; + read_from := (fun s => s.(InBranchDelay)); + write_to := (fun v s => ({[ s with InBranchDelay := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition NextInBranchDelay_ref := {| + name := "NextInBranchDelay"; + read_from := (fun s => s.(NextInBranchDelay)); + write_to := (fun v s => ({[ s with NextInBranchDelay := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition CP0Status_ref := {| + name := "CP0Status"; + read_from := (fun s => s.(CP0Status)); + write_to := (fun v s => ({[ s with CP0Status := v ]})); + of_regval := (fun v => StatusReg_of_regval v); + regval_of := (fun v => regval_of_StatusReg v) |}. + +Definition CP0ConfigK0_ref := {| + name := "CP0ConfigK0"; + read_from := (fun s => s.(CP0ConfigK0)); + write_to := (fun v s => ({[ s with CP0ConfigK0 := v ]})); + of_regval := (fun v => vector_3_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_3_dec_bit v) |}. + +Definition CP0UserLocal_ref := {| + name := "CP0UserLocal"; + read_from := (fun s => s.(CP0UserLocal)); + write_to := (fun v s => ({[ s with CP0UserLocal := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0HWREna_ref := {| + name := "CP0HWREna"; + read_from := (fun s => s.(CP0HWREna)); + write_to := (fun v s => ({[ s with CP0HWREna := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0Count_ref := {| + name := "CP0Count"; + read_from := (fun s => s.(CP0Count)); + write_to := (fun v s => ({[ s with CP0Count := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0BadInstrP_ref := {| + name := "CP0BadInstrP"; + read_from := (fun s => s.(CP0BadInstrP)); + write_to := (fun v s => ({[ s with CP0BadInstrP := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0BadInstr_ref := {| + name := "CP0BadInstr"; + read_from := (fun s => s.(CP0BadInstr)); + write_to := (fun v s => ({[ s with CP0BadInstr := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition LastInstrBits_ref := {| + name := "LastInstrBits"; + read_from := (fun s => s.(LastInstrBits)); + write_to := (fun v s => ({[ s with LastInstrBits := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CurrentInstrBits_ref := {| + name := "CurrentInstrBits"; + read_from := (fun s => s.(CurrentInstrBits)); + write_to := (fun v s => ({[ s with CurrentInstrBits := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0BadVAddr_ref := {| + name := "CP0BadVAddr"; + read_from := (fun s => s.(CP0BadVAddr)); + write_to := (fun v s => ({[ s with CP0BadVAddr := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0LLAddr_ref := {| + name := "CP0LLAddr"; + read_from := (fun s => s.(CP0LLAddr)); + write_to := (fun v s => ({[ s with CP0LLAddr := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0LLBit_ref := {| + name := "CP0LLBit"; + read_from := (fun s => s.(CP0LLBit)); + write_to := (fun v s => ({[ s with CP0LLBit := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition CP0ErrorEPC_ref := {| + name := "CP0ErrorEPC"; + read_from := (fun s => s.(CP0ErrorEPC)); + write_to := (fun v s => ({[ s with CP0ErrorEPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0EPC_ref := {| + name := "CP0EPC"; + read_from := (fun s => s.(CP0EPC)); + write_to := (fun v s => ({[ s with CP0EPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0Cause_ref := {| + name := "CP0Cause"; + read_from := (fun s => s.(CP0Cause)); + write_to := (fun v s => ({[ s with CP0Cause := v ]})); + of_regval := (fun v => CauseReg_of_regval v); + regval_of := (fun v => regval_of_CauseReg v) |}. + +Definition CP0Compare_ref := {| + name := "CP0Compare"; + read_from := (fun s => s.(CP0Compare)); + write_to := (fun v s => ({[ s with CP0Compare := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition TLBEntry63_ref := {| + name := "TLBEntry63"; + read_from := (fun s => s.(TLBEntry63)); + write_to := (fun v s => ({[ s with TLBEntry63 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry62_ref := {| + name := "TLBEntry62"; + read_from := (fun s => s.(TLBEntry62)); + write_to := (fun v s => ({[ s with TLBEntry62 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry61_ref := {| + name := "TLBEntry61"; + read_from := (fun s => s.(TLBEntry61)); + write_to := (fun v s => ({[ s with TLBEntry61 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry60_ref := {| + name := "TLBEntry60"; + read_from := (fun s => s.(TLBEntry60)); + write_to := (fun v s => ({[ s with TLBEntry60 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry59_ref := {| + name := "TLBEntry59"; + read_from := (fun s => s.(TLBEntry59)); + write_to := (fun v s => ({[ s with TLBEntry59 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry58_ref := {| + name := "TLBEntry58"; + read_from := (fun s => s.(TLBEntry58)); + write_to := (fun v s => ({[ s with TLBEntry58 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry57_ref := {| + name := "TLBEntry57"; + read_from := (fun s => s.(TLBEntry57)); + write_to := (fun v s => ({[ s with TLBEntry57 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry56_ref := {| + name := "TLBEntry56"; + read_from := (fun s => s.(TLBEntry56)); + write_to := (fun v s => ({[ s with TLBEntry56 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry55_ref := {| + name := "TLBEntry55"; + read_from := (fun s => s.(TLBEntry55)); + write_to := (fun v s => ({[ s with TLBEntry55 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry54_ref := {| + name := "TLBEntry54"; + read_from := (fun s => s.(TLBEntry54)); + write_to := (fun v s => ({[ s with TLBEntry54 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry53_ref := {| + name := "TLBEntry53"; + read_from := (fun s => s.(TLBEntry53)); + write_to := (fun v s => ({[ s with TLBEntry53 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry52_ref := {| + name := "TLBEntry52"; + read_from := (fun s => s.(TLBEntry52)); + write_to := (fun v s => ({[ s with TLBEntry52 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry51_ref := {| + name := "TLBEntry51"; + read_from := (fun s => s.(TLBEntry51)); + write_to := (fun v s => ({[ s with TLBEntry51 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry50_ref := {| + name := "TLBEntry50"; + read_from := (fun s => s.(TLBEntry50)); + write_to := (fun v s => ({[ s with TLBEntry50 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry49_ref := {| + name := "TLBEntry49"; + read_from := (fun s => s.(TLBEntry49)); + write_to := (fun v s => ({[ s with TLBEntry49 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry48_ref := {| + name := "TLBEntry48"; + read_from := (fun s => s.(TLBEntry48)); + write_to := (fun v s => ({[ s with TLBEntry48 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry47_ref := {| + name := "TLBEntry47"; + read_from := (fun s => s.(TLBEntry47)); + write_to := (fun v s => ({[ s with TLBEntry47 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry46_ref := {| + name := "TLBEntry46"; + read_from := (fun s => s.(TLBEntry46)); + write_to := (fun v s => ({[ s with TLBEntry46 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry45_ref := {| + name := "TLBEntry45"; + read_from := (fun s => s.(TLBEntry45)); + write_to := (fun v s => ({[ s with TLBEntry45 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry44_ref := {| + name := "TLBEntry44"; + read_from := (fun s => s.(TLBEntry44)); + write_to := (fun v s => ({[ s with TLBEntry44 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry43_ref := {| + name := "TLBEntry43"; + read_from := (fun s => s.(TLBEntry43)); + write_to := (fun v s => ({[ s with TLBEntry43 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry42_ref := {| + name := "TLBEntry42"; + read_from := (fun s => s.(TLBEntry42)); + write_to := (fun v s => ({[ s with TLBEntry42 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry41_ref := {| + name := "TLBEntry41"; + read_from := (fun s => s.(TLBEntry41)); + write_to := (fun v s => ({[ s with TLBEntry41 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry40_ref := {| + name := "TLBEntry40"; + read_from := (fun s => s.(TLBEntry40)); + write_to := (fun v s => ({[ s with TLBEntry40 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry39_ref := {| + name := "TLBEntry39"; + read_from := (fun s => s.(TLBEntry39)); + write_to := (fun v s => ({[ s with TLBEntry39 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry38_ref := {| + name := "TLBEntry38"; + read_from := (fun s => s.(TLBEntry38)); + write_to := (fun v s => ({[ s with TLBEntry38 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry37_ref := {| + name := "TLBEntry37"; + read_from := (fun s => s.(TLBEntry37)); + write_to := (fun v s => ({[ s with TLBEntry37 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry36_ref := {| + name := "TLBEntry36"; + read_from := (fun s => s.(TLBEntry36)); + write_to := (fun v s => ({[ s with TLBEntry36 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry35_ref := {| + name := "TLBEntry35"; + read_from := (fun s => s.(TLBEntry35)); + write_to := (fun v s => ({[ s with TLBEntry35 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry34_ref := {| + name := "TLBEntry34"; + read_from := (fun s => s.(TLBEntry34)); + write_to := (fun v s => ({[ s with TLBEntry34 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry33_ref := {| + name := "TLBEntry33"; + read_from := (fun s => s.(TLBEntry33)); + write_to := (fun v s => ({[ s with TLBEntry33 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry32_ref := {| + name := "TLBEntry32"; + read_from := (fun s => s.(TLBEntry32)); + write_to := (fun v s => ({[ s with TLBEntry32 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry31_ref := {| + name := "TLBEntry31"; + read_from := (fun s => s.(TLBEntry31)); + write_to := (fun v s => ({[ s with TLBEntry31 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry30_ref := {| + name := "TLBEntry30"; + read_from := (fun s => s.(TLBEntry30)); + write_to := (fun v s => ({[ s with TLBEntry30 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry29_ref := {| + name := "TLBEntry29"; + read_from := (fun s => s.(TLBEntry29)); + write_to := (fun v s => ({[ s with TLBEntry29 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry28_ref := {| + name := "TLBEntry28"; + read_from := (fun s => s.(TLBEntry28)); + write_to := (fun v s => ({[ s with TLBEntry28 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry27_ref := {| + name := "TLBEntry27"; + read_from := (fun s => s.(TLBEntry27)); + write_to := (fun v s => ({[ s with TLBEntry27 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry26_ref := {| + name := "TLBEntry26"; + read_from := (fun s => s.(TLBEntry26)); + write_to := (fun v s => ({[ s with TLBEntry26 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry25_ref := {| + name := "TLBEntry25"; + read_from := (fun s => s.(TLBEntry25)); + write_to := (fun v s => ({[ s with TLBEntry25 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry24_ref := {| + name := "TLBEntry24"; + read_from := (fun s => s.(TLBEntry24)); + write_to := (fun v s => ({[ s with TLBEntry24 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry23_ref := {| + name := "TLBEntry23"; + read_from := (fun s => s.(TLBEntry23)); + write_to := (fun v s => ({[ s with TLBEntry23 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry22_ref := {| + name := "TLBEntry22"; + read_from := (fun s => s.(TLBEntry22)); + write_to := (fun v s => ({[ s with TLBEntry22 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry21_ref := {| + name := "TLBEntry21"; + read_from := (fun s => s.(TLBEntry21)); + write_to := (fun v s => ({[ s with TLBEntry21 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry20_ref := {| + name := "TLBEntry20"; + read_from := (fun s => s.(TLBEntry20)); + write_to := (fun v s => ({[ s with TLBEntry20 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry19_ref := {| + name := "TLBEntry19"; + read_from := (fun s => s.(TLBEntry19)); + write_to := (fun v s => ({[ s with TLBEntry19 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry18_ref := {| + name := "TLBEntry18"; + read_from := (fun s => s.(TLBEntry18)); + write_to := (fun v s => ({[ s with TLBEntry18 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry17_ref := {| + name := "TLBEntry17"; + read_from := (fun s => s.(TLBEntry17)); + write_to := (fun v s => ({[ s with TLBEntry17 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry16_ref := {| + name := "TLBEntry16"; + read_from := (fun s => s.(TLBEntry16)); + write_to := (fun v s => ({[ s with TLBEntry16 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry15_ref := {| + name := "TLBEntry15"; + read_from := (fun s => s.(TLBEntry15)); + write_to := (fun v s => ({[ s with TLBEntry15 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry14_ref := {| + name := "TLBEntry14"; + read_from := (fun s => s.(TLBEntry14)); + write_to := (fun v s => ({[ s with TLBEntry14 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry13_ref := {| + name := "TLBEntry13"; + read_from := (fun s => s.(TLBEntry13)); + write_to := (fun v s => ({[ s with TLBEntry13 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry12_ref := {| + name := "TLBEntry12"; + read_from := (fun s => s.(TLBEntry12)); + write_to := (fun v s => ({[ s with TLBEntry12 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry11_ref := {| + name := "TLBEntry11"; + read_from := (fun s => s.(TLBEntry11)); + write_to := (fun v s => ({[ s with TLBEntry11 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry10_ref := {| + name := "TLBEntry10"; + read_from := (fun s => s.(TLBEntry10)); + write_to := (fun v s => ({[ s with TLBEntry10 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry09_ref := {| + name := "TLBEntry09"; + read_from := (fun s => s.(TLBEntry09)); + write_to := (fun v s => ({[ s with TLBEntry09 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry08_ref := {| + name := "TLBEntry08"; + read_from := (fun s => s.(TLBEntry08)); + write_to := (fun v s => ({[ s with TLBEntry08 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry07_ref := {| + name := "TLBEntry07"; + read_from := (fun s => s.(TLBEntry07)); + write_to := (fun v s => ({[ s with TLBEntry07 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry06_ref := {| + name := "TLBEntry06"; + read_from := (fun s => s.(TLBEntry06)); + write_to := (fun v s => ({[ s with TLBEntry06 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry05_ref := {| + name := "TLBEntry05"; + read_from := (fun s => s.(TLBEntry05)); + write_to := (fun v s => ({[ s with TLBEntry05 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry04_ref := {| + name := "TLBEntry04"; + read_from := (fun s => s.(TLBEntry04)); + write_to := (fun v s => ({[ s with TLBEntry04 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry03_ref := {| + name := "TLBEntry03"; + read_from := (fun s => s.(TLBEntry03)); + write_to := (fun v s => ({[ s with TLBEntry03 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry02_ref := {| + name := "TLBEntry02"; + read_from := (fun s => s.(TLBEntry02)); + write_to := (fun v s => ({[ s with TLBEntry02 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry01_ref := {| + name := "TLBEntry01"; + read_from := (fun s => s.(TLBEntry01)); + write_to := (fun v s => ({[ s with TLBEntry01 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry00_ref := {| + name := "TLBEntry00"; + read_from := (fun s => s.(TLBEntry00)); + write_to := (fun v s => ({[ s with TLBEntry00 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBXContext_ref := {| + name := "TLBXContext"; + read_from := (fun s => s.(TLBXContext)); + write_to := (fun v s => ({[ s with TLBXContext := v ]})); + of_regval := (fun v => XContextReg_of_regval v); + regval_of := (fun v => regval_of_XContextReg v) |}. + +Definition TLBEntryHi_ref := {| + name := "TLBEntryHi"; + read_from := (fun s => s.(TLBEntryHi)); + write_to := (fun v s => ({[ s with TLBEntryHi := v ]})); + of_regval := (fun v => TLBEntryHiReg_of_regval v); + regval_of := (fun v => regval_of_TLBEntryHiReg v) |}. + +Definition TLBWired_ref := {| + name := "TLBWired"; + read_from := (fun s => s.(TLBWired)); + write_to := (fun v s => ({[ s with TLBWired := v ]})); + of_regval := (fun v => vector_6_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. + +Definition TLBPageMask_ref := {| + name := "TLBPageMask"; + read_from := (fun s => s.(TLBPageMask)); + write_to := (fun v s => ({[ s with TLBPageMask := v ]})); + of_regval := (fun v => vector_16_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_16_dec_bit v) |}. + +Definition TLBContext_ref := {| + name := "TLBContext"; + read_from := (fun s => s.(TLBContext)); + write_to := (fun v s => ({[ s with TLBContext := v ]})); + of_regval := (fun v => ContextReg_of_regval v); + regval_of := (fun v => regval_of_ContextReg v) |}. + +Definition TLBEntryLo1_ref := {| + name := "TLBEntryLo1"; + read_from := (fun s => s.(TLBEntryLo1)); + write_to := (fun v s => ({[ s with TLBEntryLo1 := v ]})); + of_regval := (fun v => TLBEntryLoReg_of_regval v); + regval_of := (fun v => regval_of_TLBEntryLoReg v) |}. + +Definition TLBEntryLo0_ref := {| + name := "TLBEntryLo0"; + read_from := (fun s => s.(TLBEntryLo0)); + write_to := (fun v s => ({[ s with TLBEntryLo0 := v ]})); + of_regval := (fun v => TLBEntryLoReg_of_regval v); + regval_of := (fun v => regval_of_TLBEntryLoReg v) |}. + +Definition TLBRandom_ref := {| + name := "TLBRandom"; + read_from := (fun s => s.(TLBRandom)); + write_to := (fun v s => ({[ s with TLBRandom := v ]})); + of_regval := (fun v => vector_6_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. + +Definition TLBIndex_ref := {| + name := "TLBIndex"; + read_from := (fun s => s.(TLBIndex)); + write_to := (fun v s => ({[ s with TLBIndex := v ]})); + of_regval := (fun v => vector_6_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. + +Definition TLBProbe_ref := {| + name := "TLBProbe"; + read_from := (fun s => s.(TLBProbe)); + write_to := (fun v s => ({[ s with TLBProbe := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition NextPC_ref := {| + name := "NextPC"; + read_from := (fun s => s.(NextPC)); + write_to := (fun v s => ({[ s with NextPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition PC_ref := {| + name := "PC"; + read_from := (fun s => s.(PC)); + write_to := (fun v s => ({[ s with PC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Local Open Scope string. +Definition get_regval (reg_name : string) (s : regstate) : option register_value := + if string_dec reg_name "CID" then Some (CID_ref.(regval_of) (CID_ref.(read_from) s)) else + if string_dec reg_name "CapCause" then Some (CapCause_ref.(regval_of) (CapCause_ref.(read_from) s)) else + if string_dec reg_name "KDC" then Some (KDC_ref.(regval_of) (KDC_ref.(read_from) s)) else + if string_dec reg_name "KR2C" then Some (KR2C_ref.(regval_of) (KR2C_ref.(read_from) s)) else + if string_dec reg_name "KR1C" then Some (KR1C_ref.(regval_of) (KR1C_ref.(read_from) s)) else + if string_dec reg_name "CTLSP" then Some (CTLSP_ref.(regval_of) (CTLSP_ref.(read_from) s)) else + if string_dec reg_name "CTLSU" then Some (CTLSU_ref.(regval_of) (CTLSU_ref.(read_from) s)) else + if string_dec reg_name "C31" then Some (C31_ref.(regval_of) (C31_ref.(read_from) s)) else + if string_dec reg_name "C30" then Some (C30_ref.(regval_of) (C30_ref.(read_from) s)) else + if string_dec reg_name "C29" then Some (C29_ref.(regval_of) (C29_ref.(read_from) s)) else + if string_dec reg_name "C28" then Some (C28_ref.(regval_of) (C28_ref.(read_from) s)) else + if string_dec reg_name "C27" then Some (C27_ref.(regval_of) (C27_ref.(read_from) s)) else + if string_dec reg_name "C26" then Some (C26_ref.(regval_of) (C26_ref.(read_from) s)) else + if string_dec reg_name "C25" then Some (C25_ref.(regval_of) (C25_ref.(read_from) s)) else + if string_dec reg_name "C24" then Some (C24_ref.(regval_of) (C24_ref.(read_from) s)) else + if string_dec reg_name "C23" then Some (C23_ref.(regval_of) (C23_ref.(read_from) s)) else + if string_dec reg_name "C22" then Some (C22_ref.(regval_of) (C22_ref.(read_from) s)) else + if string_dec reg_name "C21" then Some (C21_ref.(regval_of) (C21_ref.(read_from) s)) else + if string_dec reg_name "C20" then Some (C20_ref.(regval_of) (C20_ref.(read_from) s)) else + if string_dec reg_name "C19" then Some (C19_ref.(regval_of) (C19_ref.(read_from) s)) else + if string_dec reg_name "C18" then Some (C18_ref.(regval_of) (C18_ref.(read_from) s)) else + if string_dec reg_name "C17" then Some (C17_ref.(regval_of) (C17_ref.(read_from) s)) else + if string_dec reg_name "C16" then Some (C16_ref.(regval_of) (C16_ref.(read_from) s)) else + if string_dec reg_name "C15" then Some (C15_ref.(regval_of) (C15_ref.(read_from) s)) else + if string_dec reg_name "C14" then Some (C14_ref.(regval_of) (C14_ref.(read_from) s)) else + if string_dec reg_name "C13" then Some (C13_ref.(regval_of) (C13_ref.(read_from) s)) else + if string_dec reg_name "C12" then Some (C12_ref.(regval_of) (C12_ref.(read_from) s)) else + if string_dec reg_name "C11" then Some (C11_ref.(regval_of) (C11_ref.(read_from) s)) else + if string_dec reg_name "C10" then Some (C10_ref.(regval_of) (C10_ref.(read_from) s)) else + if string_dec reg_name "C09" then Some (C09_ref.(regval_of) (C09_ref.(read_from) s)) else + if string_dec reg_name "C08" then Some (C08_ref.(regval_of) (C08_ref.(read_from) s)) else + if string_dec reg_name "C07" then Some (C07_ref.(regval_of) (C07_ref.(read_from) s)) else + if string_dec reg_name "C06" then Some (C06_ref.(regval_of) (C06_ref.(read_from) s)) else + if string_dec reg_name "C05" then Some (C05_ref.(regval_of) (C05_ref.(read_from) s)) else + if string_dec reg_name "C04" then Some (C04_ref.(regval_of) (C04_ref.(read_from) s)) else + if string_dec reg_name "C03" then Some (C03_ref.(regval_of) (C03_ref.(read_from) s)) else + if string_dec reg_name "C02" then Some (C02_ref.(regval_of) (C02_ref.(read_from) s)) else + if string_dec reg_name "C01" then Some (C01_ref.(regval_of) (C01_ref.(read_from) s)) else + if string_dec reg_name "DDC" then Some (DDC_ref.(regval_of) (DDC_ref.(read_from) s)) else + if string_dec reg_name "NextPCC" then Some (NextPCC_ref.(regval_of) (NextPCC_ref.(read_from) s)) else + if string_dec reg_name "DelayedPCC" then Some (DelayedPCC_ref.(regval_of) (DelayedPCC_ref.(read_from) s)) else + if string_dec reg_name "PCC" then Some (PCC_ref.(regval_of) (PCC_ref.(read_from) s)) else + if string_dec reg_name "KCC" then Some (KCC_ref.(regval_of) (KCC_ref.(read_from) s)) else + if string_dec reg_name "EPCC" then Some (EPCC_ref.(regval_of) (EPCC_ref.(read_from) s)) else + if string_dec reg_name "UART_RVALID" then Some (UART_RVALID_ref.(regval_of) (UART_RVALID_ref.(read_from) s)) else + if string_dec reg_name "UART_RDATA" then Some (UART_RDATA_ref.(regval_of) (UART_RDATA_ref.(read_from) s)) else + if string_dec reg_name "UART_WRITTEN" then Some (UART_WRITTEN_ref.(regval_of) (UART_WRITTEN_ref.(read_from) s)) else + if string_dec reg_name "UART_WDATA" then Some (UART_WDATA_ref.(regval_of) (UART_WDATA_ref.(read_from) s)) else + if string_dec reg_name "GPR" then Some (GPR_ref.(regval_of) (GPR_ref.(read_from) s)) else + if string_dec reg_name "LO" then Some (LO_ref.(regval_of) (LO_ref.(read_from) s)) else + if string_dec reg_name "HI" then Some (HI_ref.(regval_of) (HI_ref.(read_from) s)) else + if string_dec reg_name "DelayedPC" then Some (DelayedPC_ref.(regval_of) (DelayedPC_ref.(read_from) s)) else + if string_dec reg_name "BranchPending" then Some (BranchPending_ref.(regval_of) (BranchPending_ref.(read_from) s)) else + if string_dec reg_name "InBranchDelay" then Some (InBranchDelay_ref.(regval_of) (InBranchDelay_ref.(read_from) s)) else + if string_dec reg_name "NextInBranchDelay" then Some (NextInBranchDelay_ref.(regval_of) (NextInBranchDelay_ref.(read_from) s)) else + if string_dec reg_name "CP0Status" then Some (CP0Status_ref.(regval_of) (CP0Status_ref.(read_from) s)) else + if string_dec reg_name "CP0ConfigK0" then Some (CP0ConfigK0_ref.(regval_of) (CP0ConfigK0_ref.(read_from) s)) else + if string_dec reg_name "CP0UserLocal" then Some (CP0UserLocal_ref.(regval_of) (CP0UserLocal_ref.(read_from) s)) else + if string_dec reg_name "CP0HWREna" then Some (CP0HWREna_ref.(regval_of) (CP0HWREna_ref.(read_from) s)) else + if string_dec reg_name "CP0Count" then Some (CP0Count_ref.(regval_of) (CP0Count_ref.(read_from) s)) else + if string_dec reg_name "CP0BadInstrP" then Some (CP0BadInstrP_ref.(regval_of) (CP0BadInstrP_ref.(read_from) s)) else + if string_dec reg_name "CP0BadInstr" then Some (CP0BadInstr_ref.(regval_of) (CP0BadInstr_ref.(read_from) s)) else + if string_dec reg_name "LastInstrBits" then Some (LastInstrBits_ref.(regval_of) (LastInstrBits_ref.(read_from) s)) else + if string_dec reg_name "CurrentInstrBits" then Some (CurrentInstrBits_ref.(regval_of) (CurrentInstrBits_ref.(read_from) s)) else + if string_dec reg_name "CP0BadVAddr" then Some (CP0BadVAddr_ref.(regval_of) (CP0BadVAddr_ref.(read_from) s)) else + if string_dec reg_name "CP0LLAddr" then Some (CP0LLAddr_ref.(regval_of) (CP0LLAddr_ref.(read_from) s)) else + if string_dec reg_name "CP0LLBit" then Some (CP0LLBit_ref.(regval_of) (CP0LLBit_ref.(read_from) s)) else + if string_dec reg_name "CP0ErrorEPC" then Some (CP0ErrorEPC_ref.(regval_of) (CP0ErrorEPC_ref.(read_from) s)) else + if string_dec reg_name "CP0EPC" then Some (CP0EPC_ref.(regval_of) (CP0EPC_ref.(read_from) s)) else + if string_dec reg_name "CP0Cause" then Some (CP0Cause_ref.(regval_of) (CP0Cause_ref.(read_from) s)) else + if string_dec reg_name "CP0Compare" then Some (CP0Compare_ref.(regval_of) (CP0Compare_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry63" then Some (TLBEntry63_ref.(regval_of) (TLBEntry63_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry62" then Some (TLBEntry62_ref.(regval_of) (TLBEntry62_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry61" then Some (TLBEntry61_ref.(regval_of) (TLBEntry61_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry60" then Some (TLBEntry60_ref.(regval_of) (TLBEntry60_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry59" then Some (TLBEntry59_ref.(regval_of) (TLBEntry59_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry58" then Some (TLBEntry58_ref.(regval_of) (TLBEntry58_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry57" then Some (TLBEntry57_ref.(regval_of) (TLBEntry57_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry56" then Some (TLBEntry56_ref.(regval_of) (TLBEntry56_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry55" then Some (TLBEntry55_ref.(regval_of) (TLBEntry55_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry54" then Some (TLBEntry54_ref.(regval_of) (TLBEntry54_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry53" then Some (TLBEntry53_ref.(regval_of) (TLBEntry53_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry52" then Some (TLBEntry52_ref.(regval_of) (TLBEntry52_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry51" then Some (TLBEntry51_ref.(regval_of) (TLBEntry51_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry50" then Some (TLBEntry50_ref.(regval_of) (TLBEntry50_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry49" then Some (TLBEntry49_ref.(regval_of) (TLBEntry49_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry48" then Some (TLBEntry48_ref.(regval_of) (TLBEntry48_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry47" then Some (TLBEntry47_ref.(regval_of) (TLBEntry47_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry46" then Some (TLBEntry46_ref.(regval_of) (TLBEntry46_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry45" then Some (TLBEntry45_ref.(regval_of) (TLBEntry45_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry44" then Some (TLBEntry44_ref.(regval_of) (TLBEntry44_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry43" then Some (TLBEntry43_ref.(regval_of) (TLBEntry43_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry42" then Some (TLBEntry42_ref.(regval_of) (TLBEntry42_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry41" then Some (TLBEntry41_ref.(regval_of) (TLBEntry41_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry40" then Some (TLBEntry40_ref.(regval_of) (TLBEntry40_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry39" then Some (TLBEntry39_ref.(regval_of) (TLBEntry39_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry38" then Some (TLBEntry38_ref.(regval_of) (TLBEntry38_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry37" then Some (TLBEntry37_ref.(regval_of) (TLBEntry37_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry36" then Some (TLBEntry36_ref.(regval_of) (TLBEntry36_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry35" then Some (TLBEntry35_ref.(regval_of) (TLBEntry35_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry34" then Some (TLBEntry34_ref.(regval_of) (TLBEntry34_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry33" then Some (TLBEntry33_ref.(regval_of) (TLBEntry33_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry32" then Some (TLBEntry32_ref.(regval_of) (TLBEntry32_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry31" then Some (TLBEntry31_ref.(regval_of) (TLBEntry31_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry30" then Some (TLBEntry30_ref.(regval_of) (TLBEntry30_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry29" then Some (TLBEntry29_ref.(regval_of) (TLBEntry29_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry28" then Some (TLBEntry28_ref.(regval_of) (TLBEntry28_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry27" then Some (TLBEntry27_ref.(regval_of) (TLBEntry27_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry26" then Some (TLBEntry26_ref.(regval_of) (TLBEntry26_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry25" then Some (TLBEntry25_ref.(regval_of) (TLBEntry25_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry24" then Some (TLBEntry24_ref.(regval_of) (TLBEntry24_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry23" then Some (TLBEntry23_ref.(regval_of) (TLBEntry23_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry22" then Some (TLBEntry22_ref.(regval_of) (TLBEntry22_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry21" then Some (TLBEntry21_ref.(regval_of) (TLBEntry21_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry20" then Some (TLBEntry20_ref.(regval_of) (TLBEntry20_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry19" then Some (TLBEntry19_ref.(regval_of) (TLBEntry19_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry18" then Some (TLBEntry18_ref.(regval_of) (TLBEntry18_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry17" then Some (TLBEntry17_ref.(regval_of) (TLBEntry17_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry16" then Some (TLBEntry16_ref.(regval_of) (TLBEntry16_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry15" then Some (TLBEntry15_ref.(regval_of) (TLBEntry15_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry14" then Some (TLBEntry14_ref.(regval_of) (TLBEntry14_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry13" then Some (TLBEntry13_ref.(regval_of) (TLBEntry13_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry12" then Some (TLBEntry12_ref.(regval_of) (TLBEntry12_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry11" then Some (TLBEntry11_ref.(regval_of) (TLBEntry11_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry10" then Some (TLBEntry10_ref.(regval_of) (TLBEntry10_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry09" then Some (TLBEntry09_ref.(regval_of) (TLBEntry09_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry08" then Some (TLBEntry08_ref.(regval_of) (TLBEntry08_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry07" then Some (TLBEntry07_ref.(regval_of) (TLBEntry07_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry06" then Some (TLBEntry06_ref.(regval_of) (TLBEntry06_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry05" then Some (TLBEntry05_ref.(regval_of) (TLBEntry05_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry04" then Some (TLBEntry04_ref.(regval_of) (TLBEntry04_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry03" then Some (TLBEntry03_ref.(regval_of) (TLBEntry03_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry02" then Some (TLBEntry02_ref.(regval_of) (TLBEntry02_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry01" then Some (TLBEntry01_ref.(regval_of) (TLBEntry01_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry00" then Some (TLBEntry00_ref.(regval_of) (TLBEntry00_ref.(read_from) s)) else + if string_dec reg_name "TLBXContext" then Some (TLBXContext_ref.(regval_of) (TLBXContext_ref.(read_from) s)) else + if string_dec reg_name "TLBEntryHi" then Some (TLBEntryHi_ref.(regval_of) (TLBEntryHi_ref.(read_from) s)) else + if string_dec reg_name "TLBWired" then Some (TLBWired_ref.(regval_of) (TLBWired_ref.(read_from) s)) else + if string_dec reg_name "TLBPageMask" then Some (TLBPageMask_ref.(regval_of) (TLBPageMask_ref.(read_from) s)) else + if string_dec reg_name "TLBContext" then Some (TLBContext_ref.(regval_of) (TLBContext_ref.(read_from) s)) else + if string_dec reg_name "TLBEntryLo1" then Some (TLBEntryLo1_ref.(regval_of) (TLBEntryLo1_ref.(read_from) s)) else + if string_dec reg_name "TLBEntryLo0" then Some (TLBEntryLo0_ref.(regval_of) (TLBEntryLo0_ref.(read_from) s)) else + if string_dec reg_name "TLBRandom" then Some (TLBRandom_ref.(regval_of) (TLBRandom_ref.(read_from) s)) else + if string_dec reg_name "TLBIndex" then Some (TLBIndex_ref.(regval_of) (TLBIndex_ref.(read_from) s)) else + if string_dec reg_name "TLBProbe" then Some (TLBProbe_ref.(regval_of) (TLBProbe_ref.(read_from) s)) else + if string_dec reg_name "NextPC" then Some (NextPC_ref.(regval_of) (NextPC_ref.(read_from) s)) else + if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else + None. + +Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate := + if string_dec reg_name "CID" then option_map (fun v => CID_ref.(write_to) v s) (CID_ref.(of_regval) v) else + if string_dec reg_name "CapCause" then option_map (fun v => CapCause_ref.(write_to) v s) (CapCause_ref.(of_regval) v) else + if string_dec reg_name "KDC" then option_map (fun v => KDC_ref.(write_to) v s) (KDC_ref.(of_regval) v) else + if string_dec reg_name "KR2C" then option_map (fun v => KR2C_ref.(write_to) v s) (KR2C_ref.(of_regval) v) else + if string_dec reg_name "KR1C" then option_map (fun v => KR1C_ref.(write_to) v s) (KR1C_ref.(of_regval) v) else + if string_dec reg_name "CTLSP" then option_map (fun v => CTLSP_ref.(write_to) v s) (CTLSP_ref.(of_regval) v) else + if string_dec reg_name "CTLSU" then option_map (fun v => CTLSU_ref.(write_to) v s) (CTLSU_ref.(of_regval) v) else + if string_dec reg_name "C31" then option_map (fun v => C31_ref.(write_to) v s) (C31_ref.(of_regval) v) else + if string_dec reg_name "C30" then option_map (fun v => C30_ref.(write_to) v s) (C30_ref.(of_regval) v) else + if string_dec reg_name "C29" then option_map (fun v => C29_ref.(write_to) v s) (C29_ref.(of_regval) v) else + if string_dec reg_name "C28" then option_map (fun v => C28_ref.(write_to) v s) (C28_ref.(of_regval) v) else + if string_dec reg_name "C27" then option_map (fun v => C27_ref.(write_to) v s) (C27_ref.(of_regval) v) else + if string_dec reg_name "C26" then option_map (fun v => C26_ref.(write_to) v s) (C26_ref.(of_regval) v) else + if string_dec reg_name "C25" then option_map (fun v => C25_ref.(write_to) v s) (C25_ref.(of_regval) v) else + if string_dec reg_name "C24" then option_map (fun v => C24_ref.(write_to) v s) (C24_ref.(of_regval) v) else + if string_dec reg_name "C23" then option_map (fun v => C23_ref.(write_to) v s) (C23_ref.(of_regval) v) else + if string_dec reg_name "C22" then option_map (fun v => C22_ref.(write_to) v s) (C22_ref.(of_regval) v) else + if string_dec reg_name "C21" then option_map (fun v => C21_ref.(write_to) v s) (C21_ref.(of_regval) v) else + if string_dec reg_name "C20" then option_map (fun v => C20_ref.(write_to) v s) (C20_ref.(of_regval) v) else + if string_dec reg_name "C19" then option_map (fun v => C19_ref.(write_to) v s) (C19_ref.(of_regval) v) else + if string_dec reg_name "C18" then option_map (fun v => C18_ref.(write_to) v s) (C18_ref.(of_regval) v) else + if string_dec reg_name "C17" then option_map (fun v => C17_ref.(write_to) v s) (C17_ref.(of_regval) v) else + if string_dec reg_name "C16" then option_map (fun v => C16_ref.(write_to) v s) (C16_ref.(of_regval) v) else + if string_dec reg_name "C15" then option_map (fun v => C15_ref.(write_to) v s) (C15_ref.(of_regval) v) else + if string_dec reg_name "C14" then option_map (fun v => C14_ref.(write_to) v s) (C14_ref.(of_regval) v) else + if string_dec reg_name "C13" then option_map (fun v => C13_ref.(write_to) v s) (C13_ref.(of_regval) v) else + if string_dec reg_name "C12" then option_map (fun v => C12_ref.(write_to) v s) (C12_ref.(of_regval) v) else + if string_dec reg_name "C11" then option_map (fun v => C11_ref.(write_to) v s) (C11_ref.(of_regval) v) else + if string_dec reg_name "C10" then option_map (fun v => C10_ref.(write_to) v s) (C10_ref.(of_regval) v) else + if string_dec reg_name "C09" then option_map (fun v => C09_ref.(write_to) v s) (C09_ref.(of_regval) v) else + if string_dec reg_name "C08" then option_map (fun v => C08_ref.(write_to) v s) (C08_ref.(of_regval) v) else + if string_dec reg_name "C07" then option_map (fun v => C07_ref.(write_to) v s) (C07_ref.(of_regval) v) else + if string_dec reg_name "C06" then option_map (fun v => C06_ref.(write_to) v s) (C06_ref.(of_regval) v) else + if string_dec reg_name "C05" then option_map (fun v => C05_ref.(write_to) v s) (C05_ref.(of_regval) v) else + if string_dec reg_name "C04" then option_map (fun v => C04_ref.(write_to) v s) (C04_ref.(of_regval) v) else + if string_dec reg_name "C03" then option_map (fun v => C03_ref.(write_to) v s) (C03_ref.(of_regval) v) else + if string_dec reg_name "C02" then option_map (fun v => C02_ref.(write_to) v s) (C02_ref.(of_regval) v) else + if string_dec reg_name "C01" then option_map (fun v => C01_ref.(write_to) v s) (C01_ref.(of_regval) v) else + if string_dec reg_name "DDC" then option_map (fun v => DDC_ref.(write_to) v s) (DDC_ref.(of_regval) v) else + if string_dec reg_name "NextPCC" then option_map (fun v => NextPCC_ref.(write_to) v s) (NextPCC_ref.(of_regval) v) else + if string_dec reg_name "DelayedPCC" then option_map (fun v => DelayedPCC_ref.(write_to) v s) (DelayedPCC_ref.(of_regval) v) else + if string_dec reg_name "PCC" then option_map (fun v => PCC_ref.(write_to) v s) (PCC_ref.(of_regval) v) else + if string_dec reg_name "KCC" then option_map (fun v => KCC_ref.(write_to) v s) (KCC_ref.(of_regval) v) else + if string_dec reg_name "EPCC" then option_map (fun v => EPCC_ref.(write_to) v s) (EPCC_ref.(of_regval) v) else + if string_dec reg_name "UART_RVALID" then option_map (fun v => UART_RVALID_ref.(write_to) v s) (UART_RVALID_ref.(of_regval) v) else + if string_dec reg_name "UART_RDATA" then option_map (fun v => UART_RDATA_ref.(write_to) v s) (UART_RDATA_ref.(of_regval) v) else + if string_dec reg_name "UART_WRITTEN" then option_map (fun v => UART_WRITTEN_ref.(write_to) v s) (UART_WRITTEN_ref.(of_regval) v) else + if string_dec reg_name "UART_WDATA" then option_map (fun v => UART_WDATA_ref.(write_to) v s) (UART_WDATA_ref.(of_regval) v) else + if string_dec reg_name "GPR" then option_map (fun v => GPR_ref.(write_to) v s) (GPR_ref.(of_regval) v) else + if string_dec reg_name "LO" then option_map (fun v => LO_ref.(write_to) v s) (LO_ref.(of_regval) v) else + if string_dec reg_name "HI" then option_map (fun v => HI_ref.(write_to) v s) (HI_ref.(of_regval) v) else + if string_dec reg_name "DelayedPC" then option_map (fun v => DelayedPC_ref.(write_to) v s) (DelayedPC_ref.(of_regval) v) else + if string_dec reg_name "BranchPending" then option_map (fun v => BranchPending_ref.(write_to) v s) (BranchPending_ref.(of_regval) v) else + if string_dec reg_name "InBranchDelay" then option_map (fun v => InBranchDelay_ref.(write_to) v s) (InBranchDelay_ref.(of_regval) v) else + if string_dec reg_name "NextInBranchDelay" then option_map (fun v => NextInBranchDelay_ref.(write_to) v s) (NextInBranchDelay_ref.(of_regval) v) else + if string_dec reg_name "CP0Status" then option_map (fun v => CP0Status_ref.(write_to) v s) (CP0Status_ref.(of_regval) v) else + if string_dec reg_name "CP0ConfigK0" then option_map (fun v => CP0ConfigK0_ref.(write_to) v s) (CP0ConfigK0_ref.(of_regval) v) else + if string_dec reg_name "CP0UserLocal" then option_map (fun v => CP0UserLocal_ref.(write_to) v s) (CP0UserLocal_ref.(of_regval) v) else + if string_dec reg_name "CP0HWREna" then option_map (fun v => CP0HWREna_ref.(write_to) v s) (CP0HWREna_ref.(of_regval) v) else + if string_dec reg_name "CP0Count" then option_map (fun v => CP0Count_ref.(write_to) v s) (CP0Count_ref.(of_regval) v) else + if string_dec reg_name "CP0BadInstrP" then option_map (fun v => CP0BadInstrP_ref.(write_to) v s) (CP0BadInstrP_ref.(of_regval) v) else + if string_dec reg_name "CP0BadInstr" then option_map (fun v => CP0BadInstr_ref.(write_to) v s) (CP0BadInstr_ref.(of_regval) v) else + if string_dec reg_name "LastInstrBits" then option_map (fun v => LastInstrBits_ref.(write_to) v s) (LastInstrBits_ref.(of_regval) v) else + if string_dec reg_name "CurrentInstrBits" then option_map (fun v => CurrentInstrBits_ref.(write_to) v s) (CurrentInstrBits_ref.(of_regval) v) else + if string_dec reg_name "CP0BadVAddr" then option_map (fun v => CP0BadVAddr_ref.(write_to) v s) (CP0BadVAddr_ref.(of_regval) v) else + if string_dec reg_name "CP0LLAddr" then option_map (fun v => CP0LLAddr_ref.(write_to) v s) (CP0LLAddr_ref.(of_regval) v) else + if string_dec reg_name "CP0LLBit" then option_map (fun v => CP0LLBit_ref.(write_to) v s) (CP0LLBit_ref.(of_regval) v) else + if string_dec reg_name "CP0ErrorEPC" then option_map (fun v => CP0ErrorEPC_ref.(write_to) v s) (CP0ErrorEPC_ref.(of_regval) v) else + if string_dec reg_name "CP0EPC" then option_map (fun v => CP0EPC_ref.(write_to) v s) (CP0EPC_ref.(of_regval) v) else + if string_dec reg_name "CP0Cause" then option_map (fun v => CP0Cause_ref.(write_to) v s) (CP0Cause_ref.(of_regval) v) else + if string_dec reg_name "CP0Compare" then option_map (fun v => CP0Compare_ref.(write_to) v s) (CP0Compare_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry63" then option_map (fun v => TLBEntry63_ref.(write_to) v s) (TLBEntry63_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry62" then option_map (fun v => TLBEntry62_ref.(write_to) v s) (TLBEntry62_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry61" then option_map (fun v => TLBEntry61_ref.(write_to) v s) (TLBEntry61_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry60" then option_map (fun v => TLBEntry60_ref.(write_to) v s) (TLBEntry60_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry59" then option_map (fun v => TLBEntry59_ref.(write_to) v s) (TLBEntry59_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry58" then option_map (fun v => TLBEntry58_ref.(write_to) v s) (TLBEntry58_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry57" then option_map (fun v => TLBEntry57_ref.(write_to) v s) (TLBEntry57_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry56" then option_map (fun v => TLBEntry56_ref.(write_to) v s) (TLBEntry56_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry55" then option_map (fun v => TLBEntry55_ref.(write_to) v s) (TLBEntry55_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry54" then option_map (fun v => TLBEntry54_ref.(write_to) v s) (TLBEntry54_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry53" then option_map (fun v => TLBEntry53_ref.(write_to) v s) (TLBEntry53_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry52" then option_map (fun v => TLBEntry52_ref.(write_to) v s) (TLBEntry52_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry51" then option_map (fun v => TLBEntry51_ref.(write_to) v s) (TLBEntry51_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry50" then option_map (fun v => TLBEntry50_ref.(write_to) v s) (TLBEntry50_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry49" then option_map (fun v => TLBEntry49_ref.(write_to) v s) (TLBEntry49_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry48" then option_map (fun v => TLBEntry48_ref.(write_to) v s) (TLBEntry48_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry47" then option_map (fun v => TLBEntry47_ref.(write_to) v s) (TLBEntry47_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry46" then option_map (fun v => TLBEntry46_ref.(write_to) v s) (TLBEntry46_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry45" then option_map (fun v => TLBEntry45_ref.(write_to) v s) (TLBEntry45_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry44" then option_map (fun v => TLBEntry44_ref.(write_to) v s) (TLBEntry44_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry43" then option_map (fun v => TLBEntry43_ref.(write_to) v s) (TLBEntry43_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry42" then option_map (fun v => TLBEntry42_ref.(write_to) v s) (TLBEntry42_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry41" then option_map (fun v => TLBEntry41_ref.(write_to) v s) (TLBEntry41_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry40" then option_map (fun v => TLBEntry40_ref.(write_to) v s) (TLBEntry40_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry39" then option_map (fun v => TLBEntry39_ref.(write_to) v s) (TLBEntry39_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry38" then option_map (fun v => TLBEntry38_ref.(write_to) v s) (TLBEntry38_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry37" then option_map (fun v => TLBEntry37_ref.(write_to) v s) (TLBEntry37_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry36" then option_map (fun v => TLBEntry36_ref.(write_to) v s) (TLBEntry36_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry35" then option_map (fun v => TLBEntry35_ref.(write_to) v s) (TLBEntry35_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry34" then option_map (fun v => TLBEntry34_ref.(write_to) v s) (TLBEntry34_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry33" then option_map (fun v => TLBEntry33_ref.(write_to) v s) (TLBEntry33_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry32" then option_map (fun v => TLBEntry32_ref.(write_to) v s) (TLBEntry32_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry31" then option_map (fun v => TLBEntry31_ref.(write_to) v s) (TLBEntry31_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry30" then option_map (fun v => TLBEntry30_ref.(write_to) v s) (TLBEntry30_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry29" then option_map (fun v => TLBEntry29_ref.(write_to) v s) (TLBEntry29_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry28" then option_map (fun v => TLBEntry28_ref.(write_to) v s) (TLBEntry28_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry27" then option_map (fun v => TLBEntry27_ref.(write_to) v s) (TLBEntry27_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry26" then option_map (fun v => TLBEntry26_ref.(write_to) v s) (TLBEntry26_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry25" then option_map (fun v => TLBEntry25_ref.(write_to) v s) (TLBEntry25_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry24" then option_map (fun v => TLBEntry24_ref.(write_to) v s) (TLBEntry24_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry23" then option_map (fun v => TLBEntry23_ref.(write_to) v s) (TLBEntry23_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry22" then option_map (fun v => TLBEntry22_ref.(write_to) v s) (TLBEntry22_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry21" then option_map (fun v => TLBEntry21_ref.(write_to) v s) (TLBEntry21_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry20" then option_map (fun v => TLBEntry20_ref.(write_to) v s) (TLBEntry20_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry19" then option_map (fun v => TLBEntry19_ref.(write_to) v s) (TLBEntry19_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry18" then option_map (fun v => TLBEntry18_ref.(write_to) v s) (TLBEntry18_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry17" then option_map (fun v => TLBEntry17_ref.(write_to) v s) (TLBEntry17_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry16" then option_map (fun v => TLBEntry16_ref.(write_to) v s) (TLBEntry16_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry15" then option_map (fun v => TLBEntry15_ref.(write_to) v s) (TLBEntry15_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry14" then option_map (fun v => TLBEntry14_ref.(write_to) v s) (TLBEntry14_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry13" then option_map (fun v => TLBEntry13_ref.(write_to) v s) (TLBEntry13_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry12" then option_map (fun v => TLBEntry12_ref.(write_to) v s) (TLBEntry12_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry11" then option_map (fun v => TLBEntry11_ref.(write_to) v s) (TLBEntry11_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry10" then option_map (fun v => TLBEntry10_ref.(write_to) v s) (TLBEntry10_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry09" then option_map (fun v => TLBEntry09_ref.(write_to) v s) (TLBEntry09_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry08" then option_map (fun v => TLBEntry08_ref.(write_to) v s) (TLBEntry08_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry07" then option_map (fun v => TLBEntry07_ref.(write_to) v s) (TLBEntry07_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry06" then option_map (fun v => TLBEntry06_ref.(write_to) v s) (TLBEntry06_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry05" then option_map (fun v => TLBEntry05_ref.(write_to) v s) (TLBEntry05_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry04" then option_map (fun v => TLBEntry04_ref.(write_to) v s) (TLBEntry04_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry03" then option_map (fun v => TLBEntry03_ref.(write_to) v s) (TLBEntry03_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry02" then option_map (fun v => TLBEntry02_ref.(write_to) v s) (TLBEntry02_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry01" then option_map (fun v => TLBEntry01_ref.(write_to) v s) (TLBEntry01_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry00" then option_map (fun v => TLBEntry00_ref.(write_to) v s) (TLBEntry00_ref.(of_regval) v) else + if string_dec reg_name "TLBXContext" then option_map (fun v => TLBXContext_ref.(write_to) v s) (TLBXContext_ref.(of_regval) v) else + if string_dec reg_name "TLBEntryHi" then option_map (fun v => TLBEntryHi_ref.(write_to) v s) (TLBEntryHi_ref.(of_regval) v) else + if string_dec reg_name "TLBWired" then option_map (fun v => TLBWired_ref.(write_to) v s) (TLBWired_ref.(of_regval) v) else + if string_dec reg_name "TLBPageMask" then option_map (fun v => TLBPageMask_ref.(write_to) v s) (TLBPageMask_ref.(of_regval) v) else + if string_dec reg_name "TLBContext" then option_map (fun v => TLBContext_ref.(write_to) v s) (TLBContext_ref.(of_regval) v) else + if string_dec reg_name "TLBEntryLo1" then option_map (fun v => TLBEntryLo1_ref.(write_to) v s) (TLBEntryLo1_ref.(of_regval) v) else + if string_dec reg_name "TLBEntryLo0" then option_map (fun v => TLBEntryLo0_ref.(write_to) v s) (TLBEntryLo0_ref.(of_regval) v) else + if string_dec reg_name "TLBRandom" then option_map (fun v => TLBRandom_ref.(write_to) v s) (TLBRandom_ref.(of_regval) v) else + if string_dec reg_name "TLBIndex" then option_map (fun v => TLBIndex_ref.(write_to) v s) (TLBIndex_ref.(of_regval) v) else + if string_dec reg_name "TLBProbe" then option_map (fun v => TLBProbe_ref.(write_to) v s) (TLBProbe_ref.(of_regval) v) else + if string_dec reg_name "NextPC" then option_map (fun v => NextPC_ref.(write_to) v s) (NextPC_ref.(of_regval) v) else + if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else + None. + +Definition register_accessors := (get_regval, set_regval). + + +Definition MR a r := monadR register_value a r exception. +Definition M a := monad register_value a exception. diff --git a/snapshots/coq/mips/mips.v b/snapshots/coq/cheri-mips/mips.v index 8d43a6e2..dd3c206d 100644 --- a/snapshots/coq/mips/mips.v +++ b/snapshots/coq/cheri-mips/mips.v @@ -1,6 +1,8 @@ (*Generated by Sail from mips.*) Require Import Sail2_instr_kinds. Require Import Sail2_values. +Require Import Sail2_string. +Require Import Sail2_real. Require Import Sail2_operators_mwords. Require Import Sail2_prompt_monad. Require Import Sail2_prompt. @@ -9,153 +11,184 @@ Require Import mips_types. Require Import mips_extras. Import ListNotations. Open Scope string. +Open Scope bool. Section Content. -Definition neq_atom (x : Z) (y : Z) `{ArithFact (x = x)} `{ArithFact (y = y)} -: bool := - negb (Z.eqb x y). - -Definition neq_range {n : Z} {m : Z} {o : Z} {p : Z} '((existT _ x _) : {rangevar : Z & ArithFact (n <= - rangevar /\ - rangevar <= m)}) '((existT _ y _) : {rangevar : Z & ArithFact (o <= rangevar /\ rangevar <= p)}) -: bool := - negb (eq_range (build_ex x) (build_ex y)). +Definition trace : bool := false. +Hint Unfold trace : sail. +Definition eq_unit (g__17 : unit) (g__18 : unit) : bool := true. -Definition neq_int (x : Z) (y : Z) : bool := negb (Z.eqb x y). +Definition neq_int (x : Z) (y : Z) : bool := negb (Z.eqb x y). -Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y). +Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y). Definition undefined_option {a : Type} (typ_a : a) : M (option a) := - undefined_unit tt >>= fun u_0 => + + (undefined_unit tt) >>= fun u_0 : unit => let u_1 : a := typ_a in - (internal_pick [Some u_1;None]) + (internal_pick [Some (u_1);None]) : M (option a). Definition is_none {a : Type} (opt : option a) : bool := + match opt with | Some (_) => false | None => true end. Definition is_some {a : Type} (opt : option a) : bool := + match opt with | Some (_) => true | None => false end. -Definition sail_mask {v0 : Z} (len : Z) (v : mword v0) `{ArithFact (len >= 0 /\ v0 >= 0)} `{ArithFact (len = - len)} +Definition sail_mask {v0 : Z} (len : Z) (v : mword v0) `{ArithFact (len >= 0 /\ v0 >= 0)} : mword len := + if sumbool_of_bool ((Z.leb len (length_mword v))) then vector_truncate v len else zero_extend v len. -Definition neq_vec {n : Z} (x : mword n) (y : mword n) : bool := negb (eq_vec x y). +Definition neq_vec {n : Z} (x : mword n) (y : mword n) : bool := negb (eq_vec x y). Definition cast_unit_vec (b : bitU) : mword 1 := + match b with | B0 => (vec_of_bits [B0] : mword 1) | _ => (vec_of_bits [B1] : mword 1) end. -Definition __MIPS_write (addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width = - width)} +Definition __MIPS_write (addr : mword 64) (width : Z) (data : mword (8 * width)) : M (unit) := + (write_ram 64 width (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0] - : mword 64) addr data) - : M (unit). + : mword 64) addr data) >> + returnm (tt + : unit). -Definition __MIPS_read (addr : mword 64) (width : Z) `{ArithFact (width >= 0)} `{ArithFact (width = - width)} +Definition __MIPS_read (addr : mword 64) (width : Z) `{ArithFact (width >= 0)} : M (mword (8 * width)) := - (autocast_m (read_ram 64 width - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) addr)) + + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) : M (mword (8 * width)). -Definition zopz0zQzQ {n0 : Z} (bs : mword n0) (n : Z) `{ArithFact (n >= 0)} `{ArithFact (n = n)} +Definition zopz0zQzQ {n0 : Z} (bs : mword n0) (n : Z) `{ArithFact (n >= 0)} : mword (n0 * n) := + replicate_bits bs n. Definition undefined_exception '(tt : unit) : M (exception) := - undefined_string tt >>= fun u_0 => - undefined_unit tt >>= fun u_1 => + + (undefined_string tt) >>= fun u_0 : string => + (undefined_unit tt) >>= fun u_1 : unit => (internal_pick - [ISAException u_1;Error_not_implemented u_0;Error_misaligned_access u_1;Error_EBREAK u_1;Error_internal_error u_1]) + [ISAException + (u_1);Error_not_implemented + (u_0);Error_misaligned_access + (u_1);Error_EBREAK + (u_1);Error_internal_error + (u_1)]) : M (exception). Definition mips_sign_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} : mword m__tv := + sign_extend v m__tv. Definition mips_zero_extend {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} : mword m__tv := + zero_extend v m__tv. -Definition zeros (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} +Axiom sign_extend : forall {n : Z} {m : Z} (_ : mword n) `{ArithFact (m >= n)}, mword m. + +Axiom zero_extend : forall {n : Z} {m : Z} (_ : mword n) `{ArithFact (m >= n)}, mword m. + +Definition zeros_implicit (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} : mword n__tv := - autocast (replicate_bits (vec_of_bits [B0] : mword 1) n__tv). -Arguments zeros _ _ {_}. + + zeros n__tv. +Arguments zeros_implicit _ _ {_}. + +Definition ones_n (n : Z) `{ArithFact (n >= 0)} +: mword n := + + autocast (replicate_bits (vec_of_bits [B1] : mword 1) n). -Definition ones (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} +Definition ones_implicit (n__tv : Z) '(tt : unit) `{ArithFact (n__tv >= 0)} : mword n__tv := - autocast (replicate_bits (vec_of_bits [B1] : mword 1) n__tv). -Arguments ones _ _ {_}. + + ones_n n__tv. +Arguments ones_implicit _ _ {_}. -Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 1)} +Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} : bool := + Z.ltb (projT1 (sint x)) (projT1 (sint y)). -Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 1)} +Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} : bool := + Z.geb (projT1 (sint x)) (projT1 (sint y)). Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} : bool := + Z.ltb (projT1 (uint x)) (projT1 (uint y)). Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= 0)} : bool := + Z.geb (projT1 (uint x)) (projT1 (uint y)). Definition bool_to_bits (x : bool) : mword 1 := + if (x) then (vec_of_bits [B1] : mword 1) else (vec_of_bits [B0] : mword 1). -Definition bit_to_bool (b : bitU) : bool := match b with | B1 => true | _ => false end. +Definition bool_to_bit (x : bool) : bitU := if (x) then B1 else B0. -Definition bits_to_bool (x : mword 1) : bool := bit_to_bool (access_vec_dec x 0). +Definition bit_to_bool (b : bitU) : bool := match b with | B1 => true | _ => false end. -Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} `{ArithFact (l = l)} -: mword l := - get_slice_int l n 0. +Definition bits_to_bool (x : mword 1) : bool := bit_to_bool (access_vec_dec x 0). -Definition mask {m : Z} (n__tv : Z) (bs : mword m) `{ArithFact (m >= n__tv /\ n__tv >= 1)} +Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} : mword l := get_slice_int l n 0. + +Definition mask {m : Z} (n__tv : Z) (bs : mword m) `{ArithFact (m >= n__tv /\ n__tv >= (0 + 1))} : mword n__tv := + autocast (subrange_vec_dec bs (Z.sub n__tv 1) 0). Definition undefined_CauseReg '(tt : unit) : M (CauseReg) := - undefined_bitvector 32 >>= fun w__0 => + + (undefined_bitvector 32) >>= fun w__0 : mword 32 => returnm (({| CauseReg_CauseReg_chunk_0 := w__0 |}) : CauseReg). Definition Mk_CauseReg (v : mword 32) : CauseReg := + {| CauseReg_CauseReg_chunk_0 := (subrange_vec_dec v 31 0) |}. Definition _get_CauseReg_bits (v : CauseReg) : mword 32 := + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0. -Definition _set_CauseReg_bits (r_ref : register_ref regstate register_value CauseReg) (v : mword 32) +Definition _set_CauseReg_bits (r_ref : register_ref regstate register_value CauseReg) (v : mword 32) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with CauseReg_CauseReg_chunk_0 := @@ -166,17 +199,20 @@ Definition _set_CauseReg_bits (r_ref : register_ref regstate register_value Caus Definition _update_CauseReg_bits (v : CauseReg) (x : mword 32) : CauseReg := + {[ v with CauseReg_CauseReg_chunk_0 := (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. Definition _get_CauseReg_BD (v : CauseReg) : mword 1 := + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31. Definition _set_CauseReg_BD (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with CauseReg_CauseReg_chunk_0 := @@ -187,17 +223,20 @@ Definition _set_CauseReg_BD (r_ref : register_ref regstate register_value CauseR Definition _update_CauseReg_BD (v : CauseReg) (x : mword 1) : CauseReg := + {[ v with CauseReg_CauseReg_chunk_0 := (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}. Definition _get_CauseReg_CE (v : CauseReg) : mword 2 := + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28. Definition _set_CauseReg_CE (r_ref : register_ref regstate register_value CauseReg) (v : mword 2) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with CauseReg_CauseReg_chunk_0 := @@ -208,17 +247,20 @@ Definition _set_CauseReg_CE (r_ref : register_ref regstate register_value CauseR Definition _update_CauseReg_CE (v : CauseReg) (x : mword 2) : CauseReg := + {[ v with CauseReg_CauseReg_chunk_0 := (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 29 28 (subrange_vec_dec x 1 0)) ]}. Definition _get_CauseReg_IV (v : CauseReg) : mword 1 := + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23. Definition _set_CauseReg_IV (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with CauseReg_CauseReg_chunk_0 := @@ -229,17 +271,20 @@ Definition _set_CauseReg_IV (r_ref : register_ref regstate register_value CauseR Definition _update_CauseReg_IV (v : CauseReg) (x : mword 1) : CauseReg := + {[ v with CauseReg_CauseReg_chunk_0 := (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 23 23 (subrange_vec_dec x 0 0)) ]}. Definition _get_CauseReg_WP (v : CauseReg) : mword 1 := + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22. Definition _set_CauseReg_WP (r_ref : register_ref regstate register_value CauseReg) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with CauseReg_CauseReg_chunk_0 := @@ -250,17 +295,20 @@ Definition _set_CauseReg_WP (r_ref : register_ref regstate register_value CauseR Definition _update_CauseReg_WP (v : CauseReg) (x : mword 1) : CauseReg := + {[ v with CauseReg_CauseReg_chunk_0 := (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. Definition _get_CauseReg_IP (v : CauseReg) : mword 8 := + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8. Definition _set_CauseReg_IP (r_ref : register_ref regstate register_value CauseReg) (v : mword 8) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with CauseReg_CauseReg_chunk_0 := @@ -271,17 +319,21 @@ Definition _set_CauseReg_IP (r_ref : register_ref regstate register_value CauseR Definition _update_CauseReg_IP (v : CauseReg) (x : mword 8) : CauseReg := + {[ v with CauseReg_CauseReg_chunk_0 := (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}. Definition _get_CauseReg_ExcCode (v : CauseReg) : mword 5 := + subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2. -Definition _set_CauseReg_ExcCode (r_ref : register_ref regstate register_value CauseReg) (v : mword 5) +Definition _set_CauseReg_ExcCode +(r_ref : register_ref regstate register_value CauseReg) (v : mword 5) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with CauseReg_CauseReg_chunk_0 := @@ -292,27 +344,33 @@ Definition _set_CauseReg_ExcCode (r_ref : register_ref regstate register_value C Definition _update_CauseReg_ExcCode (v : CauseReg) (x : mword 5) : CauseReg := + {[ v with CauseReg_CauseReg_chunk_0 := (update_subrange_vec_dec v.(CauseReg_CauseReg_chunk_0) 6 2 (subrange_vec_dec x 4 0)) ]}. Definition undefined_TLBEntryLoReg '(tt : unit) : M (TLBEntryLoReg) := - undefined_bitvector 64 >>= fun w__0 => + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => returnm (({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := w__0 |}) : TLBEntryLoReg). Definition Mk_TLBEntryLoReg (v : mword 64) : TLBEntryLoReg := + {| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (subrange_vec_dec v 63 0) |}. Definition _get_TLBEntryLoReg_bits (v : TLBEntryLoReg) : mword 64 := + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0. -Definition _set_TLBEntryLoReg_bits (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 64) +Definition _set_TLBEntryLoReg_bits +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 64) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := @@ -324,6 +382,7 @@ Definition _set_TLBEntryLoReg_bits (r_ref : register_ref regstate register_value Definition _update_TLBEntryLoReg_bits (v : TLBEntryLoReg) (x : mword 64) : TLBEntryLoReg := + {[ v with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 0 @@ -331,11 +390,14 @@ Definition _update_TLBEntryLoReg_bits (v : TLBEntryLoReg) (x : mword 64) Definition _get_TLBEntryLoReg_CapS (v : TLBEntryLoReg) : mword 1 := + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63. -Definition _set_TLBEntryLoReg_CapS (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +Definition _set_TLBEntryLoReg_CapS +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := @@ -347,6 +409,7 @@ Definition _set_TLBEntryLoReg_CapS (r_ref : register_ref regstate register_value Definition _update_TLBEntryLoReg_CapS (v : TLBEntryLoReg) (x : mword 1) : TLBEntryLoReg := + {[ v with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 63 63 @@ -354,11 +417,14 @@ Definition _update_TLBEntryLoReg_CapS (v : TLBEntryLoReg) (x : mword 1) Definition _get_TLBEntryLoReg_CapL (v : TLBEntryLoReg) : mword 1 := + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62. -Definition _set_TLBEntryLoReg_CapL (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +Definition _set_TLBEntryLoReg_CapL +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := @@ -370,6 +436,7 @@ Definition _set_TLBEntryLoReg_CapL (r_ref : register_ref regstate register_value Definition _update_TLBEntryLoReg_CapL (v : TLBEntryLoReg) (x : mword 1) : TLBEntryLoReg := + {[ v with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 62 62 @@ -377,11 +444,14 @@ Definition _update_TLBEntryLoReg_CapL (v : TLBEntryLoReg) (x : mword 1) Definition _get_TLBEntryLoReg_PFN (v : TLBEntryLoReg) : mword 24 := + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6. -Definition _set_TLBEntryLoReg_PFN (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 24) +Definition _set_TLBEntryLoReg_PFN +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 24) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := @@ -393,6 +463,7 @@ Definition _set_TLBEntryLoReg_PFN (r_ref : register_ref regstate register_value Definition _update_TLBEntryLoReg_PFN (v : TLBEntryLoReg) (x : mword 24) : TLBEntryLoReg := + {[ v with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 29 6 @@ -400,11 +471,14 @@ Definition _update_TLBEntryLoReg_PFN (v : TLBEntryLoReg) (x : mword 24) Definition _get_TLBEntryLoReg_C (v : TLBEntryLoReg) : mword 3 := + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3. -Definition _set_TLBEntryLoReg_C (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 3) +Definition _set_TLBEntryLoReg_C +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 3) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := @@ -416,17 +490,21 @@ Definition _set_TLBEntryLoReg_C (r_ref : register_ref regstate register_value TL Definition _update_TLBEntryLoReg_C (v : TLBEntryLoReg) (x : mword 3) : TLBEntryLoReg := + {[ v with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 5 3 (subrange_vec_dec x 2 0)) ]}. Definition _get_TLBEntryLoReg_D (v : TLBEntryLoReg) : mword 1 := + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2. -Definition _set_TLBEntryLoReg_D (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +Definition _set_TLBEntryLoReg_D +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := @@ -438,17 +516,21 @@ Definition _set_TLBEntryLoReg_D (r_ref : register_ref regstate register_value TL Definition _update_TLBEntryLoReg_D (v : TLBEntryLoReg) (x : mword 1) : TLBEntryLoReg := + {[ v with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. Definition _get_TLBEntryLoReg_V (v : TLBEntryLoReg) : mword 1 := + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1. -Definition _set_TLBEntryLoReg_V (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +Definition _set_TLBEntryLoReg_V +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := @@ -460,17 +542,21 @@ Definition _set_TLBEntryLoReg_V (r_ref : register_ref regstate register_value TL Definition _update_TLBEntryLoReg_V (v : TLBEntryLoReg) (x : mword 1) : TLBEntryLoReg := + {[ v with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. Definition _get_TLBEntryLoReg_G (v : TLBEntryLoReg) : mword 1 := + subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0. -Definition _set_TLBEntryLoReg_G (r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) +Definition _set_TLBEntryLoReg_G +(r_ref : register_ref regstate register_value TLBEntryLoReg) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := @@ -482,27 +568,33 @@ Definition _set_TLBEntryLoReg_G (r_ref : register_ref regstate register_value TL Definition _update_TLBEntryLoReg_G (v : TLBEntryLoReg) (x : mword 1) : TLBEntryLoReg := + {[ v with TLBEntryLoReg_TLBEntryLoReg_chunk_0 := (update_subrange_vec_dec v.(TLBEntryLoReg_TLBEntryLoReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. Definition undefined_TLBEntryHiReg '(tt : unit) : M (TLBEntryHiReg) := - undefined_bitvector 64 >>= fun w__0 => + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => returnm (({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := w__0 |}) : TLBEntryHiReg). Definition Mk_TLBEntryHiReg (v : mword 64) : TLBEntryHiReg := + {| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := (subrange_vec_dec v 63 0) |}. Definition _get_TLBEntryHiReg_bits (v : TLBEntryHiReg) : mword 64 := + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0. -Definition _set_TLBEntryHiReg_bits (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 64) +Definition _set_TLBEntryHiReg_bits +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 64) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntryHiReg_TLBEntryHiReg_chunk_0 := @@ -514,6 +606,7 @@ Definition _set_TLBEntryHiReg_bits (r_ref : register_ref regstate register_value Definition _update_TLBEntryHiReg_bits (v : TLBEntryHiReg) (x : mword 64) : TLBEntryHiReg := + {[ v with TLBEntryHiReg_TLBEntryHiReg_chunk_0 := (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 0 @@ -521,11 +614,14 @@ Definition _update_TLBEntryHiReg_bits (v : TLBEntryHiReg) (x : mword 64) Definition _get_TLBEntryHiReg_R (v : TLBEntryHiReg) : mword 2 := + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62. -Definition _set_TLBEntryHiReg_R (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 2) +Definition _set_TLBEntryHiReg_R +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 2) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntryHiReg_TLBEntryHiReg_chunk_0 := @@ -537,6 +633,7 @@ Definition _set_TLBEntryHiReg_R (r_ref : register_ref regstate register_value TL Definition _update_TLBEntryHiReg_R (v : TLBEntryHiReg) (x : mword 2) : TLBEntryHiReg := + {[ v with TLBEntryHiReg_TLBEntryHiReg_chunk_0 := (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 63 62 @@ -544,11 +641,14 @@ Definition _update_TLBEntryHiReg_R (v : TLBEntryHiReg) (x : mword 2) Definition _get_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) : mword 27 := + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13. -Definition _set_TLBEntryHiReg_VPN2 (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 27) +Definition _set_TLBEntryHiReg_VPN2 +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 27) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntryHiReg_TLBEntryHiReg_chunk_0 := @@ -560,6 +660,7 @@ Definition _set_TLBEntryHiReg_VPN2 (r_ref : register_ref regstate register_value Definition _update_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) (x : mword 27) : TLBEntryHiReg := + {[ v with TLBEntryHiReg_TLBEntryHiReg_chunk_0 := (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 39 13 @@ -567,11 +668,14 @@ Definition _update_TLBEntryHiReg_VPN2 (v : TLBEntryHiReg) (x : mword 27) Definition _get_TLBEntryHiReg_ASID (v : TLBEntryHiReg) : mword 8 := + subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0. -Definition _set_TLBEntryHiReg_ASID (r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 8) +Definition _set_TLBEntryHiReg_ASID +(r_ref : register_ref regstate register_value TLBEntryHiReg) (v : mword 8) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntryHiReg_TLBEntryHiReg_chunk_0 := @@ -583,27 +687,33 @@ Definition _set_TLBEntryHiReg_ASID (r_ref : register_ref regstate register_value Definition _update_TLBEntryHiReg_ASID (v : TLBEntryHiReg) (x : mword 8) : TLBEntryHiReg := + {[ v with TLBEntryHiReg_TLBEntryHiReg_chunk_0 := (update_subrange_vec_dec v.(TLBEntryHiReg_TLBEntryHiReg_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. Definition undefined_ContextReg '(tt : unit) : M (ContextReg) := - undefined_bitvector 64 >>= fun w__0 => + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => returnm (({| ContextReg_ContextReg_chunk_0 := w__0 |}) : ContextReg). Definition Mk_ContextReg (v : mword 64) : ContextReg := + {| ContextReg_ContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}. Definition _get_ContextReg_bits (v : ContextReg) : mword 64 := + subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0. -Definition _set_ContextReg_bits (r_ref : register_ref regstate register_value ContextReg) (v : mword 64) +Definition _set_ContextReg_bits +(r_ref : register_ref regstate register_value ContextReg) (v : mword 64) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with ContextReg_ContextReg_chunk_0 := @@ -614,17 +724,21 @@ Definition _set_ContextReg_bits (r_ref : register_ref regstate register_value Co Definition _update_ContextReg_bits (v : ContextReg) (x : mword 64) : ContextReg := + {[ v with ContextReg_ContextReg_chunk_0 := (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. Definition _get_ContextReg_PTEBase (v : ContextReg) : mword 41 := + subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23. -Definition _set_ContextReg_PTEBase (r_ref : register_ref regstate register_value ContextReg) (v : mword 41) +Definition _set_ContextReg_PTEBase +(r_ref : register_ref regstate register_value ContextReg) (v : mword 41) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with ContextReg_ContextReg_chunk_0 := @@ -635,17 +749,21 @@ Definition _set_ContextReg_PTEBase (r_ref : register_ref regstate register_value Definition _update_ContextReg_PTEBase (v : ContextReg) (x : mword 41) : ContextReg := + {[ v with ContextReg_ContextReg_chunk_0 := (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 63 23 (subrange_vec_dec x 40 0)) ]}. Definition _get_ContextReg_BadVPN2 (v : ContextReg) : mword 19 := + subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4. -Definition _set_ContextReg_BadVPN2 (r_ref : register_ref regstate register_value ContextReg) (v : mword 19) +Definition _set_ContextReg_BadVPN2 +(r_ref : register_ref regstate register_value ContextReg) (v : mword 19) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with ContextReg_ContextReg_chunk_0 := @@ -656,27 +774,33 @@ Definition _set_ContextReg_BadVPN2 (r_ref : register_ref regstate register_value Definition _update_ContextReg_BadVPN2 (v : ContextReg) (x : mword 19) : ContextReg := + {[ v with ContextReg_ContextReg_chunk_0 := (update_subrange_vec_dec v.(ContextReg_ContextReg_chunk_0) 22 4 (subrange_vec_dec x 18 0)) ]}. Definition undefined_XContextReg '(tt : unit) : M (XContextReg) := - undefined_bitvector 64 >>= fun w__0 => + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => returnm (({| XContextReg_XContextReg_chunk_0 := w__0 |}) : XContextReg). Definition Mk_XContextReg (v : mword 64) : XContextReg := + {| XContextReg_XContextReg_chunk_0 := (subrange_vec_dec v 63 0) |}. Definition _get_XContextReg_bits (v : XContextReg) : mword 64 := + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0. -Definition _set_XContextReg_bits (r_ref : register_ref regstate register_value XContextReg) (v : mword 64) +Definition _set_XContextReg_bits +(r_ref : register_ref regstate register_value XContextReg) (v : mword 64) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with XContextReg_XContextReg_chunk_0 := @@ -687,17 +811,21 @@ Definition _set_XContextReg_bits (r_ref : register_ref regstate register_value X Definition _update_XContextReg_bits (v : XContextReg) (x : mword 64) : XContextReg := + {[ v with XContextReg_XContextReg_chunk_0 := (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. Definition _get_XContextReg_XPTEBase (v : XContextReg) : mword 31 := + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33. -Definition _set_XContextReg_XPTEBase (r_ref : register_ref regstate register_value XContextReg) (v : mword 31) +Definition _set_XContextReg_XPTEBase +(r_ref : register_ref regstate register_value XContextReg) (v : mword 31) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with XContextReg_XContextReg_chunk_0 := @@ -709,17 +837,21 @@ Definition _set_XContextReg_XPTEBase (r_ref : register_ref regstate register_val Definition _update_XContextReg_XPTEBase (v : XContextReg) (x : mword 31) : XContextReg := + {[ v with XContextReg_XContextReg_chunk_0 := (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 63 33 (subrange_vec_dec x 30 0)) ]}. Definition _get_XContextReg_XR (v : XContextReg) : mword 2 := + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31. -Definition _set_XContextReg_XR (r_ref : register_ref regstate register_value XContextReg) (v : mword 2) +Definition _set_XContextReg_XR +(r_ref : register_ref regstate register_value XContextReg) (v : mword 2) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with XContextReg_XContextReg_chunk_0 := @@ -730,17 +862,21 @@ Definition _set_XContextReg_XR (r_ref : register_ref regstate register_value XCo Definition _update_XContextReg_XR (v : XContextReg) (x : mword 2) : XContextReg := + {[ v with XContextReg_XContextReg_chunk_0 := (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 32 31 (subrange_vec_dec x 1 0)) ]}. Definition _get_XContextReg_XBadVPN2 (v : XContextReg) : mword 27 := + subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4. -Definition _set_XContextReg_XBadVPN2 (r_ref : register_ref regstate register_value XContextReg) (v : mword 27) +Definition _set_XContextReg_XBadVPN2 +(r_ref : register_ref regstate register_value XContextReg) (v : mword 27) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with XContextReg_XContextReg_chunk_0 := @@ -751,43 +887,52 @@ Definition _set_XContextReg_XBadVPN2 (r_ref : register_ref regstate register_val Definition _update_XContextReg_XBadVPN2 (v : XContextReg) (x : mword 27) : XContextReg := + {[ v with XContextReg_XContextReg_chunk_0 := (update_subrange_vec_dec v.(XContextReg_XContextReg_chunk_0) 30 4 (subrange_vec_dec x 26 0)) ]}. Definition TLBNumEntries := 64. - +Hint Unfold TLBNumEntries : sail. Definition TLBIndexMax : TLBIndexT := (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword 6). - -Definition MAX (n : Z) `{ArithFact (n = n)} : Z := Z.sub (pow2 n) 1. - -Definition MAX_U64 := MAX 64. - -Definition MAX_VA := MAX 40. - -Definition MAX_PA := MAX 36. - +Hint Unfold TLBIndexMax : sail. +Definition MAX (n : Z) `{ArithFact (n >= 0)} +: {_retval : Z & ArithFact (_retval = (2 ^ n - 1))} := + + build_ex(Z.sub (projT1 (pow2 n)) 1). + +Definition MAX_U64 := projT1 (MAX 64). +Hint Unfold MAX_U64 : sail. +Definition MAX_VA := projT1 (MAX 40). +Hint Unfold MAX_VA : sail. +Definition MAX_PA := projT1 (MAX 36). +Hint Unfold MAX_PA : sail. Definition undefined_TLBEntry '(tt : unit) : M (TLBEntry) := - undefined_bitvector 53 >>= fun w__0 => - undefined_bitvector 64 >>= fun w__1 => + + (undefined_bitvector 53) >>= fun w__0 : mword 53 => + (undefined_bitvector 64) >>= fun w__1 : mword 64 => returnm (({| TLBEntry_TLBEntry_chunk_1 := w__0; TLBEntry_TLBEntry_chunk_0 := w__1 |}) : TLBEntry). Definition Mk_TLBEntry (v : mword 117) : TLBEntry := + {| TLBEntry_TLBEntry_chunk_1 := (subrange_vec_dec v 116 64); TLBEntry_TLBEntry_chunk_0 := (subrange_vec_dec v 63 0) |}. Definition _get_TLBEntry_bits (v : TLBEntry) : mword 117 := + concat_vec (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 0) (subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 0). -Definition _set_TLBEntry_bits (r_ref : register_ref regstate register_value TLBEntry) (v : mword 117) +Definition _set_TLBEntry_bits +(r_ref : register_ref regstate register_value TLBEntry) (v : mword 117) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_1 := @@ -803,6 +948,7 @@ Definition _set_TLBEntry_bits (r_ref : register_ref regstate register_value TLBE Definition _update_TLBEntry_bits (v : TLBEntry) (x : mword 117) : TLBEntry := + let v := {[ v with TLBEntry_TLBEntry_chunk_1 := @@ -813,11 +959,14 @@ Definition _update_TLBEntry_bits (v : TLBEntry) (x : mword 117) Definition _get_TLBEntry_pagemask (v : TLBEntry) : mword 16 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37. -Definition _set_TLBEntry_pagemask (r_ref : register_ref regstate register_value TLBEntry) (v : mword 16) +Definition _set_TLBEntry_pagemask +(r_ref : register_ref regstate register_value TLBEntry) (v : mword 16) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_1 := @@ -828,17 +977,20 @@ Definition _set_TLBEntry_pagemask (r_ref : register_ref regstate register_value Definition _update_TLBEntry_pagemask (v : TLBEntry) (x : mword 16) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_1 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 52 37 (subrange_vec_dec x 15 0)) ]}. Definition _get_TLBEntry_r (v : TLBEntry) : mword 2 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35. Definition _set_TLBEntry_r (r_ref : register_ref regstate register_value TLBEntry) (v : mword 2) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_1 := @@ -849,17 +1001,21 @@ Definition _set_TLBEntry_r (r_ref : register_ref regstate register_value TLBEntr Definition _update_TLBEntry_r (v : TLBEntry) (x : mword 2) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_1 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 36 35 (subrange_vec_dec x 1 0)) ]}. Definition _get_TLBEntry_vpn2 (v : TLBEntry) : mword 27 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8. -Definition _set_TLBEntry_vpn2 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 27) +Definition _set_TLBEntry_vpn2 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 27) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_1 := @@ -870,17 +1026,20 @@ Definition _set_TLBEntry_vpn2 (r_ref : register_ref regstate register_value TLBE Definition _update_TLBEntry_vpn2 (v : TLBEntry) (x : mword 27) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_1 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 34 8 (subrange_vec_dec x 26 0)) ]}. Definition _get_TLBEntry_asid (v : TLBEntry) : mword 8 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0. Definition _set_TLBEntry_asid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 8) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_1 := @@ -891,17 +1050,20 @@ Definition _set_TLBEntry_asid (r_ref : register_ref regstate register_value TLBE Definition _update_TLBEntry_asid (v : TLBEntry) (x : mword 8) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_1 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_1) 7 0 (subrange_vec_dec x 7 0)) ]}. Definition _get_TLBEntry_g (v : TLBEntry) : mword 1 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63. Definition _set_TLBEntry_g (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -912,17 +1074,21 @@ Definition _set_TLBEntry_g (r_ref : register_ref regstate register_value TLBEntr Definition _update_TLBEntry_g (v : TLBEntry) (x : mword 1) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. Definition _get_TLBEntry_valid (v : TLBEntry) : mword 1 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62. -Definition _set_TLBEntry_valid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +Definition _set_TLBEntry_valid (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -933,17 +1099,21 @@ Definition _set_TLBEntry_valid (r_ref : register_ref regstate register_value TLB Definition _update_TLBEntry_valid (v : TLBEntry) (x : mword 1) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 62 62 (subrange_vec_dec x 0 0)) ]}. Definition _get_TLBEntry_caps1 (v : TLBEntry) : mword 1 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61. -Definition _set_TLBEntry_caps1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +Definition _set_TLBEntry_caps1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -954,17 +1124,21 @@ Definition _set_TLBEntry_caps1 (r_ref : register_ref regstate register_value TLB Definition _update_TLBEntry_caps1 (v : TLBEntry) (x : mword 1) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 61 61 (subrange_vec_dec x 0 0)) ]}. Definition _get_TLBEntry_capl1 (v : TLBEntry) : mword 1 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60. -Definition _set_TLBEntry_capl1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +Definition _set_TLBEntry_capl1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -975,17 +1149,21 @@ Definition _set_TLBEntry_capl1 (r_ref : register_ref regstate register_value TLB Definition _update_TLBEntry_capl1 (v : TLBEntry) (x : mword 1) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 60 60 (subrange_vec_dec x 0 0)) ]}. Definition _get_TLBEntry_pfn1 (v : TLBEntry) : mword 24 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36. -Definition _set_TLBEntry_pfn1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) +Definition _set_TLBEntry_pfn1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -996,17 +1174,20 @@ Definition _set_TLBEntry_pfn1 (r_ref : register_ref regstate register_value TLBE Definition _update_TLBEntry_pfn1 (v : TLBEntry) (x : mword 24) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 59 36 (subrange_vec_dec x 23 0)) ]}. Definition _get_TLBEntry_c1 (v : TLBEntry) : mword 3 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33. Definition _set_TLBEntry_c1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -1017,17 +1198,20 @@ Definition _set_TLBEntry_c1 (r_ref : register_ref regstate register_value TLBEnt Definition _update_TLBEntry_c1 (v : TLBEntry) (x : mword 3) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 35 33 (subrange_vec_dec x 2 0)) ]}. Definition _get_TLBEntry_d1 (v : TLBEntry) : mword 1 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32. Definition _set_TLBEntry_d1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -1038,17 +1222,20 @@ Definition _set_TLBEntry_d1 (r_ref : register_ref regstate register_value TLBEnt Definition _update_TLBEntry_d1 (v : TLBEntry) (x : mword 1) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 32 32 (subrange_vec_dec x 0 0)) ]}. Definition _get_TLBEntry_v1 (v : TLBEntry) : mword 1 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31. Definition _set_TLBEntry_v1 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -1059,17 +1246,21 @@ Definition _set_TLBEntry_v1 (r_ref : register_ref regstate register_value TLBEnt Definition _update_TLBEntry_v1 (v : TLBEntry) (x : mword 1) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 31 31 (subrange_vec_dec x 0 0)) ]}. Definition _get_TLBEntry_caps0 (v : TLBEntry) : mword 1 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30. -Definition _set_TLBEntry_caps0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +Definition _set_TLBEntry_caps0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -1080,17 +1271,21 @@ Definition _set_TLBEntry_caps0 (r_ref : register_ref regstate register_value TLB Definition _update_TLBEntry_caps0 (v : TLBEntry) (x : mword 1) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 30 30 (subrange_vec_dec x 0 0)) ]}. Definition _get_TLBEntry_capl0 (v : TLBEntry) : mword 1 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29. -Definition _set_TLBEntry_capl0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) +Definition _set_TLBEntry_capl0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -1101,17 +1296,21 @@ Definition _set_TLBEntry_capl0 (r_ref : register_ref regstate register_value TLB Definition _update_TLBEntry_capl0 (v : TLBEntry) (x : mword 1) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 29 29 (subrange_vec_dec x 0 0)) ]}. Definition _get_TLBEntry_pfn0 (v : TLBEntry) : mword 24 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5. -Definition _set_TLBEntry_pfn0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) +Definition _set_TLBEntry_pfn0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 24) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -1122,17 +1321,20 @@ Definition _set_TLBEntry_pfn0 (r_ref : register_ref regstate register_value TLBE Definition _update_TLBEntry_pfn0 (v : TLBEntry) (x : mword 24) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 28 5 (subrange_vec_dec x 23 0)) ]}. Definition _get_TLBEntry_c0 (v : TLBEntry) : mword 3 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2. Definition _set_TLBEntry_c0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 3) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -1143,17 +1345,20 @@ Definition _set_TLBEntry_c0 (r_ref : register_ref regstate register_value TLBEnt Definition _update_TLBEntry_c0 (v : TLBEntry) (x : mword 3) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 4 2 (subrange_vec_dec x 2 0)) ]}. Definition _get_TLBEntry_d0 (v : TLBEntry) : mword 1 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1. Definition _set_TLBEntry_d0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -1164,17 +1369,20 @@ Definition _set_TLBEntry_d0 (r_ref : register_ref regstate register_value TLBEnt Definition _update_TLBEntry_d0 (v : TLBEntry) (x : mword 1) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. Definition _get_TLBEntry_v0 (v : TLBEntry) : mword 1 := + subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0. Definition _set_TLBEntry_v0 (r_ref : register_ref regstate register_value TLBEntry) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with TLBEntry_TLBEntry_chunk_0 := @@ -1185,6 +1393,7 @@ Definition _set_TLBEntry_v0 (r_ref : register_ref regstate register_value TLBEnt Definition _update_TLBEntry_v0 (v : TLBEntry) (x : mword 1) : TLBEntry := + {[ v with TLBEntry_TLBEntry_chunk_0 := (update_subrange_vec_dec v.(TLBEntry_TLBEntry_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. @@ -1194,24 +1403,29 @@ vec_of_list_len [TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLB TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref;TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref;TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref;TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref; TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref;TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref;TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref;TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref; TLBEntry00_ref]. - +Hint Unfold TLBEntries : sail. Definition undefined_StatusReg '(tt : unit) : M (StatusReg) := - undefined_bitvector 32 >>= fun w__0 => + + (undefined_bitvector 32) >>= fun w__0 : mword 32 => returnm (({| StatusReg_StatusReg_chunk_0 := w__0 |}) : StatusReg). Definition Mk_StatusReg (v : mword 32) : StatusReg := + {| StatusReg_StatusReg_chunk_0 := (subrange_vec_dec v 31 0) |}. Definition _get_StatusReg_bits (v : StatusReg) : mword 32 := + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0. -Definition _set_StatusReg_bits (r_ref : register_ref regstate register_value StatusReg) (v : mword 32) +Definition _set_StatusReg_bits +(r_ref : register_ref regstate register_value StatusReg) (v : mword 32) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with StatusReg_StatusReg_chunk_0 := @@ -1222,17 +1436,20 @@ Definition _set_StatusReg_bits (r_ref : register_ref regstate register_value Sta Definition _update_StatusReg_bits (v : StatusReg) (x : mword 32) : StatusReg := + {[ v with StatusReg_StatusReg_chunk_0 := (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. Definition _get_StatusReg_CU (v : StatusReg) : mword 4 := + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28. Definition _set_StatusReg_CU (r_ref : register_ref regstate register_value StatusReg) (v : mword 4) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with StatusReg_StatusReg_chunk_0 := @@ -1243,17 +1460,21 @@ Definition _set_StatusReg_CU (r_ref : register_ref regstate register_value Statu Definition _update_StatusReg_CU (v : StatusReg) (x : mword 4) : StatusReg := + {[ v with StatusReg_StatusReg_chunk_0 := (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 31 28 (subrange_vec_dec x 3 0)) ]}. Definition _get_StatusReg_BEV (v : StatusReg) : mword 1 := + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22. -Definition _set_StatusReg_BEV (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +Definition _set_StatusReg_BEV (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with StatusReg_StatusReg_chunk_0 := @@ -1264,17 +1485,20 @@ Definition _set_StatusReg_BEV (r_ref : register_ref regstate register_value Stat Definition _update_StatusReg_BEV (v : StatusReg) (x : mword 1) : StatusReg := + {[ v with StatusReg_StatusReg_chunk_0 := (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. Definition _get_StatusReg_IM (v : StatusReg) : mword 8 := + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8. Definition _set_StatusReg_IM (r_ref : register_ref regstate register_value StatusReg) (v : mword 8) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with StatusReg_StatusReg_chunk_0 := @@ -1285,17 +1509,20 @@ Definition _set_StatusReg_IM (r_ref : register_ref regstate register_value Statu Definition _update_StatusReg_IM (v : StatusReg) (x : mword 8) : StatusReg := + {[ v with StatusReg_StatusReg_chunk_0 := (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 15 8 (subrange_vec_dec x 7 0)) ]}. Definition _get_StatusReg_KX (v : StatusReg) : mword 1 := + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7. Definition _set_StatusReg_KX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with StatusReg_StatusReg_chunk_0 := @@ -1306,17 +1533,20 @@ Definition _set_StatusReg_KX (r_ref : register_ref regstate register_value Statu Definition _update_StatusReg_KX (v : StatusReg) (x : mword 1) : StatusReg := + {[ v with StatusReg_StatusReg_chunk_0 := (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. Definition _get_StatusReg_SX (v : StatusReg) : mword 1 := + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6. Definition _set_StatusReg_SX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with StatusReg_StatusReg_chunk_0 := @@ -1327,17 +1557,20 @@ Definition _set_StatusReg_SX (r_ref : register_ref regstate register_value Statu Definition _update_StatusReg_SX (v : StatusReg) (x : mword 1) : StatusReg := + {[ v with StatusReg_StatusReg_chunk_0 := (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. Definition _get_StatusReg_UX (v : StatusReg) : mword 1 := + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5. Definition _set_StatusReg_UX (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with StatusReg_StatusReg_chunk_0 := @@ -1348,17 +1581,21 @@ Definition _set_StatusReg_UX (r_ref : register_ref regstate register_value Statu Definition _update_StatusReg_UX (v : StatusReg) (x : mword 1) : StatusReg := + {[ v with StatusReg_StatusReg_chunk_0 := (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. Definition _get_StatusReg_KSU (v : StatusReg) : mword 2 := + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3. -Definition _set_StatusReg_KSU (r_ref : register_ref regstate register_value StatusReg) (v : mword 2) +Definition _set_StatusReg_KSU (r_ref : register_ref regstate register_value StatusReg) (v : mword 2) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with StatusReg_StatusReg_chunk_0 := @@ -1369,17 +1606,21 @@ Definition _set_StatusReg_KSU (r_ref : register_ref regstate register_value Stat Definition _update_StatusReg_KSU (v : StatusReg) (x : mword 2) : StatusReg := + {[ v with StatusReg_StatusReg_chunk_0 := (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 4 3 (subrange_vec_dec x 1 0)) ]}. Definition _get_StatusReg_ERL (v : StatusReg) : mword 1 := + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2. -Definition _set_StatusReg_ERL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +Definition _set_StatusReg_ERL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with StatusReg_StatusReg_chunk_0 := @@ -1390,17 +1631,21 @@ Definition _set_StatusReg_ERL (r_ref : register_ref regstate register_value Stat Definition _update_StatusReg_ERL (v : StatusReg) (x : mword 1) : StatusReg := + {[ v with StatusReg_StatusReg_chunk_0 := (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. Definition _get_StatusReg_EXL (v : StatusReg) : mword 1 := + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1. -Definition _set_StatusReg_EXL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) +Definition _set_StatusReg_EXL (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) + : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with StatusReg_StatusReg_chunk_0 := @@ -1411,17 +1656,20 @@ Definition _set_StatusReg_EXL (r_ref : register_ref regstate register_value Stat Definition _update_StatusReg_EXL (v : StatusReg) (x : mword 1) : StatusReg := + {[ v with StatusReg_StatusReg_chunk_0 := (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. Definition _get_StatusReg_IE (v : StatusReg) : mword 1 := + subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0. Definition _set_StatusReg_IE (r_ref : register_ref regstate register_value StatusReg) (v : mword 1) : M (unit) := - reg_deref r_ref >>= fun r => + + (reg_deref r_ref) >>= fun r => let r := {[ r with StatusReg_StatusReg_chunk_0 := @@ -1432,24 +1680,28 @@ Definition _set_StatusReg_IE (r_ref : register_ref regstate register_value Statu Definition _update_StatusReg_IE (v : StatusReg) (x : mword 1) : StatusReg := + {[ v with StatusReg_StatusReg_chunk_0 := (update_subrange_vec_dec v.(StatusReg_StatusReg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. -Definition execute_branch (pc : mword 64) +Definition execute_branch_mips (pc : mword 64) : M (unit) := - write_reg delayedPC_ref pc >> - write_reg branchPending_ref (vec_of_bits [B1] : mword 1) + + write_reg DelayedPC_ref pc >> + write_reg BranchPending_ref (vec_of_bits [B1] : mword 1) >> + write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) : M (unit). Definition NotWordVal (word : mword 64) : bool := - neq_vec (zopz0zQzQ ((cast_unit_vec (access_vec_dec word 31)) : mword 1) 32) - (subrange_vec_dec word 63 32). + + neq_vec (zopz0zQzQ (cast_unit_vec (access_vec_dec word 31)) 32) (subrange_vec_dec word 63 32). Definition rGPR (idx : mword 5) : M (mword 64) := - let '(existT _ i _) := uint idx in + + let 'i := projT1 (uint idx) in (if sumbool_of_bool ((Z.eqb i 0)) then returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -1457,53 +1709,61 @@ Definition rGPR (idx : mword 5) B0] : mword 64) : mword 64) - else read_reg GPR_ref >>= fun w__0 => returnm ((vec_access_dec w__0 i) : mword 64)) + else + read_reg GPR_ref >>= fun w__0 : vec (bits 64) 32 => + returnm ((vec_access_dec w__0 i) + : mword 64)) : M (mword 64). Definition wGPR (idx : mword 5) (v : mword 64) : M (unit) := - let '(existT _ i _) := uint idx in - (if ((neq_atom i 0)) then - read_reg GPR_ref >>= fun w__0 => write_reg GPR_ref (vec_update_dec w__0 i v) : M (unit) + + let 'i := projT1 (uint idx) in + (if ((neq_int i 0)) then + let '_ := + (if (trace) then + let '_ := (prerr (string_of_int i)) : unit in + prerr_bits " <- " v + else tt) + : unit in + read_reg GPR_ref >>= fun w__0 : vec (bits 64) 32 => + write_reg GPR_ref (vec_update_dec w__0 i v) + : M (unit) else returnm (tt : unit)) : M (unit). -Definition MEMr (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} `{ArithFact (size = size)} +Definition MEMr (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} : M (mword (8 * size)) := - (autocast_m (__MIPS_read addr size)) + + (__MIPS_read addr size) : M (mword (8 * size)). -Definition MEMr_reserve (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} `{ArithFact (size = - size)} +Definition MEMr_reserve (addr : mword 64) (size : Z) `{ArithFact (size >= 0)} : M (mword (8 * size)) := - (autocast_m (__MIPS_read addr size)) + + (__MIPS_read addr size) : M (mword (8 * size)). -Definition MEM_sync '(tt : unit) : M (unit) := (skip tt) : M (unit). +Definition MEM_sync '(tt : unit) : M (unit) := (skip tt) : M (unit). -Definition MEMea (addr : mword 64) (size : Z) `{ArithFact (size = size)} -: M (unit) := - (skip tt) - : M (unit). +Definition MEMea (addr : mword 64) (size : Z) : M (unit) := (skip tt) : M (unit). -Definition MEMea_conditional (addr : mword 64) (size : Z) `{ArithFact (size = size)} -: M (unit) := - (skip tt) - : M (unit). +Definition MEMea_conditional (addr : mword 64) (size : Z) : M (unit) := (skip tt) : M (unit). -Definition MEMval (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (size = size)} +Definition MEMval (addr : mword 64) (size : Z) (data : mword (8 * size)) : M (unit) := + (__MIPS_write addr size data) : M (unit). -Definition MEMval_conditional (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (size = - size)} +Definition MEMval_conditional (addr : mword 64) (size : Z) (data : mword (8 * size)) : M (bool) := - __MIPS_write addr size data >> returnm (true : bool). + + (__MIPS_write addr size data) >> returnm (true : bool). -Definition Exception_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 18)} `{ArithFact (arg_ = - arg_)} +Definition Exception_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 18)} : Exception := + let p0_ := arg_ in if sumbool_of_bool ((Z.eqb p0_ 0)) then Interrupt else if sumbool_of_bool ((Z.eqb p0_ 1)) then TLBMod @@ -1527,36 +1787,39 @@ Definition Exception_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 18)} `{ Definition num_of_Exception (arg_ : Exception) : {e : Z & ArithFact (0 <= e /\ e <= 18)} := - match arg_ with - | Interrupt => build_ex 0 - | TLBMod => build_ex 1 - | TLBL => build_ex 2 - | TLBS => build_ex 3 - | AdEL => build_ex 4 - | AdES => build_ex 5 - | Sys => build_ex 6 - | Bp => build_ex 7 - | ResI => build_ex 8 - | CpU => build_ex 9 - | Ov => build_ex 10 - | Tr => build_ex 11 - | C2E => build_ex 12 - | C2Trap => build_ex 13 - | XTLBRefillL => build_ex 14 - | XTLBRefillS => build_ex 15 - | XTLBInvL => build_ex 16 - | XTLBInvS => build_ex 17 - | MCheck => build_ex 18 - end. + + build_ex(match arg_ with + | Interrupt => 0 + | TLBMod => 1 + | TLBL => 2 + | TLBS => 3 + | AdEL => 4 + | AdES => 5 + | Sys => 6 + | Bp => 7 + | ResI => 8 + | CpU => 9 + | Ov => 10 + | Tr => 11 + | C2E => 12 + | C2Trap => 13 + | XTLBRefillL => 14 + | XTLBRefillS => 15 + | XTLBInvL => 16 + | XTLBInvS => 17 + | MCheck => 18 + end). Definition undefined_Exception '(tt : unit) : M (Exception) := + (internal_pick [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]) : M (Exception). Definition ExceptionCode (ex : Exception) : mword 5 := + let x : bits 8 := match ex with | Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) @@ -1581,35 +1844,75 @@ Definition ExceptionCode (ex : Exception) end in subrange_vec_dec x 4 0. +Definition string_of_exception (ex : Exception) +: string := + + match ex with + | Interrupt => "Interrupt" + | TLBMod => "TLBMod" + | TLBL => "TLBL" + | TLBS => "TLBS" + | AdEL => "AdEL" + | AdES => "AdES" + | Sys => "Sys" + | Bp => "Bp " + | ResI => "ResI" + | CpU => "CpU" + | Ov => "Ov" + | Tr => "Tr" + | C2E => "C2E" + | C2Trap => "C2Trap" + | XTLBRefillL => "XTLBRefillL" + | XTLBRefillS => "XTLBRefillS" + | XTLBInvL => "XTLBInvL" + | XTLBInvS => "XTLBInvS" + | MCheck => "MCheck" + end. + Definition SignalExceptionMIPS {o : Type} (ex : Exception) (kccBase : mword 64) : M (o) := - read_reg CP0Status_ref >>= fun w__0 => + + let '_ := + (if (trace) then + let '_ := (prerr " EXCEPTION ") : unit in + prerr_endline (string_of_exception ex) + else tt) + : unit in + read_reg CP0Status_ref >>= fun w__0 : StatusReg => (if ((negb ((bits_to_bool (_get_StatusReg_EXL w__0)) : bool))) then - (read_reg inBranchDelay_ref : M (mword 1)) >>= fun w__1 => + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__1 : bits 1 => (if (((bit_to_bool (access_vec_dec w__1 0)) : bool)) then - (read_reg PC_ref : M (mword 64)) >>= fun w__2 => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => write_reg CP0EPC_ref (sub_vec_int w__2 4) >> (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] : mword 1)) : M (unit) else - (read_reg PC_ref : M (mword 64)) >>= fun w__3 => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : bits 64 => write_reg CP0EPC_ref w__3 >> (_set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] : mword 1)) : M (unit)) : M (unit) else returnm (tt : unit)) >> - read_reg CP0Status_ref >>= fun w__4 => + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__4 : bits 1 => + (if (((bit_to_bool (access_vec_dec w__4 0)) : bool)) then + ((read_reg LastInstrBits_ref) : M (mword 32)) >>= fun w__5 : bits 32 => + write_reg CP0BadInstrP_ref w__5 + : M (unit) + else returnm (tt : unit)) >> + ((read_reg CurrentInstrBits_ref) : M (mword 32)) >>= fun w__6 : bits 32 => + write_reg CP0BadInstr_ref w__6 >> + read_reg CP0Status_ref >>= fun w__7 : StatusReg => let vectorOffset := - if (((bits_to_bool (_get_StatusReg_EXL w__4)) : bool)) then + if (((bits_to_bool (_get_StatusReg_EXL w__7)) : bool)) then (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) else if ((orb (generic_eq ex XTLBRefillL) (generic_eq ex XTLBRefillS))) then (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) else if ((generic_eq ex C2Trap)) then (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) in - read_reg CP0Status_ref >>= fun w__5 => + read_reg CP0Status_ref >>= fun w__8 : StatusReg => let vectorBase : bits 64 := - if (((bits_to_bool (_get_StatusReg_BEV w__5)) : bool)) then + if (((bits_to_bool (_get_StatusReg_BEV w__8)) : bool)) then (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0; @@ -1621,14 +1924,16 @@ Definition SignalExceptionMIPS {o : Type} (ex : Exception) (kccBase : mword 64) B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0] : mword 64) in - write_reg nextPC_ref (sub_vec (add_vec vectorBase (mips_sign_extend 64 vectorOffset)) kccBase) >> - _set_CauseReg_ExcCode CP0Cause_ref (ExceptionCode ex) >> - _set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] : mword 1) >> - (throw (ISAException tt)) + write_reg NextPC_ref (sub_vec (add_vec vectorBase (mips_sign_extend 64 vectorOffset)) kccBase) >> + (_set_CauseReg_ExcCode CP0Cause_ref (ExceptionCode ex)) >> + (_set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] : mword 1)) >> + (throw (ISAException + (tt))) : M (o). Definition SignalException {o : Type} (ex : Exception) : M (o) := + (SignalExceptionMIPS ex (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -1639,22 +1944,24 @@ Definition SignalException {o : Type} (ex : Exception) Definition SignalExceptionBadAddr {o : Type} (ex : Exception) (badAddr : mword 64) : M (o) := + write_reg CP0BadVAddr_ref badAddr >> (SignalException ex) : M (o). Definition SignalExceptionTLB {o : Type} (ex : Exception) (badAddr : mword 64) : M (o) := + write_reg CP0BadVAddr_ref badAddr >> - _set_ContextReg_BadVPN2 TLBContext_ref (subrange_vec_dec badAddr 31 13) >> - _set_XContextReg_XBadVPN2 TLBXContext_ref (subrange_vec_dec badAddr 39 13) >> - _set_XContextReg_XR TLBXContext_ref (subrange_vec_dec badAddr 63 62) >> - _set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec badAddr 63 62) >> - _set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec badAddr 39 13) >> + (_set_ContextReg_BadVPN2 TLBContext_ref (subrange_vec_dec badAddr 31 13)) >> + (_set_XContextReg_XBadVPN2 TLBXContext_ref (subrange_vec_dec badAddr 39 13)) >> + (_set_XContextReg_XR TLBXContext_ref (subrange_vec_dec badAddr 63 62)) >> + (_set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec badAddr 63 62)) >> + (_set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec badAddr 39 13)) >> (SignalException ex) : M (o). -Definition MemAccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} `{ArithFact (arg_ = - arg_)} +Definition MemAccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} : MemAccessType := + let p0_ := arg_ in if sumbool_of_bool ((Z.eqb p0_ 0)) then Instruction else if sumbool_of_bool ((Z.eqb p0_ 1)) then LoadData @@ -1662,20 +1969,18 @@ Definition MemAccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} Definition num_of_MemAccessType (arg_ : MemAccessType) : {e : Z & ArithFact (0 <= e /\ e <= 2)} := - match arg_ with - | Instruction => build_ex 0 - | LoadData => build_ex 1 - | StoreData => build_ex 2 - end. + + build_ex(match arg_ with | Instruction => 0 | LoadData => 1 | StoreData => 2 end). Definition undefined_MemAccessType '(tt : unit) : M (MemAccessType) := + (internal_pick [Instruction;LoadData;StoreData]) : M (MemAccessType). -Definition AccessLevel_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} `{ArithFact (arg_ = - arg_)} +Definition AccessLevel_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} : AccessLevel := + let p0_ := arg_ in if sumbool_of_bool ((Z.eqb p0_ 0)) then User else if sumbool_of_bool ((Z.eqb p0_ 1)) then Supervisor @@ -1683,35 +1988,40 @@ Definition AccessLevel_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} ` Definition num_of_AccessLevel (arg_ : AccessLevel) : {e : Z & ArithFact (0 <= e /\ e <= 2)} := - match arg_ with | User => build_ex 0 | Supervisor => build_ex 1 | Kernel => build_ex 2 end. + + build_ex(match arg_ with | User => 0 | Supervisor => 1 | Kernel => 2 end). Definition undefined_AccessLevel '(tt : unit) : M (AccessLevel) := + (internal_pick [User;Supervisor;Kernel]) : M (AccessLevel). Definition int_of_AccessLevel (level : AccessLevel) -: Z := - match level with | User => 0 | Supervisor => 1 | Kernel => 2 end. +: {n : Z & ArithFact (In n [0; 1; 2])} := + + build_ex(match level with | User => 0 | Supervisor => 1 | Kernel => 2 end). Definition grantsAccess (currentLevel : AccessLevel) (requiredLevel : AccessLevel) : bool := - Z.geb (int_of_AccessLevel currentLevel) (int_of_AccessLevel requiredLevel). + + Z.geb (projT1 (int_of_AccessLevel currentLevel)) (projT1 (int_of_AccessLevel requiredLevel)). Definition getAccessLevel '(tt : unit) : M (AccessLevel) := - or_boolM - (read_reg CP0Status_ref >>= fun w__0 => - returnm ((bits_to_bool (_get_StatusReg_EXL w__0)) - : bool)) - (read_reg CP0Status_ref >>= fun w__1 => - returnm ((bits_to_bool (_get_StatusReg_ERL w__1)) - : bool)) >>= fun w__2 => + + (or_boolM + (read_reg CP0Status_ref >>= fun w__0 : StatusReg => + returnm ((bits_to_bool (_get_StatusReg_EXL w__0)) + : bool)) + (read_reg CP0Status_ref >>= fun w__1 : StatusReg => + returnm ((bits_to_bool (_get_StatusReg_ERL w__1)) + : bool))) >>= fun w__2 : bool => (if (w__2) then returnm (Kernel : AccessLevel) else - read_reg CP0Status_ref >>= fun w__3 => - let p__27 := _get_StatusReg_KSU w__3 in - let b__0 := p__27 in + read_reg CP0Status_ref >>= fun w__3 : StatusReg => + let p__16 := _get_StatusReg_KSU w__3 in + let b__0 := p__16 in returnm ((if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then Kernel else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Supervisor else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then User @@ -1721,13 +2031,14 @@ Definition getAccessLevel '(tt : unit) Definition checkCP0Access '(tt : unit) : M (unit) := - getAccessLevel tt >>= fun accessLevel => - and_boolM (returnm ((generic_neq accessLevel Kernel) : bool)) - (read_reg CP0Status_ref >>= fun w__0 => - returnm ((negb ((bit_to_bool (access_vec_dec (_get_StatusReg_CU w__0) 0)) : bool)) - : bool)) >>= fun w__1 => + + (getAccessLevel tt) >>= fun accessLevel => + (and_boolM (returnm ((generic_neq accessLevel Kernel) : bool)) + (read_reg CP0Status_ref >>= fun w__0 : StatusReg => + returnm ((negb ((bit_to_bool (access_vec_dec (_get_StatusReg_CU w__0) 0)) : bool)) + : bool))) >>= fun w__1 : bool => (if (w__1) then - _set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0] : mword 2) >> + (_set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0] : mword 2)) >> (SignalException CpU) : M (unit) else returnm (tt : unit)) @@ -1735,33 +2046,34 @@ Definition checkCP0Access '(tt : unit) Definition incrementCP0Count '(tt : unit) : M (unit) := - (read_reg TLBRandom_ref : M (mword 6)) >>= fun w__0 => - (read_reg TLBWired_ref : M (mword 6)) >>= fun w__1 => + + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + ((read_reg TLBWired_ref) : M (mword 6)) >>= fun w__1 : TLBIndexT => (if ((eq_vec w__0 w__1)) then returnm (TLBIndexMax : TLBIndexT) else - (read_reg TLBRandom_ref : M (mword 6)) >>= fun w__2 => + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__2 : TLBIndexT => returnm ((sub_vec_int w__2 1) - : TLBIndexT)) >>= fun w__3 => + : mword 6)) >>= fun w__3 : mword 6 => write_reg TLBRandom_ref w__3 >> - (read_reg CP0Count_ref : M (mword 32)) >>= fun w__4 => + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__4 : bits 32 => write_reg CP0Count_ref (add_vec_int w__4 1) >> - (read_reg CP0Count_ref : M (mword 32)) >>= fun w__5 => - (read_reg CP0Compare_ref : M (mword 32)) >>= fun w__6 => + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__5 : bits 32 => + ((read_reg CP0Compare_ref) : M (mword 32)) >>= fun w__6 : bits 32 => (if ((eq_vec w__5 w__6)) then - read_reg CP0Cause_ref >>= fun w__7 => + read_reg CP0Cause_ref >>= fun w__7 : CauseReg => (_set_CauseReg_IP CP0Cause_ref (or_vec (_get_CauseReg_IP w__7) (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0] : mword 8))) : M (unit) else returnm (tt : unit)) >> - read_reg CP0Status_ref >>= fun w__8 => + read_reg CP0Status_ref >>= fun w__8 : StatusReg => let ims := _get_StatusReg_IM w__8 in - read_reg CP0Cause_ref >>= fun w__9 => + read_reg CP0Cause_ref >>= fun w__9 : CauseReg => let ips := _get_CauseReg_IP w__9 in - read_reg CP0Status_ref >>= fun w__10 => + read_reg CP0Status_ref >>= fun w__10 : StatusReg => let ie := _get_StatusReg_IE w__10 in - read_reg CP0Status_ref >>= fun w__11 => + read_reg CP0Status_ref >>= fun w__11 : StatusReg => let exl := _get_StatusReg_EXL w__11 in - read_reg CP0Status_ref >>= fun w__12 => + read_reg CP0Status_ref >>= fun w__12 : StatusReg => let erl := _get_StatusReg_ERL w__12 in (if ((andb (negb ((bits_to_bool exl) : bool)) (andb (negb ((bits_to_bool erl) : bool)) @@ -1773,9 +2085,9 @@ Definition incrementCP0Count '(tt : unit) else returnm (tt : unit)) : M (unit). -Definition decode_failure_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{ArithFact (arg_ = - arg_)} +Definition decode_failure_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} : decode_failure := + let p0_ := arg_ in if sumbool_of_bool ((Z.eqb p0_ 0)) then no_matching_pattern else if sumbool_of_bool ((Z.eqb p0_ 1)) then unsupported_instruction @@ -1784,21 +2096,23 @@ Definition decode_failure_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3) Definition num_of_decode_failure (arg_ : decode_failure) : {e : Z & ArithFact (0 <= e /\ e <= 3)} := - match arg_ with - | no_matching_pattern => build_ex 0 - | unsupported_instruction => build_ex 1 - | illegal_instruction => build_ex 2 - | internal_error => build_ex 3 - end. + + build_ex(match arg_ with + | no_matching_pattern => 0 + | unsupported_instruction => 1 + | illegal_instruction => 2 + | internal_error => 3 + end). Definition undefined_decode_failure '(tt : unit) : M (decode_failure) := + (internal_pick [no_matching_pattern;unsupported_instruction;illegal_instruction;internal_error]) : M (decode_failure). -Definition Comparison_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 7)} `{ArithFact (arg_ = - arg_)} +Definition Comparison_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 7)} : Comparison := + let p0_ := arg_ in if sumbool_of_bool ((Z.eqb p0_ 0)) then EQ' else if sumbool_of_bool ((Z.eqb p0_ 1)) then NE @@ -1811,24 +2125,27 @@ Definition Comparison_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 7)} `{ Definition num_of_Comparison (arg_ : Comparison) : {e : Z & ArithFact (0 <= e /\ e <= 7)} := - match arg_ with - | EQ' => build_ex 0 - | NE => build_ex 1 - | GE => build_ex 2 - | GEU => build_ex 3 - | GT' => build_ex 4 - | LE => build_ex 5 - | LT' => build_ex 6 - | LTU => build_ex 7 - end. + + build_ex(match arg_ with + | EQ' => 0 + | NE => 1 + | GE => 2 + | GEU => 3 + | GT' => 4 + | LE => 5 + | LT' => 6 + | LTU => 7 + end). Definition undefined_Comparison '(tt : unit) : M (Comparison) := + (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU]) : M (Comparison). Definition compare (cmp : Comparison) (valA : mword 64) (valB : mword 64) : bool := + match cmp with | EQ' => eq_vec valA valB | NE => neq_vec valA valB @@ -1840,8 +2157,9 @@ Definition compare (cmp : Comparison) (valA : mword 64) (valB : mword 64) | LTU => zopz0zI_u valA valB end. -Definition WordType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{ArithFact (arg_ = arg_)} +Definition WordType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} : WordType := + let p0_ := arg_ in if sumbool_of_bool ((Z.eqb p0_ 0)) then B else if sumbool_of_bool ((Z.eqb p0_ 1)) then H @@ -1850,16 +2168,18 @@ Definition WordType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{Ar Definition num_of_WordType (arg_ : WordType) : {e : Z & ArithFact (0 <= e /\ e <= 3)} := - match arg_ with | B => build_ex 0 | H => build_ex 1 | W => build_ex 2 | D => build_ex 3 end. + + build_ex(match arg_ with | B => 0 | H => 1 | W => 2 | D => 3 end). Definition undefined_WordType '(tt : unit) : M (WordType) := + (internal_pick [B;H;W;D]) : M (WordType). -Definition WordTypeUnaligned_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} `{ArithFact (arg_ = - arg_)} +Definition WordTypeUnaligned_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} : WordTypeUnaligned := + let p0_ := arg_ in if sumbool_of_bool ((Z.eqb p0_ 0)) then WL else if sumbool_of_bool ((Z.eqb p0_ 1)) then WR @@ -1868,37 +2188,47 @@ Definition WordTypeUnaligned_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= Definition num_of_WordTypeUnaligned (arg_ : WordTypeUnaligned) : {e : Z & ArithFact (0 <= e /\ e <= 3)} := - match arg_ with | WL => build_ex 0 | WR => build_ex 1 | DL => build_ex 2 | DR => build_ex 3 end. + + build_ex(match arg_ with | WL => 0 | WR => 1 | DL => 2 | DR => 3 end). Definition undefined_WordTypeUnaligned '(tt : unit) : M (WordTypeUnaligned) := + (internal_pick [WL;WR;DL;DR]) : M (WordTypeUnaligned). Definition wordWidthBytes (w : WordType) : {rangevar : Z & ArithFact (1 <= rangevar /\ rangevar <= 8)} := - match w with | B => build_ex 1 | H => build_ex 2 | W => build_ex 4 | D => build_ex 8 end. + + build_ex(match w with | B => 1 | H => 2 | W => 4 | D => 8 end). Definition alignment_width := 16. - +Hint Unfold alignment_width : sail. Definition isAddressAligned (addr : mword 64) (wordType : WordType) : bool := - let '(existT _ a _) := uint addr in - Z.eqb (projT1 (div_with_eq a alignment_width)) - (Z.quot (Z.sub (Z.add a (projT1 (wordWidthBytes wordType))) 1) alignment_width). + + let 'a := projT1 (uint addr) in + Z.eqb (projT1 (ediv_with_eq a alignment_width)) + (projT1 (ediv_with_eq (Z.sub (Z.add a (projT1 (wordWidthBytes wordType))) 1) alignment_width)). -Definition MEMr_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} `{ArithFact (size = - size)} +Definition extendLoad {sz : Z} (memResult : mword sz) (sign : bool) `{ArithFact (sz <= 64)} +: mword 64 := + + if (sign) then mips_sign_extend 64 memResult + else mips_zero_extend 64 memResult. + +Definition MEMr_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} : M (mword (8 * size)) := + (if ((eq_vec addr (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0] : mword 64))) then - (read_reg UART_RVALID_ref : M (mword 1)) >>= fun rvalid => + ((read_reg UART_RVALID_ref) : M (mword 1)) >>= fun rvalid => write_reg UART_RVALID_ref (vec_of_bits [B0] : mword 1) >> - (read_reg UART_RDATA_ref : M (mword 8)) >>= fun w__0 => + ((read_reg UART_RDATA_ref) : M (mword 8)) >>= fun w__0 : bits 8 => returnm ((mask (Z.mul 8 size) (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -1924,25 +2254,27 @@ Definition MEMr_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ s : mword 64)) : mword (8 * size)) else - autocast_m (MEMr addr size) >>= fun w__1 => - returnm ((autocast (reverse_endianness w__1)) + (MEMr addr size) >>= fun w__1 : mword (8 * size) => + returnm ((reverse_endianness w__1) : mword (8 * size))) : M (mword (8 * size)). -Definition MEMr_reserve_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} `{ArithFact (size = - size)} +Definition MEMr_reserve_wrapper (addr : mword 64) (size : Z) `{ArithFact (1 <= size /\ size <= 8)} : M (mword (8 * size)) := - autocast_m (MEMr_reserve addr size) >>= fun w__0 => - returnm ((autocast (reverse_endianness w__0)) + + (MEMr_reserve addr size) >>= fun w__0 : mword (8 * size) => + returnm ((reverse_endianness w__0) : mword (8 * size)). Definition init_cp0_state '(tt : unit) : M (unit) := + (_set_StatusReg_BEV CP0Status_ref ((cast_unit_vec B1) : mword 1)) : M (unit). Definition tlbEntryMatch (r : mword 2) (vpn2 : mword 27) (asid : mword 8) (entry : TLBEntry) : bool := + let entryValid := _get_TLBEntry_valid entry in let entryR := _get_TLBEntry_r entry in let entryMask := _get_TLBEntry_pagemask entry in @@ -1957,16 +2289,19 @@ Definition tlbEntryMatch (r : mword 2) (vpn2 : mword 27) (asid : mword 8) (entry Definition tlbSearch (VAddr : mword 64) : M (option (mword 6)) := + catch_early_return (let r := subrange_vec_dec VAddr 63 62 in let vpn2 := subrange_vec_dec VAddr 39 13 in - liftR (read_reg TLBEntryHi_ref) >>= fun w__0 => + liftR (read_reg TLBEntryHi_ref) >>= fun w__0 : TLBEntryHiReg => let asid := _get_TLBEntryHiReg_ASID w__0 in (foreach_ZM_up 0 63 1 tt (fun idx _ unit_var => - liftR (reg_deref (vec_access_dec TLBEntries idx)) >>= fun w__1 => + liftR ((reg_deref (vec_access_dec TLBEntries idx))) >>= fun w__1 : TLBEntry => (if ((tlbEntryMatch r vpn2 asid w__1)) then - (early_return ((Some (to_bits 6 idx)) : option (mword 6)) : MR unit (option (mword 6))) + (early_return ((Some + (to_bits 6 idx)) + : option (mword 6))) : MR (unit) _ else returnm (tt : unit)) : MR (unit) _)) >> @@ -1975,83 +2310,73 @@ Definition tlbSearch (VAddr : mword 64) Definition TLBTranslate2 (vAddr : mword 64) (accessType : MemAccessType) : M ((mword 64 * bool)) := - tlbSearch vAddr >>= fun idx => + + (tlbSearch vAddr) >>= fun idx => (match idx with | Some (idx) => - let '(existT _ i _) := uint idx in - reg_deref (vec_access_dec TLBEntries i) >>= fun entry => + let 'i := projT1 (uint idx) in + (reg_deref (vec_access_dec TLBEntries i)) >>= fun entry => let entryMask := _get_TLBEntry_pagemask entry in let b__0 := entryMask in (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16))) then - returnm ((build_ex - 12) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) + returnm (build_ex (12 + : Z)) else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 16))) then - returnm ((build_ex - 14) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) + returnm (build_ex (14 + : Z)) else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] : mword 16))) then - returnm ((build_ex - 16) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) + returnm (build_ex (16 + : Z)) else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1] : mword 16))) then - returnm ((build_ex - 18) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) + returnm (build_ex (18 + : Z)) else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then - returnm ((build_ex - 20) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) + returnm (build_ex (20 + : Z)) else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then - returnm ((build_ex - 22) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) + returnm (build_ex (22 + : Z)) else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then - returnm ((build_ex - 24) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) + returnm (build_ex (24 + : Z)) else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then - returnm ((build_ex - 26) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) + returnm (build_ex (26 + : Z)) else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] : mword 16))) then - returnm ((build_ex - 28) - : {rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)}) + returnm (build_ex (28 + : Z)) else (undefined_range 12 28) - : M ({rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})) >>= fun '(existT _ evenOddBit _) => + : M ({rangevar : Z & ArithFact (12 <= rangevar /\ rangevar <= 28)})) >>= fun '(existT _ evenOddBit _ : {rangevar : Z & ArithFact (12 <= + rangevar /\ + rangevar <= 28)}) => let isOdd := access_vec_dec vAddr evenOddBit in let '(caps, capl, pfn, d, v) := if (((bit_to_bool isOdd) : bool)) then - (_get_TLBEntry_caps1 entry, - _get_TLBEntry_capl1 entry, - _get_TLBEntry_pfn1 entry, - _get_TLBEntry_d1 entry, - _get_TLBEntry_v1 entry) + (_get_TLBEntry_caps1 entry, _get_TLBEntry_capl1 entry, _get_TLBEntry_pfn1 entry, _get_TLBEntry_d1 + entry, _get_TLBEntry_v1 + entry) else - (_get_TLBEntry_caps0 entry, - _get_TLBEntry_capl0 entry, - _get_TLBEntry_pfn0 entry, - _get_TLBEntry_d0 entry, - _get_TLBEntry_v0 entry) in + (_get_TLBEntry_caps0 entry, _get_TLBEntry_capl0 entry, _get_TLBEntry_pfn0 entry, _get_TLBEntry_d0 + entry, _get_TLBEntry_v0 + entry) in (if ((negb ((bits_to_bool v) : bool))) then (SignalExceptionTLB (if ((generic_eq accessType StoreData)) then XTLBInvS else XTLBInvL) vAddr) @@ -2064,8 +2389,7 @@ Definition TLBTranslate2 (vAddr : mword 64) (accessType : MemAccessType) mips_zero_extend 64 (concat_vec (subrange_vec_dec pfn 23 (Z.sub evenOddBit 12)) (subrange_vec_dec vAddr (Z.sub evenOddBit 1) 0)) in - returnm ((res, bits_to_bool (if ((generic_eq accessType StoreData)) then caps else capl)) - : (mword 64 * bool))) + returnm (res, bits_to_bool (if ((generic_eq accessType StoreData)) then caps else capl))) : M ((mword 64 * bool)) | None => (SignalExceptionTLB @@ -2077,75 +2401,85 @@ Definition TLBTranslate2 (vAddr : mword 64) (accessType : MemAccessType) Definition TLBTranslateC (vAddr : mword 64) (accessType : MemAccessType) : M ((mword 64 * bool)) := - getAccessLevel tt >>= fun currentAccessLevel => + + (getAccessLevel tt) >>= fun currentAccessLevel => let compat32 := eq_vec (subrange_vec_dec vAddr 61 31) (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1; B1;B1;B1;B1;B1;B1;B1;B1;B1;B1] - : mword 31) in + : mword (61 - 31 + 1)) in let b__0 := subrange_vec_dec vAddr 63 62 in let '(requiredLevel, addr) := - (if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then + (if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword (63 - 62 + 1)))) then match (compat32, subrange_vec_dec vAddr 30 29) with | (true, b__1) => - if ((eq_vec b__1 (vec_of_bits [B1;B1] : mword 2))) then - (Kernel, None : option (bits 64)) - else if ((eq_vec b__1 (vec_of_bits [B1;B0] : mword 2))) then - (Supervisor, None : option (bits 64)) - else if ((eq_vec b__1 (vec_of_bits [B0;B1] : mword 2))) then - (Kernel, - Some (concat_vec - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) (subrange_vec_dec vAddr 28 0)))) - else if ((eq_vec b__1 (vec_of_bits [B0;B0] : mword 2))) then - (Kernel, - Some (concat_vec - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) (subrange_vec_dec vAddr 28 0)))) - else match (true, b__1) with | (g__25, g__26) => (Kernel, None : option (bits 64)) end - | (g__25, g__26) => (Kernel, None : option (bits 64)) + if ((eq_vec b__1 (vec_of_bits [B1;B1] : mword (30 - 29 + 1)))) then + (Kernel, None + : option (bits 64)) + else if ((eq_vec b__1 (vec_of_bits [B1;B0] : mword (30 - 29 + 1)))) then + (Supervisor, None + : option (bits 64)) + else if ((eq_vec b__1 (vec_of_bits [B0;B1] : mword (30 - 29 + 1)))) then + (Kernel, Some + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (subrange_vec_dec vAddr 28 0)))) + else if ((eq_vec b__1 (vec_of_bits [B0;B0] : mword (30 - 29 + 1)))) then + (Kernel, Some + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (subrange_vec_dec vAddr 28 0)))) + else match (true, b__1) with | (g__14, g__15) => (Kernel, None : option (bits 64)) end + | (g__14, g__15) => (Kernel, None : option (bits 64)) end - else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then - (Kernel, - Some (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) (subrange_vec_dec vAddr 58 0))) - else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then - (Supervisor, None : option (bits 64)) + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword (63 - 62 + 1)))) then + (Kernel, Some + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (subrange_vec_dec vAddr 58 0))) + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword (63 - 62 + 1)))) then + (Supervisor, None + : option (bits 64)) else (User, None : option (bits 64))) : (AccessLevel * option (bits 64)) in (if ((negb (grantsAccess currentAccessLevel requiredLevel))) then (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr) : M ((mword 64 * bool)) else - match addr with - | Some (a) => returnm ((a, false) : (mword 64 * bool)) - | None => - (if ((andb (negb compat32) (gtb_range_l (uint (subrange_vec_dec vAddr 61 0)) MAX_VA))) then - (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) - vAddr) - : M ((bits 64 * bool)) - else (TLBTranslate2 vAddr accessType) : M ((bits 64 * bool))) - : M ((mword 64 * bool)) - end >>= fun '(pa, c) => - (if ((gtb_range_l (uint pa) MAX_PA)) then + (match addr with + | Some (a) => returnm (a, false) + | None => + (if sumbool_of_bool ((andb (negb compat32) + (Z.gtb (projT1 (uint (subrange_vec_dec vAddr 61 0))) MAX_VA))) + then + (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) + vAddr) + : M ((mword 64 * bool)) + else (TLBTranslate2 vAddr accessType) : M ((mword 64 * bool))) + : M ((mword 64 * bool)) + end) >>= fun '(pa, c) => + (if sumbool_of_bool ((Z.gtb (projT1 (uint pa)) MAX_PA)) then (SignalExceptionBadAddr (if ((generic_eq accessType StoreData)) then AdES else AdEL) vAddr) : M ((mword 64 * bool)) - else returnm ((pa, c) : (mword 64 * bool))) + else returnm (pa, c)) : M ((mword 64 * bool))) : M ((mword 64 * bool)). Definition TLBTranslate (vAddr : mword 64) (accessType : MemAccessType) : M (mword 64) := - TLBTranslateC vAddr accessType >>= fun '(addr, c) => returnm (addr : mword 64). + + (TLBTranslateC vAddr accessType) >>= fun '(addr, c) => returnm (addr : mword 64). -Definition MEMw_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (1 <= - size /\ - size <= 8)} `{ArithFact (size = size)} +Definition MEMw_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) +`{ArithFact (1 <= size /\ size <= 8)} : M (unit) := - let ledata := autocast (reverse_endianness data) in + + let ledata := reverse_endianness data in (if ((eq_vec addr (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0; @@ -2155,70 +2489,57 @@ Definition MEMw_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) ` write_reg UART_WDATA_ref (subrange_vec_dec ledata 7 0) >> write_reg UART_WRITTEN_ref ((cast_unit_vec B1) : bits 1) : M (unit) - else MEMea addr size >> (MEMval addr size ledata) : M (unit)) + else (MEMea addr size) >> (MEMval addr size ledata) : M (unit)) : M (unit). -Definition MEMw_conditional_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) `{ArithFact (1 <= - size /\ - size <= 8)} `{ArithFact (size = size)} +Definition MEMw_conditional_wrapper (addr : mword 64) (size : Z) (data : mword (8 * size)) +`{ArithFact (1 <= size /\ size <= 8)} : M (bool) := - MEMea_conditional addr size >> - (MEMval_conditional addr size (autocast (reverse_endianness data))) + + (MEMea_conditional addr size) >> + (MEMval_conditional addr size (reverse_endianness data)) : M (bool). Definition addrWrapper (addr : mword 64) (accessType : MemAccessType) (width : WordType) : mword 64 := + addr. -Definition addrWrapperUnaligned (addr : mword 64) (accessType : MemAccessType) (width : WordTypeUnaligned) +Definition addrWrapperUnaligned +(addr : mword 64) (accessType : MemAccessType) (width : WordTypeUnaligned) : mword 64 := + addr. Definition TranslatePC (vAddr : mword 64) : M (mword 64) := - incrementCP0Count tt >> - (if ((neq_vec (subrange_vec_dec vAddr 1 0) (vec_of_bits [B0;B0] : mword 2))) then + + (incrementCP0Count tt) >> + (if ((neq_vec (subrange_vec_dec vAddr 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then (SignalExceptionBadAddr AdEL vAddr) : M (mword 64) else (TLBTranslate vAddr Instruction) : M (mword 64)) : M (mword 64). Definition have_cp2 := false. +Hint Unfold have_cp2 : sail. +Definition ERETHook '(tt : unit) : unit := tt. -Definition ERETHook '(tt : unit) : unit := tt. - -Definition init_cp2_state '(tt : unit) : M (unit) := (skip tt) : M (unit). +Definition init_cp2_state '(tt : unit) : M (unit) := (skip tt) >> (skip tt) : M (unit). -Definition cp2_next_pc '(tt : unit) : M (unit) := skip tt >> (skip tt) : M (unit). +Definition cp2_next_pc '(tt : unit) : M (unit) := (skip tt) >> (skip tt) : M (unit). -Definition dump_cp2_state '(tt : unit) : M (unit) := skip tt >> (skip tt) : M (unit). +Definition dump_cp2_state '(tt : unit) : M (unit) := (skip tt) >> (skip tt) : M (unit). -Definition undefined_ast '(tt : unit) -: M (ast) := - undefined_Comparison tt >>= fun u_0 => - undefined_WordType tt >>= fun u_1 => - undefined_bool tt >>= fun u_3 => - undefined_bool tt >>= fun u_2 => - undefined_bitvector 16 >>= fun u_4 => - undefined_bitvector 5 >>= fun u_7 => - undefined_bitvector 5 >>= fun u_6 => - undefined_bitvector 5 >>= fun u_5 => - undefined_unit tt >>= fun u_8 => - undefined_bitvector 3 >>= fun u_9 => - undefined_bitvector 16 >>= fun u_10 => - undefined_bitvector 26 >>= fun u_11 => - (internal_pick - [DADDIU (u_6,u_5,u_4);DADDU (u_7,u_6,u_5);DADDI (u_6,u_5,u_10);DADD (u_7,u_6,u_5);ADD (u_7,u_6,u_5);ADDI (u_6,u_5,u_10);ADDU (u_7,u_6,u_5);ADDIU (u_6,u_5,u_10);DSUBU (u_7,u_6,u_5);DSUB (u_7,u_6,u_5);SUB (u_7,u_6,u_5);SUBU (u_7,u_6,u_5);AND (u_7,u_6,u_5);ANDI (u_6,u_5,u_10);OR (u_7,u_6,u_5);ORI (u_6,u_5,u_10);NOR (u_7,u_6,u_5);XOR (u_7,u_6,u_5);XORI (u_6,u_5,u_10);LUI (u_5,u_4);DSLL (u_7,u_6,u_5);DSLL32 (u_7,u_6,u_5);DSLLV (u_7,u_6,u_5);DSRA (u_7,u_6,u_5);DSRA32 (u_7,u_6,u_5);DSRAV (u_7,u_6,u_5);DSRL (u_7,u_6,u_5);DSRL32 (u_7,u_6,u_5);DSRLV (u_7,u_6,u_5);SLL (u_7,u_6,u_5);SLLV (u_7,u_6,u_5);SRA (u_7,u_6,u_5);SRAV (u_7,u_6,u_5);SRL (u_7,u_6,u_5);SRLV (u_7,u_6,u_5);SLT (u_7,u_6,u_5);SLTI (u_6,u_5,u_10);SLTU (u_7,u_6,u_5);SLTIU (u_6,u_5,u_10);MOVN (u_7,u_6,u_5);MOVZ (u_7,u_6,u_5);MFHI u_5;MFLO u_5;MTHI u_5;MTLO u_5;MUL (u_7,u_6,u_5);MULT (u_6,u_5);MULTU (u_6,u_5);DMULT (u_6,u_5);DMULTU (u_6,u_5);MADD (u_6,u_5);MADDU (u_6,u_5);MSUB (u_6,u_5);MSUBU (u_6,u_5);DIV (u_6,u_5);DIVU (u_6,u_5);DDIV (u_6,u_5);DDIVU (u_6,u_5);J u_11;JAL u_11;JR u_5;JALR (u_6,u_5);BEQ (u_6,u_5,u_4,u_3,u_2);BCMPZ (u_5,u_4,u_0,u_3,u_2);SYSCALL u_8;BREAK u_8;WAIT u_8;TRAPREG (u_6,u_5,u_0);TRAPIMM (u_5,u_4,u_0);Load (u_1,u_3,u_2,u_6,u_5,u_4);Store (u_1,u_2,u_6,u_5,u_4);LWL (u_6,u_5,u_10);LWR (u_6,u_5,u_10);SWL (u_6,u_5,u_10);SWR (u_6,u_5,u_10);LDL (u_6,u_5,u_10);LDR (u_6,u_5,u_10);SDL (u_6,u_5,u_10);SDR (u_6,u_5,u_10);CACHE (u_6,u_5,u_10);SYNC u_8;MFC0 (u_6,u_5,u_9,u_2);HCF u_8;MTC0 (u_6,u_5,u_9,u_2);TLBWI u_8;TLBWR u_8;TLBR u_8;TLBP u_8;RDHWR (u_6,u_5);ERET u_8;RI u_8]) - : M (ast). - -Definition extendLoad {sz : Z} (memResult : mword sz) (sign : bool) `{ArithFact (sz <= 64)} -: mword 64 := - if (sign) then mips_sign_extend 64 memResult - else mips_zero_extend 64 memResult. +Definition execute_branch (pc : mword 64) +: M (unit) := + + (skip tt) >> (skip tt) >> (execute_branch_mips pc) : M (unit). Definition TLBWriteEntry (idx : mword 6) : M (unit) := - (read_reg TLBPageMask_ref : M (mword 16)) >>= fun pagemask => + + ((read_reg TLBPageMask_ref) : M (mword 16)) >>= fun pagemask => let b__0 := pagemask in (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16))) then @@ -2257,988 +2578,1330 @@ Definition TLBWriteEntry (idx : mword 6) returnm (tt : unit) else (SignalException MCheck) : M (unit)) >> - let '(existT _ i _) := uint idx in + let 'i := projT1 (uint idx) in let entry := vec_access_dec TLBEntries i in - _set_TLBEntry_pagemask entry pagemask >> - read_reg TLBEntryHi_ref >>= fun w__0 => - _set_TLBEntry_r entry (_get_TLBEntryHiReg_R w__0) >> - read_reg TLBEntryHi_ref >>= fun w__1 => - _set_TLBEntry_vpn2 entry (_get_TLBEntryHiReg_VPN2 w__1) >> - read_reg TLBEntryHi_ref >>= fun w__2 => - _set_TLBEntry_asid entry (_get_TLBEntryHiReg_ASID w__2) >> - and_boolM - (read_reg TLBEntryLo0_ref >>= fun w__3 => - returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__3)) - : bool)) - (read_reg TLBEntryLo1_ref >>= fun w__4 => - returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__4)) - : bool)) >>= fun w__5 => - _set_TLBEntry_g entry ((bool_to_bits w__5) : mword 1) >> - _set_TLBEntry_valid entry ((cast_unit_vec B1) : mword 1) >> - read_reg TLBEntryLo0_ref >>= fun w__6 => - _set_TLBEntry_caps0 entry (_get_TLBEntryLoReg_CapS w__6) >> - read_reg TLBEntryLo0_ref >>= fun w__7 => - _set_TLBEntry_capl0 entry (_get_TLBEntryLoReg_CapL w__7) >> - read_reg TLBEntryLo0_ref >>= fun w__8 => - _set_TLBEntry_pfn0 entry (_get_TLBEntryLoReg_PFN w__8) >> - read_reg TLBEntryLo0_ref >>= fun w__9 => - _set_TLBEntry_c0 entry (_get_TLBEntryLoReg_C w__9) >> - read_reg TLBEntryLo0_ref >>= fun w__10 => - _set_TLBEntry_d0 entry (_get_TLBEntryLoReg_D w__10) >> - read_reg TLBEntryLo0_ref >>= fun w__11 => - _set_TLBEntry_v0 entry (_get_TLBEntryLoReg_V w__11) >> - read_reg TLBEntryLo1_ref >>= fun w__12 => - _set_TLBEntry_caps1 entry (_get_TLBEntryLoReg_CapS w__12) >> - read_reg TLBEntryLo1_ref >>= fun w__13 => - _set_TLBEntry_capl1 entry (_get_TLBEntryLoReg_CapL w__13) >> - read_reg TLBEntryLo1_ref >>= fun w__14 => - _set_TLBEntry_pfn1 entry (_get_TLBEntryLoReg_PFN w__14) >> - read_reg TLBEntryLo1_ref >>= fun w__15 => - _set_TLBEntry_c1 entry (_get_TLBEntryLoReg_C w__15) >> - read_reg TLBEntryLo1_ref >>= fun w__16 => - _set_TLBEntry_d1 entry (_get_TLBEntryLoReg_D w__16) >> - read_reg TLBEntryLo1_ref >>= fun w__17 => + (_set_TLBEntry_pagemask entry pagemask) >> + read_reg TLBEntryHi_ref >>= fun w__0 : TLBEntryHiReg => + (_set_TLBEntry_r entry (_get_TLBEntryHiReg_R w__0)) >> + read_reg TLBEntryHi_ref >>= fun w__1 : TLBEntryHiReg => + (_set_TLBEntry_vpn2 entry (_get_TLBEntryHiReg_VPN2 w__1)) >> + read_reg TLBEntryHi_ref >>= fun w__2 : TLBEntryHiReg => + (_set_TLBEntry_asid entry (_get_TLBEntryHiReg_ASID w__2)) >> + (and_boolM + (read_reg TLBEntryLo0_ref >>= fun w__3 : TLBEntryLoReg => + returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__3)) + : bool)) + (read_reg TLBEntryLo1_ref >>= fun w__4 : TLBEntryLoReg => + returnm ((bits_to_bool (_get_TLBEntryLoReg_G w__4)) + : bool))) >>= fun w__5 : bool => + (_set_TLBEntry_g entry ((bool_to_bits w__5) : mword 1)) >> + (_set_TLBEntry_valid entry ((cast_unit_vec B1) : mword 1)) >> + read_reg TLBEntryLo0_ref >>= fun w__6 : TLBEntryLoReg => + (_set_TLBEntry_caps0 entry (_get_TLBEntryLoReg_CapS w__6)) >> + read_reg TLBEntryLo0_ref >>= fun w__7 : TLBEntryLoReg => + (_set_TLBEntry_capl0 entry (_get_TLBEntryLoReg_CapL w__7)) >> + read_reg TLBEntryLo0_ref >>= fun w__8 : TLBEntryLoReg => + (_set_TLBEntry_pfn0 entry (_get_TLBEntryLoReg_PFN w__8)) >> + read_reg TLBEntryLo0_ref >>= fun w__9 : TLBEntryLoReg => + (_set_TLBEntry_c0 entry (_get_TLBEntryLoReg_C w__9)) >> + read_reg TLBEntryLo0_ref >>= fun w__10 : TLBEntryLoReg => + (_set_TLBEntry_d0 entry (_get_TLBEntryLoReg_D w__10)) >> + read_reg TLBEntryLo0_ref >>= fun w__11 : TLBEntryLoReg => + (_set_TLBEntry_v0 entry (_get_TLBEntryLoReg_V w__11)) >> + read_reg TLBEntryLo1_ref >>= fun w__12 : TLBEntryLoReg => + (_set_TLBEntry_caps1 entry (_get_TLBEntryLoReg_CapS w__12)) >> + read_reg TLBEntryLo1_ref >>= fun w__13 : TLBEntryLoReg => + (_set_TLBEntry_capl1 entry (_get_TLBEntryLoReg_CapL w__13)) >> + read_reg TLBEntryLo1_ref >>= fun w__14 : TLBEntryLoReg => + (_set_TLBEntry_pfn1 entry (_get_TLBEntryLoReg_PFN w__14)) >> + read_reg TLBEntryLo1_ref >>= fun w__15 : TLBEntryLoReg => + (_set_TLBEntry_c1 entry (_get_TLBEntryLoReg_C w__15)) >> + read_reg TLBEntryLo1_ref >>= fun w__16 : TLBEntryLoReg => + (_set_TLBEntry_d1 entry (_get_TLBEntryLoReg_D w__16)) >> + read_reg TLBEntryLo1_ref >>= fun w__17 : TLBEntryLoReg => (_set_TLBEntry_v1 entry (_get_TLBEntryLoReg_V w__17)) : M (unit). Definition decode (v__0 : mword 32) : option ast := - if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B0;B1] : mword 6))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + + if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B0;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (DADDIU (rs,rt,imm)) + Some + (DADDIU + ((rs, rt, imm))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DADDU (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B0;B0] : mword 6))) - then let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (DADDU + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (DADDI (rs,rt,imm)) + Some + (DADDI + ((rs, rt, imm))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DADD (rs,rt,rd)) + Some + (DADD + ((rs, rt, rd))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (ADD (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword 6))) - then let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (ADD + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (ADDI (rs,rt,imm)) + Some + (ADDI + ((rs, rt, imm))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (ADDU (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword 6))) - then let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (ADDU + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (ADDIU (rs,rt,imm)) + Some + (ADDIU + ((rs, rt, imm))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DSUBU (rs,rt,rd)) + Some + (DSUBU + ((rs, rt, rd))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DSUB (rs,rt,rd)) + Some + (DSUB + ((rs, rt, rd))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SUB (rs,rt,rd)) + Some + (SUB + ((rs, rt, rd))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SUBU (rs,rt,rd)) + Some + (SUBU + ((rs, rt, rd))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (AND (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword 6))) - then let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (AND + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (ANDI (rs,rt,imm)) + Some + (ANDI + ((rs, rt, imm))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (OR (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword 6))) - then let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (OR + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (ORI (rs,rt,imm)) + Some + (ORI + ((rs, rt, imm))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (NOR (rs,rt,rd)) + Some + (NOR + ((rs, rt, rd))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (XOR (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B1;B1;B0] : mword 6))) - then let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (XOR + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B1;B1;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (XORI (rs,rt,imm)) + Some + (XORI + ((rs, rt, imm))) else if ((eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword 11))) then + (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword (31 - 21 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (LUI (rt,imm)) + Some + (LUI + ((rt, imm))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B0;B0;B0] : mword 6)))) - then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B0;B0;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : bits 5 := subrange_vec_dec v__0 10 6 in - Some (DSLL (rt,rd,sa)) + Some + (DSLL + ((rt, rd, sa))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B1;B0;B0] : mword 6)))) - then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B1;B0;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : bits 5 := subrange_vec_dec v__0 10 6 in - Some (DSLL32 (rt,rd,sa)) + Some + (DSLL32 + ((rt, rd, sa))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DSLLV (rs,rt,rd)) + Some + (DSLLV + ((rs, rt, rd))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B0;B1;B1] : mword 6)))) - then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B0;B1;B1] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : bits 5 := subrange_vec_dec v__0 10 6 in - Some (DSRA (rt,rd,sa)) + Some + (DSRA + ((rt, rd, sa))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword 6)))) - then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : bits 5 := subrange_vec_dec v__0 10 6 in - Some (DSRA32 (rt,rd,sa)) + Some + (DSRA32 + ((rt, rd, sa))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DSRAV (rs,rt,rd)) + Some + (DSRAV + ((rs, rt, rd))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword 6)))) - then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B0;B1;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : bits 5 := subrange_vec_dec v__0 10 6 in - Some (DSRL (rt,rd,sa)) + Some + (DSRL + ((rt, rd, sa))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B1;B1;B1;B0] : mword 6)))) - then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B1;B1;B1;B0] : mword (5 - 0 + 1))))) then + let sa : bits 5 := subrange_vec_dec v__0 10 6 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : bits 5 := subrange_vec_dec v__0 10 6 in - Some (DSRL32 (rt,rd,sa)) + Some + (DSRL32 + ((rt, rd, sa))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (DSRLV (rs,rt,rd)) + Some + (DSRLV + ((rs, rt, rd))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)))) - then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then + let sa : regno := subrange_vec_dec v__0 10 6 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : regno := subrange_vec_dec v__0 10 6 in - Some (SLL (rt,rd,sa)) + Some + (SLL + ((rt, rd, sa))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SLLV (rs,rt,rd)) + Some + (SLLV + ((rs, rt, rd))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword 6)))) - then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then + let sa : regno := subrange_vec_dec v__0 10 6 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : regno := subrange_vec_dec v__0 10 6 in - Some (SRA (rt,rd,sa)) + Some + (SRA + ((rt, rd, sa))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SRAV (rs,rt,rd)) + Some + (SRAV + ((rs, rt, rd))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword 6)))) - then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let sa : regno := subrange_vec_dec v__0 10 6 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sa : regno := subrange_vec_dec v__0 10 6 in - Some (SRL (rt,rd,sa)) + Some + (SRL + ((rt, rd, sa))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SRLV (rs,rt,rd)) + Some + (SRLV + ((rs, rt, rd))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SLT (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B1;B0] : mword 6))) - then let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLT + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B1;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (SLTI (rs,rt,imm)) + Some + (SLTI + ((rs, rt, imm))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - let rd : regno := subrange_vec_dec v__0 15 11 in - Some (SLTU (rs,rt,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B1;B0;B1;B1] : mword 6))) - then let rs : regno := subrange_vec_dec v__0 25 21 in + let rd : regno := subrange_vec_dec v__0 15 11 in + Some + (SLTU + ((rs, rt, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B1;B0;B1;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (SLTIU (rs,rt,imm)) + Some + (SLTIU + ((rs, rt, imm))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (MOVN (rs,rt,rd)) + Some + (MOVN + ((rs, rt, rd))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (MOVZ (rs,rt,rd)) + Some + (MOVZ + ((rs, rt, rd))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 16) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 16 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0] : mword 11)))) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0] : mword (10 - 0 + 1))))) then let rd : regno := subrange_vec_dec v__0 15 11 in - Some (MFHI rd) + Some + (MFHI + (rd)) else if ((andb (eq_vec (subrange_vec_dec v__0 31 16) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (31 - 16 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0] : mword 11)))) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then let rd : regno := subrange_vec_dec v__0 15 11 in - Some (MFLO rd) + Some + (MFLO + (rd)) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 20 0) (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1] - : mword 21)))) then + : mword (20 - 0 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in - Some (MTHI rs) + Some + (MTHI + (rs)) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 20 0) (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1] - : mword 21)))) then + : mword (20 - 0 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in - Some (MTLO rs) + Some + (MTLO + (rs)) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 11)))) then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (MUL (rs,rt,rd)) + Some + (MUL + ((rs, rt, rd))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] + : mword (15 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (MULT (rs,rt)) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MULT + ((rs, rt))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1] + : mword (15 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (MULTU (rs,rt)) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MULTU + ((rs, rt))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0] + : mword (15 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (DMULT (rs,rt)) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DMULT + ((rs, rt))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1] + : mword (15 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (DMULTU (rs,rt)) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DMULTU + ((rs, rt))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (15 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (MADD (rs,rt)) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MADD + ((rs, rt))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] + : mword (15 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (MADDU (rs,rt)) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MADDU + ((rs, rt))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] + : mword (15 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (MSUB (rs,rt)) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MSUB + ((rs, rt))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B1;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] + : mword (15 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (MSUBU (rs,rt)) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (MSUBU + ((rs, rt))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0] + : mword (15 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (DIV (rs,rt)) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DIV + ((rs, rt))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1] + : mword (15 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (DIVU (rs,rt)) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DIVU + ((rs, rt))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0] + : mword (15 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (DDIV (rs,rt)) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DDIV + ((rs, rt))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 16)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] + : mword (15 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (DDIVU (rs,rt)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword 6))) - then + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (DDIVU + ((rs, rt))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B1;B0] : mword (31 - 26 + 1)))) then let offset : bits 26 := subrange_vec_dec v__0 25 0 in - Some (J offset) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword 6))) - then + Some + (J + (offset)) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B1;B1] : mword (31 - 26 + 1)))) then let offset : bits 26 := subrange_vec_dec v__0 25 0 in - Some (JAL offset) + Some + (JAL + (offset)) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (andb (eq_vec (subrange_vec_dec v__0 20 11) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 10)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword 6))))) - then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (20 - 11 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B0;B0] : mword (5 - 0 + 1)))))) then let rs : regno := subrange_vec_dec v__0 25 21 in - Some (JR rs) + Some + (JR + (rs)) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) (andb - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword 6))))) - then + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1] : mword (5 - 0 + 1)))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (JALR (rs,rd)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B0;B0] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (JALR + ((rs, rd))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in - let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BEQ (rs,rt,imm,false,false)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B0;B0] : mword 6))) - then let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BEQ (rs,rt,imm,false,true)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B0;B1] : mword 6))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (BEQ + ((rs, rt, imm, false, false))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BEQ (rs,rt,imm,true,false)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B0;B1] : mword 6))) - then + Some + (BEQ + ((rs, rt, imm, false, true))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B0;B1] : mword (31 - 26 + 1)))) then + let rt : regno := subrange_vec_dec v__0 20 16 in let rs : regno := subrange_vec_dec v__0 25 21 in + let imm : imm16 := subrange_vec_dec v__0 15 0 in + Some + (BEQ + ((rs, rt, imm, true, false))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B0;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in + let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BEQ (rs,rt,imm,true,true)) + Some + (BEQ + ((rs, rt, imm, true, true))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,LT',false,false)) + Some + (BCMPZ + ((rs, imm, LT', false, false))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,LT',true,false)) + Some + (BCMPZ + ((rs, imm, LT', true, false))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B1;B0] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,LT',false,true)) + Some + (BCMPZ + ((rs, imm, LT', false, true))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B1;B0] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B1;B0] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,LT',true,true)) + Some + (BCMPZ + ((rs, imm, LT', true, true))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B1] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,GE,false,false)) + Some + (BCMPZ + ((rs, imm, GE, false, false))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B0;B1] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B0;B1] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,GE,true,false)) + Some + (BCMPZ + ((rs, imm, GE, true, false))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B1;B1] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,GE,false,true)) + Some + (BCMPZ + ((rs, imm, GE, false, true))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B1;B0;B0;B1;B1] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B1;B0;B0;B1;B1] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,GE,true,true)) + Some + (BCMPZ + ((rs, imm, GE, true, true))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B1;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B1;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,GT',false,false)) + Some + (BCMPZ + ((rs, imm, GT', false, false))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B1;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B1;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,GT',false,true)) + Some + (BCMPZ + ((rs, imm, GT', false, true))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B1;B1;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B1;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,LE,false,false)) + Some + (BCMPZ + ((rs, imm, LE, false, false))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B0;B1;B1;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B0;B1;B1;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B0;B0;B0;B0] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (BCMPZ (rs,imm,LE,false,true)) + Some + (BCMPZ + ((rs, imm, LE, false, true))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword 6)))) - then - Some (SYSCALL tt) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B0;B0] : mword (5 - 0 + 1))))) then + Some + (SYSCALL + (tt)) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword 6)))) - then - Some (BREAK tt) + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1] : mword (5 - 0 + 1))))) then + Some + (BREAK + (tt)) else if ((eq_vec v__0 (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0] : mword 32))) then - Some (WAIT tt) + Some + (WAIT + (tt)) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B0;B0] : mword 6)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B0;B0] : mword (5 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (TRAPREG (rs,rt,GE)) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B0;B1] : mword 6)))) - then let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (TRAPREG (rs,rt,GEU)) + Some + (TRAPREG + ((rs, rt, GE))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword 6)))) - then - let rs : regno := subrange_vec_dec v__0 25 21 in + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B0;B1] : mword (5 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (TRAPREG (rs,rt,LT')) - else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B0;B1;B1] : mword 6)))) - then let rs : regno := subrange_vec_dec v__0 25 21 in - let rt : regno := subrange_vec_dec v__0 20 16 in - Some (TRAPREG (rs,rt,LTU)) + Some + (TRAPREG + ((rs, rt, GEU))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B1;B0;B0] : mword 6)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B1;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, LT'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B0;B1;B1] : mword (5 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (TRAPREG (rs,rt,EQ')) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, LTU))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B1;B1;B0;B1;B1;B0] : mword 6)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B1;B0;B0] : mword (5 - 0 + 1))))) then + let rt : regno := subrange_vec_dec v__0 20 16 in let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, EQ'))) + else if ((andb + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B1;B1;B0;B1;B1;B0] : mword (5 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in - Some (TRAPREG (rs,rt,NE)) + let rs : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPREG + ((rs, rt, NE))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B1;B0;B0] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (TRAPIMM (rs,imm,EQ')) + Some + (TRAPIMM + ((rs, imm, EQ'))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B1;B1;B0] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (TRAPIMM (rs,imm,NE)) + Some + (TRAPIMM + ((rs, imm, NE))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B0;B0] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (TRAPIMM (rs,imm,GE)) + Some + (TRAPIMM + ((rs, imm, GE))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B0;B1] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (TRAPIMM (rs,imm,GEU)) + Some + (TRAPIMM + ((rs, imm, GEU))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B1;B0] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (TRAPIMM (rs,imm,LT')) + Some + (TRAPIMM + ((rs, imm, LT'))) else if ((andb - (eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword 6)) - (eq_vec (subrange_vec_dec v__0 20 16) (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)))) - then + (eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B1] : mword (31 - 26 + 1))) + (eq_vec (subrange_vec_dec v__0 20 16) + (vec_of_bits [B0;B1;B0;B1;B1] : mword (20 - 16 + 1))))) then let rs : regno := subrange_vec_dec v__0 25 21 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (TRAPIMM (rs,imm,LTU)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B0;B0] : mword 6))) - then - let base : regno := subrange_vec_dec v__0 25 21 in + Some + (TRAPIMM + ((rs, imm, LTU))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (B,true,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B0;B0] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((B, true, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (B,false,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B0;B1] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((B, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B0;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (H,true,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B0;B1] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((H, true, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B0;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (H,false,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((H, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (W,true,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((W, true, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (W,false,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B0;B1;B1;B1] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((W, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B1;B1;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (D,false,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B0;B0;B0;B0] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((D, false, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B0;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (W,true,true,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B0;B1;B0;B0] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((W, true, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B0;B1;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Load (D,false,true,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B0;B0] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Load + ((D, false, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Store (B,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B0;B1] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((B, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B0;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Store (H,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B1;B1] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((H, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B1;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Store (W,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((W, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B1;B1;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Store (D,false,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B1;B0;B0;B0] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((D, false, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B0;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Store (W,true,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B1;B1;B1;B0;B0] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((W, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B1;B1;B1;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (Store (D,true,base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B0;B1;B0] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (Store + ((D, true, base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B0;B1;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (LWL (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B0;B1;B1;B0] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LWL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B0;B1;B1;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (LWR (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B0;B1;B0] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LWR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B0;B1;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (SWL (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B1;B0] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SWL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B1;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (SWR (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B1;B0] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SWR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B1;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (LDL (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B0;B1;B1;B0;B1;B1] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LDL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B0;B1;B1;B0;B1;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (LDR (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B0;B0] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (LDR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B0;B0] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (SDL (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B0;B1] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SDL + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B0;B1] : mword (31 - 26 + 1)))) then let rt : regno := subrange_vec_dec v__0 20 16 in let offset : imm16 := subrange_vec_dec v__0 15 0 in - Some (SDR (base,rt,offset)) - else if ((eq_vec (subrange_vec_dec v__0 31 26) (vec_of_bits [B1;B0;B1;B1;B1;B1] : mword 6))) - then let base : regno := subrange_vec_dec v__0 25 21 in + Some + (SDR + ((base, rt, offset))) + else if ((eq_vec (subrange_vec_dec v__0 31 26) + (vec_of_bits [B1;B0;B1;B1;B1;B1] : mword (31 - 26 + 1)))) then let op : regno := subrange_vec_dec v__0 20 16 in let imm : imm16 := subrange_vec_dec v__0 15 0 in - Some (CACHE (base,op,imm)) + let base : regno := subrange_vec_dec v__0 25 21 in + Some + (CACHE + ((base, op, imm))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 11) (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 21)) - (eq_vec (subrange_vec_dec v__0 5 0) (vec_of_bits [B0;B0;B1;B1;B1;B1] : mword 6)))) - then - Some (SYNC tt) + : mword (31 - 11 + 1))) + (eq_vec (subrange_vec_dec v__0 5 0) + (vec_of_bits [B0;B0;B1;B1;B1;B1] : mword (5 - 0 + 1))))) then + Some + (SYNC + (tt)) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 11)) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) (eq_vec (subrange_vec_dec v__0 10 3) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)))) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sel : bits 3 := subrange_vec_dec v__0 2 0 in - Some (MFC0 (rt,rd,sel,false)) + Some + (MFC0 + ((rt, rd, sel, false))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 11)) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword (31 - 21 + 1))) (eq_vec (subrange_vec_dec v__0 10 3) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)))) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sel : bits 3 := subrange_vec_dec v__0 2 0 in - Some (MFC0 (rt,rd,sel,true)) + Some + (MFC0 + ((rt, rd, sel, true))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 11)) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)))) - then - Some (HCF tt) + (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (15 - 0 + 1))))) then + Some + (HCF + (tt)) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 11)) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) (eq_vec (subrange_vec_dec v__0 15 0) - (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)))) - then - Some (HCF tt) + (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword (15 - 0 + 1))))) then + Some + (HCF + (tt)) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 11)) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword (31 - 21 + 1))) (eq_vec (subrange_vec_dec v__0 10 3) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)))) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sel : bits 3 := subrange_vec_dec v__0 2 0 in - Some (MTC0 (rt,rd,sel,false)) + Some + (MTC0 + ((rt, rd, sel, false))) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 11)) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword (31 - 21 + 1))) (eq_vec (subrange_vec_dec v__0 10 3) - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8)))) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (10 - 3 + 1))))) then + let sel : bits 3 := subrange_vec_dec v__0 2 0 in let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - let sel : bits 3 := subrange_vec_dec v__0 2 0 in - Some (MTC0 (rt,rd,sel,true)) + Some + (MTC0 + ((rt, rd, sel, true))) else if ((eq_vec v__0 (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 32))) then - Some ((TLBWI tt) - : ast) + Some + ((TLBWI + (tt)) + : ast) else if ((eq_vec v__0 (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0] : mword 32))) then - Some ((TLBWR tt) - : ast) + Some + ((TLBWR + (tt)) + : ast) else if ((eq_vec v__0 (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 32))) then - Some ((TLBR tt) - : ast) + Some + ((TLBR + (tt)) + : ast) else if ((eq_vec v__0 (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0] : mword 32))) then - Some ((TLBP tt) - : ast) + Some + ((TLBP + (tt)) + : ast) else if ((andb (eq_vec (subrange_vec_dec v__0 31 21) - (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword 11)) + (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0] : mword (31 - 21 + 1))) (eq_vec (subrange_vec_dec v__0 10 0) - (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1] : mword 11)))) then + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1] : mword (10 - 0 + 1))))) then let rt : regno := subrange_vec_dec v__0 20 16 in let rd : regno := subrange_vec_dec v__0 15 11 in - Some (RDHWR (rt,rd)) + Some + (RDHWR + ((rt, rd))) else if ((eq_vec v__0 (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0] : mword 32))) then - Some (ERET tt) - else Some (RI tt). + Some + (ERET + (tt)) + else Some (RI (tt)). Definition execute_XORI (rs : mword 5) (rt : mword 5) (imm : mword 16) : M (unit) := - rGPR rs >>= fun w__0 => (wGPR rt (xor_vec w__0 (mips_zero_extend 64 imm))) : M (unit). + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (xor_vec w__0 (mips_zero_extend 64 imm))) + : M (unit). Definition execute_XOR (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (xor_vec w__0 w__1)) : M (unit). + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (xor_vec w__0 w__1)) : M (unit). -Definition execute_WAIT (g__16 : unit) +Definition execute_WAIT '(tt : unit) : M (unit) := - (read_reg PC_ref : M (mword 64)) >>= fun w__0 => write_reg nextPC_ref w__0 : M (unit). + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + write_reg NextPC_ref w__1 + : M (unit). Definition execute_TRAPREG (rs : mword 5) (rt : mword 5) (cmp : Comparison) : M (unit) := - rGPR rs >>= fun rs_val => - rGPR rt >>= fun rt_val => + + (rGPR rs) >>= fun rs_val => + (rGPR rt) >>= fun rt_val => let condition := compare cmp rs_val rt_val in (if (condition) then (SignalException Tr) : M (unit) else returnm (tt : unit)) @@ -3246,54 +3909,63 @@ Definition execute_TRAPREG (rs : mword 5) (rt : mword 5) (cmp : Comparison) Definition execute_TRAPIMM (rs : mword 5) (imm : mword 16) (cmp : Comparison) : M (unit) := - rGPR rs >>= fun rs_val => + + (rGPR rs) >>= fun rs_val => let imm_val : bits 64 := mips_sign_extend 64 imm in let condition := compare cmp rs_val imm_val in (if (condition) then (SignalException Tr) : M (unit) else returnm (tt : unit)) : M (unit). -Definition execute_TLBWR (g__20 : unit) +Definition execute_TLBWR '(tt : unit) : M (unit) := - checkCP0Access tt >> - (read_reg TLBRandom_ref : M (mword 6)) >>= fun w__0 => (TLBWriteEntry w__0) : M (unit). + + (checkCP0Access tt) >> + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + (TLBWriteEntry w__0) + : M (unit). -Definition execute_TLBWI (g__19 : unit) +Definition execute_TLBWI '(tt : unit) : M (unit) := - checkCP0Access tt >> - (read_reg TLBIndex_ref : M (mword 6)) >>= fun w__0 => (TLBWriteEntry w__0) : M (unit). + + (checkCP0Access tt) >> + ((read_reg TLBIndex_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + (TLBWriteEntry w__0) + : M (unit). -Definition execute_TLBR (g__21 : unit) +Definition execute_TLBR '(tt : unit) : M (unit) := - checkCP0Access tt >> - (read_reg TLBIndex_ref : M (mword 6)) >>= fun w__0 => - let '(existT _ i _) := uint w__0 in - reg_deref (vec_access_dec TLBEntries i) >>= fun entry => + + (checkCP0Access tt) >> + ((read_reg TLBIndex_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + let 'i := projT1 (uint w__0) in + (reg_deref (vec_access_dec TLBEntries i)) >>= fun entry => write_reg TLBPageMask_ref (_get_TLBEntry_pagemask entry) >> - _set_TLBEntryHiReg_R TLBEntryHi_ref (_get_TLBEntry_r entry) >> - _set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (_get_TLBEntry_vpn2 entry) >> - _set_TLBEntryHiReg_ASID TLBEntryHi_ref (_get_TLBEntry_asid entry) >> - _set_TLBEntryLoReg_CapS TLBEntryLo0_ref (_get_TLBEntry_caps0 entry) >> - _set_TLBEntryLoReg_CapL TLBEntryLo0_ref (_get_TLBEntry_capl0 entry) >> - _set_TLBEntryLoReg_PFN TLBEntryLo0_ref (_get_TLBEntry_pfn0 entry) >> - _set_TLBEntryLoReg_C TLBEntryLo0_ref (_get_TLBEntry_c0 entry) >> - _set_TLBEntryLoReg_D TLBEntryLo0_ref (_get_TLBEntry_d0 entry) >> - _set_TLBEntryLoReg_V TLBEntryLo0_ref (_get_TLBEntry_v0 entry) >> - _set_TLBEntryLoReg_G TLBEntryLo0_ref (_get_TLBEntry_g entry) >> - _set_TLBEntryLoReg_CapS TLBEntryLo1_ref (_get_TLBEntry_caps1 entry) >> - _set_TLBEntryLoReg_CapL TLBEntryLo1_ref (_get_TLBEntry_capl1 entry) >> - _set_TLBEntryLoReg_PFN TLBEntryLo1_ref (_get_TLBEntry_pfn1 entry) >> - _set_TLBEntryLoReg_C TLBEntryLo1_ref (_get_TLBEntry_c1 entry) >> - _set_TLBEntryLoReg_D TLBEntryLo1_ref (_get_TLBEntry_d1 entry) >> - _set_TLBEntryLoReg_V TLBEntryLo1_ref (_get_TLBEntry_v1 entry) >> + (_set_TLBEntryHiReg_R TLBEntryHi_ref (_get_TLBEntry_r entry)) >> + (_set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (_get_TLBEntry_vpn2 entry)) >> + (_set_TLBEntryHiReg_ASID TLBEntryHi_ref (_get_TLBEntry_asid entry)) >> + (_set_TLBEntryLoReg_CapS TLBEntryLo0_ref (_get_TLBEntry_caps0 entry)) >> + (_set_TLBEntryLoReg_CapL TLBEntryLo0_ref (_get_TLBEntry_capl0 entry)) >> + (_set_TLBEntryLoReg_PFN TLBEntryLo0_ref (_get_TLBEntry_pfn0 entry)) >> + (_set_TLBEntryLoReg_C TLBEntryLo0_ref (_get_TLBEntry_c0 entry)) >> + (_set_TLBEntryLoReg_D TLBEntryLo0_ref (_get_TLBEntry_d0 entry)) >> + (_set_TLBEntryLoReg_V TLBEntryLo0_ref (_get_TLBEntry_v0 entry)) >> + (_set_TLBEntryLoReg_G TLBEntryLo0_ref (_get_TLBEntry_g entry)) >> + (_set_TLBEntryLoReg_CapS TLBEntryLo1_ref (_get_TLBEntry_caps1 entry)) >> + (_set_TLBEntryLoReg_CapL TLBEntryLo1_ref (_get_TLBEntry_capl1 entry)) >> + (_set_TLBEntryLoReg_PFN TLBEntryLo1_ref (_get_TLBEntry_pfn1 entry)) >> + (_set_TLBEntryLoReg_C TLBEntryLo1_ref (_get_TLBEntry_c1 entry)) >> + (_set_TLBEntryLoReg_D TLBEntryLo1_ref (_get_TLBEntry_d1 entry)) >> + (_set_TLBEntryLoReg_V TLBEntryLo1_ref (_get_TLBEntry_v1 entry)) >> (_set_TLBEntryLoReg_G TLBEntryLo1_ref (_get_TLBEntry_g entry)) : M (unit). -Definition execute_TLBP (g__22 : unit) +Definition execute_TLBP '(tt : unit) : M (unit) := - checkCP0Access tt >> - read_reg TLBEntryHi_ref >>= fun w__0 => - tlbSearch (_get_TLBEntryHiReg_bits w__0) >>= fun result => + + (checkCP0Access tt) >> + read_reg TLBEntryHi_ref >>= fun w__0 : TLBEntryHiReg => + (tlbSearch (_get_TLBEntryHiReg_bits w__0)) >>= fun result => (match result with | Some (idx) => write_reg TLBProbe_ref (vec_of_bits [B0] : mword 1) >> @@ -3306,25 +3978,27 @@ Definition execute_TLBP (g__22 : unit) end) : M (unit). -Definition execute_Store (width : WordType) (conditional : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) +Definition execute_Store +(width : WordType) (conditional : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) : M (unit) := - rGPR base >>= fun w__0 => + + (rGPR base) >>= fun w__0 : mword 64 => let vAddr : bits 64 := addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) StoreData width in - rGPR rt >>= fun rt_val => + (rGPR rt) >>= fun rt_val => (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdES vAddr) : M (unit) else - TLBTranslate vAddr StoreData >>= fun pAddr => + (TLBTranslate vAddr StoreData) >>= fun pAddr => (if (conditional) then - (read_reg CP0LLBit_ref : M (mword 1)) >>= fun w__1 => + ((read_reg CP0LLBit_ref) : M (mword 1)) >>= fun w__1 : bits 1 => (if (((bit_to_bool (access_vec_dec w__1 0)) : bool)) then (match width with | W => (MEMw_conditional_wrapper pAddr 4 (subrange_vec_dec rt_val 31 0)) : M (bool) | D => (MEMw_conditional_wrapper pAddr 8 rt_val) : M (bool) - | _ => (throw (Error_internal_error tt)) : M (bool) + | _ => (throw (Error_internal_error (tt))) : M (bool) end) : M (bool) - else returnm (false : bool)) >>= fun success => - (wGPR rt (mips_zero_extend 64 ((bool_to_bits success) : mword 1))) + else returnm (false : bool)) >>= fun success : bool => + (wGPR rt (mips_zero_extend 64 (bool_to_bits success))) : M (unit) else (match width with @@ -3337,25 +4011,26 @@ Definition execute_Store (width : WordType) (conditional : bool) (base : mword 5 : M (unit)) : M (unit). -Definition execute_SYSCALL (g__14 : unit) : M (unit) := (SignalException Sys) : M (unit). +Definition execute_SYSCALL '(tt : unit) : M (unit) := (SignalException Sys) : M (unit). -Definition execute_SYNC (g__17 : unit) : M (unit) := (MEM_sync tt) : M (unit). +Definition execute_SYNC '(tt : unit) : M (unit) := (MEM_sync tt) : M (unit). Definition execute_SWR (base : mword 5) (rt : mword 5) (offset : mword 16) : M (unit) := - rGPR base >>= fun w__0 => + + (rGPR base) >>= fun w__0 : mword 64 => let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WR in - TLBTranslate vAddr StoreData >>= fun pAddr => + (TLBTranslate vAddr StoreData) >>= fun pAddr => let wordAddr := concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2) in - rGPR rt >>= fun reg_val => + (rGPR rt) >>= fun reg_val => let b__12 := subrange_vec_dec vAddr 1 0 in - (if ((eq_vec b__12 (vec_of_bits [B0;B0] : mword 2))) then + (if ((eq_vec b__12 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0)) : M (unit) - else if ((eq_vec b__12 (vec_of_bits [B0;B1] : mword 2))) then + else if ((eq_vec b__12 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0)) : M (unit) - else if ((eq_vec b__12 (vec_of_bits [B1;B0] : mword 2))) then + else if ((eq_vec b__12 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0)) : M (unit) else (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0)) : M (unit)) @@ -3363,18 +4038,19 @@ Definition execute_SWR (base : mword 5) (rt : mword 5) (offset : mword 16) Definition execute_SWL (base : mword 5) (rt : mword 5) (offset : mword 16) : M (unit) := - rGPR base >>= fun w__0 => + + (rGPR base) >>= fun w__0 : mword 64 => let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData WL in - TLBTranslate vAddr StoreData >>= fun pAddr => - rGPR rt >>= fun reg_val => + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (rGPR rt) >>= fun reg_val => let b__8 := subrange_vec_dec vAddr 1 0 in - (if ((eq_vec b__8 (vec_of_bits [B0;B0] : mword 2))) then + (if ((eq_vec b__8 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 31 0)) : M (unit) - else if ((eq_vec b__8 (vec_of_bits [B0;B1] : mword 2))) then + else if ((eq_vec b__8 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 31 8)) : M (unit) - else if ((eq_vec b__8 (vec_of_bits [B1;B0] : mword 2))) then + else if ((eq_vec b__8 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 31 16)) : M (unit) else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 31 24)) : M (unit)) @@ -3382,10 +4058,11 @@ Definition execute_SWL (base : mword 5) (rt : mword 5) (offset : mword 16) Definition execute_SUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun opA => - rGPR rt >>= fun opB => + + (rGPR rs) >>= fun opA => + (rGPR rt) >>= fun opB => (if ((orb (NotWordVal opA) (NotWordVal opB))) then - undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0) : M (unit) + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) else (wGPR rd (mips_sign_extend 64 (sub_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0)))) @@ -3394,10 +4071,11 @@ Definition execute_SUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) Definition execute_SUB (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun opA => - rGPR rt >>= fun opB => + + (rGPR rs) >>= fun opA => + (rGPR rt) >>= fun opB => (if ((orb (NotWordVal opA) (NotWordVal opB))) then - undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0) : M (unit) + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) else let temp33 : bits 33 := sub_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) @@ -3413,52 +4091,65 @@ Definition execute_SUB (rs : mword 5) (rt : mword 5) (rd : mword 5) Definition execute_SRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rt >>= fun temp => - rGPR rs >>= fun w__0 => + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => let sa := subrange_vec_dec w__0 4 0 in - (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__1 => (wGPR rd w__1) : M (unit) + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) else let rt32 := subrange_vec_dec temp 31 0 in - shift_bits_right rt32 sa >>= fun w__2 => (wGPR rd (mips_sign_extend 64 w__2)) : M (unit)) + (shift_bits_right rt32 sa) >>= fun w__2 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__2)) + : M (unit)) : M (unit). Definition execute_SRL (rt : mword 5) (rd : mword 5) (sa : mword 5) : M (unit) := - rGPR rt >>= fun temp => - (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0) : M (unit) + + (rGPR rt) >>= fun temp => + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) else let rt32 := subrange_vec_dec temp 31 0 in - shift_bits_right rt32 sa >>= fun w__1 => (wGPR rd (mips_sign_extend 64 w__1)) : M (unit)) + (shift_bits_right rt32 sa) >>= fun w__1 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__1)) + : M (unit)) : M (unit). Definition execute_SRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rt >>= fun temp => - rGPR rs >>= fun w__0 => + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => let sa := subrange_vec_dec w__0 4 0 in - (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__1 => (wGPR rd w__1) : M (unit) + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) else let rt32 := subrange_vec_dec temp 31 0 in - shift_bits_right_arith rt32 sa >>= fun w__2 => + (shift_bits_right_arith rt32 sa) >>= fun w__2 : mword (31 - 0 + 1) => (wGPR rd (mips_sign_extend 64 w__2)) : M (unit)) : M (unit). Definition execute_SRA (rt : mword 5) (rd : mword 5) (sa : mword 5) : M (unit) := - rGPR rt >>= fun temp => - (if ((NotWordVal temp)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0) : M (unit) + + (rGPR rt) >>= fun temp => + (if ((NotWordVal temp)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) else let rt32 := subrange_vec_dec temp 31 0 in - shift_bits_right_arith rt32 sa >>= fun w__1 => + (shift_bits_right_arith rt32 sa) >>= fun w__1 : mword (31 - 0 + 1) => (wGPR rd (mips_sign_extend 64 w__1)) : M (unit)) : M (unit). Definition execute_SLTU (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun rs_val => - rGPR rt >>= fun rt_val => + + (rGPR rs) >>= fun rs_val => + (rGPR rt) >>= fun rt_val => (wGPR rd (mips_zero_extend 64 (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] : mword 1) @@ -3467,7 +4158,8 @@ Definition execute_SLTU (rs : mword 5) (rt : mword 5) (rd : mword 5) Definition execute_SLTIU (rs : mword 5) (rt : mword 5) (imm : mword 16) : M (unit) := - rGPR rs >>= fun rs_val => + + (rGPR rs) >>= fun rs_val => let immext : bits 64 := mips_sign_extend 64 imm in (wGPR rt (mips_zero_extend 64 @@ -3477,9 +4169,10 @@ Definition execute_SLTIU (rs : mword 5) (rt : mword 5) (imm : mword 16) Definition execute_SLTI (rs : mword 5) (rt : mword 5) (imm : mword 16) : M (unit) := - let '(existT _ imm_val _) := sint imm in - rGPR rs >>= fun w__0 => - let '(existT _ rs_val _) := sint w__0 in + + let 'imm_val := projT1 (sint imm) in + (rGPR rs) >>= fun w__0 : mword 64 => + let 'rs_val := projT1 (sint w__0) in (wGPR rt (mips_zero_extend 64 (if sumbool_of_bool ((Z.ltb rs_val imm_val)) then (vec_of_bits [B1] : mword 1) @@ -3488,8 +4181,9 @@ Definition execute_SLTI (rs : mword 5) (rt : mword 5) (imm : mword 16) Definition execute_SLT (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => - rGPR rt >>= fun w__1 => + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (mips_zero_extend 64 (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] : mword 1) @@ -3498,45 +4192,52 @@ Definition execute_SLT (rs : mword 5) (rt : mword 5) (rd : mword 5) Definition execute_SLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => + + (rGPR rs) >>= fun w__0 : mword 64 => let sa := subrange_vec_dec w__0 4 0 in - rGPR rt >>= fun w__1 => + (rGPR rt) >>= fun w__1 : mword 64 => let rt32 := subrange_vec_dec w__1 31 0 in - shift_bits_left rt32 sa >>= fun w__2 => (wGPR rd (mips_sign_extend 64 w__2)) : M (unit). + (shift_bits_left rt32 sa) >>= fun w__2 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__2)) + : M (unit). Definition execute_SLL (rt : mword 5) (rd : mword 5) (sa : mword 5) : M (unit) := - rGPR rt >>= fun w__0 => + + (rGPR rt) >>= fun w__0 : mword 64 => let rt32 := subrange_vec_dec w__0 31 0 in - shift_bits_left rt32 sa >>= fun w__1 => (wGPR rd (mips_sign_extend 64 w__1)) : M (unit). + (shift_bits_left rt32 sa) >>= fun w__1 : mword (31 - 0 + 1) => + (wGPR rd (mips_sign_extend 64 w__1)) + : M (unit). Definition execute_SDR (base : mword 5) (rt : mword 5) (offset : mword 16) : M (unit) := - rGPR base >>= fun w__0 => + + (rGPR base) >>= fun w__0 : mword 64 => let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DR in - TLBTranslate vAddr StoreData >>= fun pAddr => - rGPR rt >>= fun reg_val => + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (rGPR rt) >>= fun reg_val => let wordAddr := concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3) in let b__40 := subrange_vec_dec vAddr 2 0 in - (if ((eq_vec b__40 (vec_of_bits [B0;B0;B0] : mword 3))) then + (if ((eq_vec b__40 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then (MEMw_wrapper wordAddr 1 (subrange_vec_dec reg_val 7 0)) : M (unit) - else if ((eq_vec b__40 (vec_of_bits [B0;B0;B1] : mword 3))) then + else if ((eq_vec b__40 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then (MEMw_wrapper wordAddr 2 (subrange_vec_dec reg_val 15 0)) : M (unit) - else if ((eq_vec b__40 (vec_of_bits [B0;B1;B0] : mword 3))) then + else if ((eq_vec b__40 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then (MEMw_wrapper wordAddr 3 (subrange_vec_dec reg_val 23 0)) : M (unit) - else if ((eq_vec b__40 (vec_of_bits [B0;B1;B1] : mword 3))) then + else if ((eq_vec b__40 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then (MEMw_wrapper wordAddr 4 (subrange_vec_dec reg_val 31 0)) : M (unit) - else if ((eq_vec b__40 (vec_of_bits [B1;B0;B0] : mword 3))) then + else if ((eq_vec b__40 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then (MEMw_wrapper wordAddr 5 (subrange_vec_dec reg_val 39 0)) : M (unit) - else if ((eq_vec b__40 (vec_of_bits [B1;B0;B1] : mword 3))) then + else if ((eq_vec b__40 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then (MEMw_wrapper wordAddr 6 (subrange_vec_dec reg_val 47 0)) : M (unit) - else if ((eq_vec b__40 (vec_of_bits [B1;B1;B0] : mword 3))) then + else if ((eq_vec b__40 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then (MEMw_wrapper wordAddr 7 (subrange_vec_dec reg_val 55 0)) : M (unit) else (MEMw_wrapper wordAddr 8 (subrange_vec_dec reg_val 63 0)) : M (unit)) @@ -3544,164 +4245,180 @@ Definition execute_SDR (base : mword 5) (rt : mword 5) (offset : mword 16) Definition execute_SDL (base : mword 5) (rt : mword 5) (offset : mword 16) : M (unit) := - rGPR base >>= fun w__0 => + + (rGPR base) >>= fun w__0 : mword 64 => let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) StoreData DL in - TLBTranslate vAddr StoreData >>= fun pAddr => - rGPR rt >>= fun reg_val => + (TLBTranslate vAddr StoreData) >>= fun pAddr => + (rGPR rt) >>= fun reg_val => let b__32 := subrange_vec_dec vAddr 2 0 in - (if ((eq_vec b__32 (vec_of_bits [B0;B0;B0] : mword 3))) then + (if ((eq_vec b__32 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then (MEMw_wrapper pAddr 8 (subrange_vec_dec reg_val 63 0)) : M (unit) - else if ((eq_vec b__32 (vec_of_bits [B0;B0;B1] : mword 3))) then + else if ((eq_vec b__32 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then (MEMw_wrapper pAddr 7 (subrange_vec_dec reg_val 63 8)) : M (unit) - else if ((eq_vec b__32 (vec_of_bits [B0;B1;B0] : mword 3))) then + else if ((eq_vec b__32 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then (MEMw_wrapper pAddr 6 (subrange_vec_dec reg_val 63 16)) : M (unit) - else if ((eq_vec b__32 (vec_of_bits [B0;B1;B1] : mword 3))) then + else if ((eq_vec b__32 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then (MEMw_wrapper pAddr 5 (subrange_vec_dec reg_val 63 24)) : M (unit) - else if ((eq_vec b__32 (vec_of_bits [B1;B0;B0] : mword 3))) then + else if ((eq_vec b__32 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then (MEMw_wrapper pAddr 4 (subrange_vec_dec reg_val 63 32)) : M (unit) - else if ((eq_vec b__32 (vec_of_bits [B1;B0;B1] : mword 3))) then + else if ((eq_vec b__32 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then (MEMw_wrapper pAddr 3 (subrange_vec_dec reg_val 63 40)) : M (unit) - else if ((eq_vec b__32 (vec_of_bits [B1;B1;B0] : mword 3))) then + else if ((eq_vec b__32 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then (MEMw_wrapper pAddr 2 (subrange_vec_dec reg_val 63 48)) : M (unit) else (MEMw_wrapper pAddr 1 (subrange_vec_dec reg_val 63 56)) : M (unit)) : M (unit). -Definition execute_RI (g__24 : unit) : M (unit) := (SignalException ResI) : M (unit). +Definition execute_RI '(tt : unit) : M (unit) := (skip tt) >> (SignalException ResI) : M (unit). Definition execute_RDHWR (rt : mword 5) (rd : mword 5) : M (unit) := - getAccessLevel tt >>= fun accessLevel => + + (getAccessLevel tt) >>= fun accessLevel => let haveAccessLevel : bool := generic_eq accessLevel Kernel in - read_reg CP0Status_ref >>= fun w__0 => + read_reg CP0Status_ref >>= fun w__0 : StatusReg => let haveCU0 : bool := eq_bit B1 (access_vec_dec (_get_StatusReg_CU w__0) 0) in - let '(existT _ rdi _) := uint rd in - (read_reg CP0HWREna_ref : M (mword 32)) >>= fun w__1 => + let 'rdi := projT1 (uint rd) in + ((read_reg CP0HWREna_ref) : M (mword 32)) >>= fun w__1 : bits 32 => let haveHWREna : bool := eq_bit B1 (access_vec_dec w__1 rdi) in (if ((negb (orb haveAccessLevel (orb haveCU0 haveHWREna)))) then (SignalException ResI) : M (unit) else returnm (tt : unit)) >> - let b__146 := rd in - (if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then + let b__150 := rd in + (if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))) then returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))) then returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))) then - (read_reg CP0Count_ref : M (mword 32)) >>= fun w__2 => + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))) then + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__2 : bits 32 => returnm ((mips_zero_extend 64 w__2) - : bits 64) - else if ((eq_vec b__146 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))) then + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))) then returnm ((mips_zero_extend 64 (vec_of_bits [B1] : mword 1)) - : bits 64) - else if ((eq_vec b__146 (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))) then - (read_reg CP0UserLocal_ref : M (mword 64)) + : mword 64) + else if ((eq_vec b__150 (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))) then + ((read_reg CP0UserLocal_ref) : M (mword 64)) : M (bits 64) - else (SignalException ResI) : M (bits 64)) >>= fun temp => + else (SignalException ResI) : M (mword 64)) >>= fun temp : bits 64 => (wGPR rt temp) : M (unit). Definition execute_ORI (rs : mword 5) (rt : mword 5) (imm : mword 16) : M (unit) := - rGPR rs >>= fun w__0 => (wGPR rt (or_vec w__0 (mips_zero_extend 64 imm))) : M (unit). + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (or_vec w__0 (mips_zero_extend 64 imm))) + : M (unit). Definition execute_OR (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (or_vec w__0 w__1)) : M (unit). + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (or_vec w__0 w__1)) : M (unit). Definition execute_NOR (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => - rGPR rt >>= fun w__1 => (wGPR rd (not_vec (or_vec w__0 w__1))) : M (unit). + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (not_vec (or_vec w__0 w__1))) : M (unit). Definition execute_MULTU (rs : mword 5) (rt : mword 5) : M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (bits 64) - else returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) : bits 64)) >>= fun result => + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun result : bits 64 => write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) : M (unit). Definition execute_MULT (rs : mword 5) (rt : mword 5) : M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (bits 64) + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) else returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) - : bits 64)) >>= fun result => + : mword (2 * 32))) >>= fun result : bits 64 => write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) : M (unit). Definition execute_MUL (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => let result : bits 64 := mips_sign_extend 64 (mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) in (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) - else returnm ((mips_sign_extend 64 (subrange_vec_dec result 31 0)) : mword 64)) >>= fun w__1 => + else returnm ((mips_sign_extend 64 (subrange_vec_dec result 31 0)) : mword 64)) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). Definition execute_MTLO (rs : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => write_reg LO_ref w__0 : M (unit). + + (rGPR rs) >>= fun w__0 : mword 64 => write_reg LO_ref w__0 : M (unit). Definition execute_MTHI (rs : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => write_reg HI_ref w__0 : M (unit). + + (rGPR rs) >>= fun w__0 : mword 64 => write_reg HI_ref w__0 : M (unit). Definition execute_MTC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) : M (unit) := - checkCP0Access tt >> - rGPR rt >>= fun reg_val => + + (checkCP0Access tt) >> + (rGPR rt) >>= fun reg_val => (match (rd, sel) with - | (b__108, b__109) => - (if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + | (b__112, b__113) => + (if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then write_reg TLBIndex_ref (mask 6 reg_val) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then returnm (tt : unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then (_set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then (_set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then (_set_ContextReg_PTEBase TLBContext_ref (subrange_vec_dec reg_val 63 23)) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B1;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B1;B0] : mword 3)))) then write_reg CP0UserLocal_ref reg_val : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then write_reg TLBPageMask_ref (subrange_vec_dec reg_val 28 13) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then write_reg TLBWired_ref (mask 6 reg_val) >> write_reg TLBRandom_ref TLBIndexMax : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then write_reg CP0HWREna_ref (concat_vec (subrange_vec_dec reg_val 31 29) @@ -3710,62 +4427,65 @@ Definition execute_MTC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : B0;B0;B0;B0] : mword 25) (subrange_vec_dec reg_val 3 0))) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then returnm (tt : unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then write_reg CP0Count_ref (subrange_vec_dec reg_val 31 0) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - _set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec reg_val 63 62) >> - _set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec reg_val 39 13) >> + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_TLBEntryHiReg_R TLBEntryHi_ref (subrange_vec_dec reg_val 63 62)) >> + (_set_TLBEntryHiReg_VPN2 TLBEntryHi_ref (subrange_vec_dec reg_val 39 13)) >> (_set_TLBEntryHiReg_ASID TLBEntryHi_ref (subrange_vec_dec reg_val 7 0)) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then write_reg CP0Compare_ref (subrange_vec_dec reg_val 31 0) >> - read_reg CP0Cause_ref >>= fun w__0 => + read_reg CP0Cause_ref >>= fun w__0 : CauseReg => (_set_CauseReg_IP CP0Cause_ref (and_vec (_get_CauseReg_IP w__0) (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : mword 8))) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - _set_StatusReg_CU CP0Status_ref (subrange_vec_dec reg_val 31 28) >> - _set_StatusReg_BEV CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 22)) : mword 1) >> - _set_StatusReg_IM CP0Status_ref (subrange_vec_dec reg_val 15 8) >> - _set_StatusReg_KX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 7)) : mword 1) >> - _set_StatusReg_SX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 6)) : mword 1) >> - _set_StatusReg_UX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 5)) : mword 1) >> - _set_StatusReg_KSU CP0Status_ref (subrange_vec_dec reg_val 4 3) >> - _set_StatusReg_ERL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 2)) : mword 1) >> - _set_StatusReg_EXL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 1)) : mword 1) >> + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_StatusReg_CU CP0Status_ref + (and_vec (subrange_vec_dec reg_val 31 28) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (bool_to_bits have_cp2) (vec_of_bits [B0;B1] : mword 2))))) >> + (_set_StatusReg_BEV CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 22)) : mword 1)) >> + (_set_StatusReg_IM CP0Status_ref (subrange_vec_dec reg_val 15 8)) >> + (_set_StatusReg_KX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 7)) : mword 1)) >> + (_set_StatusReg_SX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 6)) : mword 1)) >> + (_set_StatusReg_UX CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 5)) : mword 1)) >> + (_set_StatusReg_KSU CP0Status_ref (subrange_vec_dec reg_val 4 3)) >> + (_set_StatusReg_ERL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 2)) : mword 1)) >> + (_set_StatusReg_EXL CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 1)) : mword 1)) >> (_set_StatusReg_IE CP0Status_ref ((cast_unit_vec (access_vec_dec reg_val 0)) : mword 1)) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then - _set_CauseReg_IV CP0Cause_ref ((cast_unit_vec (access_vec_dec reg_val 23)) : mword 1) >> - read_reg CP0Cause_ref >>= fun w__1 => + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then + (_set_CauseReg_IV CP0Cause_ref ((cast_unit_vec (access_vec_dec reg_val 23)) : mword 1)) >> + read_reg CP0Cause_ref >>= fun w__1 : CauseReg => let ip := _get_CauseReg_IP w__1 in (_set_CauseReg_IP CP0Cause_ref (concat_vec (subrange_vec_dec ip 7 2) (subrange_vec_dec reg_val 9 8))) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then write_reg CP0EPC_ref reg_val : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then write_reg CP0ConfigK0_ref (subrange_vec_dec reg_val 2 0) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then (_set_XContextReg_XPTEBase TLBXContext_ref (subrange_vec_dec reg_val 63 33)) : M (unit) - else if ((andb (eq_vec b__108 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5)) - (eq_vec b__109 (vec_of_bits [B0;B0;B0] : mword 3)))) then + else if ((andb (eq_vec b__112 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5)) + (eq_vec b__113 (vec_of_bits [B0;B0;B0] : mword 3)))) then write_reg CP0ErrorEPC_ref reg_val : M (unit) else (SignalException ResI) : M (unit)) @@ -3775,12 +4495,15 @@ Definition execute_MTC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : Definition execute_MSUBU (rs : mword 5) (rt : mword 5) : M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (bits 64) - else returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) : bits 64)) >>= fun mul_result => - (read_reg HI_ref : M (mword 64)) >>= fun w__1 => - (read_reg LO_ref : M (mword 64)) >>= fun w__2 => + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => let result := sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> @@ -3789,14 +4512,15 @@ Definition execute_MSUBU (rs : mword 5) (rt : mword 5) Definition execute_MSUB (rs : mword 5) (rt : mword 5) : M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (bits 64) + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) else returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) - : bits 64)) >>= fun mul_result => - (read_reg HI_ref : M (mword 64)) >>= fun w__1 => - (read_reg LO_ref : M (mword 64)) >>= fun w__2 => + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => let result := sub_vec (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) mul_result in write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> @@ -3805,241 +4529,265 @@ Definition execute_MSUB (rs : mword 5) (rt : mword 5) Definition execute_MOVZ (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rt >>= fun w__0 => + + (rGPR rt) >>= fun w__0 : mword 64 => (if ((eq_vec w__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0] : mword 64))) then - rGPR rs >>= fun w__1 => (wGPR rd w__1) : M (unit) + (rGPR rs) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) else returnm (tt : unit)) : M (unit). Definition execute_MOVN (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rt >>= fun w__0 => + + (rGPR rt) >>= fun w__0 : mword 64 => (if ((neq_vec w__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0] : mword 64))) then - rGPR rs >>= fun w__1 => (wGPR rd w__1) : M (unit) + (rGPR rs) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit) else returnm (tt : unit)) : M (unit). Definition execute_MFLO (rd : mword 5) : M (unit) := - (read_reg LO_ref : M (mword 64)) >>= fun w__0 => (wGPR rd w__0) : M (unit). + + ((read_reg LO_ref) : M (mword 64)) >>= fun w__0 : bits 64 => (wGPR rd w__0) : M (unit). Definition execute_MFHI (rd : mword 5) : M (unit) := - (read_reg HI_ref : M (mword 64)) >>= fun w__0 => (wGPR rd w__0) : M (unit). + + ((read_reg HI_ref) : M (mword 64)) >>= fun w__0 : bits 64 => (wGPR rd w__0) : M (unit). Definition execute_MFC0 (rt : mword 5) (rd : mword 5) (sel : mword 3) (double : bool) : M (unit) := - checkCP0Access tt >> - match (rd, sel) with - | (b__48, b__49) => - (if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg TLBIndex_ref : M (mword 6)) >>= fun w__0 => - let idx : bits 31 := mips_zero_extend 31 w__0 in - (read_reg TLBProbe_ref : M (mword 1)) >>= fun w__1 => - returnm ((concat_vec - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32) (concat_vec w__1 idx)) - : mword 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg TLBRandom_ref : M (mword 6)) >>= fun w__2 => - returnm ((mips_zero_extend 64 w__2) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg TLBEntryLo0_ref >>= fun w__3 => - returnm ((_get_TLBEntryLoReg_bits w__3) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg TLBEntryLo1_ref >>= fun w__4 => - returnm ((_get_TLBEntryLoReg_bits w__4) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg TLBContext_ref >>= fun w__5 => returnm ((_get_ContextReg_bits w__5) : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then - (read_reg CP0UserLocal_ref : M (mword 64)) - : M (bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg TLBPageMask_ref : M (mword 16)) >>= fun w__7 => - returnm ((mips_zero_extend 64 - (concat_vec w__7 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg TLBWired_ref : M (mword 6)) >>= fun w__8 => - returnm ((mips_zero_extend 64 w__8) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0HWREna_ref : M (mword 32)) >>= fun w__9 => - returnm ((mips_zero_extend 64 w__9) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0BadVAddr_ref : M (mword 64)) - : M (bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B1] : mword 3)))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0Count_ref : M (mword 32)) >>= fun w__11 => - returnm ((mips_zero_extend 64 w__11) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg TLBEntryHi_ref >>= fun w__12 => - returnm ((_get_TLBEntryHiReg_bits w__12) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0Compare_ref : M (mword 32)) >>= fun w__13 => - returnm ((mips_zero_extend 64 w__13) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg CP0Status_ref >>= fun w__14 => - returnm ((mips_zero_extend 64 (_get_StatusReg_bits w__14)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg CP0Cause_ref >>= fun w__15 => - returnm ((mips_zero_extend 64 (_get_CauseReg_bits w__15)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0EPC_ref : M (mword 64)) - : M (bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - returnm ((mips_zero_extend 64 - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] - : mword 32)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B1;B1;B0] : mword 3)))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B1;B1;B1] : mword 3)))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0ConfigK0_ref : M (mword 3)) >>= fun w__17 => - returnm ((mips_zero_extend 64 - (concat_vec (vec_of_bits [B1] : mword 1) - (concat_vec - (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 15) - (concat_vec (vec_of_bits [B1] : mword 1) - (concat_vec (vec_of_bits [B1;B0] : mword 2) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) w__17)))))))) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B1] : mword 3)))) then - returnm ((mips_zero_extend 64 - (concat_vec (vec_of_bits [B1] : mword 1) - (concat_vec TLBIndexMax - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (bool_to_bits have_cp2) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec (vec_of_bits [B0] : mword 1) - (concat_vec - (vec_of_bits [B0] : mword 1) - (vec_of_bits [B0] : mword 1)))))))))))))))) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then - returnm ((mips_zero_extend 64 - (concat_vec (vec_of_bits [B1] : mword 1) - (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) - (vec_of_bits [B0;B0;B0;B0] : mword 4)))))))))) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B1;B1] : mword 3)))) then - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) - : mword 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B1;B0;B1] : mword 3)))) then - returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; - B0] - : mword 64) - : mword 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0LLAddr_ref : M (mword 64)) - : M (bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B1] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - read_reg TLBXContext_ref >>= fun w__19 => - returnm ((_get_XContextReg_bits w__19) - : bits 64) - else if ((andb (eq_vec b__48 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5)) - (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then - (read_reg CP0ErrorEPC_ref : M (mword 64)) - : M (bits 64) - else (SignalException ResI) : M (bits 64)) - : M (mword 64) - end >>= fun result => + + (checkCP0Access tt) >> + (match (rd, sel) with + | (b__48, b__49) => + (if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBIndex_ref) : M (mword 6)) >>= fun w__0 : TLBIndexT => + let idx : bits 31 := mips_zero_extend 31 w__0 in + ((read_reg TLBProbe_ref) : M (mword 1)) >>= fun w__1 : bits 1 => + returnm ((concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) (concat_vec w__1 idx)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBRandom_ref) : M (mword 6)) >>= fun w__2 : TLBIndexT => + returnm ((mips_zero_extend 64 w__2) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBEntryLo0_ref >>= fun w__3 : TLBEntryLoReg => + returnm ((_get_TLBEntryLoReg_bits w__3) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBEntryLo1_ref >>= fun w__4 : TLBEntryLoReg => + returnm ((_get_TLBEntryLoReg_bits w__4) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBContext_ref >>= fun w__5 : ContextReg => + returnm ((_get_ContextReg_bits w__5) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then + ((read_reg CP0UserLocal_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBPageMask_ref) : M (mword 16)) >>= fun w__7 : bits 16 => + returnm ((mips_zero_extend 64 + (concat_vec w__7 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg TLBWired_ref) : M (mword 6)) >>= fun w__8 : TLBIndexT => + returnm ((mips_zero_extend 64 w__8) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B0;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0HWREna_ref) : M (mword 32)) >>= fun w__9 : bits 32 => + returnm ((mips_zero_extend 64 w__9) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0BadVAddr_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B1] : mword 3)))) then + ((read_reg CP0BadInstr_ref) : M (mword 32)) >>= fun w__11 : bits 32 => + returnm ((mips_zero_extend 64 w__11) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then + ((read_reg CP0BadInstrP_ref) : M (mword 32)) >>= fun w__12 : bits 32 => + returnm ((mips_zero_extend 64 w__12) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0Count_ref) : M (mword 32)) >>= fun w__13 : bits 32 => + returnm ((mips_zero_extend 64 w__13) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBEntryHi_ref >>= fun w__14 : TLBEntryHiReg => + returnm ((_get_TLBEntryHiReg_bits w__14) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B0;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0Compare_ref) : M (mword 32)) >>= fun w__15 : bits 32 => + returnm ((mips_zero_extend 64 w__15) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg CP0Status_ref >>= fun w__16 : StatusReg => + returnm ((mips_zero_extend 64 (_get_StatusReg_bits w__16)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg CP0Cause_ref >>= fun w__17 : CauseReg => + returnm ((mips_zero_extend 64 (_get_CauseReg_bits w__17)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0EPC_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B1;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B0;B1;B1;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B1;B1] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0ConfigK0_ref) : M (mword 3)) >>= fun w__19 : bits 3 => + returnm ((mips_zero_extend 64 + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 15) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B1;B0] : mword 2) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) w__19)))))))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B1] : mword 3)))) then + returnm ((mips_zero_extend 64 + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec TLBIndexMax + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (bool_to_bits have_cp2) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec + (vec_of_bits [B0] : mword 1) + (vec_of_bits [B0] : mword 1)))))))))))))))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (vec_of_bits [B0;B0;B0;B0] : mword 4)))))))))) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B1;B1] : mword 3)))) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B0;B1] : mword 3)))) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B1;B1;B0] : mword 3)))) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B0;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0LLAddr_ref) : M (mword 64)) + : M (bits 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B0;B1;B1] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + returnm ((mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B0;B1;B0;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + read_reg TLBXContext_ref >>= fun w__21 : XContextReg => + returnm ((_get_XContextReg_bits w__21) + : mword 64) + else if ((andb (eq_vec b__48 (vec_of_bits [B1;B1;B1;B1;B0] : mword 5)) + (eq_vec b__49 (vec_of_bits [B0;B0;B0] : mword 3)))) then + ((read_reg CP0ErrorEPC_ref) : M (mword 64)) + : M (bits 64) + else (SignalException ResI) : M (mword 64)) + : M (mword 64) + end) >>= fun result : bits 64 => (wGPR rt (if (double) then result else mips_sign_extend 64 (subrange_vec_dec result 31 0))) : M (unit). Definition execute_MADDU (rs : mword 5) (rt : mword 5) : M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (bits 64) - else returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) : bits 64)) >>= fun mul_result => - (read_reg HI_ref : M (mword 64)) >>= fun w__1 => - (read_reg LO_ref : M (mword 64)) >>= fun w__2 => + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) + else + returnm ((mult_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => let result := add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> @@ -4048,68 +4796,85 @@ Definition execute_MADDU (rs : mword 5) (rt : mword 5) Definition execute_MADD (rs : mword 5) (rt : mword 5) : M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => - (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (bits 64) + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => + (if ((orb (NotWordVal rsVal) (NotWordVal rtVal))) then (undefined_bitvector 64) : M (mword 64) else returnm ((mults_vec (subrange_vec_dec rsVal 31 0) (subrange_vec_dec rtVal 31 0)) - : bits 64)) >>= fun mul_result => - (read_reg HI_ref : M (mword 64)) >>= fun w__1 => - (read_reg LO_ref : M (mword 64)) >>= fun w__2 => + : mword (2 * 32))) >>= fun mul_result : bits 64 => + ((read_reg HI_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + ((read_reg LO_ref) : M (mword 64)) >>= fun w__2 : bits 64 => let result := add_vec mul_result (concat_vec (subrange_vec_dec w__1 31 0) (subrange_vec_dec w__2 31 0)) in write_reg HI_ref (mips_sign_extend 64 (subrange_vec_dec result 63 32)) >> write_reg LO_ref (mips_sign_extend 64 (subrange_vec_dec result 31 0)) : M (unit). -Definition execute_Load (width : WordType) (sign : bool) (linked : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) +Definition execute_Load +(width : WordType) (sign : bool) (linked : bool) (base : mword 5) (rt : mword 5) (offset : mword 16) + : M (unit) := - rGPR base >>= fun w__0 => + + (rGPR base) >>= fun w__0 : mword 64 => let vAddr : bits 64 := addrWrapper (add_vec (mips_sign_extend 64 offset) w__0) LoadData width in (if ((negb (isAddressAligned vAddr width))) then (SignalExceptionBadAddr AdEL vAddr) : M (unit) else - TLBTranslate vAddr LoadData >>= fun pAddr => + (TLBTranslate vAddr LoadData) >>= fun pAddr => (if (linked) then write_reg CP0LLBit_ref (vec_of_bits [B1] : mword 1) >> write_reg CP0LLAddr_ref pAddr >> (match width with | W => - MEMr_reserve_wrapper pAddr 4 >>= fun w__1 => + (MEMr_reserve_wrapper pAddr 4) >>= fun w__1 : mword (8 * 4) => returnm ((extendLoad w__1 sign) - : bits 64) + : mword 64) | D => - MEMr_reserve_wrapper pAddr 8 >>= fun w__2 => + (MEMr_reserve_wrapper pAddr 8) >>= fun w__2 : mword (8 * 8) => returnm ((extendLoad w__2 sign) - : bits 64) - | _ => (throw (Error_internal_error tt)) : M (mword 64) + : mword 64) + | _ => (throw (Error_internal_error (tt))) : M (mword 64) end) : M (mword 64) else (match width with - | B => MEMr_wrapper pAddr 1 >>= fun w__5 => returnm ((extendLoad w__5 sign) : bits 64) - | H => MEMr_wrapper pAddr 2 >>= fun w__6 => returnm ((extendLoad w__6 sign) : bits 64) - | W => MEMr_wrapper pAddr 4 >>= fun w__7 => returnm ((extendLoad w__7 sign) : bits 64) - | D => MEMr_wrapper pAddr 8 >>= fun w__8 => returnm ((extendLoad w__8 sign) : bits 64) + | B => + (MEMr_wrapper pAddr 1) >>= fun w__5 : mword (8 * 1) => + returnm ((extendLoad w__5 sign) + : mword 64) + | H => + (MEMr_wrapper pAddr 2) >>= fun w__6 : mword (8 * 2) => + returnm ((extendLoad w__6 sign) + : mword 64) + | W => + (MEMr_wrapper pAddr 4) >>= fun w__7 : mword (8 * 4) => + returnm ((extendLoad w__7 sign) + : mword 64) + | D => + (MEMr_wrapper pAddr 8) >>= fun w__8 : mword (8 * 8) => + returnm ((extendLoad w__8 sign) + : mword 64) end) - : M (mword 64)) >>= fun memResult => + : M (mword 64)) >>= fun memResult : bits 64 => (wGPR rt memResult) : M (unit)) : M (unit). Definition execute_LWR (base : mword 5) (rt : mword 5) (offset : mword 16) : M (unit) := - rGPR base >>= fun w__0 => + + (rGPR base) >>= fun w__0 : mword 64 => let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WR in - TLBTranslate vAddr LoadData >>= fun pAddr => - MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2)) 4 >>= fun mem_val => - rGPR rt >>= fun reg_val => + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2)) 4) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => let b__4 := subrange_vec_dec vAddr 1 0 in let result : bits 32 := - if ((eq_vec b__4 (vec_of_bits [B0;B0] : mword 2))) then + if ((eq_vec b__4 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then concat_vec (subrange_vec_dec reg_val 31 8) (subrange_vec_dec mem_val 31 24) - else if ((eq_vec b__4 (vec_of_bits [B0;B1] : mword 2))) then + else if ((eq_vec b__4 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then concat_vec (subrange_vec_dec reg_val 31 16) (subrange_vec_dec mem_val 31 16) - else if ((eq_vec b__4 (vec_of_bits [B1;B0] : mword 2))) then + else if ((eq_vec b__4 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then concat_vec (subrange_vec_dec reg_val 31 24) (subrange_vec_dec mem_val 31 8) else mem_val in (wGPR rt (mips_sign_extend 64 result)) @@ -4117,17 +4882,18 @@ Definition execute_LWR (base : mword 5) (rt : mword 5) (offset : mword 16) Definition execute_LWL (base : mword 5) (rt : mword 5) (offset : mword 16) : M (unit) := - rGPR base >>= fun w__0 => + + (rGPR base) >>= fun w__0 : mword 64 => let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData WL in - TLBTranslate vAddr LoadData >>= fun pAddr => - MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2)) 4 >>= fun mem_val => - rGPR rt >>= fun reg_val => + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 2) (vec_of_bits [B0;B0] : mword 2)) 4) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => let b__0 := subrange_vec_dec vAddr 1 0 in let result : bits 32 := - if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then mem_val - else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) then mem_val + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))) then concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 7 0) - else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))) then concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 15 0) else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 23 0) in (wGPR rt (mips_sign_extend 64 result)) @@ -4135,6 +4901,7 @@ Definition execute_LWL (base : mword 5) (rt : mword 5) (offset : mword 16) Definition execute_LUI (rt : mword 5) (imm : mword 16) : M (unit) := + (wGPR rt (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 16)))) @@ -4142,112 +4909,136 @@ Definition execute_LUI (rt : mword 5) (imm : mword 16) Definition execute_LDR (base : mword 5) (rt : mword 5) (offset : mword 16) : M (unit) := - rGPR base >>= fun w__0 => + + (rGPR base) >>= fun w__0 : mword 64 => let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DR in - TLBTranslate vAddr LoadData >>= fun pAddr => - MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3)) 8 >>= fun mem_val => - rGPR rt >>= fun reg_val => + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3)) 8) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => let b__24 := subrange_vec_dec vAddr 2 0 in (wGPR rt - (if ((eq_vec b__24 (vec_of_bits [B0;B0;B0] : mword 3))) then + (if ((eq_vec b__24 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec reg_val 63 8) (subrange_vec_dec mem_val 63 56) - else if ((eq_vec b__24 (vec_of_bits [B0;B0;B1] : mword 3))) then + else if ((eq_vec b__24 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec reg_val 63 16) (subrange_vec_dec mem_val 63 48) - else if ((eq_vec b__24 (vec_of_bits [B0;B1;B0] : mword 3))) then + else if ((eq_vec b__24 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec reg_val 63 24) (subrange_vec_dec mem_val 63 40) - else if ((eq_vec b__24 (vec_of_bits [B0;B1;B1] : mword 3))) then + else if ((eq_vec b__24 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec reg_val 63 32) (subrange_vec_dec mem_val 63 32) - else if ((eq_vec b__24 (vec_of_bits [B1;B0;B0] : mword 3))) then + else if ((eq_vec b__24 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec reg_val 63 40) (subrange_vec_dec mem_val 63 24) - else if ((eq_vec b__24 (vec_of_bits [B1;B0;B1] : mword 3))) then + else if ((eq_vec b__24 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec reg_val 63 48) (subrange_vec_dec mem_val 63 16) - else if ((eq_vec b__24 (vec_of_bits [B1;B1;B0] : mword 3))) then + else if ((eq_vec b__24 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec reg_val 63 56) (subrange_vec_dec mem_val 63 8) else mem_val)) : M (unit). Definition execute_LDL (base : mword 5) (rt : mword 5) (offset : mword 16) : M (unit) := - rGPR base >>= fun w__0 => + + (rGPR base) >>= fun w__0 : mword 64 => let vAddr := addrWrapperUnaligned (add_vec (mips_sign_extend 64 offset) w__0) LoadData DL in - TLBTranslate vAddr LoadData >>= fun pAddr => - MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3)) 8 >>= fun mem_val => - rGPR rt >>= fun reg_val => + (TLBTranslate vAddr LoadData) >>= fun pAddr => + (MEMr_wrapper (concat_vec (subrange_vec_dec pAddr 63 3) (vec_of_bits [B0;B0;B0] : mword 3)) 8) >>= fun mem_val => + (rGPR rt) >>= fun reg_val => let b__16 := subrange_vec_dec vAddr 2 0 in (wGPR rt - (if ((eq_vec b__16 (vec_of_bits [B0;B0;B0] : mword 3))) then mem_val - else if ((eq_vec b__16 (vec_of_bits [B0;B0;B1] : mword 3))) then + (if ((eq_vec b__16 (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1)))) then mem_val + else if ((eq_vec b__16 (vec_of_bits [B0;B0;B1] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec mem_val 55 0) (subrange_vec_dec reg_val 7 0) - else if ((eq_vec b__16 (vec_of_bits [B0;B1;B0] : mword 3))) then + else if ((eq_vec b__16 (vec_of_bits [B0;B1;B0] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec mem_val 47 0) (subrange_vec_dec reg_val 15 0) - else if ((eq_vec b__16 (vec_of_bits [B0;B1;B1] : mword 3))) then + else if ((eq_vec b__16 (vec_of_bits [B0;B1;B1] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec mem_val 39 0) (subrange_vec_dec reg_val 23 0) - else if ((eq_vec b__16 (vec_of_bits [B1;B0;B0] : mword 3))) then + else if ((eq_vec b__16 (vec_of_bits [B1;B0;B0] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec mem_val 31 0) (subrange_vec_dec reg_val 31 0) - else if ((eq_vec b__16 (vec_of_bits [B1;B0;B1] : mword 3))) then + else if ((eq_vec b__16 (vec_of_bits [B1;B0;B1] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec mem_val 23 0) (subrange_vec_dec reg_val 39 0) - else if ((eq_vec b__16 (vec_of_bits [B1;B1;B0] : mword 3))) then + else if ((eq_vec b__16 (vec_of_bits [B1;B1;B0] : mword (2 - 0 + 1)))) then concat_vec (subrange_vec_dec mem_val 15 0) (subrange_vec_dec reg_val 47 0) else concat_vec (subrange_vec_dec mem_val 7 0) (subrange_vec_dec reg_val 55 0))) : M (unit). Definition execute_JR (rs : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => (execute_branch w__0) : M (unit). + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (rGPR rs) >>= fun w__1 : mword 64 => (execute_branch w__1) : M (unit). Definition execute_JALR (rs : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => - execute_branch w__0 >> - (read_reg PC_ref : M (mword 64)) >>= fun w__1 => (wGPR rd (add_vec_int w__1 8)) : M (unit). + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (rGPR rs) >>= fun w__1 : mword 64 => + (execute_branch w__1) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + (wGPR rd (add_vec_int w__2 8)) + : M (unit). Definition execute_JAL (offset : mword 26) : M (unit) := - (read_reg PC_ref : M (mword 64)) >>= fun w__0 => - execute_branch - (concat_vec (subrange_vec_dec (add_vec_int w__0 4) 63 28) - (concat_vec offset (vec_of_bits [B0;B0] : mword 2))) >> - (read_reg PC_ref : M (mword 64)) >>= fun w__1 => - (wGPR (vec_of_bits [B1;B1;B1;B1;B1] : mword 5) (add_vec_int w__1 8)) + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + (execute_branch + (concat_vec (subrange_vec_dec (add_vec_int w__1 4) 63 28) + (concat_vec offset (vec_of_bits [B0;B0] : mword 2)))) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + (wGPR (vec_of_bits [B1;B1;B1;B1;B1] : mword 5) (add_vec_int w__2 8)) : M (unit). Definition execute_J (offset : mword 26) : M (unit) := - (read_reg PC_ref : M (mword 64)) >>= fun w__0 => + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => (execute_branch - (concat_vec (subrange_vec_dec (add_vec_int w__0 4) 63 28) + (concat_vec (subrange_vec_dec (add_vec_int w__1 4) 63 28) (concat_vec offset (vec_of_bits [B0;B0] : mword 2)))) : M (unit). -Definition execute_HCF (g__18 : unit) : unit := tt. +Definition execute_HCF '(tt : unit) : unit := tt. -Definition execute_ERET (g__23 : unit) +Definition execute_ERET '(tt : unit) : M (unit) := - checkCP0Access tt >> + + (checkCP0Access tt) >> let '_ := (ERETHook tt) : unit in write_reg CP0LLBit_ref (vec_of_bits [B0] : mword 1) >> - read_reg CP0Status_ref >>= fun w__0 => + read_reg CP0Status_ref >>= fun w__0 : StatusReg => (if ((Bool.eqb ((bits_to_bool (_get_StatusReg_ERL w__0)) : bool) ((bit_to_bool B1) : bool))) then - (read_reg CP0ErrorEPC_ref : M (mword 64)) >>= fun w__1 => - write_reg nextPC_ref w__1 >> + ((read_reg CP0ErrorEPC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + write_reg NextPC_ref w__1 >> (_set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] : mword 1)) : M (unit) else - (read_reg CP0EPC_ref : M (mword 64)) >>= fun w__2 => - write_reg nextPC_ref w__2 >> + ((read_reg CP0EPC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + write_reg NextPC_ref w__2 >> (_set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] : mword 1)) : M (unit)) : M (unit). Definition execute_DSUBU (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (sub_vec w__0 w__1)) : M (unit). + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (sub_vec w__0 w__1)) : M (unit). Definition execute_DSUB (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => - rGPR rt >>= fun w__1 => + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => let temp65 : bits 65 := sub_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in (if ((neq_bool ((bit_to_bool (access_vec_dec temp65 64)) : bool) ((bit_to_bool (access_vec_dec temp65 63)) @@ -4259,59 +5050,74 @@ Definition execute_DSUB (rs : mword 5) (rt : mword 5) (rd : mword 5) Definition execute_DSRLV (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rt >>= fun temp => - rGPR rs >>= fun w__0 => + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => let sa := subrange_vec_dec w__0 5 0 in - shift_bits_right temp sa >>= fun w__1 => (wGPR rd w__1) : M (unit). + (shift_bits_right temp sa) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). Definition execute_DSRL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) : M (unit) := - rGPR rt >>= fun temp => + + (rGPR rt) >>= fun temp => let sa32 := concat_vec (vec_of_bits [B1] : mword 1) sa in - shift_bits_right temp sa32 >>= fun w__0 => (wGPR rd w__0) : M (unit). + (shift_bits_right temp sa32) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). Definition execute_DSRL (rt : mword 5) (rd : mword 5) (sa : mword 5) : M (unit) := - rGPR rt >>= fun temp => shift_bits_right temp sa >>= fun w__0 => (wGPR rd w__0) : M (unit). + + (rGPR rt) >>= fun temp => + (shift_bits_right temp sa) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). Definition execute_DSRAV (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rt >>= fun temp => - rGPR rs >>= fun w__0 => + + (rGPR rt) >>= fun temp => + (rGPR rs) >>= fun w__0 : mword 64 => let sa := subrange_vec_dec w__0 5 0 in - shift_bits_right_arith temp sa >>= fun w__1 => (wGPR rd w__1) : M (unit). + (shift_bits_right_arith temp sa) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). Definition execute_DSRA32 (rt : mword 5) (rd : mword 5) (sa : mword 5) : M (unit) := - rGPR rt >>= fun temp => + + (rGPR rt) >>= fun temp => let sa32 := concat_vec (vec_of_bits [B1] : mword 1) sa in - shift_bits_right_arith temp sa32 >>= fun w__0 => (wGPR rd w__0) : M (unit). + (shift_bits_right_arith temp sa32) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). Definition execute_DSRA (rt : mword 5) (rd : mword 5) (sa : mword 5) : M (unit) := - rGPR rt >>= fun temp => shift_bits_right_arith temp sa >>= fun w__0 => (wGPR rd w__0) : M (unit). + + (rGPR rt) >>= fun temp => + (shift_bits_right_arith temp sa) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit). Definition execute_DSLLV (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rt >>= fun w__0 => - rGPR rs >>= fun w__1 => - shift_bits_left w__0 (subrange_vec_dec w__1 5 0) >>= fun w__2 => (wGPR rd w__2) : M (unit). + + (rGPR rt) >>= fun w__0 : mword 64 => + (rGPR rs) >>= fun w__1 : mword 64 => + (shift_bits_left w__0 (subrange_vec_dec w__1 5 0)) >>= fun w__2 : mword 64 => + (wGPR rd w__2) + : M (unit). Definition execute_DSLL32 (rt : mword 5) (rd : mword 5) (sa : mword 5) : M (unit) := - rGPR rt >>= fun w__0 => - shift_bits_left w__0 (concat_vec (vec_of_bits [B1] : mword 1) sa) >>= fun w__1 => + + (rGPR rt) >>= fun w__0 : mword 64 => + (shift_bits_left w__0 (concat_vec (vec_of_bits [B1] : mword 1) sa)) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). Definition execute_DSLL (rt : mword 5) (rd : mword 5) (sa : mword 5) : M (unit) := - rGPR rt >>= fun w__0 => shift_bits_left w__0 sa >>= fun w__1 => (wGPR rd w__1) : M (unit). + + (rGPR rt) >>= fun w__0 : mword 64 => + (shift_bits_left w__0 sa) >>= fun w__1 : mword 64 => (wGPR rd w__1) : M (unit). Definition execute_DMULTU (rs : mword 5) (rt : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => - rGPR rt >>= fun w__1 => + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => let result := mult_vec w__0 w__1 in write_reg HI_ref (subrange_vec_dec result 127 64) >> write_reg LO_ref (subrange_vec_dec result 63 0) @@ -4319,8 +5125,9 @@ Definition execute_DMULTU (rs : mword 5) (rt : mword 5) Definition execute_DMULT (rs : mword 5) (rt : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => - rGPR rt >>= fun w__1 => + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => let result := mults_vec w__0 w__1 in write_reg HI_ref (subrange_vec_dec result 127 64) >> write_reg LO_ref (subrange_vec_dec result 63 0) @@ -4328,8 +5135,9 @@ Definition execute_DMULT (rs : mword 5) (rt : mword 5) Definition execute_DIVU (rs : mword 5) (rt : mword 5) : M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => (if ((orb (NotWordVal rsVal) (orb (NotWordVal rtVal) (eq_vec rtVal @@ -4338,23 +5146,21 @@ Definition execute_DIVU (rs : mword 5) (rt : mword 5) B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0] : mword 64))))) then - undefined_bitvector 32 >>= fun w__0 => - undefined_bitvector 32 >>= fun w__1 => - returnm ((w__0 : bits 32, w__1 : bits 32) - : (bits 32 * bits 32)) + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + (undefined_bitvector 32) >>= fun w__1 : mword 32 => returnm (w__0 : bits 32, w__1 : bits 32) else - let '(existT _ si _) := uint (subrange_vec_dec rsVal 31 0) in - let '(existT _ ti _) := uint (subrange_vec_dec rtVal 31 0) in + let 'si := projT1 (uint (subrange_vec_dec rsVal 31 0)) in + let 'ti := projT1 (uint (subrange_vec_dec rtVal 31 0)) in let qi := Z.quot si ti in let ri := Z.rem si ti in - returnm ((to_bits 32 qi, to_bits 32 ri) - : (mword 32 * mword 32))) >>= fun '(q, r) => + returnm (to_bits 32 qi, to_bits 32 ri)) >>= fun '(q, r) => write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q) : M (unit). Definition execute_DIV (rs : mword 5) (rt : mword 5) : M (unit) := - rGPR rs >>= fun rsVal => - rGPR rt >>= fun rtVal => + + (rGPR rs) >>= fun rsVal => + (rGPR rt) >>= fun rtVal => (if ((orb (NotWordVal rsVal) (orb (NotWordVal rtVal) (eq_vec rtVal @@ -4363,66 +5169,65 @@ Definition execute_DIV (rs : mword 5) (rt : mword 5) B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0] : mword 64))))) then - undefined_bitvector 32 >>= fun w__0 => - undefined_bitvector 32 >>= fun w__1 => - returnm ((w__0 : bits 32, w__1 : bits 32) - : (bits 32 * bits 32)) + (undefined_bitvector 32) >>= fun w__0 : mword 32 => + (undefined_bitvector 32) >>= fun w__1 : mword 32 => returnm (w__0 : bits 32, w__1 : bits 32) else - let '(existT _ si _) := sint (subrange_vec_dec rsVal 31 0) in - let '(existT _ ti _) := sint (subrange_vec_dec rtVal 31 0) in + let 'si := projT1 (sint (subrange_vec_dec rsVal 31 0)) in + let 'ti := projT1 (sint (subrange_vec_dec rtVal 31 0)) in let qi := Z.quot si ti in let ri := Z.sub si (Z.mul ti qi) in - returnm ((to_bits 32 qi, to_bits 32 ri) - : (mword 32 * mword 32))) >>= fun '(q, r) => + returnm (to_bits 32 qi, to_bits 32 ri)) >>= fun '(q, r) => write_reg HI_ref (mips_sign_extend 64 r) >> write_reg LO_ref (mips_sign_extend 64 q) : M (unit). Definition execute_DDIVU (rs : mword 5) (rt : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => - let '(existT _ rsVal _) := uint w__0 in - rGPR rt >>= fun w__1 => - let '(existT _ rtVal _) := uint w__1 in - (if ((eq_range (build_ex rtVal) (build_ex 0))) then - undefined_bitvector 64 >>= fun w__2 => - undefined_bitvector 64 >>= fun w__3 => - returnm ((w__2 : bits 64, w__3 : bits 64) - : (bits 64 * bits 64)) + + (rGPR rs) >>= fun w__0 : mword 64 => + let 'rsVal := projT1 (uint w__0) in + (rGPR rt) >>= fun w__1 : mword 64 => + let 'rtVal := projT1 (uint w__1) in + (if sumbool_of_bool ((Z.eqb rtVal 0)) then + (undefined_bitvector 64) >>= fun w__2 : mword 64 => + (undefined_bitvector 64) >>= fun w__3 : mword 64 => returnm (w__2 : bits 64, w__3 : bits 64) else let qi := Z.quot rsVal rtVal in let ri := Z.rem rsVal rtVal in - returnm ((to_bits 64 qi, to_bits 64 ri) - : (mword 64 * mword 64))) >>= fun '(q, r) => + returnm (to_bits 64 qi, to_bits 64 ri)) >>= fun '(q, r) => write_reg LO_ref q >> write_reg HI_ref r : M (unit). Definition execute_DDIV (rs : mword 5) (rt : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => - let '(existT _ rsVal _) := sint w__0 in - rGPR rt >>= fun w__1 => - let '(existT _ rtVal _) := sint w__1 in - (if ((eq_range (build_ex rtVal) (build_ex 0))) then - undefined_bitvector 64 >>= fun w__2 => - undefined_bitvector 64 >>= fun w__3 => - returnm ((w__2 : bits 64, w__3 : bits 64) - : (bits 64 * bits 64)) + + (rGPR rs) >>= fun w__0 : mword 64 => + let 'rsVal := projT1 (sint w__0) in + (rGPR rt) >>= fun w__1 : mword 64 => + let 'rtVal := projT1 (sint w__1) in + (if sumbool_of_bool ((Z.eqb rtVal 0)) then + (undefined_bitvector 64) >>= fun w__2 : mword 64 => + (undefined_bitvector 64) >>= fun w__3 : mword 64 => returnm (w__2 : bits 64, w__3 : bits 64) else let qi := Z.quot rsVal rtVal in let ri := Z.sub rsVal (Z.mul qi rtVal) in - returnm ((to_bits 64 qi, to_bits 64 ri) - : (mword 64 * mword 64))) >>= fun '(q, r) => + returnm (to_bits 64 qi, to_bits 64 ri)) >>= fun '(q, r) => write_reg LO_ref q >> write_reg HI_ref r : M (unit). Definition execute_DADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (add_vec w__0 w__1)) : M (unit). + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (add_vec w__0 w__1)) : M (unit). Definition execute_DADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) : M (unit) := - rGPR rs >>= fun w__0 => (wGPR rt (add_vec w__0 (mips_sign_extend 64 imm))) : M (unit). + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (add_vec w__0 (mips_sign_extend 64 imm))) + : M (unit). Definition execute_DADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) : M (unit) := - rGPR rs >>= fun w__0 => + + (rGPR rs) >>= fun w__0 : mword 64 => let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 imm) in (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64)) : bool) ((bit_to_bool (access_vec_dec sum65 63)) @@ -4434,8 +5239,9 @@ Definition execute_DADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) Definition execute_DADD (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => - rGPR rt >>= fun w__1 => + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => let sum65 : bits 65 := add_vec (mips_sign_extend 65 w__0) (mips_sign_extend 65 w__1) in (if ((neq_bool ((bit_to_bool (access_vec_dec sum65 64)) : bool) ((bit_to_bool (access_vec_dec sum65 63)) @@ -4447,65 +5253,80 @@ Definition execute_DADD (rs : mword 5) (rt : mword 5) (rd : mword 5) Definition execute_CACHE (base : mword 5) (op : mword 5) (imm : mword 16) : M (unit) := + (checkCP0Access tt) : M (unit). -Definition execute_BREAK (g__15 : unit) : M (unit) := (SignalException Bp) : M (unit). +Definition execute_BREAK '(tt : unit) : M (unit) := (SignalException Bp) : M (unit). Definition execute_BEQ (rs : mword 5) (rd : mword 5) (imm : mword 16) (ne : bool) (likely : bool) : M (unit) := - rGPR rs >>= fun w__0 => - rGPR rd >>= fun w__1 => - (if (((bits_to_bool - (xor_vec ((bool_to_bits (eq_vec w__0 w__1)) : mword 1) ((bool_to_bits ne) : mword 1))) + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + (rGPR rs) >>= fun w__1 : mword 64 => + (rGPR rd) >>= fun w__2 : mword 64 => + (if (((bits_to_bool (xor_vec (bool_to_bits (eq_vec w__1 w__2)) ((bool_to_bits ne) : mword 1))) : bool)) then let offset : bits 64 := add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in - (read_reg PC_ref : M (mword 64)) >>= fun w__2 => - (execute_branch (add_vec w__2 offset)) + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : bits 64 => + (execute_branch (add_vec w__3 offset)) : M (unit) else if (likely) then - (read_reg PC_ref : M (mword 64)) >>= fun w__3 => - write_reg nextPC_ref (add_vec_int w__3 8) + ((read_reg PC_ref) : M (mword 64)) >>= fun w__4 : bits 64 => + write_reg NextPC_ref (add_vec_int w__4 8) : M (unit) - else returnm (tt : unit)) + else write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) : M (unit)) : M (unit). -Definition execute_BCMPZ (rs : mword 5) (imm : mword 16) (cmp : Comparison) (link : bool) (likely : bool) +Definition execute_BCMPZ +(rs : mword 5) (imm : mword 16) (cmp : Comparison) (link : bool) (likely : bool) : M (unit) := - (read_reg PC_ref : M (mword 64)) >>= fun w__0 => - let linkVal := add_vec_int w__0 8 in - rGPR rs >>= fun regVal => + + ((read_reg InBranchDelay_ref) : M (mword 1)) >>= fun w__0 : bits 1 => + (if (((bits_to_bool w__0) : bool)) then (SignalException ResI) : M (unit) + else returnm (tt : unit)) >> + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : bits 64 => + let linkVal := add_vec_int w__1 8 in + (rGPR rs) >>= fun regVal => let condition := compare cmp regVal (mips_zero_extend 64 (vec_of_bits [B0] : mword 1)) in (if (condition) then let offset : bits 64 := add_vec_int (mips_sign_extend 64 (concat_vec imm (vec_of_bits [B0;B0] : mword 2))) 4 in - (read_reg PC_ref : M (mword 64)) >>= fun w__1 => - (execute_branch (add_vec w__1 offset)) + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : bits 64 => + (execute_branch (add_vec w__2 offset)) : M (unit) else if (likely) then - (read_reg PC_ref : M (mword 64)) >>= fun w__2 => - write_reg nextPC_ref (add_vec_int w__2 8) + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : bits 64 => + write_reg NextPC_ref (add_vec_int w__3 8) : M (unit) - else returnm (tt : unit)) >> + else write_reg NextInBranchDelay_ref (vec_of_bits [B1] : mword 1) : M (unit)) >> (if (link) then (wGPR (vec_of_bits [B1;B1;B1;B1;B1] : mword 5) linkVal) : M (unit) else returnm (tt : unit)) : M (unit). Definition execute_ANDI (rs : mword 5) (rt : mword 5) (imm : mword 16) : M (unit) := - rGPR rs >>= fun w__0 => (wGPR rt (and_vec w__0 (mips_zero_extend 64 imm))) : M (unit). + + (rGPR rs) >>= fun w__0 : mword 64 => + (wGPR rt (and_vec w__0 (mips_zero_extend 64 imm))) + : M (unit). Definition execute_AND (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun w__0 => rGPR rt >>= fun w__1 => (wGPR rd (and_vec w__0 w__1)) : M (unit). + + (rGPR rs) >>= fun w__0 : mword 64 => + (rGPR rt) >>= fun w__1 : mword 64 => (wGPR rd (and_vec w__0 w__1)) : M (unit). Definition execute_ADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun opA => - rGPR rt >>= fun opB => + + (rGPR rs) >>= fun opA => + (rGPR rt) >>= fun opB => (if ((orb (NotWordVal opA) (NotWordVal opB))) then - undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0) : M (unit) + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) else (wGPR rd (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (subrange_vec_dec opB 31 0)))) @@ -4514,8 +5335,10 @@ Definition execute_ADDU (rs : mword 5) (rt : mword 5) (rd : mword 5) Definition execute_ADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) : M (unit) := - rGPR rs >>= fun opA => - (if ((NotWordVal opA)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rt w__0) : M (unit) + + (rGPR rs) >>= fun opA => + (if ((NotWordVal opA)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rt w__0) : M (unit) else (wGPR rt (mips_sign_extend 64 (add_vec (subrange_vec_dec opA 31 0) (mips_sign_extend 32 imm)))) : M (unit)) @@ -4523,8 +5346,10 @@ Definition execute_ADDIU (rs : mword 5) (rt : mword 5) (imm : mword 16) Definition execute_ADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) : M (unit) := - rGPR rs >>= fun opA => - (if ((NotWordVal opA)) then undefined_bitvector 64 >>= fun w__0 => (wGPR rt w__0) : M (unit) + + (rGPR rs) >>= fun opA => + (if ((NotWordVal opA)) then + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rt w__0) : M (unit) else let sum33 : bits 33 := add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) (mips_sign_extend 33 imm) in @@ -4539,10 +5364,11 @@ Definition execute_ADDI (rs : mword 5) (rt : mword 5) (imm : mword 16) Definition execute_ADD (rs : mword 5) (rt : mword 5) (rd : mword 5) : M (unit) := - rGPR rs >>= fun opA => - rGPR rt >>= fun opB => + + (rGPR rs) >>= fun opA : bits 64 => + (rGPR rt) >>= fun opB : bits 64 => (if ((orb (NotWordVal opA) (NotWordVal opB))) then - undefined_bitvector 64 >>= fun w__0 => (wGPR rd w__0) : M (unit) + (undefined_bitvector 64) >>= fun w__0 : mword 64 => (wGPR rd w__0) : M (unit) else let sum33 : bits 33 := add_vec (mips_sign_extend 33 (subrange_vec_dec opA 31 0)) @@ -4558,302 +5384,315 @@ Definition execute_ADD (rs : mword 5) (rt : mword 5) (rd : mword 5) Definition execute (merge_var : ast) : M (unit) := - match merge_var with - | DADDIU (rs,rt,imm) => (execute_DADDIU rs rt imm) : M (unit) - | DADDU (rs,rt,rd) => (execute_DADDU rs rt rd) : M (unit) - | DADDI (rs,rt,imm) => (execute_DADDI rs rt imm) : M (unit) - | DADD (rs,rt,rd) => (execute_DADD rs rt rd) : M (unit) - | ADD (rs,rt,rd) => (execute_ADD rs rt rd) : M (unit) - | ADDI (rs,rt,imm) => (execute_ADDI rs rt imm) : M (unit) - | ADDU (rs,rt,rd) => (execute_ADDU rs rt rd) : M (unit) - | ADDIU (rs,rt,imm) => (execute_ADDIU rs rt imm) : M (unit) - | DSUBU (rs,rt,rd) => (execute_DSUBU rs rt rd) : M (unit) - | DSUB (rs,rt,rd) => (execute_DSUB rs rt rd) : M (unit) - | SUB (rs,rt,rd) => (execute_SUB rs rt rd) : M (unit) - | SUBU (rs,rt,rd) => (execute_SUBU rs rt rd) : M (unit) - | AND (rs,rt,rd) => (execute_AND rs rt rd) : M (unit) - | ANDI (rs,rt,imm) => (execute_ANDI rs rt imm) : M (unit) - | OR (rs,rt,rd) => (execute_OR rs rt rd) : M (unit) - | ORI (rs,rt,imm) => (execute_ORI rs rt imm) : M (unit) - | NOR (rs,rt,rd) => (execute_NOR rs rt rd) : M (unit) - | XOR (rs,rt,rd) => (execute_XOR rs rt rd) : M (unit) - | XORI (rs,rt,imm) => (execute_XORI rs rt imm) : M (unit) - | LUI (rt,imm) => (execute_LUI rt imm) : M (unit) - | DSLL (rt,rd,sa) => (execute_DSLL rt rd sa) : M (unit) - | DSLL32 (rt,rd,sa) => (execute_DSLL32 rt rd sa) : M (unit) - | DSLLV (rs,rt,rd) => (execute_DSLLV rs rt rd) : M (unit) - | DSRA (rt,rd,sa) => (execute_DSRA rt rd sa) : M (unit) - | DSRA32 (rt,rd,sa) => (execute_DSRA32 rt rd sa) : M (unit) - | DSRAV (rs,rt,rd) => (execute_DSRAV rs rt rd) : M (unit) - | DSRL (rt,rd,sa) => (execute_DSRL rt rd sa) : M (unit) - | DSRL32 (rt,rd,sa) => (execute_DSRL32 rt rd sa) : M (unit) - | DSRLV (rs,rt,rd) => (execute_DSRLV rs rt rd) : M (unit) - | SLL (rt,rd,sa) => (execute_SLL rt rd sa) : M (unit) - | SLLV (rs,rt,rd) => (execute_SLLV rs rt rd) : M (unit) - | SRA (rt,rd,sa) => (execute_SRA rt rd sa) : M (unit) - | SRAV (rs,rt,rd) => (execute_SRAV rs rt rd) : M (unit) - | SRL (rt,rd,sa) => (execute_SRL rt rd sa) : M (unit) - | SRLV (rs,rt,rd) => (execute_SRLV rs rt rd) : M (unit) - | SLT (rs,rt,rd) => (execute_SLT rs rt rd) : M (unit) - | SLTI (rs,rt,imm) => (execute_SLTI rs rt imm) : M (unit) - | SLTU (rs,rt,rd) => (execute_SLTU rs rt rd) : M (unit) - | SLTIU (rs,rt,imm) => (execute_SLTIU rs rt imm) : M (unit) - | MOVN (rs,rt,rd) => (execute_MOVN rs rt rd) : M (unit) - | MOVZ (rs,rt,rd) => (execute_MOVZ rs rt rd) : M (unit) - | MFHI (rd) => (execute_MFHI rd) : M (unit) - | MFLO (rd) => (execute_MFLO rd) : M (unit) - | MTHI (rs) => (execute_MTHI rs) : M (unit) - | MTLO (rs) => (execute_MTLO rs) : M (unit) - | MUL (rs,rt,rd) => (execute_MUL rs rt rd) : M (unit) - | MULT (rs,rt) => (execute_MULT rs rt) : M (unit) - | MULTU (rs,rt) => (execute_MULTU rs rt) : M (unit) - | DMULT (rs,rt) => (execute_DMULT rs rt) : M (unit) - | DMULTU (rs,rt) => (execute_DMULTU rs rt) : M (unit) - | MADD (rs,rt) => (execute_MADD rs rt) : M (unit) - | MADDU (rs,rt) => (execute_MADDU rs rt) : M (unit) - | MSUB (rs,rt) => (execute_MSUB rs rt) : M (unit) - | MSUBU (rs,rt) => (execute_MSUBU rs rt) : M (unit) - | DIV (rs,rt) => (execute_DIV rs rt) : M (unit) - | DIVU (rs,rt) => (execute_DIVU rs rt) : M (unit) - | DDIV (rs,rt) => (execute_DDIV rs rt) : M (unit) - | DDIVU (rs,rt) => (execute_DDIVU rs rt) : M (unit) - | J (offset) => (execute_J offset) : M (unit) - | JAL (offset) => (execute_JAL offset) : M (unit) - | JR (rs) => (execute_JR rs) : M (unit) - | JALR (rs,rd) => (execute_JALR rs rd) : M (unit) - | BEQ (rs,rd,imm,ne,likely) => (execute_BEQ rs rd imm ne likely) : M (unit) - | BCMPZ (rs,imm,cmp,link,likely) => (execute_BCMPZ rs imm cmp link likely) : M (unit) - | SYSCALL (g__14) => (execute_SYSCALL g__14) : M (unit) - | BREAK (g__15) => (execute_BREAK g__15) : M (unit) - | WAIT (g__16) => (execute_WAIT g__16) : M (unit) - | TRAPREG (rs,rt,cmp) => (execute_TRAPREG rs rt cmp) : M (unit) - | TRAPIMM (rs,imm,cmp) => (execute_TRAPIMM rs imm cmp) : M (unit) - | Load (width,sign,linked,base,rt,offset) => - (execute_Load width sign linked base rt offset) : M (unit) - | Store (width,conditional,base,rt,offset) => - (execute_Store width conditional base rt offset) : M (unit) - | LWL (base,rt,offset) => (execute_LWL base rt offset) : M (unit) - | LWR (base,rt,offset) => (execute_LWR base rt offset) : M (unit) - | SWL (base,rt,offset) => (execute_SWL base rt offset) : M (unit) - | SWR (base,rt,offset) => (execute_SWR base rt offset) : M (unit) - | LDL (base,rt,offset) => (execute_LDL base rt offset) : M (unit) - | LDR (base,rt,offset) => (execute_LDR base rt offset) : M (unit) - | SDL (base,rt,offset) => (execute_SDL base rt offset) : M (unit) - | SDR (base,rt,offset) => (execute_SDR base rt offset) : M (unit) - | CACHE (base,op,imm) => (execute_CACHE base op imm) : M (unit) - | SYNC (g__17) => (execute_SYNC g__17) : M (unit) - | MFC0 (rt,rd,sel,double) => (execute_MFC0 rt rd sel double) : M (unit) - | HCF (g__18) => returnm ((execute_HCF g__18) : unit) - | MTC0 (rt,rd,sel,double) => (execute_MTC0 rt rd sel double) : M (unit) - | TLBWI (g__19) => (execute_TLBWI g__19) : M (unit) - | TLBWR (g__20) => (execute_TLBWR g__20) : M (unit) - | TLBR (g__21) => (execute_TLBR g__21) : M (unit) - | TLBP (g__22) => (execute_TLBP g__22) : M (unit) - | RDHWR (rt,rd) => (execute_RDHWR rt rd) : M (unit) - | ERET (g__23) => (execute_ERET g__23) : M (unit) - | RI (g__24) => (execute_RI g__24) : M (unit) - end. + + (match merge_var with + | DADDIU (rs,rt,imm) => (execute_DADDIU rs rt imm) : M (unit) + | DADDU (rs,rt,rd) => (execute_DADDU rs rt rd) : M (unit) + | DADDI (rs,rt,imm) => (execute_DADDI rs rt imm) : M (unit) + | DADD (rs,rt,rd) => (execute_DADD rs rt rd) : M (unit) + | ADD (rs,rt,rd) => (execute_ADD rs rt rd) : M (unit) + | ADDI (rs,rt,imm) => (execute_ADDI rs rt imm) : M (unit) + | ADDU (rs,rt,rd) => (execute_ADDU rs rt rd) : M (unit) + | ADDIU (rs,rt,imm) => (execute_ADDIU rs rt imm) : M (unit) + | DSUBU (rs,rt,rd) => (execute_DSUBU rs rt rd) : M (unit) + | DSUB (rs,rt,rd) => (execute_DSUB rs rt rd) : M (unit) + | SUB (rs,rt,rd) => (execute_SUB rs rt rd) : M (unit) + | SUBU (rs,rt,rd) => (execute_SUBU rs rt rd) : M (unit) + | AND (rs,rt,rd) => (execute_AND rs rt rd) : M (unit) + | ANDI (rs,rt,imm) => (execute_ANDI rs rt imm) : M (unit) + | OR (rs,rt,rd) => (execute_OR rs rt rd) : M (unit) + | ORI (rs,rt,imm) => (execute_ORI rs rt imm) : M (unit) + | NOR (rs,rt,rd) => (execute_NOR rs rt rd) : M (unit) + | XOR (rs,rt,rd) => (execute_XOR rs rt rd) : M (unit) + | XORI (rs,rt,imm) => (execute_XORI rs rt imm) : M (unit) + | LUI (rt,imm) => (execute_LUI rt imm) : M (unit) + | DSLL (rt,rd,sa) => (execute_DSLL rt rd sa) : M (unit) + | DSLL32 (rt,rd,sa) => (execute_DSLL32 rt rd sa) : M (unit) + | DSLLV (rs,rt,rd) => (execute_DSLLV rs rt rd) : M (unit) + | DSRA (rt,rd,sa) => (execute_DSRA rt rd sa) : M (unit) + | DSRA32 (rt,rd,sa) => (execute_DSRA32 rt rd sa) : M (unit) + | DSRAV (rs,rt,rd) => (execute_DSRAV rs rt rd) : M (unit) + | DSRL (rt,rd,sa) => (execute_DSRL rt rd sa) : M (unit) + | DSRL32 (rt,rd,sa) => (execute_DSRL32 rt rd sa) : M (unit) + | DSRLV (rs,rt,rd) => (execute_DSRLV rs rt rd) : M (unit) + | SLL (rt,rd,sa) => (execute_SLL rt rd sa) : M (unit) + | SLLV (rs,rt,rd) => (execute_SLLV rs rt rd) : M (unit) + | SRA (rt,rd,sa) => (execute_SRA rt rd sa) : M (unit) + | SRAV (rs,rt,rd) => (execute_SRAV rs rt rd) : M (unit) + | SRL (rt,rd,sa) => (execute_SRL rt rd sa) : M (unit) + | SRLV (rs,rt,rd) => (execute_SRLV rs rt rd) : M (unit) + | SLT (rs,rt,rd) => (execute_SLT rs rt rd) : M (unit) + | SLTI (rs,rt,imm) => (execute_SLTI rs rt imm) : M (unit) + | SLTU (rs,rt,rd) => (execute_SLTU rs rt rd) : M (unit) + | SLTIU (rs,rt,imm) => (execute_SLTIU rs rt imm) : M (unit) + | MOVN (rs,rt,rd) => (execute_MOVN rs rt rd) : M (unit) + | MOVZ (rs,rt,rd) => (execute_MOVZ rs rt rd) : M (unit) + | MFHI (rd) => (execute_MFHI rd) : M (unit) + | MFLO (rd) => (execute_MFLO rd) : M (unit) + | MTHI (rs) => (execute_MTHI rs) : M (unit) + | MTLO (rs) => (execute_MTLO rs) : M (unit) + | MUL (rs,rt,rd) => (execute_MUL rs rt rd) : M (unit) + | MULT (rs,rt) => (execute_MULT rs rt) : M (unit) + | MULTU (rs,rt) => (execute_MULTU rs rt) : M (unit) + | DMULT (rs,rt) => (execute_DMULT rs rt) : M (unit) + | DMULTU (rs,rt) => (execute_DMULTU rs rt) : M (unit) + | MADD (rs,rt) => (execute_MADD rs rt) : M (unit) + | MADDU (rs,rt) => (execute_MADDU rs rt) : M (unit) + | MSUB (rs,rt) => (execute_MSUB rs rt) : M (unit) + | MSUBU (rs,rt) => (execute_MSUBU rs rt) : M (unit) + | DIV (rs,rt) => (execute_DIV rs rt) : M (unit) + | DIVU (rs,rt) => (execute_DIVU rs rt) : M (unit) + | DDIV (rs,rt) => (execute_DDIV rs rt) : M (unit) + | DDIVU (rs,rt) => (execute_DDIVU rs rt) : M (unit) + | J (offset) => (execute_J offset) : M (unit) + | JAL (offset) => (execute_JAL offset) : M (unit) + | JR (rs) => (execute_JR rs) : M (unit) + | JALR (rs,rd) => (execute_JALR rs rd) : M (unit) + | BEQ (rs,rd,imm,ne,likely) => (execute_BEQ rs rd imm ne likely) : M (unit) + | BCMPZ (rs,imm,cmp,link,likely) => (execute_BCMPZ rs imm cmp link likely) : M (unit) + | SYSCALL (arg0) => (execute_SYSCALL arg0) : M (unit) + | BREAK (arg0) => (execute_BREAK arg0) : M (unit) + | WAIT (arg0) => (execute_WAIT arg0) : M (unit) + | TRAPREG (rs,rt,cmp) => (execute_TRAPREG rs rt cmp) : M (unit) + | TRAPIMM (rs,imm,cmp) => (execute_TRAPIMM rs imm cmp) : M (unit) + | Load (width,sign,linked,base,rt,offset) => + (execute_Load width sign linked base rt offset) : M (unit) + | Store (width,conditional,base,rt,offset) => + (execute_Store width conditional base rt offset) : M (unit) + | LWL (base,rt,offset) => (execute_LWL base rt offset) : M (unit) + | LWR (base,rt,offset) => (execute_LWR base rt offset) : M (unit) + | SWL (base,rt,offset) => (execute_SWL base rt offset) : M (unit) + | SWR (base,rt,offset) => (execute_SWR base rt offset) : M (unit) + | LDL (base,rt,offset) => (execute_LDL base rt offset) : M (unit) + | LDR (base,rt,offset) => (execute_LDR base rt offset) : M (unit) + | SDL (base,rt,offset) => (execute_SDL base rt offset) : M (unit) + | SDR (base,rt,offset) => (execute_SDR base rt offset) : M (unit) + | CACHE (base,op,imm) => (execute_CACHE base op imm) : M (unit) + | SYNC (arg0) => (execute_SYNC arg0) : M (unit) + | MFC0 (rt,rd,sel,double) => (execute_MFC0 rt rd sel double) : M (unit) + | HCF (arg0) => returnm ((execute_HCF arg0) : unit) + | MTC0 (rt,rd,sel,double) => (execute_MTC0 rt rd sel double) : M (unit) + | TLBWI (arg0) => (execute_TLBWI arg0) : M (unit) + | TLBWR (arg0) => (execute_TLBWR arg0) : M (unit) + | TLBR (arg0) => (execute_TLBR arg0) : M (unit) + | TLBP (arg0) => (execute_TLBP arg0) : M (unit) + | RDHWR (rt,rd) => (execute_RDHWR rt rd) : M (unit) + | ERET (arg0) => (execute_ERET arg0) : M (unit) + | RI (arg0) => (execute_RI arg0) : M (unit) + end) + : M (unit). -Definition supported_instructions (instr : ast) : option ast := Some instr. +Definition supported_instructions (instr : ast) : option ast := Some (instr). Definition initialize_registers '(tt : unit) : M (unit) := - undefined_bitvector 64 >>= fun w__0 => + + (undefined_bitvector 64) >>= fun w__0 : mword 64 => write_reg PC_ref w__0 >> - undefined_bitvector 64 >>= fun w__1 => - write_reg nextPC_ref w__1 >> - undefined_bitvector 1 >>= fun w__2 => + (undefined_bitvector 64) >>= fun w__1 : mword 64 => + write_reg NextPC_ref w__1 >> + (undefined_bitvector 1) >>= fun w__2 : mword 1 => write_reg TLBProbe_ref w__2 >> - undefined_bitvector 6 >>= fun w__3 => + (undefined_bitvector 6) >>= fun w__3 : mword 6 => write_reg TLBIndex_ref w__3 >> - undefined_bitvector 6 >>= fun w__4 => + (undefined_bitvector 6) >>= fun w__4 : mword 6 => write_reg TLBRandom_ref w__4 >> - undefined_TLBEntryLoReg tt >>= fun w__5 => + (undefined_TLBEntryLoReg tt) >>= fun w__5 : TLBEntryLoReg => write_reg TLBEntryLo0_ref w__5 >> - undefined_TLBEntryLoReg tt >>= fun w__6 => + (undefined_TLBEntryLoReg tt) >>= fun w__6 : TLBEntryLoReg => write_reg TLBEntryLo1_ref w__6 >> - undefined_ContextReg tt >>= fun w__7 => + (undefined_ContextReg tt) >>= fun w__7 : ContextReg => write_reg TLBContext_ref w__7 >> - undefined_bitvector 16 >>= fun w__8 => + (undefined_bitvector 16) >>= fun w__8 : mword 16 => write_reg TLBPageMask_ref w__8 >> - undefined_bitvector 6 >>= fun w__9 => + (undefined_bitvector 6) >>= fun w__9 : mword 6 => write_reg TLBWired_ref w__9 >> - undefined_TLBEntryHiReg tt >>= fun w__10 => + (undefined_TLBEntryHiReg tt) >>= fun w__10 : TLBEntryHiReg => write_reg TLBEntryHi_ref w__10 >> - undefined_XContextReg tt >>= fun w__11 => + (undefined_XContextReg tt) >>= fun w__11 : XContextReg => write_reg TLBXContext_ref w__11 >> - undefined_TLBEntry tt >>= fun w__12 => + (undefined_TLBEntry tt) >>= fun w__12 : TLBEntry => write_reg TLBEntry00_ref w__12 >> - undefined_TLBEntry tt >>= fun w__13 => + (undefined_TLBEntry tt) >>= fun w__13 : TLBEntry => write_reg TLBEntry01_ref w__13 >> - undefined_TLBEntry tt >>= fun w__14 => + (undefined_TLBEntry tt) >>= fun w__14 : TLBEntry => write_reg TLBEntry02_ref w__14 >> - undefined_TLBEntry tt >>= fun w__15 => + (undefined_TLBEntry tt) >>= fun w__15 : TLBEntry => write_reg TLBEntry03_ref w__15 >> - undefined_TLBEntry tt >>= fun w__16 => + (undefined_TLBEntry tt) >>= fun w__16 : TLBEntry => write_reg TLBEntry04_ref w__16 >> - undefined_TLBEntry tt >>= fun w__17 => + (undefined_TLBEntry tt) >>= fun w__17 : TLBEntry => write_reg TLBEntry05_ref w__17 >> - undefined_TLBEntry tt >>= fun w__18 => + (undefined_TLBEntry tt) >>= fun w__18 : TLBEntry => write_reg TLBEntry06_ref w__18 >> - undefined_TLBEntry tt >>= fun w__19 => + (undefined_TLBEntry tt) >>= fun w__19 : TLBEntry => write_reg TLBEntry07_ref w__19 >> - undefined_TLBEntry tt >>= fun w__20 => + (undefined_TLBEntry tt) >>= fun w__20 : TLBEntry => write_reg TLBEntry08_ref w__20 >> - undefined_TLBEntry tt >>= fun w__21 => + (undefined_TLBEntry tt) >>= fun w__21 : TLBEntry => write_reg TLBEntry09_ref w__21 >> - undefined_TLBEntry tt >>= fun w__22 => + (undefined_TLBEntry tt) >>= fun w__22 : TLBEntry => write_reg TLBEntry10_ref w__22 >> - undefined_TLBEntry tt >>= fun w__23 => + (undefined_TLBEntry tt) >>= fun w__23 : TLBEntry => write_reg TLBEntry11_ref w__23 >> - undefined_TLBEntry tt >>= fun w__24 => + (undefined_TLBEntry tt) >>= fun w__24 : TLBEntry => write_reg TLBEntry12_ref w__24 >> - undefined_TLBEntry tt >>= fun w__25 => + (undefined_TLBEntry tt) >>= fun w__25 : TLBEntry => write_reg TLBEntry13_ref w__25 >> - undefined_TLBEntry tt >>= fun w__26 => + (undefined_TLBEntry tt) >>= fun w__26 : TLBEntry => write_reg TLBEntry14_ref w__26 >> - undefined_TLBEntry tt >>= fun w__27 => + (undefined_TLBEntry tt) >>= fun w__27 : TLBEntry => write_reg TLBEntry15_ref w__27 >> - undefined_TLBEntry tt >>= fun w__28 => + (undefined_TLBEntry tt) >>= fun w__28 : TLBEntry => write_reg TLBEntry16_ref w__28 >> - undefined_TLBEntry tt >>= fun w__29 => + (undefined_TLBEntry tt) >>= fun w__29 : TLBEntry => write_reg TLBEntry17_ref w__29 >> - undefined_TLBEntry tt >>= fun w__30 => + (undefined_TLBEntry tt) >>= fun w__30 : TLBEntry => write_reg TLBEntry18_ref w__30 >> - undefined_TLBEntry tt >>= fun w__31 => + (undefined_TLBEntry tt) >>= fun w__31 : TLBEntry => write_reg TLBEntry19_ref w__31 >> - undefined_TLBEntry tt >>= fun w__32 => + (undefined_TLBEntry tt) >>= fun w__32 : TLBEntry => write_reg TLBEntry20_ref w__32 >> - undefined_TLBEntry tt >>= fun w__33 => + (undefined_TLBEntry tt) >>= fun w__33 : TLBEntry => write_reg TLBEntry21_ref w__33 >> - undefined_TLBEntry tt >>= fun w__34 => + (undefined_TLBEntry tt) >>= fun w__34 : TLBEntry => write_reg TLBEntry22_ref w__34 >> - undefined_TLBEntry tt >>= fun w__35 => + (undefined_TLBEntry tt) >>= fun w__35 : TLBEntry => write_reg TLBEntry23_ref w__35 >> - undefined_TLBEntry tt >>= fun w__36 => + (undefined_TLBEntry tt) >>= fun w__36 : TLBEntry => write_reg TLBEntry24_ref w__36 >> - undefined_TLBEntry tt >>= fun w__37 => + (undefined_TLBEntry tt) >>= fun w__37 : TLBEntry => write_reg TLBEntry25_ref w__37 >> - undefined_TLBEntry tt >>= fun w__38 => + (undefined_TLBEntry tt) >>= fun w__38 : TLBEntry => write_reg TLBEntry26_ref w__38 >> - undefined_TLBEntry tt >>= fun w__39 => + (undefined_TLBEntry tt) >>= fun w__39 : TLBEntry => write_reg TLBEntry27_ref w__39 >> - undefined_TLBEntry tt >>= fun w__40 => + (undefined_TLBEntry tt) >>= fun w__40 : TLBEntry => write_reg TLBEntry28_ref w__40 >> - undefined_TLBEntry tt >>= fun w__41 => + (undefined_TLBEntry tt) >>= fun w__41 : TLBEntry => write_reg TLBEntry29_ref w__41 >> - undefined_TLBEntry tt >>= fun w__42 => + (undefined_TLBEntry tt) >>= fun w__42 : TLBEntry => write_reg TLBEntry30_ref w__42 >> - undefined_TLBEntry tt >>= fun w__43 => + (undefined_TLBEntry tt) >>= fun w__43 : TLBEntry => write_reg TLBEntry31_ref w__43 >> - undefined_TLBEntry tt >>= fun w__44 => + (undefined_TLBEntry tt) >>= fun w__44 : TLBEntry => write_reg TLBEntry32_ref w__44 >> - undefined_TLBEntry tt >>= fun w__45 => + (undefined_TLBEntry tt) >>= fun w__45 : TLBEntry => write_reg TLBEntry33_ref w__45 >> - undefined_TLBEntry tt >>= fun w__46 => + (undefined_TLBEntry tt) >>= fun w__46 : TLBEntry => write_reg TLBEntry34_ref w__46 >> - undefined_TLBEntry tt >>= fun w__47 => + (undefined_TLBEntry tt) >>= fun w__47 : TLBEntry => write_reg TLBEntry35_ref w__47 >> - undefined_TLBEntry tt >>= fun w__48 => + (undefined_TLBEntry tt) >>= fun w__48 : TLBEntry => write_reg TLBEntry36_ref w__48 >> - undefined_TLBEntry tt >>= fun w__49 => + (undefined_TLBEntry tt) >>= fun w__49 : TLBEntry => write_reg TLBEntry37_ref w__49 >> - undefined_TLBEntry tt >>= fun w__50 => + (undefined_TLBEntry tt) >>= fun w__50 : TLBEntry => write_reg TLBEntry38_ref w__50 >> - undefined_TLBEntry tt >>= fun w__51 => + (undefined_TLBEntry tt) >>= fun w__51 : TLBEntry => write_reg TLBEntry39_ref w__51 >> - undefined_TLBEntry tt >>= fun w__52 => + (undefined_TLBEntry tt) >>= fun w__52 : TLBEntry => write_reg TLBEntry40_ref w__52 >> - undefined_TLBEntry tt >>= fun w__53 => + (undefined_TLBEntry tt) >>= fun w__53 : TLBEntry => write_reg TLBEntry41_ref w__53 >> - undefined_TLBEntry tt >>= fun w__54 => + (undefined_TLBEntry tt) >>= fun w__54 : TLBEntry => write_reg TLBEntry42_ref w__54 >> - undefined_TLBEntry tt >>= fun w__55 => + (undefined_TLBEntry tt) >>= fun w__55 : TLBEntry => write_reg TLBEntry43_ref w__55 >> - undefined_TLBEntry tt >>= fun w__56 => + (undefined_TLBEntry tt) >>= fun w__56 : TLBEntry => write_reg TLBEntry44_ref w__56 >> - undefined_TLBEntry tt >>= fun w__57 => + (undefined_TLBEntry tt) >>= fun w__57 : TLBEntry => write_reg TLBEntry45_ref w__57 >> - undefined_TLBEntry tt >>= fun w__58 => + (undefined_TLBEntry tt) >>= fun w__58 : TLBEntry => write_reg TLBEntry46_ref w__58 >> - undefined_TLBEntry tt >>= fun w__59 => + (undefined_TLBEntry tt) >>= fun w__59 : TLBEntry => write_reg TLBEntry47_ref w__59 >> - undefined_TLBEntry tt >>= fun w__60 => + (undefined_TLBEntry tt) >>= fun w__60 : TLBEntry => write_reg TLBEntry48_ref w__60 >> - undefined_TLBEntry tt >>= fun w__61 => + (undefined_TLBEntry tt) >>= fun w__61 : TLBEntry => write_reg TLBEntry49_ref w__61 >> - undefined_TLBEntry tt >>= fun w__62 => + (undefined_TLBEntry tt) >>= fun w__62 : TLBEntry => write_reg TLBEntry50_ref w__62 >> - undefined_TLBEntry tt >>= fun w__63 => + (undefined_TLBEntry tt) >>= fun w__63 : TLBEntry => write_reg TLBEntry51_ref w__63 >> - undefined_TLBEntry tt >>= fun w__64 => + (undefined_TLBEntry tt) >>= fun w__64 : TLBEntry => write_reg TLBEntry52_ref w__64 >> - undefined_TLBEntry tt >>= fun w__65 => + (undefined_TLBEntry tt) >>= fun w__65 : TLBEntry => write_reg TLBEntry53_ref w__65 >> - undefined_TLBEntry tt >>= fun w__66 => + (undefined_TLBEntry tt) >>= fun w__66 : TLBEntry => write_reg TLBEntry54_ref w__66 >> - undefined_TLBEntry tt >>= fun w__67 => + (undefined_TLBEntry tt) >>= fun w__67 : TLBEntry => write_reg TLBEntry55_ref w__67 >> - undefined_TLBEntry tt >>= fun w__68 => + (undefined_TLBEntry tt) >>= fun w__68 : TLBEntry => write_reg TLBEntry56_ref w__68 >> - undefined_TLBEntry tt >>= fun w__69 => + (undefined_TLBEntry tt) >>= fun w__69 : TLBEntry => write_reg TLBEntry57_ref w__69 >> - undefined_TLBEntry tt >>= fun w__70 => + (undefined_TLBEntry tt) >>= fun w__70 : TLBEntry => write_reg TLBEntry58_ref w__70 >> - undefined_TLBEntry tt >>= fun w__71 => + (undefined_TLBEntry tt) >>= fun w__71 : TLBEntry => write_reg TLBEntry59_ref w__71 >> - undefined_TLBEntry tt >>= fun w__72 => + (undefined_TLBEntry tt) >>= fun w__72 : TLBEntry => write_reg TLBEntry60_ref w__72 >> - undefined_TLBEntry tt >>= fun w__73 => + (undefined_TLBEntry tt) >>= fun w__73 : TLBEntry => write_reg TLBEntry61_ref w__73 >> - undefined_TLBEntry tt >>= fun w__74 => + (undefined_TLBEntry tt) >>= fun w__74 : TLBEntry => write_reg TLBEntry62_ref w__74 >> - undefined_TLBEntry tt >>= fun w__75 => + (undefined_TLBEntry tt) >>= fun w__75 : TLBEntry => write_reg TLBEntry63_ref w__75 >> - undefined_bitvector 32 >>= fun w__76 => + (undefined_bitvector 32) >>= fun w__76 : mword 32 => write_reg CP0Compare_ref w__76 >> - undefined_CauseReg tt >>= fun w__77 => + (undefined_CauseReg tt) >>= fun w__77 : CauseReg => write_reg CP0Cause_ref w__77 >> - undefined_bitvector 64 >>= fun w__78 => + (undefined_bitvector 64) >>= fun w__78 : mword 64 => write_reg CP0EPC_ref w__78 >> - undefined_bitvector 64 >>= fun w__79 => + (undefined_bitvector 64) >>= fun w__79 : mword 64 => write_reg CP0ErrorEPC_ref w__79 >> - undefined_bitvector 1 >>= fun w__80 => + (undefined_bitvector 1) >>= fun w__80 : mword 1 => write_reg CP0LLBit_ref w__80 >> - undefined_bitvector 64 >>= fun w__81 => + (undefined_bitvector 64) >>= fun w__81 : mword 64 => write_reg CP0LLAddr_ref w__81 >> - undefined_bitvector 64 >>= fun w__82 => + (undefined_bitvector 64) >>= fun w__82 : mword 64 => write_reg CP0BadVAddr_ref w__82 >> - undefined_bitvector 32 >>= fun w__83 => - write_reg CP0Count_ref w__83 >> - undefined_bitvector 32 >>= fun w__84 => - write_reg CP0HWREna_ref w__84 >> - undefined_bitvector 64 >>= fun w__85 => - write_reg CP0UserLocal_ref w__85 >> - undefined_bitvector 3 >>= fun w__86 => - write_reg CP0ConfigK0_ref w__86 >> - undefined_StatusReg tt >>= fun w__87 => - write_reg CP0Status_ref w__87 >> - undefined_bitvector 1 >>= fun w__88 => - write_reg branchPending_ref w__88 >> - undefined_bitvector 1 >>= fun w__89 => - write_reg inBranchDelay_ref w__89 >> - undefined_bitvector 64 >>= fun w__90 => - write_reg delayedPC_ref w__90 >> - undefined_bitvector 64 >>= fun w__91 => - write_reg HI_ref w__91 >> - undefined_bitvector 64 >>= fun w__92 => - write_reg LO_ref w__92 >> - undefined_bitvector 64 >>= fun w__93 => - undefined_vector 32 w__93 >>= fun w__94 => - write_reg GPR_ref w__94 >> - undefined_bitvector 8 >>= fun w__95 => - write_reg UART_WDATA_ref w__95 >> - undefined_bitvector 1 >>= fun w__96 => - write_reg UART_WRITTEN_ref w__96 >> - undefined_bitvector 8 >>= fun w__97 => - write_reg UART_RDATA_ref w__97 >> - undefined_bitvector 1 >>= fun w__98 => write_reg UART_RVALID_ref w__98 : M (unit). + (undefined_bitvector 32) >>= fun w__83 : mword 32 => + write_reg CurrentInstrBits_ref w__83 >> + (undefined_bitvector 32) >>= fun w__84 : mword 32 => + write_reg LastInstrBits_ref w__84 >> + (undefined_bitvector 32) >>= fun w__85 : mword 32 => + write_reg CP0BadInstr_ref w__85 >> + (undefined_bitvector 32) >>= fun w__86 : mword 32 => + write_reg CP0BadInstrP_ref w__86 >> + (undefined_bitvector 32) >>= fun w__87 : mword 32 => + write_reg CP0Count_ref w__87 >> + (undefined_bitvector 32) >>= fun w__88 : mword 32 => + write_reg CP0HWREna_ref w__88 >> + (undefined_bitvector 64) >>= fun w__89 : mword 64 => + write_reg CP0UserLocal_ref w__89 >> + (undefined_bitvector 3) >>= fun w__90 : mword 3 => + write_reg CP0ConfigK0_ref w__90 >> + (undefined_StatusReg tt) >>= fun w__91 : StatusReg => + write_reg CP0Status_ref w__91 >> + (undefined_bitvector 1) >>= fun w__92 : mword 1 => + write_reg NextInBranchDelay_ref w__92 >> + (undefined_bitvector 1) >>= fun w__93 : mword 1 => + write_reg InBranchDelay_ref w__93 >> + (undefined_bitvector 1) >>= fun w__94 : mword 1 => + write_reg BranchPending_ref w__94 >> + (undefined_bitvector 64) >>= fun w__95 : mword 64 => + write_reg DelayedPC_ref w__95 >> + (undefined_bitvector 64) >>= fun w__96 : mword 64 => + write_reg HI_ref w__96 >> + (undefined_bitvector 64) >>= fun w__97 : mword 64 => + write_reg LO_ref w__97 >> + (undefined_bitvector 64) >>= fun w__98 : mword 64 => + (undefined_vector 32 w__98) >>= fun w__99 : vec (mword 64) 32 => + write_reg GPR_ref w__99 >> + (undefined_bitvector 8) >>= fun w__100 : mword 8 => + write_reg UART_WDATA_ref w__100 >> + (undefined_bitvector 1) >>= fun w__101 : mword 1 => + write_reg UART_WRITTEN_ref w__101 >> + (undefined_bitvector 8) >>= fun w__102 : mword 8 => + write_reg UART_RDATA_ref w__102 >> + (undefined_bitvector 1) >>= fun w__103 : mword 1 => write_reg UART_RVALID_ref w__103 : M (unit). Definition initial_regstate : regstate := {| UART_RVALID := (vec_of_bits [B0] : mword 1); @@ -5003,14 +5842,15 @@ Definition initial_regstate : regstate := B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0] : mword 64); - delayedPC := + DelayedPC := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0] : mword 64); - inBranchDelay := (vec_of_bits [B0] : mword 1); - branchPending := (vec_of_bits [B0] : mword 1); + BranchPending := (vec_of_bits [B0] : mword 1); + InBranchDelay := (vec_of_bits [B0] : mword 1); + NextInBranchDelay := (vec_of_bits [B0] : mword 1); CP0Status := ({| StatusReg_StatusReg_chunk_0 := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -5031,6 +5871,22 @@ Definition initial_regstate : regstate := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 32); + CP0BadInstrP := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CP0BadInstr := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + LastInstrBits := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); + CurrentInstrBits := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32); CP0BadVAddr := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -5873,7 +6729,7 @@ Definition initial_regstate : regstate := TLBRandom := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); TLBIndex := (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6); TLBProbe := (vec_of_bits [B0] : mword 1); - nextPC := + NextPC := (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; @@ -5885,6 +6741,6 @@ Definition initial_regstate : regstate := B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; B0] : mword 64) |}. - +Hint Unfold initial_regstate : sail. End Content. diff --git a/snapshots/coq/mips/mips_extras.v b/snapshots/coq/cheri-mips/mips_extras.v index cc905f11..cdb9956d 100644 --- a/snapshots/coq/mips/mips_extras.v +++ b/snapshots/coq/cheri-mips/mips_extras.v @@ -140,10 +140,10 @@ Definition eq_bit (x : bitU) (y : bitU) : bool := Require Import Zeuclid. Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}. -refine (build_ex (ZEuclid.modulo m n)). +refine (existT _ (ZEuclid.modulo m n) _). constructor. destruct H. -assert (Zabs n = n). { rewrite Zabs_eq; auto with zarith. } +assert (Z.abs n = n). { rewrite Z.abs_eq; auto with zarith. } rewrite <- H at 3. lapply (ZEuclid.mod_always_pos m n); omega. Qed. @@ -160,3 +160,32 @@ Definition prerr_string (_:string) : unit := tt. Definition putchar {T} (_:T) : unit := tt. Require DecimalString. Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z). + +Lemma __MIPS_read_lemma : forall width, 8 * width = 8 * (8 * width ÷ 8). +intros. +rewrite Z.mul_comm. +rewrite Z.quot_mul; auto with zarith. +Qed. +Hint Resolve __MIPS_read_lemma : sail. + +Lemma MEMr_wrapper_lemma : forall size : Z, 8 * size = 8 * (8 * (8 * size ÷ 8) ÷ 8). +intros. +rewrite Z.mul_comm. +rewrite Z.quot_mul; auto with zarith. +rewrite Z.mul_comm with (m := size). +rewrite Z.quot_mul; auto with zarith. +Qed. +Hint Resolve MEMr_wrapper_lemma : sail. + +Lemma getCapOffset_lemma {x0 x1 x2 x : Z} : + 0 <= x0 <= 18446744073709551616 - 1 -> + 0 <= x1 <= 18446744073709551616 - 1 -> + 18446744073709551616 <= x2 <= 18446744073709551616 -> + x = ZEuclid.modulo (x0 - x1) x2 -> + 0 <= x <= 18446744073709551616 - 1. +intros. +match goal with H:context [ZEuclid.modulo ?X ?Y] |- _ => pose proof (ZEuclid.mod_always_pos X Y) end. +omega with Z. +Qed. +Hint Resolve getCapOffset_lemma : sail. + diff --git a/snapshots/coq/cheri-mips/mips_types.v b/snapshots/coq/cheri-mips/mips_types.v new file mode 100644 index 00000000..36c5e40b --- /dev/null +++ b/snapshots/coq/cheri-mips/mips_types.v @@ -0,0 +1,1549 @@ +(*Generated by Sail from mips.*) +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_string. +Require Import Sail2_real. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import Sail2_state. + + +Definition bits (n : Z) : Type := mword n. + +Inductive exception := + ISAException : unit -> exception + | Error_not_implemented : string -> exception + | Error_misaligned_access : unit -> exception + | Error_EBREAK : unit -> exception + | Error_internal_error : unit -> exception. +Arguments exception : clear implicits. + + + +Record CauseReg := { CauseReg_CauseReg_chunk_0 : mword 32; }. +Notation "{[ r 'with' 'CauseReg_CauseReg_chunk_0' := e ]}" := ({| CauseReg_CauseReg_chunk_0 := e |}). + +Record StatusReg := { StatusReg_StatusReg_chunk_0 : mword 32; }. +Notation "{[ r 'with' 'StatusReg_StatusReg_chunk_0' := e ]}" := ({| StatusReg_StatusReg_chunk_0 := e |}). + +Record TLBEntryLoReg := { TLBEntryLoReg_TLBEntryLoReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'TLBEntryLoReg_TLBEntryLoReg_chunk_0' := e ]}" := ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := e |}). + +Record TLBEntryHiReg := { TLBEntryHiReg_TLBEntryHiReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'TLBEntryHiReg_TLBEntryHiReg_chunk_0' := e ]}" := ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := e |}). + +Record ContextReg := { ContextReg_ContextReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'ContextReg_ContextReg_chunk_0' := e ]}" := ({| ContextReg_ContextReg_chunk_0 := e |}). + +Record XContextReg := { XContextReg_XContextReg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'XContextReg_XContextReg_chunk_0' := e ]}" := ({| XContextReg_XContextReg_chunk_0 := e |}). + +Definition TLBIndexT : Type := bits 6. + +Record TLBEntry := { TLBEntry_TLBEntry_chunk_1 : mword 53; TLBEntry_TLBEntry_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_1' := e ]}" := ({| TLBEntry_TLBEntry_chunk_1 := e; TLBEntry_TLBEntry_chunk_0 := TLBEntry_TLBEntry_chunk_0 r |}). +Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_0' := e ]}" := ({| TLBEntry_TLBEntry_chunk_0 := e; TLBEntry_TLBEntry_chunk_1 := TLBEntry_TLBEntry_chunk_1 r |}). + +Inductive Exception := + Interrupt + | TLBMod + | TLBL + | TLBS + | AdEL + | AdES + | Sys + | Bp + | ResI + | CpU + | Ov + | Tr + | C2E + | C2Trap + | XTLBRefillL + | XTLBRefillS + | XTLBInvL + | XTLBInvS + | MCheck. +Scheme Equality for Exception. +Instance Decidable_eq_Exception : +forall (x y : Exception), Decidable (x = y) := +Decidable_eq_from_dec Exception_eq_dec. + + +Inductive MemAccessType := Instruction | LoadData | StoreData. +Scheme Equality for MemAccessType. +Instance Decidable_eq_MemAccessType : +forall (x y : MemAccessType), Decidable (x = y) := +Decidable_eq_from_dec MemAccessType_eq_dec. + + +Inductive AccessLevel := User | Supervisor | Kernel. +Scheme Equality for AccessLevel. +Instance Decidable_eq_AccessLevel : +forall (x y : AccessLevel), Decidable (x = y) := +Decidable_eq_from_dec AccessLevel_eq_dec. + + +Definition regno : Type := bits 5. + +Definition imm16 : Type := bits 16. + +Definition regregreg : Type := (regno * regno * regno). + +Definition regregimm16 : Type := (regno * regno * imm16). + +Inductive decode_failure := + no_matching_pattern | unsupported_instruction | illegal_instruction | internal_error. +Scheme Equality for decode_failure. +Instance Decidable_eq_decode_failure : +forall (x y : decode_failure), Decidable (x = y) := +Decidable_eq_from_dec decode_failure_eq_dec. + + +Inductive Comparison := EQ' | NE | GE | GEU | GT' | LE | LT' | LTU. +Scheme Equality for Comparison. +Instance Decidable_eq_Comparison : +forall (x y : Comparison), Decidable (x = y) := +Decidable_eq_from_dec Comparison_eq_dec. + + +Inductive WordType := B | H | W | D. +Scheme Equality for WordType. +Instance Decidable_eq_WordType : +forall (x y : WordType), Decidable (x = y) := +Decidable_eq_from_dec WordType_eq_dec. + + +Inductive WordTypeUnaligned := WL | WR | DL | DR. +Scheme Equality for WordTypeUnaligned. +Instance Decidable_eq_WordTypeUnaligned : +forall (x y : WordTypeUnaligned), Decidable (x = y) := +Decidable_eq_from_dec WordTypeUnaligned_eq_dec. + + +Inductive ast := + DADDIU : (regno * regno * imm16) -> ast + | DADDU : (regno * regno * regno) -> ast + | DADDI : (regno * regno * bits 16) -> ast + | DADD : (regno * regno * regno) -> ast + | ADD : (regno * regno * regno) -> ast + | ADDI : (regno * regno * bits 16) -> ast + | ADDU : (regno * regno * regno) -> ast + | ADDIU : (regno * regno * bits 16) -> ast + | DSUBU : (regno * regno * regno) -> ast + | DSUB : (regno * regno * regno) -> ast + | SUB : (regno * regno * regno) -> ast + | SUBU : (regno * regno * regno) -> ast + | AND : (regno * regno * regno) -> ast + | ANDI : (regno * regno * bits 16) -> ast + | OR : (regno * regno * regno) -> ast + | ORI : (regno * regno * bits 16) -> ast + | NOR : (regno * regno * regno) -> ast + | XOR : (regno * regno * regno) -> ast + | XORI : (regno * regno * bits 16) -> ast + | LUI : (regno * imm16) -> ast + | DSLL : (regno * regno * regno) -> ast + | DSLL32 : (regno * regno * regno) -> ast + | DSLLV : (regno * regno * regno) -> ast + | DSRA : (regno * regno * regno) -> ast + | DSRA32 : (regno * regno * regno) -> ast + | DSRAV : (regno * regno * regno) -> ast + | DSRL : (regno * regno * regno) -> ast + | DSRL32 : (regno * regno * regno) -> ast + | DSRLV : (regno * regno * regno) -> ast + | SLL : (regno * regno * regno) -> ast + | SLLV : (regno * regno * regno) -> ast + | SRA : (regno * regno * regno) -> ast + | SRAV : (regno * regno * regno) -> ast + | SRL : (regno * regno * regno) -> ast + | SRLV : (regno * regno * regno) -> ast + | SLT : (regno * regno * regno) -> ast + | SLTI : (regno * regno * bits 16) -> ast + | SLTU : (regno * regno * regno) -> ast + | SLTIU : (regno * regno * bits 16) -> ast + | MOVN : (regno * regno * regno) -> ast + | MOVZ : (regno * regno * regno) -> ast + | MFHI : regno -> ast + | MFLO : regno -> ast + | MTHI : regno -> ast + | MTLO : regno -> ast + | MUL : (regno * regno * regno) -> ast + | MULT : (regno * regno) -> ast + | MULTU : (regno * regno) -> ast + | DMULT : (regno * regno) -> ast + | DMULTU : (regno * regno) -> ast + | MADD : (regno * regno) -> ast + | MADDU : (regno * regno) -> ast + | MSUB : (regno * regno) -> ast + | MSUBU : (regno * regno) -> ast + | DIV : (regno * regno) -> ast + | DIVU : (regno * regno) -> ast + | DDIV : (regno * regno) -> ast + | DDIVU : (regno * regno) -> ast + | J : bits 26 -> ast + | JAL : bits 26 -> ast + | JR : regno -> ast + | JALR : (regno * regno) -> ast + | BEQ : (regno * regno * imm16 * bool * bool) -> ast + | BCMPZ : (regno * imm16 * Comparison * bool * bool) -> ast + | SYSCALL : unit -> ast + | BREAK : unit -> ast + | WAIT : unit -> ast + | TRAPREG : (regno * regno * Comparison) -> ast + | TRAPIMM : (regno * imm16 * Comparison) -> ast + | Load : (WordType * bool * bool * regno * regno * imm16) -> ast + | Store : (WordType * bool * regno * regno * imm16) -> ast + | LWL : (regno * regno * bits 16) -> ast + | LWR : (regno * regno * bits 16) -> ast + | SWL : (regno * regno * bits 16) -> ast + | SWR : (regno * regno * bits 16) -> ast + | LDL : (regno * regno * bits 16) -> ast + | LDR : (regno * regno * bits 16) -> ast + | SDL : (regno * regno * bits 16) -> ast + | SDR : (regno * regno * bits 16) -> ast + | CACHE : (regno * regno * bits 16) -> ast + | SYNC : unit -> ast + | MFC0 : (regno * regno * bits 3 * bool) -> ast + | HCF : unit -> ast + | MTC0 : (regno * regno * bits 3 * bool) -> ast + | TLBWI : unit -> ast + | TLBWR : unit -> ast + | TLBR : unit -> ast + | TLBP : unit -> ast + | RDHWR : (regno * regno) -> ast + | ERET : unit -> ast + | RI : unit -> ast. +Arguments ast : clear implicits. + + + +Inductive register_value := + Regval_vector : (Z * bool * list register_value) -> register_value + | Regval_list : list register_value -> register_value + | Regval_option : option register_value -> register_value + | Regval_CauseReg : CauseReg -> register_value + | Regval_ContextReg : ContextReg -> register_value + | Regval_StatusReg : StatusReg -> register_value + | Regval_TLBEntry : TLBEntry -> register_value + | Regval_TLBEntryHiReg : TLBEntryHiReg -> register_value + | Regval_TLBEntryLoReg : TLBEntryLoReg -> register_value + | Regval_XContextReg : XContextReg -> register_value + | Regval_vector_16_dec_bit : mword 16 -> register_value + | Regval_vector_1_dec_bit : mword 1 -> register_value + | Regval_vector_32_dec_bit : mword 32 -> register_value + | Regval_vector_3_dec_bit : mword 3 -> register_value + | Regval_vector_64_dec_bit : mword 64 -> register_value + | Regval_vector_6_dec_bit : mword 6 -> register_value + | Regval_vector_8_dec_bit : mword 8 -> register_value. +Arguments register_value : clear implicits. + + + +Record regstate := + { UART_RVALID : mword 1; + UART_RDATA : mword 8; + UART_WRITTEN : mword 1; + UART_WDATA : mword 8; + GPR : vec (mword 64) 32; + LO : mword 64; + HI : mword 64; + DelayedPC : mword 64; + BranchPending : mword 1; + InBranchDelay : mword 1; + NextInBranchDelay : mword 1; + CP0Status : StatusReg; + CP0ConfigK0 : mword 3; + CP0UserLocal : mword 64; + CP0HWREna : mword 32; + CP0Count : mword 32; + CP0BadInstrP : mword 32; + CP0BadInstr : mword 32; + LastInstrBits : mword 32; + CurrentInstrBits : mword 32; + CP0BadVAddr : mword 64; + CP0LLAddr : mword 64; + CP0LLBit : mword 1; + CP0ErrorEPC : mword 64; + CP0EPC : mword 64; + CP0Cause : CauseReg; + CP0Compare : mword 32; + TLBEntry63 : TLBEntry; + TLBEntry62 : TLBEntry; + TLBEntry61 : TLBEntry; + TLBEntry60 : TLBEntry; + TLBEntry59 : TLBEntry; + TLBEntry58 : TLBEntry; + TLBEntry57 : TLBEntry; + TLBEntry56 : TLBEntry; + TLBEntry55 : TLBEntry; + TLBEntry54 : TLBEntry; + TLBEntry53 : TLBEntry; + TLBEntry52 : TLBEntry; + TLBEntry51 : TLBEntry; + TLBEntry50 : TLBEntry; + TLBEntry49 : TLBEntry; + TLBEntry48 : TLBEntry; + TLBEntry47 : TLBEntry; + TLBEntry46 : TLBEntry; + TLBEntry45 : TLBEntry; + TLBEntry44 : TLBEntry; + TLBEntry43 : TLBEntry; + TLBEntry42 : TLBEntry; + TLBEntry41 : TLBEntry; + TLBEntry40 : TLBEntry; + TLBEntry39 : TLBEntry; + TLBEntry38 : TLBEntry; + TLBEntry37 : TLBEntry; + TLBEntry36 : TLBEntry; + TLBEntry35 : TLBEntry; + TLBEntry34 : TLBEntry; + TLBEntry33 : TLBEntry; + TLBEntry32 : TLBEntry; + TLBEntry31 : TLBEntry; + TLBEntry30 : TLBEntry; + TLBEntry29 : TLBEntry; + TLBEntry28 : TLBEntry; + TLBEntry27 : TLBEntry; + TLBEntry26 : TLBEntry; + TLBEntry25 : TLBEntry; + TLBEntry24 : TLBEntry; + TLBEntry23 : TLBEntry; + TLBEntry22 : TLBEntry; + TLBEntry21 : TLBEntry; + TLBEntry20 : TLBEntry; + TLBEntry19 : TLBEntry; + TLBEntry18 : TLBEntry; + TLBEntry17 : TLBEntry; + TLBEntry16 : TLBEntry; + TLBEntry15 : TLBEntry; + TLBEntry14 : TLBEntry; + TLBEntry13 : TLBEntry; + TLBEntry12 : TLBEntry; + TLBEntry11 : TLBEntry; + TLBEntry10 : TLBEntry; + TLBEntry09 : TLBEntry; + TLBEntry08 : TLBEntry; + TLBEntry07 : TLBEntry; + TLBEntry06 : TLBEntry; + TLBEntry05 : TLBEntry; + TLBEntry04 : TLBEntry; + TLBEntry03 : TLBEntry; + TLBEntry02 : TLBEntry; + TLBEntry01 : TLBEntry; + TLBEntry00 : TLBEntry; + TLBXContext : XContextReg; + TLBEntryHi : TLBEntryHiReg; + TLBWired : mword 6; + TLBPageMask : mword 16; + TLBContext : ContextReg; + TLBEntryLo1 : TLBEntryLoReg; + TLBEntryLo0 : TLBEntryLoReg; + TLBRandom : mword 6; + TLBIndex : mword 6; + TLBProbe : mword 1; + NextPC : mword 64; + PC : mword 64; }. +Notation "{[ r 'with' 'UART_RVALID' := e ]}" := ({| UART_RVALID := e; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_RDATA' := e ]}" := ({| UART_RDATA := e; UART_RVALID := UART_RVALID r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_WRITTEN' := e ]}" := ({| UART_WRITTEN := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'UART_WDATA' := e ]}" := ({| UART_WDATA := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'GPR' := e ]}" := ({| GPR := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'LO' := e ]}" := ({| LO := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'HI' := e ]}" := ({| HI := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'DelayedPC' := e ]}" := ({| DelayedPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'BranchPending' := e ]}" := ({| BranchPending := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'InBranchDelay' := e ]}" := ({| InBranchDelay := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'NextInBranchDelay' := e ]}" := ({| NextInBranchDelay := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Status' := e ]}" := ({| CP0Status := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0ConfigK0' := e ]}" := ({| CP0ConfigK0 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0UserLocal' := e ]}" := ({| CP0UserLocal := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0HWREna' := e ]}" := ({| CP0HWREna := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Count' := e ]}" := ({| CP0Count := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0BadInstrP' := e ]}" := ({| CP0BadInstrP := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0BadInstr' := e ]}" := ({| CP0BadInstr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'LastInstrBits' := e ]}" := ({| LastInstrBits := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CurrentInstrBits' := e ]}" := ({| CurrentInstrBits := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0BadVAddr' := e ]}" := ({| CP0BadVAddr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0LLAddr' := e ]}" := ({| CP0LLAddr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0LLBit' := e ]}" := ({| CP0LLBit := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0ErrorEPC' := e ]}" := ({| CP0ErrorEPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0EPC' := e ]}" := ({| CP0EPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Cause' := e ]}" := ({| CP0Cause := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'CP0Compare' := e ]}" := ({| CP0Compare := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry63' := e ]}" := ({| TLBEntry63 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry62' := e ]}" := ({| TLBEntry62 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry61' := e ]}" := ({| TLBEntry61 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry60' := e ]}" := ({| TLBEntry60 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry59' := e ]}" := ({| TLBEntry59 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry58' := e ]}" := ({| TLBEntry58 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry57' := e ]}" := ({| TLBEntry57 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry56' := e ]}" := ({| TLBEntry56 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry55' := e ]}" := ({| TLBEntry55 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry54' := e ]}" := ({| TLBEntry54 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry53' := e ]}" := ({| TLBEntry53 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry52' := e ]}" := ({| TLBEntry52 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry51' := e ]}" := ({| TLBEntry51 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry50' := e ]}" := ({| TLBEntry50 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry49' := e ]}" := ({| TLBEntry49 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry48' := e ]}" := ({| TLBEntry48 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry47' := e ]}" := ({| TLBEntry47 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry46' := e ]}" := ({| TLBEntry46 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry45' := e ]}" := ({| TLBEntry45 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry44' := e ]}" := ({| TLBEntry44 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry43' := e ]}" := ({| TLBEntry43 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry42' := e ]}" := ({| TLBEntry42 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry41' := e ]}" := ({| TLBEntry41 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry40' := e ]}" := ({| TLBEntry40 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry39' := e ]}" := ({| TLBEntry39 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry38' := e ]}" := ({| TLBEntry38 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry37' := e ]}" := ({| TLBEntry37 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry36' := e ]}" := ({| TLBEntry36 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry35' := e ]}" := ({| TLBEntry35 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry34' := e ]}" := ({| TLBEntry34 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry33' := e ]}" := ({| TLBEntry33 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry32' := e ]}" := ({| TLBEntry32 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry31' := e ]}" := ({| TLBEntry31 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry30' := e ]}" := ({| TLBEntry30 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry29' := e ]}" := ({| TLBEntry29 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry28' := e ]}" := ({| TLBEntry28 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry27' := e ]}" := ({| TLBEntry27 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry26' := e ]}" := ({| TLBEntry26 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry25' := e ]}" := ({| TLBEntry25 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry24' := e ]}" := ({| TLBEntry24 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry23' := e ]}" := ({| TLBEntry23 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry22' := e ]}" := ({| TLBEntry22 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry21' := e ]}" := ({| TLBEntry21 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry20' := e ]}" := ({| TLBEntry20 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry19' := e ]}" := ({| TLBEntry19 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry18' := e ]}" := ({| TLBEntry18 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry17' := e ]}" := ({| TLBEntry17 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry16' := e ]}" := ({| TLBEntry16 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry15' := e ]}" := ({| TLBEntry15 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry14' := e ]}" := ({| TLBEntry14 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry13' := e ]}" := ({| TLBEntry13 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry12' := e ]}" := ({| TLBEntry12 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry11' := e ]}" := ({| TLBEntry11 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry10' := e ]}" := ({| TLBEntry10 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry09' := e ]}" := ({| TLBEntry09 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry08' := e ]}" := ({| TLBEntry08 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry07' := e ]}" := ({| TLBEntry07 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry06' := e ]}" := ({| TLBEntry06 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry05' := e ]}" := ({| TLBEntry05 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry04' := e ]}" := ({| TLBEntry04 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry03' := e ]}" := ({| TLBEntry03 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry02' := e ]}" := ({| TLBEntry02 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry01' := e ]}" := ({| TLBEntry01 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntry00' := e ]}" := ({| TLBEntry00 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBXContext' := e ]}" := ({| TLBXContext := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntryHi' := e ]}" := ({| TLBEntryHi := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBWired' := e ]}" := ({| TLBWired := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBPageMask' := e ]}" := ({| TLBPageMask := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBContext' := e ]}" := ({| TLBContext := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntryLo1' := e ]}" := ({| TLBEntryLo1 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBEntryLo0' := e ]}" := ({| TLBEntryLo0 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBRandom' := e ]}" := ({| TLBRandom := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBIndex' := e ]}" := ({| TLBIndex := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBProbe := TLBProbe r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'TLBProbe' := e ]}" := ({| TLBProbe := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; NextPC := NextPC r; PC := PC r |}). +Notation "{[ r 'with' 'NextPC' := e ]}" := ({| NextPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; PC := PC r |}). +Notation "{[ r 'with' 'PC' := e ]}" := ({| PC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; DelayedPC := DelayedPC r; BranchPending := BranchPending r; InBranchDelay := InBranchDelay r; NextInBranchDelay := NextInBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadInstrP := CP0BadInstrP r; CP0BadInstr := CP0BadInstr r; LastInstrBits := LastInstrBits r; CurrentInstrBits := CurrentInstrBits r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; NextPC := NextPC r |}). + + + +Definition CauseReg_of_regval (merge_var : register_value) +: option CauseReg := + + match merge_var with | Regval_CauseReg (v) => Some (v) | g__13 => None end. + +Definition regval_of_CauseReg (v : CauseReg) : register_value := Regval_CauseReg (v). + +Definition ContextReg_of_regval (merge_var : register_value) +: option ContextReg := + + match merge_var with | Regval_ContextReg (v) => Some (v) | g__12 => None end. + +Definition regval_of_ContextReg (v : ContextReg) : register_value := Regval_ContextReg (v). + +Definition StatusReg_of_regval (merge_var : register_value) +: option StatusReg := + + match merge_var with | Regval_StatusReg (v) => Some (v) | g__11 => None end. + +Definition regval_of_StatusReg (v : StatusReg) : register_value := Regval_StatusReg (v). + +Definition TLBEntry_of_regval (merge_var : register_value) +: option TLBEntry := + + match merge_var with | Regval_TLBEntry (v) => Some (v) | g__10 => None end. + +Definition regval_of_TLBEntry (v : TLBEntry) : register_value := Regval_TLBEntry (v). + +Definition TLBEntryHiReg_of_regval (merge_var : register_value) +: option TLBEntryHiReg := + + match merge_var with | Regval_TLBEntryHiReg (v) => Some (v) | g__9 => None end. + +Definition regval_of_TLBEntryHiReg (v : TLBEntryHiReg) +: register_value := + + Regval_TLBEntryHiReg + (v). + +Definition TLBEntryLoReg_of_regval (merge_var : register_value) +: option TLBEntryLoReg := + + match merge_var with | Regval_TLBEntryLoReg (v) => Some (v) | g__8 => None end. + +Definition regval_of_TLBEntryLoReg (v : TLBEntryLoReg) +: register_value := + + Regval_TLBEntryLoReg + (v). + +Definition XContextReg_of_regval (merge_var : register_value) +: option XContextReg := + + match merge_var with | Regval_XContextReg (v) => Some (v) | g__7 => None end. + +Definition regval_of_XContextReg (v : XContextReg) : register_value := Regval_XContextReg (v). + +Definition vector_16_dec_bit_of_regval (merge_var : register_value) +: option (mword 16) := + + match merge_var with | Regval_vector_16_dec_bit (v) => Some (v) | g__6 => None end. + +Definition regval_of_vector_16_dec_bit (v : mword 16) +: register_value := + + Regval_vector_16_dec_bit + (v). + +Definition vector_1_dec_bit_of_regval (merge_var : register_value) +: option (mword 1) := + + match merge_var with | Regval_vector_1_dec_bit (v) => Some (v) | g__5 => None end. + +Definition regval_of_vector_1_dec_bit (v : mword 1) +: register_value := + + Regval_vector_1_dec_bit + (v). + +Definition vector_32_dec_bit_of_regval (merge_var : register_value) +: option (mword 32) := + + match merge_var with | Regval_vector_32_dec_bit (v) => Some (v) | g__4 => None end. + +Definition regval_of_vector_32_dec_bit (v : mword 32) +: register_value := + + Regval_vector_32_dec_bit + (v). + +Definition vector_3_dec_bit_of_regval (merge_var : register_value) +: option (mword 3) := + + match merge_var with | Regval_vector_3_dec_bit (v) => Some (v) | g__3 => None end. + +Definition regval_of_vector_3_dec_bit (v : mword 3) +: register_value := + + Regval_vector_3_dec_bit + (v). + +Definition vector_64_dec_bit_of_regval (merge_var : register_value) +: option (mword 64) := + + match merge_var with | Regval_vector_64_dec_bit (v) => Some (v) | g__2 => None end. + +Definition regval_of_vector_64_dec_bit (v : mword 64) +: register_value := + + Regval_vector_64_dec_bit + (v). + +Definition vector_6_dec_bit_of_regval (merge_var : register_value) +: option (mword 6) := + + match merge_var with | Regval_vector_6_dec_bit (v) => Some (v) | g__1 => None end. + +Definition regval_of_vector_6_dec_bit (v : mword 6) +: register_value := + + Regval_vector_6_dec_bit + (v). + +Definition vector_8_dec_bit_of_regval (merge_var : register_value) +: option (mword 8) := + + match merge_var with | Regval_vector_8_dec_bit (v) => Some (v) | g__0 => None end. + +Definition regval_of_vector_8_dec_bit (v : mword 8) +: register_value := + + Regval_vector_8_dec_bit + (v). + + + +Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with + | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None + | _ => None +end. + +Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)). + +Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with + | Regval_list v => just_list (List.map of_regval v) + | _ => None +end. + +Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs). + +Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with + | Regval_option v => option_map of_regval v + | _ => None +end. + +Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v). + + +Definition UART_RVALID_ref := {| + name := "UART_RVALID"; + read_from := (fun s => s.(UART_RVALID)); + write_to := (fun v s => ({[ s with UART_RVALID := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition UART_RDATA_ref := {| + name := "UART_RDATA"; + read_from := (fun s => s.(UART_RDATA)); + write_to := (fun v s => ({[ s with UART_RDATA := v ]})); + of_regval := (fun v => vector_8_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_8_dec_bit v) |}. + +Definition UART_WRITTEN_ref := {| + name := "UART_WRITTEN"; + read_from := (fun s => s.(UART_WRITTEN)); + write_to := (fun v s => ({[ s with UART_WRITTEN := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition UART_WDATA_ref := {| + name := "UART_WDATA"; + read_from := (fun s => s.(UART_WDATA)); + write_to := (fun v s => ({[ s with UART_WDATA := v ]})); + of_regval := (fun v => vector_8_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_8_dec_bit v) |}. + +Definition GPR_ref := {| + name := "GPR"; + read_from := (fun s => s.(GPR)); + write_to := (fun v s => ({[ s with GPR := v ]})); + of_regval := (fun v => vector_of_regval 32 (fun v => vector_64_dec_bit_of_regval v) v); + regval_of := (fun v => regval_of_vector (fun v => regval_of_vector_64_dec_bit v) 32 false v) |}. + +Definition LO_ref := {| + name := "LO"; + read_from := (fun s => s.(LO)); + write_to := (fun v s => ({[ s with LO := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition HI_ref := {| + name := "HI"; + read_from := (fun s => s.(HI)); + write_to := (fun v s => ({[ s with HI := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition DelayedPC_ref := {| + name := "DelayedPC"; + read_from := (fun s => s.(DelayedPC)); + write_to := (fun v s => ({[ s with DelayedPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition BranchPending_ref := {| + name := "BranchPending"; + read_from := (fun s => s.(BranchPending)); + write_to := (fun v s => ({[ s with BranchPending := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition InBranchDelay_ref := {| + name := "InBranchDelay"; + read_from := (fun s => s.(InBranchDelay)); + write_to := (fun v s => ({[ s with InBranchDelay := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition NextInBranchDelay_ref := {| + name := "NextInBranchDelay"; + read_from := (fun s => s.(NextInBranchDelay)); + write_to := (fun v s => ({[ s with NextInBranchDelay := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition CP0Status_ref := {| + name := "CP0Status"; + read_from := (fun s => s.(CP0Status)); + write_to := (fun v s => ({[ s with CP0Status := v ]})); + of_regval := (fun v => StatusReg_of_regval v); + regval_of := (fun v => regval_of_StatusReg v) |}. + +Definition CP0ConfigK0_ref := {| + name := "CP0ConfigK0"; + read_from := (fun s => s.(CP0ConfigK0)); + write_to := (fun v s => ({[ s with CP0ConfigK0 := v ]})); + of_regval := (fun v => vector_3_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_3_dec_bit v) |}. + +Definition CP0UserLocal_ref := {| + name := "CP0UserLocal"; + read_from := (fun s => s.(CP0UserLocal)); + write_to := (fun v s => ({[ s with CP0UserLocal := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0HWREna_ref := {| + name := "CP0HWREna"; + read_from := (fun s => s.(CP0HWREna)); + write_to := (fun v s => ({[ s with CP0HWREna := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0Count_ref := {| + name := "CP0Count"; + read_from := (fun s => s.(CP0Count)); + write_to := (fun v s => ({[ s with CP0Count := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0BadInstrP_ref := {| + name := "CP0BadInstrP"; + read_from := (fun s => s.(CP0BadInstrP)); + write_to := (fun v s => ({[ s with CP0BadInstrP := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0BadInstr_ref := {| + name := "CP0BadInstr"; + read_from := (fun s => s.(CP0BadInstr)); + write_to := (fun v s => ({[ s with CP0BadInstr := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition LastInstrBits_ref := {| + name := "LastInstrBits"; + read_from := (fun s => s.(LastInstrBits)); + write_to := (fun v s => ({[ s with LastInstrBits := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CurrentInstrBits_ref := {| + name := "CurrentInstrBits"; + read_from := (fun s => s.(CurrentInstrBits)); + write_to := (fun v s => ({[ s with CurrentInstrBits := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition CP0BadVAddr_ref := {| + name := "CP0BadVAddr"; + read_from := (fun s => s.(CP0BadVAddr)); + write_to := (fun v s => ({[ s with CP0BadVAddr := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0LLAddr_ref := {| + name := "CP0LLAddr"; + read_from := (fun s => s.(CP0LLAddr)); + write_to := (fun v s => ({[ s with CP0LLAddr := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0LLBit_ref := {| + name := "CP0LLBit"; + read_from := (fun s => s.(CP0LLBit)); + write_to := (fun v s => ({[ s with CP0LLBit := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition CP0ErrorEPC_ref := {| + name := "CP0ErrorEPC"; + read_from := (fun s => s.(CP0ErrorEPC)); + write_to := (fun v s => ({[ s with CP0ErrorEPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0EPC_ref := {| + name := "CP0EPC"; + read_from := (fun s => s.(CP0EPC)); + write_to := (fun v s => ({[ s with CP0EPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition CP0Cause_ref := {| + name := "CP0Cause"; + read_from := (fun s => s.(CP0Cause)); + write_to := (fun v s => ({[ s with CP0Cause := v ]})); + of_regval := (fun v => CauseReg_of_regval v); + regval_of := (fun v => regval_of_CauseReg v) |}. + +Definition CP0Compare_ref := {| + name := "CP0Compare"; + read_from := (fun s => s.(CP0Compare)); + write_to := (fun v s => ({[ s with CP0Compare := v ]})); + of_regval := (fun v => vector_32_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. + +Definition TLBEntry63_ref := {| + name := "TLBEntry63"; + read_from := (fun s => s.(TLBEntry63)); + write_to := (fun v s => ({[ s with TLBEntry63 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry62_ref := {| + name := "TLBEntry62"; + read_from := (fun s => s.(TLBEntry62)); + write_to := (fun v s => ({[ s with TLBEntry62 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry61_ref := {| + name := "TLBEntry61"; + read_from := (fun s => s.(TLBEntry61)); + write_to := (fun v s => ({[ s with TLBEntry61 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry60_ref := {| + name := "TLBEntry60"; + read_from := (fun s => s.(TLBEntry60)); + write_to := (fun v s => ({[ s with TLBEntry60 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry59_ref := {| + name := "TLBEntry59"; + read_from := (fun s => s.(TLBEntry59)); + write_to := (fun v s => ({[ s with TLBEntry59 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry58_ref := {| + name := "TLBEntry58"; + read_from := (fun s => s.(TLBEntry58)); + write_to := (fun v s => ({[ s with TLBEntry58 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry57_ref := {| + name := "TLBEntry57"; + read_from := (fun s => s.(TLBEntry57)); + write_to := (fun v s => ({[ s with TLBEntry57 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry56_ref := {| + name := "TLBEntry56"; + read_from := (fun s => s.(TLBEntry56)); + write_to := (fun v s => ({[ s with TLBEntry56 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry55_ref := {| + name := "TLBEntry55"; + read_from := (fun s => s.(TLBEntry55)); + write_to := (fun v s => ({[ s with TLBEntry55 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry54_ref := {| + name := "TLBEntry54"; + read_from := (fun s => s.(TLBEntry54)); + write_to := (fun v s => ({[ s with TLBEntry54 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry53_ref := {| + name := "TLBEntry53"; + read_from := (fun s => s.(TLBEntry53)); + write_to := (fun v s => ({[ s with TLBEntry53 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry52_ref := {| + name := "TLBEntry52"; + read_from := (fun s => s.(TLBEntry52)); + write_to := (fun v s => ({[ s with TLBEntry52 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry51_ref := {| + name := "TLBEntry51"; + read_from := (fun s => s.(TLBEntry51)); + write_to := (fun v s => ({[ s with TLBEntry51 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry50_ref := {| + name := "TLBEntry50"; + read_from := (fun s => s.(TLBEntry50)); + write_to := (fun v s => ({[ s with TLBEntry50 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry49_ref := {| + name := "TLBEntry49"; + read_from := (fun s => s.(TLBEntry49)); + write_to := (fun v s => ({[ s with TLBEntry49 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry48_ref := {| + name := "TLBEntry48"; + read_from := (fun s => s.(TLBEntry48)); + write_to := (fun v s => ({[ s with TLBEntry48 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry47_ref := {| + name := "TLBEntry47"; + read_from := (fun s => s.(TLBEntry47)); + write_to := (fun v s => ({[ s with TLBEntry47 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry46_ref := {| + name := "TLBEntry46"; + read_from := (fun s => s.(TLBEntry46)); + write_to := (fun v s => ({[ s with TLBEntry46 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry45_ref := {| + name := "TLBEntry45"; + read_from := (fun s => s.(TLBEntry45)); + write_to := (fun v s => ({[ s with TLBEntry45 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry44_ref := {| + name := "TLBEntry44"; + read_from := (fun s => s.(TLBEntry44)); + write_to := (fun v s => ({[ s with TLBEntry44 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry43_ref := {| + name := "TLBEntry43"; + read_from := (fun s => s.(TLBEntry43)); + write_to := (fun v s => ({[ s with TLBEntry43 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry42_ref := {| + name := "TLBEntry42"; + read_from := (fun s => s.(TLBEntry42)); + write_to := (fun v s => ({[ s with TLBEntry42 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry41_ref := {| + name := "TLBEntry41"; + read_from := (fun s => s.(TLBEntry41)); + write_to := (fun v s => ({[ s with TLBEntry41 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry40_ref := {| + name := "TLBEntry40"; + read_from := (fun s => s.(TLBEntry40)); + write_to := (fun v s => ({[ s with TLBEntry40 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry39_ref := {| + name := "TLBEntry39"; + read_from := (fun s => s.(TLBEntry39)); + write_to := (fun v s => ({[ s with TLBEntry39 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry38_ref := {| + name := "TLBEntry38"; + read_from := (fun s => s.(TLBEntry38)); + write_to := (fun v s => ({[ s with TLBEntry38 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry37_ref := {| + name := "TLBEntry37"; + read_from := (fun s => s.(TLBEntry37)); + write_to := (fun v s => ({[ s with TLBEntry37 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry36_ref := {| + name := "TLBEntry36"; + read_from := (fun s => s.(TLBEntry36)); + write_to := (fun v s => ({[ s with TLBEntry36 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry35_ref := {| + name := "TLBEntry35"; + read_from := (fun s => s.(TLBEntry35)); + write_to := (fun v s => ({[ s with TLBEntry35 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry34_ref := {| + name := "TLBEntry34"; + read_from := (fun s => s.(TLBEntry34)); + write_to := (fun v s => ({[ s with TLBEntry34 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry33_ref := {| + name := "TLBEntry33"; + read_from := (fun s => s.(TLBEntry33)); + write_to := (fun v s => ({[ s with TLBEntry33 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry32_ref := {| + name := "TLBEntry32"; + read_from := (fun s => s.(TLBEntry32)); + write_to := (fun v s => ({[ s with TLBEntry32 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry31_ref := {| + name := "TLBEntry31"; + read_from := (fun s => s.(TLBEntry31)); + write_to := (fun v s => ({[ s with TLBEntry31 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry30_ref := {| + name := "TLBEntry30"; + read_from := (fun s => s.(TLBEntry30)); + write_to := (fun v s => ({[ s with TLBEntry30 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry29_ref := {| + name := "TLBEntry29"; + read_from := (fun s => s.(TLBEntry29)); + write_to := (fun v s => ({[ s with TLBEntry29 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry28_ref := {| + name := "TLBEntry28"; + read_from := (fun s => s.(TLBEntry28)); + write_to := (fun v s => ({[ s with TLBEntry28 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry27_ref := {| + name := "TLBEntry27"; + read_from := (fun s => s.(TLBEntry27)); + write_to := (fun v s => ({[ s with TLBEntry27 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry26_ref := {| + name := "TLBEntry26"; + read_from := (fun s => s.(TLBEntry26)); + write_to := (fun v s => ({[ s with TLBEntry26 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry25_ref := {| + name := "TLBEntry25"; + read_from := (fun s => s.(TLBEntry25)); + write_to := (fun v s => ({[ s with TLBEntry25 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry24_ref := {| + name := "TLBEntry24"; + read_from := (fun s => s.(TLBEntry24)); + write_to := (fun v s => ({[ s with TLBEntry24 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry23_ref := {| + name := "TLBEntry23"; + read_from := (fun s => s.(TLBEntry23)); + write_to := (fun v s => ({[ s with TLBEntry23 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry22_ref := {| + name := "TLBEntry22"; + read_from := (fun s => s.(TLBEntry22)); + write_to := (fun v s => ({[ s with TLBEntry22 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry21_ref := {| + name := "TLBEntry21"; + read_from := (fun s => s.(TLBEntry21)); + write_to := (fun v s => ({[ s with TLBEntry21 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry20_ref := {| + name := "TLBEntry20"; + read_from := (fun s => s.(TLBEntry20)); + write_to := (fun v s => ({[ s with TLBEntry20 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry19_ref := {| + name := "TLBEntry19"; + read_from := (fun s => s.(TLBEntry19)); + write_to := (fun v s => ({[ s with TLBEntry19 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry18_ref := {| + name := "TLBEntry18"; + read_from := (fun s => s.(TLBEntry18)); + write_to := (fun v s => ({[ s with TLBEntry18 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry17_ref := {| + name := "TLBEntry17"; + read_from := (fun s => s.(TLBEntry17)); + write_to := (fun v s => ({[ s with TLBEntry17 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry16_ref := {| + name := "TLBEntry16"; + read_from := (fun s => s.(TLBEntry16)); + write_to := (fun v s => ({[ s with TLBEntry16 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry15_ref := {| + name := "TLBEntry15"; + read_from := (fun s => s.(TLBEntry15)); + write_to := (fun v s => ({[ s with TLBEntry15 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry14_ref := {| + name := "TLBEntry14"; + read_from := (fun s => s.(TLBEntry14)); + write_to := (fun v s => ({[ s with TLBEntry14 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry13_ref := {| + name := "TLBEntry13"; + read_from := (fun s => s.(TLBEntry13)); + write_to := (fun v s => ({[ s with TLBEntry13 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry12_ref := {| + name := "TLBEntry12"; + read_from := (fun s => s.(TLBEntry12)); + write_to := (fun v s => ({[ s with TLBEntry12 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry11_ref := {| + name := "TLBEntry11"; + read_from := (fun s => s.(TLBEntry11)); + write_to := (fun v s => ({[ s with TLBEntry11 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry10_ref := {| + name := "TLBEntry10"; + read_from := (fun s => s.(TLBEntry10)); + write_to := (fun v s => ({[ s with TLBEntry10 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry09_ref := {| + name := "TLBEntry09"; + read_from := (fun s => s.(TLBEntry09)); + write_to := (fun v s => ({[ s with TLBEntry09 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry08_ref := {| + name := "TLBEntry08"; + read_from := (fun s => s.(TLBEntry08)); + write_to := (fun v s => ({[ s with TLBEntry08 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry07_ref := {| + name := "TLBEntry07"; + read_from := (fun s => s.(TLBEntry07)); + write_to := (fun v s => ({[ s with TLBEntry07 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry06_ref := {| + name := "TLBEntry06"; + read_from := (fun s => s.(TLBEntry06)); + write_to := (fun v s => ({[ s with TLBEntry06 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry05_ref := {| + name := "TLBEntry05"; + read_from := (fun s => s.(TLBEntry05)); + write_to := (fun v s => ({[ s with TLBEntry05 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry04_ref := {| + name := "TLBEntry04"; + read_from := (fun s => s.(TLBEntry04)); + write_to := (fun v s => ({[ s with TLBEntry04 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry03_ref := {| + name := "TLBEntry03"; + read_from := (fun s => s.(TLBEntry03)); + write_to := (fun v s => ({[ s with TLBEntry03 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry02_ref := {| + name := "TLBEntry02"; + read_from := (fun s => s.(TLBEntry02)); + write_to := (fun v s => ({[ s with TLBEntry02 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry01_ref := {| + name := "TLBEntry01"; + read_from := (fun s => s.(TLBEntry01)); + write_to := (fun v s => ({[ s with TLBEntry01 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBEntry00_ref := {| + name := "TLBEntry00"; + read_from := (fun s => s.(TLBEntry00)); + write_to := (fun v s => ({[ s with TLBEntry00 := v ]})); + of_regval := (fun v => TLBEntry_of_regval v); + regval_of := (fun v => regval_of_TLBEntry v) |}. + +Definition TLBXContext_ref := {| + name := "TLBXContext"; + read_from := (fun s => s.(TLBXContext)); + write_to := (fun v s => ({[ s with TLBXContext := v ]})); + of_regval := (fun v => XContextReg_of_regval v); + regval_of := (fun v => regval_of_XContextReg v) |}. + +Definition TLBEntryHi_ref := {| + name := "TLBEntryHi"; + read_from := (fun s => s.(TLBEntryHi)); + write_to := (fun v s => ({[ s with TLBEntryHi := v ]})); + of_regval := (fun v => TLBEntryHiReg_of_regval v); + regval_of := (fun v => regval_of_TLBEntryHiReg v) |}. + +Definition TLBWired_ref := {| + name := "TLBWired"; + read_from := (fun s => s.(TLBWired)); + write_to := (fun v s => ({[ s with TLBWired := v ]})); + of_regval := (fun v => vector_6_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. + +Definition TLBPageMask_ref := {| + name := "TLBPageMask"; + read_from := (fun s => s.(TLBPageMask)); + write_to := (fun v s => ({[ s with TLBPageMask := v ]})); + of_regval := (fun v => vector_16_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_16_dec_bit v) |}. + +Definition TLBContext_ref := {| + name := "TLBContext"; + read_from := (fun s => s.(TLBContext)); + write_to := (fun v s => ({[ s with TLBContext := v ]})); + of_regval := (fun v => ContextReg_of_regval v); + regval_of := (fun v => regval_of_ContextReg v) |}. + +Definition TLBEntryLo1_ref := {| + name := "TLBEntryLo1"; + read_from := (fun s => s.(TLBEntryLo1)); + write_to := (fun v s => ({[ s with TLBEntryLo1 := v ]})); + of_regval := (fun v => TLBEntryLoReg_of_regval v); + regval_of := (fun v => regval_of_TLBEntryLoReg v) |}. + +Definition TLBEntryLo0_ref := {| + name := "TLBEntryLo0"; + read_from := (fun s => s.(TLBEntryLo0)); + write_to := (fun v s => ({[ s with TLBEntryLo0 := v ]})); + of_regval := (fun v => TLBEntryLoReg_of_regval v); + regval_of := (fun v => regval_of_TLBEntryLoReg v) |}. + +Definition TLBRandom_ref := {| + name := "TLBRandom"; + read_from := (fun s => s.(TLBRandom)); + write_to := (fun v s => ({[ s with TLBRandom := v ]})); + of_regval := (fun v => vector_6_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. + +Definition TLBIndex_ref := {| + name := "TLBIndex"; + read_from := (fun s => s.(TLBIndex)); + write_to := (fun v s => ({[ s with TLBIndex := v ]})); + of_regval := (fun v => vector_6_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. + +Definition TLBProbe_ref := {| + name := "TLBProbe"; + read_from := (fun s => s.(TLBProbe)); + write_to := (fun v s => ({[ s with TLBProbe := v ]})); + of_regval := (fun v => vector_1_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. + +Definition NextPC_ref := {| + name := "NextPC"; + read_from := (fun s => s.(NextPC)); + write_to := (fun v s => ({[ s with NextPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition PC_ref := {| + name := "PC"; + read_from := (fun s => s.(PC)); + write_to := (fun v s => ({[ s with PC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Local Open Scope string. +Definition get_regval (reg_name : string) (s : regstate) : option register_value := + if string_dec reg_name "UART_RVALID" then Some (UART_RVALID_ref.(regval_of) (UART_RVALID_ref.(read_from) s)) else + if string_dec reg_name "UART_RDATA" then Some (UART_RDATA_ref.(regval_of) (UART_RDATA_ref.(read_from) s)) else + if string_dec reg_name "UART_WRITTEN" then Some (UART_WRITTEN_ref.(regval_of) (UART_WRITTEN_ref.(read_from) s)) else + if string_dec reg_name "UART_WDATA" then Some (UART_WDATA_ref.(regval_of) (UART_WDATA_ref.(read_from) s)) else + if string_dec reg_name "GPR" then Some (GPR_ref.(regval_of) (GPR_ref.(read_from) s)) else + if string_dec reg_name "LO" then Some (LO_ref.(regval_of) (LO_ref.(read_from) s)) else + if string_dec reg_name "HI" then Some (HI_ref.(regval_of) (HI_ref.(read_from) s)) else + if string_dec reg_name "DelayedPC" then Some (DelayedPC_ref.(regval_of) (DelayedPC_ref.(read_from) s)) else + if string_dec reg_name "BranchPending" then Some (BranchPending_ref.(regval_of) (BranchPending_ref.(read_from) s)) else + if string_dec reg_name "InBranchDelay" then Some (InBranchDelay_ref.(regval_of) (InBranchDelay_ref.(read_from) s)) else + if string_dec reg_name "NextInBranchDelay" then Some (NextInBranchDelay_ref.(regval_of) (NextInBranchDelay_ref.(read_from) s)) else + if string_dec reg_name "CP0Status" then Some (CP0Status_ref.(regval_of) (CP0Status_ref.(read_from) s)) else + if string_dec reg_name "CP0ConfigK0" then Some (CP0ConfigK0_ref.(regval_of) (CP0ConfigK0_ref.(read_from) s)) else + if string_dec reg_name "CP0UserLocal" then Some (CP0UserLocal_ref.(regval_of) (CP0UserLocal_ref.(read_from) s)) else + if string_dec reg_name "CP0HWREna" then Some (CP0HWREna_ref.(regval_of) (CP0HWREna_ref.(read_from) s)) else + if string_dec reg_name "CP0Count" then Some (CP0Count_ref.(regval_of) (CP0Count_ref.(read_from) s)) else + if string_dec reg_name "CP0BadInstrP" then Some (CP0BadInstrP_ref.(regval_of) (CP0BadInstrP_ref.(read_from) s)) else + if string_dec reg_name "CP0BadInstr" then Some (CP0BadInstr_ref.(regval_of) (CP0BadInstr_ref.(read_from) s)) else + if string_dec reg_name "LastInstrBits" then Some (LastInstrBits_ref.(regval_of) (LastInstrBits_ref.(read_from) s)) else + if string_dec reg_name "CurrentInstrBits" then Some (CurrentInstrBits_ref.(regval_of) (CurrentInstrBits_ref.(read_from) s)) else + if string_dec reg_name "CP0BadVAddr" then Some (CP0BadVAddr_ref.(regval_of) (CP0BadVAddr_ref.(read_from) s)) else + if string_dec reg_name "CP0LLAddr" then Some (CP0LLAddr_ref.(regval_of) (CP0LLAddr_ref.(read_from) s)) else + if string_dec reg_name "CP0LLBit" then Some (CP0LLBit_ref.(regval_of) (CP0LLBit_ref.(read_from) s)) else + if string_dec reg_name "CP0ErrorEPC" then Some (CP0ErrorEPC_ref.(regval_of) (CP0ErrorEPC_ref.(read_from) s)) else + if string_dec reg_name "CP0EPC" then Some (CP0EPC_ref.(regval_of) (CP0EPC_ref.(read_from) s)) else + if string_dec reg_name "CP0Cause" then Some (CP0Cause_ref.(regval_of) (CP0Cause_ref.(read_from) s)) else + if string_dec reg_name "CP0Compare" then Some (CP0Compare_ref.(regval_of) (CP0Compare_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry63" then Some (TLBEntry63_ref.(regval_of) (TLBEntry63_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry62" then Some (TLBEntry62_ref.(regval_of) (TLBEntry62_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry61" then Some (TLBEntry61_ref.(regval_of) (TLBEntry61_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry60" then Some (TLBEntry60_ref.(regval_of) (TLBEntry60_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry59" then Some (TLBEntry59_ref.(regval_of) (TLBEntry59_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry58" then Some (TLBEntry58_ref.(regval_of) (TLBEntry58_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry57" then Some (TLBEntry57_ref.(regval_of) (TLBEntry57_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry56" then Some (TLBEntry56_ref.(regval_of) (TLBEntry56_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry55" then Some (TLBEntry55_ref.(regval_of) (TLBEntry55_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry54" then Some (TLBEntry54_ref.(regval_of) (TLBEntry54_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry53" then Some (TLBEntry53_ref.(regval_of) (TLBEntry53_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry52" then Some (TLBEntry52_ref.(regval_of) (TLBEntry52_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry51" then Some (TLBEntry51_ref.(regval_of) (TLBEntry51_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry50" then Some (TLBEntry50_ref.(regval_of) (TLBEntry50_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry49" then Some (TLBEntry49_ref.(regval_of) (TLBEntry49_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry48" then Some (TLBEntry48_ref.(regval_of) (TLBEntry48_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry47" then Some (TLBEntry47_ref.(regval_of) (TLBEntry47_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry46" then Some (TLBEntry46_ref.(regval_of) (TLBEntry46_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry45" then Some (TLBEntry45_ref.(regval_of) (TLBEntry45_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry44" then Some (TLBEntry44_ref.(regval_of) (TLBEntry44_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry43" then Some (TLBEntry43_ref.(regval_of) (TLBEntry43_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry42" then Some (TLBEntry42_ref.(regval_of) (TLBEntry42_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry41" then Some (TLBEntry41_ref.(regval_of) (TLBEntry41_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry40" then Some (TLBEntry40_ref.(regval_of) (TLBEntry40_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry39" then Some (TLBEntry39_ref.(regval_of) (TLBEntry39_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry38" then Some (TLBEntry38_ref.(regval_of) (TLBEntry38_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry37" then Some (TLBEntry37_ref.(regval_of) (TLBEntry37_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry36" then Some (TLBEntry36_ref.(regval_of) (TLBEntry36_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry35" then Some (TLBEntry35_ref.(regval_of) (TLBEntry35_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry34" then Some (TLBEntry34_ref.(regval_of) (TLBEntry34_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry33" then Some (TLBEntry33_ref.(regval_of) (TLBEntry33_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry32" then Some (TLBEntry32_ref.(regval_of) (TLBEntry32_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry31" then Some (TLBEntry31_ref.(regval_of) (TLBEntry31_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry30" then Some (TLBEntry30_ref.(regval_of) (TLBEntry30_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry29" then Some (TLBEntry29_ref.(regval_of) (TLBEntry29_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry28" then Some (TLBEntry28_ref.(regval_of) (TLBEntry28_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry27" then Some (TLBEntry27_ref.(regval_of) (TLBEntry27_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry26" then Some (TLBEntry26_ref.(regval_of) (TLBEntry26_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry25" then Some (TLBEntry25_ref.(regval_of) (TLBEntry25_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry24" then Some (TLBEntry24_ref.(regval_of) (TLBEntry24_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry23" then Some (TLBEntry23_ref.(regval_of) (TLBEntry23_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry22" then Some (TLBEntry22_ref.(regval_of) (TLBEntry22_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry21" then Some (TLBEntry21_ref.(regval_of) (TLBEntry21_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry20" then Some (TLBEntry20_ref.(regval_of) (TLBEntry20_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry19" then Some (TLBEntry19_ref.(regval_of) (TLBEntry19_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry18" then Some (TLBEntry18_ref.(regval_of) (TLBEntry18_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry17" then Some (TLBEntry17_ref.(regval_of) (TLBEntry17_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry16" then Some (TLBEntry16_ref.(regval_of) (TLBEntry16_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry15" then Some (TLBEntry15_ref.(regval_of) (TLBEntry15_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry14" then Some (TLBEntry14_ref.(regval_of) (TLBEntry14_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry13" then Some (TLBEntry13_ref.(regval_of) (TLBEntry13_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry12" then Some (TLBEntry12_ref.(regval_of) (TLBEntry12_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry11" then Some (TLBEntry11_ref.(regval_of) (TLBEntry11_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry10" then Some (TLBEntry10_ref.(regval_of) (TLBEntry10_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry09" then Some (TLBEntry09_ref.(regval_of) (TLBEntry09_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry08" then Some (TLBEntry08_ref.(regval_of) (TLBEntry08_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry07" then Some (TLBEntry07_ref.(regval_of) (TLBEntry07_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry06" then Some (TLBEntry06_ref.(regval_of) (TLBEntry06_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry05" then Some (TLBEntry05_ref.(regval_of) (TLBEntry05_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry04" then Some (TLBEntry04_ref.(regval_of) (TLBEntry04_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry03" then Some (TLBEntry03_ref.(regval_of) (TLBEntry03_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry02" then Some (TLBEntry02_ref.(regval_of) (TLBEntry02_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry01" then Some (TLBEntry01_ref.(regval_of) (TLBEntry01_ref.(read_from) s)) else + if string_dec reg_name "TLBEntry00" then Some (TLBEntry00_ref.(regval_of) (TLBEntry00_ref.(read_from) s)) else + if string_dec reg_name "TLBXContext" then Some (TLBXContext_ref.(regval_of) (TLBXContext_ref.(read_from) s)) else + if string_dec reg_name "TLBEntryHi" then Some (TLBEntryHi_ref.(regval_of) (TLBEntryHi_ref.(read_from) s)) else + if string_dec reg_name "TLBWired" then Some (TLBWired_ref.(regval_of) (TLBWired_ref.(read_from) s)) else + if string_dec reg_name "TLBPageMask" then Some (TLBPageMask_ref.(regval_of) (TLBPageMask_ref.(read_from) s)) else + if string_dec reg_name "TLBContext" then Some (TLBContext_ref.(regval_of) (TLBContext_ref.(read_from) s)) else + if string_dec reg_name "TLBEntryLo1" then Some (TLBEntryLo1_ref.(regval_of) (TLBEntryLo1_ref.(read_from) s)) else + if string_dec reg_name "TLBEntryLo0" then Some (TLBEntryLo0_ref.(regval_of) (TLBEntryLo0_ref.(read_from) s)) else + if string_dec reg_name "TLBRandom" then Some (TLBRandom_ref.(regval_of) (TLBRandom_ref.(read_from) s)) else + if string_dec reg_name "TLBIndex" then Some (TLBIndex_ref.(regval_of) (TLBIndex_ref.(read_from) s)) else + if string_dec reg_name "TLBProbe" then Some (TLBProbe_ref.(regval_of) (TLBProbe_ref.(read_from) s)) else + if string_dec reg_name "NextPC" then Some (NextPC_ref.(regval_of) (NextPC_ref.(read_from) s)) else + if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else + None. + +Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate := + if string_dec reg_name "UART_RVALID" then option_map (fun v => UART_RVALID_ref.(write_to) v s) (UART_RVALID_ref.(of_regval) v) else + if string_dec reg_name "UART_RDATA" then option_map (fun v => UART_RDATA_ref.(write_to) v s) (UART_RDATA_ref.(of_regval) v) else + if string_dec reg_name "UART_WRITTEN" then option_map (fun v => UART_WRITTEN_ref.(write_to) v s) (UART_WRITTEN_ref.(of_regval) v) else + if string_dec reg_name "UART_WDATA" then option_map (fun v => UART_WDATA_ref.(write_to) v s) (UART_WDATA_ref.(of_regval) v) else + if string_dec reg_name "GPR" then option_map (fun v => GPR_ref.(write_to) v s) (GPR_ref.(of_regval) v) else + if string_dec reg_name "LO" then option_map (fun v => LO_ref.(write_to) v s) (LO_ref.(of_regval) v) else + if string_dec reg_name "HI" then option_map (fun v => HI_ref.(write_to) v s) (HI_ref.(of_regval) v) else + if string_dec reg_name "DelayedPC" then option_map (fun v => DelayedPC_ref.(write_to) v s) (DelayedPC_ref.(of_regval) v) else + if string_dec reg_name "BranchPending" then option_map (fun v => BranchPending_ref.(write_to) v s) (BranchPending_ref.(of_regval) v) else + if string_dec reg_name "InBranchDelay" then option_map (fun v => InBranchDelay_ref.(write_to) v s) (InBranchDelay_ref.(of_regval) v) else + if string_dec reg_name "NextInBranchDelay" then option_map (fun v => NextInBranchDelay_ref.(write_to) v s) (NextInBranchDelay_ref.(of_regval) v) else + if string_dec reg_name "CP0Status" then option_map (fun v => CP0Status_ref.(write_to) v s) (CP0Status_ref.(of_regval) v) else + if string_dec reg_name "CP0ConfigK0" then option_map (fun v => CP0ConfigK0_ref.(write_to) v s) (CP0ConfigK0_ref.(of_regval) v) else + if string_dec reg_name "CP0UserLocal" then option_map (fun v => CP0UserLocal_ref.(write_to) v s) (CP0UserLocal_ref.(of_regval) v) else + if string_dec reg_name "CP0HWREna" then option_map (fun v => CP0HWREna_ref.(write_to) v s) (CP0HWREna_ref.(of_regval) v) else + if string_dec reg_name "CP0Count" then option_map (fun v => CP0Count_ref.(write_to) v s) (CP0Count_ref.(of_regval) v) else + if string_dec reg_name "CP0BadInstrP" then option_map (fun v => CP0BadInstrP_ref.(write_to) v s) (CP0BadInstrP_ref.(of_regval) v) else + if string_dec reg_name "CP0BadInstr" then option_map (fun v => CP0BadInstr_ref.(write_to) v s) (CP0BadInstr_ref.(of_regval) v) else + if string_dec reg_name "LastInstrBits" then option_map (fun v => LastInstrBits_ref.(write_to) v s) (LastInstrBits_ref.(of_regval) v) else + if string_dec reg_name "CurrentInstrBits" then option_map (fun v => CurrentInstrBits_ref.(write_to) v s) (CurrentInstrBits_ref.(of_regval) v) else + if string_dec reg_name "CP0BadVAddr" then option_map (fun v => CP0BadVAddr_ref.(write_to) v s) (CP0BadVAddr_ref.(of_regval) v) else + if string_dec reg_name "CP0LLAddr" then option_map (fun v => CP0LLAddr_ref.(write_to) v s) (CP0LLAddr_ref.(of_regval) v) else + if string_dec reg_name "CP0LLBit" then option_map (fun v => CP0LLBit_ref.(write_to) v s) (CP0LLBit_ref.(of_regval) v) else + if string_dec reg_name "CP0ErrorEPC" then option_map (fun v => CP0ErrorEPC_ref.(write_to) v s) (CP0ErrorEPC_ref.(of_regval) v) else + if string_dec reg_name "CP0EPC" then option_map (fun v => CP0EPC_ref.(write_to) v s) (CP0EPC_ref.(of_regval) v) else + if string_dec reg_name "CP0Cause" then option_map (fun v => CP0Cause_ref.(write_to) v s) (CP0Cause_ref.(of_regval) v) else + if string_dec reg_name "CP0Compare" then option_map (fun v => CP0Compare_ref.(write_to) v s) (CP0Compare_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry63" then option_map (fun v => TLBEntry63_ref.(write_to) v s) (TLBEntry63_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry62" then option_map (fun v => TLBEntry62_ref.(write_to) v s) (TLBEntry62_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry61" then option_map (fun v => TLBEntry61_ref.(write_to) v s) (TLBEntry61_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry60" then option_map (fun v => TLBEntry60_ref.(write_to) v s) (TLBEntry60_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry59" then option_map (fun v => TLBEntry59_ref.(write_to) v s) (TLBEntry59_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry58" then option_map (fun v => TLBEntry58_ref.(write_to) v s) (TLBEntry58_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry57" then option_map (fun v => TLBEntry57_ref.(write_to) v s) (TLBEntry57_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry56" then option_map (fun v => TLBEntry56_ref.(write_to) v s) (TLBEntry56_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry55" then option_map (fun v => TLBEntry55_ref.(write_to) v s) (TLBEntry55_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry54" then option_map (fun v => TLBEntry54_ref.(write_to) v s) (TLBEntry54_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry53" then option_map (fun v => TLBEntry53_ref.(write_to) v s) (TLBEntry53_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry52" then option_map (fun v => TLBEntry52_ref.(write_to) v s) (TLBEntry52_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry51" then option_map (fun v => TLBEntry51_ref.(write_to) v s) (TLBEntry51_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry50" then option_map (fun v => TLBEntry50_ref.(write_to) v s) (TLBEntry50_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry49" then option_map (fun v => TLBEntry49_ref.(write_to) v s) (TLBEntry49_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry48" then option_map (fun v => TLBEntry48_ref.(write_to) v s) (TLBEntry48_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry47" then option_map (fun v => TLBEntry47_ref.(write_to) v s) (TLBEntry47_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry46" then option_map (fun v => TLBEntry46_ref.(write_to) v s) (TLBEntry46_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry45" then option_map (fun v => TLBEntry45_ref.(write_to) v s) (TLBEntry45_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry44" then option_map (fun v => TLBEntry44_ref.(write_to) v s) (TLBEntry44_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry43" then option_map (fun v => TLBEntry43_ref.(write_to) v s) (TLBEntry43_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry42" then option_map (fun v => TLBEntry42_ref.(write_to) v s) (TLBEntry42_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry41" then option_map (fun v => TLBEntry41_ref.(write_to) v s) (TLBEntry41_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry40" then option_map (fun v => TLBEntry40_ref.(write_to) v s) (TLBEntry40_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry39" then option_map (fun v => TLBEntry39_ref.(write_to) v s) (TLBEntry39_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry38" then option_map (fun v => TLBEntry38_ref.(write_to) v s) (TLBEntry38_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry37" then option_map (fun v => TLBEntry37_ref.(write_to) v s) (TLBEntry37_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry36" then option_map (fun v => TLBEntry36_ref.(write_to) v s) (TLBEntry36_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry35" then option_map (fun v => TLBEntry35_ref.(write_to) v s) (TLBEntry35_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry34" then option_map (fun v => TLBEntry34_ref.(write_to) v s) (TLBEntry34_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry33" then option_map (fun v => TLBEntry33_ref.(write_to) v s) (TLBEntry33_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry32" then option_map (fun v => TLBEntry32_ref.(write_to) v s) (TLBEntry32_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry31" then option_map (fun v => TLBEntry31_ref.(write_to) v s) (TLBEntry31_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry30" then option_map (fun v => TLBEntry30_ref.(write_to) v s) (TLBEntry30_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry29" then option_map (fun v => TLBEntry29_ref.(write_to) v s) (TLBEntry29_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry28" then option_map (fun v => TLBEntry28_ref.(write_to) v s) (TLBEntry28_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry27" then option_map (fun v => TLBEntry27_ref.(write_to) v s) (TLBEntry27_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry26" then option_map (fun v => TLBEntry26_ref.(write_to) v s) (TLBEntry26_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry25" then option_map (fun v => TLBEntry25_ref.(write_to) v s) (TLBEntry25_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry24" then option_map (fun v => TLBEntry24_ref.(write_to) v s) (TLBEntry24_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry23" then option_map (fun v => TLBEntry23_ref.(write_to) v s) (TLBEntry23_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry22" then option_map (fun v => TLBEntry22_ref.(write_to) v s) (TLBEntry22_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry21" then option_map (fun v => TLBEntry21_ref.(write_to) v s) (TLBEntry21_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry20" then option_map (fun v => TLBEntry20_ref.(write_to) v s) (TLBEntry20_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry19" then option_map (fun v => TLBEntry19_ref.(write_to) v s) (TLBEntry19_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry18" then option_map (fun v => TLBEntry18_ref.(write_to) v s) (TLBEntry18_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry17" then option_map (fun v => TLBEntry17_ref.(write_to) v s) (TLBEntry17_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry16" then option_map (fun v => TLBEntry16_ref.(write_to) v s) (TLBEntry16_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry15" then option_map (fun v => TLBEntry15_ref.(write_to) v s) (TLBEntry15_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry14" then option_map (fun v => TLBEntry14_ref.(write_to) v s) (TLBEntry14_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry13" then option_map (fun v => TLBEntry13_ref.(write_to) v s) (TLBEntry13_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry12" then option_map (fun v => TLBEntry12_ref.(write_to) v s) (TLBEntry12_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry11" then option_map (fun v => TLBEntry11_ref.(write_to) v s) (TLBEntry11_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry10" then option_map (fun v => TLBEntry10_ref.(write_to) v s) (TLBEntry10_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry09" then option_map (fun v => TLBEntry09_ref.(write_to) v s) (TLBEntry09_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry08" then option_map (fun v => TLBEntry08_ref.(write_to) v s) (TLBEntry08_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry07" then option_map (fun v => TLBEntry07_ref.(write_to) v s) (TLBEntry07_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry06" then option_map (fun v => TLBEntry06_ref.(write_to) v s) (TLBEntry06_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry05" then option_map (fun v => TLBEntry05_ref.(write_to) v s) (TLBEntry05_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry04" then option_map (fun v => TLBEntry04_ref.(write_to) v s) (TLBEntry04_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry03" then option_map (fun v => TLBEntry03_ref.(write_to) v s) (TLBEntry03_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry02" then option_map (fun v => TLBEntry02_ref.(write_to) v s) (TLBEntry02_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry01" then option_map (fun v => TLBEntry01_ref.(write_to) v s) (TLBEntry01_ref.(of_regval) v) else + if string_dec reg_name "TLBEntry00" then option_map (fun v => TLBEntry00_ref.(write_to) v s) (TLBEntry00_ref.(of_regval) v) else + if string_dec reg_name "TLBXContext" then option_map (fun v => TLBXContext_ref.(write_to) v s) (TLBXContext_ref.(of_regval) v) else + if string_dec reg_name "TLBEntryHi" then option_map (fun v => TLBEntryHi_ref.(write_to) v s) (TLBEntryHi_ref.(of_regval) v) else + if string_dec reg_name "TLBWired" then option_map (fun v => TLBWired_ref.(write_to) v s) (TLBWired_ref.(of_regval) v) else + if string_dec reg_name "TLBPageMask" then option_map (fun v => TLBPageMask_ref.(write_to) v s) (TLBPageMask_ref.(of_regval) v) else + if string_dec reg_name "TLBContext" then option_map (fun v => TLBContext_ref.(write_to) v s) (TLBContext_ref.(of_regval) v) else + if string_dec reg_name "TLBEntryLo1" then option_map (fun v => TLBEntryLo1_ref.(write_to) v s) (TLBEntryLo1_ref.(of_regval) v) else + if string_dec reg_name "TLBEntryLo0" then option_map (fun v => TLBEntryLo0_ref.(write_to) v s) (TLBEntryLo0_ref.(of_regval) v) else + if string_dec reg_name "TLBRandom" then option_map (fun v => TLBRandom_ref.(write_to) v s) (TLBRandom_ref.(of_regval) v) else + if string_dec reg_name "TLBIndex" then option_map (fun v => TLBIndex_ref.(write_to) v s) (TLBIndex_ref.(of_regval) v) else + if string_dec reg_name "TLBProbe" then option_map (fun v => TLBProbe_ref.(write_to) v s) (TLBProbe_ref.(of_regval) v) else + if string_dec reg_name "NextPC" then option_map (fun v => NextPC_ref.(write_to) v s) (NextPC_ref.(of_regval) v) else + if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else + None. + +Definition register_accessors := (get_regval, set_regval). + + +Definition MR a r := monadR register_value a r exception. +Definition M a := monad register_value a exception. diff --git a/snapshots/coq/clean b/snapshots/coq/clean index 0d6f8785..c37bb40f 100755 --- a/snapshots/coq/clean +++ b/snapshots/coq/clean @@ -1,11 +1,12 @@ #!/bin/bash -if [ ! -d mips ]; then +if [ ! -d cheri-mips ]; then echo Run clean from the coq directory exit 1 fi set -ex -rm -f mips/*.vo +rm -f cheri-mips/*.{vo,glob} cheri-mips/.*.aux +rm -f riscv/*.{vo,glob} riscv/.*.aux cd lib/coq make clean diff --git a/snapshots/coq/lib/coq/Makefile b/snapshots/coq/lib/coq/Makefile index 97869e3c..a5f2874b 100644 --- a/snapshots/coq/lib/coq/Makefile +++ b/snapshots/coq/lib/coq/Makefile @@ -1,6 +1,6 @@ BBV_DIR=../../../bbv/theories -SRC=Sail2_prompt_monad.v Sail2_prompt.v Sail2_impl_base.v Sail2_instr_kinds.v Sail2_operators_bitlists.v Sail2_operators_mwords.v Sail2_operators.v Sail2_values.v Sail2_state_monad.v Sail2_state.v +SRC=Sail2_prompt_monad.v Sail2_prompt.v Sail2_impl_base.v Sail2_instr_kinds.v Sail2_operators_bitlists.v Sail2_operators_mwords.v Sail2_operators.v Sail2_values.v Sail2_state_monad.v Sail2_state.v Sail2_string.v Sail2_real.v COQ_LIBS = -R . Sail -R "$(BBV_DIR)" bbv diff --git a/snapshots/coq/lib/coq/Sail2_impl_base.v b/snapshots/coq/lib/coq/Sail2_impl_base.v index 639083f6..464c2902 100644 --- a/snapshots/coq/lib/coq/Sail2_impl_base.v +++ b/snapshots/coq/lib/coq/Sail2_impl_base.v @@ -1,6 +1,51 @@ (*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) +(* Sail *) +(* *) +(* Copyright (c) 2013-2017 *) +(* Kathyrn Gray *) +(* Shaked Flur *) +(* Stephen Kell *) +(* Gabriel Kerneis *) +(* Robert Norton-Wright *) +(* Christopher Pulte *) +(* Peter Sewell *) +(* Alasdair Armstrong *) +(* Brian Campbell *) +(* Thomas Bauereiss *) +(* Anthony Fox *) +(* Jon French *) +(* Dominic Mulligan *) +(* Stephen Kell *) +(* Mark Wassell *) +(* *) +(* All rights reserved. *) +(* *) +(* This software was developed by the University of Cambridge Computer *) +(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) +(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in *) +(* the documentation and/or other materials provided with the *) +(* distribution. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) +(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) +(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) +(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) +(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) +(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) +(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) +(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) +(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) +(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) +(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) +(* SUCH DAMAGE. *) (*========================================================================*) Require Import Sail2_instr_kinds. diff --git a/snapshots/coq/lib/coq/Sail2_instr_kinds.v b/snapshots/coq/lib/coq/Sail2_instr_kinds.v index 0145d8b3..c6fb866b 100644 --- a/snapshots/coq/lib/coq/Sail2_instr_kinds.v +++ b/snapshots/coq/lib/coq/Sail2_instr_kinds.v @@ -1,6 +1,51 @@ (*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) +(* Sail *) +(* *) +(* Copyright (c) 2013-2017 *) +(* Kathyrn Gray *) +(* Shaked Flur *) +(* Stephen Kell *) +(* Gabriel Kerneis *) +(* Robert Norton-Wright *) +(* Christopher Pulte *) +(* Peter Sewell *) +(* Alasdair Armstrong *) +(* Brian Campbell *) +(* Thomas Bauereiss *) +(* Anthony Fox *) +(* Jon French *) +(* Dominic Mulligan *) +(* Stephen Kell *) +(* Mark Wassell *) +(* *) +(* All rights reserved. *) +(* *) +(* This software was developed by the University of Cambridge Computer *) +(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) +(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in *) +(* the documentation and/or other materials provided with the *) +(* distribution. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) +(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) +(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) +(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) +(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) +(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) +(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) +(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) +(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) +(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) +(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) +(* SUCH DAMAGE. *) (*========================================================================*) @@ -99,7 +144,7 @@ Inductive barrier_kind := (* AArch64 barriers *) | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB - | Barrier_TM_COMMIT + (* | Barrier_TM_COMMIT*) (* MIPS barriers *) | Barrier_MIPS_SYNC (* RISC-V barriers *) @@ -108,6 +153,11 @@ Inductive barrier_kind := | Barrier_RISCV_r_r | Barrier_RISCV_rw_w | Barrier_RISCV_w_w + | Barrier_RISCV_w_rw + | Barrier_RISCV_rw_r + | Barrier_RISCV_r_w + | Barrier_RISCV_w_r + | Barrier_RISCV_tso | Barrier_RISCV_i (* X86 *) | Barrier_x86_MFENCE. @@ -133,6 +183,11 @@ instance (Show barrier_kind) | Barrier_RISCV_r_r -> "Barrier_RISCV_r_r" | Barrier_RISCV_rw_w -> "Barrier_RISCV_rw_w" | Barrier_RISCV_w_w -> "Barrier_RISCV_w_w" + | Barrier_RISCV_w_rw -> "Barrier_RISCV_w_rw" + | Barrier_RISCV_rw_r -> "Barrier_RISCV_rw_r" + | Barrier_RISCV_r_w -> "Barrier_RISCV_r_w" + | Barrier_RISCV_w_r -> "Barrier_RISCV_w_r" + | Barrier_RISCV_tso -> "Barrier_RISCV_tso" | Barrier_RISCV_i -> "Barrier_RISCV_i" | Barrier_x86_MFENCE -> "Barrier_x86_MFENCE" end @@ -155,11 +210,11 @@ Inductive instruction_kind := | IK_mem_read : read_kind -> instruction_kind | IK_mem_write : write_kind -> instruction_kind | IK_mem_rmw : (read_kind * write_kind) -> instruction_kind - | IK_branch (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address), + | IK_branch : unit -> instruction_kind (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address), indirect/computed-branch (single nia of kind NIA_indirect_address) and branch/jump (single nia of kind NIA_concrete_address) *) | IK_trans : trans_kind -> instruction_kind - | IK_simple : instruction_kind. + | IK_simple : unit -> instruction_kind. (* instance (Show instruction_kind) @@ -246,8 +301,13 @@ instance (EnumerationType barrier_kind) | Barrier_RISCV_r_r -> 15 | Barrier_RISCV_rw_w -> 16 | Barrier_RISCV_w_w -> 17 - | Barrier_RISCV_i -> 18 - | Barrier_x86_MFENCE -> 19 + | Barrier_RISCV_w_rw -> 18 + | Barrier_RISCV_rw_r -> 19 + | Barrier_RISCV_r_w -> 20 + | Barrier_RISCV_w_r -> 21 + | Barrier_RISCV_tso -> 22 + | Barrier_RISCV_i -> 23 + | Barrier_x86_MFENCE -> 24 end end *) diff --git a/snapshots/coq/lib/coq/Sail2_operators.v b/snapshots/coq/lib/coq/Sail2_operators.v index 5a8b1119..ab02c4a8 100644 --- a/snapshots/coq/lib/coq/Sail2_operators.v +++ b/snapshots/coq/lib/coq/Sail2_operators.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - Require Import Sail2_values. Require List. Import List.ListNotations. diff --git a/snapshots/coq/lib/coq/Sail2_operators_bitlists.v b/snapshots/coq/lib/coq/Sail2_operators_bitlists.v index b0240c4e..dbd8215c 100644 --- a/snapshots/coq/lib/coq/Sail2_operators_bitlists.v +++ b/snapshots/coq/lib/coq/Sail2_operators_bitlists.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - Require Import Sail2_values. Require Import Sail2_operators. diff --git a/snapshots/coq/lib/coq/Sail2_operators_mwords.v b/snapshots/coq/lib/coq/Sail2_operators_mwords.v index fba23071..7e4abe29 100644 --- a/snapshots/coq/lib/coq/Sail2_operators_mwords.v +++ b/snapshots/coq/lib/coq/Sail2_operators_mwords.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - Require Import Sail2_values. Require Import Sail2_operators. Require Import Sail2_prompt_monad. @@ -14,49 +9,71 @@ Require Import ZArith. Require Import Omega. Require Import Eqdep_dec. -Module Z_eq_dec. -Definition U := Z. -Definition eq_dec := Z.eq_dec. -End Z_eq_dec. -Module ZEqdep := DecidableEqDep (Z_eq_dec). +Fixpoint cast_positive (T : positive -> Type) (p q : positive) : T p -> p = q -> T q. +refine ( +match p, q with +| xH, xH => fun x _ => x +| xO p', xO q' => fun x e => cast_positive (fun x => T (xO x)) p' q' x _ +| xI p', xI q' => fun x e => cast_positive (fun x => T (xI x)) p' q' x _ +| _, _ => _ +end); congruence. +Defined. -Definition cast_mword {m n} (x : mword m) (eq : m = n) : mword n. -rewrite <- eq. -exact x. +Definition cast_T {T : Z -> Type} {m n} : forall (x : T m) (eq : m = n), T n. +refine (match m,n with +| Z0, Z0 => fun x _ => x +| Zneg p1, Zneg p2 => fun x e => cast_positive (fun p => T (Zneg p)) p1 p2 x _ +| Zpos p1, Zpos p2 => fun x e => cast_positive (fun p => T (Zpos p)) p1 p2 x _ +| _,_ => _ +end); congruence. Defined. -Lemma cast_mword_refl {m} {H:m = m} (x : mword m) : cast_mword x H = x. -rewrite (ZEqdep.UIP _ _ H eq_refl). -reflexivity. +Lemma cast_positive_refl : forall p T x (e : p = p), + cast_positive T p p x e = x. +induction p. +* intros. simpl. rewrite IHp; auto. +* intros. simpl. rewrite IHp; auto. +* reflexivity. +Qed. + +Lemma cast_T_refl {T : Z -> Type} {m} {H:m = m} (x : T m) : cast_T x H = x. +destruct m. +* reflexivity. +* simpl. rewrite cast_positive_refl. reflexivity. +* simpl. rewrite cast_positive_refl. reflexivity. Qed. -Definition autocast {m n} (x : mword m) `{H:ArithFact (m = n)} : mword n := - cast_mword x (use_ArithFact H). +Definition autocast {T : Z -> Type} {m n} (x : T m) `{H:ArithFact (m = n)} : T n := + cast_T x (use_ArithFact H). Definition autocast_m {rv e m n} (x : monad rv (mword m) e) `{H:ArithFact (m = n)} : monad rv (mword n) e := - x >>= fun x => returnm (cast_mword x (use_ArithFact H)). + x >>= fun x => returnm (cast_T x (use_ArithFact H)). -Definition cast_word {m n} (x : Word.word m) (eq : m = n) : Word.word n. -rewrite <- eq. -exact x. -Defined. +Definition cast_word {m n} (x : Word.word m) (eq : m = n) : Word.word n := + DepEqNat.nat_cast _ eq x. Lemma cast_word_refl {m} {H:m = m} (x : word m) : cast_word x H = x. rewrite (UIP_refl_nat _ H). -reflexivity. +apply nat_cast_same. Qed. -Definition mword_of_nat {m} (x : Word.word m) : mword (Z.of_nat m). -destruct m. -- exact x. -- simpl. rewrite SuccNat2Pos.id_succ. exact x. +Definition mword_of_nat {m} : Word.word m -> mword (Z.of_nat m). +refine (match m return word m -> mword (Z.of_nat m) with +| O => fun x => x +| S m' => fun x => nat_cast _ _ x +end). +rewrite SuccNat2Pos.id_succ. +reflexivity. Defined. -Definition cast_to_mword {m n} (x : Word.word m) (eq : Z.of_nat m = n) : mword n. -destruct n. -- constructor. -- rewrite <- eq. exact (mword_of_nat x). -- exfalso. destruct m; simpl in *; congruence. +Definition cast_to_mword {m n} (x : Word.word m) : Z.of_nat m = n -> mword n. +refine (match n return Z.of_nat m = n -> mword n with +| Z0 => fun _ => WO +| Zpos p => fun eq => cast_T (mword_of_nat x) eq +| Zneg p => _ +end). +intro eq. +exfalso. destruct m; simpl in *; congruence. Defined. (* @@ -155,16 +172,32 @@ Definition zero_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n Definition sign_extend {a} (v : mword a) (n : Z) `{ArithFact (n >= a)} : mword n := exts_vec n v. +Definition zeros (n : Z) `{ArithFact (n >= 0)} : mword n. +refine (cast_to_mword (Word.wzero (Z.to_nat n)) _). +unwrap_ArithFacts. +apply Z2Nat.id. +auto with zarith. +Defined. + Lemma truncate_eq {m n} : m >= 0 -> m <= n -> (Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat. intros. assert ((Z.to_nat m <= Z.to_nat n)%nat). { apply Z2Nat.inj_le; omega. } omega. Qed. +Lemma truncateLSB_eq {m n} : m >= 0 -> m <= n -> (Z.to_nat n = (Z.to_nat n - Z.to_nat m) + Z.to_nat m)%nat. +intros. +assert ((Z.to_nat m <= Z.to_nat n)%nat). +{ apply Z2Nat.inj_le; omega. } +omega. +Qed. Definition vector_truncate {n} (v : mword n) (m : Z) `{ArithFact (m >= 0)} `{ArithFact (m <= n)} : mword m := cast_to_mword (Word.split1 _ _ (cast_word (get_word v) (ltac:(unwrap_ArithFacts; apply truncate_eq; auto) : Z.to_nat n = Z.to_nat m + (Z.to_nat n - Z.to_nat m))%nat)) (ltac:(unwrap_ArithFacts; apply Z2Nat.id; omega) : Z.of_nat (Z.to_nat m) = m). +Definition vector_truncateLSB {n} (v : mword n) (m : Z) `{ArithFact (m >= 0)} `{ArithFact (m <= n)} : mword m := + cast_to_mword (Word.split2 _ _ (cast_word (get_word v) (ltac:(unwrap_ArithFacts; apply truncateLSB_eq; auto) : Z.to_nat n = (Z.to_nat n - Z.to_nat m) + Z.to_nat m)%nat)) (ltac:(unwrap_ArithFacts; apply Z2Nat.id; omega) : Z.of_nat (Z.to_nat m) = m). + Lemma concat_eq {a b} : a >= 0 -> b >= 0 -> Z.of_nat (Z.to_nat b + Z.to_nat a)%nat = a + b. intros. rewrite Nat2Z.inj_add. @@ -421,6 +454,20 @@ Definition sgteq_vec := sgteq_bv. *) +Definition eq_vec_dec {n} : forall (x y : mword n), {x = y} + {x <> y}. +refine (match n with +| Z0 => _ +| Zpos m => _ +| Zneg m => _ +end). +* simpl. apply Word.weq. +* simpl. apply Word.weq. +* simpl. destruct x. +Defined. + +Instance Decidable_eq_mword {n} : forall (x y : mword n), Decidable (x = y) := + Decidable_eq_from_dec eq_vec_dec. + Program Fixpoint reverse_endianness_word {n} (bits : word n) : word n := match n with | S (S (S (S (S (S (S (S m))))))) => @@ -436,3 +483,17 @@ Qed. Definition reverse_endianness {n} (bits : mword n) := with_word (P := id) reverse_endianness_word bits. Definition get_slice_int {a} `{ArithFact (a >= 0)} : Z -> Z -> Z -> mword a := get_slice_int_bv. + +Definition set_slice n m (v : mword n) x (w : mword m) : mword n := + update_subrange_vec_dec v (x + m - 1) x v. + +Definition set_slice_int len n lo (v : mword len) : Z := + let hi := lo + len - 1 in + (* We don't currently have a constraint on lo in the sail prelude, so let's + avoid one here. *) + if sumbool_of_bool (Z.gtb hi 0) then + let bs : mword (hi + 1) := mword_of_int n in + (int_of_mword true (update_subrange_vec_dec bs hi lo v)) + else n. + +Definition prerr_bits {a} (s : string) (bs : mword a) : unit := tt. diff --git a/snapshots/coq/lib/coq/Sail2_prompt.v b/snapshots/coq/lib/coq/Sail2_prompt.v index ab7d5bac..bd0d7750 100644 --- a/snapshots/coq/lib/coq/Sail2_prompt.v +++ b/snapshots/coq/lib/coq/Sail2_prompt.v @@ -1,12 +1,7 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - (*Require Import Sail_impl_base*) Require Import Sail2_values. Require Import Sail2_prompt_monad. - +Require Export ZArith.Zwf. Require Import List. Import ListNotations. (* @@ -35,7 +30,7 @@ match l with foreachM xs vars body end. -Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (from <= to)} `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e := +Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e := if sumbool_of_bool (from + off <=? to) then match n with | O => returnm vars @@ -43,7 +38,7 @@ Fixpoint foreach_ZM_up' {rv e Vars} from to step off n `{ArithFact (from <= to)} end else returnm vars. -Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (to <= from)} `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e := +Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> monad rv Vars e) {struct n} : monad rv Vars e := if sumbool_of_bool (to <=? from + off) then match n with | O => returnm vars @@ -51,9 +46,9 @@ Fixpoint foreach_ZM_down' {rv e Vars} from to step off n `{ArithFact (to <= from end else returnm vars. -Definition foreach_ZM_up {rv e Vars} from to step vars body `{ArithFact (from <= to)} `{ArithFact (0 < step)} := +Definition foreach_ZM_up {rv e Vars} from to step vars body `{ArithFact (0 < step)} := foreach_ZM_up' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body. -Definition foreach_ZM_down {rv e Vars} from to step vars body `{ArithFact (to <= from)} `{ArithFact (0 < step)} := +Definition foreach_ZM_down {rv e Vars} from to step vars body `{ArithFact (0 < step)} := foreach_ZM_down' (rv := rv) (e := e) (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body. (*declare {isabelle} termination_argument foreachM = automatic*) @@ -82,6 +77,35 @@ match b with | BU => undefined_bool tt end. +(* For termination of recursive functions. We don't name assertions, so use + the type class mechanism to find it. *) +Definition _limit_reduces {_limit} (_acc:Acc (Zwf 0) _limit) `{ArithFact (_limit >= 0)} : Acc (Zwf 0) (_limit - 1). +refine (Acc_inv _acc _). +destruct H. +red. +omega. +Defined. + +(* A version of well-foundedness of measures with a guard to ensure that + definitions can be reduced without inspecting proofs, based on a coq-club + thread featuring Barras, Gonthier and Gregoire, see + https://sympa.inria.fr/sympa/arc/coq-club/2007-07/msg00014.html *) + +Fixpoint pos_guard_wf {A:Type} {R:A -> A -> Prop} (p:positive) : well_founded R -> well_founded R := + match p with + | xH => fun wfR x => Acc_intro x (fun y _ => wfR y) + | xO p' => fun wfR x => let F := pos_guard_wf p' in Acc_intro x (fun y _ => F (F +wfR) y) + | xI p' => fun wfR x => let F := pos_guard_wf p' in Acc_intro x (fun y _ => F (F +wfR) y) + end. + +Definition Zwf_guarded (z:Z) : Acc (Zwf 0) z := + match z with + | Zpos p => pos_guard_wf p (Zwf_well_founded _) _ + | _ => Zwf_well_founded _ _ + end. + (*val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) -> ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e @@ -120,3 +144,15 @@ let rec untilM vars cond body = write_reg r1 r1_v >> write_reg r2 r2_v*) *) + +(* If we need to build an existential after a monadic operation, assume that + we can do it entirely from the type. *) + +Definition build_ex_m {rv e} {T:Type} (x:monad rv T e) {P:T -> Prop} `{H:forall x, ArithFact (P x)} : monad rv {x : T & ArithFact (P x)} e := + x >>= fun y => returnm (existT _ y (H y)). + +Definition projT1_m {rv e} {T:Type} {P:T -> Prop} (x: monad rv {x : T & P x} e) : monad rv T e := + x >>= fun y => returnm (projT1 y). + +Definition derive_m {rv e} {T:Type} {P Q:T -> Prop} (x : monad rv {x : T & P x} e) `{forall x, ArithFact (P x) -> ArithFact (Q x)} : monad rv {x : T & (ArithFact (Q x))} e := + x >>= fun y => returnm (build_ex (projT1 y)). diff --git a/snapshots/coq/lib/coq/Sail2_prompt_monad.v b/snapshots/coq/lib/coq/Sail2_prompt_monad.v index 43e873f7..2715b5e7 100644 --- a/snapshots/coq/lib/coq/Sail2_prompt_monad.v +++ b/snapshots/coq/lib/coq/Sail2_prompt_monad.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - Require Import String. (*Require Import Sail_impl_base*) Require Import Sail2_instr_kinds. diff --git a/snapshots/coq/lib/coq/Sail2_real.v b/snapshots/coq/lib/coq/Sail2_real.v new file mode 100644 index 00000000..e4e4316e --- /dev/null +++ b/snapshots/coq/lib/coq/Sail2_real.v @@ -0,0 +1,24 @@ +Require Export Rbase. +Require Import Reals. +Require Export ROrderedType. +Require Import Sail2_values. + +(* "Decidable" in a classical sense... *) +Instance Decidable_eq_real : forall (x y : R), Decidable (x = y) := + Decidable_eq_from_dec Req_dec. + +Definition realFromFrac (num denom : Z) : R := Rdiv (IZR num) (IZR denom). + +Definition gteq_real (x y : R) : bool := if Rge_dec x y then true else false. +Definition lteq_real (x y : R) : bool := if Rle_dec x y then true else false. +Definition gt_real (x y : R) : bool := if Rgt_dec x y then true else false. +Definition lt_real (x y : R) : bool := if Rlt_dec x y then true else false. + +(* Export select definitions from outside of Rbase *) +Definition powerRZ := powerRZ. +Definition Rabs := Rabs. +Definition sqrt := sqrt. + +(* Use flocq definitions, but without making the whole library a dependency. *) +Definition Zfloor (x : R) := (up x - 1)%Z. +Definition Zceil (x : R) := (- Zfloor (- x))%Z. diff --git a/snapshots/coq/lib/coq/Sail2_state.v b/snapshots/coq/lib/coq/Sail2_state.v index 404309e0..1d5cb342 100644 --- a/snapshots/coq/lib/coq/Sail2_state.v +++ b/snapshots/coq/lib/coq/Sail2_state.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - (*Require Import Sail_impl_base*) Require Import Sail2_values. Require Import Sail2_prompt_monad. diff --git a/snapshots/coq/lib/coq/Sail2_state_monad.v b/snapshots/coq/lib/coq/Sail2_state_monad.v index 5258c37a..c48db31b 100644 --- a/snapshots/coq/lib/coq/Sail2_state_monad.v +++ b/snapshots/coq/lib/coq/Sail2_state_monad.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - Require Import Sail2_instr_kinds. Require Import Sail2_values. (* diff --git a/snapshots/coq/lib/coq/Sail2_string.v b/snapshots/coq/lib/coq/Sail2_string.v new file mode 100644 index 00000000..0a00f8d7 --- /dev/null +++ b/snapshots/coq/lib/coq/Sail2_string.v @@ -0,0 +1,190 @@ +Require Import Sail2_values. + +Definition string_sub (s : string) (start : Z) (len : Z) : string := + String.substring (Z.to_nat start) (Z.to_nat len) s. + +Definition string_startswith s expected := + let prefix := String.substring 0 (String.length expected) s in + generic_eq prefix expected. + +Definition string_drop s (n : Z) `{ArithFact (n >= 0)} := + let n := Z.to_nat n in + String.substring n (String.length s - n) s. + +Definition string_take s (n : Z) `{ArithFact (n >= 0)} := + let n := Z.to_nat n in + String.substring 0 n s. + +Definition string_length s : {n : Z & ArithFact (n >= 0)} := + build_ex (Z.of_nat (String.length s)). + +Definition string_append := String.append. + +Local Open Scope char_scope. +Local Definition hex_char (c : Ascii.ascii) : option Z := +match c with +| "0" => Some 0 +| "1" => Some 1 +| "2" => Some 2 +| "3" => Some 3 +| "4" => Some 4 +| "5" => Some 5 +| "6" => Some 6 +| "7" => Some 7 +| "8" => Some 8 +| "9" => Some 9 +| "a" => Some 10 +| "b" => Some 11 +| "c" => Some 12 +| "d" => Some 13 +| "e" => Some 14 +| "f" => Some 15 +| _ => None +end. +Local Close Scope char_scope. +Local Fixpoint more_digits (s : string) (base : Z) (acc : Z) (len : nat) : Z * nat := +match s with +| EmptyString => (acc, len) +| String "_" t => more_digits t base acc (S len) +| String h t => + match hex_char h with + | None => (acc, len) + | Some i => + if i <? base + then more_digits t base (base * acc + i) (S len) + else (acc, len) + end +end. +Local Definition int_of (s : string) (base : Z) (len : nat) : option (Z * {n : Z & ArithFact (n >= 0)}) := +match s with +| EmptyString => None +| String h t => + match hex_char h with + | None => None + | Some i => + if i <? base + then + let (i, len') := more_digits t base i (S len) in + Some (i, build_ex (Z.of_nat len')) + else None + end +end. + +(* I've stuck closely to OCaml's int_of_string, because that's what's currently + used elsewhere. *) + +Definition maybe_int_of_prefix (s : string) : option (Z * {n : Z & ArithFact (n >= 0)}) := +match s with +| EmptyString => None +| String "0" (String ("x"|"X") t) => int_of t 16 2 +| String "0" (String ("o"|"O") t) => int_of t 8 2 +| String "0" (String ("b"|"B") t) => int_of t 2 2 +| String "0" (String "u" t) => int_of t 10 2 +| String "-" t => + match int_of t 10 1 with + | None => None + | Some (i,len) => Some (-i,len) + end +| _ => int_of s 10 0 +end. + +Definition maybe_int_of_string (s : string) : option Z := +match maybe_int_of_prefix s with +| None => None +| Some (i,len) => + if projT1 len =? projT1 (string_length s) + then Some i + else None +end. + +Fixpoint n_leading_spaces (s:string) : nat := + match s with + | EmptyString => 0 + | String " " t => S (n_leading_spaces t) + | _ => 0 + end. + +Definition opt_spc_matches_prefix s : option (unit * {n : Z & ArithFact (n >= 0)}) := + Some (tt, build_ex (Z.of_nat (n_leading_spaces s))). + +Definition spc_matches_prefix s : option (unit * {n : Z & ArithFact (n >= 0)}) := + match n_leading_spaces s with + | O => None + | S n => Some (tt, build_ex (Z.of_nat (S n))) + end. + +Definition hex_bits_n_matches_prefix sz `{ArithFact (sz >= 0)} s : option (mword sz * {n : Z & ArithFact (n >= 0)}) := + match maybe_int_of_prefix s with + | None => None + | Some (n, len) => + if andb (0 <=? n) (n <? pow 2 sz) + then Some (of_int sz n, len) + else None + end. + +Definition hex_bits_1_matches_prefix s := hex_bits_n_matches_prefix 1 s. +Definition hex_bits_2_matches_prefix s := hex_bits_n_matches_prefix 2 s. +Definition hex_bits_3_matches_prefix s := hex_bits_n_matches_prefix 3 s. +Definition hex_bits_4_matches_prefix s := hex_bits_n_matches_prefix 4 s. +Definition hex_bits_5_matches_prefix s := hex_bits_n_matches_prefix 5 s. +Definition hex_bits_6_matches_prefix s := hex_bits_n_matches_prefix 6 s. +Definition hex_bits_7_matches_prefix s := hex_bits_n_matches_prefix 7 s. +Definition hex_bits_8_matches_prefix s := hex_bits_n_matches_prefix 8 s. +Definition hex_bits_9_matches_prefix s := hex_bits_n_matches_prefix 9 s. +Definition hex_bits_10_matches_prefix s := hex_bits_n_matches_prefix 10 s. +Definition hex_bits_11_matches_prefix s := hex_bits_n_matches_prefix 11 s. +Definition hex_bits_12_matches_prefix s := hex_bits_n_matches_prefix 12 s. +Definition hex_bits_13_matches_prefix s := hex_bits_n_matches_prefix 13 s. +Definition hex_bits_14_matches_prefix s := hex_bits_n_matches_prefix 14 s. +Definition hex_bits_15_matches_prefix s := hex_bits_n_matches_prefix 15 s. +Definition hex_bits_16_matches_prefix s := hex_bits_n_matches_prefix 16 s. +Definition hex_bits_17_matches_prefix s := hex_bits_n_matches_prefix 17 s. +Definition hex_bits_18_matches_prefix s := hex_bits_n_matches_prefix 18 s. +Definition hex_bits_19_matches_prefix s := hex_bits_n_matches_prefix 19 s. +Definition hex_bits_20_matches_prefix s := hex_bits_n_matches_prefix 20 s. +Definition hex_bits_21_matches_prefix s := hex_bits_n_matches_prefix 21 s. +Definition hex_bits_22_matches_prefix s := hex_bits_n_matches_prefix 22 s. +Definition hex_bits_23_matches_prefix s := hex_bits_n_matches_prefix 23 s. +Definition hex_bits_24_matches_prefix s := hex_bits_n_matches_prefix 24 s. +Definition hex_bits_25_matches_prefix s := hex_bits_n_matches_prefix 25 s. +Definition hex_bits_26_matches_prefix s := hex_bits_n_matches_prefix 26 s. +Definition hex_bits_27_matches_prefix s := hex_bits_n_matches_prefix 27 s. +Definition hex_bits_28_matches_prefix s := hex_bits_n_matches_prefix 28 s. +Definition hex_bits_29_matches_prefix s := hex_bits_n_matches_prefix 29 s. +Definition hex_bits_30_matches_prefix s := hex_bits_n_matches_prefix 30 s. +Definition hex_bits_31_matches_prefix s := hex_bits_n_matches_prefix 31 s. +Definition hex_bits_32_matches_prefix s := hex_bits_n_matches_prefix 32 s. +Definition hex_bits_33_matches_prefix s := hex_bits_n_matches_prefix 33 s. +Definition hex_bits_48_matches_prefix s := hex_bits_n_matches_prefix 48 s. +Definition hex_bits_64_matches_prefix s := hex_bits_n_matches_prefix 64 s. + +Local Definition zero : N := Ascii.N_of_ascii "0". +Local Fixpoint string_of_N (limit : nat) (n : N) (acc : string) : string := +match limit with +| O => acc +| S limit' => + let (d,m) := N.div_eucl n 10 in + let acc := String (Ascii.ascii_of_N (m + zero)) acc in + if N.ltb 0 d then string_of_N limit' d acc else acc +end. +Local Fixpoint pos_limit p := +match p with +| xH => S O +| xI p | xO p => S (pos_limit p) +end. +Definition string_of_int (z : Z) : string := +match z with +| Z0 => "0" +| Zpos p => string_of_N (pos_limit p) (Npos p) "" +| Zneg p => String "-" (string_of_N (pos_limit p) (Npos p) "") +end. + +Definition decimal_string_of_bv {a} `{Bitvector a} (bv : a) : string := + match unsigned bv with + | None => "?" + | Some i => string_of_int i + end. + +Definition decimal_string_of_bits {n} (bv : mword n) : string := decimal_string_of_bv bv. + + diff --git a/snapshots/coq/lib/coq/Sail2_values.v b/snapshots/coq/lib/coq/Sail2_values.v index f1f5f1de..219a6f84 100644 --- a/snapshots/coq/lib/coq/Sail2_values.v +++ b/snapshots/coq/lib/coq/Sail2_values.v @@ -1,8 +1,3 @@ -(*========================================================================*) -(* Copyright (c) 2018 Sail contributors. *) -(* This material is provided for anonymous review purposes only. *) -(*========================================================================*) - (* Version of sail_values.lem that uses Lems machine words library *) (*Require Import Sail_impl_base*) @@ -13,10 +8,19 @@ Require Import bbv.Word. Require Export List. Require Export Sumbool. Require Export DecidableClass. +Require Import Eqdep_dec. +Require Export Zeuclid. Import ListNotations. Open Scope Z. +Module Z_eq_dec. +Definition U := Z. +Definition eq_dec := Z.eq_dec. +End Z_eq_dec. +Module ZEqdep := DecidableEqDep (Z_eq_dec). + + (* Constraint solving basics. A HintDb which unfolding hints and lemmata can be added to, and a typeclass to wrap constraint arguments in to trigger automatic solving. *) @@ -26,7 +30,19 @@ Lemma use_ArithFact {P} `(ArithFact P) : P. apply fact. Defined. -Definition build_ex (n:Z) {P:Z -> Prop} `{H:ArithFact (P n)} : {x : Z & ArithFact (P x)} := +(* Allow setoid rewriting through ArithFact *) +Require Import Coq.Classes.Morphisms. +Require Import Coq.Program.Basics. +Require Import Coq.Program.Tactics. +Section Morphism. +Local Obligation Tactic := try solve [simpl_relation | firstorder auto]. + +Global Program Instance ArithFact_iff_morphism : + Proper (iff ==> iff) ArithFact. +End Morphism. + + +Definition build_ex {T:Type} (n:T) {P:T -> Prop} `{H:ArithFact (P n)} : {x : T & ArithFact (P x)} := existT _ n H. Definition generic_eq {T:Type} (x y:T) `{Decidable (x = y)} := Decidable_witness. @@ -59,18 +75,59 @@ Instance Decidable_eq_from_dec {T:Type} (eqdec: forall x y : T, {x = y} + {x <> Decidable_witness := proj1_sig (bool_of_sumbool (eqdec x y)) }. destruct (eqdec x y); simpl; split; congruence. +Defined. + +Instance Decidable_eq_string : forall (x y : string), Decidable (x = y) := + Decidable_eq_from_dec String.string_dec. + +Instance Decidable_eq_pair {A B : Type} `(DA : forall x y : A, Decidable (x = y), DB : forall x y : B, Decidable (x = y)) : forall x y : A*B, Decidable (x = y) := +{ Decidable_witness := andb (@Decidable_witness _ (DA (fst x) (fst y))) +(@Decidable_witness _ (DB (snd x) (snd y))) }. +destruct x as [x1 x2]. +destruct y as [y1 y2]. +simpl. +destruct (DA x1 y1) as [b1 H1]; +destruct (DB x2 y2) as [b2 H2]; +simpl. +split. +* intro H. + apply Bool.andb_true_iff in H. + destruct H as [H1b H2b]. + apply H1 in H1b. + apply H2 in H2b. + congruence. +* intro. inversion H. + subst. + apply Bool.andb_true_iff. + tauto. Qed. +Definition generic_dec {T:Type} (x y:T) `{Decidable (x = y)} : {x = y} + {x <> y}. +refine ((if Decidable_witness as b return (b = true <-> x = y -> _) then fun H' => _ else fun H' => _) Decidable_spec). +* left. tauto. +* right. intuition. +Defined. + +(* Used by generated code that builds Decidable equality instances for records. *) +Ltac cmp_record_field x y := + let H := fresh "H" in + case (generic_dec x y); + intro H; [ | + refine (Build_Decidable _ false _); + split; [congruence | intros Z; destruct H; injection Z; auto] + ]. + + (* Project away range constraints in comparisons *) -Definition ltb_range_l {P} (l : sigT P) r := Z.ltb (projT1 l) r. -Definition leb_range_l {P} (l : sigT P) r := Z.leb (projT1 l) r. -Definition gtb_range_l {P} (l : sigT P) r := Z.gtb (projT1 l) r. -Definition geb_range_l {P} (l : sigT P) r := Z.geb (projT1 l) r. -Definition ltb_range_r {P} l (r : sigT P) := Z.ltb l (projT1 r). -Definition leb_range_r {P} l (r : sigT P) := Z.leb l (projT1 r). -Definition gtb_range_r {P} l (r : sigT P) := Z.gtb l (projT1 r). -Definition geb_range_r {P} l (r : sigT P) := Z.geb l (projT1 r). +Definition ltb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.ltb (projT1 l) r. +Definition leb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.leb (projT1 l) r. +Definition gtb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.gtb (projT1 l) r. +Definition geb_range_l {lo hi} (l : {x & ArithFact (lo <= x /\ x <= hi)}) r := Z.geb (projT1 l) r. +Definition ltb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.ltb l (projT1 r). +Definition leb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.leb l (projT1 r). +Definition gtb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.gtb l (projT1 r). +Definition geb_range_r {lo hi} l (r : {x & ArithFact (lo <= x /\ x <= hi)}) := Z.geb l (projT1 r). Definition ii := Z. Definition nn := nat. @@ -78,7 +135,13 @@ Definition nn := nat. (*val pow : Z -> Z -> Z*) Definition pow m n := m ^ n. -Definition pow2 n := pow 2 n. +Program Definition pow2 n : {z : Z & ArithFact (2 ^ n <= z <= 2 ^ n)} := existT _ (pow 2 n) _. +Next Obligation. +constructor. +unfold pow. +auto using Z.le_refl. +Qed. + (* Definition inline lt := (<) Definition inline gt := (>) @@ -111,7 +174,15 @@ Definition negate_real r := realNegate r Definition abs_real r := realAbs r Definition power_real b e := realPowInteger b e*) +Definition print_endline (_ : string) : unit := tt. +Definition prerr_endline (_ : string) : unit := tt. +Definition prerr (_ : string) : unit := tt. Definition print_int (_ : string) (_ : Z) : unit := tt. +Definition prerr_int (_ : string) (_ : Z) : unit := tt. +Definition putchar (_ : Z) : unit := tt. + +Definition shl_int := Z.shiftl. +Definition shr_int := Z.shiftr. (* Definition or_bool l r := (l || r) @@ -238,9 +309,29 @@ f_equal. auto using just_list_length. Qed. +Fixpoint member_Z_list (x : Z) (l : list Z) : bool := +match l with +| [] => false +| h::t => if x =? h then true else member_Z_list x t +end. + +Lemma member_Z_list_In {x l} : member_Z_list x l = true <-> In x l. +induction l. +* simpl. split. congruence. tauto. +* simpl. destruct (x =? a) eqn:H. + + rewrite Z.eqb_eq in H. subst. tauto. + + rewrite Z.eqb_neq in H. split. + - intro Heq. right. apply IHl. assumption. + - intros [bad | good]. congruence. apply IHl. assumption. +Qed. + (*** Bits *) Inductive bitU := B0 | B1 | BU. +Scheme Equality for bitU. +Instance Decidable_eq_bit : forall (x y : bitU), Decidable (x = y) := + Decidable_eq_from_dec bitU_eq_dec. + Definition showBitU b := match b with | B0 => "O" @@ -829,42 +920,42 @@ val make_the_value : forall n. Z -> itself n Definition inline make_the_value x := the_value *) -Fixpoint bitlistFromWord {n} w := +Fixpoint bitlistFromWord_rev {n} w := match w with | WO => [] -| WS b w => b :: bitlistFromWord w +| WS b w => b :: bitlistFromWord_rev w end. +Definition bitlistFromWord {n} w := + List.rev (@bitlistFromWord_rev n w). -Fixpoint wordFromBitlist l : word (length l) := +Fixpoint wordFromBitlist_rev l : word (length l) := match l with | [] => WO -| b::t => WS b (wordFromBitlist t) +| b::t => WS b (wordFromBitlist_rev t) end. +Definition wordFromBitlist l : word (length l) := + nat_cast _ (List.rev_length l) (wordFromBitlist_rev (List.rev l)). Local Open Scope nat. -Program Definition fit_bbv_word {n m} (w : word n) : word m := -match Nat.compare m n with -| Gt => extz w (m - n) -| Eq => w -| Lt => split2 (n - m) m w -end. -Next Obligation. -symmetry in Heq_anonymous. -apply nat_compare_gt in Heq_anonymous. -omega. -Defined. -Next Obligation. -symmetry in Heq_anonymous. -apply nat_compare_eq in Heq_anonymous. -omega. -Defined. -Next Obligation. +Fixpoint nat_diff {T : nat -> Type} n m {struct n} : +forall + (lt : forall p, T n -> T (n + p)) + (eq : T m -> T m) + (gt : forall p, T (m + p) -> T m), T n -> T m := +(match n, m return (forall p, T n -> T (n + p)) -> (T m -> T m) -> (forall p, T (m + p) -> T m) -> T n -> T m with +| O, O => fun lt eq gt => eq +| S n', O => fun lt eq gt => gt _ +| O, S m' => fun lt eq gt => lt _ +| S n', S m' => @nat_diff (fun x => T (S x)) n' m' +end). + +Definition fit_bbv_word {n m} : word n -> word m := +nat_diff n m + (fun p w => nat_cast _ (Nat.add_comm _ _) (extz w p)) + (fun w => w) + (fun p w => split2 _ _ (nat_cast _ (Nat.add_comm _ _) w)). -symmetry in Heq_anonymous. -apply nat_compare_lt in Heq_anonymous. -omega. -Defined. Local Close Scope nat. (*** Bitvectors *) @@ -896,12 +987,10 @@ Class ReasonableSize (a : Z) : Prop := { isPositive : a >= 0 }. -Hint Resolve -> Z.gtb_lt Z.geb_le Z.ltb_lt Z.leb_le : zbool. -Hint Resolve <- Z.ge_le_iff Z.gt_lt_iff : zbool. - (* Omega doesn't know about In, but can handle disjunctions. *) Ltac unfold_In := repeat match goal with +| H:context [member_Z_list _ _ = true] |- _ => rewrite member_Z_list_In in H | H:context [In ?x (?y :: ?t)] |- _ => change (In x (y :: t)) with (y = x \/ In x t) in H | H:context [In ?x []] |- _ => change (In x []) with False in H end. @@ -912,6 +1001,11 @@ end. Ltac not_Z ty := match ty with Z => fail 1 | _ => idtac end. Ltac clear_non_Z_defns := repeat match goal with H := _ : ?X |- _ => not_Z X; clearbody H end. +Ltac clear_irrelevant_defns := +repeat match goal with X := _ |- _ => + match goal with |- context[X] => idtac end || + match goal with _ : context[X] |- _ => idtac end || clear X +end. Lemma ArithFact_mword (a : Z) (w : mword a) : ArithFact (a >= 0). constructor. @@ -921,7 +1015,7 @@ auto using Z.le_ge, Zle_0_pos. destruct w. Qed. Ltac unwrap_ArithFacts := - repeat match goal with H:(ArithFact _) |- _ => let H' := fresh H in case H as [H'] end. + repeat match goal with H:(ArithFact _) |- _ => let H' := fresh H in case H as [H']; clear H end. Ltac unbool_comparisons := repeat match goal with | H:context [Z.geb _ _] |- _ => rewrite Z.geb_leb in H @@ -933,23 +1027,50 @@ Ltac unbool_comparisons := | H:context [Z.ltb _ _ = false] |- _ => rewrite Z.ltb_ge in H | H:context [Z.eqb _ _ = false] |- _ => rewrite Z.eqb_neq in H | H:context [orb _ _ = true] |- _ => rewrite Bool.orb_true_iff in H - | H:context [andb _ _ = true] |- _ => apply andb_prop in H + | H:context [orb _ _ = false] |- _ => rewrite Bool.orb_false_iff in H + | H:context [andb _ _ = true] |- _ => rewrite Bool.andb_true_iff in H + | H:context [andb _ _ = false] |- _ => rewrite Bool.andb_false_iff in H + | H:context [negb _ = true] |- _ => rewrite Bool.negb_true_iff in H + | H:context [negb _ = false] |- _ => rewrite Bool.negb_false_iff in H | H:context [generic_eq _ _ = true] |- _ => apply generic_eq_true in H | H:context [generic_eq _ _ = false] |- _ => apply generic_eq_false in H | H:context [generic_neq _ _ = true] |- _ => apply generic_neq_true in H | H:context [generic_neq _ _ = false] |- _ => apply generic_neq_false in H end. + (* Split up dependent pairs to get at proofs of properties *) Ltac extract_properties := + (* Properties of local definitions *) repeat match goal with H := (projT1 ?X) |- _ => let x := fresh "x" in let Hx := fresh "Hx" in destruct X as [x Hx] in *; change (projT1 (existT _ x Hx)) with x in *; unfold H in * end; + (* Properties in the goal *) repeat match goal with |- context [projT1 ?X] => let x := fresh "x" in let Hx := fresh "Hx" in destruct X as [x Hx] in *; + change (projT1 (existT _ x Hx)) with x in * end; + (* Properties with proofs embedded by build_ex; uses revert/generalize + rather than destruct because it seemed to be more efficient, but + some experimentation would be needed to be sure. + repeat ( + match goal with H:context [@build_ex ?T ?n ?P ?prf] |- _ => + let x := fresh "x" in + let zz := constr:(@build_ex T n P prf) in + revert dependent H(*; generalize zz; intros*) + end; + match goal with |- context [@build_ex ?T ?n ?P ?prf] => + let x := fresh "x" in + let zz := constr:(@build_ex T n P prf) in + generalize zz as x + end; + intros).*) + repeat match goal with _:context [projT1 ?X] |- _ => + let x := fresh "x" in + let Hx := fresh "Hx" in + destruct X as [x Hx] in *; change (projT1 (existT _ x Hx)) with x in * end. (* TODO: hyps, too? *) Ltac reduce_list_lengths := @@ -972,26 +1093,110 @@ Ltac dump_context := | H:=?X |- _ => idtac H ":=" X; fail | H:?X |- _ => idtac H ":" X; fail end; match goal with |- ?X => idtac "Goal:" X end. -Ltac solve_arithfact := +Ltac split_cases := + repeat match goal with + |- context [match ?X with _ => _ end] => destruct X + end. +Lemma True_left {P:Prop} : (True /\ P) <-> P. +tauto. +Qed. +Lemma True_right {P:Prop} : (P /\ True) <-> P. +tauto. +Qed. + +(* Turn exists into metavariables like eexists, except put in dummy values when + the variable is unused. This is used so that we can use eauto with a low + search bound that doesn't include the exists. (Not terribly happy with + how this works...) *) +Ltac drop_exists := +repeat + match goal with |- @ex Z ?p => + let a := eval hnf in (p 0) in + let b := eval hnf in (p 1) in + match a with b => exists 0 | _ => eexists end + end. +(* + match goal with |- @ex Z (fun x => @?p x) => + let xx := fresh "x" in + evar (xx : Z); + let a := eval hnf in (p xx) in + match a with context [xx] => eexists | _ => exists 0 end; + instantiate (xx := 0); + clear xx + end. +*) + +(* The linear solver doesn't like existentials. *) +Ltac destruct_exists := + repeat match goal with H:@ex Z _ |- _ => destruct H end. + +Ltac prepare_for_solver := (*dump_context;*) + clear_irrelevant_defns; clear_non_Z_defns; + autounfold with sail in * |- *; (* You can add Hint Unfold ... : sail to let omega see through fns *) + split_cases; extract_properties; repeat match goal with w:mword ?n |- _ => apply ArithFact_mword in w end; unwrap_ArithFacts; - unfold_In; - autounfold with sail in * |- *; (* You can add Hint Unfold ... : sail to let omega see through fns *) + destruct_exists; unbool_comparisons; + unfold_In; (* after unbool_comparisons to deal with && and || *) reduce_list_lengths; reduce_pow; + (* omega doesn't cope well with extra "True"s in the goal *) + repeat setoid_rewrite True_left; + repeat setoid_rewrite True_right. + +Lemma trivial_range {x : Z} : ArithFact (x <= x /\ x <= x). +constructor. +auto with zarith. +Qed. + +Lemma ArithFact_self_proof {P} : forall x : {y : Z & ArithFact (P y)}, ArithFact (P (projT1 x)). +intros [x H]. +exact H. +Qed. + +Ltac fill_in_evar_eq := + match goal with |- ArithFact (?x = ?y) => + (is_evar x || is_evar y); + (* compute to allow projections to remove proofs that might not be allowed in the evar *) +(* Disabled because cbn may reduce definitions, even after clearbody + let x := eval cbn in x in + let y := eval cbn in y in*) + idtac "Warning: unknown equality constraint"; constructor; exact (eq_refl _ : x = y) end. + +Ltac solve_arithfact := +(* Attempt a simple proof first to avoid lengthy preparation steps (especially + as the large proof terms can upset subsequent proofs). *) +intros; (* To solve implications for derive_m *) +try (exact trivial_range); +try fill_in_evar_eq; +try match goal with |- context [projT1 ?X] => apply (ArithFact_self_proof X) end; +try (constructor; omega); +prepare_for_solver; (*dump_context;*) - solve [apply ArithFact_mword; assumption - | constructor; omega with Z - (* The datatypes hints give us some list handling, esp In *) - | constructor; auto with datatypes zbool zarith sail]. -Hint Extern 0 (ArithFact _) => solve_arithfact : typeclass_instances. + solve + [ match goal with |- ArithFact (?x _) => is_evar x; idtac "Warning: unknown constraint"; constructor; exact (I : (fun _ => True) _) end + | apply ArithFact_mword; assumption + | constructor; omega with Z + (* Try sail hints before dropping the existential *) + | constructor; eauto 3 with zarith sail + (* The datatypes hints give us some list handling, esp In *) + | constructor; drop_exists; eauto 3 with datatypes zarith sail + | constructor; idtac "Unable to solve constraint"; dump_context; fail + ]. +(* Add an indirection so that you can redefine run_solver to fail to get + slow running constraints into proof mode. *) +Ltac run_solver := solve_arithfact. +Hint Extern 0 (ArithFact _) => run_solver : typeclass_instances. Hint Unfold length_mword : sail. +Definition neq_atom (x : Z) (y : Z) : bool := negb (Z.eqb x y). +Hint Unfold neq_atom : sail. + Lemma ReasonableSize_witness (a : Z) (w : mword a) : ReasonableSize a. constructor. destruct a. @@ -1002,6 +1207,10 @@ Qed. Hint Extern 0 (ReasonableSize ?A) => (unwrap_ArithFacts; solve [apply ReasonableSize_witness; assumption | constructor; omega]) : typeclass_instances. +Definition to_range (x : Z) : {y : Z & ArithFact (x <= y <= x)} := build_ex x. + + + Instance mword_Bitvector {a : Z} `{ArithFact (a >= 0)} : (Bitvector (mword a)) := { bits_of v := List.map bitU_of_bool (bitlistFromWord (get_word v)); of_bits v := option_map (fun bl => to_word isPositive (fit_bbv_word (wordFromBitlist bl))) (just_list (List.map bool_of_bitU v)); @@ -1335,7 +1544,7 @@ Fixpoint foreach_Z' {Vars} from to step n (vars : Vars) (body : Z -> Vars -> Var Definition foreach_Z {Vars} from to step vars body := foreach_Z' (Vars := Vars) from to step (S (Z.abs_nat (from - to))) vars body. -Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (from <= to)} `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> Vars) {struct n} : Vars := +Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (0 <= off)} (vars : Vars) (body : forall (z : Z) `(ArithFact (from <= z <= to)), Vars -> Vars) {struct n} : Vars := if sumbool_of_bool (from + off <=? to) then match n with | O => vars @@ -1343,7 +1552,7 @@ Fixpoint foreach_Z_up' {Vars} from to step off n `{ArithFact (from <= to)} `{Ari end else vars. -Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (to <= from)} `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> Vars) {struct n} : Vars := +Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (0 < step)} `{ArithFact (off <= 0)} (vars : Vars) (body : forall (z : Z) `(ArithFact (to <= z <= from)), Vars -> Vars) {struct n} : Vars := if sumbool_of_bool (to <=? from + off) then match n with | O => vars @@ -1351,9 +1560,9 @@ Fixpoint foreach_Z_down' {Vars} from to step off n `{ArithFact (to <= from)} `{A end else vars. -Definition foreach_Z_up {Vars} from to step vars body `{ArithFact (from <= to)} `{ArithFact (0 < step)} := +Definition foreach_Z_up {Vars} from to step vars body `{ArithFact (0 < step)} := foreach_Z_up' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body. -Definition foreach_Z_down {Vars} from to step vars body `{ArithFact (to <= from)} `{ArithFact (0 < step)} := +Definition foreach_Z_down {Vars} from to step vars body `{ArithFact (0 < step)} := foreach_Z_down' (Vars := Vars) from to step 0 (S (Z.abs_nat (from - to))) vars body. (*val while : forall vars. vars -> (vars -> bool) -> (vars -> vars) -> vars @@ -1446,8 +1655,8 @@ end (* Arithmetic functions which return proofs that match the expected Sail types in smt.sail. *) -Definition div_with_eq n m : {o : Z & ArithFact (o = Z.quot n m)} := build_ex (Z.quot n m). -Definition mod_with_eq n m : {o : Z & ArithFact (o = Z.rem n m)} := build_ex (Z.rem n m). +Definition ediv_with_eq n m : {o : Z & ArithFact (o = ZEuclid.div n m)} := build_ex (ZEuclid.div n m). +Definition emod_with_eq n m : {o : Z & ArithFact (o = ZEuclid.modulo n m)} := build_ex (ZEuclid.modulo n m). Definition abs_with_eq n : {o : Z & ArithFact (o = Z.abs n)} := build_ex (Z.abs n). (* Similarly, for ranges (currently in MIPS) *) @@ -1559,6 +1768,20 @@ Qed. Definition list_of_vec {A n} (v : vec A n) : list A := projT1 v. +Definition vec_eq_dec {T n} (D : forall x y : T, {x = y} + {x <> y}) (x y : vec T n) : + {x = y} + {x <> y}. +refine (if List.list_eq_dec D (projT1 x) (projT1 y) then left _ else right _). +* apply eq_sigT_hprop; auto using ZEqdep.UIP. +* contradict n0. rewrite n0. reflexivity. +Defined. + +Instance Decidable_eq_vec {T : Type} {n} `(DT : forall x y : T, Decidable (x = y)) : + forall x y : vec T n, Decidable (x = y) := { + Decidable_witness := proj1_sig (bool_of_sumbool (vec_eq_dec (fun x y => generic_dec x y) x y)) +}. +destruct (vec_eq_dec _ x y); simpl; split; congruence. +Defined. + Program Definition vec_of_list {A} n (l : list A) : option (vec A n) := if sumbool_of_bool (n =? length_list l) then Some (existT _ l _) else None. Next Obligation. @@ -1573,4 +1796,17 @@ Definition map_bind {A B} (f : A -> option B) (a : option A) : option B := match a with | Some a' => f a' | None => None -end.
\ No newline at end of file +end. + +Definition sub_nat (x : Z) `{ArithFact (x >= 0)} (y : Z) `{ArithFact (y >= 0)} : + {z : Z & ArithFact (z >= 0)} := + let z := x - y in + if sumbool_of_bool (z >=? 0) then build_ex z else build_ex 0. + +Definition min_nat (x : Z) `{ArithFact (x >= 0)} (y : Z) `{ArithFact (y >= 0)} : + {z : Z & ArithFact (z >= 0)} := + build_ex (Z.min x y). + +Definition max_nat (x : Z) `{ArithFact (x >= 0)} (y : Z) `{ArithFact (y >= 0)} : + {z : Z & ArithFact (z >= 0)} := + build_ex (Z.max x y). diff --git a/snapshots/coq/mips/mips_types.v b/snapshots/coq/mips/mips_types.v deleted file mode 100644 index 12d7d6cd..00000000 --- a/snapshots/coq/mips/mips_types.v +++ /dev/null @@ -1,1441 +0,0 @@ -(*Generated by Sail from mips.*) -Require Import Sail2_instr_kinds. -Require Import Sail2_values. -Require Import Sail2_operators_mwords. -Require Import Sail2_prompt_monad. -Require Import Sail2_prompt. -Require Import Sail2_state. -Definition bits (n : Z) : Type := mword n. - - - -Inductive exception := - ISAException : unit -> exception - | Error_not_implemented : string -> exception - | Error_misaligned_access : unit -> exception - | Error_EBREAK : unit -> exception - | Error_internal_error : unit -> exception. -Arguments exception : clear implicits. - - - -Record CauseReg := { CauseReg_CauseReg_chunk_0 : mword 32; }. -Notation "{[ r 'with' 'CauseReg_CauseReg_chunk_0' := e ]}" := ({| CauseReg_CauseReg_chunk_0 := e |}). - -Record StatusReg := { StatusReg_StatusReg_chunk_0 : mword 32; }. -Notation "{[ r 'with' 'StatusReg_StatusReg_chunk_0' := e ]}" := ({| StatusReg_StatusReg_chunk_0 := e |}). - -Record TLBEntryLoReg := { TLBEntryLoReg_TLBEntryLoReg_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'TLBEntryLoReg_TLBEntryLoReg_chunk_0' := e ]}" := ({| TLBEntryLoReg_TLBEntryLoReg_chunk_0 := e |}). - -Record TLBEntryHiReg := { TLBEntryHiReg_TLBEntryHiReg_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'TLBEntryHiReg_TLBEntryHiReg_chunk_0' := e ]}" := ({| TLBEntryHiReg_TLBEntryHiReg_chunk_0 := e |}). - -Record ContextReg := { ContextReg_ContextReg_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'ContextReg_ContextReg_chunk_0' := e ]}" := ({| ContextReg_ContextReg_chunk_0 := e |}). - -Record XContextReg := { XContextReg_XContextReg_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'XContextReg_XContextReg_chunk_0' := e ]}" := ({| XContextReg_XContextReg_chunk_0 := e |}). - -Definition TLBIndexT : Type := bits 6. - -Record TLBEntry := { TLBEntry_TLBEntry_chunk_1 : mword 53; TLBEntry_TLBEntry_chunk_0 : mword 64; }. -Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_1' := e ]}" := ({| TLBEntry_TLBEntry_chunk_1 := e; TLBEntry_TLBEntry_chunk_0 := TLBEntry_TLBEntry_chunk_0 r |}). -Notation "{[ r 'with' 'TLBEntry_TLBEntry_chunk_0' := e ]}" := ({| TLBEntry_TLBEntry_chunk_0 := e; TLBEntry_TLBEntry_chunk_1 := TLBEntry_TLBEntry_chunk_1 r |}). - -Inductive Exception := - Interrupt - | TLBMod - | TLBL - | TLBS - | AdEL - | AdES - | Sys - | Bp - | ResI - | CpU - | Ov - | Tr - | C2E - | C2Trap - | XTLBRefillL - | XTLBRefillS - | XTLBInvL - | XTLBInvS - | MCheck. -Scheme Equality for Exception. -Instance Decidable_eq_Exception : forall (x y : Exception), Decidable (x = y) := -Decidable_eq_from_dec Exception_eq_dec. - - -Inductive MemAccessType := Instruction | LoadData | StoreData. -Scheme Equality for MemAccessType. -Instance Decidable_eq_MemAccessType : forall (x y : MemAccessType), Decidable (x = y) := -Decidable_eq_from_dec MemAccessType_eq_dec. - - -Inductive AccessLevel := User | Supervisor | Kernel. -Scheme Equality for AccessLevel. -Instance Decidable_eq_AccessLevel : forall (x y : AccessLevel), Decidable (x = y) := -Decidable_eq_from_dec AccessLevel_eq_dec. - - -Definition regno : Type := bits 5. - -Definition imm16 : Type := bits 16. - -Definition regregreg : Type := (regno * regno * regno). - -Definition regregimm16 : Type := (regno * regno * imm16). - -Inductive decode_failure := - no_matching_pattern | unsupported_instruction | illegal_instruction | internal_error. -Scheme Equality for decode_failure. -Instance Decidable_eq_decode_failure : forall (x y : decode_failure), Decidable (x = y) := -Decidable_eq_from_dec decode_failure_eq_dec. - - -Inductive Comparison := EQ' | NE | GE | GEU | GT' | LE | LT' | LTU. -Scheme Equality for Comparison. -Instance Decidable_eq_Comparison : forall (x y : Comparison), Decidable (x = y) := -Decidable_eq_from_dec Comparison_eq_dec. - - -Inductive WordType := B | H | W | D. -Scheme Equality for WordType. -Instance Decidable_eq_WordType : forall (x y : WordType), Decidable (x = y) := -Decidable_eq_from_dec WordType_eq_dec. - - -Inductive WordTypeUnaligned := WL | WR | DL | DR. -Scheme Equality for WordTypeUnaligned. -Instance Decidable_eq_WordTypeUnaligned : forall (x y : WordTypeUnaligned), Decidable (x = y) := -Decidable_eq_from_dec WordTypeUnaligned_eq_dec. - - -Inductive ast := - DADDIU : (regno * regno * imm16) -> ast - | DADDU : (regno * regno * regno) -> ast - | DADDI : (regno * regno * bits 16) -> ast - | DADD : (regno * regno * regno) -> ast - | ADD : (regno * regno * regno) -> ast - | ADDI : (regno * regno * bits 16) -> ast - | ADDU : (regno * regno * regno) -> ast - | ADDIU : (regno * regno * bits 16) -> ast - | DSUBU : (regno * regno * regno) -> ast - | DSUB : (regno * regno * regno) -> ast - | SUB : (regno * regno * regno) -> ast - | SUBU : (regno * regno * regno) -> ast - | AND : (regno * regno * regno) -> ast - | ANDI : (regno * regno * bits 16) -> ast - | OR : (regno * regno * regno) -> ast - | ORI : (regno * regno * bits 16) -> ast - | NOR : (regno * regno * regno) -> ast - | XOR : (regno * regno * regno) -> ast - | XORI : (regno * regno * bits 16) -> ast - | LUI : (regno * imm16) -> ast - | DSLL : (regno * regno * regno) -> ast - | DSLL32 : (regno * regno * regno) -> ast - | DSLLV : (regno * regno * regno) -> ast - | DSRA : (regno * regno * regno) -> ast - | DSRA32 : (regno * regno * regno) -> ast - | DSRAV : (regno * regno * regno) -> ast - | DSRL : (regno * regno * regno) -> ast - | DSRL32 : (regno * regno * regno) -> ast - | DSRLV : (regno * regno * regno) -> ast - | SLL : (regno * regno * regno) -> ast - | SLLV : (regno * regno * regno) -> ast - | SRA : (regno * regno * regno) -> ast - | SRAV : (regno * regno * regno) -> ast - | SRL : (regno * regno * regno) -> ast - | SRLV : (regno * regno * regno) -> ast - | SLT : (regno * regno * regno) -> ast - | SLTI : (regno * regno * bits 16) -> ast - | SLTU : (regno * regno * regno) -> ast - | SLTIU : (regno * regno * bits 16) -> ast - | MOVN : (regno * regno * regno) -> ast - | MOVZ : (regno * regno * regno) -> ast - | MFHI : regno -> ast - | MFLO : regno -> ast - | MTHI : regno -> ast - | MTLO : regno -> ast - | MUL : (regno * regno * regno) -> ast - | MULT : (regno * regno) -> ast - | MULTU : (regno * regno) -> ast - | DMULT : (regno * regno) -> ast - | DMULTU : (regno * regno) -> ast - | MADD : (regno * regno) -> ast - | MADDU : (regno * regno) -> ast - | MSUB : (regno * regno) -> ast - | MSUBU : (regno * regno) -> ast - | DIV : (regno * regno) -> ast - | DIVU : (regno * regno) -> ast - | DDIV : (regno * regno) -> ast - | DDIVU : (regno * regno) -> ast - | J : bits 26 -> ast - | JAL : bits 26 -> ast - | JR : regno -> ast - | JALR : (regno * regno) -> ast - | BEQ : (regno * regno * imm16 * bool * bool) -> ast - | BCMPZ : (regno * imm16 * Comparison * bool * bool) -> ast - | SYSCALL : unit -> ast - | BREAK : unit -> ast - | WAIT : unit -> ast - | TRAPREG : (regno * regno * Comparison) -> ast - | TRAPIMM : (regno * imm16 * Comparison) -> ast - | Load : (WordType * bool * bool * regno * regno * imm16) -> ast - | Store : (WordType * bool * regno * regno * imm16) -> ast - | LWL : (regno * regno * bits 16) -> ast - | LWR : (regno * regno * bits 16) -> ast - | SWL : (regno * regno * bits 16) -> ast - | SWR : (regno * regno * bits 16) -> ast - | LDL : (regno * regno * bits 16) -> ast - | LDR : (regno * regno * bits 16) -> ast - | SDL : (regno * regno * bits 16) -> ast - | SDR : (regno * regno * bits 16) -> ast - | CACHE : (regno * regno * bits 16) -> ast - | SYNC : unit -> ast - | MFC0 : (regno * regno * bits 3 * bool) -> ast - | HCF : unit -> ast - | MTC0 : (regno * regno * bits 3 * bool) -> ast - | TLBWI : unit -> ast - | TLBWR : unit -> ast - | TLBR : unit -> ast - | TLBP : unit -> ast - | RDHWR : (regno * regno) -> ast - | ERET : unit -> ast - | RI : unit -> ast. -Arguments ast : clear implicits. - - - -Inductive register_value := - Regval_vector : (Z * bool * list register_value) -> register_value - | Regval_list : list register_value -> register_value - | Regval_option : option register_value -> register_value - | Regval_CauseReg : CauseReg -> register_value - | Regval_ContextReg : ContextReg -> register_value - | Regval_StatusReg : StatusReg -> register_value - | Regval_TLBEntry : TLBEntry -> register_value - | Regval_TLBEntryHiReg : TLBEntryHiReg -> register_value - | Regval_TLBEntryLoReg : TLBEntryLoReg -> register_value - | Regval_XContextReg : XContextReg -> register_value - | Regval_vector_16_dec_bit : mword 16 -> register_value - | Regval_vector_1_dec_bit : mword 1 -> register_value - | Regval_vector_32_dec_bit : mword 32 -> register_value - | Regval_vector_3_dec_bit : mword 3 -> register_value - | Regval_vector_64_dec_bit : mword 64 -> register_value - | Regval_vector_6_dec_bit : mword 6 -> register_value - | Regval_vector_8_dec_bit : mword 8 -> register_value. -Arguments register_value : clear implicits. - - - -Record regstate := - { UART_RVALID : mword 1; - UART_RDATA : mword 8; - UART_WRITTEN : mword 1; - UART_WDATA : mword 8; - GPR : vec (mword 64) 32; - LO : mword 64; - HI : mword 64; - delayedPC : mword 64; - inBranchDelay : mword 1; - branchPending : mword 1; - CP0Status : StatusReg; - CP0ConfigK0 : mword 3; - CP0UserLocal : mword 64; - CP0HWREna : mword 32; - CP0Count : mword 32; - CP0BadVAddr : mword 64; - CP0LLAddr : mword 64; - CP0LLBit : mword 1; - CP0ErrorEPC : mword 64; - CP0EPC : mword 64; - CP0Cause : CauseReg; - CP0Compare : mword 32; - TLBEntry63 : TLBEntry; - TLBEntry62 : TLBEntry; - TLBEntry61 : TLBEntry; - TLBEntry60 : TLBEntry; - TLBEntry59 : TLBEntry; - TLBEntry58 : TLBEntry; - TLBEntry57 : TLBEntry; - TLBEntry56 : TLBEntry; - TLBEntry55 : TLBEntry; - TLBEntry54 : TLBEntry; - TLBEntry53 : TLBEntry; - TLBEntry52 : TLBEntry; - TLBEntry51 : TLBEntry; - TLBEntry50 : TLBEntry; - TLBEntry49 : TLBEntry; - TLBEntry48 : TLBEntry; - TLBEntry47 : TLBEntry; - TLBEntry46 : TLBEntry; - TLBEntry45 : TLBEntry; - TLBEntry44 : TLBEntry; - TLBEntry43 : TLBEntry; - TLBEntry42 : TLBEntry; - TLBEntry41 : TLBEntry; - TLBEntry40 : TLBEntry; - TLBEntry39 : TLBEntry; - TLBEntry38 : TLBEntry; - TLBEntry37 : TLBEntry; - TLBEntry36 : TLBEntry; - TLBEntry35 : TLBEntry; - TLBEntry34 : TLBEntry; - TLBEntry33 : TLBEntry; - TLBEntry32 : TLBEntry; - TLBEntry31 : TLBEntry; - TLBEntry30 : TLBEntry; - TLBEntry29 : TLBEntry; - TLBEntry28 : TLBEntry; - TLBEntry27 : TLBEntry; - TLBEntry26 : TLBEntry; - TLBEntry25 : TLBEntry; - TLBEntry24 : TLBEntry; - TLBEntry23 : TLBEntry; - TLBEntry22 : TLBEntry; - TLBEntry21 : TLBEntry; - TLBEntry20 : TLBEntry; - TLBEntry19 : TLBEntry; - TLBEntry18 : TLBEntry; - TLBEntry17 : TLBEntry; - TLBEntry16 : TLBEntry; - TLBEntry15 : TLBEntry; - TLBEntry14 : TLBEntry; - TLBEntry13 : TLBEntry; - TLBEntry12 : TLBEntry; - TLBEntry11 : TLBEntry; - TLBEntry10 : TLBEntry; - TLBEntry09 : TLBEntry; - TLBEntry08 : TLBEntry; - TLBEntry07 : TLBEntry; - TLBEntry06 : TLBEntry; - TLBEntry05 : TLBEntry; - TLBEntry04 : TLBEntry; - TLBEntry03 : TLBEntry; - TLBEntry02 : TLBEntry; - TLBEntry01 : TLBEntry; - TLBEntry00 : TLBEntry; - TLBXContext : XContextReg; - TLBEntryHi : TLBEntryHiReg; - TLBWired : mword 6; - TLBPageMask : mword 16; - TLBContext : ContextReg; - TLBEntryLo1 : TLBEntryLoReg; - TLBEntryLo0 : TLBEntryLoReg; - TLBRandom : mword 6; - TLBIndex : mword 6; - TLBProbe : mword 1; - nextPC : mword 64; - PC : mword 64; }. -Notation "{[ r 'with' 'UART_RVALID' := e ]}" := ({| UART_RVALID := e; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'UART_RDATA' := e ]}" := ({| UART_RDATA := e; UART_RVALID := UART_RVALID r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'UART_WRITTEN' := e ]}" := ({| UART_WRITTEN := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'UART_WDATA' := e ]}" := ({| UART_WDATA := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'GPR' := e ]}" := ({| GPR := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'LO' := e ]}" := ({| LO := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'HI' := e ]}" := ({| HI := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'delayedPC' := e ]}" := ({| delayedPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'inBranchDelay' := e ]}" := ({| inBranchDelay := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'branchPending' := e ]}" := ({| branchPending := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0Status' := e ]}" := ({| CP0Status := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0ConfigK0' := e ]}" := ({| CP0ConfigK0 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0UserLocal' := e ]}" := ({| CP0UserLocal := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0HWREna' := e ]}" := ({| CP0HWREna := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0Count' := e ]}" := ({| CP0Count := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0BadVAddr' := e ]}" := ({| CP0BadVAddr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0LLAddr' := e ]}" := ({| CP0LLAddr := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0LLBit' := e ]}" := ({| CP0LLBit := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0ErrorEPC' := e ]}" := ({| CP0ErrorEPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0EPC' := e ]}" := ({| CP0EPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0Cause' := e ]}" := ({| CP0Cause := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'CP0Compare' := e ]}" := ({| CP0Compare := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry63' := e ]}" := ({| TLBEntry63 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry62' := e ]}" := ({| TLBEntry62 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry61' := e ]}" := ({| TLBEntry61 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry60' := e ]}" := ({| TLBEntry60 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry59' := e ]}" := ({| TLBEntry59 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry58' := e ]}" := ({| TLBEntry58 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry57' := e ]}" := ({| TLBEntry57 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry56' := e ]}" := ({| TLBEntry56 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry55' := e ]}" := ({| TLBEntry55 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry54' := e ]}" := ({| TLBEntry54 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry53' := e ]}" := ({| TLBEntry53 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry52' := e ]}" := ({| TLBEntry52 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry51' := e ]}" := ({| TLBEntry51 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry50' := e ]}" := ({| TLBEntry50 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry49' := e ]}" := ({| TLBEntry49 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry48' := e ]}" := ({| TLBEntry48 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry47' := e ]}" := ({| TLBEntry47 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry46' := e ]}" := ({| TLBEntry46 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry45' := e ]}" := ({| TLBEntry45 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry44' := e ]}" := ({| TLBEntry44 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry43' := e ]}" := ({| TLBEntry43 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry42' := e ]}" := ({| TLBEntry42 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry41' := e ]}" := ({| TLBEntry41 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry40' := e ]}" := ({| TLBEntry40 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry39' := e ]}" := ({| TLBEntry39 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry38' := e ]}" := ({| TLBEntry38 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry37' := e ]}" := ({| TLBEntry37 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry36' := e ]}" := ({| TLBEntry36 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry35' := e ]}" := ({| TLBEntry35 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry34' := e ]}" := ({| TLBEntry34 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry33' := e ]}" := ({| TLBEntry33 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry32' := e ]}" := ({| TLBEntry32 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry31' := e ]}" := ({| TLBEntry31 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry30' := e ]}" := ({| TLBEntry30 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry29' := e ]}" := ({| TLBEntry29 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry28' := e ]}" := ({| TLBEntry28 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry27' := e ]}" := ({| TLBEntry27 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry26' := e ]}" := ({| TLBEntry26 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry25' := e ]}" := ({| TLBEntry25 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry24' := e ]}" := ({| TLBEntry24 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry23' := e ]}" := ({| TLBEntry23 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry22' := e ]}" := ({| TLBEntry22 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry21' := e ]}" := ({| TLBEntry21 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry20' := e ]}" := ({| TLBEntry20 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry19' := e ]}" := ({| TLBEntry19 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry18' := e ]}" := ({| TLBEntry18 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry17' := e ]}" := ({| TLBEntry17 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry16' := e ]}" := ({| TLBEntry16 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry15' := e ]}" := ({| TLBEntry15 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry14' := e ]}" := ({| TLBEntry14 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry13' := e ]}" := ({| TLBEntry13 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry12' := e ]}" := ({| TLBEntry12 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry11' := e ]}" := ({| TLBEntry11 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry10' := e ]}" := ({| TLBEntry10 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry09' := e ]}" := ({| TLBEntry09 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry08' := e ]}" := ({| TLBEntry08 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry07' := e ]}" := ({| TLBEntry07 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry06' := e ]}" := ({| TLBEntry06 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry05' := e ]}" := ({| TLBEntry05 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry04' := e ]}" := ({| TLBEntry04 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry03' := e ]}" := ({| TLBEntry03 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry02' := e ]}" := ({| TLBEntry02 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry01' := e ]}" := ({| TLBEntry01 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntry00' := e ]}" := ({| TLBEntry00 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBXContext' := e ]}" := ({| TLBXContext := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntryHi' := e ]}" := ({| TLBEntryHi := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBWired' := e ]}" := ({| TLBWired := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBPageMask' := e ]}" := ({| TLBPageMask := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBContext' := e ]}" := ({| TLBContext := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntryLo1' := e ]}" := ({| TLBEntryLo1 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBEntryLo0' := e ]}" := ({| TLBEntryLo0 := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBRandom' := e ]}" := ({| TLBRandom := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBIndex' := e ]}" := ({| TLBIndex := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBProbe := TLBProbe r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'TLBProbe' := e ]}" := ({| TLBProbe := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; nextPC := nextPC r; PC := PC r |}). -Notation "{[ r 'with' 'nextPC' := e ]}" := ({| nextPC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; PC := PC r |}). -Notation "{[ r 'with' 'PC' := e ]}" := ({| PC := e; UART_RVALID := UART_RVALID r; UART_RDATA := UART_RDATA r; UART_WRITTEN := UART_WRITTEN r; UART_WDATA := UART_WDATA r; GPR := GPR r; LO := LO r; HI := HI r; delayedPC := delayedPC r; inBranchDelay := inBranchDelay r; branchPending := branchPending r; CP0Status := CP0Status r; CP0ConfigK0 := CP0ConfigK0 r; CP0UserLocal := CP0UserLocal r; CP0HWREna := CP0HWREna r; CP0Count := CP0Count r; CP0BadVAddr := CP0BadVAddr r; CP0LLAddr := CP0LLAddr r; CP0LLBit := CP0LLBit r; CP0ErrorEPC := CP0ErrorEPC r; CP0EPC := CP0EPC r; CP0Cause := CP0Cause r; CP0Compare := CP0Compare r; TLBEntry63 := TLBEntry63 r; TLBEntry62 := TLBEntry62 r; TLBEntry61 := TLBEntry61 r; TLBEntry60 := TLBEntry60 r; TLBEntry59 := TLBEntry59 r; TLBEntry58 := TLBEntry58 r; TLBEntry57 := TLBEntry57 r; TLBEntry56 := TLBEntry56 r; TLBEntry55 := TLBEntry55 r; TLBEntry54 := TLBEntry54 r; TLBEntry53 := TLBEntry53 r; TLBEntry52 := TLBEntry52 r; TLBEntry51 := TLBEntry51 r; TLBEntry50 := TLBEntry50 r; TLBEntry49 := TLBEntry49 r; TLBEntry48 := TLBEntry48 r; TLBEntry47 := TLBEntry47 r; TLBEntry46 := TLBEntry46 r; TLBEntry45 := TLBEntry45 r; TLBEntry44 := TLBEntry44 r; TLBEntry43 := TLBEntry43 r; TLBEntry42 := TLBEntry42 r; TLBEntry41 := TLBEntry41 r; TLBEntry40 := TLBEntry40 r; TLBEntry39 := TLBEntry39 r; TLBEntry38 := TLBEntry38 r; TLBEntry37 := TLBEntry37 r; TLBEntry36 := TLBEntry36 r; TLBEntry35 := TLBEntry35 r; TLBEntry34 := TLBEntry34 r; TLBEntry33 := TLBEntry33 r; TLBEntry32 := TLBEntry32 r; TLBEntry31 := TLBEntry31 r; TLBEntry30 := TLBEntry30 r; TLBEntry29 := TLBEntry29 r; TLBEntry28 := TLBEntry28 r; TLBEntry27 := TLBEntry27 r; TLBEntry26 := TLBEntry26 r; TLBEntry25 := TLBEntry25 r; TLBEntry24 := TLBEntry24 r; TLBEntry23 := TLBEntry23 r; TLBEntry22 := TLBEntry22 r; TLBEntry21 := TLBEntry21 r; TLBEntry20 := TLBEntry20 r; TLBEntry19 := TLBEntry19 r; TLBEntry18 := TLBEntry18 r; TLBEntry17 := TLBEntry17 r; TLBEntry16 := TLBEntry16 r; TLBEntry15 := TLBEntry15 r; TLBEntry14 := TLBEntry14 r; TLBEntry13 := TLBEntry13 r; TLBEntry12 := TLBEntry12 r; TLBEntry11 := TLBEntry11 r; TLBEntry10 := TLBEntry10 r; TLBEntry09 := TLBEntry09 r; TLBEntry08 := TLBEntry08 r; TLBEntry07 := TLBEntry07 r; TLBEntry06 := TLBEntry06 r; TLBEntry05 := TLBEntry05 r; TLBEntry04 := TLBEntry04 r; TLBEntry03 := TLBEntry03 r; TLBEntry02 := TLBEntry02 r; TLBEntry01 := TLBEntry01 r; TLBEntry00 := TLBEntry00 r; TLBXContext := TLBXContext r; TLBEntryHi := TLBEntryHi r; TLBWired := TLBWired r; TLBPageMask := TLBPageMask r; TLBContext := TLBContext r; TLBEntryLo1 := TLBEntryLo1 r; TLBEntryLo0 := TLBEntryLo0 r; TLBRandom := TLBRandom r; TLBIndex := TLBIndex r; TLBProbe := TLBProbe r; nextPC := nextPC r |}). - - - -Definition CauseReg_of_regval (merge_var : register_value) -: option CauseReg := - match merge_var with | Regval_CauseReg (v) => Some v | g__13 => None end. - -Definition regval_of_CauseReg (v : CauseReg) : register_value := Regval_CauseReg v. - -Definition ContextReg_of_regval (merge_var : register_value) -: option ContextReg := - match merge_var with | Regval_ContextReg (v) => Some v | g__12 => None end. - -Definition regval_of_ContextReg (v : ContextReg) : register_value := Regval_ContextReg v. - -Definition StatusReg_of_regval (merge_var : register_value) -: option StatusReg := - match merge_var with | Regval_StatusReg (v) => Some v | g__11 => None end. - -Definition regval_of_StatusReg (v : StatusReg) : register_value := Regval_StatusReg v. - -Definition TLBEntry_of_regval (merge_var : register_value) -: option TLBEntry := - match merge_var with | Regval_TLBEntry (v) => Some v | g__10 => None end. - -Definition regval_of_TLBEntry (v : TLBEntry) : register_value := Regval_TLBEntry v. - -Definition TLBEntryHiReg_of_regval (merge_var : register_value) -: option TLBEntryHiReg := - match merge_var with | Regval_TLBEntryHiReg (v) => Some v | g__9 => None end. - -Definition regval_of_TLBEntryHiReg (v : TLBEntryHiReg) : register_value := Regval_TLBEntryHiReg v. - -Definition TLBEntryLoReg_of_regval (merge_var : register_value) -: option TLBEntryLoReg := - match merge_var with | Regval_TLBEntryLoReg (v) => Some v | g__8 => None end. - -Definition regval_of_TLBEntryLoReg (v : TLBEntryLoReg) : register_value := Regval_TLBEntryLoReg v. - -Definition XContextReg_of_regval (merge_var : register_value) -: option XContextReg := - match merge_var with | Regval_XContextReg (v) => Some v | g__7 => None end. - -Definition regval_of_XContextReg (v : XContextReg) : register_value := Regval_XContextReg v. - -Definition vector_16_dec_bit_of_regval (merge_var : register_value) -: option (mword 16) := - match merge_var with | Regval_vector_16_dec_bit (v) => Some v | g__6 => None end. - -Definition regval_of_vector_16_dec_bit (v : mword 16) -: register_value := - Regval_vector_16_dec_bit v. - -Definition vector_1_dec_bit_of_regval (merge_var : register_value) -: option (mword 1) := - match merge_var with | Regval_vector_1_dec_bit (v) => Some v | g__5 => None end. - -Definition regval_of_vector_1_dec_bit (v : mword 1) : register_value := Regval_vector_1_dec_bit v. - -Definition vector_32_dec_bit_of_regval (merge_var : register_value) -: option (mword 32) := - match merge_var with | Regval_vector_32_dec_bit (v) => Some v | g__4 => None end. - -Definition regval_of_vector_32_dec_bit (v : mword 32) -: register_value := - Regval_vector_32_dec_bit v. - -Definition vector_3_dec_bit_of_regval (merge_var : register_value) -: option (mword 3) := - match merge_var with | Regval_vector_3_dec_bit (v) => Some v | g__3 => None end. - -Definition regval_of_vector_3_dec_bit (v : mword 3) : register_value := Regval_vector_3_dec_bit v. - -Definition vector_64_dec_bit_of_regval (merge_var : register_value) -: option (mword 64) := - match merge_var with | Regval_vector_64_dec_bit (v) => Some v | g__2 => None end. - -Definition regval_of_vector_64_dec_bit (v : mword 64) -: register_value := - Regval_vector_64_dec_bit v. - -Definition vector_6_dec_bit_of_regval (merge_var : register_value) -: option (mword 6) := - match merge_var with | Regval_vector_6_dec_bit (v) => Some v | g__1 => None end. - -Definition regval_of_vector_6_dec_bit (v : mword 6) : register_value := Regval_vector_6_dec_bit v. - -Definition vector_8_dec_bit_of_regval (merge_var : register_value) -: option (mword 8) := - match merge_var with | Regval_vector_8_dec_bit (v) => Some v | g__0 => None end. - -Definition regval_of_vector_8_dec_bit (v : mword 8) : register_value := Regval_vector_8_dec_bit v. - - - -Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with - | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None - | _ => None -end. - -Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)). - -Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with - | Regval_list v => just_list (List.map of_regval v) - | _ => None -end. - -Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs). - -Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with - | Regval_option v => option_map of_regval v - | _ => None -end. - -Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v). - - -Definition UART_RVALID_ref := {| - name := "UART_RVALID"; - read_from := (fun s => s.(UART_RVALID)); - write_to := (fun v s => ({[ s with UART_RVALID := v ]})); - of_regval := (fun v => vector_1_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. - -Definition UART_RDATA_ref := {| - name := "UART_RDATA"; - read_from := (fun s => s.(UART_RDATA)); - write_to := (fun v s => ({[ s with UART_RDATA := v ]})); - of_regval := (fun v => vector_8_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_8_dec_bit v) |}. - -Definition UART_WRITTEN_ref := {| - name := "UART_WRITTEN"; - read_from := (fun s => s.(UART_WRITTEN)); - write_to := (fun v s => ({[ s with UART_WRITTEN := v ]})); - of_regval := (fun v => vector_1_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. - -Definition UART_WDATA_ref := {| - name := "UART_WDATA"; - read_from := (fun s => s.(UART_WDATA)); - write_to := (fun v s => ({[ s with UART_WDATA := v ]})); - of_regval := (fun v => vector_8_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_8_dec_bit v) |}. - -Definition GPR_ref := {| - name := "GPR"; - read_from := (fun s => s.(GPR)); - write_to := (fun v s => ({[ s with GPR := v ]})); - of_regval := (fun v => vector_of_regval 32 (fun v => vector_64_dec_bit_of_regval v) v); - regval_of := (fun v => regval_of_vector (fun v => regval_of_vector_64_dec_bit v) 32 false v) |}. - -Definition LO_ref := {| - name := "LO"; - read_from := (fun s => s.(LO)); - write_to := (fun v s => ({[ s with LO := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition HI_ref := {| - name := "HI"; - read_from := (fun s => s.(HI)); - write_to := (fun v s => ({[ s with HI := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition delayedPC_ref := {| - name := "delayedPC"; - read_from := (fun s => s.(delayedPC)); - write_to := (fun v s => ({[ s with delayedPC := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition inBranchDelay_ref := {| - name := "inBranchDelay"; - read_from := (fun s => s.(inBranchDelay)); - write_to := (fun v s => ({[ s with inBranchDelay := v ]})); - of_regval := (fun v => vector_1_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. - -Definition branchPending_ref := {| - name := "branchPending"; - read_from := (fun s => s.(branchPending)); - write_to := (fun v s => ({[ s with branchPending := v ]})); - of_regval := (fun v => vector_1_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. - -Definition CP0Status_ref := {| - name := "CP0Status"; - read_from := (fun s => s.(CP0Status)); - write_to := (fun v s => ({[ s with CP0Status := v ]})); - of_regval := (fun v => StatusReg_of_regval v); - regval_of := (fun v => regval_of_StatusReg v) |}. - -Definition CP0ConfigK0_ref := {| - name := "CP0ConfigK0"; - read_from := (fun s => s.(CP0ConfigK0)); - write_to := (fun v s => ({[ s with CP0ConfigK0 := v ]})); - of_regval := (fun v => vector_3_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_3_dec_bit v) |}. - -Definition CP0UserLocal_ref := {| - name := "CP0UserLocal"; - read_from := (fun s => s.(CP0UserLocal)); - write_to := (fun v s => ({[ s with CP0UserLocal := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition CP0HWREna_ref := {| - name := "CP0HWREna"; - read_from := (fun s => s.(CP0HWREna)); - write_to := (fun v s => ({[ s with CP0HWREna := v ]})); - of_regval := (fun v => vector_32_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. - -Definition CP0Count_ref := {| - name := "CP0Count"; - read_from := (fun s => s.(CP0Count)); - write_to := (fun v s => ({[ s with CP0Count := v ]})); - of_regval := (fun v => vector_32_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. - -Definition CP0BadVAddr_ref := {| - name := "CP0BadVAddr"; - read_from := (fun s => s.(CP0BadVAddr)); - write_to := (fun v s => ({[ s with CP0BadVAddr := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition CP0LLAddr_ref := {| - name := "CP0LLAddr"; - read_from := (fun s => s.(CP0LLAddr)); - write_to := (fun v s => ({[ s with CP0LLAddr := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition CP0LLBit_ref := {| - name := "CP0LLBit"; - read_from := (fun s => s.(CP0LLBit)); - write_to := (fun v s => ({[ s with CP0LLBit := v ]})); - of_regval := (fun v => vector_1_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. - -Definition CP0ErrorEPC_ref := {| - name := "CP0ErrorEPC"; - read_from := (fun s => s.(CP0ErrorEPC)); - write_to := (fun v s => ({[ s with CP0ErrorEPC := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition CP0EPC_ref := {| - name := "CP0EPC"; - read_from := (fun s => s.(CP0EPC)); - write_to := (fun v s => ({[ s with CP0EPC := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition CP0Cause_ref := {| - name := "CP0Cause"; - read_from := (fun s => s.(CP0Cause)); - write_to := (fun v s => ({[ s with CP0Cause := v ]})); - of_regval := (fun v => CauseReg_of_regval v); - regval_of := (fun v => regval_of_CauseReg v) |}. - -Definition CP0Compare_ref := {| - name := "CP0Compare"; - read_from := (fun s => s.(CP0Compare)); - write_to := (fun v s => ({[ s with CP0Compare := v ]})); - of_regval := (fun v => vector_32_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_32_dec_bit v) |}. - -Definition TLBEntry63_ref := {| - name := "TLBEntry63"; - read_from := (fun s => s.(TLBEntry63)); - write_to := (fun v s => ({[ s with TLBEntry63 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry62_ref := {| - name := "TLBEntry62"; - read_from := (fun s => s.(TLBEntry62)); - write_to := (fun v s => ({[ s with TLBEntry62 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry61_ref := {| - name := "TLBEntry61"; - read_from := (fun s => s.(TLBEntry61)); - write_to := (fun v s => ({[ s with TLBEntry61 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry60_ref := {| - name := "TLBEntry60"; - read_from := (fun s => s.(TLBEntry60)); - write_to := (fun v s => ({[ s with TLBEntry60 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry59_ref := {| - name := "TLBEntry59"; - read_from := (fun s => s.(TLBEntry59)); - write_to := (fun v s => ({[ s with TLBEntry59 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry58_ref := {| - name := "TLBEntry58"; - read_from := (fun s => s.(TLBEntry58)); - write_to := (fun v s => ({[ s with TLBEntry58 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry57_ref := {| - name := "TLBEntry57"; - read_from := (fun s => s.(TLBEntry57)); - write_to := (fun v s => ({[ s with TLBEntry57 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry56_ref := {| - name := "TLBEntry56"; - read_from := (fun s => s.(TLBEntry56)); - write_to := (fun v s => ({[ s with TLBEntry56 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry55_ref := {| - name := "TLBEntry55"; - read_from := (fun s => s.(TLBEntry55)); - write_to := (fun v s => ({[ s with TLBEntry55 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry54_ref := {| - name := "TLBEntry54"; - read_from := (fun s => s.(TLBEntry54)); - write_to := (fun v s => ({[ s with TLBEntry54 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry53_ref := {| - name := "TLBEntry53"; - read_from := (fun s => s.(TLBEntry53)); - write_to := (fun v s => ({[ s with TLBEntry53 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry52_ref := {| - name := "TLBEntry52"; - read_from := (fun s => s.(TLBEntry52)); - write_to := (fun v s => ({[ s with TLBEntry52 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry51_ref := {| - name := "TLBEntry51"; - read_from := (fun s => s.(TLBEntry51)); - write_to := (fun v s => ({[ s with TLBEntry51 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry50_ref := {| - name := "TLBEntry50"; - read_from := (fun s => s.(TLBEntry50)); - write_to := (fun v s => ({[ s with TLBEntry50 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry49_ref := {| - name := "TLBEntry49"; - read_from := (fun s => s.(TLBEntry49)); - write_to := (fun v s => ({[ s with TLBEntry49 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry48_ref := {| - name := "TLBEntry48"; - read_from := (fun s => s.(TLBEntry48)); - write_to := (fun v s => ({[ s with TLBEntry48 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry47_ref := {| - name := "TLBEntry47"; - read_from := (fun s => s.(TLBEntry47)); - write_to := (fun v s => ({[ s with TLBEntry47 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry46_ref := {| - name := "TLBEntry46"; - read_from := (fun s => s.(TLBEntry46)); - write_to := (fun v s => ({[ s with TLBEntry46 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry45_ref := {| - name := "TLBEntry45"; - read_from := (fun s => s.(TLBEntry45)); - write_to := (fun v s => ({[ s with TLBEntry45 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry44_ref := {| - name := "TLBEntry44"; - read_from := (fun s => s.(TLBEntry44)); - write_to := (fun v s => ({[ s with TLBEntry44 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry43_ref := {| - name := "TLBEntry43"; - read_from := (fun s => s.(TLBEntry43)); - write_to := (fun v s => ({[ s with TLBEntry43 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry42_ref := {| - name := "TLBEntry42"; - read_from := (fun s => s.(TLBEntry42)); - write_to := (fun v s => ({[ s with TLBEntry42 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry41_ref := {| - name := "TLBEntry41"; - read_from := (fun s => s.(TLBEntry41)); - write_to := (fun v s => ({[ s with TLBEntry41 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry40_ref := {| - name := "TLBEntry40"; - read_from := (fun s => s.(TLBEntry40)); - write_to := (fun v s => ({[ s with TLBEntry40 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry39_ref := {| - name := "TLBEntry39"; - read_from := (fun s => s.(TLBEntry39)); - write_to := (fun v s => ({[ s with TLBEntry39 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry38_ref := {| - name := "TLBEntry38"; - read_from := (fun s => s.(TLBEntry38)); - write_to := (fun v s => ({[ s with TLBEntry38 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry37_ref := {| - name := "TLBEntry37"; - read_from := (fun s => s.(TLBEntry37)); - write_to := (fun v s => ({[ s with TLBEntry37 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry36_ref := {| - name := "TLBEntry36"; - read_from := (fun s => s.(TLBEntry36)); - write_to := (fun v s => ({[ s with TLBEntry36 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry35_ref := {| - name := "TLBEntry35"; - read_from := (fun s => s.(TLBEntry35)); - write_to := (fun v s => ({[ s with TLBEntry35 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry34_ref := {| - name := "TLBEntry34"; - read_from := (fun s => s.(TLBEntry34)); - write_to := (fun v s => ({[ s with TLBEntry34 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry33_ref := {| - name := "TLBEntry33"; - read_from := (fun s => s.(TLBEntry33)); - write_to := (fun v s => ({[ s with TLBEntry33 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry32_ref := {| - name := "TLBEntry32"; - read_from := (fun s => s.(TLBEntry32)); - write_to := (fun v s => ({[ s with TLBEntry32 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry31_ref := {| - name := "TLBEntry31"; - read_from := (fun s => s.(TLBEntry31)); - write_to := (fun v s => ({[ s with TLBEntry31 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry30_ref := {| - name := "TLBEntry30"; - read_from := (fun s => s.(TLBEntry30)); - write_to := (fun v s => ({[ s with TLBEntry30 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry29_ref := {| - name := "TLBEntry29"; - read_from := (fun s => s.(TLBEntry29)); - write_to := (fun v s => ({[ s with TLBEntry29 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry28_ref := {| - name := "TLBEntry28"; - read_from := (fun s => s.(TLBEntry28)); - write_to := (fun v s => ({[ s with TLBEntry28 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry27_ref := {| - name := "TLBEntry27"; - read_from := (fun s => s.(TLBEntry27)); - write_to := (fun v s => ({[ s with TLBEntry27 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry26_ref := {| - name := "TLBEntry26"; - read_from := (fun s => s.(TLBEntry26)); - write_to := (fun v s => ({[ s with TLBEntry26 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry25_ref := {| - name := "TLBEntry25"; - read_from := (fun s => s.(TLBEntry25)); - write_to := (fun v s => ({[ s with TLBEntry25 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry24_ref := {| - name := "TLBEntry24"; - read_from := (fun s => s.(TLBEntry24)); - write_to := (fun v s => ({[ s with TLBEntry24 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry23_ref := {| - name := "TLBEntry23"; - read_from := (fun s => s.(TLBEntry23)); - write_to := (fun v s => ({[ s with TLBEntry23 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry22_ref := {| - name := "TLBEntry22"; - read_from := (fun s => s.(TLBEntry22)); - write_to := (fun v s => ({[ s with TLBEntry22 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry21_ref := {| - name := "TLBEntry21"; - read_from := (fun s => s.(TLBEntry21)); - write_to := (fun v s => ({[ s with TLBEntry21 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry20_ref := {| - name := "TLBEntry20"; - read_from := (fun s => s.(TLBEntry20)); - write_to := (fun v s => ({[ s with TLBEntry20 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry19_ref := {| - name := "TLBEntry19"; - read_from := (fun s => s.(TLBEntry19)); - write_to := (fun v s => ({[ s with TLBEntry19 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry18_ref := {| - name := "TLBEntry18"; - read_from := (fun s => s.(TLBEntry18)); - write_to := (fun v s => ({[ s with TLBEntry18 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry17_ref := {| - name := "TLBEntry17"; - read_from := (fun s => s.(TLBEntry17)); - write_to := (fun v s => ({[ s with TLBEntry17 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry16_ref := {| - name := "TLBEntry16"; - read_from := (fun s => s.(TLBEntry16)); - write_to := (fun v s => ({[ s with TLBEntry16 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry15_ref := {| - name := "TLBEntry15"; - read_from := (fun s => s.(TLBEntry15)); - write_to := (fun v s => ({[ s with TLBEntry15 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry14_ref := {| - name := "TLBEntry14"; - read_from := (fun s => s.(TLBEntry14)); - write_to := (fun v s => ({[ s with TLBEntry14 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry13_ref := {| - name := "TLBEntry13"; - read_from := (fun s => s.(TLBEntry13)); - write_to := (fun v s => ({[ s with TLBEntry13 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry12_ref := {| - name := "TLBEntry12"; - read_from := (fun s => s.(TLBEntry12)); - write_to := (fun v s => ({[ s with TLBEntry12 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry11_ref := {| - name := "TLBEntry11"; - read_from := (fun s => s.(TLBEntry11)); - write_to := (fun v s => ({[ s with TLBEntry11 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry10_ref := {| - name := "TLBEntry10"; - read_from := (fun s => s.(TLBEntry10)); - write_to := (fun v s => ({[ s with TLBEntry10 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry09_ref := {| - name := "TLBEntry09"; - read_from := (fun s => s.(TLBEntry09)); - write_to := (fun v s => ({[ s with TLBEntry09 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry08_ref := {| - name := "TLBEntry08"; - read_from := (fun s => s.(TLBEntry08)); - write_to := (fun v s => ({[ s with TLBEntry08 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry07_ref := {| - name := "TLBEntry07"; - read_from := (fun s => s.(TLBEntry07)); - write_to := (fun v s => ({[ s with TLBEntry07 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry06_ref := {| - name := "TLBEntry06"; - read_from := (fun s => s.(TLBEntry06)); - write_to := (fun v s => ({[ s with TLBEntry06 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry05_ref := {| - name := "TLBEntry05"; - read_from := (fun s => s.(TLBEntry05)); - write_to := (fun v s => ({[ s with TLBEntry05 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry04_ref := {| - name := "TLBEntry04"; - read_from := (fun s => s.(TLBEntry04)); - write_to := (fun v s => ({[ s with TLBEntry04 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry03_ref := {| - name := "TLBEntry03"; - read_from := (fun s => s.(TLBEntry03)); - write_to := (fun v s => ({[ s with TLBEntry03 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry02_ref := {| - name := "TLBEntry02"; - read_from := (fun s => s.(TLBEntry02)); - write_to := (fun v s => ({[ s with TLBEntry02 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry01_ref := {| - name := "TLBEntry01"; - read_from := (fun s => s.(TLBEntry01)); - write_to := (fun v s => ({[ s with TLBEntry01 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBEntry00_ref := {| - name := "TLBEntry00"; - read_from := (fun s => s.(TLBEntry00)); - write_to := (fun v s => ({[ s with TLBEntry00 := v ]})); - of_regval := (fun v => TLBEntry_of_regval v); - regval_of := (fun v => regval_of_TLBEntry v) |}. - -Definition TLBXContext_ref := {| - name := "TLBXContext"; - read_from := (fun s => s.(TLBXContext)); - write_to := (fun v s => ({[ s with TLBXContext := v ]})); - of_regval := (fun v => XContextReg_of_regval v); - regval_of := (fun v => regval_of_XContextReg v) |}. - -Definition TLBEntryHi_ref := {| - name := "TLBEntryHi"; - read_from := (fun s => s.(TLBEntryHi)); - write_to := (fun v s => ({[ s with TLBEntryHi := v ]})); - of_regval := (fun v => TLBEntryHiReg_of_regval v); - regval_of := (fun v => regval_of_TLBEntryHiReg v) |}. - -Definition TLBWired_ref := {| - name := "TLBWired"; - read_from := (fun s => s.(TLBWired)); - write_to := (fun v s => ({[ s with TLBWired := v ]})); - of_regval := (fun v => vector_6_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. - -Definition TLBPageMask_ref := {| - name := "TLBPageMask"; - read_from := (fun s => s.(TLBPageMask)); - write_to := (fun v s => ({[ s with TLBPageMask := v ]})); - of_regval := (fun v => vector_16_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_16_dec_bit v) |}. - -Definition TLBContext_ref := {| - name := "TLBContext"; - read_from := (fun s => s.(TLBContext)); - write_to := (fun v s => ({[ s with TLBContext := v ]})); - of_regval := (fun v => ContextReg_of_regval v); - regval_of := (fun v => regval_of_ContextReg v) |}. - -Definition TLBEntryLo1_ref := {| - name := "TLBEntryLo1"; - read_from := (fun s => s.(TLBEntryLo1)); - write_to := (fun v s => ({[ s with TLBEntryLo1 := v ]})); - of_regval := (fun v => TLBEntryLoReg_of_regval v); - regval_of := (fun v => regval_of_TLBEntryLoReg v) |}. - -Definition TLBEntryLo0_ref := {| - name := "TLBEntryLo0"; - read_from := (fun s => s.(TLBEntryLo0)); - write_to := (fun v s => ({[ s with TLBEntryLo0 := v ]})); - of_regval := (fun v => TLBEntryLoReg_of_regval v); - regval_of := (fun v => regval_of_TLBEntryLoReg v) |}. - -Definition TLBRandom_ref := {| - name := "TLBRandom"; - read_from := (fun s => s.(TLBRandom)); - write_to := (fun v s => ({[ s with TLBRandom := v ]})); - of_regval := (fun v => vector_6_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. - -Definition TLBIndex_ref := {| - name := "TLBIndex"; - read_from := (fun s => s.(TLBIndex)); - write_to := (fun v s => ({[ s with TLBIndex := v ]})); - of_regval := (fun v => vector_6_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_6_dec_bit v) |}. - -Definition TLBProbe_ref := {| - name := "TLBProbe"; - read_from := (fun s => s.(TLBProbe)); - write_to := (fun v s => ({[ s with TLBProbe := v ]})); - of_regval := (fun v => vector_1_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_1_dec_bit v) |}. - -Definition nextPC_ref := {| - name := "nextPC"; - read_from := (fun s => s.(nextPC)); - write_to := (fun v s => ({[ s with nextPC := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Definition PC_ref := {| - name := "PC"; - read_from := (fun s => s.(PC)); - write_to := (fun v s => ({[ s with PC := v ]})); - of_regval := (fun v => vector_64_dec_bit_of_regval v); - regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. - -Local Open Scope string. -Definition get_regval (reg_name : string) (s : regstate) : option register_value := - if string_dec reg_name "UART_RVALID" then Some (UART_RVALID_ref.(regval_of) (UART_RVALID_ref.(read_from) s)) else - if string_dec reg_name "UART_RDATA" then Some (UART_RDATA_ref.(regval_of) (UART_RDATA_ref.(read_from) s)) else - if string_dec reg_name "UART_WRITTEN" then Some (UART_WRITTEN_ref.(regval_of) (UART_WRITTEN_ref.(read_from) s)) else - if string_dec reg_name "UART_WDATA" then Some (UART_WDATA_ref.(regval_of) (UART_WDATA_ref.(read_from) s)) else - if string_dec reg_name "GPR" then Some (GPR_ref.(regval_of) (GPR_ref.(read_from) s)) else - if string_dec reg_name "LO" then Some (LO_ref.(regval_of) (LO_ref.(read_from) s)) else - if string_dec reg_name "HI" then Some (HI_ref.(regval_of) (HI_ref.(read_from) s)) else - if string_dec reg_name "delayedPC" then Some (delayedPC_ref.(regval_of) (delayedPC_ref.(read_from) s)) else - if string_dec reg_name "inBranchDelay" then Some (inBranchDelay_ref.(regval_of) (inBranchDelay_ref.(read_from) s)) else - if string_dec reg_name "branchPending" then Some (branchPending_ref.(regval_of) (branchPending_ref.(read_from) s)) else - if string_dec reg_name "CP0Status" then Some (CP0Status_ref.(regval_of) (CP0Status_ref.(read_from) s)) else - if string_dec reg_name "CP0ConfigK0" then Some (CP0ConfigK0_ref.(regval_of) (CP0ConfigK0_ref.(read_from) s)) else - if string_dec reg_name "CP0UserLocal" then Some (CP0UserLocal_ref.(regval_of) (CP0UserLocal_ref.(read_from) s)) else - if string_dec reg_name "CP0HWREna" then Some (CP0HWREna_ref.(regval_of) (CP0HWREna_ref.(read_from) s)) else - if string_dec reg_name "CP0Count" then Some (CP0Count_ref.(regval_of) (CP0Count_ref.(read_from) s)) else - if string_dec reg_name "CP0BadVAddr" then Some (CP0BadVAddr_ref.(regval_of) (CP0BadVAddr_ref.(read_from) s)) else - if string_dec reg_name "CP0LLAddr" then Some (CP0LLAddr_ref.(regval_of) (CP0LLAddr_ref.(read_from) s)) else - if string_dec reg_name "CP0LLBit" then Some (CP0LLBit_ref.(regval_of) (CP0LLBit_ref.(read_from) s)) else - if string_dec reg_name "CP0ErrorEPC" then Some (CP0ErrorEPC_ref.(regval_of) (CP0ErrorEPC_ref.(read_from) s)) else - if string_dec reg_name "CP0EPC" then Some (CP0EPC_ref.(regval_of) (CP0EPC_ref.(read_from) s)) else - if string_dec reg_name "CP0Cause" then Some (CP0Cause_ref.(regval_of) (CP0Cause_ref.(read_from) s)) else - if string_dec reg_name "CP0Compare" then Some (CP0Compare_ref.(regval_of) (CP0Compare_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry63" then Some (TLBEntry63_ref.(regval_of) (TLBEntry63_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry62" then Some (TLBEntry62_ref.(regval_of) (TLBEntry62_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry61" then Some (TLBEntry61_ref.(regval_of) (TLBEntry61_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry60" then Some (TLBEntry60_ref.(regval_of) (TLBEntry60_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry59" then Some (TLBEntry59_ref.(regval_of) (TLBEntry59_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry58" then Some (TLBEntry58_ref.(regval_of) (TLBEntry58_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry57" then Some (TLBEntry57_ref.(regval_of) (TLBEntry57_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry56" then Some (TLBEntry56_ref.(regval_of) (TLBEntry56_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry55" then Some (TLBEntry55_ref.(regval_of) (TLBEntry55_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry54" then Some (TLBEntry54_ref.(regval_of) (TLBEntry54_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry53" then Some (TLBEntry53_ref.(regval_of) (TLBEntry53_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry52" then Some (TLBEntry52_ref.(regval_of) (TLBEntry52_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry51" then Some (TLBEntry51_ref.(regval_of) (TLBEntry51_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry50" then Some (TLBEntry50_ref.(regval_of) (TLBEntry50_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry49" then Some (TLBEntry49_ref.(regval_of) (TLBEntry49_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry48" then Some (TLBEntry48_ref.(regval_of) (TLBEntry48_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry47" then Some (TLBEntry47_ref.(regval_of) (TLBEntry47_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry46" then Some (TLBEntry46_ref.(regval_of) (TLBEntry46_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry45" then Some (TLBEntry45_ref.(regval_of) (TLBEntry45_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry44" then Some (TLBEntry44_ref.(regval_of) (TLBEntry44_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry43" then Some (TLBEntry43_ref.(regval_of) (TLBEntry43_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry42" then Some (TLBEntry42_ref.(regval_of) (TLBEntry42_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry41" then Some (TLBEntry41_ref.(regval_of) (TLBEntry41_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry40" then Some (TLBEntry40_ref.(regval_of) (TLBEntry40_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry39" then Some (TLBEntry39_ref.(regval_of) (TLBEntry39_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry38" then Some (TLBEntry38_ref.(regval_of) (TLBEntry38_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry37" then Some (TLBEntry37_ref.(regval_of) (TLBEntry37_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry36" then Some (TLBEntry36_ref.(regval_of) (TLBEntry36_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry35" then Some (TLBEntry35_ref.(regval_of) (TLBEntry35_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry34" then Some (TLBEntry34_ref.(regval_of) (TLBEntry34_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry33" then Some (TLBEntry33_ref.(regval_of) (TLBEntry33_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry32" then Some (TLBEntry32_ref.(regval_of) (TLBEntry32_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry31" then Some (TLBEntry31_ref.(regval_of) (TLBEntry31_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry30" then Some (TLBEntry30_ref.(regval_of) (TLBEntry30_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry29" then Some (TLBEntry29_ref.(regval_of) (TLBEntry29_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry28" then Some (TLBEntry28_ref.(regval_of) (TLBEntry28_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry27" then Some (TLBEntry27_ref.(regval_of) (TLBEntry27_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry26" then Some (TLBEntry26_ref.(regval_of) (TLBEntry26_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry25" then Some (TLBEntry25_ref.(regval_of) (TLBEntry25_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry24" then Some (TLBEntry24_ref.(regval_of) (TLBEntry24_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry23" then Some (TLBEntry23_ref.(regval_of) (TLBEntry23_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry22" then Some (TLBEntry22_ref.(regval_of) (TLBEntry22_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry21" then Some (TLBEntry21_ref.(regval_of) (TLBEntry21_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry20" then Some (TLBEntry20_ref.(regval_of) (TLBEntry20_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry19" then Some (TLBEntry19_ref.(regval_of) (TLBEntry19_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry18" then Some (TLBEntry18_ref.(regval_of) (TLBEntry18_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry17" then Some (TLBEntry17_ref.(regval_of) (TLBEntry17_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry16" then Some (TLBEntry16_ref.(regval_of) (TLBEntry16_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry15" then Some (TLBEntry15_ref.(regval_of) (TLBEntry15_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry14" then Some (TLBEntry14_ref.(regval_of) (TLBEntry14_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry13" then Some (TLBEntry13_ref.(regval_of) (TLBEntry13_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry12" then Some (TLBEntry12_ref.(regval_of) (TLBEntry12_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry11" then Some (TLBEntry11_ref.(regval_of) (TLBEntry11_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry10" then Some (TLBEntry10_ref.(regval_of) (TLBEntry10_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry09" then Some (TLBEntry09_ref.(regval_of) (TLBEntry09_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry08" then Some (TLBEntry08_ref.(regval_of) (TLBEntry08_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry07" then Some (TLBEntry07_ref.(regval_of) (TLBEntry07_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry06" then Some (TLBEntry06_ref.(regval_of) (TLBEntry06_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry05" then Some (TLBEntry05_ref.(regval_of) (TLBEntry05_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry04" then Some (TLBEntry04_ref.(regval_of) (TLBEntry04_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry03" then Some (TLBEntry03_ref.(regval_of) (TLBEntry03_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry02" then Some (TLBEntry02_ref.(regval_of) (TLBEntry02_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry01" then Some (TLBEntry01_ref.(regval_of) (TLBEntry01_ref.(read_from) s)) else - if string_dec reg_name "TLBEntry00" then Some (TLBEntry00_ref.(regval_of) (TLBEntry00_ref.(read_from) s)) else - if string_dec reg_name "TLBXContext" then Some (TLBXContext_ref.(regval_of) (TLBXContext_ref.(read_from) s)) else - if string_dec reg_name "TLBEntryHi" then Some (TLBEntryHi_ref.(regval_of) (TLBEntryHi_ref.(read_from) s)) else - if string_dec reg_name "TLBWired" then Some (TLBWired_ref.(regval_of) (TLBWired_ref.(read_from) s)) else - if string_dec reg_name "TLBPageMask" then Some (TLBPageMask_ref.(regval_of) (TLBPageMask_ref.(read_from) s)) else - if string_dec reg_name "TLBContext" then Some (TLBContext_ref.(regval_of) (TLBContext_ref.(read_from) s)) else - if string_dec reg_name "TLBEntryLo1" then Some (TLBEntryLo1_ref.(regval_of) (TLBEntryLo1_ref.(read_from) s)) else - if string_dec reg_name "TLBEntryLo0" then Some (TLBEntryLo0_ref.(regval_of) (TLBEntryLo0_ref.(read_from) s)) else - if string_dec reg_name "TLBRandom" then Some (TLBRandom_ref.(regval_of) (TLBRandom_ref.(read_from) s)) else - if string_dec reg_name "TLBIndex" then Some (TLBIndex_ref.(regval_of) (TLBIndex_ref.(read_from) s)) else - if string_dec reg_name "TLBProbe" then Some (TLBProbe_ref.(regval_of) (TLBProbe_ref.(read_from) s)) else - if string_dec reg_name "nextPC" then Some (nextPC_ref.(regval_of) (nextPC_ref.(read_from) s)) else - if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else - None. - -Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate := - if string_dec reg_name "UART_RVALID" then option_map (fun v => UART_RVALID_ref.(write_to) v s) (UART_RVALID_ref.(of_regval) v) else - if string_dec reg_name "UART_RDATA" then option_map (fun v => UART_RDATA_ref.(write_to) v s) (UART_RDATA_ref.(of_regval) v) else - if string_dec reg_name "UART_WRITTEN" then option_map (fun v => UART_WRITTEN_ref.(write_to) v s) (UART_WRITTEN_ref.(of_regval) v) else - if string_dec reg_name "UART_WDATA" then option_map (fun v => UART_WDATA_ref.(write_to) v s) (UART_WDATA_ref.(of_regval) v) else - if string_dec reg_name "GPR" then option_map (fun v => GPR_ref.(write_to) v s) (GPR_ref.(of_regval) v) else - if string_dec reg_name "LO" then option_map (fun v => LO_ref.(write_to) v s) (LO_ref.(of_regval) v) else - if string_dec reg_name "HI" then option_map (fun v => HI_ref.(write_to) v s) (HI_ref.(of_regval) v) else - if string_dec reg_name "delayedPC" then option_map (fun v => delayedPC_ref.(write_to) v s) (delayedPC_ref.(of_regval) v) else - if string_dec reg_name "inBranchDelay" then option_map (fun v => inBranchDelay_ref.(write_to) v s) (inBranchDelay_ref.(of_regval) v) else - if string_dec reg_name "branchPending" then option_map (fun v => branchPending_ref.(write_to) v s) (branchPending_ref.(of_regval) v) else - if string_dec reg_name "CP0Status" then option_map (fun v => CP0Status_ref.(write_to) v s) (CP0Status_ref.(of_regval) v) else - if string_dec reg_name "CP0ConfigK0" then option_map (fun v => CP0ConfigK0_ref.(write_to) v s) (CP0ConfigK0_ref.(of_regval) v) else - if string_dec reg_name "CP0UserLocal" then option_map (fun v => CP0UserLocal_ref.(write_to) v s) (CP0UserLocal_ref.(of_regval) v) else - if string_dec reg_name "CP0HWREna" then option_map (fun v => CP0HWREna_ref.(write_to) v s) (CP0HWREna_ref.(of_regval) v) else - if string_dec reg_name "CP0Count" then option_map (fun v => CP0Count_ref.(write_to) v s) (CP0Count_ref.(of_regval) v) else - if string_dec reg_name "CP0BadVAddr" then option_map (fun v => CP0BadVAddr_ref.(write_to) v s) (CP0BadVAddr_ref.(of_regval) v) else - if string_dec reg_name "CP0LLAddr" then option_map (fun v => CP0LLAddr_ref.(write_to) v s) (CP0LLAddr_ref.(of_regval) v) else - if string_dec reg_name "CP0LLBit" then option_map (fun v => CP0LLBit_ref.(write_to) v s) (CP0LLBit_ref.(of_regval) v) else - if string_dec reg_name "CP0ErrorEPC" then option_map (fun v => CP0ErrorEPC_ref.(write_to) v s) (CP0ErrorEPC_ref.(of_regval) v) else - if string_dec reg_name "CP0EPC" then option_map (fun v => CP0EPC_ref.(write_to) v s) (CP0EPC_ref.(of_regval) v) else - if string_dec reg_name "CP0Cause" then option_map (fun v => CP0Cause_ref.(write_to) v s) (CP0Cause_ref.(of_regval) v) else - if string_dec reg_name "CP0Compare" then option_map (fun v => CP0Compare_ref.(write_to) v s) (CP0Compare_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry63" then option_map (fun v => TLBEntry63_ref.(write_to) v s) (TLBEntry63_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry62" then option_map (fun v => TLBEntry62_ref.(write_to) v s) (TLBEntry62_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry61" then option_map (fun v => TLBEntry61_ref.(write_to) v s) (TLBEntry61_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry60" then option_map (fun v => TLBEntry60_ref.(write_to) v s) (TLBEntry60_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry59" then option_map (fun v => TLBEntry59_ref.(write_to) v s) (TLBEntry59_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry58" then option_map (fun v => TLBEntry58_ref.(write_to) v s) (TLBEntry58_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry57" then option_map (fun v => TLBEntry57_ref.(write_to) v s) (TLBEntry57_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry56" then option_map (fun v => TLBEntry56_ref.(write_to) v s) (TLBEntry56_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry55" then option_map (fun v => TLBEntry55_ref.(write_to) v s) (TLBEntry55_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry54" then option_map (fun v => TLBEntry54_ref.(write_to) v s) (TLBEntry54_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry53" then option_map (fun v => TLBEntry53_ref.(write_to) v s) (TLBEntry53_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry52" then option_map (fun v => TLBEntry52_ref.(write_to) v s) (TLBEntry52_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry51" then option_map (fun v => TLBEntry51_ref.(write_to) v s) (TLBEntry51_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry50" then option_map (fun v => TLBEntry50_ref.(write_to) v s) (TLBEntry50_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry49" then option_map (fun v => TLBEntry49_ref.(write_to) v s) (TLBEntry49_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry48" then option_map (fun v => TLBEntry48_ref.(write_to) v s) (TLBEntry48_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry47" then option_map (fun v => TLBEntry47_ref.(write_to) v s) (TLBEntry47_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry46" then option_map (fun v => TLBEntry46_ref.(write_to) v s) (TLBEntry46_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry45" then option_map (fun v => TLBEntry45_ref.(write_to) v s) (TLBEntry45_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry44" then option_map (fun v => TLBEntry44_ref.(write_to) v s) (TLBEntry44_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry43" then option_map (fun v => TLBEntry43_ref.(write_to) v s) (TLBEntry43_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry42" then option_map (fun v => TLBEntry42_ref.(write_to) v s) (TLBEntry42_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry41" then option_map (fun v => TLBEntry41_ref.(write_to) v s) (TLBEntry41_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry40" then option_map (fun v => TLBEntry40_ref.(write_to) v s) (TLBEntry40_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry39" then option_map (fun v => TLBEntry39_ref.(write_to) v s) (TLBEntry39_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry38" then option_map (fun v => TLBEntry38_ref.(write_to) v s) (TLBEntry38_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry37" then option_map (fun v => TLBEntry37_ref.(write_to) v s) (TLBEntry37_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry36" then option_map (fun v => TLBEntry36_ref.(write_to) v s) (TLBEntry36_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry35" then option_map (fun v => TLBEntry35_ref.(write_to) v s) (TLBEntry35_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry34" then option_map (fun v => TLBEntry34_ref.(write_to) v s) (TLBEntry34_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry33" then option_map (fun v => TLBEntry33_ref.(write_to) v s) (TLBEntry33_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry32" then option_map (fun v => TLBEntry32_ref.(write_to) v s) (TLBEntry32_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry31" then option_map (fun v => TLBEntry31_ref.(write_to) v s) (TLBEntry31_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry30" then option_map (fun v => TLBEntry30_ref.(write_to) v s) (TLBEntry30_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry29" then option_map (fun v => TLBEntry29_ref.(write_to) v s) (TLBEntry29_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry28" then option_map (fun v => TLBEntry28_ref.(write_to) v s) (TLBEntry28_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry27" then option_map (fun v => TLBEntry27_ref.(write_to) v s) (TLBEntry27_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry26" then option_map (fun v => TLBEntry26_ref.(write_to) v s) (TLBEntry26_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry25" then option_map (fun v => TLBEntry25_ref.(write_to) v s) (TLBEntry25_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry24" then option_map (fun v => TLBEntry24_ref.(write_to) v s) (TLBEntry24_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry23" then option_map (fun v => TLBEntry23_ref.(write_to) v s) (TLBEntry23_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry22" then option_map (fun v => TLBEntry22_ref.(write_to) v s) (TLBEntry22_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry21" then option_map (fun v => TLBEntry21_ref.(write_to) v s) (TLBEntry21_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry20" then option_map (fun v => TLBEntry20_ref.(write_to) v s) (TLBEntry20_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry19" then option_map (fun v => TLBEntry19_ref.(write_to) v s) (TLBEntry19_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry18" then option_map (fun v => TLBEntry18_ref.(write_to) v s) (TLBEntry18_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry17" then option_map (fun v => TLBEntry17_ref.(write_to) v s) (TLBEntry17_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry16" then option_map (fun v => TLBEntry16_ref.(write_to) v s) (TLBEntry16_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry15" then option_map (fun v => TLBEntry15_ref.(write_to) v s) (TLBEntry15_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry14" then option_map (fun v => TLBEntry14_ref.(write_to) v s) (TLBEntry14_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry13" then option_map (fun v => TLBEntry13_ref.(write_to) v s) (TLBEntry13_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry12" then option_map (fun v => TLBEntry12_ref.(write_to) v s) (TLBEntry12_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry11" then option_map (fun v => TLBEntry11_ref.(write_to) v s) (TLBEntry11_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry10" then option_map (fun v => TLBEntry10_ref.(write_to) v s) (TLBEntry10_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry09" then option_map (fun v => TLBEntry09_ref.(write_to) v s) (TLBEntry09_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry08" then option_map (fun v => TLBEntry08_ref.(write_to) v s) (TLBEntry08_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry07" then option_map (fun v => TLBEntry07_ref.(write_to) v s) (TLBEntry07_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry06" then option_map (fun v => TLBEntry06_ref.(write_to) v s) (TLBEntry06_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry05" then option_map (fun v => TLBEntry05_ref.(write_to) v s) (TLBEntry05_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry04" then option_map (fun v => TLBEntry04_ref.(write_to) v s) (TLBEntry04_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry03" then option_map (fun v => TLBEntry03_ref.(write_to) v s) (TLBEntry03_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry02" then option_map (fun v => TLBEntry02_ref.(write_to) v s) (TLBEntry02_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry01" then option_map (fun v => TLBEntry01_ref.(write_to) v s) (TLBEntry01_ref.(of_regval) v) else - if string_dec reg_name "TLBEntry00" then option_map (fun v => TLBEntry00_ref.(write_to) v s) (TLBEntry00_ref.(of_regval) v) else - if string_dec reg_name "TLBXContext" then option_map (fun v => TLBXContext_ref.(write_to) v s) (TLBXContext_ref.(of_regval) v) else - if string_dec reg_name "TLBEntryHi" then option_map (fun v => TLBEntryHi_ref.(write_to) v s) (TLBEntryHi_ref.(of_regval) v) else - if string_dec reg_name "TLBWired" then option_map (fun v => TLBWired_ref.(write_to) v s) (TLBWired_ref.(of_regval) v) else - if string_dec reg_name "TLBPageMask" then option_map (fun v => TLBPageMask_ref.(write_to) v s) (TLBPageMask_ref.(of_regval) v) else - if string_dec reg_name "TLBContext" then option_map (fun v => TLBContext_ref.(write_to) v s) (TLBContext_ref.(of_regval) v) else - if string_dec reg_name "TLBEntryLo1" then option_map (fun v => TLBEntryLo1_ref.(write_to) v s) (TLBEntryLo1_ref.(of_regval) v) else - if string_dec reg_name "TLBEntryLo0" then option_map (fun v => TLBEntryLo0_ref.(write_to) v s) (TLBEntryLo0_ref.(of_regval) v) else - if string_dec reg_name "TLBRandom" then option_map (fun v => TLBRandom_ref.(write_to) v s) (TLBRandom_ref.(of_regval) v) else - if string_dec reg_name "TLBIndex" then option_map (fun v => TLBIndex_ref.(write_to) v s) (TLBIndex_ref.(of_regval) v) else - if string_dec reg_name "TLBProbe" then option_map (fun v => TLBProbe_ref.(write_to) v s) (TLBProbe_ref.(of_regval) v) else - if string_dec reg_name "nextPC" then option_map (fun v => nextPC_ref.(write_to) v s) (nextPC_ref.(of_regval) v) else - if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else - None. - -Definition register_accessors := (get_regval, set_regval). - - -Definition MR a r := monadR register_value a r exception. -Definition M a := monad register_value a exception. diff --git a/snapshots/coq/riscv/riscv.v b/snapshots/coq/riscv/riscv.v new file mode 100644 index 00000000..620e5c37 --- /dev/null +++ b/snapshots/coq/riscv/riscv.v @@ -0,0 +1,37814 @@ +(*Generated by Sail from riscv.*) +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_string. +Require Import Sail2_real. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import Sail2_state. +Require Import riscv_types. +Require Import riscv_extras. +Import ListNotations. +Open Scope string. +Open Scope bool. +Section Content. + +Definition eq_unit (g__147 : unit) (g__148 : unit) : bool := true. + +Definition neq_int (x : Z) (y : Z) : bool := negb (Z.eqb x y). + +Definition neq_bool (x : bool) (y : bool) : bool := negb (Bool.eqb x y). + +Axiom eq_real : forall (_ : R) (_ : R) , bool. + +Axiom lteq_real : forall (_ : R) (_ : R) , bool. + +Axiom lt_real : forall (_ : R) (_ : R) , bool. + +Axiom gteq_real : forall (_ : R) (_ : R) , bool. + +Axiom gt_real : forall (_ : R) (_ : R) , bool. + +Definition hex_bits_1_forwards_matches (bv : mword 1) : bool := true. + +Definition hex_bits_1_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_1_matches_prefix s) with + | Some (g__144,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__145 := Some ((g__144, n)) in + false + | g__145 => false + end)) then + true + else + let g__146 := s in + false + end. + +Definition hex_bits_1_backwards (s : string) +: M (mword 1) := + + (match (hex_bits_1_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 1) + | _ => exit tt : M (mword 1) + end) + : M (mword 1). + +Definition hex_bits_2_forwards_matches (bv : mword 2) : bool := true. + +Definition hex_bits_2_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_2_matches_prefix s) with + | Some (g__141,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__142 := Some ((g__141, n)) in + false + | g__142 => false + end)) then + true + else + let g__143 := s in + false + end. + +Definition hex_bits_2_backwards (s : string) +: M (mword 2) := + + (match (hex_bits_2_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 2) + | _ => exit tt : M (mword 2) + end) + : M (mword 2). + +Definition hex_bits_3_forwards_matches (bv : mword 3) : bool := true. + +Definition hex_bits_3_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_3_matches_prefix s) with + | Some (g__138,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__139 := Some ((g__138, n)) in + false + | g__139 => false + end)) then + true + else + let g__140 := s in + false + end. + +Definition hex_bits_3_backwards (s : string) +: M (mword 3) := + + (match (hex_bits_3_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 3) + | _ => exit tt : M (mword 3) + end) + : M (mword 3). + +Definition hex_bits_4_forwards_matches (bv : mword 4) : bool := true. + +Definition hex_bits_4_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_4_matches_prefix s) with + | Some (g__135,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__136 := Some ((g__135, n)) in + false + | g__136 => false + end)) then + true + else + let g__137 := s in + false + end. + +Definition hex_bits_4_backwards (s : string) +: M (mword 4) := + + (match (hex_bits_4_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 4) + | _ => exit tt : M (mword 4) + end) + : M (mword 4). + +Definition hex_bits_5_forwards_matches (bv : mword 5) : bool := true. + +Definition hex_bits_5_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_5_matches_prefix s) with + | Some (g__132,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__133 := Some ((g__132, n)) in + false + | g__133 => false + end)) then + true + else + let g__134 := s in + false + end. + +Definition hex_bits_5_backwards (s : string) +: M (mword 5) := + + (match (hex_bits_5_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 5) + | _ => exit tt : M (mword 5) + end) + : M (mword 5). + +Definition hex_bits_6_forwards_matches (bv : mword 6) : bool := true. + +Definition hex_bits_6_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_6_matches_prefix s) with + | Some (g__129,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__130 := Some ((g__129, n)) in + false + | g__130 => false + end)) then + true + else + let g__131 := s in + false + end. + +Definition hex_bits_6_backwards (s : string) +: M (mword 6) := + + (match (hex_bits_6_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 6) + | _ => exit tt : M (mword 6) + end) + : M (mword 6). + +Definition hex_bits_7_forwards_matches (bv : mword 7) : bool := true. + +Definition hex_bits_7_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_7_matches_prefix s) with + | Some (g__126,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__127 := Some ((g__126, n)) in + false + | g__127 => false + end)) then + true + else + let g__128 := s in + false + end. + +Definition hex_bits_7_backwards (s : string) +: M (mword 7) := + + (match (hex_bits_7_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 7) + | _ => exit tt : M (mword 7) + end) + : M (mword 7). + +Definition hex_bits_8_forwards_matches (bv : mword 8) : bool := true. + +Definition hex_bits_8_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_8_matches_prefix s) with + | Some (g__123,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__124 := Some ((g__123, n)) in + false + | g__124 => false + end)) then + true + else + let g__125 := s in + false + end. + +Definition hex_bits_8_backwards (s : string) +: M (mword 8) := + + (match (hex_bits_8_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 8) + | _ => exit tt : M (mword 8) + end) + : M (mword 8). + +Definition hex_bits_9_forwards_matches (bv : mword 9) : bool := true. + +Definition hex_bits_9_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_9_matches_prefix s) with + | Some (g__120,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__121 := Some ((g__120, n)) in + false + | g__121 => false + end)) then + true + else + let g__122 := s in + false + end. + +Definition hex_bits_9_backwards (s : string) +: M (mword 9) := + + (match (hex_bits_9_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 9) + | _ => exit tt : M (mword 9) + end) + : M (mword 9). + +Definition hex_bits_10_forwards_matches (bv : mword 10) : bool := true. + +Definition hex_bits_10_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_10_matches_prefix s) with + | Some (g__117,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__118 := Some ((g__117, n)) in + false + | g__118 => false + end)) then + true + else + let g__119 := s in + false + end. + +Definition hex_bits_10_backwards (s : string) +: M (mword 10) := + + (match (hex_bits_10_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 10) + | _ => exit tt : M (mword 10) + end) + : M (mword 10). + +Definition hex_bits_11_forwards_matches (bv : mword 11) : bool := true. + +Definition hex_bits_11_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_11_matches_prefix s) with + | Some (g__114,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__115 := Some ((g__114, n)) in + false + | g__115 => false + end)) then + true + else + let g__116 := s in + false + end. + +Definition hex_bits_11_backwards (s : string) +: M (mword 11) := + + (match (hex_bits_11_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 11) + | _ => exit tt : M (mword 11) + end) + : M (mword 11). + +Definition hex_bits_12_forwards_matches (bv : mword 12) : bool := true. + +Definition hex_bits_12_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_12_matches_prefix s) with + | Some (g__111,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__112 := Some ((g__111, n)) in + false + | g__112 => false + end)) then + true + else + let g__113 := s in + false + end. + +Definition hex_bits_12_backwards (s : string) +: M (mword 12) := + + (match (hex_bits_12_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 12) + | _ => exit tt : M (mword 12) + end) + : M (mword 12). + +Definition hex_bits_13_forwards_matches (bv : mword 13) : bool := true. + +Definition hex_bits_13_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_13_matches_prefix s) with + | Some (g__108,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__109 := Some ((g__108, n)) in + false + | g__109 => false + end)) then + true + else + let g__110 := s in + false + end. + +Definition hex_bits_13_backwards (s : string) +: M (mword 13) := + + (match (hex_bits_13_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 13) + | _ => exit tt : M (mword 13) + end) + : M (mword 13). + +Definition hex_bits_14_forwards_matches (bv : mword 14) : bool := true. + +Definition hex_bits_14_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_14_matches_prefix s) with + | Some (g__105,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__106 := Some ((g__105, n)) in + false + | g__106 => false + end)) then + true + else + let g__107 := s in + false + end. + +Definition hex_bits_14_backwards (s : string) +: M (mword 14) := + + (match (hex_bits_14_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 14) + | _ => exit tt : M (mword 14) + end) + : M (mword 14). + +Definition hex_bits_15_forwards_matches (bv : mword 15) : bool := true. + +Definition hex_bits_15_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_15_matches_prefix s) with + | Some (g__102,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__103 := Some ((g__102, n)) in + false + | g__103 => false + end)) then + true + else + let g__104 := s in + false + end. + +Definition hex_bits_15_backwards (s : string) +: M (mword 15) := + + (match (hex_bits_15_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 15) + | _ => exit tt : M (mword 15) + end) + : M (mword 15). + +Definition hex_bits_16_forwards_matches (bv : mword 16) : bool := true. + +Definition hex_bits_16_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_16_matches_prefix s) with + | Some (g__99,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__100 := Some ((g__99, n)) in + false + | g__100 => false + end)) then + true + else + let g__101 := s in + false + end. + +Definition hex_bits_16_backwards (s : string) +: M (mword 16) := + + (match (hex_bits_16_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 16) + | _ => exit tt : M (mword 16) + end) + : M (mword 16). + +Definition hex_bits_17_forwards_matches (bv : mword 17) : bool := true. + +Definition hex_bits_17_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_17_matches_prefix s) with + | Some (g__96,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__97 := Some ((g__96, n)) in + false + | g__97 => false + end)) then + true + else + let g__98 := s in + false + end. + +Definition hex_bits_17_backwards (s : string) +: M (mword 17) := + + (match (hex_bits_17_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 17) + | _ => exit tt : M (mword 17) + end) + : M (mword 17). + +Definition hex_bits_18_forwards_matches (bv : mword 18) : bool := true. + +Definition hex_bits_18_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_18_matches_prefix s) with + | Some (g__93,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__94 := Some ((g__93, n)) in + false + | g__94 => false + end)) then + true + else + let g__95 := s in + false + end. + +Definition hex_bits_18_backwards (s : string) +: M (mword 18) := + + (match (hex_bits_18_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 18) + | _ => exit tt : M (mword 18) + end) + : M (mword 18). + +Definition hex_bits_19_forwards_matches (bv : mword 19) : bool := true. + +Definition hex_bits_19_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_19_matches_prefix s) with + | Some (g__90,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__91 := Some ((g__90, n)) in + false + | g__91 => false + end)) then + true + else + let g__92 := s in + false + end. + +Definition hex_bits_19_backwards (s : string) +: M (mword 19) := + + (match (hex_bits_19_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 19) + | _ => exit tt : M (mword 19) + end) + : M (mword 19). + +Definition hex_bits_20_forwards_matches (bv : mword 20) : bool := true. + +Definition hex_bits_20_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_20_matches_prefix s) with + | Some (g__87,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__88 := Some ((g__87, n)) in + false + | g__88 => false + end)) then + true + else + let g__89 := s in + false + end. + +Definition hex_bits_20_backwards (s : string) +: M (mword 20) := + + (match (hex_bits_20_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 20) + | _ => exit tt : M (mword 20) + end) + : M (mword 20). + +Definition hex_bits_21_forwards_matches (bv : mword 21) : bool := true. + +Definition hex_bits_21_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_21_matches_prefix s) with + | Some (g__84,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__85 := Some ((g__84, n)) in + false + | g__85 => false + end)) then + true + else + let g__86 := s in + false + end. + +Definition hex_bits_21_backwards (s : string) +: M (mword 21) := + + (match (hex_bits_21_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 21) + | _ => exit tt : M (mword 21) + end) + : M (mword 21). + +Definition hex_bits_22_forwards_matches (bv : mword 22) : bool := true. + +Definition hex_bits_22_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_22_matches_prefix s) with + | Some (g__81,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__82 := Some ((g__81, n)) in + false + | g__82 => false + end)) then + true + else + let g__83 := s in + false + end. + +Definition hex_bits_22_backwards (s : string) +: M (mword 22) := + + (match (hex_bits_22_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 22) + | _ => exit tt : M (mword 22) + end) + : M (mword 22). + +Definition hex_bits_23_forwards_matches (bv : mword 23) : bool := true. + +Definition hex_bits_23_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_23_matches_prefix s) with + | Some (g__78,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__79 := Some ((g__78, n)) in + false + | g__79 => false + end)) then + true + else + let g__80 := s in + false + end. + +Definition hex_bits_23_backwards (s : string) +: M (mword 23) := + + (match (hex_bits_23_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 23) + | _ => exit tt : M (mword 23) + end) + : M (mword 23). + +Definition hex_bits_24_forwards_matches (bv : mword 24) : bool := true. + +Definition hex_bits_24_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_24_matches_prefix s) with + | Some (g__75,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__76 := Some ((g__75, n)) in + false + | g__76 => false + end)) then + true + else + let g__77 := s in + false + end. + +Definition hex_bits_24_backwards (s : string) +: M (mword 24) := + + (match (hex_bits_24_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 24) + | _ => exit tt : M (mword 24) + end) + : M (mword 24). + +Definition hex_bits_25_forwards_matches (bv : mword 25) : bool := true. + +Definition hex_bits_25_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_25_matches_prefix s) with + | Some (g__72,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__73 := Some ((g__72, n)) in + false + | g__73 => false + end)) then + true + else + let g__74 := s in + false + end. + +Definition hex_bits_25_backwards (s : string) +: M (mword 25) := + + (match (hex_bits_25_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 25) + | _ => exit tt : M (mword 25) + end) + : M (mword 25). + +Definition hex_bits_26_forwards_matches (bv : mword 26) : bool := true. + +Definition hex_bits_26_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_26_matches_prefix s) with + | Some (g__69,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__70 := Some ((g__69, n)) in + false + | g__70 => false + end)) then + true + else + let g__71 := s in + false + end. + +Definition hex_bits_26_backwards (s : string) +: M (mword 26) := + + (match (hex_bits_26_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 26) + | _ => exit tt : M (mword 26) + end) + : M (mword 26). + +Definition hex_bits_27_forwards_matches (bv : mword 27) : bool := true. + +Definition hex_bits_27_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_27_matches_prefix s) with + | Some (g__66,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__67 := Some ((g__66, n)) in + false + | g__67 => false + end)) then + true + else + let g__68 := s in + false + end. + +Definition hex_bits_27_backwards (s : string) +: M (mword 27) := + + (match (hex_bits_27_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 27) + | _ => exit tt : M (mword 27) + end) + : M (mword 27). + +Definition hex_bits_28_forwards_matches (bv : mword 28) : bool := true. + +Definition hex_bits_28_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_28_matches_prefix s) with + | Some (g__63,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__64 := Some ((g__63, n)) in + false + | g__64 => false + end)) then + true + else + let g__65 := s in + false + end. + +Definition hex_bits_28_backwards (s : string) +: M (mword 28) := + + (match (hex_bits_28_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 28) + | _ => exit tt : M (mword 28) + end) + : M (mword 28). + +Definition hex_bits_29_forwards_matches (bv : mword 29) : bool := true. + +Definition hex_bits_29_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_29_matches_prefix s) with + | Some (g__60,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__61 := Some ((g__60, n)) in + false + | g__61 => false + end)) then + true + else + let g__62 := s in + false + end. + +Definition hex_bits_29_backwards (s : string) +: M (mword 29) := + + (match (hex_bits_29_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 29) + | _ => exit tt : M (mword 29) + end) + : M (mword 29). + +Definition hex_bits_30_forwards_matches (bv : mword 30) : bool := true. + +Definition hex_bits_30_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_30_matches_prefix s) with + | Some (g__57,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__58 := Some ((g__57, n)) in + false + | g__58 => false + end)) then + true + else + let g__59 := s in + false + end. + +Definition hex_bits_30_backwards (s : string) +: M (mword 30) := + + (match (hex_bits_30_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 30) + | _ => exit tt : M (mword 30) + end) + : M (mword 30). + +Definition hex_bits_31_forwards_matches (bv : mword 31) : bool := true. + +Definition hex_bits_31_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_31_matches_prefix s) with + | Some (g__54,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__55 := Some ((g__54, n)) in + false + | g__55 => false + end)) then + true + else + let g__56 := s in + false + end. + +Definition hex_bits_31_backwards (s : string) +: M (mword 31) := + + (match (hex_bits_31_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 31) + | _ => exit tt : M (mword 31) + end) + : M (mword 31). + +Definition hex_bits_32_forwards_matches (bv : mword 32) : bool := true. + +Definition hex_bits_32_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_32_matches_prefix s) with + | Some (g__51,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__52 := Some ((g__51, n)) in + false + | g__52 => false + end)) then + true + else + let g__53 := s in + false + end. + +Definition hex_bits_32_backwards (s : string) +: M (mword 32) := + + (match (hex_bits_32_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 32) + | _ => exit tt : M (mword 32) + end) + : M (mword 32). + +Definition hex_bits_33_forwards_matches (bv : mword 33) : bool := true. + +Definition hex_bits_33_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_33_matches_prefix s) with + | Some (g__48,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__49 := Some ((g__48, n)) in + false + | g__49 => false + end)) then + true + else + let g__50 := s in + false + end. + +Definition hex_bits_33_backwards (s : string) +: M (mword 33) := + + (match (hex_bits_33_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 33) + | _ => exit tt : M (mword 33) + end) + : M (mword 33). + +Definition hex_bits_48_forwards_matches (bv : mword 48) : bool := true. + +Definition hex_bits_48_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_48_matches_prefix s) with + | Some (g__45,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__46 := Some ((g__45, n)) in + false + | g__46 => false + end)) then + true + else + let g__47 := s in + false + end. + +Definition hex_bits_48_backwards (s : string) +: M (mword 48) := + + (match (hex_bits_48_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 48) + | _ => exit tt : M (mword 48) + end) + : M (mword 48). + +Definition hex_bits_64_forwards_matches (bv : mword 64) : bool := true. + +Definition hex_bits_64_backwards_matches (s : string) +: bool := + + match s with + | s => + if sumbool_of_bool ((match (hex_bits_64_matches_prefix s) with + | Some (g__42,(existT _ n _)) => + if sumbool_of_bool ((Z.eqb n (projT1 (string_length s)))) then true + else + let g__43 := Some ((g__42, n)) in + false + | g__43 => false + end)) then + true + else + let g__44 := s in + false + end. + +Definition hex_bits_64_backwards (s : string) +: M (mword 64) := + + (match (hex_bits_64_matches_prefix s) with + | Some (bv,(existT _ n _)) => returnm (bv : mword 64) + | _ => exit tt : M (mword 64) + end) + : M (mword 64). + +Axiom vcons : forall {n : Z} {a : Type} (_ : a) (_ : vec a n) , vec a (n + 1). + +Axiom vector_concat : forall {n : Z} {m : Z} {a : Type} (_ : vec a n) (_ : vec a m) , vec a (n + m). + +Definition neq_vec {n : Z} (x : mword n) (y : mword n) : bool := negb (eq_vec x y). + + + +Axiom __raw_SetSlice_int : forall (w : Z) (_ : Z) (_ : Z) (_ : mword w) , Z. + +Definition __GetSlice_int (n : Z) (m : Z) (o : Z) `{ArithFact (n >= 0)} +: mword n := + + get_slice_int n m o. + +Axiom __raw_SetSlice_bits : forall (n : Z) (w : Z) (_ : mword n) (_ : Z) (_ : mword w) , mword n. + +Axiom __raw_GetSlice_bits : forall + +(n : Z) (w : Z) (_ : mword n) (_ : Z) +`{ArithFact (w >= 0)}, +mword w. + +Axiom __SignExtendSlice : forall {m : Z} (_ : mword m) (_ : Z) (_ : Z) , mword m. + +Axiom __ZeroExtendSlice : forall {m : Z} (_ : mword m) (_ : Z) (_ : Z) , mword m. + +Definition cast_unit_vec (b : bitU) +: M (mword 1) := + + (match b with + | B0 => returnm ((vec_of_bits [B0] : mword 1) : mword 1) + | B1 => returnm ((vec_of_bits [B1] : mword 1) : mword 1) + | _ => exit tt : M (mword 1) + end) + : M (mword 1). + +Axiom DecStr : forall (_ : Z) , string. + +Axiom HexStr : forall (_ : Z) , string. + +Axiom real_power : forall (_ : R) (_ : Z) , R. + +Axiom add_real : forall (_ : R) (_ : R) , R. + +Axiom sub_real : forall (_ : R) (_ : R) , R. + +Axiom negate_real : forall (_ : R) , R. + +Axiom mult_real : forall (_ : R) (_ : R) , R. + +Axiom Sqrt : forall (_ : R) , R. + +Axiom RoundDown : forall (_ : R) , Z. + +Axiom RoundUp : forall (_ : R) , Z. + +Axiom abs_real : forall (_ : R) , R. + +Axiom quotient_nat : forall + +(_ : {n : Z & ArithFact (n >= 0)}) (_ : {n : Z & ArithFact (n >= 0)}) +, +{n : Z & ArithFact (n >= 0)}. + +Axiom quotient_real : forall (_ : R) (_ : R) , R. + +Axiom quotient : forall (_ : Z) (_ : Z) , Z. + +Axiom quot_round_zero : forall (_ : Z) (_ : Z) , Z. + +Axiom rem_round_zero : forall (_ : Z) (_ : Z) , Z. + +Axiom modulus : forall (_ : Z) (_ : Z) , Z. + +Axiom Real : forall (_ : Z) , R. + +Definition __RISCV_write (addr : mword 64) (width : Z) (data : mword (8 * width)) +: M (bool) := + + (write_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr data) + : M (bool). + +Axiom __TraceMemoryWrite : forall {m : Z} (n : Z) (_ : mword m) (_ : mword (8 * n)) , unit. + +Definition __RISCV_read (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool) +`{ArithFact (width >= 0)} +: M (option (mword (8 * width))) := + + (match (aq, rl, res) with + | (false, false, false) => + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) >>= fun w__0 : mword (8 * width) => + returnm ((Some + (w__0)) + : option (mword (8 * width))) + | (true, false, false) => + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) >>= fun w__1 : mword (8 * width) => + returnm ((Some + (w__1)) + : option (mword (8 * width))) + | (true, true, false) => + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) >>= fun w__2 : mword (8 * width) => + returnm ((Some + (w__2)) + : option (mword (8 * width))) + | (false, false, true) => + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) >>= fun w__3 : mword (8 * width) => + returnm ((Some + (w__3)) + : option (mword (8 * width))) + | (true, false, true) => + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) >>= fun w__4 : mword (8 * width) => + returnm ((Some + (w__4)) + : option (mword (8 * width))) + | (true, true, true) => + (read_ram 64 width + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) addr) >>= fun w__5 : mword (8 * width) => + returnm ((Some + (w__5)) + : option (mword (8 * width))) + | (false, true, false) => returnm (None : option (mword (8 * width))) + | (false, true, true) => returnm (None : option (mword (8 * width))) + end) + : M (option (mword (8 * width))). + +Axiom __TraceMemoryRead : forall {m : Z} (n : Z) (_ : mword m) (_ : mword (8 * n)) , unit. + +Definition ex_nat {ex30597_ : Z} (n : Z) `{ArithFact (0 <= ex30597_)} `{ArithFact (n = ex30597_)} +: {syn_n : Z & ArithFact (syn_n >= 0)} := + + build_ex(n). + +Definition ex_int {ex30599_ : Z} (n : Z) `{ArithFact (n = ex30599_)} +: {syn_n : Z & ArithFact (True)} := + + build_ex(n). + +Definition coerce_int_nat {ex30601_ : Z} (x : Z) `{ArithFact (x = ex30601_)} +: M ({n : Z & ArithFact (n >= 0)}) := + + assert_exp' (x >=? 0) "file ""prelude.sail"", line 1034, character 29 to line 1034, character 29: constraint('x >= 0)" >>= fun _ => + returnm (build_ex (x + : Z)). + +Definition EXTS {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} +: mword m__tv := + + sign_extend v m__tv. + +Definition EXTZ {n : Z} (m__tv : Z) (v : mword n) `{ArithFact (m__tv >= n)} +: mword m__tv := + + zero_extend v m__tv. + +Definition zopz0zI_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} +: bool := + + Z.ltb (projT1 (sint x)) (projT1 (sint y)). + +Definition zopz0zKzJ_s {n : Z} (x : mword n) (y : mword n) `{ArithFact (n >= (0 + 1))} +: bool := + + Z.geb (projT1 (sint x)) (projT1 (sint y)). + +Definition zopz0zI_u {n : Z} (x : mword n) (y : mword n) +: bool := + + Z.ltb (projT1 (uint x)) (projT1 (uint y)). + +Definition zopz0zKzJ_u {n : Z} (x : mword n) (y : mword n) +: bool := + + Z.geb (projT1 (uint x)) (projT1 (uint y)). + +Definition zopz0zIzJ_u {n : Z} (x : mword n) (y : mword n) +: bool := + + Z.leb (projT1 (uint x)) (projT1 (uint y)). + +Definition bool_to_bits (x : bool) +: mword 1 := + + if (x) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bit_to_bool (b : bitU) +: M (bool) := + + (match b with + | B1 => returnm (true : bool) + | B0 => returnm (false : bool) + | _ => exit tt : M (bool) + end) + : M (bool). + +Definition vector64 (n : Z) : mword 64 := get_slice_int 64 n 0. + +Definition to_bits (l : Z) (n : Z) `{ArithFact (l >= 0)} : mword l := get_slice_int l n 0. + +Axiom vector_update_subrange_inc : forall +{n : Z} +(_ : mword n) (m : Z) (o : Z) (_ : mword (o - (m - 1))) +, +mword n. + +Definition shift_right_arith64 (v : mword 64) (shift : mword 6) +: mword 64 := + + let v128 : bits 128 := EXTS 128 v in + subrange_vec_dec (shift_bits_right v128 shift) 63 0. + +Definition shift_right_arith32 (v : mword 32) (shift : mword 5) +: mword 32 := + + let v64 : bits 64 := EXTS 64 v in + subrange_vec_dec (shift_bits_right v64 shift) 31 0. + +Fixpoint _rec_n_leading_spaces (s : string) (_reclimit : Z) (_acc : Acc (Zwf 0) _reclimit) +{struct _acc} : M ({n : Z & ArithFact (n >= 0)}) := + + assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ => + let p0_ := s in + (if ((generic_eq p0_ "")) then returnm (build_ex (0 : Z)) + else + let p0_ := string_take s 1 in + (if ((generic_eq p0_ " ")) then + (_rec_n_leading_spaces (string_drop s 1) (Z.sub _reclimit 1) (_limit_reduces _acc)) >>= fun '(existT _ w__0 _ : {n : Z & ArithFact (n >= + 0)}) => + returnm (build_ex (projT1 (build_ex (Z.add 1 w__0) + : {_atom : Z & ArithFact (exists ex21215_ , _atom = (1 + ex21215_) /\ 0 <= ex21215_)}))) + else returnm (build_ex (0 : Z))) + : M ({n : Z & ArithFact (n >= 0)})) + : M ({n : Z & ArithFact (n >= 0)}). + +Definition n_leading_spaces (s : string) +: M ({n : Z & ArithFact (n >= 0)}) := + + (_rec_n_leading_spaces s ((projT1 (string_length s)) : Z) (Zwf_guarded _)) + : M ({n : Z & ArithFact (n >= 0)}). + +Definition spc_forwards '(tt : unit) : string := " ". + +Definition spc_backwards (s : string) : unit := tt. + +Definition spc_matches_prefix (s : string) +: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) := + + (n_leading_spaces s) >>= fun '(existT _ n _) => + let p0_ := n in + returnm ((if sumbool_of_bool ((Z.eqb p0_ 0)) then None + else Some ((tt, build_ex n))) + : option ((unit * {n : Z & ArithFact (n >= 0)}))). + +Definition opt_spc_forwards '(tt : unit) : string := "". + +Definition opt_spc_backwards (s : string) : unit := tt. + +Definition opt_spc_matches_prefix (s : string) +: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) := + + (n_leading_spaces s) >>= fun '(existT _ w__0 _ : {n : Z & ArithFact (n >= 0)}) => + returnm ((Some + ((tt, build_ex w__0))) + : option ((unit * {n : Z & ArithFact (n >= 0)}))). + +Definition def_spc_forwards '(tt : unit) : string := " ". + +Definition def_spc_backwards (s : string) : unit := tt. + +Definition def_spc_matches_prefix (s : string) +: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) := + + (opt_spc_matches_prefix s) + : M (option ((unit * {n : Z & ArithFact (n >= 0)}))). + +Definition xlen := 64. +Hint Unfold xlen : sail. +Definition xlen_max_unsigned := Z.sub (projT1 (pow2 xlen)) 1. +Hint Unfold xlen_max_unsigned : sail. +Definition xlen_max_signed := Z.sub (projT1 (pow2 (Z.sub xlen 1))) 1. +Hint Unfold xlen_max_signed : sail. +Definition xlen_min_signed := Z.sub 0 (projT1 (pow2 (Z.sub xlen 1))). +Hint Unfold xlen_min_signed : sail. +Definition regbits_to_regno (b : mword 5) +: {n : Z & ArithFact (0 <= n /\ (n + 1) <= 32)} := + + build_ex(let 'r := projT1 (uint b) in + r). + +Definition creg2reg_bits (creg : mword 3) +: mword 5 := + + concat_vec (vec_of_bits [B0;B1] : mword 2) creg. + +Definition zreg : regbits := (vec_of_bits [B0;B0;B0;B0;B0] : mword 5). +Hint Unfold zreg : sail. +Definition ra : regbits := (vec_of_bits [B0;B0;B0;B0;B1] : mword 5). +Hint Unfold ra : sail. +Definition sp : regbits := (vec_of_bits [B0;B0;B0;B1;B0] : mword 5). +Hint Unfold sp : sail. +Definition rX (r : Z) `{ArithFact (0 <= r /\ (r + 1) <= 32)} +: M (mword 64) := + + let p0_ := r in + (if sumbool_of_bool ((Z.eqb p0_ 0)) then + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64) + else if sumbool_of_bool ((Z.eqb p0_ 1)) then ((read_reg x1_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 2)) then ((read_reg x2_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 3)) then ((read_reg x3_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 4)) then ((read_reg x4_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 5)) then ((read_reg x5_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 6)) then ((read_reg x6_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 7)) then ((read_reg x7_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 8)) then ((read_reg x8_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 9)) then ((read_reg x9_ref) : M (mword 64)) : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 10)) then + ((read_reg x10_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 11)) then + ((read_reg x11_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 12)) then + ((read_reg x12_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 13)) then + ((read_reg x13_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 14)) then + ((read_reg x14_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 15)) then + ((read_reg x15_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 16)) then + ((read_reg x16_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 17)) then + ((read_reg x17_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 18)) then + ((read_reg x18_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 19)) then + ((read_reg x19_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 20)) then + ((read_reg x20_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 21)) then + ((read_reg x21_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 22)) then + ((read_reg x22_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 23)) then + ((read_reg x23_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 24)) then + ((read_reg x24_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 25)) then + ((read_reg x25_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 26)) then + ((read_reg x26_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 27)) then + ((read_reg x27_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 28)) then + ((read_reg x28_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 29)) then + ((read_reg x29_ref) : M (mword 64)) + : M (xlenbits) + else if sumbool_of_bool ((Z.eqb p0_ 30)) then + ((read_reg x30_ref) : M (mword 64)) + : M (xlenbits) + else ((read_reg x31_ref) : M (mword 64)) : M (xlenbits)) + : M (mword 64). + +Definition rvfi_wX (r : Z) (v : mword 64) `{ArithFact (0 <= r /\ (r + 1) <= 32)} : unit := tt. + +Definition wX (r : Z) (v : mword 64) `{ArithFact (0 <= r /\ (r + 1) <= 32)} +: M (unit) := + + let p0_ := r in + (if sumbool_of_bool ((Z.eqb p0_ 0)) then returnm (tt : unit) + else if sumbool_of_bool ((Z.eqb p0_ 1)) then write_reg x1_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 2)) then write_reg x2_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 3)) then write_reg x3_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 4)) then write_reg x4_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 5)) then write_reg x5_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 6)) then write_reg x6_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 7)) then write_reg x7_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 8)) then write_reg x8_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 9)) then write_reg x9_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 10)) then write_reg x10_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 11)) then write_reg x11_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 12)) then write_reg x12_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 13)) then write_reg x13_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 14)) then write_reg x14_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 15)) then write_reg x15_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 16)) then write_reg x16_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 17)) then write_reg x17_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 18)) then write_reg x18_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 19)) then write_reg x19_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 20)) then write_reg x20_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 21)) then write_reg x21_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 22)) then write_reg x22_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 23)) then write_reg x23_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 24)) then write_reg x24_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 25)) then write_reg x25_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 26)) then write_reg x26_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 27)) then write_reg x27_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 28)) then write_reg x28_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 29)) then write_reg x29_ref v : M (unit) + else if sumbool_of_bool ((Z.eqb p0_ 30)) then write_reg x30_ref v : M (unit) + else write_reg x31_ref v : M (unit)) >> + returnm ((if ((neq_int r 0)) then + let '_ := (rvfi_wX r v) : unit in + print_endline + (String.append "x" + (String.append (string_of_int r) (String.append " <- " (string_of_bits v)))) + else tt) + : unit). + +Definition reg_name_abi (r : mword 5) +: string := + + let b__0 := r in + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))))) + then + "zero" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))))) + then + "ra" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))))) + then + "sp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))))) + then + "gp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))))) + then + "tp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : mword 5))))) + then + "t0" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : mword 5))))) + then + "t1" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : mword 5))))) + then + "t2" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))))) + then + "fp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : mword 5))))) + then + "s1" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : mword 5))))) + then + "a0" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : mword 5))))) + then + "a1" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))))) + then + "a2" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : mword 5))))) + then + "a3" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : mword 5))))) + then + "a4" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : mword 5))))) + then + "a5" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))))) + then + "a6" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : mword 5))))) + then + "a7" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : mword 5))))) + then + "s2" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : mword 5))))) + then + "s3" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))))) + then + "s4" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : mword 5))))) + then + "s5" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : mword 5))))) + then + "s6" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : mword 5))))) + then + "s7" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))))) + then + "s8" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : mword 5))))) + then + "s9" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : mword 5))))) + then + "s10" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : mword 5))))) + then + "s11" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))))) + then + "t3" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))))) + then + "t4" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : mword 5))))) + then + "t5" + else "t6". + +Definition Architecture_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: Architecture := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RV32 + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RV64 + else RV128. + +Definition num_of_Architecture (arg_ : Architecture) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | RV32 => 0 | RV64 => 1 | RV128 => 2 end). + +Definition architecture (a : mword 2) +: option Architecture := + + let b__0 := a in + if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Some (RV32) + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then Some (RV64) + else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then Some (RV128) + else None. + +Definition arch_to_bits (a : Architecture) +: mword 2 := + + match a with + | RV32 => (vec_of_bits [B0;B1] : mword 2) + | RV64 => (vec_of_bits [B1;B0] : mword 2) + | RV128 => (vec_of_bits [B1;B1] : mword 2) + end. + +Definition Privilege_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: Privilege := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then User + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Supervisor + else Machine. + +Definition num_of_Privilege (arg_ : Privilege) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | User => 0 | Supervisor => 1 | Machine => 2 end). + +Definition privLevel_to_bits (p : Privilege) +: mword 2 := + + match p with + | User => (vec_of_bits [B0;B0] : mword 2) + | Supervisor => (vec_of_bits [B0;B1] : mword 2) + | Machine => (vec_of_bits [B1;B1] : mword 2) + end. + +Definition privLevel_of_bits (p : mword 2) +: Privilege := + + let b__0 := p in + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then User + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Supervisor + else Machine. + +Definition privLevel_to_str (p : Privilege) +: string := + + match p with | User => "U" | Supervisor => "S" | Machine => "M" end. + +Definition AccessType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: AccessType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Read + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Write + else if sumbool_of_bool ((Z.eqb p0_ 2)) then ReadWrite + else Execute. + +Definition num_of_AccessType (arg_ : AccessType) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | Read => 0 | Write => 1 | ReadWrite => 2 | Execute => 3 end). + +Definition accessType_to_str (a : AccessType) +: string := + + match a with | Read => "R" | Write => "W" | ReadWrite => "RW" | Execute => "X" end. + +Definition ReadType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 1)} +: ReadType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Instruction + else Data. + +Definition num_of_ReadType (arg_ : ReadType) +: {e : Z & ArithFact (0 <= e /\ e <= 1)} := + + build_ex(match arg_ with | Instruction => 0 | Data => 1 end). + +Definition readType_to_str (r : ReadType) +: string := + + match r with | Instruction => "I" | Data => "D" end. + +Definition word_width_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: word_width := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then BYTE + else if sumbool_of_bool ((Z.eqb p0_ 1)) then HALF + else if sumbool_of_bool ((Z.eqb p0_ 2)) then WORD + else DOUBLE. + +Definition num_of_word_width (arg_ : word_width) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | BYTE => 0 | HALF => 1 | WORD => 2 | DOUBLE => 3 end). + +Definition InterruptType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 8)} +: InterruptType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then I_U_Software + else if sumbool_of_bool ((Z.eqb p0_ 1)) then I_S_Software + else if sumbool_of_bool ((Z.eqb p0_ 2)) then I_M_Software + else if sumbool_of_bool ((Z.eqb p0_ 3)) then I_U_Timer + else if sumbool_of_bool ((Z.eqb p0_ 4)) then I_S_Timer + else if sumbool_of_bool ((Z.eqb p0_ 5)) then I_M_Timer + else if sumbool_of_bool ((Z.eqb p0_ 6)) then I_U_External + else if sumbool_of_bool ((Z.eqb p0_ 7)) then I_S_External + else I_M_External. + +Definition num_of_InterruptType (arg_ : InterruptType) +: {e : Z & ArithFact (0 <= e /\ e <= 8)} := + + build_ex(match arg_ with + | I_U_Software => 0 + | I_S_Software => 1 + | I_M_Software => 2 + | I_U_Timer => 3 + | I_S_Timer => 4 + | I_M_Timer => 5 + | I_U_External => 6 + | I_S_External => 7 + | I_M_External => 8 + end). + +Definition interruptType_to_bits (i : InterruptType) +: mword 4 := + + match i with + | I_U_Software => (vec_of_bits [B0;B0;B0;B0] : mword 4) + | I_S_Software => (vec_of_bits [B0;B0;B0;B1] : mword 4) + | I_M_Software => (vec_of_bits [B0;B0;B1;B1] : mword 4) + | I_U_Timer => (vec_of_bits [B0;B1;B0;B0] : mword 4) + | I_S_Timer => (vec_of_bits [B0;B1;B0;B1] : mword 4) + | I_M_Timer => (vec_of_bits [B0;B1;B1;B1] : mword 4) + | I_U_External => (vec_of_bits [B1;B0;B0;B0] : mword 4) + | I_S_External => (vec_of_bits [B1;B0;B0;B1] : mword 4) + | I_M_External => (vec_of_bits [B1;B0;B1;B1] : mword 4) + end. + +Definition ExceptionType_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 15)} +: ExceptionType := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then E_Fetch_Addr_Align + else if sumbool_of_bool ((Z.eqb p0_ 1)) then E_Fetch_Access_Fault + else if sumbool_of_bool ((Z.eqb p0_ 2)) then E_Illegal_Instr + else if sumbool_of_bool ((Z.eqb p0_ 3)) then E_Breakpoint + else if sumbool_of_bool ((Z.eqb p0_ 4)) then E_Load_Addr_Align + else if sumbool_of_bool ((Z.eqb p0_ 5)) then E_Load_Access_Fault + else if sumbool_of_bool ((Z.eqb p0_ 6)) then E_SAMO_Addr_Align + else if sumbool_of_bool ((Z.eqb p0_ 7)) then E_SAMO_Access_Fault + else if sumbool_of_bool ((Z.eqb p0_ 8)) then E_U_EnvCall + else if sumbool_of_bool ((Z.eqb p0_ 9)) then E_S_EnvCall + else if sumbool_of_bool ((Z.eqb p0_ 10)) then E_Reserved_10 + else if sumbool_of_bool ((Z.eqb p0_ 11)) then E_M_EnvCall + else if sumbool_of_bool ((Z.eqb p0_ 12)) then E_Fetch_Page_Fault + else if sumbool_of_bool ((Z.eqb p0_ 13)) then E_Load_Page_Fault + else if sumbool_of_bool ((Z.eqb p0_ 14)) then E_Reserved_14 + else E_SAMO_Page_Fault. + +Definition num_of_ExceptionType (arg_ : ExceptionType) +: {e : Z & ArithFact (0 <= e /\ e <= 15)} := + + build_ex(match arg_ with + | E_Fetch_Addr_Align => 0 + | E_Fetch_Access_Fault => 1 + | E_Illegal_Instr => 2 + | E_Breakpoint => 3 + | E_Load_Addr_Align => 4 + | E_Load_Access_Fault => 5 + | E_SAMO_Addr_Align => 6 + | E_SAMO_Access_Fault => 7 + | E_U_EnvCall => 8 + | E_S_EnvCall => 9 + | E_Reserved_10 => 10 + | E_M_EnvCall => 11 + | E_Fetch_Page_Fault => 12 + | E_Load_Page_Fault => 13 + | E_Reserved_14 => 14 + | E_SAMO_Page_Fault => 15 + end). + +Definition exceptionType_to_bits (e : ExceptionType) +: mword 4 := + + match e with + | E_Fetch_Addr_Align => (vec_of_bits [B0;B0;B0;B0] : mword 4) + | E_Fetch_Access_Fault => (vec_of_bits [B0;B0;B0;B1] : mword 4) + | E_Illegal_Instr => (vec_of_bits [B0;B0;B1;B0] : mword 4) + | E_Breakpoint => (vec_of_bits [B0;B0;B1;B1] : mword 4) + | E_Load_Addr_Align => (vec_of_bits [B0;B1;B0;B0] : mword 4) + | E_Load_Access_Fault => (vec_of_bits [B0;B1;B0;B1] : mword 4) + | E_SAMO_Addr_Align => (vec_of_bits [B0;B1;B1;B0] : mword 4) + | E_SAMO_Access_Fault => (vec_of_bits [B0;B1;B1;B1] : mword 4) + | E_U_EnvCall => (vec_of_bits [B1;B0;B0;B0] : mword 4) + | E_S_EnvCall => (vec_of_bits [B1;B0;B0;B1] : mword 4) + | E_Reserved_10 => (vec_of_bits [B1;B0;B1;B0] : mword 4) + | E_M_EnvCall => (vec_of_bits [B1;B0;B1;B1] : mword 4) + | E_Fetch_Page_Fault => (vec_of_bits [B1;B1;B0;B0] : mword 4) + | E_Load_Page_Fault => (vec_of_bits [B1;B1;B0;B1] : mword 4) + | E_Reserved_14 => (vec_of_bits [B1;B1;B1;B0] : mword 4) + | E_SAMO_Page_Fault => (vec_of_bits [B1;B1;B1;B1] : mword 4) + end. + +Definition exceptionType_to_str (e : ExceptionType) +: string := + + match e with + | E_Fetch_Addr_Align => "misaligned-fetch" + | E_Fetch_Access_Fault => "fetch-access-fault" + | E_Illegal_Instr => "illegal-instruction" + | E_Breakpoint => "breakpoint" + | E_Load_Addr_Align => "misaligned-load" + | E_Load_Access_Fault => "load-access-fault" + | E_SAMO_Addr_Align => "misaliged-store/amo" + | E_SAMO_Access_Fault => "store/amo-access-fault" + | E_U_EnvCall => "u-call" + | E_S_EnvCall => "s-call" + | E_Reserved_10 => "reserved-0" + | E_M_EnvCall => "m-call" + | E_Fetch_Page_Fault => "fetch-page-fault" + | E_Load_Page_Fault => "load-page-fault" + | E_Reserved_14 => "reserved-1" + | E_SAMO_Page_Fault => "store/amo-page-fault" + end. + +Definition not_implemented {a : Type} (message : string) +: M (a) := + + (throw (Error_not_implemented + (message))) + : M (a). + +Definition internal_error {a : Type} (s : string) +: M (a) := + + assert_exp' false s >>= fun _ => (throw (Error_internal_error (tt))) : M (a). + +Definition TrapVectorMode_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: TrapVectorMode := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then TV_Direct + else if sumbool_of_bool ((Z.eqb p0_ 1)) then TV_Vector + else TV_Reserved. + +Definition num_of_TrapVectorMode (arg_ : TrapVectorMode) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | TV_Direct => 0 | TV_Vector => 1 | TV_Reserved => 2 end). + +Definition trapVectorMode_of_bits (m : mword 2) +: TrapVectorMode := + + let b__0 := m in + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then TV_Direct + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then TV_Vector + else TV_Reserved. + +Definition ExtStatus_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 3)} +: ExtStatus := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Off + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Initial + else if sumbool_of_bool ((Z.eqb p0_ 2)) then Clean + else Dirty. + +Definition num_of_ExtStatus (arg_ : ExtStatus) +: {e : Z & ArithFact (0 <= e /\ e <= 3)} := + + build_ex(match arg_ with | Off => 0 | Initial => 1 | Clean => 2 | Dirty => 3 end). + +Definition extStatus_to_bits (e : ExtStatus) +: mword 2 := + + match e with + | Off => (vec_of_bits [B0;B0] : mword 2) + | Initial => (vec_of_bits [B0;B1] : mword 2) + | Clean => (vec_of_bits [B1;B0] : mword 2) + | Dirty => (vec_of_bits [B1;B1] : mword 2) + end. + +Definition extStatus_of_bits (e : mword 2) +: ExtStatus := + + let b__0 := e in + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then Off + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then Initial + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then Clean + else Dirty. + +Definition SATPMode_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: SATPMode := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Sbare + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Sv32 + else Sv39. + +Definition num_of_SATPMode (arg_ : SATPMode) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | Sbare => 0 | Sv32 => 1 | Sv39 => 2 end). + +Definition satpMode_of_bits (a : Architecture) (m : mword 4) +: option SATPMode := + + match (a, m) with + | (g__39, b__0) => + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0] : mword 4))) then Some (Sbare) + else + match (g__39, b__0) with + | (RV32, b__0) => + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1] : mword 4))) then Some (Sv32) + else match (RV32, b__0) with | (g__40, g__41) => None end + | (RV64, b__0) => + if ((eq_vec b__0 (vec_of_bits [B1;B0;B0;B0] : mword 4))) then Some (Sv39) + else match (RV64, b__0) with | (g__40, g__41) => None end + | (g__40, g__41) => None + end + end. + +Definition uop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 1)} +: uop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_LUI + else RISCV_AUIPC. + +Definition num_of_uop (arg_ : uop) +: {e : Z & ArithFact (0 <= e /\ e <= 1)} := + + build_ex(match arg_ with | RISCV_LUI => 0 | RISCV_AUIPC => 1 end). + +Definition bop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 5)} +: bop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_BEQ + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_BNE + else if sumbool_of_bool ((Z.eqb p0_ 2)) then RISCV_BLT + else if sumbool_of_bool ((Z.eqb p0_ 3)) then RISCV_BGE + else if sumbool_of_bool ((Z.eqb p0_ 4)) then RISCV_BLTU + else RISCV_BGEU. + +Definition num_of_bop (arg_ : bop) +: {e : Z & ArithFact (0 <= e /\ e <= 5)} := + + build_ex(match arg_ with + | RISCV_BEQ => 0 + | RISCV_BNE => 1 + | RISCV_BLT => 2 + | RISCV_BGE => 3 + | RISCV_BLTU => 4 + | RISCV_BGEU => 5 + end). + +Definition iop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 5)} +: iop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_ADDI + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SLTI + else if sumbool_of_bool ((Z.eqb p0_ 2)) then RISCV_SLTIU + else if sumbool_of_bool ((Z.eqb p0_ 3)) then RISCV_XORI + else if sumbool_of_bool ((Z.eqb p0_ 4)) then RISCV_ORI + else RISCV_ANDI. + +Definition num_of_iop (arg_ : iop) +: {e : Z & ArithFact (0 <= e /\ e <= 5)} := + + build_ex(match arg_ with + | RISCV_ADDI => 0 + | RISCV_SLTI => 1 + | RISCV_SLTIU => 2 + | RISCV_XORI => 3 + | RISCV_ORI => 4 + | RISCV_ANDI => 5 + end). + +Definition sop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: sop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_SLLI + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SRLI + else RISCV_SRAI. + +Definition num_of_sop (arg_ : sop) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | RISCV_SLLI => 0 | RISCV_SRLI => 1 | RISCV_SRAI => 2 end). + +Definition rop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 9)} +: rop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_ADD + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SUB + else if sumbool_of_bool ((Z.eqb p0_ 2)) then RISCV_SLL + else if sumbool_of_bool ((Z.eqb p0_ 3)) then RISCV_SLT + else if sumbool_of_bool ((Z.eqb p0_ 4)) then RISCV_SLTU + else if sumbool_of_bool ((Z.eqb p0_ 5)) then RISCV_XOR + else if sumbool_of_bool ((Z.eqb p0_ 6)) then RISCV_SRL + else if sumbool_of_bool ((Z.eqb p0_ 7)) then RISCV_SRA + else if sumbool_of_bool ((Z.eqb p0_ 8)) then RISCV_OR + else RISCV_AND. + +Definition num_of_rop (arg_ : rop) +: {e : Z & ArithFact (0 <= e /\ e <= 9)} := + + build_ex(match arg_ with + | RISCV_ADD => 0 + | RISCV_SUB => 1 + | RISCV_SLL => 2 + | RISCV_SLT => 3 + | RISCV_SLTU => 4 + | RISCV_XOR => 5 + | RISCV_SRL => 6 + | RISCV_SRA => 7 + | RISCV_OR => 8 + | RISCV_AND => 9 + end). + +Definition ropw_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 4)} +: ropw := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_ADDW + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SUBW + else if sumbool_of_bool ((Z.eqb p0_ 2)) then RISCV_SLLW + else if sumbool_of_bool ((Z.eqb p0_ 3)) then RISCV_SRLW + else RISCV_SRAW. + +Definition num_of_ropw (arg_ : ropw) +: {e : Z & ArithFact (0 <= e /\ e <= 4)} := + + build_ex(match arg_ with + | RISCV_ADDW => 0 + | RISCV_SUBW => 1 + | RISCV_SLLW => 2 + | RISCV_SRLW => 3 + | RISCV_SRAW => 4 + end). + +Definition sopw_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: sopw := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then RISCV_SLLIW + else if sumbool_of_bool ((Z.eqb p0_ 1)) then RISCV_SRLIW + else RISCV_SRAIW. + +Definition num_of_sopw (arg_ : sopw) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | RISCV_SLLIW => 0 | RISCV_SRLIW => 1 | RISCV_SRAIW => 2 end). + +Definition amoop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 8)} +: amoop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then AMOSWAP + else if sumbool_of_bool ((Z.eqb p0_ 1)) then AMOADD + else if sumbool_of_bool ((Z.eqb p0_ 2)) then AMOXOR + else if sumbool_of_bool ((Z.eqb p0_ 3)) then AMOAND + else if sumbool_of_bool ((Z.eqb p0_ 4)) then AMOOR + else if sumbool_of_bool ((Z.eqb p0_ 5)) then AMOMIN + else if sumbool_of_bool ((Z.eqb p0_ 6)) then AMOMAX + else if sumbool_of_bool ((Z.eqb p0_ 7)) then AMOMINU + else AMOMAXU. + +Definition num_of_amoop (arg_ : amoop) +: {e : Z & ArithFact (0 <= e /\ e <= 8)} := + + build_ex(match arg_ with + | AMOSWAP => 0 + | AMOADD => 1 + | AMOXOR => 2 + | AMOAND => 3 + | AMOOR => 4 + | AMOMIN => 5 + | AMOMAX => 6 + | AMOMINU => 7 + | AMOMAXU => 8 + end). + +Definition csrop_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: csrop := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then CSRRW + else if sumbool_of_bool ((Z.eqb p0_ 1)) then CSRRS + else CSRRC. + +Definition num_of_csrop (arg_ : csrop) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with | CSRRW => 0 | CSRRS => 1 | CSRRC => 2 end). + +Definition reg_name_forwards (arg_ : mword 5) +: string := + + let b__0 := arg_ in + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))))) + then + "zero" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))))) + then + "ra" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))))) + then + "sp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))))) + then + "gp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))))) + then + "tp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : mword 5))))) + then + "t0" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : mword 5))))) + then + "t1" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : mword 5))))) + then + "t2" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))))) + then + "fp" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : mword 5))))) + then + "s1" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : mword 5))))) + then + "a0" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : mword 5))))) + then + "a1" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))))) + then + "a2" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : mword 5))))) + then + "a3" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : mword 5))))) + then + "a4" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : mword 5))))) + then + "a5" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))))) + then + "a6" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : mword 5))))) + then + "a7" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : mword 5))))) + then + "s2" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : mword 5))))) + then + "s3" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))))) + then + "s4" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : mword 5))))) + then + "s5" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : mword 5))))) + then + "s6" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : mword 5))))) + then + "s7" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))))) + then + "s8" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : mword 5))))) + then + "s9" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : mword 5))))) + then + "s10" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : mword 5))))) + then + "s11" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))))) + then + "t3" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))))) + then + "t4" + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : mword 5))))) + then + "t5" + else "t6". + +Definition reg_name_backwards (arg_ : string) +: mword 5 := + + let p0_ := arg_ in + if ((generic_eq p0_ "zero")) then (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + else if ((generic_eq p0_ "ra")) then (vec_of_bits [B0;B0;B0;B0;B1] : mword 5) + else if ((generic_eq p0_ "sp")) then (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) + else if ((generic_eq p0_ "gp")) then (vec_of_bits [B0;B0;B0;B1;B1] : mword 5) + else if ((generic_eq p0_ "tp")) then (vec_of_bits [B0;B0;B1;B0;B0] : mword 5) + else if ((generic_eq p0_ "t0")) then (vec_of_bits [B0;B0;B1;B0;B1] : mword 5) + else if ((generic_eq p0_ "t1")) then (vec_of_bits [B0;B0;B1;B1;B0] : mword 5) + else if ((generic_eq p0_ "t2")) then (vec_of_bits [B0;B0;B1;B1;B1] : mword 5) + else if ((generic_eq p0_ "fp")) then (vec_of_bits [B0;B1;B0;B0;B0] : mword 5) + else if ((generic_eq p0_ "s1")) then (vec_of_bits [B0;B1;B0;B0;B1] : mword 5) + else if ((generic_eq p0_ "a0")) then (vec_of_bits [B0;B1;B0;B1;B0] : mword 5) + else if ((generic_eq p0_ "a1")) then (vec_of_bits [B0;B1;B0;B1;B1] : mword 5) + else if ((generic_eq p0_ "a2")) then (vec_of_bits [B0;B1;B1;B0;B0] : mword 5) + else if ((generic_eq p0_ "a3")) then (vec_of_bits [B0;B1;B1;B0;B1] : mword 5) + else if ((generic_eq p0_ "a4")) then (vec_of_bits [B0;B1;B1;B1;B0] : mword 5) + else if ((generic_eq p0_ "a5")) then (vec_of_bits [B0;B1;B1;B1;B1] : mword 5) + else if ((generic_eq p0_ "a6")) then (vec_of_bits [B1;B0;B0;B0;B0] : mword 5) + else if ((generic_eq p0_ "a7")) then (vec_of_bits [B1;B0;B0;B0;B1] : mword 5) + else if ((generic_eq p0_ "s2")) then (vec_of_bits [B1;B0;B0;B1;B0] : mword 5) + else if ((generic_eq p0_ "s3")) then (vec_of_bits [B1;B0;B0;B1;B1] : mword 5) + else if ((generic_eq p0_ "s4")) then (vec_of_bits [B1;B0;B1;B0;B0] : mword 5) + else if ((generic_eq p0_ "s5")) then (vec_of_bits [B1;B0;B1;B0;B1] : mword 5) + else if ((generic_eq p0_ "s6")) then (vec_of_bits [B1;B0;B1;B1;B0] : mword 5) + else if ((generic_eq p0_ "s7")) then (vec_of_bits [B1;B0;B1;B1;B1] : mword 5) + else if ((generic_eq p0_ "s8")) then (vec_of_bits [B1;B1;B0;B0;B0] : mword 5) + else if ((generic_eq p0_ "s9")) then (vec_of_bits [B1;B1;B0;B0;B1] : mword 5) + else if ((generic_eq p0_ "s10")) then (vec_of_bits [B1;B1;B0;B1;B0] : mword 5) + else if ((generic_eq p0_ "s11")) then (vec_of_bits [B1;B1;B0;B1;B1] : mword 5) + else if ((generic_eq p0_ "t3")) then (vec_of_bits [B1;B1;B1;B0;B0] : mword 5) + else if ((generic_eq p0_ "t4")) then (vec_of_bits [B1;B1;B1;B0;B1] : mword 5) + else if ((generic_eq p0_ "t5")) then (vec_of_bits [B1;B1;B1;B1;B0] : mword 5) + else (vec_of_bits [B1;B1;B1;B1;B1] : mword 5). + +Definition reg_name_forwards_matches (arg_ : mword 5) +: bool := + + let b__0 := arg_ in + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B1] : mword 5))))) + then + true + else false. + +Definition reg_name_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "zero")) then true + else if ((generic_eq p0_ "ra")) then true + else if ((generic_eq p0_ "sp")) then true + else if ((generic_eq p0_ "gp")) then true + else if ((generic_eq p0_ "tp")) then true + else if ((generic_eq p0_ "t0")) then true + else if ((generic_eq p0_ "t1")) then true + else if ((generic_eq p0_ "t2")) then true + else if ((generic_eq p0_ "fp")) then true + else if ((generic_eq p0_ "s1")) then true + else if ((generic_eq p0_ "a0")) then true + else if ((generic_eq p0_ "a1")) then true + else if ((generic_eq p0_ "a2")) then true + else if ((generic_eq p0_ "a3")) then true + else if ((generic_eq p0_ "a4")) then true + else if ((generic_eq p0_ "a5")) then true + else if ((generic_eq p0_ "a6")) then true + else if ((generic_eq p0_ "a7")) then true + else if ((generic_eq p0_ "s2")) then true + else if ((generic_eq p0_ "s3")) then true + else if ((generic_eq p0_ "s4")) then true + else if ((generic_eq p0_ "s5")) then true + else if ((generic_eq p0_ "s6")) then true + else if ((generic_eq p0_ "s7")) then true + else if ((generic_eq p0_ "s8")) then true + else if ((generic_eq p0_ "s9")) then true + else if ((generic_eq p0_ "s10")) then true + else if ((generic_eq p0_ "s11")) then true + else if ((generic_eq p0_ "t3")) then true + else if ((generic_eq p0_ "t4")) then true + else if ((generic_eq p0_ "t5")) then true + else if ((generic_eq p0_ "t6")) then true + else false. + +Definition _s124_ (_s125_ : string) +: option string := + + let _s126_ := _s125_ in + if ((string_startswith _s126_ "t6")) then + match (string_drop _s126_ (projT1 (string_length "t6"))) with | s_ => Some (s_) end + else None. + +Definition _s120_ (_s121_ : string) +: option string := + + let _s122_ := _s121_ in + if ((string_startswith _s122_ "t5")) then + match (string_drop _s122_ (projT1 (string_length "t5"))) with | s_ => Some (s_) end + else None. + +Definition _s116_ (_s117_ : string) +: option string := + + let _s118_ := _s117_ in + if ((string_startswith _s118_ "t4")) then + match (string_drop _s118_ (projT1 (string_length "t4"))) with | s_ => Some (s_) end + else None. + +Definition _s112_ (_s113_ : string) +: option string := + + let _s114_ := _s113_ in + if ((string_startswith _s114_ "t3")) then + match (string_drop _s114_ (projT1 (string_length "t3"))) with | s_ => Some (s_) end + else None. + +Definition _s108_ (_s109_ : string) +: option string := + + let _s110_ := _s109_ in + if ((string_startswith _s110_ "s11")) then + match (string_drop _s110_ (projT1 (string_length "s11"))) with | s_ => Some (s_) end + else None. + +Definition _s104_ (_s105_ : string) +: option string := + + let _s106_ := _s105_ in + if ((string_startswith _s106_ "s10")) then + match (string_drop _s106_ (projT1 (string_length "s10"))) with | s_ => Some (s_) end + else None. + +Definition _s100_ (_s101_ : string) +: option string := + + let _s102_ := _s101_ in + if ((string_startswith _s102_ "s9")) then + match (string_drop _s102_ (projT1 (string_length "s9"))) with | s_ => Some (s_) end + else None. + +Definition _s96_ (_s97_ : string) +: option string := + + let _s98_ := _s97_ in + if ((string_startswith _s98_ "s8")) then + match (string_drop _s98_ (projT1 (string_length "s8"))) with | s_ => Some (s_) end + else None. + +Definition _s92_ (_s93_ : string) +: option string := + + let _s94_ := _s93_ in + if ((string_startswith _s94_ "s7")) then + match (string_drop _s94_ (projT1 (string_length "s7"))) with | s_ => Some (s_) end + else None. + +Definition _s88_ (_s89_ : string) +: option string := + + let _s90_ := _s89_ in + if ((string_startswith _s90_ "s6")) then + match (string_drop _s90_ (projT1 (string_length "s6"))) with | s_ => Some (s_) end + else None. + +Definition _s84_ (_s85_ : string) +: option string := + + let _s86_ := _s85_ in + if ((string_startswith _s86_ "s5")) then + match (string_drop _s86_ (projT1 (string_length "s5"))) with | s_ => Some (s_) end + else None. + +Definition _s80_ (_s81_ : string) +: option string := + + let _s82_ := _s81_ in + if ((string_startswith _s82_ "s4")) then + match (string_drop _s82_ (projT1 (string_length "s4"))) with | s_ => Some (s_) end + else None. + +Definition _s76_ (_s77_ : string) +: option string := + + let _s78_ := _s77_ in + if ((string_startswith _s78_ "s3")) then + match (string_drop _s78_ (projT1 (string_length "s3"))) with | s_ => Some (s_) end + else None. + +Definition _s72_ (_s73_ : string) +: option string := + + let _s74_ := _s73_ in + if ((string_startswith _s74_ "s2")) then + match (string_drop _s74_ (projT1 (string_length "s2"))) with | s_ => Some (s_) end + else None. + +Definition _s68_ (_s69_ : string) +: option string := + + let _s70_ := _s69_ in + if ((string_startswith _s70_ "a7")) then + match (string_drop _s70_ (projT1 (string_length "a7"))) with | s_ => Some (s_) end + else None. + +Definition _s64_ (_s65_ : string) +: option string := + + let _s66_ := _s65_ in + if ((string_startswith _s66_ "a6")) then + match (string_drop _s66_ (projT1 (string_length "a6"))) with | s_ => Some (s_) end + else None. + +Definition _s60_ (_s61_ : string) +: option string := + + let _s62_ := _s61_ in + if ((string_startswith _s62_ "a5")) then + match (string_drop _s62_ (projT1 (string_length "a5"))) with | s_ => Some (s_) end + else None. + +Definition _s56_ (_s57_ : string) +: option string := + + let _s58_ := _s57_ in + if ((string_startswith _s58_ "a4")) then + match (string_drop _s58_ (projT1 (string_length "a4"))) with | s_ => Some (s_) end + else None. + +Definition _s52_ (_s53_ : string) +: option string := + + let _s54_ := _s53_ in + if ((string_startswith _s54_ "a3")) then + match (string_drop _s54_ (projT1 (string_length "a3"))) with | s_ => Some (s_) end + else None. + +Definition _s48_ (_s49_ : string) +: option string := + + let _s50_ := _s49_ in + if ((string_startswith _s50_ "a2")) then + match (string_drop _s50_ (projT1 (string_length "a2"))) with | s_ => Some (s_) end + else None. + +Definition _s44_ (_s45_ : string) +: option string := + + let _s46_ := _s45_ in + if ((string_startswith _s46_ "a1")) then + match (string_drop _s46_ (projT1 (string_length "a1"))) with | s_ => Some (s_) end + else None. + +Definition _s40_ (_s41_ : string) +: option string := + + let _s42_ := _s41_ in + if ((string_startswith _s42_ "a0")) then + match (string_drop _s42_ (projT1 (string_length "a0"))) with | s_ => Some (s_) end + else None. + +Definition _s36_ (_s37_ : string) +: option string := + + let _s38_ := _s37_ in + if ((string_startswith _s38_ "s1")) then + match (string_drop _s38_ (projT1 (string_length "s1"))) with | s_ => Some (s_) end + else None. + +Definition _s32_ (_s33_ : string) +: option string := + + let _s34_ := _s33_ in + if ((string_startswith _s34_ "fp")) then + match (string_drop _s34_ (projT1 (string_length "fp"))) with | s_ => Some (s_) end + else None. + +Definition _s28_ (_s29_ : string) +: option string := + + let _s30_ := _s29_ in + if ((string_startswith _s30_ "t2")) then + match (string_drop _s30_ (projT1 (string_length "t2"))) with | s_ => Some (s_) end + else None. + +Definition _s24_ (_s25_ : string) +: option string := + + let _s26_ := _s25_ in + if ((string_startswith _s26_ "t1")) then + match (string_drop _s26_ (projT1 (string_length "t1"))) with | s_ => Some (s_) end + else None. + +Definition _s20_ (_s21_ : string) +: option string := + + let _s22_ := _s21_ in + if ((string_startswith _s22_ "t0")) then + match (string_drop _s22_ (projT1 (string_length "t0"))) with | s_ => Some (s_) end + else None. + +Definition _s16_ (_s17_ : string) +: option string := + + let _s18_ := _s17_ in + if ((string_startswith _s18_ "tp")) then + match (string_drop _s18_ (projT1 (string_length "tp"))) with | s_ => Some (s_) end + else None. + +Definition _s12_ (_s13_ : string) +: option string := + + let _s14_ := _s13_ in + if ((string_startswith _s14_ "gp")) then + match (string_drop _s14_ (projT1 (string_length "gp"))) with | s_ => Some (s_) end + else None. + +Definition _s8_ (_s9_ : string) +: option string := + + let _s10_ := _s9_ in + if ((string_startswith _s10_ "sp")) then + match (string_drop _s10_ (projT1 (string_length "sp"))) with | s_ => Some (s_) end + else None. + +Definition _s4_ (_s5_ : string) +: option string := + + let _s6_ := _s5_ in + if ((string_startswith _s6_ "ra")) then + match (string_drop _s6_ (projT1 (string_length "ra"))) with | s_ => Some (s_) end + else None. + +Definition _s0_ (_s1_ : string) +: option string := + + let _s2_ := _s1_ in + if ((string_startswith _s2_ "zero")) then + match (string_drop _s2_ (projT1 (string_length "zero"))) with | s_ => Some (s_) end + else None. + +Definition reg_name_matches_prefix (arg_ : string) +: M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) := + + let _s3_ := arg_ in + (if ((match (_s0_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s0_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s4_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s4_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s8_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s8_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s12_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s12_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s16_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s16_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s20_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s20_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s24_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s24_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s28_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s28_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s32_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s32_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B0;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s36_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s36_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B0;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s40_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s40_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B0;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s44_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s44_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B0;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s48_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s48_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s52_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s52_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s56_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s56_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s60_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s60_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s64_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s64_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B0;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s68_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s68_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B0;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s72_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s72_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B0;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s76_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s76_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B0;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s80_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s80_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s84_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s84_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s88_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s88_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s92_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s92_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s96_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s96_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s100_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s100_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s104_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s104_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s108_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s108_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s112_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s112_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B0;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s116_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s116_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B0;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s120_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s120_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B1;B0] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s124_ _s3_) with | Some (s_) => true | _ => false end)) then + (match (_s124_ _s3_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B1;B1] : mword 5), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 5 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 5 * {n : Z & ArithFact (n >= 0)}))). + +Definition creg_name_forwards (arg_ : mword 3) +: string := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then "s0" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then "s1" + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then "a0" + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then "a1" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then "a2" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then "a3" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then "a4" + else "a5". + +Definition creg_name_backwards (arg_ : string) +: mword 3 := + + let p0_ := arg_ in + if ((generic_eq p0_ "s0")) then (vec_of_bits [B0;B0;B0] : mword 3) + else if ((generic_eq p0_ "s1")) then (vec_of_bits [B0;B0;B1] : mword 3) + else if ((generic_eq p0_ "a0")) then (vec_of_bits [B0;B1;B0] : mword 3) + else if ((generic_eq p0_ "a1")) then (vec_of_bits [B0;B1;B1] : mword 3) + else if ((generic_eq p0_ "a2")) then (vec_of_bits [B1;B0;B0] : mword 3) + else if ((generic_eq p0_ "a3")) then (vec_of_bits [B1;B0;B1] : mword 3) + else if ((generic_eq p0_ "a4")) then (vec_of_bits [B1;B1;B0] : mword 3) + else (vec_of_bits [B1;B1;B1] : mword 3). + +Definition creg_name_forwards_matches (arg_ : mword 3) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true + else false. + +Definition creg_name_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "s0")) then true + else if ((generic_eq p0_ "s1")) then true + else if ((generic_eq p0_ "a0")) then true + else if ((generic_eq p0_ "a1")) then true + else if ((generic_eq p0_ "a2")) then true + else if ((generic_eq p0_ "a3")) then true + else if ((generic_eq p0_ "a4")) then true + else if ((generic_eq p0_ "a5")) then true + else false. + +Definition _s156_ (_s157_ : string) +: option string := + + let _s158_ := _s157_ in + if ((string_startswith _s158_ "a5")) then + match (string_drop _s158_ (projT1 (string_length "a5"))) with | s_ => Some (s_) end + else None. + +Definition _s152_ (_s153_ : string) +: option string := + + let _s154_ := _s153_ in + if ((string_startswith _s154_ "a4")) then + match (string_drop _s154_ (projT1 (string_length "a4"))) with | s_ => Some (s_) end + else None. + +Definition _s148_ (_s149_ : string) +: option string := + + let _s150_ := _s149_ in + if ((string_startswith _s150_ "a3")) then + match (string_drop _s150_ (projT1 (string_length "a3"))) with | s_ => Some (s_) end + else None. + +Definition _s144_ (_s145_ : string) +: option string := + + let _s146_ := _s145_ in + if ((string_startswith _s146_ "a2")) then + match (string_drop _s146_ (projT1 (string_length "a2"))) with | s_ => Some (s_) end + else None. + +Definition _s140_ (_s141_ : string) +: option string := + + let _s142_ := _s141_ in + if ((string_startswith _s142_ "a1")) then + match (string_drop _s142_ (projT1 (string_length "a1"))) with | s_ => Some (s_) end + else None. + +Definition _s136_ (_s137_ : string) +: option string := + + let _s138_ := _s137_ in + if ((string_startswith _s138_ "a0")) then + match (string_drop _s138_ (projT1 (string_length "a0"))) with | s_ => Some (s_) end + else None. + +Definition _s132_ (_s133_ : string) +: option string := + + let _s134_ := _s133_ in + if ((string_startswith _s134_ "s1")) then + match (string_drop _s134_ (projT1 (string_length "s1"))) with | s_ => Some (s_) end + else None. + +Definition _s128_ (_s129_ : string) +: option string := + + let _s130_ := _s129_ in + if ((string_startswith _s130_ "s0")) then + match (string_drop _s130_ (projT1 (string_length "s0"))) with | s_ => Some (s_) end + else None. + +Definition creg_name_matches_prefix (arg_ : string) +: M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) := + + let _s131_ := arg_ in + (if ((match (_s128_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s128_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s132_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s132_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s136_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s136_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B0] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s140_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s140_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s144_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s144_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B0] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s148_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s148_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s152_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s152_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s156_ _s131_) with | Some (s_) => true | _ => false end)) then + (match (_s156_ _s131_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1] : mword 3), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 3 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 3 * {n : Z & ArithFact (n >= 0)}))). + +Definition sep_forwards (arg_ : unit) +: string := + + match arg_ with + | tt => + string_append (opt_spc_forwards tt) + (string_append "," (string_append (def_spc_forwards tt) "")) + end. + +Definition _s160_ (_s161_ : string) +: M (option unit) := + + (match _s161_ with + | _s162_ => + (opt_spc_matches_prefix _s162_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s163_ _)) => + let _s164_ := string_drop _s162_ _s163_ in + (if ((string_startswith _s164_ ",")) then + (match (string_drop _s164_ (projT1 (string_length ","))) with + | _s165_ => + (def_spc_matches_prefix _s165_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (tt,(existT _ _s166_ _)) => + let p0_ := string_drop _s165_ _s166_ in + if ((generic_eq p0_ "")) then Some (tt) + else None + | _ => None + end) + : option unit) + end) + : M (option unit) + else returnm (None : option unit)) + : M (option unit) + | _ => returnm (None : option unit) + end) + : M (option unit) + end) + : M (option unit). + +Definition sep_backwards (arg_ : string) +: M (unit) := + + let _s167_ := arg_ in + (_s160_ _s167_) >>= fun w__0 : option unit => + (match w__0 with | Some (tt) => returnm (tt : unit) | _ => exit tt : M (unit) end) + : M (unit). + +Definition sep_forwards_matches (arg_ : unit) : bool := match arg_ with | tt => true end. + +Definition _s168_ (_s169_ : string) +: M (option unit) := + + (match _s169_ with + | _s170_ => + (opt_spc_matches_prefix _s170_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s171_ _)) => + let _s172_ := string_drop _s170_ _s171_ in + (if ((string_startswith _s172_ ",")) then + (match (string_drop _s172_ (projT1 (string_length ","))) with + | _s173_ => + (def_spc_matches_prefix _s173_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (tt,(existT _ _s174_ _)) => + let p0_ := string_drop _s173_ _s174_ in + if ((generic_eq p0_ "")) then Some (tt) + else None + | _ => None + end) + : option unit) + end) + : M (option unit) + else returnm (None : option unit)) + : M (option unit) + | _ => returnm (None : option unit) + end) + : M (option unit) + end) + : M (option unit). + +Definition sep_backwards_matches (arg_ : string) +: M (bool) := + + let _s175_ := arg_ in + (_s168_ _s175_) >>= fun w__0 : option unit => + (if ((match w__0 with | Some (tt) => true | _ => false end)) then + (_s168_ _s175_) >>= fun w__1 : option unit => + (match w__1 with | Some (tt) => returnm (true : bool) | _ => exit tt : M (bool) end) + : M (bool) + else returnm (false : bool)) + : M (bool). + +Definition _s176_ (_s177_ : string) +: M (option string) := + + (match _s177_ with + | _s178_ => + (opt_spc_matches_prefix _s178_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s179_ _)) => + let _s180_ := string_drop _s178_ _s179_ in + (if ((string_startswith _s180_ ",")) then + (match (string_drop _s180_ (projT1 (string_length ","))) with + | _s181_ => + (def_spc_matches_prefix _s181_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (tt,(existT _ _s182_ _)) => + match (string_drop _s181_ _s182_) with | s_ => Some (s_) end + | _ => None + end) + : option string) + end) + : M (option string) + else returnm (None : option string)) + : M (option string) + | _ => returnm (None : option string) + end) + : M (option string) + end) + : M (option string). + +Definition sep_matches_prefix (arg_ : string) +: M (option ((unit * {n : Z & ArithFact (n >= 0)}))) := + + let _s183_ := arg_ in + (_s176_ _s183_) >>= fun w__0 : option string => + (if ((match w__0 with | Some (s_) => true | _ => false end)) then + (_s176_ _s183_) >>= fun w__1 : option string => + (match w__1 with + | Some (s_) => + returnm ((Some + ((tt, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((unit * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((unit * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((unit * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((unit * {n : Z & ArithFact (n >= 0)})))) + : M (option ((unit * {n : Z & ArithFact (n >= 0)}))). + +Definition bool_bits_forwards (arg_ : bool) +: mword 1 := + + match arg_ with + | true => (vec_of_bits [B1] : mword 1) + | false => (vec_of_bits [B0] : mword 1) + end. + +Definition bool_bits_backwards (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else false. + +Definition bool_bits_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | true => true | false => true end. + +Definition bool_bits_backwards_matches (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else false. + +Definition bool_not_bits_forwards (arg_ : bool) +: mword 1 := + + match arg_ with + | true => (vec_of_bits [B0] : mword 1) + | false => (vec_of_bits [B1] : mword 1) + end. + +Definition bool_not_bits_backwards (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else false. + +Definition bool_not_bits_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | true => true | false => true end. + +Definition bool_not_bits_backwards_matches (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else false. + +Definition size_bits_forwards (arg_ : word_width) +: mword 2 := + + match arg_ with + | BYTE => (vec_of_bits [B0;B0] : mword 2) + | HALF => (vec_of_bits [B0;B1] : mword 2) + | WORD => (vec_of_bits [B1;B0] : mword 2) + | DOUBLE => (vec_of_bits [B1;B1] : mword 2) + end. + +Definition size_bits_backwards (arg_ : mword 2) +: word_width := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then BYTE + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then HALF + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then WORD + else DOUBLE. + +Definition size_bits_forwards_matches (arg_ : word_width) +: bool := + + match arg_ with | BYTE => true | HALF => true | WORD => true | DOUBLE => true end. + +Definition size_bits_backwards_matches (arg_ : mword 2) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0] : mword 2))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then true + else false. + +Definition size_mnemonic_forwards (arg_ : word_width) +: string := + + match arg_ with | BYTE => "b" | HALF => "h" | WORD => "w" | DOUBLE => "d" end. + +Definition size_mnemonic_backwards (arg_ : string) +: word_width := + + let p0_ := arg_ in + if ((generic_eq p0_ "b")) then BYTE + else if ((generic_eq p0_ "h")) then HALF + else if ((generic_eq p0_ "w")) then WORD + else DOUBLE. + +Definition size_mnemonic_forwards_matches (arg_ : word_width) +: bool := + + match arg_ with | BYTE => true | HALF => true | WORD => true | DOUBLE => true end. + +Definition size_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "b")) then true + else if ((generic_eq p0_ "h")) then true + else if ((generic_eq p0_ "w")) then true + else if ((generic_eq p0_ "d")) then true + else false. + +Definition _s196_ (_s197_ : string) +: option string := + + let _s198_ := _s197_ in + if ((string_startswith _s198_ "d")) then + match (string_drop _s198_ (projT1 (string_length "d"))) with | s_ => Some (s_) end + else None. + +Definition _s192_ (_s193_ : string) +: option string := + + let _s194_ := _s193_ in + if ((string_startswith _s194_ "w")) then + match (string_drop _s194_ (projT1 (string_length "w"))) with | s_ => Some (s_) end + else None. + +Definition _s188_ (_s189_ : string) +: option string := + + let _s190_ := _s189_ in + if ((string_startswith _s190_ "h")) then + match (string_drop _s190_ (projT1 (string_length "h"))) with | s_ => Some (s_) end + else None. + +Definition _s184_ (_s185_ : string) +: option string := + + let _s186_ := _s185_ in + if ((string_startswith _s186_ "b")) then + match (string_drop _s186_ (projT1 (string_length "b"))) with | s_ => Some (s_) end + else None. + +Definition size_mnemonic_matches_prefix (arg_ : string) +: M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) := + + let _s187_ := arg_ in + (if ((match (_s184_ _s187_) with | Some (s_) => true | _ => false end)) then + (match (_s184_ _s187_) with + | Some (s_) => + returnm ((Some + ((BYTE, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((word_width * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s188_ _s187_) with | Some (s_) => true | _ => false end)) then + (match (_s188_ _s187_) with + | Some (s_) => + returnm ((Some + ((HALF, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((word_width * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s192_ _s187_) with | Some (s_) => true | _ => false end)) then + (match (_s192_ _s187_) with + | Some (s_) => + returnm ((Some + ((WORD, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((word_width * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s196_ _s187_) with | Some (s_) => true | _ => false end)) then + (match (_s196_ _s187_) with + | Some (s_) => + returnm ((Some + ((DOUBLE, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((word_width * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((word_width * {n : Z & ArithFact (n >= 0)})))) + : M (option ((word_width * {n : Z & ArithFact (n >= 0)}))). + +Definition Mk_Misa (v : mword 64) : Misa := {| Misa_Misa_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Misa_bits (v : Misa) : mword 64 := subrange_vec_dec v.(Misa_Misa_chunk_0) 63 0. + +Definition _set_Misa_bits (r_ref : register_ref regstate register_value Misa) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_bits (v : Misa) (x : mword 64) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Misa_MXL (v : Misa) : mword 2 := subrange_vec_dec v.(Misa_Misa_chunk_0) 63 62. + +Definition _set_Misa_MXL (r_ref : register_ref regstate register_value Misa) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 63 62 (subrange_vec_dec v 1 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_MXL (v : Misa) (x : mword 2) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 63 62 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Misa_Z (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 25 25. + +Definition _set_Misa_Z (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 25 25 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_Z (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 25 25 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_Y (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 24 24. + +Definition _set_Misa_Y (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 24 24 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_Y (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 24 24 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_X (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 23 23. + +Definition _set_Misa_X (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 23 23 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_X (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 23 23 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_W (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 22 22. + +Definition _set_Misa_W (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_W (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_V (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 21 21. + +Definition _set_Misa_V (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 21 21 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_V (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 21 21 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_U (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 20 20. + +Definition _set_Misa_U (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 20 20 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_U (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 20 20 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_T (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 19 19. + +Definition _set_Misa_T (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_T (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_S (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 18 18. + +Definition _set_Misa_S (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_S (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_R (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 17 17. + +Definition _set_Misa_R (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 17 17 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_R (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 17 17 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_Q (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 16 16. + +Definition _set_Misa_Q (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 16 16 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_Q (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 16 16 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_P (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 15 15. + +Definition _set_Misa_P (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 15 15 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_P (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 15 15 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_O (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 14 14. + +Definition _set_Misa_O (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 14 14 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_O (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 14 14 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_N (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 13 13. + +Definition _set_Misa_N (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 13 13 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_N (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 13 13 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_M (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 12 12. + +Definition _set_Misa_M (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 12 12 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_M (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 12 12 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_L (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 11 11. + +Definition _set_Misa_L (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 11 11 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_L (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 11 11 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_K (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 10 10. + +Definition _set_Misa_K (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 10 10 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_K (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 10 10 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_J (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 9 9. + +Definition _set_Misa_J (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_J (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_I (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 8 8. + +Definition _set_Misa_I (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_I (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_H (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 7 7. + +Definition _set_Misa_H (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_H (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_G (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 6 6. + +Definition _set_Misa_G (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_G (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_F (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 5 5. + +Definition _set_Misa_F (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_F (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_E (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 4 4. + +Definition _set_Misa_E (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_E (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_D (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 3 3. + +Definition _set_Misa_D (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_D (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_C (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 2 2. + +Definition _set_Misa_C (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_C (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_B (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 1 1. + +Definition _set_Misa_B (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_B (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Misa_A (v : Misa) : mword 1 := subrange_vec_dec v.(Misa_Misa_chunk_0) 0 0. + +Definition _set_Misa_A (r_ref : register_ref regstate register_value Misa) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec r.(Misa_Misa_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Misa in + write_reg r_ref r + : M (unit). + +Definition _update_Misa_A (v : Misa) (x : mword 1) +: Misa := + + {[ v with + Misa_Misa_chunk_0 := + (update_subrange_vec_dec v.(Misa_Misa_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition legalize_misa (m : Misa) (v : mword 64) +: M (Misa) := + + let v := Mk_Misa v in + (and_boolM (returnm ((eq_vec (_get_Misa_C v) ((bool_to_bits false) : mword 1)) : bool)) + (((read_reg nextPC_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + (bit_to_bool (access_vec_dec w__0 1)) >>= fun w__1 : bool => + returnm ((Bool.eqb (w__1 : bool) true) + : bool))) >>= fun w__2 : bool => + returnm ((if (w__2) then m + else _update_Misa_C m (_get_Misa_C v)) + : Misa). + +Definition Mk_Mstatus (v : mword 64) +: Mstatus := + + {| Mstatus_Mstatus_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Mstatus_bits (v : Mstatus) +: mword 64 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 0. + +Definition _set_Mstatus_bits (r_ref : register_ref regstate register_value Mstatus) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_bits (v : Mstatus) (x : mword 64) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Mstatus_SD (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 63. + +Definition _set_Mstatus_SD (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_SD (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_SXL (v : Mstatus) +: mword 2 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 35 34. + +Definition _set_Mstatus_SXL (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 35 34 (subrange_vec_dec v 1 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_SXL (v : Mstatus) (x : mword 2) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 35 34 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Mstatus_UXL (v : Mstatus) +: mword 2 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 33 32. + +Definition _set_Mstatus_UXL (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 33 32 (subrange_vec_dec v 1 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_UXL (v : Mstatus) (x : mword 2) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 33 32 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Mstatus_TSR (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 22 22. + +Definition _set_Mstatus_TSR (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 22 22 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_TSR (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 22 22 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_TW (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 21 21. + +Definition _set_Mstatus_TW (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 21 21 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_TW (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 21 21 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_TVM (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 20 20. + +Definition _set_Mstatus_TVM (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 20 20 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_TVM (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 20 20 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_MXR (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 19 19. + +Definition _set_Mstatus_MXR (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_MXR (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_SUM (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 18 18. + +Definition _set_Mstatus_SUM (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_SUM (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_MPRV (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 17 17. + +Definition _set_Mstatus_MPRV (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 17 17 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_MPRV (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 17 17 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_XS (v : Mstatus) +: mword 2 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 16 15. + +Definition _set_Mstatus_XS (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 16 15 (subrange_vec_dec v 1 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_XS (v : Mstatus) (x : mword 2) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 16 15 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Mstatus_FS (v : Mstatus) +: mword 2 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 14 13. + +Definition _set_Mstatus_FS (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 14 13 (subrange_vec_dec v 1 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_FS (v : Mstatus) (x : mword 2) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 14 13 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Mstatus_MPP (v : Mstatus) +: mword 2 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 12 11. + +Definition _set_Mstatus_MPP (r_ref : register_ref regstate register_value Mstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 12 11 (subrange_vec_dec v 1 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_MPP (v : Mstatus) (x : mword 2) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 12 11 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Mstatus_SPP (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 8 8. + +Definition _set_Mstatus_SPP (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_SPP (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_MPIE (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 7 7. + +Definition _set_Mstatus_MPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_MPIE (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_SPIE (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 5 5. + +Definition _set_Mstatus_SPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_SPIE (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_UPIE (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 4 4. + +Definition _set_Mstatus_UPIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_UPIE (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_MIE (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 3 3. + +Definition _set_Mstatus_MIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_MIE (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_SIE (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 1 1. + +Definition _set_Mstatus_SIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_SIE (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mstatus_UIE (v : Mstatus) +: mword 1 := + + subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 0 0. + +Definition _set_Mstatus_UIE (r_ref : register_ref regstate register_value Mstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec r.(Mstatus_Mstatus_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Mstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Mstatus_UIE (v : Mstatus) (x : mword 1) +: Mstatus := + + {[ v with + Mstatus_Mstatus_chunk_0 := + (update_subrange_vec_dec v.(Mstatus_Mstatus_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition legalize_mstatus (o : Mstatus) (v : mword 64) +: Mstatus := + + let m : Mstatus := Mk_Mstatus v in + let m := _update_Mstatus_XS m (extStatus_to_bits Off) in + let m := _update_Mstatus_FS m (extStatus_to_bits Off) in + let m := + _update_Mstatus_SD m + ((bool_to_bits + (orb + (eq_vec (extStatus_to_bits (extStatus_of_bits (_get_Mstatus_FS m))) + ((extStatus_to_bits Dirty) + : mword 2)) + (eq_vec (extStatus_to_bits (extStatus_of_bits (_get_Mstatus_XS m))) + ((extStatus_to_bits Dirty) + : mword 2)))) + : mword 1) in + let m := _update_Mstatus_SXL m (_get_Mstatus_SXL o) in + let m := _update_Mstatus_UXL m (_get_Mstatus_UXL o) in + let m := _update_Mstatus_UPIE m ((bool_to_bits false) : mword 1) in + _update_Mstatus_UIE m ((bool_to_bits false) : mword 1). + +Definition cur_Architecture '(tt : unit) +: M (Architecture) := + + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + (match w__0 with + | Machine => read_reg misa_ref >>= fun w__1 : Misa => returnm ((_get_Misa_MXL w__1) : mword 2) + | Supervisor => + read_reg mstatus_ref >>= fun w__2 : Mstatus => returnm ((_get_Mstatus_SXL w__2) : mword 2) + | User => + read_reg mstatus_ref >>= fun w__3 : Mstatus => returnm ((_get_Mstatus_UXL w__3) : mword 2) + end) >>= fun a : arch_xlen => + (match (architecture a) with + | Some (a) => returnm (a : Architecture) + | None => (internal_error "Invalid current architecture") : M (Architecture) + end) + : M (Architecture). + +Definition in32BitMode '(tt : unit) +: M (bool) := + + (cur_Architecture tt) >>= fun w__0 : Architecture => returnm ((generic_eq w__0 RV32) : bool). + +Definition haveAtomics '(tt : unit) +: M (bool) := + + read_reg misa_ref >>= fun w__0 : Misa => + returnm ((eq_vec (_get_Misa_A w__0) ((bool_to_bits true) : mword 1)) + : bool). + +Definition haveRVC '(tt : unit) +: M (bool) := + + read_reg misa_ref >>= fun w__0 : Misa => + returnm ((eq_vec (_get_Misa_C w__0) ((bool_to_bits true) : mword 1)) + : bool). + +Definition haveMulDiv '(tt : unit) +: M (bool) := + + read_reg misa_ref >>= fun w__0 : Misa => + returnm ((eq_vec (_get_Misa_M w__0) ((bool_to_bits true) : mword 1)) + : bool). + +Definition haveFP '(tt : unit) +: M (bool) := + + (or_boolM + (read_reg misa_ref >>= fun w__0 : Misa => + returnm ((eq_vec (_get_Misa_F w__0) ((bool_to_bits true) : mword 1)) + : bool)) + (read_reg misa_ref >>= fun w__1 : Misa => + returnm ((eq_vec (_get_Misa_D w__1) ((bool_to_bits true) : mword 1)) + : bool))) + : M (bool). + +Definition Mk_Minterrupts (v : mword 64) +: Minterrupts := + + {| Minterrupts_Minterrupts_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Minterrupts_bits (v : Minterrupts) +: mword 64 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 63 0. + +Definition _set_Minterrupts_bits +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_bits (v : Minterrupts) (x : mword 64) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Minterrupts_MEI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 11 11. + +Definition _set_Minterrupts_MEI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 11 11 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_MEI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 11 11 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_SEI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 9 9. + +Definition _set_Minterrupts_SEI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_SEI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_UEI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 8 8. + +Definition _set_Minterrupts_UEI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_UEI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_MTI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 7 7. + +Definition _set_Minterrupts_MTI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_MTI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_STI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 5 5. + +Definition _set_Minterrupts_STI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_STI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_UTI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 4 4. + +Definition _set_Minterrupts_UTI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_UTI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_MSI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 3 3. + +Definition _set_Minterrupts_MSI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_MSI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_SSI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 1 1. + +Definition _set_Minterrupts_SSI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_SSI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Minterrupts_USI (v : Minterrupts) +: mword 1 := + + subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 0 0. + +Definition _set_Minterrupts_USI +(r_ref : register_ref regstate register_value Minterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec r.(Minterrupts_Minterrupts_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Minterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Minterrupts_USI (v : Minterrupts) (x : mword 1) +: Minterrupts := + + {[ v with + Minterrupts_Minterrupts_chunk_0 := + (update_subrange_vec_dec v.(Minterrupts_Minterrupts_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition legalize_mip (o : Minterrupts) (v : mword 64) +: Minterrupts := + + let v := Mk_Minterrupts v in + let m := _update_Minterrupts_SEI o (_get_Minterrupts_SEI v) in + let m := _update_Minterrupts_STI m (_get_Minterrupts_STI v) in + _update_Minterrupts_SSI m (_get_Minterrupts_SSI v). + +Definition legalize_mie (o : Minterrupts) (v : mword 64) +: Minterrupts := + + let v := Mk_Minterrupts v in + let m := _update_Minterrupts_MEI o (_get_Minterrupts_MEI v) in + let m := _update_Minterrupts_MTI m (_get_Minterrupts_MTI v) in + let m := _update_Minterrupts_MSI m (_get_Minterrupts_MSI v) in + let m := _update_Minterrupts_SEI m (_get_Minterrupts_SEI v) in + let m := _update_Minterrupts_STI m (_get_Minterrupts_STI v) in + _update_Minterrupts_SSI m (_get_Minterrupts_SSI v). + +Definition legalize_mideleg (o : Minterrupts) (v : mword 64) +: Minterrupts := + + let m := Mk_Minterrupts v in + let m := _update_Minterrupts_MEI m ((bool_to_bits false) : mword 1) in + let m := _update_Minterrupts_MTI m ((bool_to_bits false) : mword 1) in + _update_Minterrupts_MSI m ((bool_to_bits false) : mword 1). + +Definition Mk_Medeleg (v : mword 64) +: Medeleg := + + {| Medeleg_Medeleg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Medeleg_bits (v : Medeleg) +: mword 64 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 63 0. + +Definition _set_Medeleg_bits (r_ref : register_ref regstate register_value Medeleg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_bits (v : Medeleg) (x : mword 64) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Medeleg_SAMO_Page_Fault (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 15 15. + +Definition _set_Medeleg_SAMO_Page_Fault +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 15 15 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_SAMO_Page_Fault (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 15 15 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Load_Page_Fault (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 13 13. + +Definition _set_Medeleg_Load_Page_Fault +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 13 13 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Load_Page_Fault (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 13 13 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Fetch_Page_Fault (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 12 12. + +Definition _set_Medeleg_Fetch_Page_Fault +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 12 12 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Fetch_Page_Fault (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 12 12 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_MEnvCall (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 10 10. + +Definition _set_Medeleg_MEnvCall +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 10 10 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_MEnvCall (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 10 10 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_SEnvCall (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 9 9. + +Definition _set_Medeleg_SEnvCall +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_SEnvCall (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_UEnvCall (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 8 8. + +Definition _set_Medeleg_UEnvCall +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_UEnvCall (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_SAMO_Access_Fault (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 7 7. + +Definition _set_Medeleg_SAMO_Access_Fault +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_SAMO_Access_Fault (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_SAMO_Addr_Align (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 6 6. + +Definition _set_Medeleg_SAMO_Addr_Align +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_SAMO_Addr_Align (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Load_Access_Fault (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 5 5. + +Definition _set_Medeleg_Load_Access_Fault +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Load_Access_Fault (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Load_Addr_Align (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 4 4. + +Definition _set_Medeleg_Load_Addr_Align +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Load_Addr_Align (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Breakpoint (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 3 3. + +Definition _set_Medeleg_Breakpoint +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Breakpoint (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Illegal_Instr (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 2 2. + +Definition _set_Medeleg_Illegal_Instr +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Illegal_Instr (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Fetch_Access_Fault (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 1 1. + +Definition _set_Medeleg_Fetch_Access_Fault +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Fetch_Access_Fault (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Medeleg_Fetch_Addr_Align (v : Medeleg) +: mword 1 := + + subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 0 0. + +Definition _set_Medeleg_Fetch_Addr_Align +(r_ref : register_ref regstate register_value Medeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec r.(Medeleg_Medeleg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Medeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Medeleg_Fetch_Addr_Align (v : Medeleg) (x : mword 1) +: Medeleg := + + {[ v with + Medeleg_Medeleg_chunk_0 := + (update_subrange_vec_dec v.(Medeleg_Medeleg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition legalize_medeleg (o : Medeleg) (v : mword 64) +: Medeleg := + + let m := Mk_Medeleg v in + _update_Medeleg_MEnvCall m ((bool_to_bits false) : mword 1). + +Definition Mk_Mtvec (v : mword 64) +: Mtvec := + + {| Mtvec_Mtvec_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Mtvec_bits (v : Mtvec) +: mword 64 := + + subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 0. + +Definition _set_Mtvec_bits (r_ref : register_ref regstate register_value Mtvec) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mtvec_Mtvec_chunk_0 := + (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Mtvec in + write_reg r_ref r + : M (unit). + +Definition _update_Mtvec_bits (v : Mtvec) (x : mword 64) +: Mtvec := + + {[ v with + Mtvec_Mtvec_chunk_0 := + (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Mtvec_Base (v : Mtvec) +: mword 62 := + + subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 2. + +Definition _set_Mtvec_Base (r_ref : register_ref regstate register_value Mtvec) (v : mword 62) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mtvec_Mtvec_chunk_0 := + (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 63 2 (subrange_vec_dec v 61 0)) ]} + : Mtvec in + write_reg r_ref r + : M (unit). + +Definition _update_Mtvec_Base (v : Mtvec) (x : mword 62) +: Mtvec := + + {[ v with + Mtvec_Mtvec_chunk_0 := + (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 63 2 (subrange_vec_dec x 61 0)) ]}. + +Definition _get_Mtvec_Mode (v : Mtvec) : mword 2 := subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 1 0. + +Definition _set_Mtvec_Mode (r_ref : register_ref regstate register_value Mtvec) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mtvec_Mtvec_chunk_0 := + (update_subrange_vec_dec r.(Mtvec_Mtvec_chunk_0) 1 0 (subrange_vec_dec v 1 0)) ]} + : Mtvec in + write_reg r_ref r + : M (unit). + +Definition _update_Mtvec_Mode (v : Mtvec) (x : mword 2) +: Mtvec := + + {[ v with + Mtvec_Mtvec_chunk_0 := + (update_subrange_vec_dec v.(Mtvec_Mtvec_chunk_0) 1 0 (subrange_vec_dec x 1 0)) ]}. + +Definition legalize_tvec (o : Mtvec) (v : mword 64) +: Mtvec := + + let v := Mk_Mtvec v in + match (trapVectorMode_of_bits (_get_Mtvec_Mode v)) with + | TV_Direct => v + | TV_Vector => v + | _ => _update_Mtvec_Mode v (_get_Mtvec_Mode o) + end. + +Definition Mk_Mcause (v : mword 64) +: Mcause := + + {| Mcause_Mcause_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Mcause_bits (v : Mcause) +: mword 64 := + + subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 0. + +Definition _set_Mcause_bits (r_ref : register_ref regstate register_value Mcause) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mcause_Mcause_chunk_0 := + (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Mcause in + write_reg r_ref r + : M (unit). + +Definition _update_Mcause_bits (v : Mcause) (x : mword 64) +: Mcause := + + {[ v with + Mcause_Mcause_chunk_0 := + (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Mcause_IsInterrupt (v : Mcause) +: mword 1 := + + subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 63. + +Definition _set_Mcause_IsInterrupt +(r_ref : register_ref regstate register_value Mcause) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mcause_Mcause_chunk_0 := + (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} + : Mcause in + write_reg r_ref r + : M (unit). + +Definition _update_Mcause_IsInterrupt (v : Mcause) (x : mword 1) +: Mcause := + + {[ v with + Mcause_Mcause_chunk_0 := + (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Mcause_Cause (v : Mcause) +: mword 63 := + + subrange_vec_dec v.(Mcause_Mcause_chunk_0) 62 0. + +Definition _set_Mcause_Cause (r_ref : register_ref regstate register_value Mcause) (v : mword 63) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Mcause_Mcause_chunk_0 := + (update_subrange_vec_dec r.(Mcause_Mcause_chunk_0) 62 0 (subrange_vec_dec v 62 0)) ]} + : Mcause in + write_reg r_ref r + : M (unit). + +Definition _update_Mcause_Cause (v : Mcause) (x : mword 63) +: Mcause := + + {[ v with + Mcause_Mcause_chunk_0 := + (update_subrange_vec_dec v.(Mcause_Mcause_chunk_0) 62 0 (subrange_vec_dec x 62 0)) ]}. + +Definition tvec_addr (m : Mtvec) (c : Mcause) +: option (mword 64) := + + let base : xlenbits := concat_vec (_get_Mtvec_Base m) (vec_of_bits [B0;B0] : mword 2) in + match (trapVectorMode_of_bits (_get_Mtvec_Mode m)) with + | TV_Direct => Some (base) + | TV_Vector => + if ((eq_vec (_get_Mcause_IsInterrupt c) ((bool_to_bits true) : mword 1))) then + Some + (add_vec base + (shift_bits_left (EXTZ 64 (_get_Mcause_Cause c)) (vec_of_bits [B1;B0] : mword 2))) + else Some (base) + | TV_Reserved => None + end. + +Definition legalize_xepc (v : mword 64) +: M (mword 64) := + + (haveRVC tt) >>= fun w__0 : bool => + returnm ((and_vec v + (EXTS 64 + (if (w__0) then (vec_of_bits [B1;B1;B0] : mword 3) + else (vec_of_bits [B1;B0;B0] : mword 3)))) + : mword 64). + +Definition pc_alignment_mask '(tt : unit) +: M (mword 64) := + + read_reg misa_ref >>= fun w__0 : Misa => + returnm ((not_vec + (EXTZ 64 + (if ((eq_vec (_get_Misa_C w__0) ((bool_to_bits true) : mword 1))) then + (vec_of_bits [B0;B0] : mword 2) + else (vec_of_bits [B1;B0] : mword 2)))) + : mword 64). + +Definition Mk_Counteren (v : mword 32) +: Counteren := + + {| Counteren_Counteren_chunk_0 := (subrange_vec_dec v 31 0) |}. + +Definition _get_Counteren_bits (v : Counteren) +: mword 32 := + + subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 0. + +Definition _set_Counteren_bits +(r_ref : register_ref regstate register_value Counteren) (v : mword 32) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 31 0 (subrange_vec_dec v 31 0)) ]} + : Counteren in + write_reg r_ref r + : M (unit). + +Definition _update_Counteren_bits (v : Counteren) (x : mword 32) +: Counteren := + + {[ v with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 0 (subrange_vec_dec x 31 0)) ]}. + +Definition _get_Counteren_HPM (v : Counteren) +: mword 29 := + + subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 3. + +Definition _set_Counteren_HPM +(r_ref : register_ref regstate register_value Counteren) (v : mword 29) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 31 3 (subrange_vec_dec v 28 0)) ]} + : Counteren in + write_reg r_ref r + : M (unit). + +Definition _update_Counteren_HPM (v : Counteren) (x : mword 29) +: Counteren := + + {[ v with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 31 3 (subrange_vec_dec x 28 0)) ]}. + +Definition _get_Counteren_IR (v : Counteren) +: mword 1 := + + subrange_vec_dec v.(Counteren_Counteren_chunk_0) 2 2. + +Definition _set_Counteren_IR (r_ref : register_ref regstate register_value Counteren) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : Counteren in + write_reg r_ref r + : M (unit). + +Definition _update_Counteren_IR (v : Counteren) (x : mword 1) +: Counteren := + + {[ v with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Counteren_TM (v : Counteren) +: mword 1 := + + subrange_vec_dec v.(Counteren_Counteren_chunk_0) 1 1. + +Definition _set_Counteren_TM (r_ref : register_ref regstate register_value Counteren) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Counteren in + write_reg r_ref r + : M (unit). + +Definition _update_Counteren_TM (v : Counteren) (x : mword 1) +: Counteren := + + {[ v with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Counteren_CY (v : Counteren) +: mword 1 := + + subrange_vec_dec v.(Counteren_Counteren_chunk_0) 0 0. + +Definition _set_Counteren_CY (r_ref : register_ref regstate register_value Counteren) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec r.(Counteren_Counteren_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Counteren in + write_reg r_ref r + : M (unit). + +Definition _update_Counteren_CY (v : Counteren) (x : mword 1) +: Counteren := + + {[ v with + Counteren_Counteren_chunk_0 := + (update_subrange_vec_dec v.(Counteren_Counteren_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition legalize_mcounteren (c : Counteren) (v : mword 64) +: M (Counteren) := + + (cast_unit_vec (access_vec_dec v 2)) >>= fun w__0 : mword 1 => + let c := _update_Counteren_IR c (w__0 : mword 1) in + (cast_unit_vec (access_vec_dec v 1)) >>= fun w__1 : mword 1 => + let c := _update_Counteren_TM c (w__1 : mword 1) in + (cast_unit_vec (access_vec_dec v 0)) >>= fun w__2 : mword 1 => + let c := _update_Counteren_CY c (w__2 : mword 1) in + returnm (c + : Counteren). + +Definition legalize_scounteren (c : Counteren) (v : mword 64) +: M (Counteren) := + + (cast_unit_vec (access_vec_dec v 2)) >>= fun w__0 : mword 1 => + let c := _update_Counteren_IR c (w__0 : mword 1) in + (cast_unit_vec (access_vec_dec v 1)) >>= fun w__1 : mword 1 => + let c := _update_Counteren_TM c (w__1 : mword 1) in + (cast_unit_vec (access_vec_dec v 0)) >>= fun w__2 : mword 1 => + let c := _update_Counteren_CY c (w__2 : mword 1) in + returnm (c + : Counteren). + +Definition retire_instruction '(tt : unit) +: M (unit) := + + read_reg minstret_written_ref >>= fun w__0 : bool => + (if ((Bool.eqb w__0 true)) then write_reg minstret_written_ref false : M (unit) + else + ((read_reg minstret_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + write_reg minstret_ref (add_vec_int w__1 1) + : M (unit)) + : M (unit). + +Definition Mk_Sstatus (v : mword 64) +: Sstatus := + + {| Sstatus_Sstatus_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Sstatus_bits (v : Sstatus) +: mword 64 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 0. + +Definition _set_Sstatus_bits (r_ref : register_ref regstate register_value Sstatus) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_bits (v : Sstatus) (x : mword 64) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Sstatus_SD (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 63. + +Definition _set_Sstatus_SD (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 63 63 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_SD (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 63 63 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_UXL (v : Sstatus) +: mword 2 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 33 32. + +Definition _set_Sstatus_UXL (r_ref : register_ref regstate register_value Sstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 33 32 (subrange_vec_dec v 1 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_UXL (v : Sstatus) (x : mword 2) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 33 32 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Sstatus_MXR (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 19 19. + +Definition _set_Sstatus_MXR (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 19 19 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_MXR (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 19 19 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_SUM (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 18 18. + +Definition _set_Sstatus_SUM (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 18 18 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_SUM (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 18 18 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_XS (v : Sstatus) +: mword 2 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 16 15. + +Definition _set_Sstatus_XS (r_ref : register_ref regstate register_value Sstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 16 15 (subrange_vec_dec v 1 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_XS (v : Sstatus) (x : mword 2) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 16 15 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Sstatus_FS (v : Sstatus) +: mword 2 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 14 13. + +Definition _set_Sstatus_FS (r_ref : register_ref regstate register_value Sstatus) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 14 13 (subrange_vec_dec v 1 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_FS (v : Sstatus) (x : mword 2) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 14 13 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_Sstatus_SPP (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 8 8. + +Definition _set_Sstatus_SPP (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_SPP (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_SPIE (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 5 5. + +Definition _set_Sstatus_SPIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_SPIE (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_UPIE (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 4 4. + +Definition _set_Sstatus_UPIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_UPIE (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_SIE (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 1 1. + +Definition _set_Sstatus_SIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_SIE (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sstatus_UIE (v : Sstatus) +: mword 1 := + + subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 0 0. + +Definition _set_Sstatus_UIE (r_ref : register_ref regstate register_value Sstatus) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec r.(Sstatus_Sstatus_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Sstatus in + write_reg r_ref r + : M (unit). + +Definition _update_Sstatus_UIE (v : Sstatus) (x : mword 1) +: Sstatus := + + {[ v with + Sstatus_Sstatus_chunk_0 := + (update_subrange_vec_dec v.(Sstatus_Sstatus_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition lower_mstatus (m : Mstatus) +: Sstatus := + + let s := Mk_Sstatus (EXTZ 64 (vec_of_bits [B0] : mword 1)) in + let s := _update_Sstatus_SD s (_get_Mstatus_SD m) in + let s := _update_Sstatus_UXL s (_get_Mstatus_UXL m) in + let s := _update_Sstatus_MXR s (_get_Mstatus_MXR m) in + let s := _update_Sstatus_SUM s (_get_Mstatus_SUM m) in + let s := _update_Sstatus_XS s (_get_Mstatus_XS m) in + let s := _update_Sstatus_FS s (_get_Mstatus_FS m) in + let s := _update_Sstatus_SPP s (_get_Mstatus_SPP m) in + let s := _update_Sstatus_SPIE s (_get_Mstatus_SPIE m) in + let s := _update_Sstatus_UPIE s (_get_Mstatus_UPIE m) in + let s := _update_Sstatus_SIE s (_get_Mstatus_SIE m) in + _update_Sstatus_UIE s (_get_Mstatus_UIE m). + +Definition lift_sstatus (m : Mstatus) (s : Sstatus) +: Mstatus := + + let m := _update_Mstatus_MXR m (_get_Sstatus_MXR s) in + let m := _update_Mstatus_SUM m (_get_Sstatus_SUM s) in + let m := _update_Mstatus_XS m (_get_Sstatus_XS s) in + let m := _update_Mstatus_FS m (_get_Sstatus_FS s) in + let m := + _update_Mstatus_SD m + ((bool_to_bits + (orb + (eq_vec (extStatus_to_bits (extStatus_of_bits (_get_Mstatus_FS m))) + ((extStatus_to_bits Dirty) + : mword 2)) + (eq_vec (extStatus_to_bits (extStatus_of_bits (_get_Mstatus_XS m))) + ((extStatus_to_bits Dirty) + : mword 2)))) + : mword 1) in + let m := _update_Mstatus_SPP m (_get_Sstatus_SPP s) in + let m := _update_Mstatus_SPIE m (_get_Sstatus_SPIE s) in + let m := _update_Mstatus_UPIE m (_get_Sstatus_UPIE s) in + let m := _update_Mstatus_SIE m (_get_Sstatus_SIE s) in + _update_Mstatus_UIE m (_get_Sstatus_UIE s). + +Definition legalize_sstatus (m : Mstatus) (v : mword 64) +: Mstatus := + + lift_sstatus m (Mk_Sstatus v). + +Definition Mk_Sedeleg (v : mword 64) +: Sedeleg := + + {| Sedeleg_Sedeleg_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Sedeleg_bits (v : Sedeleg) +: mword 64 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 63 0. + +Definition _set_Sedeleg_bits (r_ref : register_ref regstate register_value Sedeleg) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_bits (v : Sedeleg) (x : mword 64) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Sedeleg_UEnvCall (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 8 8. + +Definition _set_Sedeleg_UEnvCall +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_UEnvCall (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_SAMO_Access_Fault (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 7 7. + +Definition _set_Sedeleg_SAMO_Access_Fault +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_SAMO_Access_Fault (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_SAMO_Addr_Align (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 6 6. + +Definition _set_Sedeleg_SAMO_Addr_Align +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_SAMO_Addr_Align (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_Load_Access_Fault (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 5 5. + +Definition _set_Sedeleg_Load_Access_Fault +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_Load_Access_Fault (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_Load_Addr_Align (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 4 4. + +Definition _set_Sedeleg_Load_Addr_Align +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_Load_Addr_Align (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_Breakpoint (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 3 3. + +Definition _set_Sedeleg_Breakpoint +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_Breakpoint (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_Illegal_Instr (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 2 2. + +Definition _set_Sedeleg_Illegal_Instr +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_Illegal_Instr (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_Fetch_Access_Fault (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 1 1. + +Definition _set_Sedeleg_Fetch_Access_Fault +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_Fetch_Access_Fault (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sedeleg_Fetch_Addr_Align (v : Sedeleg) +: mword 1 := + + subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 0 0. + +Definition _set_Sedeleg_Fetch_Addr_Align +(r_ref : register_ref regstate register_value Sedeleg) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec r.(Sedeleg_Sedeleg_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Sedeleg in + write_reg r_ref r + : M (unit). + +Definition _update_Sedeleg_Fetch_Addr_Align (v : Sedeleg) (x : mword 1) +: Sedeleg := + + {[ v with + Sedeleg_Sedeleg_chunk_0 := + (update_subrange_vec_dec v.(Sedeleg_Sedeleg_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition legalize_sedeleg (s : Sedeleg) (v : mword 64) +: Sedeleg := + + Mk_Sedeleg (EXTZ 64 (subrange_vec_dec v 8 0)). + +Definition Mk_Sinterrupts (v : mword 64) +: Sinterrupts := + + {| Sinterrupts_Sinterrupts_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Sinterrupts_bits (v : Sinterrupts) +: mword 64 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 63 0. + +Definition _set_Sinterrupts_bits +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_bits (v : Sinterrupts) (x : mword 64) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Sinterrupts_SEI (v : Sinterrupts) +: mword 1 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 9 9. + +Definition _set_Sinterrupts_SEI +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 9 9 (subrange_vec_dec v 0 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_SEI (v : Sinterrupts) (x : mword 1) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 9 9 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sinterrupts_UEI (v : Sinterrupts) +: mword 1 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 8 8. + +Definition _set_Sinterrupts_UEI +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 8 8 (subrange_vec_dec v 0 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_UEI (v : Sinterrupts) (x : mword 1) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 8 8 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sinterrupts_STI (v : Sinterrupts) +: mword 1 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 5 5. + +Definition _set_Sinterrupts_STI +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_STI (v : Sinterrupts) (x : mword 1) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sinterrupts_UTI (v : Sinterrupts) +: mword 1 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 4 4. + +Definition _set_Sinterrupts_UTI +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_UTI (v : Sinterrupts) (x : mword 1) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sinterrupts_SSI (v : Sinterrupts) +: mword 1 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 1 1. + +Definition _set_Sinterrupts_SSI +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_SSI (v : Sinterrupts) (x : mword 1) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_Sinterrupts_USI (v : Sinterrupts) +: mword 1 := + + subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 0 0. + +Definition _set_Sinterrupts_USI +(r_ref : register_ref regstate register_value Sinterrupts) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec r.(Sinterrupts_Sinterrupts_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : Sinterrupts in + write_reg r_ref r + : M (unit). + +Definition _update_Sinterrupts_USI (v : Sinterrupts) (x : mword 1) +: Sinterrupts := + + {[ v with + Sinterrupts_Sinterrupts_chunk_0 := + (update_subrange_vec_dec v.(Sinterrupts_Sinterrupts_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition lower_mip (m : Minterrupts) (d : Minterrupts) +: Sinterrupts := + + let s : Sinterrupts := Mk_Sinterrupts (EXTZ 64 (vec_of_bits [B0] : mword 1)) in + let s := _update_Sinterrupts_SEI s (and_vec (_get_Minterrupts_SEI m) (_get_Minterrupts_SEI d)) in + let s := _update_Sinterrupts_STI s (and_vec (_get_Minterrupts_STI m) (_get_Minterrupts_STI d)) in + let s := _update_Sinterrupts_SSI s (and_vec (_get_Minterrupts_SSI m) (_get_Minterrupts_SSI d)) in + let s := _update_Sinterrupts_UEI s (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in + let s := _update_Sinterrupts_UTI s (and_vec (_get_Minterrupts_UTI m) (_get_Minterrupts_UTI d)) in + _update_Sinterrupts_USI s (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)). + +Definition lower_mie (m : Minterrupts) (d : Minterrupts) +: Sinterrupts := + + let s : Sinterrupts := Mk_Sinterrupts (EXTZ 64 (vec_of_bits [B0] : mword 1)) in + let s := _update_Sinterrupts_SEI s (and_vec (_get_Minterrupts_SEI m) (_get_Minterrupts_SEI d)) in + let s := _update_Sinterrupts_STI s (and_vec (_get_Minterrupts_STI m) (_get_Minterrupts_STI d)) in + let s := _update_Sinterrupts_SSI s (and_vec (_get_Minterrupts_SSI m) (_get_Minterrupts_SSI d)) in + let s := _update_Sinterrupts_UEI s (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in + let s := _update_Sinterrupts_UTI s (and_vec (_get_Minterrupts_UTI m) (_get_Minterrupts_UTI d)) in + _update_Sinterrupts_USI s (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)). + +Definition lift_sip (o : Minterrupts) (d : Minterrupts) (s : Sinterrupts) +: Minterrupts := + + let m : Minterrupts := o in + let m := _update_Minterrupts_SSI m (and_vec (_get_Sinterrupts_SSI s) (_get_Minterrupts_SSI d)) in + let m := _update_Minterrupts_UEI m (and_vec (_get_Minterrupts_UEI m) (_get_Minterrupts_UEI d)) in + _update_Minterrupts_USI m (and_vec (_get_Minterrupts_USI m) (_get_Minterrupts_USI d)). + +Definition legalize_sip (m : Minterrupts) (d : Minterrupts) (v : mword 64) +: Minterrupts := + + lift_sip m d (Mk_Sinterrupts v). + +Definition lift_sie (o : Minterrupts) (d : Minterrupts) (s : Sinterrupts) +: Minterrupts := + + let m : Minterrupts := o in + let m := + if ((eq_vec (_get_Minterrupts_SEI d) ((bool_to_bits true) : mword 1))) then + _update_Minterrupts_SEI m (_get_Sinterrupts_SEI s) + else m in + let m := + if ((eq_vec (_get_Minterrupts_STI d) ((bool_to_bits true) : mword 1))) then + _update_Minterrupts_STI m (_get_Sinterrupts_STI s) + else m in + let m := + if ((eq_vec (_get_Minterrupts_SSI d) ((bool_to_bits true) : mword 1))) then + _update_Minterrupts_SSI m (_get_Sinterrupts_SSI s) + else m in + let m := + if ((eq_vec (_get_Minterrupts_UEI d) ((bool_to_bits true) : mword 1))) then + _update_Minterrupts_UEI m (_get_Sinterrupts_UEI s) + else m in + let m := + if ((eq_vec (_get_Minterrupts_UTI d) ((bool_to_bits true) : mword 1))) then + _update_Minterrupts_UTI m (_get_Sinterrupts_UTI s) + else m in + if ((eq_vec (_get_Minterrupts_USI d) ((bool_to_bits true) : mword 1))) then + _update_Minterrupts_USI m (_get_Sinterrupts_USI s) + else m. + +Definition legalize_sie (m : Minterrupts) (d : Minterrupts) (v : mword 64) +: Minterrupts := + + lift_sie m d (Mk_Sinterrupts v). + +Definition Mk_Satp64 (v : mword 64) +: Satp64 := + + {| Satp64_Satp64_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_Satp64_bits (v : Satp64) +: mword 64 := + + subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 0. + +Definition _set_Satp64_bits (r_ref : register_ref regstate register_value Satp64) (v : mword 64) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : Satp64 in + write_reg r_ref r + : M (unit). + +Definition _update_Satp64_bits (v : Satp64) (x : mword 64) +: Satp64 := + + {[ v with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_Satp64_Mode (v : Satp64) +: mword 4 := + + subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 60. + +Definition _set_Satp64_Mode (r_ref : register_ref regstate register_value Satp64) (v : mword 4) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 63 60 (subrange_vec_dec v 3 0)) ]} + : Satp64 in + write_reg r_ref r + : M (unit). + +Definition _update_Satp64_Mode (v : Satp64) (x : mword 4) +: Satp64 := + + {[ v with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 63 60 (subrange_vec_dec x 3 0)) ]}. + +Definition _get_Satp64_Asid (v : Satp64) +: mword 16 := + + subrange_vec_dec v.(Satp64_Satp64_chunk_0) 59 44. + +Definition _set_Satp64_Asid (r_ref : register_ref regstate register_value Satp64) (v : mword 16) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 59 44 (subrange_vec_dec v 15 0)) ]} + : Satp64 in + write_reg r_ref r + : M (unit). + +Definition _update_Satp64_Asid (v : Satp64) (x : mword 16) +: Satp64 := + + {[ v with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 59 44 (subrange_vec_dec x 15 0)) ]}. + +Definition _get_Satp64_PPN (v : Satp64) +: mword 44 := + + subrange_vec_dec v.(Satp64_Satp64_chunk_0) 43 0. + +Definition _set_Satp64_PPN (r_ref : register_ref regstate register_value Satp64) (v : mword 44) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec r.(Satp64_Satp64_chunk_0) 43 0 (subrange_vec_dec v 43 0)) ]} + : Satp64 in + write_reg r_ref r + : M (unit). + +Definition _update_Satp64_PPN (v : Satp64) (x : mword 44) +: Satp64 := + + {[ v with + Satp64_Satp64_chunk_0 := + (update_subrange_vec_dec v.(Satp64_Satp64_chunk_0) 43 0 (subrange_vec_dec x 43 0)) ]}. + +Definition legalize_satp (a : Architecture) (o : mword 64) (v : mword 64) +: mword 64 := + + let s := Mk_Satp64 v in + match (satpMode_of_bits a (_get_Satp64_Mode s)) with + | None => o + | Some (Sv32) => o + | Some (_) => _get_Satp64_bits s + end. + +Definition csr_name (csr : mword 12) +: string := + + let b__0 := csr in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then "ustatus" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + "uie" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + "utvec" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "fflags" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "frm" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + "fcsr" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "cycle" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "time" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "instret" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "cycleh" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "timeh" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "instreth" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "sstatus" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "sedeleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + "sideleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + "sie" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + "stvec" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + "scounteren" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + "sscratch" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + "sepc" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + "scause" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + "stval" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + "sip" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "satp" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then + "mvendorid" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then + "marchid" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then + "mimpid" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then + "mhartid" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mstatus" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "misa" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "medeleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + "mideleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + "mie" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + "mtvec" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + "mcounteren" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mscratch" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + "mepc" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + "mcause" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + "mtval" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + "mip" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + "pmpcfg0" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then + "pmpaddr0" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mcycle" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "minstret" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mcycleh" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "minstreth" + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + "tselect" + else "UNKNOWN". + +Definition csr_name_map_forwards (arg_ : mword 12) +: string := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then "ustatus" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + "uie" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + "utvec" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + "uscratch" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + "uepc" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + "ucause" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + "utval" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + "uip" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "fflags" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "frm" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + "fcsr" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "cycle" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "time" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "instret" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "cycleh" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "timeh" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "instreth" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "sstatus" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "sedeleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + "sideleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + "sie" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + "stvec" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + "scounteren" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + "sscratch" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + "sepc" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + "scause" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + "stval" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + "sip" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "satp" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then + "mvendorid" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then + "marchid" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then + "mimpid" + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then + "mhartid" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mstatus" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + "misa" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "medeleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + "mideleg" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + "mie" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + "mtvec" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + "mcounteren" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mscratch" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + "mepc" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + "mcause" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + "mtval" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + "mip" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + "pmpcfg0" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then + "pmpcfg1" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then + "pmpcfg2" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then + "pmpcfg3" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then + "pmpaddr0" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then + "pmpaddr1" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then + "pmpaddr2" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then + "pmpaddr3" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then + "pmpaddr4" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then + "pmpaddr5" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then + "pmpaddr6" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then + "pmpaddr7" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then + "pmpaddr8" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then + "pmpaddr9" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then + "pmpaddr10" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then + "pmpaddr11" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then + "pmpaddr12" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then + "pmpaddr13" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then + "pmpaddr14" + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then + "pmpaddr15" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mcycle" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "minstret" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + "mcycleh" + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + "minstreth" + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + "tselect" + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then + "tdata1" + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then + "tdata2" + else "tdata3". + +Definition csr_name_map_backwards (arg_ : string) +: mword 12 := + + let p0_ := arg_ in + if ((generic_eq p0_ "ustatus")) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "uie")) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "utvec")) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12) + else if ((generic_eq p0_ "uscratch")) then + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "uepc")) then + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "ucause")) then + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "utval")) then + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "uip")) then + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "fflags")) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "frm")) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "fcsr")) then + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "cycle")) then + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "time")) then + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "instret")) then + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "cycleh")) then + (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "timeh")) then + (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "instreth")) then + (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "sstatus")) then + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "sedeleg")) then + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "sideleg")) then + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "sie")) then + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "stvec")) then + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12) + else if ((generic_eq p0_ "scounteren")) then + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12) + else if ((generic_eq p0_ "sscratch")) then + (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "sepc")) then + (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "scause")) then + (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "stval")) then + (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "sip")) then + (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "satp")) then + (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "mvendorid")) then + (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "marchid")) then + (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "mimpid")) then + (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "mhartid")) then + (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "mstatus")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "misa")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "medeleg")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "mideleg")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "mie")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "mtvec")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12) + else if ((generic_eq p0_ "mcounteren")) then + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12) + else if ((generic_eq p0_ "mscratch")) then + (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "mepc")) then + (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "mcause")) then + (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "mtval")) then + (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "mip")) then + (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "pmpcfg0")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "pmpcfg1")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "pmpcfg2")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "pmpcfg3")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr0")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr1")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr2")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr3")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr4")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr5")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr6")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr7")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr8")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr9")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr10")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr11")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr12")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr13")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12) + else if ((generic_eq p0_ "pmpaddr14")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12) + else if ((generic_eq p0_ "pmpaddr15")) then + (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12) + else if ((generic_eq p0_ "mcycle")) then + (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "minstret")) then + (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "mcycleh")) then + (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "minstreth")) then + (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12) + else if ((generic_eq p0_ "tselect")) then + (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12) + else if ((generic_eq p0_ "tdata1")) then + (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12) + else if ((generic_eq p0_ "tdata2")) then + (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12) + else (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12). + +Definition csr_name_map_forwards_matches (arg_ : mword 12) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12))) then true + else false. + +Definition csr_name_map_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "ustatus")) then true + else if ((generic_eq p0_ "uie")) then true + else if ((generic_eq p0_ "utvec")) then true + else if ((generic_eq p0_ "uscratch")) then true + else if ((generic_eq p0_ "uepc")) then true + else if ((generic_eq p0_ "ucause")) then true + else if ((generic_eq p0_ "utval")) then true + else if ((generic_eq p0_ "uip")) then true + else if ((generic_eq p0_ "fflags")) then true + else if ((generic_eq p0_ "frm")) then true + else if ((generic_eq p0_ "fcsr")) then true + else if ((generic_eq p0_ "cycle")) then true + else if ((generic_eq p0_ "time")) then true + else if ((generic_eq p0_ "instret")) then true + else if ((generic_eq p0_ "cycleh")) then true + else if ((generic_eq p0_ "timeh")) then true + else if ((generic_eq p0_ "instreth")) then true + else if ((generic_eq p0_ "sstatus")) then true + else if ((generic_eq p0_ "sedeleg")) then true + else if ((generic_eq p0_ "sideleg")) then true + else if ((generic_eq p0_ "sie")) then true + else if ((generic_eq p0_ "stvec")) then true + else if ((generic_eq p0_ "scounteren")) then true + else if ((generic_eq p0_ "sscratch")) then true + else if ((generic_eq p0_ "sepc")) then true + else if ((generic_eq p0_ "scause")) then true + else if ((generic_eq p0_ "stval")) then true + else if ((generic_eq p0_ "sip")) then true + else if ((generic_eq p0_ "satp")) then true + else if ((generic_eq p0_ "mvendorid")) then true + else if ((generic_eq p0_ "marchid")) then true + else if ((generic_eq p0_ "mimpid")) then true + else if ((generic_eq p0_ "mhartid")) then true + else if ((generic_eq p0_ "mstatus")) then true + else if ((generic_eq p0_ "misa")) then true + else if ((generic_eq p0_ "medeleg")) then true + else if ((generic_eq p0_ "mideleg")) then true + else if ((generic_eq p0_ "mie")) then true + else if ((generic_eq p0_ "mtvec")) then true + else if ((generic_eq p0_ "mcounteren")) then true + else if ((generic_eq p0_ "mscratch")) then true + else if ((generic_eq p0_ "mepc")) then true + else if ((generic_eq p0_ "mcause")) then true + else if ((generic_eq p0_ "mtval")) then true + else if ((generic_eq p0_ "mip")) then true + else if ((generic_eq p0_ "pmpcfg0")) then true + else if ((generic_eq p0_ "pmpcfg1")) then true + else if ((generic_eq p0_ "pmpcfg2")) then true + else if ((generic_eq p0_ "pmpcfg3")) then true + else if ((generic_eq p0_ "pmpaddr0")) then true + else if ((generic_eq p0_ "pmpaddr1")) then true + else if ((generic_eq p0_ "pmpaddr2")) then true + else if ((generic_eq p0_ "pmpaddr3")) then true + else if ((generic_eq p0_ "pmpaddr4")) then true + else if ((generic_eq p0_ "pmpaddr5")) then true + else if ((generic_eq p0_ "pmpaddr6")) then true + else if ((generic_eq p0_ "pmpaddr7")) then true + else if ((generic_eq p0_ "pmpaddr8")) then true + else if ((generic_eq p0_ "pmpaddr9")) then true + else if ((generic_eq p0_ "pmpaddr10")) then true + else if ((generic_eq p0_ "pmpaddr11")) then true + else if ((generic_eq p0_ "pmpaddr12")) then true + else if ((generic_eq p0_ "pmpaddr13")) then true + else if ((generic_eq p0_ "pmpaddr14")) then true + else if ((generic_eq p0_ "pmpaddr15")) then true + else if ((generic_eq p0_ "mcycle")) then true + else if ((generic_eq p0_ "minstret")) then true + else if ((generic_eq p0_ "mcycleh")) then true + else if ((generic_eq p0_ "minstreth")) then true + else if ((generic_eq p0_ "tselect")) then true + else if ((generic_eq p0_ "tdata1")) then true + else if ((generic_eq p0_ "tdata2")) then true + else if ((generic_eq p0_ "tdata3")) then true + else false. + +Definition _s488_ (_s489_ : string) +: option string := + + let _s490_ := _s489_ in + if ((string_startswith _s490_ "tdata3")) then + match (string_drop _s490_ (projT1 (string_length "tdata3"))) with | s_ => Some (s_) end + else None. + +Definition _s484_ (_s485_ : string) +: option string := + + let _s486_ := _s485_ in + if ((string_startswith _s486_ "tdata2")) then + match (string_drop _s486_ (projT1 (string_length "tdata2"))) with | s_ => Some (s_) end + else None. + +Definition _s480_ (_s481_ : string) +: option string := + + let _s482_ := _s481_ in + if ((string_startswith _s482_ "tdata1")) then + match (string_drop _s482_ (projT1 (string_length "tdata1"))) with | s_ => Some (s_) end + else None. + +Definition _s476_ (_s477_ : string) +: option string := + + let _s478_ := _s477_ in + if ((string_startswith _s478_ "tselect")) then + match (string_drop _s478_ (projT1 (string_length "tselect"))) with | s_ => Some (s_) end + else None. + +Definition _s472_ (_s473_ : string) +: option string := + + let _s474_ := _s473_ in + if ((string_startswith _s474_ "minstreth")) then + match (string_drop _s474_ (projT1 (string_length "minstreth"))) with | s_ => Some (s_) end + else None. + +Definition _s468_ (_s469_ : string) +: option string := + + let _s470_ := _s469_ in + if ((string_startswith _s470_ "mcycleh")) then + match (string_drop _s470_ (projT1 (string_length "mcycleh"))) with | s_ => Some (s_) end + else None. + +Definition _s464_ (_s465_ : string) +: option string := + + let _s466_ := _s465_ in + if ((string_startswith _s466_ "minstret")) then + match (string_drop _s466_ (projT1 (string_length "minstret"))) with | s_ => Some (s_) end + else None. + +Definition _s460_ (_s461_ : string) +: option string := + + let _s462_ := _s461_ in + if ((string_startswith _s462_ "mcycle")) then + match (string_drop _s462_ (projT1 (string_length "mcycle"))) with | s_ => Some (s_) end + else None. + +Definition _s456_ (_s457_ : string) +: option string := + + let _s458_ := _s457_ in + if ((string_startswith _s458_ "pmpaddr15")) then + match (string_drop _s458_ (projT1 (string_length "pmpaddr15"))) with | s_ => Some (s_) end + else None. + +Definition _s452_ (_s453_ : string) +: option string := + + let _s454_ := _s453_ in + if ((string_startswith _s454_ "pmpaddr14")) then + match (string_drop _s454_ (projT1 (string_length "pmpaddr14"))) with | s_ => Some (s_) end + else None. + +Definition _s448_ (_s449_ : string) +: option string := + + let _s450_ := _s449_ in + if ((string_startswith _s450_ "pmpaddr13")) then + match (string_drop _s450_ (projT1 (string_length "pmpaddr13"))) with | s_ => Some (s_) end + else None. + +Definition _s444_ (_s445_ : string) +: option string := + + let _s446_ := _s445_ in + if ((string_startswith _s446_ "pmpaddr12")) then + match (string_drop _s446_ (projT1 (string_length "pmpaddr12"))) with | s_ => Some (s_) end + else None. + +Definition _s440_ (_s441_ : string) +: option string := + + let _s442_ := _s441_ in + if ((string_startswith _s442_ "pmpaddr11")) then + match (string_drop _s442_ (projT1 (string_length "pmpaddr11"))) with | s_ => Some (s_) end + else None. + +Definition _s436_ (_s437_ : string) +: option string := + + let _s438_ := _s437_ in + if ((string_startswith _s438_ "pmpaddr10")) then + match (string_drop _s438_ (projT1 (string_length "pmpaddr10"))) with | s_ => Some (s_) end + else None. + +Definition _s432_ (_s433_ : string) +: option string := + + let _s434_ := _s433_ in + if ((string_startswith _s434_ "pmpaddr9")) then + match (string_drop _s434_ (projT1 (string_length "pmpaddr9"))) with | s_ => Some (s_) end + else None. + +Definition _s428_ (_s429_ : string) +: option string := + + let _s430_ := _s429_ in + if ((string_startswith _s430_ "pmpaddr8")) then + match (string_drop _s430_ (projT1 (string_length "pmpaddr8"))) with | s_ => Some (s_) end + else None. + +Definition _s424_ (_s425_ : string) +: option string := + + let _s426_ := _s425_ in + if ((string_startswith _s426_ "pmpaddr7")) then + match (string_drop _s426_ (projT1 (string_length "pmpaddr7"))) with | s_ => Some (s_) end + else None. + +Definition _s420_ (_s421_ : string) +: option string := + + let _s422_ := _s421_ in + if ((string_startswith _s422_ "pmpaddr6")) then + match (string_drop _s422_ (projT1 (string_length "pmpaddr6"))) with | s_ => Some (s_) end + else None. + +Definition _s416_ (_s417_ : string) +: option string := + + let _s418_ := _s417_ in + if ((string_startswith _s418_ "pmpaddr5")) then + match (string_drop _s418_ (projT1 (string_length "pmpaddr5"))) with | s_ => Some (s_) end + else None. + +Definition _s412_ (_s413_ : string) +: option string := + + let _s414_ := _s413_ in + if ((string_startswith _s414_ "pmpaddr4")) then + match (string_drop _s414_ (projT1 (string_length "pmpaddr4"))) with | s_ => Some (s_) end + else None. + +Definition _s408_ (_s409_ : string) +: option string := + + let _s410_ := _s409_ in + if ((string_startswith _s410_ "pmpaddr3")) then + match (string_drop _s410_ (projT1 (string_length "pmpaddr3"))) with | s_ => Some (s_) end + else None. + +Definition _s404_ (_s405_ : string) +: option string := + + let _s406_ := _s405_ in + if ((string_startswith _s406_ "pmpaddr2")) then + match (string_drop _s406_ (projT1 (string_length "pmpaddr2"))) with | s_ => Some (s_) end + else None. + +Definition _s400_ (_s401_ : string) +: option string := + + let _s402_ := _s401_ in + if ((string_startswith _s402_ "pmpaddr1")) then + match (string_drop _s402_ (projT1 (string_length "pmpaddr1"))) with | s_ => Some (s_) end + else None. + +Definition _s396_ (_s397_ : string) +: option string := + + let _s398_ := _s397_ in + if ((string_startswith _s398_ "pmpaddr0")) then + match (string_drop _s398_ (projT1 (string_length "pmpaddr0"))) with | s_ => Some (s_) end + else None. + +Definition _s392_ (_s393_ : string) +: option string := + + let _s394_ := _s393_ in + if ((string_startswith _s394_ "pmpcfg3")) then + match (string_drop _s394_ (projT1 (string_length "pmpcfg3"))) with | s_ => Some (s_) end + else None. + +Definition _s388_ (_s389_ : string) +: option string := + + let _s390_ := _s389_ in + if ((string_startswith _s390_ "pmpcfg2")) then + match (string_drop _s390_ (projT1 (string_length "pmpcfg2"))) with | s_ => Some (s_) end + else None. + +Definition _s384_ (_s385_ : string) +: option string := + + let _s386_ := _s385_ in + if ((string_startswith _s386_ "pmpcfg1")) then + match (string_drop _s386_ (projT1 (string_length "pmpcfg1"))) with | s_ => Some (s_) end + else None. + +Definition _s380_ (_s381_ : string) +: option string := + + let _s382_ := _s381_ in + if ((string_startswith _s382_ "pmpcfg0")) then + match (string_drop _s382_ (projT1 (string_length "pmpcfg0"))) with | s_ => Some (s_) end + else None. + +Definition _s376_ (_s377_ : string) +: option string := + + let _s378_ := _s377_ in + if ((string_startswith _s378_ "mip")) then + match (string_drop _s378_ (projT1 (string_length "mip"))) with | s_ => Some (s_) end + else None. + +Definition _s372_ (_s373_ : string) +: option string := + + let _s374_ := _s373_ in + if ((string_startswith _s374_ "mtval")) then + match (string_drop _s374_ (projT1 (string_length "mtval"))) with | s_ => Some (s_) end + else None. + +Definition _s368_ (_s369_ : string) +: option string := + + let _s370_ := _s369_ in + if ((string_startswith _s370_ "mcause")) then + match (string_drop _s370_ (projT1 (string_length "mcause"))) with | s_ => Some (s_) end + else None. + +Definition _s364_ (_s365_ : string) +: option string := + + let _s366_ := _s365_ in + if ((string_startswith _s366_ "mepc")) then + match (string_drop _s366_ (projT1 (string_length "mepc"))) with | s_ => Some (s_) end + else None. + +Definition _s360_ (_s361_ : string) +: option string := + + let _s362_ := _s361_ in + if ((string_startswith _s362_ "mscratch")) then + match (string_drop _s362_ (projT1 (string_length "mscratch"))) with | s_ => Some (s_) end + else None. + +Definition _s356_ (_s357_ : string) +: option string := + + let _s358_ := _s357_ in + if ((string_startswith _s358_ "mcounteren")) then + match (string_drop _s358_ (projT1 (string_length "mcounteren"))) with | s_ => Some (s_) end + else None. + +Definition _s352_ (_s353_ : string) +: option string := + + let _s354_ := _s353_ in + if ((string_startswith _s354_ "mtvec")) then + match (string_drop _s354_ (projT1 (string_length "mtvec"))) with | s_ => Some (s_) end + else None. + +Definition _s348_ (_s349_ : string) +: option string := + + let _s350_ := _s349_ in + if ((string_startswith _s350_ "mie")) then + match (string_drop _s350_ (projT1 (string_length "mie"))) with | s_ => Some (s_) end + else None. + +Definition _s344_ (_s345_ : string) +: option string := + + let _s346_ := _s345_ in + if ((string_startswith _s346_ "mideleg")) then + match (string_drop _s346_ (projT1 (string_length "mideleg"))) with | s_ => Some (s_) end + else None. + +Definition _s340_ (_s341_ : string) +: option string := + + let _s342_ := _s341_ in + if ((string_startswith _s342_ "medeleg")) then + match (string_drop _s342_ (projT1 (string_length "medeleg"))) with | s_ => Some (s_) end + else None. + +Definition _s336_ (_s337_ : string) +: option string := + + let _s338_ := _s337_ in + if ((string_startswith _s338_ "misa")) then + match (string_drop _s338_ (projT1 (string_length "misa"))) with | s_ => Some (s_) end + else None. + +Definition _s332_ (_s333_ : string) +: option string := + + let _s334_ := _s333_ in + if ((string_startswith _s334_ "mstatus")) then + match (string_drop _s334_ (projT1 (string_length "mstatus"))) with | s_ => Some (s_) end + else None. + +Definition _s328_ (_s329_ : string) +: option string := + + let _s330_ := _s329_ in + if ((string_startswith _s330_ "mhartid")) then + match (string_drop _s330_ (projT1 (string_length "mhartid"))) with | s_ => Some (s_) end + else None. + +Definition _s324_ (_s325_ : string) +: option string := + + let _s326_ := _s325_ in + if ((string_startswith _s326_ "mimpid")) then + match (string_drop _s326_ (projT1 (string_length "mimpid"))) with | s_ => Some (s_) end + else None. + +Definition _s320_ (_s321_ : string) +: option string := + + let _s322_ := _s321_ in + if ((string_startswith _s322_ "marchid")) then + match (string_drop _s322_ (projT1 (string_length "marchid"))) with | s_ => Some (s_) end + else None. + +Definition _s316_ (_s317_ : string) +: option string := + + let _s318_ := _s317_ in + if ((string_startswith _s318_ "mvendorid")) then + match (string_drop _s318_ (projT1 (string_length "mvendorid"))) with | s_ => Some (s_) end + else None. + +Definition _s312_ (_s313_ : string) +: option string := + + let _s314_ := _s313_ in + if ((string_startswith _s314_ "satp")) then + match (string_drop _s314_ (projT1 (string_length "satp"))) with | s_ => Some (s_) end + else None. + +Definition _s308_ (_s309_ : string) +: option string := + + let _s310_ := _s309_ in + if ((string_startswith _s310_ "sip")) then + match (string_drop _s310_ (projT1 (string_length "sip"))) with | s_ => Some (s_) end + else None. + +Definition _s304_ (_s305_ : string) +: option string := + + let _s306_ := _s305_ in + if ((string_startswith _s306_ "stval")) then + match (string_drop _s306_ (projT1 (string_length "stval"))) with | s_ => Some (s_) end + else None. + +Definition _s300_ (_s301_ : string) +: option string := + + let _s302_ := _s301_ in + if ((string_startswith _s302_ "scause")) then + match (string_drop _s302_ (projT1 (string_length "scause"))) with | s_ => Some (s_) end + else None. + +Definition _s296_ (_s297_ : string) +: option string := + + let _s298_ := _s297_ in + if ((string_startswith _s298_ "sepc")) then + match (string_drop _s298_ (projT1 (string_length "sepc"))) with | s_ => Some (s_) end + else None. + +Definition _s292_ (_s293_ : string) +: option string := + + let _s294_ := _s293_ in + if ((string_startswith _s294_ "sscratch")) then + match (string_drop _s294_ (projT1 (string_length "sscratch"))) with | s_ => Some (s_) end + else None. + +Definition _s288_ (_s289_ : string) +: option string := + + let _s290_ := _s289_ in + if ((string_startswith _s290_ "scounteren")) then + match (string_drop _s290_ (projT1 (string_length "scounteren"))) with | s_ => Some (s_) end + else None. + +Definition _s284_ (_s285_ : string) +: option string := + + let _s286_ := _s285_ in + if ((string_startswith _s286_ "stvec")) then + match (string_drop _s286_ (projT1 (string_length "stvec"))) with | s_ => Some (s_) end + else None. + +Definition _s280_ (_s281_ : string) +: option string := + + let _s282_ := _s281_ in + if ((string_startswith _s282_ "sie")) then + match (string_drop _s282_ (projT1 (string_length "sie"))) with | s_ => Some (s_) end + else None. + +Definition _s276_ (_s277_ : string) +: option string := + + let _s278_ := _s277_ in + if ((string_startswith _s278_ "sideleg")) then + match (string_drop _s278_ (projT1 (string_length "sideleg"))) with | s_ => Some (s_) end + else None. + +Definition _s272_ (_s273_ : string) +: option string := + + let _s274_ := _s273_ in + if ((string_startswith _s274_ "sedeleg")) then + match (string_drop _s274_ (projT1 (string_length "sedeleg"))) with | s_ => Some (s_) end + else None. + +Definition _s268_ (_s269_ : string) +: option string := + + let _s270_ := _s269_ in + if ((string_startswith _s270_ "sstatus")) then + match (string_drop _s270_ (projT1 (string_length "sstatus"))) with | s_ => Some (s_) end + else None. + +Definition _s264_ (_s265_ : string) +: option string := + + let _s266_ := _s265_ in + if ((string_startswith _s266_ "instreth")) then + match (string_drop _s266_ (projT1 (string_length "instreth"))) with | s_ => Some (s_) end + else None. + +Definition _s260_ (_s261_ : string) +: option string := + + let _s262_ := _s261_ in + if ((string_startswith _s262_ "timeh")) then + match (string_drop _s262_ (projT1 (string_length "timeh"))) with | s_ => Some (s_) end + else None. + +Definition _s256_ (_s257_ : string) +: option string := + + let _s258_ := _s257_ in + if ((string_startswith _s258_ "cycleh")) then + match (string_drop _s258_ (projT1 (string_length "cycleh"))) with | s_ => Some (s_) end + else None. + +Definition _s252_ (_s253_ : string) +: option string := + + let _s254_ := _s253_ in + if ((string_startswith _s254_ "instret")) then + match (string_drop _s254_ (projT1 (string_length "instret"))) with | s_ => Some (s_) end + else None. + +Definition _s248_ (_s249_ : string) +: option string := + + let _s250_ := _s249_ in + if ((string_startswith _s250_ "time")) then + match (string_drop _s250_ (projT1 (string_length "time"))) with | s_ => Some (s_) end + else None. + +Definition _s244_ (_s245_ : string) +: option string := + + let _s246_ := _s245_ in + if ((string_startswith _s246_ "cycle")) then + match (string_drop _s246_ (projT1 (string_length "cycle"))) with | s_ => Some (s_) end + else None. + +Definition _s240_ (_s241_ : string) +: option string := + + let _s242_ := _s241_ in + if ((string_startswith _s242_ "fcsr")) then + match (string_drop _s242_ (projT1 (string_length "fcsr"))) with | s_ => Some (s_) end + else None. + +Definition _s236_ (_s237_ : string) +: option string := + + let _s238_ := _s237_ in + if ((string_startswith _s238_ "frm")) then + match (string_drop _s238_ (projT1 (string_length "frm"))) with | s_ => Some (s_) end + else None. + +Definition _s232_ (_s233_ : string) +: option string := + + let _s234_ := _s233_ in + if ((string_startswith _s234_ "fflags")) then + match (string_drop _s234_ (projT1 (string_length "fflags"))) with | s_ => Some (s_) end + else None. + +Definition _s228_ (_s229_ : string) +: option string := + + let _s230_ := _s229_ in + if ((string_startswith _s230_ "uip")) then + match (string_drop _s230_ (projT1 (string_length "uip"))) with | s_ => Some (s_) end + else None. + +Definition _s224_ (_s225_ : string) +: option string := + + let _s226_ := _s225_ in + if ((string_startswith _s226_ "utval")) then + match (string_drop _s226_ (projT1 (string_length "utval"))) with | s_ => Some (s_) end + else None. + +Definition _s220_ (_s221_ : string) +: option string := + + let _s222_ := _s221_ in + if ((string_startswith _s222_ "ucause")) then + match (string_drop _s222_ (projT1 (string_length "ucause"))) with | s_ => Some (s_) end + else None. + +Definition _s216_ (_s217_ : string) +: option string := + + let _s218_ := _s217_ in + if ((string_startswith _s218_ "uepc")) then + match (string_drop _s218_ (projT1 (string_length "uepc"))) with | s_ => Some (s_) end + else None. + +Definition _s212_ (_s213_ : string) +: option string := + + let _s214_ := _s213_ in + if ((string_startswith _s214_ "uscratch")) then + match (string_drop _s214_ (projT1 (string_length "uscratch"))) with | s_ => Some (s_) end + else None. + +Definition _s208_ (_s209_ : string) +: option string := + + let _s210_ := _s209_ in + if ((string_startswith _s210_ "utvec")) then + match (string_drop _s210_ (projT1 (string_length "utvec"))) with | s_ => Some (s_) end + else None. + +Definition _s204_ (_s205_ : string) +: option string := + + let _s206_ := _s205_ in + if ((string_startswith _s206_ "uie")) then + match (string_drop _s206_ (projT1 (string_length "uie"))) with | s_ => Some (s_) end + else None. + +Definition _s200_ (_s201_ : string) +: option string := + + let _s202_ := _s201_ in + if ((string_startswith _s202_ "ustatus")) then + match (string_drop _s202_ (projT1 (string_length "ustatus"))) with | s_ => Some (s_) end + else None. + +Definition csr_name_map_matches_prefix (arg_ : string) +: M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) := + + let _s203_ := arg_ in + (if ((match (_s200_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s200_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s204_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s204_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s208_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s208_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s212_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s212_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s216_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s216_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s220_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s220_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s224_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s224_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s228_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s228_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s232_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s232_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s236_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s236_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s240_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s240_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s244_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s244_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s248_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s248_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s252_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s252_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s256_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s256_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s260_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s260_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s264_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s264_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s268_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s268_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s272_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s272_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s276_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s276_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s280_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s280_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s284_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s284_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s288_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s288_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s292_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s292_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s296_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s296_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s300_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s300_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s304_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s304_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s308_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s308_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s312_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s312_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s316_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s316_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s320_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s320_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s324_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s324_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s328_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s328_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s332_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s332_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s336_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s336_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s340_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s340_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s344_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s344_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s348_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s348_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s352_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s352_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s356_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s356_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s360_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s360_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s364_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s364_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s368_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s368_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s372_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s372_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s376_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s376_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s380_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s380_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s384_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s384_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s388_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s388_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s392_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s392_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s396_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s396_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s400_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s400_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s404_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s404_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s408_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s408_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s412_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s412_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s416_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s416_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s420_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s420_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s424_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s424_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B1;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s428_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s428_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s432_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s432_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s436_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s436_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s440_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s440_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s444_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s444_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s448_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s448_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s452_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s452_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s456_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s456_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s460_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s460_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s464_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s464_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s468_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s468_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s472_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s472_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s476_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s476_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s480_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s480_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s484_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s484_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B0] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s488_ _s203_) with | Some (s_) => true | _ => false end)) then + (match (_s488_ _s203_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B1;B1] : mword 12), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 12 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 12 * {n : Z & ArithFact (n >= 0)}))). + +Definition csrAccess (csr : mword 12) : mword 2 := subrange_vec_dec csr 11 10. + +Definition csrPriv (csr : mword 12) : mword 2 := subrange_vec_dec csr 9 8. + +Definition is_CSR_defined (csr : mword 12) (p : Privilege) +: bool := + + let b__0 := csr in + if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then + false + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + orb (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2)) + (eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + eq_vec (privLevel_to_bits p) ((privLevel_to_bits Machine) : mword 2) + else false. + +Definition check_CSR_access (csrrw : mword 2) (csrpr : mword 2) (p : Privilege) (isWrite : bool) +: bool := + + andb (negb (andb (Bool.eqb isWrite true) (eq_vec csrrw (vec_of_bits [B1;B1] : mword 2)))) + (zopz0zKzJ_u (privLevel_to_bits p) csrpr). + +Definition check_TVM_SATP (csr : mword 12) (p : Privilege) +: M (bool) := + + (and_boolM + (returnm ((eq_vec csr (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12)) + : bool)) + ((and_boolM + (returnm ((eq_vec (privLevel_to_bits p) ((privLevel_to_bits Supervisor) : mword 2)) + : bool)) + (read_reg mstatus_ref >>= fun w__0 : Mstatus => + returnm ((eq_vec (_get_Mstatus_TVM w__0) ((bool_to_bits true) : mword 1)) + : bool))) + : M (bool))) >>= fun w__2 : bool => + returnm ((negb w__2) + : bool). + +Definition check_Counteren (csr : mword 12) (p : Privilege) +: M (bool) := + + (match (csr, p) with + | (b__0, Supervisor) => + (if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + read_reg mcounteren_ref >>= fun w__0 : Counteren => + returnm ((eq_vec (_get_Counteren_CY w__0) ((bool_to_bits true) : mword 1)) + : bool) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + read_reg mcounteren_ref >>= fun w__1 : Counteren => + returnm ((eq_vec (_get_Counteren_TM w__1) ((bool_to_bits true) : mword 1)) + : bool) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg mcounteren_ref >>= fun w__2 : Counteren => + returnm ((eq_vec (_get_Counteren_IR w__2) ((bool_to_bits true) : mword 1)) + : bool) + else + returnm ((match (b__0, Supervisor) with + | (g__37, g__38) => + if ((andb + (zopz0zIzJ_u + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) csr) + (zopz0zIzJ_u csr + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12)))) + then + false + else true + end) + : bool)) + : M (bool) + | (b__3, User) => + (if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + read_reg scounteren_ref >>= fun w__6 : Counteren => + returnm ((eq_vec (_get_Counteren_CY w__6) ((bool_to_bits true) : mword 1)) + : bool) + else if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + read_reg scounteren_ref >>= fun w__7 : Counteren => + returnm ((eq_vec (_get_Counteren_TM w__7) ((bool_to_bits true) : mword 1)) + : bool) + else if ((eq_vec b__3 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg scounteren_ref >>= fun w__8 : Counteren => + returnm ((eq_vec (_get_Counteren_IR w__8) ((bool_to_bits true) : mword 1)) + : bool) + else + returnm ((match (b__3, User) with + | (g__37, g__38) => + if ((andb + (zopz0zIzJ_u + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) csr) + (zopz0zIzJ_u csr + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12)))) + then + false + else true + end) + : bool)) + : M (bool) + | (g__37, g__38) => + returnm ((if ((andb + (zopz0zIzJ_u (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12) + csr) + (zopz0zIzJ_u csr + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1] : mword 12)))) then + false + else true) + : bool) + end) + : M (bool). + +Definition check_CSR (csr : mword 12) (p : Privilege) (isWrite : bool) +: M (bool) := + + (and_boolM (returnm ((is_CSR_defined csr p) : bool)) + ((and_boolM (returnm ((check_CSR_access (csrAccess csr) (csrPriv csr) p isWrite) : bool)) + ((and_boolM ((check_TVM_SATP csr p) : M (bool)) ((check_Counteren csr p) : M (bool))) + : M (bool))) + : M (bool))) + : M (bool). + +Axiom speculate_conditional : forall (_ : unit) , M (bool). + +Axiom load_reservation : forall (_ : mword 64) , unit. + +Axiom match_reservation : forall (_ : mword 64) , bool. + +Axiom cancel_reservation : forall (_ : unit) , unit. + +Definition exception_delegatee (e : ExceptionType) (p : Privilege) +: M (Privilege) := + + let 'idx := projT1 (num_of_ExceptionType e) in + read_reg medeleg_ref >>= fun w__0 : Medeleg => + let super := access_vec_dec (_get_Medeleg_bits w__0) idx in + read_reg sedeleg_ref >>= fun w__1 : Sedeleg => + let user := access_vec_dec (_get_Sedeleg_bits w__1) idx in + (and_boolM + (read_reg misa_ref >>= fun w__2 : Misa => + returnm ((eq_vec (_get_Misa_S w__2) ((bool_to_bits true) : mword 1)) + : bool)) ((bit_to_bool super) : M (bool))) >>= fun w__4 : bool => + let deleg := if (w__4) then Supervisor else Machine in + returnm ((if ((zopz0zI_u (privLevel_to_bits deleg) (privLevel_to_bits p))) then p + else deleg) + : Privilege). + +Definition findPendingInterrupt (ip : mword 64) +: option InterruptType := + + let ip := Mk_Minterrupts ip in + if ((eq_vec (_get_Minterrupts_MEI ip) ((bool_to_bits true) : mword 1))) then Some (I_M_External) + else if ((eq_vec (_get_Minterrupts_MSI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_M_Software) + else if ((eq_vec (_get_Minterrupts_MTI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_M_Timer) + else if ((eq_vec (_get_Minterrupts_SEI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_S_External) + else if ((eq_vec (_get_Minterrupts_SSI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_S_Software) + else if ((eq_vec (_get_Minterrupts_STI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_S_Timer) + else if ((eq_vec (_get_Minterrupts_UEI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_U_External) + else if ((eq_vec (_get_Minterrupts_USI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_U_Software) + else if ((eq_vec (_get_Minterrupts_UTI ip) ((bool_to_bits true) : mword 1))) then + Some + (I_U_Timer) + else None. + +Definition curInterrupt +(priv : Privilege) (pend : Minterrupts) (enbl : Minterrupts) (delg : Minterrupts) +: M (option ((InterruptType * Privilege))) := + + let en_mip : xlenbits := and_vec (_get_Minterrupts_bits pend) (_get_Minterrupts_bits enbl) in + (if ((eq_vec en_mip (EXTZ 64 (vec_of_bits [B0] : mword 1)))) then + returnm (None + : option ((InterruptType * Privilege))) + else + (or_boolM + (returnm ((neq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2)) + : bool)) + ((and_boolM + (returnm ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2)) + : bool)) + (read_reg mstatus_ref >>= fun w__0 : Mstatus => + returnm ((eq_vec (_get_Mstatus_MIE w__0) ((bool_to_bits true) : mword 1)) + : bool))) + : M (bool))) >>= fun eff_mie => + (or_boolM + (returnm ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits User) : mword 2)) + : bool)) + ((and_boolM + (returnm ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits Supervisor) : mword 2)) + : bool)) + (read_reg mstatus_ref >>= fun w__2 : Mstatus => + returnm ((eq_vec (_get_Mstatus_SIE w__2) ((bool_to_bits true) : mword 1)) + : bool))) + : M (bool))) >>= fun eff_sie => + let eff_mip := and_vec en_mip (not_vec (_get_Minterrupts_bits delg)) in + let eff_sip := and_vec en_mip (_get_Minterrupts_bits delg) in + (if ((andb eff_mie (neq_vec eff_mip (EXTZ 64 (vec_of_bits [B0] : mword 1))))) then + (match (findPendingInterrupt eff_mip) with + | Some (i) => + let r := (i, Machine) in + returnm ((Some + (r)) + : option ((InterruptType * Privilege))) + | None => + (internal_error + (String.append "non-zero eff_mip=" + (String.append (string_of_bits eff_mip) ", but nothing pending"))) + : M (option ((InterruptType * Privilege))) + end) + : M (option ((InterruptType * Privilege))) + else if ((andb eff_sie (neq_vec eff_sip (EXTZ 64 (vec_of_bits [B0] : mword 1))))) then + (match (findPendingInterrupt eff_sip) with + | Some (i) => + let r := (i, Supervisor) in + returnm ((Some + (r)) + : option ((InterruptType * Privilege))) + | None => + (internal_error + (String.append "non-zero eff_sip=" + (String.append (string_of_bits eff_sip) ", but nothing pending"))) + : M (option ((InterruptType * Privilege))) + end) + : M (option ((InterruptType * Privilege))) + else + let p := + if ((eq_vec (_get_Minterrupts_MTI pend) ((bool_to_bits true) : mword 1))) then "1" + else "0" in + let e := + if ((eq_vec (_get_Minterrupts_MTI enbl) ((bool_to_bits true) : mword 1))) then "1" + else "0" in + let d := + if ((eq_vec (_get_Minterrupts_MTI delg) ((bool_to_bits true) : mword 1))) then "1" + else "0" in + let '_ := + (print_endline + (String.append " MTI: pend=" + (String.append p + (String.append " enbl=" (String.append e (String.append " delg=" d)))))) + : unit in + let eff_mip := and_vec en_mip (not_vec (_get_Minterrupts_bits delg)) in + let eff_sip := and_vec en_mip (_get_Minterrupts_bits delg) in + read_reg mstatus_ref >>= fun w__8 : Mstatus => + read_reg mstatus_ref >>= fun w__9 : Mstatus => + read_reg mstatus_ref >>= fun w__10 : Mstatus => + let '_ := + (print_endline + (String.append "mstatus=" + (String.append (string_of_bits (_get_Mstatus_bits w__8)) + (String.append " mie,sie=" + (String.append (string_of_bits (_get_Mstatus_MIE w__9)) + (String.append "," + (String.append (string_of_bits (_get_Mstatus_SIE w__10)) + (String.append " en_mip=" + (String.append (string_of_bits en_mip) + (String.append " eff_mip=" + (String.append (string_of_bits eff_mip) + (String.append " eff_sip=" (string_of_bits eff_sip))))))))))))) + : unit in + returnm (None + : option ((InterruptType * Privilege)))) + : M (option ((InterruptType * Privilege)))) + : M (option ((InterruptType * Privilege))). + +Definition tval (excinfo : option (mword 64)) +: mword 64 := + + match excinfo with | Some (e) => e | None => EXTZ 64 (vec_of_bits [B0] : mword 1) end. + +Definition rvfi_trap '(tt : unit) : unit := tt. + +Definition handle_trap +(del_priv : Privilege) (intr : bool) (c : mword 4) (pc : mword 64) (info : option (mword 64)) +: M (mword 64) := + + let '_ := (rvfi_trap tt) : unit in + let '_ := + (print_endline + (String.append "handling " + (String.append (if (intr) then "int#" else "exc#") + (String.append (string_of_bits c) + (String.append " at priv " + (String.append ((privLevel_to_str del_priv) : string) + (String.append " with tval " (string_of_bits (tval info))))))))) + : unit in + (match del_priv with + | Machine => + (_set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr) : mword 1)) >> + (_set_Mcause_Cause mcause_ref (EXTZ 63 c)) >> + read_reg mstatus_ref >>= fun w__0 : Mstatus => + (_set_Mstatus_MPIE mstatus_ref (_get_Mstatus_MIE w__0)) >> + (_set_Mstatus_MIE mstatus_ref ((bool_to_bits false) : mword 1)) >> + read_reg cur_privilege_ref >>= fun w__1 : Privilege => + (_set_Mstatus_MPP mstatus_ref (privLevel_to_bits w__1)) >> + write_reg mtval_ref (tval info) >> + write_reg mepc_ref pc >> + write_reg cur_privilege_ref del_priv >> + read_reg mstatus_ref >>= fun w__2 : Mstatus => + read_reg mstatus_ref >>= fun w__3 : Mstatus => + let '_ := + (print_endline + (String.append "CSR mstatus <- " + (String.append (string_of_bits (_get_Mstatus_bits w__2)) + (String.append " (input: " + (String.append (string_of_bits (_get_Mstatus_bits w__3)) ")"))))) + : unit in + let '_ := (cancel_reservation tt) : unit in + read_reg mtvec_ref >>= fun w__4 : Mtvec => + read_reg mcause_ref >>= fun w__5 : Mcause => + (match (tvec_addr w__4 w__5) with + | Some (epc) => returnm (epc : mword 64) + | None => (internal_error "Invalid mtvec mode") : M (mword 64) + end) + : M (mword 64) + | Supervisor => + (_set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr) : mword 1)) >> + (_set_Mcause_Cause scause_ref (EXTZ 63 c)) >> + read_reg mstatus_ref >>= fun w__8 : Mstatus => + (_set_Mstatus_SPIE mstatus_ref (_get_Mstatus_SIE w__8)) >> + (_set_Mstatus_SIE mstatus_ref ((bool_to_bits false) : mword 1)) >> + read_reg cur_privilege_ref >>= fun w__9 : Privilege => + (match w__9 with + | User => returnm ((bool_to_bits false) : mword 1) + | Supervisor => returnm ((bool_to_bits true) : mword 1) + | Machine => (internal_error "invalid privilege for s-mode trap") : M (mword 1) + end) >>= fun w__11 : mword 1 => + (_set_Mstatus_SPP mstatus_ref w__11) >> + write_reg stval_ref (tval info) >> + write_reg sepc_ref pc >> + write_reg cur_privilege_ref del_priv >> + read_reg mstatus_ref >>= fun w__12 : Mstatus => + read_reg mstatus_ref >>= fun w__13 : Mstatus => + let '_ := + (print_endline + (String.append "CSR mstatus <- " + (String.append (string_of_bits (_get_Mstatus_bits w__12)) + (String.append " (input: " + (String.append (string_of_bits (_get_Mstatus_bits w__13)) ")"))))) + : unit in + let '_ := (cancel_reservation tt) : unit in + read_reg stvec_ref >>= fun w__14 : Mtvec => + read_reg scause_ref >>= fun w__15 : Mcause => + (match (tvec_addr w__14 w__15) with + | Some (epc) => returnm (epc : mword 64) + | None => (internal_error "Invalid stvec mode") : M (mword 64) + end) + : M (mword 64) + | User => (internal_error "the N extension is currently unsupported") : M (mword 64) + end) + : M (mword 64). + +Definition handle_exception (cur_priv : Privilege) (ctl : ctl_result) (pc : mword 64) +: M (mword 64) := + + (match (cur_priv, ctl) with + | (_, CTL_TRAP (e)) => + (exception_delegatee e.(sync_exception_trap) cur_priv) >>= fun del_priv => + let '_ := + (print_endline + (String.append "trapping from " + (String.append ((privLevel_to_str cur_priv) : string) + (String.append " to " + (String.append ((privLevel_to_str del_priv) : string) + (String.append " to handle " + ((exceptionType_to_str e.(sync_exception_trap)) + : string))))))) + : unit in + (handle_trap del_priv false ((exceptionType_to_bits e.(sync_exception_trap)) : mword 4) pc + e.(sync_exception_excinfo)) + : M (mword 64) + | (_, CTL_MRET (tt)) => + read_reg cur_privilege_ref >>= fun prev_priv => + read_reg mstatus_ref >>= fun w__1 : Mstatus => + (_set_Mstatus_MIE mstatus_ref (_get_Mstatus_MPIE w__1)) >> + (_set_Mstatus_MPIE mstatus_ref ((bool_to_bits true) : mword 1)) >> + read_reg mstatus_ref >>= fun w__2 : Mstatus => + write_reg cur_privilege_ref (privLevel_of_bits (_get_Mstatus_MPP w__2)) >> + (_set_Mstatus_MPP mstatus_ref (privLevel_to_bits User)) >> + read_reg mstatus_ref >>= fun w__3 : Mstatus => + read_reg mstatus_ref >>= fun w__4 : Mstatus => + let '_ := + (print_endline + (String.append "CSR mstatus <- " + (String.append (string_of_bits (_get_Mstatus_bits w__3)) + (String.append " (input: " + (String.append (string_of_bits (_get_Mstatus_bits w__4)) ")"))))) + : unit in + read_reg cur_privilege_ref >>= fun w__5 : Privilege => + let '_ := + (print_endline + (String.append "ret-ing from " + (String.append ((privLevel_to_str prev_priv) : string) + (String.append " to " ((privLevel_to_str w__5) : string))))) + : unit in + let '_ := (cancel_reservation tt) : unit in + ((read_reg mepc_ref) : M (mword 64)) >>= fun w__6 : xlenbits => + (pc_alignment_mask tt) >>= fun w__7 : mword 64 => returnm ((and_vec w__6 w__7) : mword 64) + | (_, CTL_SRET (tt)) => + read_reg cur_privilege_ref >>= fun prev_priv => + read_reg mstatus_ref >>= fun w__8 : Mstatus => + (_set_Mstatus_SIE mstatus_ref (_get_Mstatus_SPIE w__8)) >> + (_set_Mstatus_SPIE mstatus_ref ((bool_to_bits true) : mword 1)) >> + read_reg mstatus_ref >>= fun w__9 : Mstatus => + write_reg + cur_privilege_ref + (if ((eq_vec (_get_Mstatus_SPP w__9) ((bool_to_bits true) : mword 1))) then Supervisor + else User) >> + (_set_Mstatus_SPP mstatus_ref ((bool_to_bits false) : mword 1)) >> + read_reg mstatus_ref >>= fun w__10 : Mstatus => + read_reg mstatus_ref >>= fun w__11 : Mstatus => + let '_ := + (print_endline + (String.append "CSR mstatus <- " + (String.append (string_of_bits (_get_Mstatus_bits w__10)) + (String.append " (input: " + (String.append (string_of_bits (_get_Mstatus_bits w__11)) ")"))))) + : unit in + read_reg cur_privilege_ref >>= fun w__12 : Privilege => + let '_ := + (print_endline + (String.append "ret-ing from " + (String.append ((privLevel_to_str prev_priv) : string) + (String.append " to " ((privLevel_to_str w__12) : string))))) + : unit in + let '_ := (cancel_reservation tt) : unit in + ((read_reg sepc_ref) : M (mword 64)) >>= fun w__13 : xlenbits => + (pc_alignment_mask tt) >>= fun w__14 : mword 64 => + returnm ((and_vec w__13 w__14) + : mword 64) + end) + : M (mword 64). + +Definition handle_mem_exception (addr : mword 64) (e : ExceptionType) +: M (unit) := + + let t : sync_exception := + {| sync_exception_trap := e; + sync_exception_excinfo := (Some (addr)) |} in + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + (handle_exception w__0 (CTL_TRAP (t)) w__1) >>= fun w__2 : mword 64 => + write_reg nextPC_ref w__2 + : M (unit). + +Definition handle_interrupt (i : InterruptType) (del_priv : Privilege) +: M (unit) := + + ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + (handle_trap del_priv true ((interruptType_to_bits i) : mword 4) w__0 None) >>= fun w__1 : mword 64 => + write_reg nextPC_ref w__1 + : M (unit). + +Definition init_sys '(tt : unit) +: M (unit) := + + write_reg cur_privilege_ref Machine >> + write_reg mhartid_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + (_set_Misa_MXL misa_ref (arch_to_bits RV64)) >> + (_set_Misa_A misa_ref ((bool_to_bits true) : mword 1)) >> + (_set_Misa_C misa_ref ((bool_to_bits true) : mword 1)) >> + (_set_Misa_I misa_ref ((bool_to_bits true) : mword 1)) >> + (_set_Misa_M misa_ref ((bool_to_bits true) : mword 1)) >> + (_set_Misa_U misa_ref ((bool_to_bits true) : mword 1)) >> + (_set_Misa_S misa_ref ((bool_to_bits true) : mword 1)) >> + read_reg misa_ref >>= fun w__0 : Misa => + (_set_Mstatus_SXL mstatus_ref (_get_Misa_MXL w__0)) >> + read_reg misa_ref >>= fun w__1 : Misa => + (_set_Mstatus_UXL mstatus_ref (_get_Misa_MXL w__1)) >> + (_set_Mstatus_SD mstatus_ref ((bool_to_bits false) : mword 1)) >> + (_set_Minterrupts_bits mip_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + (_set_Minterrupts_bits mie_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + (_set_Minterrupts_bits mideleg_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + (_set_Medeleg_bits medeleg_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + (_set_Mtvec_bits mtvec_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + (_set_Mcause_bits mcause_ref (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + write_reg mepc_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + write_reg mtval_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + write_reg mscratch_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + write_reg mcycle_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + write_reg mtime_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + (_set_Counteren_bits mcounteren_ref (EXTZ 32 (vec_of_bits [B0] : mword 1))) >> + write_reg minstret_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + write_reg minstret_written_ref false >> + read_reg mstatus_ref >>= fun w__2 : Mstatus => + returnm ((print_endline + (String.append "CSR mstatus <- " + (String.append (string_of_bits (_get_Mstatus_bits w__2)) + (String.append " (input: " + (String.append + (string_of_bits ((EXTZ 64 (vec_of_bits [B0] : mword 1)) : xlenbits)) + ")"))))) + : unit). + +Axiom plat_ram_base : forall (_ : unit) , mword 64. + +Axiom plat_ram_size : forall (_ : unit) , mword 64. + +Axiom plat_enable_dirty_update : forall (_ : unit) , bool. + +Axiom plat_enable_misaligned_access : forall (_ : unit) , bool. + +Axiom plat_mtval_has_illegal_inst_bits : forall (_ : unit) , bool. + +Axiom plat_rom_base : forall (_ : unit) , mword 64. + +Axiom plat_rom_size : forall (_ : unit) , mword 64. + +Axiom plat_clint_base : forall (_ : unit) , mword 64. + +Axiom plat_clint_size : forall (_ : unit) , mword 64. + +Axiom plat_htif_tohost : forall (_ : unit) , mword 64. + +Definition phys_mem_segments '(tt : unit) +: list ((mword 64 * mword 64)) := + + (plat_rom_base tt, plat_rom_size tt) :: (plat_ram_base tt, plat_ram_size tt) :: []. + +Definition within_phys_mem (addr : mword 64) (width : Z) +: bool := + + let ram_base := plat_ram_base tt in + let rom_base := plat_rom_base tt in + let ram_size := plat_ram_size tt in + let rom_size := plat_rom_size tt in + if ((andb (zopz0zIzJ_u ram_base addr) + (zopz0zIzJ_u (add_vec_int addr width) (add_vec ram_base ram_size)))) then + true + else if ((andb (zopz0zIzJ_u rom_base addr) + (zopz0zIzJ_u (add_vec_int addr width) (add_vec rom_base rom_size)))) then + true + else + let '_ := + (print_endline + (String.append "within_phys_mem: " + (String.append (string_of_bits addr) " not within phys-mem:"))) + : unit in + let '_ := (print_endline (String.append " plat_rom_base: " (string_of_bits rom_base))) : unit in + let '_ := (print_endline (String.append " plat_rom_size: " (string_of_bits rom_size))) : unit in + let '_ := (print_endline (String.append " plat_ram_base: " (string_of_bits ram_base))) : unit in + let '_ := (print_endline (String.append " plat_ram_size: " (string_of_bits ram_size))) : unit in + false. + +Definition within_clint (addr : mword 64) (width : Z) +: bool := + + andb (zopz0zIzJ_u (plat_clint_base tt) addr) + (zopz0zIzJ_u (add_vec_int addr width) (add_vec (plat_clint_base tt) (plat_clint_size tt))). + +Definition within_htif_writable (addr : mword 64) (width : Z) +: bool := + + eq_vec (plat_htif_tohost tt) addr. + +Definition within_htif_readable (addr : mword 64) (width : Z) +: bool := + + eq_vec (plat_htif_tohost tt) addr. + +Axiom plat_insns_per_tick : forall (_ : unit) , Z. + +Definition MSIP_BASE : xlenbits := +(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64). +Hint Unfold MSIP_BASE : sail. +Definition MTIMECMP_BASE : xlenbits := +(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64). +Hint Unfold MTIMECMP_BASE : sail. +Definition MTIME_BASE : xlenbits := +(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0; + B0] + : mword 64). +Hint Unfold MTIME_BASE : sail. +Definition clint_load (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + let addr := sub_vec addr (plat_clint_base tt) in + (if sumbool_of_bool ((andb (eq_vec addr MSIP_BASE) (orb (Z.eqb width 8) (Z.eqb width 4)))) then + read_reg mip_ref >>= fun w__0 : Minterrupts => + let '_ := + (print_endline + (String.append "clint[" + (String.append (string_of_bits addr) + (String.append "] -> " (string_of_bits (_get_Minterrupts_MSI w__0)))))) + : unit in + read_reg mip_ref >>= fun w__1 : Minterrupts => + returnm ((MemValue + (zero_extend (_get_Minterrupts_MSI w__1) (Z.mul 8 width))) + : MemoryOpResult (mword (8 * width))) + else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb width 8))) then + ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__2 : xlenbits => + let '_ := + (print_endline + (String.append "clint[" + (String.append (string_of_bits addr) (String.append "] -> " (string_of_bits w__2))))) + : unit in + ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__3 : xlenbits => + returnm ((MemValue + (zero_extend w__3 _)) + : MemoryOpResult (mword (8 * width))) + else if sumbool_of_bool ((andb (eq_vec addr MTIME_BASE) (Z.eqb width 8))) then + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__4 : xlenbits => + let '_ := + (print_endline + (String.append "clint[" + (String.append (string_of_bits addr) (String.append "] -> " (string_of_bits w__4))))) + : unit in + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__5 : xlenbits => + returnm ((MemValue + (zero_extend w__5 _)) + : MemoryOpResult (mword (8 * width))) + else + let '_ := + (print_endline + (String.append "clint[" (String.append (string_of_bits addr) "] -> <not-mapped>"))) + : unit in + returnm ((MemException + (E_Load_Access_Fault)) + : MemoryOpResult (mword (8 * width)))) + : M (MemoryOpResult (mword (8 * width))). + +Definition clint_dispatch '(tt : unit) +: M (unit) := + + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let '_ := (print_endline (String.append "clint::tick mtime <- " (string_of_bits w__0))) : unit in + (_set_Minterrupts_MTI mip_ref ((bool_to_bits false) : mword 1)) >> + ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__2 : xlenbits => + (if ((zopz0zIzJ_u w__1 w__2)) then + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__3 : xlenbits => + let '_ := + (print_endline (String.append " clint timer pending at mtime " (string_of_bits w__3))) + : unit in + (_set_Minterrupts_MTI mip_ref ((bool_to_bits true) : mword 1)) + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition clint_store (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + let addr := sub_vec addr (plat_clint_base tt) in + (if sumbool_of_bool ((andb (eq_vec addr MSIP_BASE) (orb (Z.eqb width 8) (Z.eqb width 4)))) then + (cast_unit_vec (access_vec_dec data 0)) >>= fun w__0 : mword 1 => + let '_ := + (print_endline + (String.append "clint[" + (String.append (string_of_bits addr) + (String.append "] <- " + (String.append (string_of_bits data) + (String.append " (mip.MSI <- " (String.append (string_of_bits w__0) ")"))))))) + : unit in + (cast_unit_vec (access_vec_dec data 0)) >>= fun w__1 : mword 1 => + (_set_Minterrupts_MSI mip_ref + ((bool_to_bits (eq_vec w__1 (vec_of_bits [B1] : mword 1))) + : mword 1)) >> + (clint_dispatch tt) >> returnm ((MemValue (true)) : MemoryOpResult bool) + else if sumbool_of_bool ((andb (eq_vec addr MTIMECMP_BASE) (Z.eqb width 8))) then + let '_ := + (print_endline + (String.append "clint[" + (String.append (string_of_bits addr) + (String.append "] <- " (String.append (string_of_bits data) " (mtimecmp)"))))) + : unit in + write_reg mtimecmp_ref (zero_extend data 64) >> + (clint_dispatch tt) >> returnm ((MemValue (true)) : MemoryOpResult bool) + else + let '_ := + (print_endline + (String.append "clint[" + (String.append (string_of_bits addr) + (String.append "] <- " (String.append (string_of_bits data) " (<unmapped>)"))))) + : unit in + returnm ((MemException + (E_SAMO_Access_Fault)) + : MemoryOpResult bool)) + : M (MemoryOpResult bool). + +Definition tick_clock '(tt : unit) +: M (unit) := + + ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + write_reg mcycle_ref (add_vec_int w__0 1) >> + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + write_reg mtime_ref (add_vec_int w__1 1) >> (clint_dispatch tt) : M (unit). + +Axiom plat_term_write : forall (_ : mword 8) , unit. + +Axiom plat_term_read : forall (_ : unit) , mword 8. + +Definition Mk_htif_cmd (v : mword 64) +: htif_cmd := + + {| htif_cmd_htif_cmd_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_htif_cmd_bits (v : htif_cmd) +: mword 64 := + + subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 0. + +Definition _set_htif_cmd_bits (r_ref : register_ref regstate register_value htif_cmd) (v : mword 64) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : htif_cmd in + write_reg r_ref r + : M (unit). + +Definition _update_htif_cmd_bits (v : htif_cmd) (x : mword 64) +: htif_cmd := + + {[ v with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_htif_cmd_device (v : htif_cmd) +: mword 8 := + + subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 56. + +Definition _set_htif_cmd_device +(r_ref : register_ref regstate register_value htif_cmd) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 63 56 (subrange_vec_dec v 7 0)) ]} + : htif_cmd in + write_reg r_ref r + : M (unit). + +Definition _update_htif_cmd_device (v : htif_cmd) (x : mword 8) +: htif_cmd := + + {[ v with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 63 56 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_htif_cmd_cmd (v : htif_cmd) +: mword 8 := + + subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 55 48. + +Definition _set_htif_cmd_cmd (r_ref : register_ref regstate register_value htif_cmd) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 55 48 (subrange_vec_dec v 7 0)) ]} + : htif_cmd in + write_reg r_ref r + : M (unit). + +Definition _update_htif_cmd_cmd (v : htif_cmd) (x : mword 8) +: htif_cmd := + + {[ v with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 55 48 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_htif_cmd_payload (v : htif_cmd) +: mword 48 := + + subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 47 0. + +Definition _set_htif_cmd_payload +(r_ref : register_ref regstate register_value htif_cmd) (v : mword 48) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec r.(htif_cmd_htif_cmd_chunk_0) 47 0 (subrange_vec_dec v 47 0)) ]} + : htif_cmd in + write_reg r_ref r + : M (unit). + +Definition _update_htif_cmd_payload (v : htif_cmd) (x : mword 48) +: htif_cmd := + + {[ v with + htif_cmd_htif_cmd_chunk_0 := + (update_subrange_vec_dec v.(htif_cmd_htif_cmd_chunk_0) 47 0 (subrange_vec_dec x 47 0)) ]}. + +Definition htif_load (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let '_ := + (print_endline + (String.append "htif[" + (String.append (string_of_bits addr) (String.append "] -> " (string_of_bits w__0))))) + : unit in + (if sumbool_of_bool ((Z.eqb width 8)) then + ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + returnm ((MemValue + (zero_extend w__1 _)) + : MemoryOpResult (mword (8 * width))) + else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width)))) + : M (MemoryOpResult (mword (8 * width))). + +Definition htif_store (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact ((0 + 1) <= width /\ width <= 8)} +: M (MemoryOpResult bool) := + + let '_ := + (print_endline + (String.append "htif[" + (String.append (string_of_bits addr) (String.append "] <- " (string_of_bits data))))) + : unit in + let cbits : xlenbits := EXTZ 64 data in + write_reg htif_tohost_ref cbits >> + let cmd := Mk_htif_cmd cbits in + let b__0 := _get_htif_cmd_device cmd in + (if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then + let '_ := + (print_endline + (String.append "htif-syscall-proxy cmd: " (string_of_bits (_get_htif_cmd_payload cmd)))) + : unit in + (cast_unit_vec (access_vec_dec (_get_htif_cmd_payload cmd) 0)) >>= fun w__0 : mword 1 => + (if ((eq_vec w__0 (vec_of_bits [B1] : mword 1))) then + write_reg htif_done_ref true >> + write_reg + htif_exit_code_ref + ((shift_bits_right (zero_extend (_get_htif_cmd_payload cmd) xlen) + (vec_of_bits [B0;B1] : mword 2)) + : xlenbits) + : M (unit) + else returnm (tt : unit)) + : M (unit) + else + returnm ((if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8))) then + let '_ := + (print_endline + (String.append "htif-term cmd: " (string_of_bits (_get_htif_cmd_payload cmd)))) + : unit in + let b__2 := _get_htif_cmd_cmd cmd in + if ((eq_vec b__2 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then tt + else if ((eq_vec b__2 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1] : mword 8))) then + plat_term_write (subrange_vec_dec (_get_htif_cmd_payload cmd) 7 0) + else print_endline (String.append "Unknown term cmd: " (string_of_bits b__2)) + else print_endline (String.append "htif-???? cmd: " (string_of_bits data))) + : unit)) >> + returnm ((MemValue + (true)) + : MemoryOpResult bool). + +Definition htif_tick '(tt : unit) +: M (unit) := + + ((read_reg htif_tohost_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let '_ := (print_endline (String.append "htif::tick " (string_of_bits w__0))) : unit in + write_reg htif_tohost_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) + : M (unit). + +Definition within_mmio_readable (addr : mword 64) (width : Z) +: bool := + + orb (within_clint addr width) (andb (within_htif_readable addr width) (Z.leb 1 width)). + +Definition within_mmio_writable (addr : mword 64) (width : Z) +: bool := + + orb (within_clint addr width) (andb (within_htif_writable addr width) (Z.leb width 8)). + +Definition mmio_read (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (if ((within_clint addr width)) then + (clint_load addr width) + : M (MemoryOpResult (mword (8 * width))) + else if sumbool_of_bool ((andb (within_htif_readable addr width) (Z.leb 1 width))) then + (htif_load addr width) + : M (MemoryOpResult (mword (8 * width))) + else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width)))) + : M (MemoryOpResult (mword (8 * width))). + +Definition mmio_write (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (if ((within_clint addr width)) then (clint_store addr width data) : M (MemoryOpResult bool) + else if sumbool_of_bool ((andb (within_htif_writable addr width) (Z.leb width 8))) then + (htif_store addr width data) + : M (MemoryOpResult bool) + else returnm ((MemException (E_SAMO_Access_Fault)) : MemoryOpResult bool)) + : M (MemoryOpResult bool). + +Definition init_platform '(tt : unit) +: M (unit) := + + write_reg htif_tohost_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) >> + write_reg htif_done_ref false >> + write_reg htif_exit_code_ref (EXTZ 64 (vec_of_bits [B0] : mword 1)) + : M (unit). + +Definition tick_platform '(tt : unit) +: M (unit) := + + let '_ := (cancel_reservation tt) : unit in + (htif_tick tt) + : M (unit). + +Definition handle_illegal '(tt : unit) +: M (unit) := + + (if ((plat_mtval_has_illegal_inst_bits tt)) then + ((read_reg instbits_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + returnm ((Some + (w__0)) + : option (mword 64)) + else returnm (None : option (mword 64))) >>= fun info => + let t : sync_exception := + {| sync_exception_trap := E_Illegal_Instr; + sync_exception_excinfo := info |} in + read_reg cur_privilege_ref >>= fun w__1 : Privilege => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : xlenbits => + (handle_exception w__1 (CTL_TRAP (t)) w__2) >>= fun w__3 : mword 64 => + write_reg nextPC_ref w__3 + : M (unit). + +Definition platform_wfi '(tt : unit) +: M (unit) := + + ((read_reg mtime_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + (if ((zopz0zI_u w__0 w__1)) then + ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__2 : xlenbits => + write_reg mtime_ref w__2 >> + ((read_reg mtimecmp_ref) : M (mword 64)) >>= fun w__3 : xlenbits => + write_reg mcycle_ref w__3 + : M (unit) + else returnm (tt : unit)) + : M (unit). + +Definition is_aligned_addr (addr : mword 64) (width : Z) +: bool := + + Z.eqb (modulus (projT1 (uint addr)) width) 0. + +Definition phys_mem_read +(t : ReadType) (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool) +`{ArithFact (width >= 0)} +: M (MemoryOpResult (mword (8 * width))) := + + (__RISCV_read addr width aq rl res) >>= fun w__0 : option (mword (8 * width)) => + returnm ((match (t, w__0) with + | (Instruction, None) => MemException (E_Fetch_Access_Fault) + | (Data, None) => MemException (E_Load_Access_Fault) + | (_, Some (v)) => + let '_ := + (print_endline + (String.append "mem[" + (String.append ((readType_to_str t) : string) + (String.append "," + (String.append (string_of_bits addr) + (String.append "] -> " (string_of_bits v))))))) + : unit in + MemValue + (v) + end) + : MemoryOpResult (mword (8 * width))). + +Definition checked_mem_read +(t : ReadType) (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (if ((andb (generic_eq ((readType_to_str t) : string) ((readType_to_str Data) : string)) + (within_mmio_readable addr width))) then + (mmio_read addr width) + : M (MemoryOpResult (mword (8 * width))) + else if ((within_phys_mem addr width)) then + (phys_mem_read t addr width aq rl res) + : M (MemoryOpResult (mword (8 * width))) + else returnm ((MemException (E_Load_Access_Fault)) : MemoryOpResult (mword (8 * width)))) + : M (MemoryOpResult (mword (8 * width))). + +Definition MEMr (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (checked_mem_read Data addr width false false false) + : M (MemoryOpResult (mword (8 * width))). + +Definition MEMr_acquire (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (checked_mem_read Data addr width true false false) + : M (MemoryOpResult (mword (8 * width))). + +Definition MEMr_strong_acquire (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (checked_mem_read Data addr width true true false) + : M (MemoryOpResult (mword (8 * width))). + +Definition MEMr_reserved (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (checked_mem_read Data addr width false false true) + : M (MemoryOpResult (mword (8 * width))). + +Definition MEMr_reserved_acquire (addr : mword 64) (width : Z) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (checked_mem_read Data addr width true false true) + : M (MemoryOpResult (mword (8 * width))). + +Definition MEMr_reserved_strong_acquire (addr : mword 64) (width : Z) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (checked_mem_read Data addr width true true true) + : M (MemoryOpResult (mword (8 * width))). + +Definition rvfi_read (addr : mword 64) (width : Z) (value : MemoryOpResult (mword (8 * width))) +`{ArithFact (width >= (0 + 1))} +: unit := + + tt. + +Definition mem_read (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (res : bool) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult (mword (8 * width))) := + + (if ((andb (orb aq res) (negb (is_aligned_addr addr width)))) then + returnm ((MemException + (E_Load_Addr_Align)) + : MemoryOpResult (mword (8 * width))) + else + (match (aq, rl, res) with + | (false, false, false) => + (checked_mem_read Data addr width false false false) + : M (MemoryOpResult (mword (8 * width))) + | (true, false, false) => (MEMr_acquire addr width) : M (MemoryOpResult (mword (8 * width))) + | (false, false, true) => + (MEMr_reserved addr width) : M (MemoryOpResult (mword (8 * width))) + | (true, false, true) => + (MEMr_reserved_acquire addr width) : M (MemoryOpResult (mword (8 * width))) + | (false, true, false) => + (throw (Error_not_implemented ("load.rl"))) : M (MemoryOpResult (mword (8 * width))) + | (true, true, false) => + (MEMr_strong_acquire addr width) : M (MemoryOpResult (mword (8 * width))) + | (false, true, true) => + (throw (Error_not_implemented ("lr.rl"))) : M (MemoryOpResult (mword (8 * width))) + | (true, true, true) => + (MEMr_reserved_strong_acquire addr width) : M (MemoryOpResult (mword (8 * width))) + end) + : M (MemoryOpResult (mword (8 * width)))) >>= fun result : MemoryOpResult (bits (8 * width)) => + let '_ := (rvfi_read addr width result) : unit in + returnm (result + : MemoryOpResult (mword (8 * width))). + +Definition mem_write_ea (addr : mword 64) (width : Z) (aq : bool) (rl : bool) (con : bool) +: M (MemoryOpResult unit) := + + (if ((andb (orb rl con) (negb (is_aligned_addr addr width)))) then + returnm ((MemException + (E_SAMO_Addr_Align)) + : MemoryOpResult unit) + else + (match (aq, rl, con) with + | (false, false, false) => + (MEMea addr width) >> returnm ((MemValue (tt)) : MemoryOpResult unit) + | (false, true, false) => + (MEMea_release addr width) >> returnm ((MemValue (tt)) : MemoryOpResult unit) + | (false, false, true) => + (MEMea_conditional addr width) >> returnm ((MemValue (tt)) : MemoryOpResult unit) + | (false, true, true) => + (MEMea_conditional_release addr width) >> returnm ((MemValue (tt)) : MemoryOpResult unit) + | (true, false, false) => + (throw (Error_not_implemented ("store.aq"))) : M (MemoryOpResult unit) + | (true, true, false) => + (MEMea_strong_release addr width) >> returnm ((MemValue (tt)) : MemoryOpResult unit) + | (true, false, true) => (throw (Error_not_implemented ("sc.aq"))) : M (MemoryOpResult unit) + | (true, true, true) => + (MEMea_conditional_strong_release addr width) >> + returnm ((MemValue + (tt)) + : MemoryOpResult unit) + end) + : M (MemoryOpResult unit)) + : M (MemoryOpResult unit). + +Definition phys_mem_write (addr : mword 64) (width : Z) (data : mword (8 * width)) +: M (MemoryOpResult bool) := + + let '_ := + (print_endline + (String.append "mem[" + (String.append (string_of_bits addr) (String.append "] <- " (string_of_bits data))))) + : unit in + (__RISCV_write addr width data) >>= fun w__0 : bool => + returnm ((MemValue + (w__0)) + : MemoryOpResult bool). + +Definition checked_mem_write (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (if ((within_mmio_writable addr width)) then + (mmio_write addr width data) + : M (MemoryOpResult bool) + else if ((within_phys_mem addr width)) then + (phys_mem_write addr width data) + : M (MemoryOpResult bool) + else returnm ((MemException (E_SAMO_Access_Fault)) : MemoryOpResult bool)) + : M (MemoryOpResult bool). + +Definition MEMval (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (checked_mem_write addr width data) + : M (MemoryOpResult bool). + +Definition MEMval_release (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (checked_mem_write addr width data) + : M (MemoryOpResult bool). + +Definition MEMval_strong_release (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (checked_mem_write addr width data) + : M (MemoryOpResult bool). + +Definition MEMval_conditional (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (checked_mem_write addr width data) + : M (MemoryOpResult bool). + +Definition MEMval_conditional_release (addr : mword 64) (width : Z) (data : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (checked_mem_write addr width data) + : M (MemoryOpResult bool). + +Definition MEMval_conditional_strong_release +(addr : mword 64) (width : Z) (data : mword (8 * width)) `{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + (checked_mem_write addr width data) + : M (MemoryOpResult bool). + +Definition rvfi_write (addr : mword 64) (width : Z) (value : mword (8 * width)) +`{ArithFact (width >= (0 + 1))} +: unit := + + tt. + +Definition mem_write_value +(addr : mword 64) (width : Z) (value : mword (8 * width)) (aq : bool) (rl : bool) (con : bool) +`{ArithFact (width >= (0 + 1))} +: M (MemoryOpResult bool) := + + let '_ := (rvfi_write addr width value) : unit in + (if ((andb (orb rl con) (negb (is_aligned_addr addr width)))) then + returnm ((MemException + (E_SAMO_Addr_Align)) + : MemoryOpResult bool) + else + (match (aq, rl, con) with + | (false, false, false) => (checked_mem_write addr width value) : M (MemoryOpResult bool) + | (false, true, false) => (MEMval_release addr width value) : M (MemoryOpResult bool) + | (false, false, true) => (MEMval_conditional addr width value) : M (MemoryOpResult bool) + | (false, true, true) => + (MEMval_conditional_release addr width value) : M (MemoryOpResult bool) + | (true, false, false) => + (throw (Error_not_implemented ("store.aq"))) : M (MemoryOpResult bool) + | (true, true, false) => (MEMval_strong_release addr width value) : M (MemoryOpResult bool) + | (true, false, true) => (throw (Error_not_implemented ("sc.aq"))) : M (MemoryOpResult bool) + | (true, true, true) => + (MEMval_conditional_strong_release addr width value) : M (MemoryOpResult bool) + end) + : M (MemoryOpResult bool)) + : M (MemoryOpResult bool). + +Definition PAGESIZE_BITS := 12. +Hint Unfold PAGESIZE_BITS : sail. +Definition Mk_PTE_Bits (v : mword 8) +: PTE_Bits := + + {| PTE_Bits_PTE_Bits_chunk_0 := (subrange_vec_dec v 7 0) |}. + +Definition _get_PTE_Bits_bits (v : PTE_Bits) +: mword 8 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 0. + +Definition _set_PTE_Bits_bits (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_bits (v : PTE_Bits) (x : mword 8) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. + +Definition _get_PTE_Bits_D (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 7. + +Definition _set_PTE_Bits_D (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 7 7 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_D (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 7 7 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_A (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 6 6. + +Definition _set_PTE_Bits_A (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 6 6 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_A (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 6 6 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_G (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 5 5. + +Definition _set_PTE_Bits_G (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 5 5 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_G (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 5 5 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_U (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 4 4. + +Definition _set_PTE_Bits_U (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 4 4 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_U (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 4 4 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_X (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 3 3. + +Definition _set_PTE_Bits_X (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 3 3 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_X (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 3 3 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_W (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 2 2. + +Definition _set_PTE_Bits_W (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 2 2 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_W (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 2 2 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_R (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 1 1. + +Definition _set_PTE_Bits_R (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 1 1 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_R (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 1 1 (subrange_vec_dec x 0 0)) ]}. + +Definition _get_PTE_Bits_V (v : PTE_Bits) +: mword 1 := + + subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 0 0. + +Definition _set_PTE_Bits_V (r_ref : register_ref regstate register_value PTE_Bits) (v : mword 1) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec r.(PTE_Bits_PTE_Bits_chunk_0) 0 0 (subrange_vec_dec v 0 0)) ]} + : PTE_Bits in + write_reg r_ref r + : M (unit). + +Definition _update_PTE_Bits_V (v : PTE_Bits) (x : mword 1) +: PTE_Bits := + + {[ v with + PTE_Bits_PTE_Bits_chunk_0 := + (update_subrange_vec_dec v.(PTE_Bits_PTE_Bits_chunk_0) 0 0 (subrange_vec_dec x 0 0)) ]}. + +Definition isPTEPtr (p : mword 8) +: bool := + + let a := Mk_PTE_Bits p in + andb (eq_vec (_get_PTE_Bits_R a) ((bool_to_bits false) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_W a) ((bool_to_bits false) : mword 1)) + (eq_vec (_get_PTE_Bits_X a) ((bool_to_bits false) : mword 1))). + +Definition isInvalidPTE (p : mword 8) +: bool := + + let a := Mk_PTE_Bits p in + orb (eq_vec (_get_PTE_Bits_V a) ((bool_to_bits false) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_W a) ((bool_to_bits true) : mword 1)) + (eq_vec (_get_PTE_Bits_R a) ((bool_to_bits false) : mword 1))). + +Definition checkPTEPermission +(ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (p : PTE_Bits) +: M (bool) := + + (match (ac, priv) with + | (Read, User) => + returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1)) + (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr))) + : bool) + | (Write, User) => + returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1)) + (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1))) + : bool) + | (ReadWrite, User) => + returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1)) + (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr)))) + : bool) + | (Execute, User) => + returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits true) : mword 1)) + (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1))) + : bool) + | (Read, Supervisor) => + returnm ((andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum) + (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr))) + : bool) + | (Write, Supervisor) => + returnm ((andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum) + (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1))) + : bool) + | (ReadWrite, Supervisor) => + returnm ((andb (orb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) do_sum) + (andb (eq_vec (_get_PTE_Bits_W p) ((bool_to_bits true) : mword 1)) + (orb (eq_vec (_get_PTE_Bits_R p) ((bool_to_bits true) : mword 1)) + (andb (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1)) mxr)))) + : bool) + | (Execute, Supervisor) => + returnm ((andb (eq_vec (_get_PTE_Bits_U p) ((bool_to_bits false) : mword 1)) + (eq_vec (_get_PTE_Bits_X p) ((bool_to_bits true) : mword 1))) + : bool) + | (_, Machine) => (internal_error "m-mode mem perm check") : M (bool) + end) + : M (bool). + +Definition update_PTE_Bits (p : PTE_Bits) (a : AccessType) +: option PTE_Bits := + + let update_d := + andb + (orb (generic_eq ((accessType_to_str a) : string) ((accessType_to_str Write) : string)) + (generic_eq ((accessType_to_str a) : string) ((accessType_to_str ReadWrite) : string))) + (eq_vec (_get_PTE_Bits_D p) ((bool_to_bits false) : mword 1)) in + let update_a := eq_vec (_get_PTE_Bits_A p) ((bool_to_bits false) : mword 1) in + if ((orb update_d update_a)) then + let np := _update_PTE_Bits_A p ((bool_to_bits true) : mword 1) in + let np := if (update_d) then _update_PTE_Bits_D np ((bool_to_bits true) : mword 1) else np in + Some + (np) + else None. + +Definition PTW_Error_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 4)} +: PTW_Error := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then PTW_Access + else if sumbool_of_bool ((Z.eqb p0_ 1)) then PTW_Invalid_PTE + else if sumbool_of_bool ((Z.eqb p0_ 2)) then PTW_No_Permission + else if sumbool_of_bool ((Z.eqb p0_ 3)) then PTW_Misaligned + else PTW_PTE_Update. + +Definition num_of_PTW_Error (arg_ : PTW_Error) +: {e : Z & ArithFact (0 <= e /\ e <= 4)} := + + build_ex(match arg_ with + | PTW_Access => 0 + | PTW_Invalid_PTE => 1 + | PTW_No_Permission => 2 + | PTW_Misaligned => 3 + | PTW_PTE_Update => 4 + end). + +Definition ptw_error_to_str (e : PTW_Error) +: string := + + match e with + | PTW_Access => "mem-access-error" + | PTW_Invalid_PTE => "invalid-pte" + | PTW_No_Permission => "no-permission" + | PTW_Misaligned => "misaligned-superpage" + | PTW_PTE_Update => "pte-update-needed" + end. + +Definition translationException (a : AccessType) (f : PTW_Error) +: ExceptionType := + + match (a, f) with + | (ReadWrite, PTW_Access) => E_SAMO_Access_Fault + | (ReadWrite, _) => E_SAMO_Page_Fault + | (Read, PTW_Access) => E_Load_Access_Fault + | (Read, _) => E_Load_Page_Fault + | (Write, PTW_Access) => E_SAMO_Access_Fault + | (Write, _) => E_SAMO_Page_Fault + | (Fetch, PTW_Access) => E_Fetch_Access_Fault + | (Fetch, _) => E_Fetch_Page_Fault + end. + +Definition SV39_LEVEL_BITS := 9. +Hint Unfold SV39_LEVEL_BITS : sail. +Definition SV39_LEVELS := 3. +Hint Unfold SV39_LEVELS : sail. +Definition PTE39_LOG_SIZE := 3. +Hint Unfold PTE39_LOG_SIZE : sail. +Definition PTE39_SIZE := 8. +Hint Unfold PTE39_SIZE : sail. +Definition Mk_SV39_Vaddr (v : mword 39) +: SV39_Vaddr := + + {| SV39_Vaddr_SV39_Vaddr_chunk_0 := (subrange_vec_dec v 38 0) |}. + +Definition _get_SV39_Vaddr_bits (v : SV39_Vaddr) +: mword 39 := + + subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0. + +Definition _set_SV39_Vaddr_bits +(r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 39) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_Vaddr_SV39_Vaddr_chunk_0 := + (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0 (subrange_vec_dec v 38 0)) ]} + : SV39_Vaddr in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_Vaddr_bits (v : SV39_Vaddr) (x : mword 39) +: SV39_Vaddr := + + {[ v with + SV39_Vaddr_SV39_Vaddr_chunk_0 := + (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 0 (subrange_vec_dec x 38 0)) ]}. + +Definition _get_SV39_Vaddr_VPNi (v : SV39_Vaddr) +: mword 27 := + + subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12. + +Definition _set_SV39_Vaddr_VPNi +(r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 27) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_Vaddr_SV39_Vaddr_chunk_0 := + (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12 (subrange_vec_dec v 26 0)) ]} + : SV39_Vaddr in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_Vaddr_VPNi (v : SV39_Vaddr) (x : mword 27) +: SV39_Vaddr := + + {[ v with + SV39_Vaddr_SV39_Vaddr_chunk_0 := + (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 38 12 (subrange_vec_dec x 26 0)) ]}. + +Definition _get_SV39_Vaddr_PgOfs (v : SV39_Vaddr) +: mword 12 := + + subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0. + +Definition _set_SV39_Vaddr_PgOfs +(r_ref : register_ref regstate register_value SV39_Vaddr) (v : mword 12) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_Vaddr_SV39_Vaddr_chunk_0 := + (update_subrange_vec_dec r.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]} + : SV39_Vaddr in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_Vaddr_PgOfs (v : SV39_Vaddr) (x : mword 12) +: SV39_Vaddr := + + {[ v with + SV39_Vaddr_SV39_Vaddr_chunk_0 := + (update_subrange_vec_dec v.(SV39_Vaddr_SV39_Vaddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}. + +Definition Mk_SV39_Paddr (v : mword 56) +: SV39_Paddr := + + {| SV39_Paddr_SV39_Paddr_chunk_0 := (subrange_vec_dec v 55 0) |}. + +Definition _get_SV39_Paddr_bits (v : SV39_Paddr) +: mword 56 := + + subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0. + +Definition _set_SV39_Paddr_bits +(r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 56) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_Paddr_SV39_Paddr_chunk_0 := + (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0 (subrange_vec_dec v 55 0)) ]} + : SV39_Paddr in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_Paddr_bits (v : SV39_Paddr) (x : mword 56) +: SV39_Paddr := + + {[ v with + SV39_Paddr_SV39_Paddr_chunk_0 := + (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 0 (subrange_vec_dec x 55 0)) ]}. + +Definition _get_SV39_Paddr_PPNi (v : SV39_Paddr) +: mword 44 := + + subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12. + +Definition _set_SV39_Paddr_PPNi +(r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 44) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_Paddr_SV39_Paddr_chunk_0 := + (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12 (subrange_vec_dec v 43 0)) ]} + : SV39_Paddr in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_Paddr_PPNi (v : SV39_Paddr) (x : mword 44) +: SV39_Paddr := + + {[ v with + SV39_Paddr_SV39_Paddr_chunk_0 := + (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 55 12 (subrange_vec_dec x 43 0)) ]}. + +Definition _get_SV39_Paddr_PgOfs (v : SV39_Paddr) +: mword 12 := + + subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0. + +Definition _set_SV39_Paddr_PgOfs +(r_ref : register_ref regstate register_value SV39_Paddr) (v : mword 12) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_Paddr_SV39_Paddr_chunk_0 := + (update_subrange_vec_dec r.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0 (subrange_vec_dec v 11 0)) ]} + : SV39_Paddr in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_Paddr_PgOfs (v : SV39_Paddr) (x : mword 12) +: SV39_Paddr := + + {[ v with + SV39_Paddr_SV39_Paddr_chunk_0 := + (update_subrange_vec_dec v.(SV39_Paddr_SV39_Paddr_chunk_0) 11 0 (subrange_vec_dec x 11 0)) ]}. + +Definition Mk_SV39_PTE (v : mword 64) +: SV39_PTE := + + {| SV39_PTE_SV39_PTE_chunk_0 := (subrange_vec_dec v 63 0) |}. + +Definition _get_SV39_PTE_bits (v : SV39_PTE) +: mword 64 := + + subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 63 0. + +Definition _set_SV39_PTE_bits (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 64) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 63 0 (subrange_vec_dec v 63 0)) ]} + : SV39_PTE in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_PTE_bits (v : SV39_PTE) (x : mword 64) +: SV39_PTE := + + {[ v with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 63 0 (subrange_vec_dec x 63 0)) ]}. + +Definition _get_SV39_PTE_PPNi (v : SV39_PTE) +: mword 44 := + + subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 53 10. + +Definition _set_SV39_PTE_PPNi (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 44) + +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 53 10 (subrange_vec_dec v 43 0)) ]} + : SV39_PTE in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_PTE_PPNi (v : SV39_PTE) (x : mword 44) +: SV39_PTE := + + {[ v with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 53 10 (subrange_vec_dec x 43 0)) ]}. + +Definition _get_SV39_PTE_RSW (v : SV39_PTE) +: mword 2 := + + subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 9 8. + +Definition _set_SV39_PTE_RSW (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 2) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 9 8 (subrange_vec_dec v 1 0)) ]} + : SV39_PTE in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_PTE_RSW (v : SV39_PTE) (x : mword 2) +: SV39_PTE := + + {[ v with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 9 8 (subrange_vec_dec x 1 0)) ]}. + +Definition _get_SV39_PTE_BITS (v : SV39_PTE) +: mword 8 := + + subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 7 0. + +Definition _set_SV39_PTE_BITS (r_ref : register_ref regstate register_value SV39_PTE) (v : mword 8) +: M (unit) := + + (reg_deref r_ref) >>= fun r => + let r := + {[ r with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec r.(SV39_PTE_SV39_PTE_chunk_0) 7 0 (subrange_vec_dec v 7 0)) ]} + : SV39_PTE in + write_reg r_ref r + : M (unit). + +Definition _update_SV39_PTE_BITS (v : SV39_PTE) (x : mword 8) +: SV39_PTE := + + {[ v with + SV39_PTE_SV39_PTE_chunk_0 := + (update_subrange_vec_dec v.(SV39_PTE_SV39_PTE_chunk_0) 7 0 (subrange_vec_dec x 7 0)) ]}. + +Definition curAsid64 '(tt : unit) +: M (mword 16) := + + ((read_reg satp_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let satp64 := Mk_Satp64 w__0 in + returnm ((_get_Satp64_Asid satp64) + : mword 16). + +Definition curPTB39 '(tt : unit) +: M (mword 56) := + + ((read_reg satp_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let satp64 := Mk_Satp64 w__0 in + returnm ((EXTZ 56 (shiftl (_get_Satp64_PPN satp64) PAGESIZE_BITS)) + : mword 56). + +Fixpoint _rec_walk39 +(vaddr : mword 39) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) +(ptb : mword 56) (level : Z) (global : bool) (_reclimit : Z) `{ArithFact (0 <= level)} +(_acc : Acc (Zwf 0) _reclimit) +{struct _acc} : M (PTW_Result) := + + assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ => + let va := Mk_SV39_Vaddr vaddr in + let pt_ofs : paddr39 := + shiftl + (EXTZ 56 + (subrange_vec_dec (shiftr (_get_SV39_Vaddr_VPNi va) (Z.mul level SV39_LEVEL_BITS)) + (Z.sub SV39_LEVEL_BITS 1) 0)) PTE39_LOG_SIZE in + let pte_addr := add_vec ptb pt_ofs in + (phys_mem_read Data (EXTZ 64 pte_addr) 8 false false false) >>= fun w__0 : MemoryOpResult (mword (8 * 8)) => + (match w__0 with + | MemException (_) => returnm ((PTW_Failure (PTW_Access)) : PTW_Result ) + | MemValue (v) => + let pte := Mk_SV39_PTE v in + let pbits := _get_SV39_PTE_BITS pte in + let pattr := Mk_PTE_Bits pbits in + let is_global := orb global (eq_vec (_get_PTE_Bits_G pattr) ((bool_to_bits true) : mword 1)) in + (if ((isInvalidPTE pbits)) then returnm ((PTW_Failure (PTW_Invalid_PTE)) : PTW_Result ) + else if ((isPTEPtr pbits)) then + (if sumbool_of_bool ((Z.eqb level 0)) then + returnm ((PTW_Failure + (PTW_Invalid_PTE)) + : PTW_Result ) + else + (_rec_walk39 vaddr ac priv mxr do_sum + (EXTZ 56 (shiftl (_get_SV39_PTE_PPNi pte) PAGESIZE_BITS)) _ is_global + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (PTW_Result)) + : M (PTW_Result) + else + (checkPTEPermission ac priv mxr do_sum pattr) >>= fun w__3 : bool => + returnm ((if ((negb w__3)) then PTW_Failure (PTW_No_Permission) + else if sumbool_of_bool ((Z.gtb level 0)) then + let mask := + sub_vec_int + (shiftl + (xor_vec (_get_SV39_PTE_PPNi pte) + (xor_vec (_get_SV39_PTE_PPNi pte) + (EXTZ 44 (vec_of_bits [B1] : mword 1)))) + (Z.mul level SV39_LEVEL_BITS)) 1 in + if ((neq_vec (and_vec (_get_SV39_PTE_PPNi pte) mask) + (EXTZ 44 (vec_of_bits [B0] : mword 1)))) then + PTW_Failure + (PTW_Misaligned) + else + let ppn := + or_vec (_get_SV39_PTE_PPNi pte) + (and_vec (EXTZ 44 (_get_SV39_Vaddr_VPNi va)) mask) in + PTW_Success + ((concat_vec ppn (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex level, is_global)) + else + PTW_Success + ((concat_vec (_get_SV39_PTE_PPNi pte) (_get_SV39_Vaddr_PgOfs va), pte, pte_addr, build_ex level, is_global))) + : PTW_Result)) + : M (PTW_Result) + end) + : M (PTW_Result). + +Definition walk39 +(_arg0 : mword 39) (_arg1 : AccessType) (_arg2 : Privilege) (_arg3 : bool) (_arg4 : bool) +(_arg5 : mword 56) (level : Z) (_arg7 : bool) `{ArithFact (0 <= level)} +: M (PTW_Result) := + + (_rec_walk39 _arg0 _arg1 _arg2 _arg3 _arg4 _arg5 level _arg7 (level : Z) (Zwf_guarded _)) + : M (PTW_Result). + +Definition make_TLB39_Entry +(asid : mword 16) (global : bool) (vAddr : mword 39) (pAddr : mword 56) (pte : SV39_PTE) (level : Z) +(pteAddr : mword 56) `{ArithFact (0 <= level)} +: M (TLB39_Entry) := + + let 'shift := + projT1 (build_ex (Z.add PAGESIZE_BITS (Z.mul level SV39_LEVEL_BITS)) + : {n : Z & ArithFact (n >= 0)}) in + let vAddrMask : vaddr39 := + sub_vec_int + (shiftl (xor_vec vAddr (xor_vec vAddr (EXTZ 39 (vec_of_bits [B1] : mword 1)))) shift) 1 in + let vMatchMask : vaddr39 := not_vec vAddrMask in + ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + returnm (({| TLB39_Entry_asid := asid; + TLB39_Entry_global := global; + TLB39_Entry_pte := pte; + TLB39_Entry_pteAddr := pteAddr; + TLB39_Entry_vAddrMask := vAddrMask; + TLB39_Entry_vMatchMask := vMatchMask; + TLB39_Entry_vAddr := (and_vec vAddr vMatchMask); + TLB39_Entry_pAddr := (shiftl (shiftr pAddr shift) shift); + TLB39_Entry_age := w__0 |}) + : TLB39_Entry). + +Definition lookupTLB39 (asid : mword 16) (vaddr : mword 39) +: M (option ((Z * TLB39_Entry))) := + + read_reg tlb39_ref >>= fun w__0 : option TLB39_Entry => + returnm ((match w__0 with + | None => None + | Some (e) => + if ((andb (orb e.(TLB39_Entry_global) (eq_vec e.(TLB39_Entry_asid) asid)) + (eq_vec e.(TLB39_Entry_vAddr) (and_vec e.(TLB39_Entry_vMatchMask) vaddr)))) + then + Some + ((0, e)) + else None + end) + : option ((Z * TLB39_Entry))). + +Definition addToTLB39 +(asid : mword 16) (vAddr : mword 39) (pAddr : mword 56) (pte : SV39_PTE) (pteAddr : mword 56) +(level : Z) (global : bool) `{ArithFact (0 <= level)} +: M (unit) := + + (make_TLB39_Entry asid global vAddr pAddr pte level pteAddr) >>= fun ent => + write_reg tlb39_ref (Some (ent)) + : M (unit). + +Definition writeTLB39 (idx : Z) (ent : TLB39_Entry) +: M (unit) := + + write_reg tlb39_ref (Some (ent)) + : M (unit). + +Definition flushTLB (asid : option (mword 16)) (addr : option (mword 39)) +: M (unit) := + + read_reg tlb39_ref >>= fun w__0 : option TLB39_Entry => + let ent : option TLB39_Entry := + match (w__0, asid, addr) with + | (None, _, _) => None + | (Some (e), None, None) => None + | (Some (e), None, Some (a)) => + if ((eq_vec e.(TLB39_Entry_vAddr) (and_vec e.(TLB39_Entry_vMatchMask) a))) then None + else Some (e) + | (Some (e), Some (i), None) => + if ((andb (eq_vec e.(TLB39_Entry_asid) i) (negb e.(TLB39_Entry_global)))) then None + else Some (e) + | (Some (e), Some (i), Some (a)) => + if ((andb (eq_vec e.(TLB39_Entry_asid) i) + (andb (eq_vec e.(TLB39_Entry_vAddr) (and_vec a e.(TLB39_Entry_vMatchMask))) + (negb e.(TLB39_Entry_global))))) then + None + else Some (e) + end in + write_reg tlb39_ref ent + : M (unit). + +Definition translate39 +(vAddr : mword 39) (ac : AccessType) (priv : Privilege) (mxr : bool) (do_sum : bool) (level : Z) +`{ArithFact (0 <= level)} +: M (TR39_Result) := + + (curAsid64 tt) >>= fun asid => + (lookupTLB39 asid vAddr) >>= fun w__0 : option ((Z * TLB39_Entry)) => + (match w__0 with + | Some (idx,ent) => + let pteBits := Mk_PTE_Bits (_get_SV39_PTE_BITS ent.(TLB39_Entry_pte)) in + (checkPTEPermission ac priv mxr do_sum pteBits) >>= fun w__1 : bool => + (if ((negb w__1)) then returnm ((TR39_Failure (PTW_No_Permission)) : TR39_Result ) + else + (match (update_PTE_Bits pteBits ac) with + | None => + returnm ((TR39_Address + (or_vec ent.(TLB39_Entry_pAddr) + (EXTZ 56 (and_vec vAddr ent.(TLB39_Entry_vAddrMask))))) + : TR39_Result ) + | Some (pbits) => + (if ((negb (plat_enable_dirty_update tt))) then + returnm ((TR39_Failure + (PTW_PTE_Update)) + : TR39_Result ) + else + let n_ent : TLB39_Entry := ent in + let n_ent := + {[ n_ent with + TLB39_Entry_pte := + (_update_SV39_PTE_BITS ent.(TLB39_Entry_pte) (_get_PTE_Bits_bits pbits)) ]} + : TLB39_Entry in + (writeTLB39 idx n_ent) >> + (checked_mem_write (EXTZ 64 ent.(TLB39_Entry_pteAddr)) 8 + (_get_SV39_PTE_bits ent.(TLB39_Entry_pte))) >>= fun w__2 : MemoryOpResult bool => + (match w__2 with + | MemValue (_) => returnm (tt : unit) + | MemException (e) => + (internal_error "invalid physical address in TLB") : M (unit) + end) >> + returnm ((TR39_Address + (or_vec ent.(TLB39_Entry_pAddr) + (EXTZ 56 (and_vec vAddr ent.(TLB39_Entry_vAddrMask))))) + : TR39_Result)) + : M (TR39_Result) + end) + : M (TR39_Result)) + : M (TR39_Result) + | None => + (curPTB39 tt) >>= fun w__6 : mword 56 => + (walk39 vAddr ac priv mxr do_sum w__6 level false) >>= fun w__7 : PTW_Result => + (match w__7 with + | PTW_Failure (f) => returnm ((TR39_Failure (f)) : TR39_Result ) + | PTW_Success (pAddr,pte,pteAddr,(existT _ level _),global) => + (match (update_PTE_Bits (Mk_PTE_Bits (_get_SV39_PTE_BITS pte)) ac) with + | None => + (addToTLB39 asid vAddr pAddr pte pteAddr level global) >> + returnm ((TR39_Address + (pAddr)) + : TR39_Result ) + | Some (pbits) => + (if ((negb (plat_enable_dirty_update tt))) then + returnm ((TR39_Failure + (PTW_PTE_Update)) + : TR39_Result ) + else + let w_pte : SV39_PTE := _update_SV39_PTE_BITS pte (_get_PTE_Bits_bits pbits) in + (checked_mem_write (EXTZ 64 pteAddr) 8 (_get_SV39_PTE_bits w_pte)) >>= fun w__8 : MemoryOpResult bool => + (match w__8 with + | MemValue (_) => + (addToTLB39 asid vAddr pAddr w_pte pteAddr level global) >> + returnm ((TR39_Address + (pAddr)) + : TR39_Result ) + | MemException (e) => returnm ((TR39_Failure (PTW_Access)) : TR39_Result ) + end) + : M (TR39_Result)) + : M (TR39_Result) + end) + : M (TR39_Result) + end) + : M (TR39_Result) + end) + : M (TR39_Result). + +Definition translationMode (priv : Privilege) +: M (SATPMode) := + + (if ((eq_vec (privLevel_to_bits priv) ((privLevel_to_bits Machine) : mword 2))) then + returnm (Sbare + : SATPMode) + else + read_reg mstatus_ref >>= fun w__0 : Mstatus => + let arch := architecture (_get_Mstatus_SXL w__0) in + (match arch with + | Some (RV64) => + ((read_reg satp_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + let mbits : satp_mode := _get_Satp64_Mode (Mk_Satp64 w__1) in + (match (satpMode_of_bits RV64 mbits) with + | Some (m) => returnm (m : SATPMode) + | None => (internal_error "invalid RV64 translation mode in satp") : M (SATPMode) + end) + : M (SATPMode) + | _ => (internal_error "unsupported address translation arch") : M (SATPMode) + end) + : M (SATPMode)) + : M (SATPMode). + +Definition translateAddr (vAddr : mword 64) (ac : AccessType) (rt : ReadType) +: M (TR_Result) := + + (match rt with + | Instruction => read_reg cur_privilege_ref : M (Privilege) + | Data => + read_reg mstatus_ref >>= fun w__1 : Mstatus => + (if ((eq_vec (_get_Mstatus_MPRV w__1) ((bool_to_bits true) : mword 1))) then + read_reg mstatus_ref >>= fun w__2 : Mstatus => + returnm ((privLevel_of_bits (_get_Mstatus_MPP w__2)) + : Privilege) + else read_reg cur_privilege_ref : M (Privilege)) + : M (Privilege) + end) >>= fun effPriv : Privilege => + read_reg mstatus_ref >>= fun w__5 : Mstatus => + let mxr : bool := eq_vec (_get_Mstatus_MXR w__5) ((bool_to_bits true) : mword 1) in + read_reg mstatus_ref >>= fun w__6 : Mstatus => + let do_sum : bool := eq_vec (_get_Mstatus_SUM w__6) ((bool_to_bits true) : mword 1) in + (translationMode effPriv) >>= fun mode : SATPMode => + (match mode with + | Sbare => returnm ((TR_Address (vAddr)) : TR_Result ) + | SV39 => + (translate39 (subrange_vec_dec vAddr 38 0) ac effPriv mxr do_sum (Z.sub SV39_LEVELS 1)) >>= fun w__7 : TR39_Result => + returnm ((match w__7 with + | TR39_Address (pa) => TR_Address (EXTZ 64 pa) + | TR39_Failure (f) => TR_Failure (translationException ac f) + end) + : TR_Result) + end) + : M (TR_Result). + +Definition encdec_uop_forwards (arg_ : uop) +: mword 7 := + + match arg_ with + | RISCV_LUI => (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7) + | RISCV_AUIPC => (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : mword 7) + end. + +Definition encdec_uop_backwards (arg_ : mword 7) +: uop := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7))) then RISCV_LUI + else RISCV_AUIPC. + +Definition encdec_uop_forwards_matches (arg_ : uop) +: bool := + + match arg_ with | RISCV_LUI => true | RISCV_AUIPC => true end. + +Definition encdec_uop_backwards_matches (arg_ : mword 7) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B0;B1;B1;B1] : mword 7))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B0;B1;B1;B1] : mword 7))) then true + else false. + +Definition utype_mnemonic_forwards (arg_ : uop) +: string := + + match arg_ with | RISCV_LUI => "lui" | RISCV_AUIPC => "auipc" end. + +Definition utype_mnemonic_backwards (arg_ : string) +: uop := + + let p0_ := arg_ in + if ((generic_eq p0_ "lui")) then RISCV_LUI + else RISCV_AUIPC. + +Definition utype_mnemonic_forwards_matches (arg_ : uop) +: bool := + + match arg_ with | RISCV_LUI => true | RISCV_AUIPC => true end. + +Definition utype_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "lui")) then true + else if ((generic_eq p0_ "auipc")) then true + else false. + +Definition _s496_ (_s497_ : string) +: option string := + + let _s498_ := _s497_ in + if ((string_startswith _s498_ "auipc")) then + match (string_drop _s498_ (projT1 (string_length "auipc"))) with | s_ => Some (s_) end + else None. + +Definition _s492_ (_s493_ : string) +: option string := + + let _s494_ := _s493_ in + if ((string_startswith _s494_ "lui")) then + match (string_drop _s494_ (projT1 (string_length "lui"))) with | s_ => Some (s_) end + else None. + +Definition utype_mnemonic_matches_prefix (arg_ : string) +: M (option ((uop * {n : Z & ArithFact (n >= 0)}))) := + + let _s495_ := arg_ in + (if ((match (_s492_ _s495_) with | Some (s_) => true | _ => false end)) then + (match (_s492_ _s495_) with + | Some (s_) => + returnm ((Some + ((RISCV_LUI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((uop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((uop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((uop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s496_ _s495_) with | Some (s_) => true | _ => false end)) then + (match (_s496_ _s495_) with + | Some (s_) => + returnm ((Some + ((RISCV_AUIPC, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((uop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((uop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((uop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((uop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((uop * {n : Z & ArithFact (n >= 0)}))). + +Definition encdec_bop_forwards (arg_ : bop) +: mword 3 := + + match arg_ with + | RISCV_BEQ => (vec_of_bits [B0;B0;B0] : mword 3) + | RISCV_BNE => (vec_of_bits [B0;B0;B1] : mword 3) + | RISCV_BLT => (vec_of_bits [B1;B0;B0] : mword 3) + | RISCV_BGE => (vec_of_bits [B1;B0;B1] : mword 3) + | RISCV_BLTU => (vec_of_bits [B1;B1;B0] : mword 3) + | RISCV_BGEU => (vec_of_bits [B1;B1;B1] : mword 3) + end. + +Definition encdec_bop_backwards (arg_ : mword 3) +: bop := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then RISCV_BEQ + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then RISCV_BNE + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then RISCV_BLT + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then RISCV_BGE + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then RISCV_BLTU + else RISCV_BGEU. + +Definition encdec_bop_forwards_matches (arg_ : bop) +: bool := + + match arg_ with + | RISCV_BEQ => true + | RISCV_BNE => true + | RISCV_BLT => true + | RISCV_BGE => true + | RISCV_BLTU => true + | RISCV_BGEU => true + end. + +Definition encdec_bop_backwards_matches (arg_ : mword 3) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true + else false. + +Definition btype_mnemonic_forwards (arg_ : bop) +: string := + + match arg_ with + | RISCV_BEQ => "beq" + | RISCV_BNE => "bne" + | RISCV_BLT => "blt" + | RISCV_BGE => "bge" + | RISCV_BLTU => "bltu" + | RISCV_BGEU => "bgeu" + end. + +Definition btype_mnemonic_backwards (arg_ : string) +: bop := + + let p0_ := arg_ in + if ((generic_eq p0_ "beq")) then RISCV_BEQ + else if ((generic_eq p0_ "bne")) then RISCV_BNE + else if ((generic_eq p0_ "blt")) then RISCV_BLT + else if ((generic_eq p0_ "bge")) then RISCV_BGE + else if ((generic_eq p0_ "bltu")) then RISCV_BLTU + else RISCV_BGEU. + +Definition btype_mnemonic_forwards_matches (arg_ : bop) +: bool := + + match arg_ with + | RISCV_BEQ => true + | RISCV_BNE => true + | RISCV_BLT => true + | RISCV_BGE => true + | RISCV_BLTU => true + | RISCV_BGEU => true + end. + +Definition btype_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "beq")) then true + else if ((generic_eq p0_ "bne")) then true + else if ((generic_eq p0_ "blt")) then true + else if ((generic_eq p0_ "bge")) then true + else if ((generic_eq p0_ "bltu")) then true + else if ((generic_eq p0_ "bgeu")) then true + else false. + +Definition _s520_ (_s521_ : string) +: option string := + + let _s522_ := _s521_ in + if ((string_startswith _s522_ "bgeu")) then + match (string_drop _s522_ (projT1 (string_length "bgeu"))) with | s_ => Some (s_) end + else None. + +Definition _s516_ (_s517_ : string) +: option string := + + let _s518_ := _s517_ in + if ((string_startswith _s518_ "bltu")) then + match (string_drop _s518_ (projT1 (string_length "bltu"))) with | s_ => Some (s_) end + else None. + +Definition _s512_ (_s513_ : string) +: option string := + + let _s514_ := _s513_ in + if ((string_startswith _s514_ "bge")) then + match (string_drop _s514_ (projT1 (string_length "bge"))) with | s_ => Some (s_) end + else None. + +Definition _s508_ (_s509_ : string) +: option string := + + let _s510_ := _s509_ in + if ((string_startswith _s510_ "blt")) then + match (string_drop _s510_ (projT1 (string_length "blt"))) with | s_ => Some (s_) end + else None. + +Definition _s504_ (_s505_ : string) +: option string := + + let _s506_ := _s505_ in + if ((string_startswith _s506_ "bne")) then + match (string_drop _s506_ (projT1 (string_length "bne"))) with | s_ => Some (s_) end + else None. + +Definition _s500_ (_s501_ : string) +: option string := + + let _s502_ := _s501_ in + if ((string_startswith _s502_ "beq")) then + match (string_drop _s502_ (projT1 (string_length "beq"))) with | s_ => Some (s_) end + else None. + +Definition btype_mnemonic_matches_prefix (arg_ : string) +: M (option ((bop * {n : Z & ArithFact (n >= 0)}))) := + + let _s503_ := arg_ in + (if ((match (_s500_ _s503_) with | Some (s_) => true | _ => false end)) then + (match (_s500_ _s503_) with + | Some (s_) => + returnm ((Some + ((RISCV_BEQ, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s504_ _s503_) with | Some (s_) => true | _ => false end)) then + (match (_s504_ _s503_) with + | Some (s_) => + returnm ((Some + ((RISCV_BNE, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s508_ _s503_) with | Some (s_) => true | _ => false end)) then + (match (_s508_ _s503_) with + | Some (s_) => + returnm ((Some + ((RISCV_BLT, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s512_ _s503_) with | Some (s_) => true | _ => false end)) then + (match (_s512_ _s503_) with + | Some (s_) => + returnm ((Some + ((RISCV_BGE, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s516_ _s503_) with | Some (s_) => true | _ => false end)) then + (match (_s516_ _s503_) with + | Some (s_) => + returnm ((Some + ((RISCV_BLTU, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s520_ _s503_) with | Some (s_) => true | _ => false end)) then + (match (_s520_ _s503_) with + | Some (s_) => + returnm ((Some + ((RISCV_BGEU, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((bop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((bop * {n : Z & ArithFact (n >= 0)}))). + +Definition encdec_iop_forwards (arg_ : iop) +: mword 3 := + + match arg_ with + | RISCV_ADDI => (vec_of_bits [B0;B0;B0] : mword 3) + | RISCV_SLTI => (vec_of_bits [B0;B1;B0] : mword 3) + | RISCV_SLTIU => (vec_of_bits [B0;B1;B1] : mword 3) + | RISCV_XORI => (vec_of_bits [B1;B0;B0] : mword 3) + | RISCV_ORI => (vec_of_bits [B1;B1;B0] : mword 3) + | RISCV_ANDI => (vec_of_bits [B1;B1;B1] : mword 3) + end. + +Definition encdec_iop_backwards (arg_ : mword 3) +: iop := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then RISCV_ADDI + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then RISCV_SLTI + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then RISCV_SLTIU + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then RISCV_XORI + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then RISCV_ORI + else RISCV_ANDI. + +Definition encdec_iop_forwards_matches (arg_ : iop) +: bool := + + match arg_ with + | RISCV_ADDI => true + | RISCV_SLTI => true + | RISCV_SLTIU => true + | RISCV_XORI => true + | RISCV_ORI => true + | RISCV_ANDI => true + end. + +Definition encdec_iop_backwards_matches (arg_ : mword 3) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1] : mword 3))) then true + else false. + +Definition itype_mnemonic_forwards (arg_ : iop) +: string := + + match arg_ with + | RISCV_ADDI => "addi" + | RISCV_SLTI => "slti" + | RISCV_SLTIU => "sltiu" + | RISCV_XORI => "xori" + | RISCV_ORI => "ori" + | RISCV_ANDI => "andi" + end. + +Definition itype_mnemonic_backwards (arg_ : string) +: iop := + + let p0_ := arg_ in + if ((generic_eq p0_ "addi")) then RISCV_ADDI + else if ((generic_eq p0_ "slti")) then RISCV_SLTI + else if ((generic_eq p0_ "sltiu")) then RISCV_SLTIU + else if ((generic_eq p0_ "xori")) then RISCV_XORI + else if ((generic_eq p0_ "ori")) then RISCV_ORI + else RISCV_ANDI. + +Definition itype_mnemonic_forwards_matches (arg_ : iop) +: bool := + + match arg_ with + | RISCV_ADDI => true + | RISCV_SLTI => true + | RISCV_SLTIU => true + | RISCV_XORI => true + | RISCV_ORI => true + | RISCV_ANDI => true + end. + +Definition itype_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "addi")) then true + else if ((generic_eq p0_ "slti")) then true + else if ((generic_eq p0_ "sltiu")) then true + else if ((generic_eq p0_ "xori")) then true + else if ((generic_eq p0_ "ori")) then true + else if ((generic_eq p0_ "andi")) then true + else false. + +Definition _s544_ (_s545_ : string) +: option string := + + let _s546_ := _s545_ in + if ((string_startswith _s546_ "andi")) then + match (string_drop _s546_ (projT1 (string_length "andi"))) with | s_ => Some (s_) end + else None. + +Definition _s540_ (_s541_ : string) +: option string := + + let _s542_ := _s541_ in + if ((string_startswith _s542_ "ori")) then + match (string_drop _s542_ (projT1 (string_length "ori"))) with | s_ => Some (s_) end + else None. + +Definition _s536_ (_s537_ : string) +: option string := + + let _s538_ := _s537_ in + if ((string_startswith _s538_ "xori")) then + match (string_drop _s538_ (projT1 (string_length "xori"))) with | s_ => Some (s_) end + else None. + +Definition _s532_ (_s533_ : string) +: option string := + + let _s534_ := _s533_ in + if ((string_startswith _s534_ "sltiu")) then + match (string_drop _s534_ (projT1 (string_length "sltiu"))) with | s_ => Some (s_) end + else None. + +Definition _s528_ (_s529_ : string) +: option string := + + let _s530_ := _s529_ in + if ((string_startswith _s530_ "slti")) then + match (string_drop _s530_ (projT1 (string_length "slti"))) with | s_ => Some (s_) end + else None. + +Definition _s524_ (_s525_ : string) +: option string := + + let _s526_ := _s525_ in + if ((string_startswith _s526_ "addi")) then + match (string_drop _s526_ (projT1 (string_length "addi"))) with | s_ => Some (s_) end + else None. + +Definition itype_mnemonic_matches_prefix (arg_ : string) +: M (option ((iop * {n : Z & ArithFact (n >= 0)}))) := + + let _s527_ := arg_ in + (if ((match (_s524_ _s527_) with | Some (s_) => true | _ => false end)) then + (match (_s524_ _s527_) with + | Some (s_) => + returnm ((Some + ((RISCV_ADDI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((iop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s528_ _s527_) with | Some (s_) => true | _ => false end)) then + (match (_s528_ _s527_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLTI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((iop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s532_ _s527_) with | Some (s_) => true | _ => false end)) then + (match (_s532_ _s527_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLTIU, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((iop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s536_ _s527_) with | Some (s_) => true | _ => false end)) then + (match (_s536_ _s527_) with + | Some (s_) => + returnm ((Some + ((RISCV_XORI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((iop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s540_ _s527_) with | Some (s_) => true | _ => false end)) then + (match (_s540_ _s527_) with + | Some (s_) => + returnm ((Some + ((RISCV_ORI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((iop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s544_ _s527_) with | Some (s_) => true | _ => false end)) then + (match (_s544_ _s527_) with + | Some (s_) => + returnm ((Some + ((RISCV_ANDI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((iop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((iop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((iop * {n : Z & ArithFact (n >= 0)}))). + +Definition encdec_sop_forwards (arg_ : sop) +: mword 3 := + + match arg_ with + | RISCV_SLLI => (vec_of_bits [B0;B0;B1] : mword 3) + | RISCV_SRLI => (vec_of_bits [B1;B0;B1] : mword 3) + | RISCV_SRAI => (vec_of_bits [B1;B0;B1] : mword 3) + end. + +Definition encdec_sop_backwards (arg_ : mword 3) +: sop := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then RISCV_SLLI + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then RISCV_SRLI + else RISCV_SRAI. + +Definition encdec_sop_forwards_matches (arg_ : sop) +: bool := + + match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end. + +Definition encdec_sop_backwards_matches (arg_ : mword 3) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0;B1] : mword 3))) then true + else false. + +Definition shiftiop_mnemonic_forwards (arg_ : sop) +: string := + + match arg_ with | RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" end. + +Definition shiftiop_mnemonic_backwards (arg_ : string) +: sop := + + let p0_ := arg_ in + if ((generic_eq p0_ "slli")) then RISCV_SLLI + else if ((generic_eq p0_ "srli")) then RISCV_SRLI + else RISCV_SRAI. + +Definition shiftiop_mnemonic_forwards_matches (arg_ : sop) +: bool := + + match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end. + +Definition shiftiop_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "slli")) then true + else if ((generic_eq p0_ "srli")) then true + else if ((generic_eq p0_ "srai")) then true + else false. + +Definition _s556_ (_s557_ : string) +: option string := + + let _s558_ := _s557_ in + if ((string_startswith _s558_ "srai")) then + match (string_drop _s558_ (projT1 (string_length "srai"))) with | s_ => Some (s_) end + else None. + +Definition _s552_ (_s553_ : string) +: option string := + + let _s554_ := _s553_ in + if ((string_startswith _s554_ "srli")) then + match (string_drop _s554_ (projT1 (string_length "srli"))) with | s_ => Some (s_) end + else None. + +Definition _s548_ (_s549_ : string) +: option string := + + let _s550_ := _s549_ in + if ((string_startswith _s550_ "slli")) then + match (string_drop _s550_ (projT1 (string_length "slli"))) with | s_ => Some (s_) end + else None. + +Definition shiftiop_mnemonic_matches_prefix (arg_ : string) +: M (option ((sop * {n : Z & ArithFact (n >= 0)}))) := + + let _s551_ := arg_ in + (if ((match (_s548_ _s551_) with | Some (s_) => true | _ => false end)) then + (match (_s548_ _s551_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLLI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s552_ _s551_) with | Some (s_) => true | _ => false end)) then + (match (_s552_ _s551_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRLI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s556_ _s551_) with | Some (s_) => true | _ => false end)) then + (match (_s556_ _s551_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRAI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((sop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))). + +Definition rtype_mnemonic_forwards (arg_ : rop) +: string := + + match arg_ with + | RISCV_ADD => "add" + | RISCV_SUB => "sub" + | RISCV_SLL => "sll" + | RISCV_SLT => "slt" + | RISCV_SLTU => "sltu" + | RISCV_XOR => "xor" + | RISCV_SRL => "srl" + | RISCV_SRA => "sra" + | RISCV_OR => "or" + | RISCV_AND => "and" + end. + +Definition rtype_mnemonic_backwards (arg_ : string) +: rop := + + let p0_ := arg_ in + if ((generic_eq p0_ "add")) then RISCV_ADD + else if ((generic_eq p0_ "sub")) then RISCV_SUB + else if ((generic_eq p0_ "sll")) then RISCV_SLL + else if ((generic_eq p0_ "slt")) then RISCV_SLT + else if ((generic_eq p0_ "sltu")) then RISCV_SLTU + else if ((generic_eq p0_ "xor")) then RISCV_XOR + else if ((generic_eq p0_ "srl")) then RISCV_SRL + else if ((generic_eq p0_ "sra")) then RISCV_SRA + else if ((generic_eq p0_ "or")) then RISCV_OR + else RISCV_AND. + +Definition rtype_mnemonic_forwards_matches (arg_ : rop) +: bool := + + match arg_ with + | RISCV_ADD => true + | RISCV_SUB => true + | RISCV_SLL => true + | RISCV_SLT => true + | RISCV_SLTU => true + | RISCV_XOR => true + | RISCV_SRL => true + | RISCV_SRA => true + | RISCV_OR => true + | RISCV_AND => true + end. + +Definition rtype_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "add")) then true + else if ((generic_eq p0_ "sub")) then true + else if ((generic_eq p0_ "sll")) then true + else if ((generic_eq p0_ "slt")) then true + else if ((generic_eq p0_ "sltu")) then true + else if ((generic_eq p0_ "xor")) then true + else if ((generic_eq p0_ "srl")) then true + else if ((generic_eq p0_ "sra")) then true + else if ((generic_eq p0_ "or")) then true + else if ((generic_eq p0_ "and")) then true + else false. + +Definition _s596_ (_s597_ : string) +: option string := + + let _s598_ := _s597_ in + if ((string_startswith _s598_ "and")) then + match (string_drop _s598_ (projT1 (string_length "and"))) with | s_ => Some (s_) end + else None. + +Definition _s592_ (_s593_ : string) +: option string := + + let _s594_ := _s593_ in + if ((string_startswith _s594_ "or")) then + match (string_drop _s594_ (projT1 (string_length "or"))) with | s_ => Some (s_) end + else None. + +Definition _s588_ (_s589_ : string) +: option string := + + let _s590_ := _s589_ in + if ((string_startswith _s590_ "sra")) then + match (string_drop _s590_ (projT1 (string_length "sra"))) with | s_ => Some (s_) end + else None. + +Definition _s584_ (_s585_ : string) +: option string := + + let _s586_ := _s585_ in + if ((string_startswith _s586_ "srl")) then + match (string_drop _s586_ (projT1 (string_length "srl"))) with | s_ => Some (s_) end + else None. + +Definition _s580_ (_s581_ : string) +: option string := + + let _s582_ := _s581_ in + if ((string_startswith _s582_ "xor")) then + match (string_drop _s582_ (projT1 (string_length "xor"))) with | s_ => Some (s_) end + else None. + +Definition _s576_ (_s577_ : string) +: option string := + + let _s578_ := _s577_ in + if ((string_startswith _s578_ "sltu")) then + match (string_drop _s578_ (projT1 (string_length "sltu"))) with | s_ => Some (s_) end + else None. + +Definition _s572_ (_s573_ : string) +: option string := + + let _s574_ := _s573_ in + if ((string_startswith _s574_ "slt")) then + match (string_drop _s574_ (projT1 (string_length "slt"))) with | s_ => Some (s_) end + else None. + +Definition _s568_ (_s569_ : string) +: option string := + + let _s570_ := _s569_ in + if ((string_startswith _s570_ "sll")) then + match (string_drop _s570_ (projT1 (string_length "sll"))) with | s_ => Some (s_) end + else None. + +Definition _s564_ (_s565_ : string) +: option string := + + let _s566_ := _s565_ in + if ((string_startswith _s566_ "sub")) then + match (string_drop _s566_ (projT1 (string_length "sub"))) with | s_ => Some (s_) end + else None. + +Definition _s560_ (_s561_ : string) +: option string := + + let _s562_ := _s561_ in + if ((string_startswith _s562_ "add")) then + match (string_drop _s562_ (projT1 (string_length "add"))) with | s_ => Some (s_) end + else None. + +Definition rtype_mnemonic_matches_prefix (arg_ : string) +: M (option ((rop * {n : Z & ArithFact (n >= 0)}))) := + + let _s563_ := arg_ in + (if ((match (_s560_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s560_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_ADD, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s564_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s564_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_SUB, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s568_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s568_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLL, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s572_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s572_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLT, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s576_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s576_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLTU, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s580_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s580_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_XOR, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s584_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s584_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRL, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s588_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s588_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRA, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s592_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s592_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_OR, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s596_ _s563_) with | Some (s_) => true | _ => false end)) then + (match (_s596_ _s563_) with + | Some (s_) => + returnm ((Some + ((RISCV_AND, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((rop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((rop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((rop * {n : Z & ArithFact (n >= 0)}))). + +Definition extend_value {n : Z} (is_unsigned : bool) (value : MemoryOpResult (mword (8 * n))) +`{ArithFact ((0 + 1) <= n /\ n <= 8)} +: MemoryOpResult (mword 64) := + + match value with + | MemValue (v) => MemValue (if (is_unsigned) then EXTZ 64 v else (EXTS 64 v) : xlenbits) + | MemException (e) => MemException (e) + end. + +Definition process_load {n : Z} +(rd : mword 5) (addr : mword 64) (value : MemoryOpResult (mword (8 * n))) (is_unsigned : bool) +`{ArithFact ((0 + 1) <= n /\ n <= 8)} +: M (bool) := + + (match (extend_value is_unsigned value) with + | MemValue (result) => (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool) + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + end) + : M (bool). + +Definition check_misaligned (vaddr : mword 64) (width : word_width) +: M (bool) := + + (if ((plat_enable_misaligned_access tt)) then returnm (false : bool) + else + (match width with + | BYTE => returnm (false : bool) + | HALF => + (bit_to_bool (access_vec_dec vaddr 0)) >>= fun w__0 : bool => + returnm ((Bool.eqb (w__0 : bool) true) + : bool) + | WORD => + (or_boolM + ((bit_to_bool (access_vec_dec vaddr 0)) >>= fun w__1 : bool => + returnm ((Bool.eqb (w__1 : bool) true) + : bool)) + ((bit_to_bool (access_vec_dec vaddr 1)) >>= fun w__2 : bool => + returnm ((Bool.eqb (w__2 : bool) true) + : bool))) + : M (bool) + | DOUBLE => + (or_boolM + ((bit_to_bool (access_vec_dec vaddr 0)) >>= fun w__4 : bool => + returnm ((Bool.eqb (w__4 : bool) true) + : bool)) + ((or_boolM + ((bit_to_bool (access_vec_dec vaddr 1)) >>= fun w__5 : bool => + returnm ((Bool.eqb (w__5 : bool) true) + : bool)) + ((bit_to_bool (access_vec_dec vaddr 2)) >>= fun w__6 : bool => + returnm ((Bool.eqb (w__6 : bool) true) + : bool))) + : M (bool))) + : M (bool) + end) + : M (bool)) + : M (bool). + +Definition maybe_aq_forwards (arg_ : bool) +: string := + + match arg_ with | true => ".aq" | false => "" end. + +Definition maybe_aq_backwards (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ ".aq")) then true + else false. + +Definition maybe_aq_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | true => true | false => true end. + +Definition maybe_aq_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ ".aq")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s604_ (_s605_ : string) +: option string := + + let _s606_ := _s605_ in + if ((string_startswith _s606_ "")) then + match (string_drop _s606_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s600_ (_s601_ : string) +: option string := + + let _s602_ := _s601_ in + if ((string_startswith _s602_ ".aq")) then + match (string_drop _s602_ (projT1 (string_length ".aq"))) with | s_ => Some (s_) end + else None. + +Definition maybe_aq_matches_prefix (arg_ : string) +: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) := + + let _s603_ := arg_ in + (if ((match (_s600_ _s603_) with | Some (s_) => true | _ => false end)) then + (match (_s600_ _s603_) with + | Some (s_) => + returnm ((Some + ((true, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s604_ _s603_) with | Some (s_) => true | _ => false end)) then + (match (_s604_ _s603_) with + | Some (s_) => + returnm ((Some + ((false, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)})))) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))). + +Definition maybe_rl_forwards (arg_ : bool) +: string := + + match arg_ with | true => ".rl" | false => "" end. + +Definition maybe_rl_backwards (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ ".rl")) then true + else false. + +Definition maybe_rl_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | true => true | false => true end. + +Definition maybe_rl_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ ".rl")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s612_ (_s613_ : string) +: option string := + + let _s614_ := _s613_ in + if ((string_startswith _s614_ "")) then + match (string_drop _s614_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s608_ (_s609_ : string) +: option string := + + let _s610_ := _s609_ in + if ((string_startswith _s610_ ".rl")) then + match (string_drop _s610_ (projT1 (string_length ".rl"))) with | s_ => Some (s_) end + else None. + +Definition maybe_rl_matches_prefix (arg_ : string) +: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) := + + let _s611_ := arg_ in + (if ((match (_s608_ _s611_) with | Some (s_) => true | _ => false end)) then + (match (_s608_ _s611_) with + | Some (s_) => + returnm ((Some + ((true, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s612_ _s611_) with | Some (s_) => true | _ => false end)) then + (match (_s612_ _s611_) with + | Some (s_) => + returnm ((Some + ((false, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)})))) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))). + +Definition maybe_u_forwards (arg_ : bool) +: string := + + match arg_ with | true => "u" | false => "" end. + +Definition maybe_u_backwards (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "u")) then true + else false. + +Definition maybe_u_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | true => true | false => true end. + +Definition maybe_u_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "u")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s620_ (_s621_ : string) +: option string := + + let _s622_ := _s621_ in + if ((string_startswith _s622_ "")) then + match (string_drop _s622_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s616_ (_s617_ : string) +: option string := + + let _s618_ := _s617_ in + if ((string_startswith _s618_ "u")) then + match (string_drop _s618_ (projT1 (string_length "u"))) with | s_ => Some (s_) end + else None. + +Definition maybe_u_matches_prefix (arg_ : string) +: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) := + + let _s619_ := arg_ in + (if ((match (_s616_ _s619_) with | Some (s_) => true | _ => false end)) then + (match (_s616_ _s619_) with + | Some (s_) => + returnm ((Some + ((true, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s620_ _s619_) with | Some (s_) => true | _ => false end)) then + (match (_s620_ _s619_) with + | Some (s_) => + returnm ((Some + ((false, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)})))) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))). + +Definition shiftw_mnemonic_forwards (arg_ : sop) +: string := + + match arg_ with | RISCV_SLLI => "slli" | RISCV_SRLI => "srli" | RISCV_SRAI => "srai" end. + +Definition shiftw_mnemonic_backwards (arg_ : string) +: sop := + + let p0_ := arg_ in + if ((generic_eq p0_ "slli")) then RISCV_SLLI + else if ((generic_eq p0_ "srli")) then RISCV_SRLI + else RISCV_SRAI. + +Definition shiftw_mnemonic_forwards_matches (arg_ : sop) +: bool := + + match arg_ with | RISCV_SLLI => true | RISCV_SRLI => true | RISCV_SRAI => true end. + +Definition shiftw_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "slli")) then true + else if ((generic_eq p0_ "srli")) then true + else if ((generic_eq p0_ "srai")) then true + else false. + +Definition _s632_ (_s633_ : string) +: option string := + + let _s634_ := _s633_ in + if ((string_startswith _s634_ "srai")) then + match (string_drop _s634_ (projT1 (string_length "srai"))) with | s_ => Some (s_) end + else None. + +Definition _s628_ (_s629_ : string) +: option string := + + let _s630_ := _s629_ in + if ((string_startswith _s630_ "srli")) then + match (string_drop _s630_ (projT1 (string_length "srli"))) with | s_ => Some (s_) end + else None. + +Definition _s624_ (_s625_ : string) +: option string := + + let _s626_ := _s625_ in + if ((string_startswith _s626_ "slli")) then + match (string_drop _s626_ (projT1 (string_length "slli"))) with | s_ => Some (s_) end + else None. + +Definition shiftw_mnemonic_matches_prefix (arg_ : string) +: M (option ((sop * {n : Z & ArithFact (n >= 0)}))) := + + let _s627_ := arg_ in + (if ((match (_s624_ _s627_) with | Some (s_) => true | _ => false end)) then + (match (_s624_ _s627_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLLI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s628_ _s627_) with | Some (s_) => true | _ => false end)) then + (match (_s628_ _s627_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRLI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s632_ _s627_) with | Some (s_) => true | _ => false end)) then + (match (_s632_ _s627_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRAI, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((sop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((sop * {n : Z & ArithFact (n >= 0)}))). + +Definition rtypew_mnemonic_forwards (arg_ : ropw) +: string := + + match arg_ with + | RISCV_ADDW => "addw" + | RISCV_SUBW => "subw" + | RISCV_SLLW => "sllw" + | RISCV_SRLW => "srlw" + | RISCV_SRAW => "sraw" + end. + +Definition rtypew_mnemonic_backwards (arg_ : string) +: ropw := + + let p0_ := arg_ in + if ((generic_eq p0_ "addw")) then RISCV_ADDW + else if ((generic_eq p0_ "subw")) then RISCV_SUBW + else if ((generic_eq p0_ "sllw")) then RISCV_SLLW + else if ((generic_eq p0_ "srlw")) then RISCV_SRLW + else RISCV_SRAW. + +Definition rtypew_mnemonic_forwards_matches (arg_ : ropw) +: bool := + + match arg_ with + | RISCV_ADDW => true + | RISCV_SUBW => true + | RISCV_SLLW => true + | RISCV_SRLW => true + | RISCV_SRAW => true + end. + +Definition rtypew_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "addw")) then true + else if ((generic_eq p0_ "subw")) then true + else if ((generic_eq p0_ "sllw")) then true + else if ((generic_eq p0_ "srlw")) then true + else if ((generic_eq p0_ "sraw")) then true + else false. + +Definition _s652_ (_s653_ : string) +: option string := + + let _s654_ := _s653_ in + if ((string_startswith _s654_ "sraw")) then + match (string_drop _s654_ (projT1 (string_length "sraw"))) with | s_ => Some (s_) end + else None. + +Definition _s648_ (_s649_ : string) +: option string := + + let _s650_ := _s649_ in + if ((string_startswith _s650_ "srlw")) then + match (string_drop _s650_ (projT1 (string_length "srlw"))) with | s_ => Some (s_) end + else None. + +Definition _s644_ (_s645_ : string) +: option string := + + let _s646_ := _s645_ in + if ((string_startswith _s646_ "sllw")) then + match (string_drop _s646_ (projT1 (string_length "sllw"))) with | s_ => Some (s_) end + else None. + +Definition _s640_ (_s641_ : string) +: option string := + + let _s642_ := _s641_ in + if ((string_startswith _s642_ "subw")) then + match (string_drop _s642_ (projT1 (string_length "subw"))) with | s_ => Some (s_) end + else None. + +Definition _s636_ (_s637_ : string) +: option string := + + let _s638_ := _s637_ in + if ((string_startswith _s638_ "addw")) then + match (string_drop _s638_ (projT1 (string_length "addw"))) with | s_ => Some (s_) end + else None. + +Definition rtypew_mnemonic_matches_prefix (arg_ : string) +: M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) := + + let _s639_ := arg_ in + (if ((match (_s636_ _s639_) with | Some (s_) => true | _ => false end)) then + (match (_s636_ _s639_) with + | Some (s_) => + returnm ((Some + ((RISCV_ADDW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ropw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s640_ _s639_) with | Some (s_) => true | _ => false end)) then + (match (_s640_ _s639_) with + | Some (s_) => + returnm ((Some + ((RISCV_SUBW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ropw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s644_ _s639_) with | Some (s_) => true | _ => false end)) then + (match (_s644_ _s639_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLLW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ropw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s648_ _s639_) with | Some (s_) => true | _ => false end)) then + (match (_s648_ _s639_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRLW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ropw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s652_ _s639_) with | Some (s_) => true | _ => false end)) then + (match (_s652_ _s639_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRAW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ropw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((ropw * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ropw * {n : Z & ArithFact (n >= 0)}))). + +Definition shiftiwop_mnemonic_forwards (arg_ : sopw) +: string := + + match arg_ with | RISCV_SLLIW => "slliw" | RISCV_SRLIW => "srliw" | RISCV_SRAIW => "sraiw" end. + +Definition shiftiwop_mnemonic_backwards (arg_ : string) +: sopw := + + let p0_ := arg_ in + if ((generic_eq p0_ "slliw")) then RISCV_SLLIW + else if ((generic_eq p0_ "srliw")) then RISCV_SRLIW + else RISCV_SRAIW. + +Definition shiftiwop_mnemonic_forwards_matches (arg_ : sopw) +: bool := + + match arg_ with | RISCV_SLLIW => true | RISCV_SRLIW => true | RISCV_SRAIW => true end. + +Definition shiftiwop_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "slliw")) then true + else if ((generic_eq p0_ "srliw")) then true + else if ((generic_eq p0_ "sraiw")) then true + else false. + +Definition _s664_ (_s665_ : string) +: option string := + + let _s666_ := _s665_ in + if ((string_startswith _s666_ "sraiw")) then + match (string_drop _s666_ (projT1 (string_length "sraiw"))) with | s_ => Some (s_) end + else None. + +Definition _s660_ (_s661_ : string) +: option string := + + let _s662_ := _s661_ in + if ((string_startswith _s662_ "srliw")) then + match (string_drop _s662_ (projT1 (string_length "srliw"))) with | s_ => Some (s_) end + else None. + +Definition _s656_ (_s657_ : string) +: option string := + + let _s658_ := _s657_ in + if ((string_startswith _s658_ "slliw")) then + match (string_drop _s658_ (projT1 (string_length "slliw"))) with | s_ => Some (s_) end + else None. + +Definition shiftiwop_mnemonic_matches_prefix (arg_ : string) +: M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) := + + let _s659_ := arg_ in + (if ((match (_s656_ _s659_) with | Some (s_) => true | _ => false end)) then + (match (_s656_ _s659_) with + | Some (s_) => + returnm ((Some + ((RISCV_SLLIW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sopw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s660_ _s659_) with | Some (s_) => true | _ => false end)) then + (match (_s660_ _s659_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRLIW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sopw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s664_ _s659_) with | Some (s_) => true | _ => false end)) then + (match (_s664_ _s659_) with + | Some (s_) => + returnm ((Some + ((RISCV_SRAIW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((sopw * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((sopw * {n : Z & ArithFact (n >= 0)})))) + : M (option ((sopw * {n : Z & ArithFact (n >= 0)}))). + +Definition encdec_mul_op_forwards (arg_ : (bool * bool * bool)) +: M (mword 3) := + + (match arg_ with + | (false, true, true) => returnm ((vec_of_bits [B0;B0;B0] : mword 3) : mword 3) + | (true, true, true) => returnm ((vec_of_bits [B0;B0;B1] : mword 3) : mword 3) + | (true, true, false) => returnm ((vec_of_bits [B0;B1;B0] : mword 3) : mword 3) + | (true, false, false) => returnm ((vec_of_bits [B0;B1;B1] : mword 3) : mword 3) + | _ => exit tt : M (mword 3) + end) + : M (mword 3). + +Definition encdec_mul_op_backwards (arg_ : mword 3) +: (bool * bool * bool) := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then (false, true, true) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then (true, true, true) + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then (true, true, false) + else (true, false, false). + +Definition encdec_mul_op_forwards_matches (arg_ : (bool * bool * bool)) +: bool := + + match arg_ with + | (false, true, true) => true + | (true, true, true) => true + | (true, true, false) => true + | (true, false, false) => true + | _ => false + end. + +Definition encdec_mul_op_backwards_matches (arg_ : mword 3) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B0;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B0] : mword 3))) then true + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1] : mword 3))) then true + else false. + +Definition mul_mnemonic_forwards (arg_ : (bool * bool * bool)) +: M (string) := + + (match arg_ with + | (false, true, true) => returnm ("mul" : string) + | (true, true, true) => returnm ("mulh" : string) + | (true, true, false) => returnm ("mulhsu" : string) + | (true, false, false) => returnm ("mulhu" : string) + | _ => exit tt : M (string) + end) + : M (string). + +Definition mul_mnemonic_backwards (arg_ : string) +: (bool * bool * bool) := + + let p0_ := arg_ in + if ((generic_eq p0_ "mul")) then (false, true, true) + else if ((generic_eq p0_ "mulh")) then (true, true, true) + else if ((generic_eq p0_ "mulhsu")) then (true, true, false) + else (true, false, false). + +Definition mul_mnemonic_forwards_matches (arg_ : (bool * bool * bool)) +: bool := + + match arg_ with + | (false, true, true) => true + | (true, true, true) => true + | (true, true, false) => true + | (true, false, false) => true + | _ => false + end. + +Definition mul_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "mul")) then true + else if ((generic_eq p0_ "mulh")) then true + else if ((generic_eq p0_ "mulhsu")) then true + else if ((generic_eq p0_ "mulhu")) then true + else false. + +Definition _s680_ (_s681_ : string) +: option string := + + let _s682_ := _s681_ in + if ((string_startswith _s682_ "mulhu")) then + match (string_drop _s682_ (projT1 (string_length "mulhu"))) with | s_ => Some (s_) end + else None. + +Definition _s676_ (_s677_ : string) +: option string := + + let _s678_ := _s677_ in + if ((string_startswith _s678_ "mulhsu")) then + match (string_drop _s678_ (projT1 (string_length "mulhsu"))) with | s_ => Some (s_) end + else None. + +Definition _s672_ (_s673_ : string) +: option string := + + let _s674_ := _s673_ in + if ((string_startswith _s674_ "mulh")) then + match (string_drop _s674_ (projT1 (string_length "mulh"))) with | s_ => Some (s_) end + else None. + +Definition _s668_ (_s669_ : string) +: option string := + + let _s670_ := _s669_ in + if ((string_startswith _s670_ "mul")) then + match (string_drop _s670_ (projT1 (string_length "mul"))) with | s_ => Some (s_) end + else None. + +Definition mul_mnemonic_matches_prefix (arg_ : string) +: M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) := + + let _s671_ := arg_ in + (if ((match (_s668_ _s671_) with | Some (s_) => true | _ => false end)) then + (match (_s668_ _s671_) with + | Some (s_) => + returnm ((Some + (((false, true, true), build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s672_ _s671_) with | Some (s_) => true | _ => false end)) then + (match (_s672_ _s671_) with + | Some (s_) => + returnm ((Some + (((true, true, true), build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s676_ _s671_) with | Some (s_) => true | _ => false end)) then + (match (_s676_ _s671_) with + | Some (s_) => + returnm ((Some + (((true, true, false), build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s680_ _s671_) with | Some (s_) => true | _ => false end)) then + (match (_s680_ _s671_) with + | Some (s_) => + returnm ((Some + (((true, false, false), build_ex (projT1 (sub_nat + (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)})))) + : M (option (((bool * bool * bool) * {n : Z & ArithFact (n >= 0)}))). + +Definition maybe_not_u_forwards (arg_ : bool) +: string := + + match arg_ with | false => "u" | true => "" end. + +Definition maybe_not_u_backwards (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "u")) then false + else true. + +Definition maybe_not_u_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | false => true | true => true end. + +Definition maybe_not_u_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "u")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s688_ (_s689_ : string) +: option string := + + let _s690_ := _s689_ in + if ((string_startswith _s690_ "")) then + match (string_drop _s690_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s684_ (_s685_ : string) +: option string := + + let _s686_ := _s685_ in + if ((string_startswith _s686_ "u")) then + match (string_drop _s686_ (projT1 (string_length "u"))) with | s_ => Some (s_) end + else None. + +Definition maybe_not_u_matches_prefix (arg_ : string) +: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) := + + let _s687_ := arg_ in + (if ((match (_s684_ _s687_) with | Some (s_) => true | _ => false end)) then + (match (_s684_ _s687_) with + | Some (s_) => + returnm ((Some + ((false, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s688_ _s687_) with | Some (s_) => true | _ => false end)) then + (match (_s688_ _s687_) with + | Some (s_) => + returnm ((Some + ((true, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)})))) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))). + +Definition bit_maybe_r_forwards (arg_ : mword 1) +: string := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then "r" + else "". + +Definition bit_maybe_r_backwards (arg_ : string) +: mword 1 := + + let p0_ := arg_ in + if ((generic_eq p0_ "r")) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bit_maybe_r_forwards_matches (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else false. + +Definition bit_maybe_r_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "r")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s696_ (_s697_ : string) +: option string := + + let _s698_ := _s697_ in + if ((string_startswith _s698_ "")) then + match (string_drop _s698_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s692_ (_s693_ : string) +: option string := + + let _s694_ := _s693_ in + if ((string_startswith _s694_ "r")) then + match (string_drop _s694_ (projT1 (string_length "r"))) with | s_ => Some (s_) end + else None. + +Definition bit_maybe_r_matches_prefix (arg_ : string) +: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) := + + let _s695_ := arg_ in + (if ((match (_s692_ _s695_) with | Some (s_) => true | _ => false end)) then + (match (_s692_ _s695_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s696_ _s695_) with | Some (s_) => true | _ => false end)) then + (match (_s696_ _s695_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))). + +Definition bit_maybe_w_forwards (arg_ : mword 1) +: string := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then "w" + else "". + +Definition bit_maybe_w_backwards (arg_ : string) +: mword 1 := + + let p0_ := arg_ in + if ((generic_eq p0_ "w")) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bit_maybe_w_forwards_matches (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else false. + +Definition bit_maybe_w_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "w")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s704_ (_s705_ : string) +: option string := + + let _s706_ := _s705_ in + if ((string_startswith _s706_ "")) then + match (string_drop _s706_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s700_ (_s701_ : string) +: option string := + + let _s702_ := _s701_ in + if ((string_startswith _s702_ "w")) then + match (string_drop _s702_ (projT1 (string_length "w"))) with | s_ => Some (s_) end + else None. + +Definition bit_maybe_w_matches_prefix (arg_ : string) +: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) := + + let _s703_ := arg_ in + (if ((match (_s700_ _s703_) with | Some (s_) => true | _ => false end)) then + (match (_s700_ _s703_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s704_ _s703_) with | Some (s_) => true | _ => false end)) then + (match (_s704_ _s703_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))). + +Definition bit_maybe_i_forwards (arg_ : mword 1) +: string := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then "i" + else "". + +Definition bit_maybe_i_backwards (arg_ : string) +: mword 1 := + + let p0_ := arg_ in + if ((generic_eq p0_ "i")) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bit_maybe_i_forwards_matches (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else false. + +Definition bit_maybe_i_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "i")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s712_ (_s713_ : string) +: option string := + + let _s714_ := _s713_ in + if ((string_startswith _s714_ "")) then + match (string_drop _s714_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s708_ (_s709_ : string) +: option string := + + let _s710_ := _s709_ in + if ((string_startswith _s710_ "i")) then + match (string_drop _s710_ (projT1 (string_length "i"))) with | s_ => Some (s_) end + else None. + +Definition bit_maybe_i_matches_prefix (arg_ : string) +: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) := + + let _s711_ := arg_ in + (if ((match (_s708_ _s711_) with | Some (s_) => true | _ => false end)) then + (match (_s708_ _s711_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s712_ _s711_) with | Some (s_) => true | _ => false end)) then + (match (_s712_ _s711_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))). + +Definition bit_maybe_o_forwards (arg_ : mword 1) +: string := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then "o" + else "". + +Definition bit_maybe_o_backwards (arg_ : string) +: mword 1 := + + let p0_ := arg_ in + if ((generic_eq p0_ "o")) then (vec_of_bits [B1] : mword 1) + else (vec_of_bits [B0] : mword 1). + +Definition bit_maybe_o_forwards_matches (arg_ : mword 1) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B1] : mword 1))) then true + else if ((eq_vec b__0 (vec_of_bits [B0] : mword 1))) then true + else false. + +Definition bit_maybe_o_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "o")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s720_ (_s721_ : string) +: option string := + + let _s722_ := _s721_ in + if ((string_startswith _s722_ "")) then + match (string_drop _s722_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s716_ (_s717_ : string) +: option string := + + let _s718_ := _s717_ in + if ((string_startswith _s718_ "o")) then + match (string_drop _s718_ (projT1 (string_length "o"))) with | s_ => Some (s_) end + else None. + +Definition bit_maybe_o_matches_prefix (arg_ : string) +: M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) := + + let _s719_ := arg_ in + (if ((match (_s716_ _s719_) with | Some (s_) => true | _ => false end)) then + (match (_s716_ _s719_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B1] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s720_ _s719_) with | Some (s_) => true | _ => false end)) then + (match (_s720_ _s719_) with + | Some (s_) => + returnm ((Some + (((vec_of_bits [B0] : mword 1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length s_))))))) + : option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 1 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 1 * {n : Z & ArithFact (n >= 0)}))). + +Definition fence_bits_forwards (arg_ : mword 4) +: string := + + match arg_ with + | v__0 => + let i : bits 1 := subrange_vec_dec v__0 3 3 in + let w : bits 1 := subrange_vec_dec v__0 0 0 in + let r : bits 1 := subrange_vec_dec v__0 1 1 in + let o : bits 1 := subrange_vec_dec v__0 2 2 in + let i : bits 1 := subrange_vec_dec v__0 3 3 in + string_append (bit_maybe_i_forwards i) + (string_append (bit_maybe_o_forwards o) + (string_append (bit_maybe_r_forwards r) (string_append (bit_maybe_w_forwards w) ""))) + end. + +Definition _s724_ (_s725_ : string) +: M (option ((mword 1 * mword 1 * mword 1 * mword 1))) := + + (match _s725_ with + | _s726_ => + (bit_maybe_i_matches_prefix _s726_) >>= fun w__0 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (i,(existT _ _s727_ _)) => + (match (string_drop _s726_ _s727_) with + | _s728_ => + (bit_maybe_o_matches_prefix _s728_) >>= fun w__1 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (o,(existT _ _s729_ _)) => + (match (string_drop _s728_ _s729_) with + | _s730_ => + (bit_maybe_r_matches_prefix _s730_) >>= fun w__2 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (r,(existT _ _s731_ _)) => + (match (string_drop _s730_ _s731_) with + | _s732_ => + (bit_maybe_w_matches_prefix _s732_) >>= fun w__3 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (w,(existT _ _s733_ _)) => + let p0_ := string_drop _s732_ _s733_ in + if ((generic_eq p0_ "")) then Some ((i, o, r, w)) + else None + | _ => None + end) + : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))). + +Definition fence_bits_backwards (arg_ : string) +: M (mword 4) := + + let _s734_ := arg_ in + (_s724_ _s734_) >>= fun w__0 : option ((mword 1 * mword 1 * mword 1 * mword 1)) => + (match w__0 with + | Some (i,o,r,w) => + returnm ((concat_vec (i : bits 1) + (concat_vec (o : bits 1) (concat_vec (r : bits 1) (w : bits 1)))) + : mword (1 + (1 + (1 + 1)))) + | _ => exit tt : M (mword 4) + end) + : M (mword 4). + +Definition fence_bits_forwards_matches (arg_ : mword 4) +: bool := + + match arg_ with | v__1 => true end. + +Definition _s735_ (_s736_ : string) +: M (option ((mword 1 * mword 1 * mword 1 * mword 1))) := + + (match _s736_ with + | _s737_ => + (bit_maybe_i_matches_prefix _s737_) >>= fun w__0 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (i,(existT _ _s738_ _)) => + (match (string_drop _s737_ _s738_) with + | _s739_ => + (bit_maybe_o_matches_prefix _s739_) >>= fun w__1 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (o,(existT _ _s740_ _)) => + (match (string_drop _s739_ _s740_) with + | _s741_ => + (bit_maybe_r_matches_prefix _s741_) >>= fun w__2 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (r,(existT _ _s742_ _)) => + (match (string_drop _s741_ _s742_) with + | _s743_ => + (bit_maybe_w_matches_prefix _s743_) >>= fun w__3 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (w,(existT _ _s744_ _)) => + let p0_ := string_drop _s743_ _s744_ in + if ((generic_eq p0_ "")) then Some ((i, o, r, w)) + else None + | _ => None + end) + : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1))). + +Definition fence_bits_backwards_matches (arg_ : string) +: M (bool) := + + let _s745_ := arg_ in + (_s735_ _s745_) >>= fun w__0 : option ((mword 1 * mword 1 * mword 1 * mword 1)) => + (if ((match w__0 with | Some (i,o,r,w) => true | _ => false end)) then + (_s735_ _s745_) >>= fun w__1 : option ((mword 1 * mword 1 * mword 1 * mword 1)) => + (match w__1 with | Some (i,o,r,w) => returnm (true : bool) | _ => exit tt : M (bool) end) + : M (bool) + else returnm (false : bool)) + : M (bool). + +Definition _s746_ (_s747_ : string) +: M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) := + + (match _s747_ with + | _s748_ => + (bit_maybe_i_matches_prefix _s748_) >>= fun w__0 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (i,(existT _ _s749_ _)) => + (match (string_drop _s748_ _s749_) with + | _s750_ => + (bit_maybe_o_matches_prefix _s750_) >>= fun w__1 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (o,(existT _ _s751_ _)) => + (match (string_drop _s750_ _s751_) with + | _s752_ => + (bit_maybe_r_matches_prefix _s752_) >>= fun w__2 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (r,(existT _ _s753_ _)) => + (match (string_drop _s752_ _s753_) with + | _s754_ => + (bit_maybe_w_matches_prefix _s754_) >>= fun w__3 : option ((mword 1 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (w,(existT _ _s755_ _)) => + match (string_drop _s754_ _s755_) with + | s_ => Some ((i, o, r, w, s_)) + end + | _ => None + end) + : option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + | _ => + returnm (None + : option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + | _ => returnm (None : option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))) + end) + : M (option ((mword 1 * mword 1 * mword 1 * mword 1 * string))). + +Definition fence_bits_matches_prefix (arg_ : string) +: M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))) := + + let _s756_ := arg_ in + (_s746_ _s756_) >>= fun w__0 : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)) => + (if ((match w__0 with | Some (i,o,r,w,s_) => true | _ => false end)) then + (_s746_ _s756_) >>= fun w__1 : option ((mword 1 * mword 1 * mword 1 * mword 1 * string)) => + (match w__1 with + | Some (i,o,r,w,s_) => + returnm ((Some + ((concat_vec (i : bits 1) + (concat_vec (o : bits 1) (concat_vec (r : bits 1) (w : bits 1))), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((mword 4 * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((mword 4 * {n : Z & ArithFact (n >= 0)})))) + : M (option ((mword 4 * {n : Z & ArithFact (n >= 0)}))). + +Definition aqrl_str (aq : bool) (rl : bool) +: string := + + match (aq, rl) with + | (false, false) => "" + | (false, true) => ".rl" + | (true, false) => ".aq" + | (true, true) => ".aqrl" + end. + +Definition lrsc_width_str (width : word_width) +: string := + + match width with | BYTE => ".b" | HALF => ".h" | WORD => ".w" | DOUBLE => ".d" end. + +Definition process_loadres {n : Z} +(rd : mword 5) (addr : mword 64) (value : MemoryOpResult (mword (8 * n))) (is_unsigned : bool) +`{ArithFact ((0 + 1) <= n /\ n <= 8)} +: M (bool) := + + (match (extend_value is_unsigned value) with + | MemValue (result) => + let '_ := (load_reservation addr) : unit in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool) + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + end) + : M (bool). + +Definition encdec_amoop_forwards (arg_ : amoop) +: mword 5 := + + match arg_ with + | AMOSWAP => (vec_of_bits [B0;B0;B0;B0;B1] : mword 5) + | AMOADD => (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + | AMOXOR => (vec_of_bits [B0;B0;B1;B0;B0] : mword 5) + | AMOAND => (vec_of_bits [B0;B1;B1;B0;B0] : mword 5) + | AMOOR => (vec_of_bits [B0;B1;B0;B0;B0] : mword 5) + | AMOMIN => (vec_of_bits [B1;B0;B0;B0;B0] : mword 5) + | AMOMAX => (vec_of_bits [B1;B0;B1;B0;B0] : mword 5) + | AMOMINU => (vec_of_bits [B1;B1;B0;B0;B0] : mword 5) + | AMOMAXU => (vec_of_bits [B1;B1;B1;B0;B0] : mword 5) + end. + +Definition encdec_amoop_backwards (arg_ : mword 5) +: amoop := + + let b__0 := arg_ in + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))))) + then + AMOSWAP + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))))) + then + AMOADD + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))))) + then + AMOXOR + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))))) + then + AMOAND + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))))) + then + AMOOR + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))))) + then + AMOMIN + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))))) + then + AMOMAX + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))))) + then + AMOMINU + else AMOMAXU. + +Definition encdec_amoop_forwards_matches (arg_ : amoop) +: bool := + + match arg_ with + | AMOSWAP => true + | AMOADD => true + | AMOXOR => true + | AMOAND => true + | AMOOR => true + | AMOMIN => true + | AMOMAX => true + | AMOMINU => true + | AMOMAXU => true + end. + +Definition encdec_amoop_backwards_matches (arg_ : mword 5) +: bool := + + let b__0 := arg_ in + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0] : mword 5))))) + then + true + else if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno b__0)) + (projT1 (regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0] : mword 5))))) + then + true + else false. + +Definition amo_mnemonic_forwards (arg_ : amoop) +: string := + + match arg_ with + | AMOSWAP => "amoswap" + | AMOADD => "amoadd" + | AMOXOR => "amoxor" + | AMOAND => "amoand" + | AMOOR => "amoor" + | AMOMIN => "amomin" + | AMOMAX => "amomax" + | AMOMINU => "amominu" + | AMOMAXU => "amomaxu" + end. + +Definition amo_mnemonic_backwards (arg_ : string) +: amoop := + + let p0_ := arg_ in + if ((generic_eq p0_ "amoswap")) then AMOSWAP + else if ((generic_eq p0_ "amoadd")) then AMOADD + else if ((generic_eq p0_ "amoxor")) then AMOXOR + else if ((generic_eq p0_ "amoand")) then AMOAND + else if ((generic_eq p0_ "amoor")) then AMOOR + else if ((generic_eq p0_ "amomin")) then AMOMIN + else if ((generic_eq p0_ "amomax")) then AMOMAX + else if ((generic_eq p0_ "amominu")) then AMOMINU + else AMOMAXU. + +Definition amo_mnemonic_forwards_matches (arg_ : amoop) +: bool := + + match arg_ with + | AMOSWAP => true + | AMOADD => true + | AMOXOR => true + | AMOAND => true + | AMOOR => true + | AMOMIN => true + | AMOMAX => true + | AMOMINU => true + | AMOMAXU => true + end. + +Definition amo_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "amoswap")) then true + else if ((generic_eq p0_ "amoadd")) then true + else if ((generic_eq p0_ "amoxor")) then true + else if ((generic_eq p0_ "amoand")) then true + else if ((generic_eq p0_ "amoor")) then true + else if ((generic_eq p0_ "amomin")) then true + else if ((generic_eq p0_ "amomax")) then true + else if ((generic_eq p0_ "amominu")) then true + else if ((generic_eq p0_ "amomaxu")) then true + else false. + +Definition _s789_ (_s790_ : string) +: option string := + + let _s791_ := _s790_ in + if ((string_startswith _s791_ "amomaxu")) then + match (string_drop _s791_ (projT1 (string_length "amomaxu"))) with | s_ => Some (s_) end + else None. + +Definition _s785_ (_s786_ : string) +: option string := + + let _s787_ := _s786_ in + if ((string_startswith _s787_ "amominu")) then + match (string_drop _s787_ (projT1 (string_length "amominu"))) with | s_ => Some (s_) end + else None. + +Definition _s781_ (_s782_ : string) +: option string := + + let _s783_ := _s782_ in + if ((string_startswith _s783_ "amomax")) then + match (string_drop _s783_ (projT1 (string_length "amomax"))) with | s_ => Some (s_) end + else None. + +Definition _s777_ (_s778_ : string) +: option string := + + let _s779_ := _s778_ in + if ((string_startswith _s779_ "amomin")) then + match (string_drop _s779_ (projT1 (string_length "amomin"))) with | s_ => Some (s_) end + else None. + +Definition _s773_ (_s774_ : string) +: option string := + + let _s775_ := _s774_ in + if ((string_startswith _s775_ "amoor")) then + match (string_drop _s775_ (projT1 (string_length "amoor"))) with | s_ => Some (s_) end + else None. + +Definition _s769_ (_s770_ : string) +: option string := + + let _s771_ := _s770_ in + if ((string_startswith _s771_ "amoand")) then + match (string_drop _s771_ (projT1 (string_length "amoand"))) with | s_ => Some (s_) end + else None. + +Definition _s765_ (_s766_ : string) +: option string := + + let _s767_ := _s766_ in + if ((string_startswith _s767_ "amoxor")) then + match (string_drop _s767_ (projT1 (string_length "amoxor"))) with | s_ => Some (s_) end + else None. + +Definition _s761_ (_s762_ : string) +: option string := + + let _s763_ := _s762_ in + if ((string_startswith _s763_ "amoadd")) then + match (string_drop _s763_ (projT1 (string_length "amoadd"))) with | s_ => Some (s_) end + else None. + +Definition _s757_ (_s758_ : string) +: option string := + + let _s759_ := _s758_ in + if ((string_startswith _s759_ "amoswap")) then + match (string_drop _s759_ (projT1 (string_length "amoswap"))) with | s_ => Some (s_) end + else None. + +Definition amo_mnemonic_matches_prefix (arg_ : string) +: M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) := + + let _s760_ := arg_ in + (if ((match (_s757_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s757_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOSWAP, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s761_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s761_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOADD, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s765_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s765_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOXOR, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s769_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s769_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOAND, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s773_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s773_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOOR, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s777_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s777_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOMIN, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s781_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s781_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOMAX, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s785_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s785_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOMINU, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s789_ _s760_) with | Some (s_) => true | _ => false end)) then + (match (_s789_ _s760_) with + | Some (s_) => + returnm ((Some + ((AMOMAXU, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((amoop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((amoop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((amoop * {n : Z & ArithFact (n >= 0)}))). + +Definition encdec_csrop_forwards (arg_ : csrop) +: mword 2 := + + match arg_ with + | CSRRW => (vec_of_bits [B0;B1] : mword 2) + | CSRRS => (vec_of_bits [B1;B0] : mword 2) + | CSRRC => (vec_of_bits [B1;B1] : mword 2) + end. + +Definition encdec_csrop_backwards (arg_ : mword 2) +: csrop := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then CSRRW + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then CSRRS + else CSRRC. + +Definition encdec_csrop_forwards_matches (arg_ : csrop) +: bool := + + match arg_ with | CSRRW => true | CSRRS => true | CSRRC => true end. + +Definition encdec_csrop_backwards_matches (arg_ : mword 2) +: bool := + + let b__0 := arg_ in + if ((eq_vec b__0 (vec_of_bits [B0;B1] : mword 2))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B0] : mword 2))) then true + else if ((eq_vec b__0 (vec_of_bits [B1;B1] : mword 2))) then true + else false. + +Definition readCSR (csr : mword 12) +: M (mword 64) := + + let b__0 := csr in + (if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1] : mword 12))) then + ((read_reg mvendorid_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0] : mword 12))) then + ((read_reg marchid_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1] : mword 12))) then + ((read_reg mimpid_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0] : mword 12))) then + ((read_reg mhartid_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + read_reg mstatus_ref >>= fun w__4 : Mstatus => returnm ((_get_Mstatus_bits w__4) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + read_reg misa_ref >>= fun w__5 : Misa => returnm ((_get_Misa_bits w__5) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg medeleg_ref >>= fun w__6 : Medeleg => returnm ((_get_Medeleg_bits w__6) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + read_reg mideleg_ref >>= fun w__7 : Minterrupts => + returnm ((_get_Minterrupts_bits w__7) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mie_ref >>= fun w__8 : Minterrupts => + returnm ((_get_Minterrupts_bits w__8) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + read_reg mtvec_ref >>= fun w__9 : Mtvec => returnm ((_get_Mtvec_bits w__9) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + read_reg mcounteren_ref >>= fun w__10 : Counteren => + returnm ((EXTZ 64 (_get_Counteren_bits w__10)) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + ((read_reg mscratch_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + ((read_reg mepc_ref) : M (mword 64)) >>= fun w__12 : xlenbits => + (pc_alignment_mask tt) >>= fun w__13 : mword 64 => returnm ((and_vec w__12 w__13) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg mcause_ref >>= fun w__14 : Mcause => returnm ((_get_Mcause_bits w__14) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + ((read_reg mtval_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mip_ref >>= fun w__16 : Minterrupts => + returnm ((_get_Minterrupts_bits w__16) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + ((read_reg pmpcfg0_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then + ((read_reg pmpaddr0_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + read_reg mstatus_ref >>= fun w__19 : Mstatus => + returnm ((_get_Sstatus_bits (lower_mstatus w__19)) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg sedeleg_ref >>= fun w__20 : Sedeleg => + returnm ((_get_Sedeleg_bits w__20) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + read_reg sideleg_ref >>= fun w__21 : Sinterrupts => + returnm ((_get_Sinterrupts_bits w__21) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mie_ref >>= fun w__22 : Minterrupts => + read_reg mideleg_ref >>= fun w__23 : Minterrupts => + returnm ((_get_Sinterrupts_bits (lower_mie w__22 w__23)) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + read_reg stvec_ref >>= fun w__24 : Mtvec => returnm ((_get_Mtvec_bits w__24) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + read_reg scounteren_ref >>= fun w__25 : Counteren => + returnm ((EXTZ 64 (_get_Counteren_bits w__25)) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + ((read_reg sscratch_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + ((read_reg sepc_ref) : M (mword 64)) >>= fun w__27 : xlenbits => + (pc_alignment_mask tt) >>= fun w__28 : mword 64 => returnm ((and_vec w__27 w__28) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg scause_ref >>= fun w__29 : Mcause => returnm ((_get_Mcause_bits w__29) : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + ((read_reg stval_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mip_ref >>= fun w__31 : Minterrupts => + read_reg mideleg_ref >>= fun w__32 : Minterrupts => + returnm ((_get_Sinterrupts_bits (lower_mip w__31 w__32)) + : mword 64) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + ((read_reg satp_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + ((read_reg mcycle_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + ((read_reg mtime_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + ((read_reg minstret_ref) : M (mword 64)) + : M (xlenbits) + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + ((read_reg tselect_ref) : M (mword 64)) >>= fun w__37 : xlenbits => + returnm ((not_vec w__37) + : mword 64) + else + let '_ := (print_bits "unhandled read to CSR " csr) : unit in + returnm ((vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) + : mword 64)) >>= fun res : xlenbits => + let '_ := + (print_endline + (String.append "CSR " + (String.append ((csr_name csr) : string) (String.append " -> " (string_of_bits res))))) + : unit in + returnm (res + : mword 64). + +Definition writeCSR (csr : mword 12) (value : mword 64) +: M (unit) := + + let b__0 := csr in + (if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + read_reg mstatus_ref >>= fun w__0 : Mstatus => + write_reg mstatus_ref (legalize_mstatus w__0 value) >> + read_reg mstatus_ref >>= fun w__1 : Mstatus => + returnm ((Some + (_get_Mstatus_bits w__1)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12))) then + read_reg misa_ref >>= fun w__2 : Misa => + (legalize_misa w__2 value) >>= fun w__3 : Misa => + write_reg misa_ref w__3 >> + read_reg misa_ref >>= fun w__4 : Misa => + returnm ((Some + (_get_Misa_bits w__4)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg medeleg_ref >>= fun w__5 : Medeleg => + write_reg medeleg_ref (legalize_medeleg w__5 value) >> + read_reg medeleg_ref >>= fun w__6 : Medeleg => + returnm ((Some + (_get_Medeleg_bits w__6)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + read_reg mideleg_ref >>= fun w__7 : Minterrupts => + write_reg mideleg_ref (legalize_mideleg w__7 value) >> + read_reg mideleg_ref >>= fun w__8 : Minterrupts => + returnm ((Some + (_get_Minterrupts_bits w__8)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mie_ref >>= fun w__9 : Minterrupts => + write_reg mie_ref (legalize_mie w__9 value) >> + read_reg mie_ref >>= fun w__10 : Minterrupts => + returnm ((Some + (_get_Minterrupts_bits w__10)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + read_reg mtvec_ref >>= fun w__11 : Mtvec => + write_reg mtvec_ref (legalize_tvec w__11 value) >> + read_reg mtvec_ref >>= fun w__12 : Mtvec => + returnm ((Some + (_get_Mtvec_bits w__12)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + read_reg mcounteren_ref >>= fun w__13 : Counteren => + (legalize_mcounteren w__13 value) >>= fun w__14 : Counteren => + write_reg mcounteren_ref w__14 >> + read_reg mcounteren_ref >>= fun w__15 : Counteren => + returnm ((Some + (EXTZ 64 (_get_Counteren_bits w__15))) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + write_reg mscratch_ref value >> + ((read_reg mscratch_ref) : M (mword 64)) >>= fun w__16 : xlenbits => + returnm ((Some + (w__16)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + (legalize_xepc value) >>= fun w__17 : mword 64 => + write_reg mepc_ref w__17 >> + ((read_reg mepc_ref) : M (mword 64)) >>= fun w__18 : xlenbits => + returnm ((Some + (w__18)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + (_set_Mcause_bits mcause_ref value) >> + read_reg mcause_ref >>= fun w__19 : Mcause => + returnm ((Some + (_get_Mcause_bits w__19)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + write_reg mtval_ref value >> + ((read_reg mtval_ref) : M (mword 64)) >>= fun w__20 : xlenbits => + returnm ((Some + (w__20)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mip_ref >>= fun w__21 : Minterrupts => + write_reg mip_ref (legalize_mip w__21 value) >> + read_reg mip_ref >>= fun w__22 : Minterrupts => + returnm ((Some + (_get_Minterrupts_bits w__22)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + write_reg pmpcfg0_ref value >> + ((read_reg pmpcfg0_ref) : M (mword 64)) >>= fun w__23 : xlenbits => + returnm ((Some + (w__23)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B1;B1;B1;B0;B1;B1;B0;B0;B0;B0] : mword 12))) then + write_reg pmpaddr0_ref value >> + ((read_reg pmpaddr0_ref) : M (mword 64)) >>= fun w__24 : xlenbits => + returnm ((Some + (w__24)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + read_reg mstatus_ref >>= fun w__25 : Mstatus => + write_reg mstatus_ref (legalize_sstatus w__25 value) >> + read_reg mstatus_ref >>= fun w__26 : Mstatus => + returnm ((Some + (_get_Mstatus_bits w__26)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + read_reg sedeleg_ref >>= fun w__27 : Sedeleg => + write_reg sedeleg_ref (legalize_sedeleg w__27 value) >> + read_reg sedeleg_ref >>= fun w__28 : Sedeleg => + returnm ((Some + (_get_Sedeleg_bits w__28)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1] : mword 12))) then + (_set_Sinterrupts_bits sideleg_ref value) >> + read_reg sideleg_ref >>= fun w__29 : Sinterrupts => + returnm ((Some + (_get_Sinterrupts_bits w__29)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mie_ref >>= fun w__30 : Minterrupts => + read_reg mideleg_ref >>= fun w__31 : Minterrupts => + write_reg mie_ref (legalize_sie w__30 w__31 value) >> + read_reg mie_ref >>= fun w__32 : Minterrupts => + returnm ((Some + (_get_Minterrupts_bits w__32)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12))) then + read_reg stvec_ref >>= fun w__33 : Mtvec => + write_reg stvec_ref (legalize_tvec w__33 value) >> + read_reg stvec_ref >>= fun w__34 : Mtvec => + returnm ((Some + (_get_Mtvec_bits w__34)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0] : mword 12))) then + read_reg scounteren_ref >>= fun w__35 : Counteren => + (legalize_scounteren w__35 value) >>= fun w__36 : Counteren => + write_reg scounteren_ref w__36 >> + read_reg scounteren_ref >>= fun w__37 : Counteren => + returnm ((Some + (EXTZ 64 (_get_Counteren_bits w__37))) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0] : mword 12))) then + write_reg sscratch_ref value >> + ((read_reg sscratch_ref) : M (mword 64)) >>= fun w__38 : xlenbits => + returnm ((Some + (w__38)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1] : mword 12))) then + (legalize_xepc value) >>= fun w__39 : mword 64 => + write_reg sepc_ref w__39 >> + ((read_reg sepc_ref) : M (mword 64)) >>= fun w__40 : xlenbits => + returnm ((Some + (w__40)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0] : mword 12))) then + (_set_Mcause_bits scause_ref value) >> + read_reg scause_ref >>= fun w__41 : Mcause => + returnm ((Some + (_get_Mcause_bits w__41)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1] : mword 12))) then + write_reg stval_ref value >> + ((read_reg stval_ref) : M (mword 64)) >>= fun w__42 : xlenbits => + returnm ((Some + (w__42)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0] : mword 12))) then + read_reg mip_ref >>= fun w__43 : Minterrupts => + read_reg mideleg_ref >>= fun w__44 : Minterrupts => + write_reg mip_ref (legalize_sip w__43 w__44 value) >> + read_reg mip_ref >>= fun w__45 : Minterrupts => + returnm ((Some + (_get_Minterrupts_bits w__45)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + (cur_Architecture tt) >>= fun w__46 : Architecture => + ((read_reg satp_ref) : M (mword 64)) >>= fun w__47 : xlenbits => + write_reg satp_ref (legalize_satp w__46 w__47 value) >> + ((read_reg satp_ref) : M (mword 64)) >>= fun w__48 : xlenbits => + returnm ((Some + (w__48)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B0;B1;B1;B1;B1;B0;B1;B0;B0;B0;B0;B0] : mword 12))) then + write_reg tselect_ref value >> + ((read_reg tselect_ref) : M (mword 64)) >>= fun w__49 : xlenbits => + returnm ((Some + (w__49)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12))) then + write_reg mcycle_ref value >> + ((read_reg mcycle_ref) : M (mword 64)) >>= fun w__50 : xlenbits => + returnm ((Some + (w__50)) + : option (mword 64)) + else if ((eq_vec b__0 (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 12))) then + write_reg minstret_ref value >> + write_reg minstret_written_ref true >> + ((read_reg minstret_ref) : M (mword 64)) >>= fun w__51 : xlenbits => + returnm ((Some + (w__51)) + : option (mword 64)) + else returnm (None : option (mword 64))) >>= fun res : option xlenbits => + returnm ((match res with + | Some (v) => + print_endline + (String.append "CSR " + (String.append ((csr_name csr) : string) + (String.append " <- " + (String.append (string_of_bits v) + (String.append " (input: " (String.append (string_of_bits value) ")")))))) + | None => print_bits "unhandled write to CSR " csr + end) + : unit). + +Definition maybe_i_forwards (arg_ : bool) +: string := + + match arg_ with | true => "i" | false => "" end. + +Definition maybe_i_backwards (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "i")) then true + else false. + +Definition maybe_i_forwards_matches (arg_ : bool) +: bool := + + match arg_ with | true => true | false => true end. + +Definition maybe_i_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "i")) then true + else if ((generic_eq p0_ "")) then true + else false. + +Definition _s797_ (_s798_ : string) +: option string := + + let _s799_ := _s798_ in + if ((string_startswith _s799_ "")) then + match (string_drop _s799_ (projT1 (string_length ""))) with | s_ => Some (s_) end + else None. + +Definition _s793_ (_s794_ : string) +: option string := + + let _s795_ := _s794_ in + if ((string_startswith _s795_ "i")) then + match (string_drop _s795_ (projT1 (string_length "i"))) with | s_ => Some (s_) end + else None. + +Definition maybe_i_matches_prefix (arg_ : string) +: M (option ((bool * {n : Z & ArithFact (n >= 0)}))) := + + let _s796_ := arg_ in + (if ((match (_s793_ _s796_) with | Some (s_) => true | _ => false end)) then + (match (_s793_ _s796_) with + | Some (s_) => + returnm ((Some + ((true, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s797_ _s796_) with | Some (s_) => true | _ => false end)) then + (match (_s797_ _s796_) with + | Some (s_) => + returnm ((Some + ((false, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((bool * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((bool * {n : Z & ArithFact (n >= 0)})))) + : M (option ((bool * {n : Z & ArithFact (n >= 0)}))). + +Definition csr_mnemonic_forwards (arg_ : csrop) +: string := + + match arg_ with | CSRRW => "csrrw" | CSRRS => "csrrs" | CSRRC => "csrrc" end. + +Definition csr_mnemonic_backwards (arg_ : string) +: csrop := + + let p0_ := arg_ in + if ((generic_eq p0_ "csrrw")) then CSRRW + else if ((generic_eq p0_ "csrrs")) then CSRRS + else CSRRC. + +Definition csr_mnemonic_forwards_matches (arg_ : csrop) +: bool := + + match arg_ with | CSRRW => true | CSRRS => true | CSRRC => true end. + +Definition csr_mnemonic_backwards_matches (arg_ : string) +: bool := + + let p0_ := arg_ in + if ((generic_eq p0_ "csrrw")) then true + else if ((generic_eq p0_ "csrrs")) then true + else if ((generic_eq p0_ "csrrc")) then true + else false. + +Definition _s809_ (_s810_ : string) +: option string := + + let _s811_ := _s810_ in + if ((string_startswith _s811_ "csrrc")) then + match (string_drop _s811_ (projT1 (string_length "csrrc"))) with | s_ => Some (s_) end + else None. + +Definition _s805_ (_s806_ : string) +: option string := + + let _s807_ := _s806_ in + if ((string_startswith _s807_ "csrrs")) then + match (string_drop _s807_ (projT1 (string_length "csrrs"))) with | s_ => Some (s_) end + else None. + +Definition _s801_ (_s802_ : string) +: option string := + + let _s803_ := _s802_ in + if ((string_startswith _s803_ "csrrw")) then + match (string_drop _s803_ (projT1 (string_length "csrrw"))) with | s_ => Some (s_) end + else None. + +Definition csr_mnemonic_matches_prefix (arg_ : string) +: M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) := + + let _s804_ := arg_ in + (if ((match (_s801_ _s804_) with | Some (s_) => true | _ => false end)) then + (match (_s801_ _s804_) with + | Some (s_) => + returnm ((Some + ((CSRRW, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((csrop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s805_ _s804_) with | Some (s_) => true | _ => false end)) then + (match (_s805_ _s804_) with + | Some (s_) => + returnm ((Some + ((CSRRS, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((csrop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) + else if ((match (_s809_ _s804_) with | Some (s_) => true | _ => false end)) then + (match (_s809_ _s804_) with + | Some (s_) => + returnm ((Some + ((CSRRC, build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((csrop * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))) + else returnm (None : option ((csrop * {n : Z & ArithFact (n >= 0)})))) + : M (option ((csrop * {n : Z & ArithFact (n >= 0)}))). + +Definition encdec_forwards (arg_ : ast) +: M (mword 32) := + + (match arg_ with + | UTYPE (imm,rd,op) => + returnm ((concat_vec (imm : mword 20) (concat_vec (rd : mword 5) (encdec_uop_forwards op))) + : mword (20 + (5 + 7))) + | RISCV_JAL (v__2,rd) => + let imm_19 : bits 1 := subrange_vec_dec v__2 20 20 in + let imm_8 : bits 1 := subrange_vec_dec v__2 11 11 in + let imm_7_0 : bits 8 := subrange_vec_dec v__2 19 12 in + let imm_19 : bits 1 := subrange_vec_dec v__2 20 20 in + let imm_18_13 : bits 6 := subrange_vec_dec v__2 10 5 in + let imm_12_9 : bits 4 := subrange_vec_dec v__2 4 1 in + returnm ((concat_vec (imm_19 : bits 1) + (concat_vec (imm_18_13 : bits 6) + (concat_vec (imm_12_9 : bits 4) + (concat_vec (imm_8 : bits 1) + (concat_vec (imm_7_0 : bits 8) + (concat_vec (rd : mword 5) + (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword 7))))))) + : mword 32) + | RISCV_JALR (imm,rs1,rd) => + returnm ((concat_vec (imm : mword 12) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | BTYPE (v__4,rs2,rs1,op) => + let imm7_6 : bits 1 := subrange_vec_dec v__4 12 12 in + let imm7_6 : bits 1 := subrange_vec_dec v__4 12 12 in + let imm7_5_0 : bits 6 := subrange_vec_dec v__4 10 5 in + let imm5_4_1 : bits 4 := subrange_vec_dec v__4 4 1 in + let imm5_0 : bits 1 := subrange_vec_dec v__4 11 11 in + returnm ((concat_vec (imm7_6 : bits 1) + (concat_vec (imm7_5_0 : bits 6) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (encdec_bop_forwards op) + (concat_vec (imm5_4_1 : bits 4) + (concat_vec (imm5_0 : bits 1) + (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword 7)))))))) + : mword 32) + | ITYPE (imm,rs1,rd,op) => + returnm ((concat_vec (imm : mword 12) + (concat_vec (rs1 : mword 5) + (concat_vec (encdec_iop_forwards op) + (concat_vec (rd : mword 5) (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | SHIFTIOP (shamt,rs1,rd,RISCV_SLLI) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6) + (concat_vec (shamt : mword 6) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (6 + (6 + (5 + (3 + (5 + 7)))))) + | SHIFTIOP (shamt,rs1,rd,RISCV_SRLI) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6) + (concat_vec (shamt : mword 6) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (6 + (6 + (5 + (3 + (5 + 7)))))) + | SHIFTIOP (shamt,rs1,rd,RISCV_SRAI) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword 6) + (concat_vec (shamt : mword 6) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (6 + (6 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_ADD) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_SUB) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_SLL) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_SLT) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B1;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_SLTU) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B1;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_XOR) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_SRL) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_SRA) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_OR) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B1;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPE (rs2,rs1,rd,RISCV_AND) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B1;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | LOAD (imm,rs1,rd,is_unsigned,size,false,false) => + returnm ((concat_vec (imm : mword 12) + (concat_vec (rs1 : mword 5) + (concat_vec (bool_bits_forwards is_unsigned) + (concat_vec (size_bits_forwards size) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword 7)))))) + : mword (12 + (5 + (1 + (2 + (5 + 7)))))) + | STORE (v__6,rs2,rs1,size,false,false) => + let imm7 : bits 7 := subrange_vec_dec v__6 11 5 in + let imm7 : bits 7 := subrange_vec_dec v__6 11 5 in + let imm5 : bits 5 := subrange_vec_dec v__6 4 0 in + returnm ((concat_vec (imm7 : bits 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (size_bits_forwards size) + (concat_vec (imm5 : bits 5) + (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword 7))))))) + : mword 32) + | ADDIW (imm,rs1,rd) => + returnm ((concat_vec (imm : mword 12) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | SHIFTW (shamt,rs1,rd,RISCV_SLLI) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (shamt : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | SHIFTW (shamt,rs1,rd,RISCV_SRLI) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (shamt : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | SHIFTW (shamt,rs1,rd,RISCV_SRAI) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (shamt : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPEW (rs2,rs1,rd,RISCV_ADDW) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPEW (rs2,rs1,rd,RISCV_SUBW) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPEW (rs2,rs1,rd,RISCV_SLLW) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPEW (rs2,rs1,rd,RISCV_SRLW) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | RTYPEW (rs2,rs1,rd,RISCV_SRAW) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | SHIFTIWOP (shamt,rs1,rd,RISCV_SLLIW) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (shamt : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | SHIFTIWOP (shamt,rs1,rd,RISCV_SRLIW) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (shamt : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | SHIFTIWOP (shamt,rs1,rd,RISCV_SRAIW) => + returnm ((concat_vec (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword 7) + (concat_vec (shamt : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | MUL (rs2,rs1,rd,high,signed1,signed2) => + (encdec_mul_op_forwards (high, signed1, signed2)) >>= fun w__0 : mword 3 => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (w__0 : bits 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | DIV (rs2,rs1,rd,s) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0] : mword 2) + (concat_vec (bool_not_bits_forwards s) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))) + : mword (7 + (5 + (5 + (2 + (1 + (5 + 7))))))) + | REM (rs2,rs1,rd,s) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (bool_not_bits_forwards s) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword 7))))))) + : mword (7 + (5 + (5 + (2 + (1 + (5 + 7))))))) + | MULW (rs2,rs1,rd) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | DIVW (rs2,rs1,rd,s) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B0] : mword 2) + (concat_vec (bool_not_bits_forwards s) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))) + : mword (7 + (5 + (5 + (2 + (1 + (5 + 7))))))) + | REMW (rs2,rs1,rd,s) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (bool_not_bits_forwards s) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword 7))))))) + : mword (7 + (5 + (5 + (2 + (1 + (5 + 7))))))) + | FENCE (pred,succ) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0] : mword 4) + (concat_vec (pred : mword 4) + (concat_vec (succ : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7))))))) + : mword (4 + (4 + (4 + (5 + (3 + (5 + 7))))))) + | FENCE_TSO (pred,succ) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0;B0] : mword 4) + (concat_vec (pred : mword 4) + (concat_vec (succ : mword 4) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7))))))) + : mword (4 + (4 + (4 + (5 + (3 + (5 + 7))))))) + | FENCEI (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B0;B0;B0;B1;B1;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | ECALL (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | MRET (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B1;B1;B0;B0;B0] : mword 7) + (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | SRET (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0] : mword 7) + (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | EBREAK (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 12) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | WFI (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1] : mword 12) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7))))) + : mword (12 + (5 + (3 + (5 + 7))))) + | SFENCE_VMA (rs1,rs2) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword 7) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (7 + (5 + (5 + (3 + (5 + 7)))))) + | LOADRES (aq,rl,rs1,size,rd) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) + (concat_vec (bool_bits_forwards aq) + (concat_vec (bool_bits_forwards rl) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (size_bits_forwards size) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))))))) + : mword (5 + (1 + (1 + (5 + (5 + (1 + (2 + (5 + 7))))))))) + | STORECON (aq,rl,rs2,rs1,size,rd) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0;B1;B1] : mword 5) + (concat_vec (bool_bits_forwards aq) + (concat_vec (bool_bits_forwards rl) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (size_bits_forwards size) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))))))) + : mword (5 + (1 + (1 + (5 + (5 + (1 + (2 + (5 + 7))))))))) + | AMO (op,aq,rl,rs2,rs1,size,rd) => + returnm ((concat_vec (encdec_amoop_forwards op) + (concat_vec (bool_bits_forwards aq) + (concat_vec (bool_bits_forwards rl) + (concat_vec (rs2 : mword 5) + (concat_vec (rs1 : mword 5) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (size_bits_forwards size) + (concat_vec (rd : mword 5) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword 7))))))))) + : mword (5 + (1 + (1 + (5 + (5 + (1 + (2 + (5 + 7))))))))) + | CSR (csr,rs1,rd,is_imm,op) => + returnm ((concat_vec (csr : mword 12) + (concat_vec (rs1 : mword 5) + (concat_vec (bool_bits_forwards is_imm) + (concat_vec (encdec_csrop_forwards op) + (concat_vec (rd : mword 5) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword 7)))))) + : mword (12 + (5 + (1 + (2 + (5 + 7)))))) + | STOP_FETCHING (tt) => + returnm ((concat_vec + (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0] : mword 16) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0;B0] : mword 2) + (concat_vec (vec_of_bits [B0;B1;B0] : mword 3) + (vec_of_bits [B1;B1] : mword 2)))))) + : mword (16 + (8 + (1 + (2 + (3 + 2)))))) + | THREAD_START (tt) => + returnm ((concat_vec + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0] : mword 16) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0;B0] : mword 2) + (concat_vec (vec_of_bits [B0;B1;B0] : mword 3) + (vec_of_bits [B1;B1] : mword 2)))))) + : mword (16 + (8 + (1 + (2 + (3 + 2)))))) + | ILLEGAL (s) => returnm (s : mword 32) + | _ => exit tt : M (mword 32) + end) + : M (mword 32). + +Definition encdec_backwards (arg_ : mword 32) +: ast := + + let v__7 := arg_ in + if ((let _mappingpatterns_23_ : mword 7 := subrange_vec_dec v__7 6 0 in + andb (encdec_uop_backwards_matches _mappingpatterns_23_) + (if ((encdec_uop_backwards_matches _mappingpatterns_23_)) then + let op := encdec_uop_backwards _mappingpatterns_23_ in + true + else false))) then + let imm : mword 20 := subrange_vec_dec v__7 31 12 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let imm : mword 20 := subrange_vec_dec v__7 31 12 in + let _mappingpatterns_23_ : mword 7 := subrange_vec_dec v__7 6 0 in + let op := encdec_uop_backwards _mappingpatterns_23_ in + UTYPE + ((imm, rd, op)) + else if ((eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))) then + let imm_19 : bits 1 := subrange_vec_dec v__7 31 31 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let imm_8 : bits 1 := subrange_vec_dec v__7 20 20 in + let imm_7_0 : bits 8 := subrange_vec_dec v__7 19 12 in + let imm_19 : bits 1 := subrange_vec_dec v__7 31 31 in + let imm_18_13 : bits 6 := subrange_vec_dec v__7 30 25 in + let imm_12_9 : bits 4 := subrange_vec_dec v__7 24 21 in + RISCV_JAL + ((concat_vec (imm_19 : bits 1) + (concat_vec (imm_7_0 : bits 8) + (concat_vec (imm_8 : bits 1) + (concat_vec (imm_18_13 : bits 6) + (concat_vec (imm_12_9 : bits 4) (vec_of_bits [B0] : mword 1))))), rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 14 12) (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword (6 - 0 + 1))))) then + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + RISCV_JALR + ((imm, rs1, rd)) + else if ((andb + (let _mappingpatterns_24_ : mword 3 := subrange_vec_dec v__7 14 12 in + andb (encdec_bop_backwards_matches _mappingpatterns_24_) + (if ((encdec_bop_backwards_matches _mappingpatterns_24_)) then + let op := encdec_bop_backwards _mappingpatterns_24_ in + true + else false)) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let imm7_6 : bits 1 := subrange_vec_dec v__7 31 31 in + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let imm7_6 : bits 1 := subrange_vec_dec v__7 31 31 in + let imm7_5_0 : bits 6 := subrange_vec_dec v__7 30 25 in + let imm5_4_1 : bits 4 := subrange_vec_dec v__7 11 8 in + let imm5_0 : bits 1 := subrange_vec_dec v__7 7 7 in + let _mappingpatterns_24_ : mword 3 := subrange_vec_dec v__7 14 12 in + let op := encdec_bop_backwards _mappingpatterns_24_ in + BTYPE + ((concat_vec (imm7_6 : bits 1) + (concat_vec (imm5_0 : bits 1) + (concat_vec (imm7_5_0 : bits 6) + (concat_vec (imm5_4_1 : bits 4) (vec_of_bits [B0] : mword 1)))), rs2, rs1, op)) + else if ((andb + (let _mappingpatterns_25_ : mword 3 := subrange_vec_dec v__7 14 12 in + andb (encdec_iop_backwards_matches _mappingpatterns_25_) + (if ((encdec_iop_backwards_matches _mappingpatterns_25_)) then + let op := encdec_iop_backwards _mappingpatterns_25_ in + true + else false)) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + let _mappingpatterns_25_ : mword 3 := subrange_vec_dec v__7 14 12 in + let op := encdec_iop_backwards _mappingpatterns_25_ in + ITYPE + ((imm, rs1, rd, op)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 6 := subrange_vec_dec v__7 25 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTIOP + ((shamt, rs1, rd, RISCV_SLLI)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 6 := subrange_vec_dec v__7 25 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTIOP + ((shamt, rs1, rd, RISCV_SRLI)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 26) + (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 6 := subrange_vec_dec v__7 25 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTIOP + ((shamt, rs1, rd, RISCV_SRAI)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_ADD)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_SUB)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_SLL)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B1;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_SLT)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B1;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_SLTU)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_XOR)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_SRL)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_SRA)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B1;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_OR)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B1;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPE + ((rs2, rs1, rd, RISCV_AND)) + else if ((andb + (let _mappingpatterns_27_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_26_ : mword 1 := subrange_vec_dec v__7 14 14 in + andb (size_bits_backwards_matches _mappingpatterns_27_) + (if ((size_bits_backwards_matches _mappingpatterns_27_)) then + let size := size_bits_backwards _mappingpatterns_27_ in + andb (bool_bits_backwards_matches _mappingpatterns_26_) + (if ((bool_bits_backwards_matches _mappingpatterns_26_)) then + let is_unsigned := bool_bits_backwards _mappingpatterns_26_ in + orb (neq_vec (size_bits_forwards size) (vec_of_bits [B1;B1] : mword 2)) + (negb is_unsigned) + else false) + else false)) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + let _mappingpatterns_27_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_26_ : mword 1 := subrange_vec_dec v__7 14 14 in + let size := size_bits_backwards _mappingpatterns_27_ in + let is_unsigned := bool_bits_backwards _mappingpatterns_26_ in + LOAD + ((imm, rs1, rd, is_unsigned, size, false, false)) + else if ((andb + (let _mappingpatterns_28_ : mword 2 := subrange_vec_dec v__7 13 12 in + andb (size_bits_backwards_matches _mappingpatterns_28_) + (if ((size_bits_backwards_matches _mappingpatterns_28_)) then + let size := size_bits_backwards _mappingpatterns_28_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 14 14) (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let imm7 : bits 7 := subrange_vec_dec v__7 31 25 in + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let imm7 : bits 7 := subrange_vec_dec v__7 31 25 in + let imm5 : bits 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_28_ : mword 2 := subrange_vec_dec v__7 13 12 in + let size := size_bits_backwards _mappingpatterns_28_ in + STORE + ((concat_vec (imm7 : bits 7) (imm5 : bits 5), rs2, rs1, size, false, false)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 14 12) (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1))))) then + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let imm : mword 12 := subrange_vec_dec v__7 31 20 in + ADDIW + ((imm, rs1, rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTW + ((shamt, rs1, rd, RISCV_SLLI)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTW + ((shamt, rs1, rd, RISCV_SRLI)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTW + ((shamt, rs1, rd, RISCV_SRAI)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPEW + ((rs2, rs1, rd, RISCV_ADDW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPEW + ((rs2, rs1, rd, RISCV_SUBW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPEW + ((rs2, rs1, rd, RISCV_SLLW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPEW + ((rs2, rs1, rd, RISCV_SRLW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + RTYPEW + ((rs2, rs1, rd, RISCV_SRAW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTIWOP + ((shamt, rs1, rd, RISCV_SLLIW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTIWOP + ((shamt, rs1, rd, RISCV_SRLIW)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let shamt : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + SHIFTIWOP + ((shamt, rs1, rd, RISCV_SRAIW)) + else if ((andb + (let _mappingpatterns_29_ : bits 3 := subrange_vec_dec v__7 14 12 in + andb (encdec_mul_op_backwards_matches _mappingpatterns_29_) + (if ((encdec_mul_op_backwards_matches _mappingpatterns_29_)) then + let '(high, signed1, signed2) := encdec_mul_op_backwards _mappingpatterns_29_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_29_ : bits 3 := subrange_vec_dec v__7 14 12 in + let '(high, signed1, signed2) := encdec_mul_op_backwards _mappingpatterns_29_ in + MUL + ((rs2, rs1, rd, high, signed1, signed2)) + else if ((andb + (let _mappingpatterns_30_ : mword 1 := subrange_vec_dec v__7 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_30_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_30_)) then + let s := bool_not_bits_backwards _mappingpatterns_30_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 13) + (vec_of_bits [B1;B0] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_30_ : mword 1 := subrange_vec_dec v__7 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_30_ in + DIV + ((rs2, rs1, rd, s)) + else if ((andb + (let _mappingpatterns_31_ : mword 1 := subrange_vec_dec v__7 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_31_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_31_)) then + let s := bool_not_bits_backwards _mappingpatterns_31_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 13) + (vec_of_bits [B1;B1] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_31_ : mword 1 := subrange_vec_dec v__7 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_31_ in + REM + ((rs2, rs1, rd, s)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + MULW + ((rs2, rs1, rd)) + else if ((andb + (let _mappingpatterns_32_ : mword 1 := subrange_vec_dec v__7 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_32_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_32_)) then + let s := bool_not_bits_backwards _mappingpatterns_32_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 13) + (vec_of_bits [B1;B0] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_32_ : mword 1 := subrange_vec_dec v__7 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_32_ in + DIVW + ((rs2, rs1, rd, s)) + else if ((andb + (let _mappingpatterns_33_ : mword 1 := subrange_vec_dec v__7 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_33_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_33_)) then + let s := bool_not_bits_backwards _mappingpatterns_33_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__7 14 13) + (vec_of_bits [B1;B1] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_33_ : mword 1 := subrange_vec_dec v__7 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_33_ in + REMW + ((rs2, rs1, rd, s)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 28) + (vec_of_bits [B0;B0;B0;B0] : mword (31 - 28 + 1))) + (eq_vec (subrange_vec_dec v__7 19 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : mword (19 - 0 + 1))))) then + let succ : mword 4 := subrange_vec_dec v__7 23 20 in + let pred : mword 4 := subrange_vec_dec v__7 27 24 in + FENCE + ((pred, succ)) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 28) + (vec_of_bits [B1;B0;B0;B0] : mword (31 - 28 + 1))) + (eq_vec (subrange_vec_dec v__7 19 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : mword (19 - 0 + 1))))) then + let succ : mword 4 := subrange_vec_dec v__7 23 20 in + let pred : mword 4 := subrange_vec_dec v__7 27 24 in + FENCE_TSO + ((pred, succ)) + else if ((eq_vec v__7 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : mword 32))) then + FENCEI + (tt) + else if ((eq_vec v__7 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + ECALL + (tt) + else if ((eq_vec v__7 + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + MRET + (tt) + else if ((eq_vec v__7 + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + SRET + (tt) + else if ((eq_vec v__7 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + EBREAK + (tt) + else if ((eq_vec v__7 + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + WFI + (tt) + else if ((andb + (eq_vec (subrange_vec_dec v__7 31 25) + (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword (31 - 25 + 1))) + (eq_vec (subrange_vec_dec v__7 14 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : mword (14 - 0 + 1))))) + then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + SFENCE_VMA + ((rs1, rs2)) + else if sumbool_of_bool ((andb + (let _mappingpatterns_36_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_35_ : mword 1 := subrange_vec_dec v__7 25 25 in + let _mappingpatterns_34_ : mword 1 := subrange_vec_dec v__7 26 26 in + andb (size_bits_backwards_matches _mappingpatterns_36_) + (if ((size_bits_backwards_matches _mappingpatterns_36_)) then + let size := size_bits_backwards _mappingpatterns_36_ in + andb (bool_bits_backwards_matches _mappingpatterns_35_) + (if ((bool_bits_backwards_matches _mappingpatterns_35_)) then + let rl := bool_bits_backwards _mappingpatterns_35_ in + andb (bool_bits_backwards_matches _mappingpatterns_34_) + (if ((bool_bits_backwards_matches _mappingpatterns_34_)) + then + let aq := bool_bits_backwards _mappingpatterns_34_ in + true + else false) + else false) + else false)) + (andb + (Z.eqb (projT1 (regbits_to_regno (subrange_vec_dec v__7 31 27))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)))) + (andb + (Z.eqb + (projT1 (regbits_to_regno (subrange_vec_dec v__7 24 20))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) + (andb + (eq_vec (subrange_vec_dec v__7 14 14) + (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))))))) + then + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_36_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_35_ : mword 1 := subrange_vec_dec v__7 25 25 in + let _mappingpatterns_34_ : mword 1 := subrange_vec_dec v__7 26 26 in + let size := size_bits_backwards _mappingpatterns_36_ in + let rl := bool_bits_backwards _mappingpatterns_35_ in + let aq := bool_bits_backwards _mappingpatterns_34_ in + LOADRES + ((aq, rl, rs1, size, rd)) + else if sumbool_of_bool ((andb + (let _mappingpatterns_39_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_38_ : mword 1 := subrange_vec_dec v__7 25 25 in + let _mappingpatterns_37_ : mword 1 := subrange_vec_dec v__7 26 26 in + andb (size_bits_backwards_matches _mappingpatterns_39_) + (if ((size_bits_backwards_matches _mappingpatterns_39_)) then + let size := size_bits_backwards _mappingpatterns_39_ in + andb (bool_bits_backwards_matches _mappingpatterns_38_) + (if ((bool_bits_backwards_matches _mappingpatterns_38_)) then + let rl := bool_bits_backwards _mappingpatterns_38_ in + andb (bool_bits_backwards_matches _mappingpatterns_37_) + (if ((bool_bits_backwards_matches _mappingpatterns_37_)) + then + let aq := bool_bits_backwards _mappingpatterns_37_ in + true + else false) + else false) + else false)) + (andb + (Z.eqb (projT1 (regbits_to_regno (subrange_vec_dec v__7 31 27))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)))) + (andb + (eq_vec (subrange_vec_dec v__7 14 14) + (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1))))))) + then + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_39_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_38_ : mword 1 := subrange_vec_dec v__7 25 25 in + let _mappingpatterns_37_ : mword 1 := subrange_vec_dec v__7 26 26 in + let size := size_bits_backwards _mappingpatterns_39_ in + let rl := bool_bits_backwards _mappingpatterns_38_ in + let aq := bool_bits_backwards _mappingpatterns_37_ in + STORECON + ((aq, rl, rs2, rs1, size, rd)) + else if ((andb + (let _mappingpatterns_40_ : mword 5 := subrange_vec_dec v__7 31 27 in + let _mappingpatterns_43_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_42_ : mword 1 := subrange_vec_dec v__7 25 25 in + let _mappingpatterns_41_ : mword 1 := subrange_vec_dec v__7 26 26 in + let _mappingpatterns_40_ : mword 5 := subrange_vec_dec v__7 31 27 in + andb (size_bits_backwards_matches _mappingpatterns_43_) + (if ((size_bits_backwards_matches _mappingpatterns_43_)) then + let size := size_bits_backwards _mappingpatterns_43_ in + andb (bool_bits_backwards_matches _mappingpatterns_42_) + (if ((bool_bits_backwards_matches _mappingpatterns_42_)) then + let rl := bool_bits_backwards _mappingpatterns_42_ in + andb (bool_bits_backwards_matches _mappingpatterns_41_) + (if ((bool_bits_backwards_matches _mappingpatterns_41_)) then + let aq := bool_bits_backwards _mappingpatterns_41_ in + andb (encdec_amoop_backwards_matches _mappingpatterns_40_) + (if ((encdec_amoop_backwards_matches _mappingpatterns_40_)) then + let op := encdec_amoop_backwards _mappingpatterns_40_ in + true + else false) + else false) + else false) + else false)) + (andb + (eq_vec (subrange_vec_dec v__7 14 14) (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))))) then + let _mappingpatterns_40_ : mword 5 := subrange_vec_dec v__7 31 27 in + let rs2 : mword 5 := subrange_vec_dec v__7 24 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let _mappingpatterns_43_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_42_ : mword 1 := subrange_vec_dec v__7 25 25 in + let _mappingpatterns_41_ : mword 1 := subrange_vec_dec v__7 26 26 in + let _mappingpatterns_40_ : mword 5 := subrange_vec_dec v__7 31 27 in + let size := size_bits_backwards _mappingpatterns_43_ in + let rl := bool_bits_backwards _mappingpatterns_42_ in + let aq := bool_bits_backwards _mappingpatterns_41_ in + let op := encdec_amoop_backwards _mappingpatterns_40_ in + AMO + ((op, aq, rl, rs2, rs1, size, rd)) + else if ((andb + (let _mappingpatterns_45_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_44_ : mword 1 := subrange_vec_dec v__7 14 14 in + andb (encdec_csrop_backwards_matches _mappingpatterns_45_) + (if ((encdec_csrop_backwards_matches _mappingpatterns_45_)) then + let op := encdec_csrop_backwards _mappingpatterns_45_ in + andb (bool_bits_backwards_matches _mappingpatterns_44_) + (if ((bool_bits_backwards_matches _mappingpatterns_44_)) then + let is_imm := bool_bits_backwards _mappingpatterns_44_ in + true + else false) + else false)) + (eq_vec (subrange_vec_dec v__7 6 0) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let csr : mword 12 := subrange_vec_dec v__7 31 20 in + let rs1 : mword 5 := subrange_vec_dec v__7 19 15 in + let rd : mword 5 := subrange_vec_dec v__7 11 7 in + let csr : mword 12 := subrange_vec_dec v__7 31 20 in + let _mappingpatterns_45_ : mword 2 := subrange_vec_dec v__7 13 12 in + let _mappingpatterns_44_ : mword 1 := subrange_vec_dec v__7 14 14 in + let op := encdec_csrop_backwards _mappingpatterns_45_ in + let is_imm := bool_bits_backwards _mappingpatterns_44_ in + CSR + ((csr, rs1, rd, is_imm, op)) + else if ((eq_vec v__7 + (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] + : mword 32))) then + STOP_FETCHING + (tt) + else if ((eq_vec v__7 + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] + : mword 32))) then + THREAD_START + (tt) + else ILLEGAL (v__7). + +Definition encdec_forwards_matches (arg_ : ast) +: bool := + + match arg_ with + | UTYPE (imm,rd,op) => true + | RISCV_JAL (v__227,rd) => + if ((eq_vec (subrange_vec_dec v__227 0 0) (vec_of_bits [B0] : mword (0 - 0 + 1)))) then true + else + let g__36 := RISCV_JAL ((v__227, rd)) in + false + | RISCV_JALR (imm,rs1,rd) => true + | BTYPE (v__229,rs2,rs1,op) => + if ((eq_vec (subrange_vec_dec v__229 0 0) (vec_of_bits [B0] : mword (0 - 0 + 1)))) then true + else + let g__36 := BTYPE ((v__229, rs2, rs1, op)) in + false + | ITYPE (imm,rs1,rd,op) => true + | SHIFTIOP (shamt,rs1,rd,RISCV_SLLI) => true + | SHIFTIOP (shamt,rs1,rd,RISCV_SRLI) => true + | SHIFTIOP (shamt,rs1,rd,RISCV_SRAI) => true + | RTYPE (rs2,rs1,rd,RISCV_ADD) => true + | RTYPE (rs2,rs1,rd,RISCV_SUB) => true + | RTYPE (rs2,rs1,rd,RISCV_SLL) => true + | RTYPE (rs2,rs1,rd,RISCV_SLT) => true + | RTYPE (rs2,rs1,rd,RISCV_SLTU) => true + | RTYPE (rs2,rs1,rd,RISCV_XOR) => true + | RTYPE (rs2,rs1,rd,RISCV_SRL) => true + | RTYPE (rs2,rs1,rd,RISCV_SRA) => true + | RTYPE (rs2,rs1,rd,RISCV_OR) => true + | RTYPE (rs2,rs1,rd,RISCV_AND) => true + | LOAD (imm,rs1,rd,is_unsigned,size,false,false) => + if ((orb (neq_vec (size_bits_forwards size) (vec_of_bits [B1;B1] : mword 2)) + (negb is_unsigned))) then + true + else + let g__36 := LOAD ((imm, rs1, rd, is_unsigned, size, false, false)) in + false + | STORE (v__231,rs2,rs1,size,false,false) => true + | ADDIW (imm,rs1,rd) => true + | SHIFTW (shamt,rs1,rd,RISCV_SLLI) => true + | SHIFTW (shamt,rs1,rd,RISCV_SRLI) => true + | SHIFTW (shamt,rs1,rd,RISCV_SRAI) => true + | RTYPEW (rs2,rs1,rd,RISCV_ADDW) => true + | RTYPEW (rs2,rs1,rd,RISCV_SUBW) => true + | RTYPEW (rs2,rs1,rd,RISCV_SLLW) => true + | RTYPEW (rs2,rs1,rd,RISCV_SRLW) => true + | RTYPEW (rs2,rs1,rd,RISCV_SRAW) => true + | SHIFTIWOP (shamt,rs1,rd,RISCV_SLLIW) => true + | SHIFTIWOP (shamt,rs1,rd,RISCV_SRLIW) => true + | SHIFTIWOP (shamt,rs1,rd,RISCV_SRAIW) => true + | MUL (rs2,rs1,rd,high,signed1,signed2) => true + | DIV (rs2,rs1,rd,s) => true + | REM (rs2,rs1,rd,s) => true + | MULW (rs2,rs1,rd) => true + | DIVW (rs2,rs1,rd,s) => true + | REMW (rs2,rs1,rd,s) => true + | FENCE (pred,succ) => true + | FENCE_TSO (pred,succ) => true + | FENCEI (tt) => true + | ECALL (tt) => true + | MRET (tt) => true + | SRET (tt) => true + | EBREAK (tt) => true + | WFI (tt) => true + | SFENCE_VMA (rs1,rs2) => true + | LOADRES (aq,rl,rs1,size,rd) => true + | STORECON (aq,rl,rs2,rs1,size,rd) => true + | AMO (op,aq,rl,rs2,rs1,size,rd) => true + | CSR (csr,rs1,rd,is_imm,op) => true + | STOP_FETCHING (tt) => true + | THREAD_START (tt) => true + | ILLEGAL (s) => true + | g__36 => false + end. + +Definition encdec_backwards_matches (arg_ : mword 32) +: bool := + + let v__232 := arg_ in + if ((let _mappingpatterns_0_ : mword 7 := subrange_vec_dec v__232 6 0 in + andb (encdec_uop_backwards_matches _mappingpatterns_0_) + (if ((encdec_uop_backwards_matches _mappingpatterns_0_)) then + let op := encdec_uop_backwards _mappingpatterns_0_ in + true + else false))) then + let _mappingpatterns_0_ : mword 7 := subrange_vec_dec v__232 6 0 in + let op := encdec_uop_backwards _mappingpatterns_0_ in + true + else if ((eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B1;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B1;B1;B0;B0;B1;B1;B1] : mword (6 - 0 + 1))))) then + true + else if ((andb + (let _mappingpatterns_1_ : mword 3 := subrange_vec_dec v__232 14 12 in + andb (encdec_bop_backwards_matches _mappingpatterns_1_) + (if ((encdec_bop_backwards_matches _mappingpatterns_1_)) then + let op := encdec_bop_backwards _mappingpatterns_1_ in + true + else false)) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B1;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let _mappingpatterns_1_ : mword 3 := subrange_vec_dec v__232 14 12 in + let op := encdec_bop_backwards _mappingpatterns_1_ in + true + else if ((andb + (let _mappingpatterns_2_ : mword 3 := subrange_vec_dec v__232 14 12 in + andb (encdec_iop_backwards_matches _mappingpatterns_2_) + (if ((encdec_iop_backwards_matches _mappingpatterns_2_)) then + let op := encdec_iop_backwards _mappingpatterns_2_ in + true + else false)) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let _mappingpatterns_2_ : mword 3 := subrange_vec_dec v__232 14 12 in + let op := encdec_iop_backwards _mappingpatterns_2_ in + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 26) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 26) + (vec_of_bits [B0;B1;B0;B0;B0;B0] : mword (31 - 26 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B1;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B1;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B1;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B1;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (let _mappingpatterns_4_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_3_ : mword 1 := subrange_vec_dec v__232 14 14 in + andb (size_bits_backwards_matches _mappingpatterns_4_) + (if ((size_bits_backwards_matches _mappingpatterns_4_)) then + let size := size_bits_backwards _mappingpatterns_4_ in + andb (bool_bits_backwards_matches _mappingpatterns_3_) + (if ((bool_bits_backwards_matches _mappingpatterns_3_)) then + let is_unsigned := bool_bits_backwards _mappingpatterns_3_ in + orb (neq_vec (size_bits_forwards size) (vec_of_bits [B1;B1] : mword 2)) + (negb is_unsigned) + else false) + else false)) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let _mappingpatterns_4_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_3_ : mword 1 := subrange_vec_dec v__232 14 14 in + let size := size_bits_backwards _mappingpatterns_4_ in + let is_unsigned := bool_bits_backwards _mappingpatterns_3_ in + true + else if ((andb + (let _mappingpatterns_5_ : mword 2 := subrange_vec_dec v__232 13 12 in + andb (size_bits_backwards_matches _mappingpatterns_5_) + (if ((size_bits_backwards_matches _mappingpatterns_5_)) then + let size := size_bits_backwards _mappingpatterns_5_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 14 14) (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B0;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let _mappingpatterns_5_ : mword 2 := subrange_vec_dec v__232 13 12 in + let size := size_bits_backwards _mappingpatterns_5_ in + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B1;B0;B0;B0;B0;B0] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B1;B0;B1] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B0;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (let _mappingpatterns_6_ : bits 3 := subrange_vec_dec v__232 14 12 in + andb (encdec_mul_op_backwards_matches _mappingpatterns_6_) + (if ((encdec_mul_op_backwards_matches _mappingpatterns_6_)) then + let '(high, signed1, signed2) := encdec_mul_op_backwards _mappingpatterns_6_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1)))))) then + let _mappingpatterns_6_ : bits 3 := subrange_vec_dec v__232 14 12 in + let '(high, signed1, signed2) := encdec_mul_op_backwards _mappingpatterns_6_ in + true + else if ((andb + (let _mappingpatterns_7_ : mword 1 := subrange_vec_dec v__232 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_7_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_7_)) then + let s := bool_not_bits_backwards _mappingpatterns_7_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 13) + (vec_of_bits [B1;B0] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let _mappingpatterns_7_ : mword 1 := subrange_vec_dec v__232 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_7_ in + true + else if ((andb + (let _mappingpatterns_8_ : mword 1 := subrange_vec_dec v__232 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_8_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_8_)) then + let s := bool_not_bits_backwards _mappingpatterns_8_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 13) + (vec_of_bits [B1;B1] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let _mappingpatterns_8_ : mword 1 := subrange_vec_dec v__232 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_8_ in + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 12) + (vec_of_bits [B0;B0;B0] : mword (14 - 12 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (let _mappingpatterns_9_ : mword 1 := subrange_vec_dec v__232 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_9_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_9_)) then + let s := bool_not_bits_backwards _mappingpatterns_9_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 13) + (vec_of_bits [B1;B0] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let _mappingpatterns_9_ : mword 1 := subrange_vec_dec v__232 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_9_ in + true + else if ((andb + (let _mappingpatterns_10_ : mword 1 := subrange_vec_dec v__232 12 12 in + andb (bool_not_bits_backwards_matches _mappingpatterns_10_) + (if ((bool_not_bits_backwards_matches _mappingpatterns_10_)) then + let s := bool_not_bits_backwards _mappingpatterns_10_ in + true + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B1] : mword (31 - 25 + 1))) + (andb + (eq_vec (subrange_vec_dec v__232 14 13) + (vec_of_bits [B1;B1] : mword (14 - 13 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B1;B1;B0;B1;B1] : mword (6 - 0 + 1))))))) then + let _mappingpatterns_10_ : mword 1 := subrange_vec_dec v__232 12 12 in + let s := bool_not_bits_backwards _mappingpatterns_10_ in + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 28) + (vec_of_bits [B0;B0;B0;B0] : mword (31 - 28 + 1))) + (eq_vec (subrange_vec_dec v__232 19 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : mword (19 - 0 + 1))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 28) + (vec_of_bits [B1;B0;B0;B0] : mword (31 - 28 + 1))) + (eq_vec (subrange_vec_dec v__232 19 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : mword (19 - 0 + 1))))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1] + : mword 32))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] + : mword 32))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__232 31 25) + (vec_of_bits [B0;B0;B0;B1;B0;B0;B1] : mword (31 - 25 + 1))) + (eq_vec (subrange_vec_dec v__232 14 0) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1] : mword (14 - 0 + 1))))) + then + true + else if sumbool_of_bool ((andb + (let _mappingpatterns_13_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_12_ : mword 1 := subrange_vec_dec v__232 25 25 in + let _mappingpatterns_11_ : mword 1 := subrange_vec_dec v__232 26 26 in + andb (size_bits_backwards_matches _mappingpatterns_13_) + (if ((size_bits_backwards_matches _mappingpatterns_13_)) then + let size := size_bits_backwards _mappingpatterns_13_ in + andb (bool_bits_backwards_matches _mappingpatterns_12_) + (if ((bool_bits_backwards_matches _mappingpatterns_12_)) then + let rl := bool_bits_backwards _mappingpatterns_12_ in + andb (bool_bits_backwards_matches _mappingpatterns_11_) + (if ((bool_bits_backwards_matches _mappingpatterns_11_)) + then + let aq := bool_bits_backwards _mappingpatterns_11_ in + true + else false) + else false) + else false)) + (andb + (Z.eqb (projT1 (regbits_to_regno (subrange_vec_dec v__232 31 27))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)))) + (andb + (Z.eqb + (projT1 (regbits_to_regno (subrange_vec_dec v__232 24 20))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B0;B0] : mword 5)))) + (andb + (eq_vec (subrange_vec_dec v__232 14 14) + (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))))))) + then + let _mappingpatterns_13_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_12_ : mword 1 := subrange_vec_dec v__232 25 25 in + let _mappingpatterns_11_ : mword 1 := subrange_vec_dec v__232 26 26 in + let size := size_bits_backwards _mappingpatterns_13_ in + let rl := bool_bits_backwards _mappingpatterns_12_ in + let aq := bool_bits_backwards _mappingpatterns_11_ in + true + else if sumbool_of_bool ((andb + (let _mappingpatterns_16_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_15_ : mword 1 := subrange_vec_dec v__232 25 25 in + let _mappingpatterns_14_ : mword 1 := subrange_vec_dec v__232 26 26 in + andb (size_bits_backwards_matches _mappingpatterns_16_) + (if ((size_bits_backwards_matches _mappingpatterns_16_)) then + let size := size_bits_backwards _mappingpatterns_16_ in + andb (bool_bits_backwards_matches _mappingpatterns_15_) + (if ((bool_bits_backwards_matches _mappingpatterns_15_)) then + let rl := bool_bits_backwards _mappingpatterns_15_ in + andb (bool_bits_backwards_matches _mappingpatterns_14_) + (if ((bool_bits_backwards_matches _mappingpatterns_14_)) + then + let aq := bool_bits_backwards _mappingpatterns_14_ in + true + else false) + else false) + else false)) + (andb + (Z.eqb (projT1 (regbits_to_regno (subrange_vec_dec v__232 31 27))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B1;B1] : mword 5)))) + (andb + (eq_vec (subrange_vec_dec v__232 14 14) + (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1))))))) + then + let _mappingpatterns_16_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_15_ : mword 1 := subrange_vec_dec v__232 25 25 in + let _mappingpatterns_14_ : mword 1 := subrange_vec_dec v__232 26 26 in + let size := size_bits_backwards _mappingpatterns_16_ in + let rl := bool_bits_backwards _mappingpatterns_15_ in + let aq := bool_bits_backwards _mappingpatterns_14_ in + true + else if ((andb + (let _mappingpatterns_17_ : mword 5 := subrange_vec_dec v__232 31 27 in + let _mappingpatterns_20_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_19_ : mword 1 := subrange_vec_dec v__232 25 25 in + let _mappingpatterns_18_ : mword 1 := subrange_vec_dec v__232 26 26 in + let _mappingpatterns_17_ : mword 5 := subrange_vec_dec v__232 31 27 in + andb (size_bits_backwards_matches _mappingpatterns_20_) + (if ((size_bits_backwards_matches _mappingpatterns_20_)) then + let size := size_bits_backwards _mappingpatterns_20_ in + andb (bool_bits_backwards_matches _mappingpatterns_19_) + (if ((bool_bits_backwards_matches _mappingpatterns_19_)) then + let rl := bool_bits_backwards _mappingpatterns_19_ in + andb (bool_bits_backwards_matches _mappingpatterns_18_) + (if ((bool_bits_backwards_matches _mappingpatterns_18_)) then + let aq := bool_bits_backwards _mappingpatterns_18_ in + andb (encdec_amoop_backwards_matches _mappingpatterns_17_) + (if ((encdec_amoop_backwards_matches _mappingpatterns_17_)) then + let op := encdec_amoop_backwards _mappingpatterns_17_ in + true + else false) + else false) + else false) + else false)) + (andb + (eq_vec (subrange_vec_dec v__232 14 14) (vec_of_bits [B0] : mword (14 - 14 + 1))) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B0;B1;B0;B1;B1;B1;B1] : mword (6 - 0 + 1)))))) then + let _mappingpatterns_17_ : mword 5 := subrange_vec_dec v__232 31 27 in + let _mappingpatterns_20_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_19_ : mword 1 := subrange_vec_dec v__232 25 25 in + let _mappingpatterns_18_ : mword 1 := subrange_vec_dec v__232 26 26 in + let _mappingpatterns_17_ : mword 5 := subrange_vec_dec v__232 31 27 in + let size := size_bits_backwards _mappingpatterns_20_ in + let rl := bool_bits_backwards _mappingpatterns_19_ in + let aq := bool_bits_backwards _mappingpatterns_18_ in + let op := encdec_amoop_backwards _mappingpatterns_17_ in + true + else if ((andb + (let _mappingpatterns_22_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_21_ : mword 1 := subrange_vec_dec v__232 14 14 in + andb (encdec_csrop_backwards_matches _mappingpatterns_22_) + (if ((encdec_csrop_backwards_matches _mappingpatterns_22_)) then + let op := encdec_csrop_backwards _mappingpatterns_22_ in + andb (bool_bits_backwards_matches _mappingpatterns_21_) + (if ((bool_bits_backwards_matches _mappingpatterns_21_)) then + let is_imm := bool_bits_backwards _mappingpatterns_21_ in + true + else false) + else false)) + (eq_vec (subrange_vec_dec v__232 6 0) + (vec_of_bits [B1;B1;B1;B0;B0;B1;B1] : mword (6 - 0 + 1))))) then + let _mappingpatterns_22_ : mword 2 := subrange_vec_dec v__232 13 12 in + let _mappingpatterns_21_ : mword 1 := subrange_vec_dec v__232 14 14 in + let op := encdec_csrop_backwards _mappingpatterns_22_ in + let is_imm := bool_bits_backwards _mappingpatterns_21_ in + true + else if ((eq_vec v__232 + (vec_of_bits [B1;B1;B1;B1;B1;B0;B1;B0;B1;B1;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] + : mword 32))) then + true + else if ((eq_vec v__232 + (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1] + : mword 32))) then + true + else true. + +Definition encdec_compressed_forwards (arg_ : ast) +: M (mword 16) := + + (match arg_ with + | C_NOP (tt) => + returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B0;B1] : mword 2))))) + : mword (3 + (1 + (5 + (5 + 2))))) + | C_ADDI4SPN (rd,v__452) => + let nz96 : bits 4 := subrange_vec_dec v__452 7 4 in + let nz96 : bits 4 := subrange_vec_dec v__452 7 4 in + let nz54 : bits 2 := subrange_vec_dec v__452 3 2 in + let nz3 : bits 1 := subrange_vec_dec v__452 1 1 in + let nz2 : bits 1 := subrange_vec_dec v__452 0 0 in + returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (nz54 : bits 2) + (concat_vec (nz96 : bits 4) + (concat_vec (nz2 : bits 1) + (concat_vec (nz3 : bits 1) + (concat_vec (rd : cregbits) (vec_of_bits [B0;B0] : mword 2))))))) + : mword 16) + | C_LW (v__453,rs1,rd) => + let ui6 : bits 1 := subrange_vec_dec v__453 4 4 in + let ui6 : bits 1 := subrange_vec_dec v__453 4 4 in + let ui53 : bits 3 := subrange_vec_dec v__453 3 1 in + let ui2 : bits 1 := subrange_vec_dec v__453 0 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B0] : mword 3) + (concat_vec (ui53 : bits 3) + (concat_vec (rs1 : cregbits) + (concat_vec (ui2 : bits 1) + (concat_vec (ui6 : bits 1) + (concat_vec (rd : cregbits) (vec_of_bits [B0;B0] : mword 2))))))) + : mword 16) + | C_LD (v__454,rs1,rd) => + let ui76 : bits 2 := subrange_vec_dec v__454 4 3 in + let ui76 : bits 2 := subrange_vec_dec v__454 4 3 in + let ui53 : bits 3 := subrange_vec_dec v__454 2 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3) + (concat_vec (ui53 : bits 3) + (concat_vec (rs1 : cregbits) + (concat_vec (ui76 : bits 2) + (concat_vec (rd : cregbits) (vec_of_bits [B0;B0] : mword 2)))))) + : mword 16) + | C_SW (v__455,rs1,rs2) => + let ui6 : bits 1 := subrange_vec_dec v__455 4 4 in + let ui6 : bits 1 := subrange_vec_dec v__455 4 4 in + let ui53 : bits 3 := subrange_vec_dec v__455 3 1 in + let ui2 : bits 1 := subrange_vec_dec v__455 0 0 in + returnm ((concat_vec (vec_of_bits [B1;B1;B0] : mword 3) + (concat_vec (ui53 : bits 3) + (concat_vec (rs1 : cregbits) + (concat_vec (ui2 : bits 1) + (concat_vec (ui6 : bits 1) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B0] : mword 2))))))) + : mword 16) + | C_SD (v__456,rs1,rs2) => + let ui76 : bits 2 := subrange_vec_dec v__456 4 3 in + let ui76 : bits 2 := subrange_vec_dec v__456 4 3 in + let ui53 : bits 3 := subrange_vec_dec v__456 2 0 in + returnm ((concat_vec (vec_of_bits [B1;B1;B1] : mword 3) + (concat_vec (ui53 : bits 3) + (concat_vec (rs1 : bits 3) + (concat_vec (ui76 : bits 2) + (concat_vec (rs2 : bits 3) (vec_of_bits [B0;B0] : mword 2)))))) + : mword 16) + | C_ADDI (v__457,rsd) => + let nzi5 : bits 1 := subrange_vec_dec v__457 5 5 in + let nzi5 : bits 1 := subrange_vec_dec v__457 5 5 in + let nzi40 : bits 5 := subrange_vec_dec v__457 4 0 in + returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (nzi5 : bits 1) + (concat_vec (rsd : regbits) + (concat_vec (nzi40 : bits 5) (vec_of_bits [B0;B1] : mword 2))))) + : mword 16) + | C_ADDIW (v__458,rsd) => + let imm5 : bits 1 := subrange_vec_dec v__458 5 5 in + let imm5 : bits 1 := subrange_vec_dec v__458 5 5 in + let imm40 : bits 5 := subrange_vec_dec v__458 4 0 in + returnm ((concat_vec (vec_of_bits [B0;B0;B1] : mword 3) + (concat_vec (imm5 : bits 1) + (concat_vec (rsd : regbits) + (concat_vec (imm40 : bits 5) (vec_of_bits [B0;B1] : mword 2))))) + : mword 16) + | C_LI (v__459,rd) => + let imm5 : bits 1 := subrange_vec_dec v__459 5 5 in + let imm5 : bits 1 := subrange_vec_dec v__459 5 5 in + let imm40 : bits 5 := subrange_vec_dec v__459 4 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B0] : mword 3) + (concat_vec (imm5 : bits 1) + (concat_vec (rd : regbits) + (concat_vec (imm40 : bits 5) (vec_of_bits [B0;B1] : mword 2))))) + : mword 16) + | C_ADDI16SP (v__460) => + let nzi9 : bits 1 := subrange_vec_dec v__460 5 5 in + let nzi9 : bits 1 := subrange_vec_dec v__460 5 5 in + let nzi87 : bits 2 := subrange_vec_dec v__460 4 3 in + let nzi6 : bits 1 := subrange_vec_dec v__460 2 2 in + let nzi5 : bits 1 := subrange_vec_dec v__460 1 1 in + let nzi4 : bits 1 := subrange_vec_dec v__460 0 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3) + (concat_vec (nzi9 : bits 1) + (concat_vec (vec_of_bits [B0;B0;B0;B1;B0] : mword 5) + (concat_vec (nzi4 : bits 1) + (concat_vec (nzi6 : bits 1) + (concat_vec (nzi87 : bits 2) + (concat_vec (nzi5 : bits 1) (vec_of_bits [B0;B1] : mword 2)))))))) + : mword 16) + | C_LUI (v__461,rd) => + let imm17 : bits 1 := subrange_vec_dec v__461 5 5 in + let imm17 : bits 1 := subrange_vec_dec v__461 5 5 in + let imm1612 : bits 5 := subrange_vec_dec v__461 4 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3) + (concat_vec (imm17 : bits 1) + (concat_vec (rd : regbits) + (concat_vec (imm1612 : bits 5) (vec_of_bits [B0;B1] : mword 2))))) + : mword 16) + | C_SRLI (v__462,rsd) => + let nzui5 : bits 1 := subrange_vec_dec v__462 5 5 in + let nzui5 : bits 1 := subrange_vec_dec v__462 5 5 in + let nzui40 : bits 5 := subrange_vec_dec v__462 4 0 in + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (nzui5 : bits 1) + (concat_vec (vec_of_bits [B0;B0] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (nzui40 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))) + : mword 16) + | C_SRAI (v__463,rsd) => + let nzui5 : bits 1 := subrange_vec_dec v__463 5 5 in + let nzui5 : bits 1 := subrange_vec_dec v__463 5 5 in + let nzui40 : bits 5 := subrange_vec_dec v__463 4 0 in + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (nzui5 : bits 1) + (concat_vec (vec_of_bits [B0;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (nzui40 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))) + : mword 16) + | C_ANDI (v__464,rsd) => + let i5 : bits 1 := subrange_vec_dec v__464 5 5 in + let i5 : bits 1 := subrange_vec_dec v__464 5 5 in + let i40 : bits 5 := subrange_vec_dec v__464 4 0 in + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (i5 : bits 1) + (concat_vec (vec_of_bits [B1;B0] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (i40 : bits 5) (vec_of_bits [B0;B1] : mword 2)))))) + : mword 16) + | C_SUB (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (vec_of_bits [B0;B0] : mword 2) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B1] : mword 2))))))) + : mword (3 + (1 + (2 + (3 + (2 + (3 + 2))))))) + | C_XOR (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (vec_of_bits [B0;B1] : mword 2) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B1] : mword 2))))))) + : mword (3 + (1 + (2 + (3 + (2 + (3 + 2))))))) + | C_OR (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (vec_of_bits [B1;B0] : mword 2) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B1] : mword 2))))))) + : mword (3 + (1 + (2 + (3 + (2 + (3 + 2))))))) + | C_AND (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B1] : mword 2))))))) + : mword (3 + (1 + (2 + (3 + (2 + (3 + 2))))))) + | C_SUBW (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (vec_of_bits [B0;B0] : mword 2) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B1] : mword 2))))))) + : mword (3 + (1 + (2 + (3 + (2 + (3 + 2))))))) + | C_ADDW (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B1;B1] : mword 2) + (concat_vec (rsd : cregbits) + (concat_vec (vec_of_bits [B0;B1] : mword 2) + (concat_vec (rs2 : cregbits) (vec_of_bits [B0;B1] : mword 2))))))) + : mword (3 + (1 + (2 + (3 + (2 + (3 + 2))))))) + | C_J (v__465) => + let i11 : bits 1 := subrange_vec_dec v__465 10 10 in + let i98 : bits 2 := subrange_vec_dec v__465 8 7 in + let i7 : bits 1 := subrange_vec_dec v__465 6 6 in + let i6 : bits 1 := subrange_vec_dec v__465 5 5 in + let i5 : bits 1 := subrange_vec_dec v__465 4 4 in + let i4 : bits 1 := subrange_vec_dec v__465 3 3 in + let i31 : bits 3 := subrange_vec_dec v__465 2 0 in + let i11 : bits 1 := subrange_vec_dec v__465 10 10 in + let i10 : bits 1 := subrange_vec_dec v__465 9 9 in + returnm ((concat_vec (vec_of_bits [B1;B0;B1] : mword 3) + (concat_vec (i11 : bits 1) + (concat_vec (i4 : bits 1) + (concat_vec (i98 : bits 2) + (concat_vec (i10 : bits 1) + (concat_vec (i6 : bits 1) + (concat_vec (i7 : bits 1) + (concat_vec (i31 : bits 3) + (concat_vec (i5 : bits 1) (vec_of_bits [B0;B1] : mword 2)))))))))) + : mword 16) + | C_BEQZ (v__466,rs) => + let i8 : bits 1 := subrange_vec_dec v__466 7 7 in + let i8 : bits 1 := subrange_vec_dec v__466 7 7 in + let i76 : bits 2 := subrange_vec_dec v__466 6 5 in + let i5 : bits 1 := subrange_vec_dec v__466 4 4 in + let i43 : bits 2 := subrange_vec_dec v__466 3 2 in + let i21 : bits 2 := subrange_vec_dec v__466 1 0 in + returnm ((concat_vec (vec_of_bits [B1;B1;B0] : mword 3) + (concat_vec (i8 : bits 1) + (concat_vec (i43 : bits 2) + (concat_vec (rs : cregbits) + (concat_vec (i76 : bits 2) + (concat_vec (i21 : bits 2) + (concat_vec (i5 : bits 1) (vec_of_bits [B0;B1] : mword 2)))))))) + : mword 16) + | C_BNEZ (v__467,rs) => + let i8 : bits 1 := subrange_vec_dec v__467 7 7 in + let i8 : bits 1 := subrange_vec_dec v__467 7 7 in + let i76 : bits 2 := subrange_vec_dec v__467 6 5 in + let i5 : bits 1 := subrange_vec_dec v__467 4 4 in + let i43 : bits 2 := subrange_vec_dec v__467 3 2 in + let i21 : bits 2 := subrange_vec_dec v__467 1 0 in + returnm ((concat_vec (vec_of_bits [B1;B1;B1] : mword 3) + (concat_vec (i8 : bits 1) + (concat_vec (i43 : bits 2) + (concat_vec (rs : cregbits) + (concat_vec (i76 : bits 2) + (concat_vec (i21 : bits 2) + (concat_vec (i5 : bits 1) (vec_of_bits [B0;B1] : mword 2)))))))) + : mword 16) + | C_SLLI (v__468,rsd) => + let nzui5 : bits 1 := subrange_vec_dec v__468 5 5 in + let nzui5 : bits 1 := subrange_vec_dec v__468 5 5 in + let nzui40 : bits 5 := subrange_vec_dec v__468 4 0 in + returnm ((concat_vec (vec_of_bits [B0;B0;B0] : mword 3) + (concat_vec (nzui5 : bits 1) + (concat_vec (rsd : regbits) + (concat_vec (nzui40 : bits 5) (vec_of_bits [B1;B0] : mword 2))))) + : mword 16) + | C_LWSP (v__469,rd) => + let ui76 : bits 2 := subrange_vec_dec v__469 5 4 in + let ui76 : bits 2 := subrange_vec_dec v__469 5 4 in + let ui5 : bits 1 := subrange_vec_dec v__469 3 3 in + let ui42 : bits 3 := subrange_vec_dec v__469 2 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B0] : mword 3) + (concat_vec (ui5 : bits 1) + (concat_vec (rd : regbits) + (concat_vec (ui42 : bits 3) + (concat_vec (ui76 : bits 2) (vec_of_bits [B1;B0] : mword 2)))))) + : mword 16) + | C_LDSP (v__470,rd) => + let ui86 : bits 3 := subrange_vec_dec v__470 5 3 in + let ui86 : bits 3 := subrange_vec_dec v__470 5 3 in + let ui5 : bits 1 := subrange_vec_dec v__470 2 2 in + let ui43 : bits 2 := subrange_vec_dec v__470 1 0 in + returnm ((concat_vec (vec_of_bits [B0;B1;B1] : mword 3) + (concat_vec (ui5 : bits 1) + (concat_vec (rd : regbits) + (concat_vec (ui43 : bits 2) + (concat_vec (ui86 : bits 3) (vec_of_bits [B1;B0] : mword 2)))))) + : mword 16) + | C_SWSP (v__471,rs2) => + let ui76 : bits 2 := subrange_vec_dec v__471 5 4 in + let ui76 : bits 2 := subrange_vec_dec v__471 5 4 in + let ui52 : bits 4 := subrange_vec_dec v__471 3 0 in + returnm ((concat_vec (vec_of_bits [B1;B1;B0] : mword 3) + (concat_vec (ui52 : bits 4) + (concat_vec (ui76 : bits 2) + (concat_vec (rs2 : regbits) (vec_of_bits [B1;B0] : mword 2))))) + : mword 16) + | C_SDSP (v__472,rs2) => + let ui86 : bits 3 := subrange_vec_dec v__472 5 3 in + let ui86 : bits 3 := subrange_vec_dec v__472 5 3 in + let ui53 : bits 3 := subrange_vec_dec v__472 2 0 in + returnm ((concat_vec (vec_of_bits [B1;B1;B1] : mword 3) + (concat_vec (ui53 : bits 3) + (concat_vec (ui86 : bits 3) + (concat_vec (rs2 : regbits) (vec_of_bits [B1;B0] : mword 2))))) + : mword 16) + | C_JR (rs1) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (rs1 : regbits) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B0] : mword 2))))) + : mword (3 + (1 + (5 + (5 + 2))))) + | C_JALR (rs1) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (rs1 : regbits) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B0] : mword 2))))) + : mword (3 + (1 + (5 + (5 + 2))))) + | C_MV (rd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B0] : mword 1) + (concat_vec (rd : regbits) + (concat_vec (rs2 : regbits) (vec_of_bits [B1;B0] : mword 2))))) + : mword (3 + (1 + (5 + (5 + 2))))) + | C_EBREAK (tt) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (concat_vec (vec_of_bits [B0;B0;B0;B0;B0] : mword 5) + (vec_of_bits [B1;B0] : mword 2))))) + : mword (3 + (1 + (5 + (5 + 2))))) + | C_ADD (rsd,rs2) => + returnm ((concat_vec (vec_of_bits [B1;B0;B0] : mword 3) + (concat_vec (vec_of_bits [B1] : mword 1) + (concat_vec (rsd : regbits) + (concat_vec (rs2 : regbits) (vec_of_bits [B1;B0] : mword 2))))) + : mword (3 + (1 + (5 + (5 + 2))))) + | C_ILLEGAL (s) => returnm (s : mword 16) + | _ => exit tt : M (mword 16) + end) + : M (mword 16). + +Definition encdec_compressed_backwards (arg_ : mword 16) +: ast := + + let v__473 := arg_ in + if ((eq_vec v__473 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 16))) + then + C_NOP + (tt) + else if ((andb + (let nz96 : bits 4 := subrange_vec_dec v__473 10 7 in + let nz54 : bits 2 := subrange_vec_dec v__473 12 11 in + let nz3 : bits 1 := subrange_vec_dec v__473 5 5 in + let nz2 : bits 1 := subrange_vec_dec v__473 6 6 in + neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2))) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1))))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))) + then + let rd : cregbits := subrange_vec_dec v__473 4 2 in + let nz96 : bits 4 := subrange_vec_dec v__473 10 7 in + let nz54 : bits 2 := subrange_vec_dec v__473 12 11 in + let nz3 : bits 1 := subrange_vec_dec v__473 5 5 in + let nz2 : bits 1 := subrange_vec_dec v__473 6 6 in + C_ADDI4SPN + ((rd, concat_vec (nz96 : bits 4) + (concat_vec (nz54 : bits 2) (concat_vec (nz3 : bits 1) (nz2 : bits 1))))) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + let ui6 : bits 1 := subrange_vec_dec v__473 5 5 in + let ui53 : bits 3 := subrange_vec_dec v__473 12 10 in + let ui2 : bits 1 := subrange_vec_dec v__473 6 6 in + let rs1 : cregbits := subrange_vec_dec v__473 9 7 in + let rd : cregbits := subrange_vec_dec v__473 4 2 in + C_LW + ((concat_vec (ui6 : bits 1) (concat_vec (ui53 : bits 3) (ui2 : bits 1)), rs1, rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + let ui76 : bits 2 := subrange_vec_dec v__473 6 5 in + let ui53 : bits 3 := subrange_vec_dec v__473 12 10 in + let rs1 : cregbits := subrange_vec_dec v__473 9 7 in + let rd : cregbits := subrange_vec_dec v__473 4 2 in + C_LD + ((concat_vec (ui76 : bits 2) (ui53 : bits 3), rs1, rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + let ui6 : bits 1 := subrange_vec_dec v__473 5 5 in + let ui53 : bits 3 := subrange_vec_dec v__473 12 10 in + let ui2 : bits 1 := subrange_vec_dec v__473 6 6 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + let rs1 : cregbits := subrange_vec_dec v__473 9 7 in + C_SW + ((concat_vec (ui6 : bits 1) (concat_vec (ui53 : bits 3) (ui2 : bits 1)), rs1, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + let ui76 : bits 2 := subrange_vec_dec v__473 6 5 in + let ui53 : bits 3 := subrange_vec_dec v__473 12 10 in + let rs2 : bits 3 := subrange_vec_dec v__473 4 2 in + let rs1 : bits 3 := subrange_vec_dec v__473 9 7 in + C_SD + ((concat_vec (ui76 : bits 2) (ui53 : bits 3), rs1, rs2)) + else if ((andb + (let rsd : regbits := subrange_vec_dec v__473 11 7 in + let nzi5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzi40 : bits 5 := subrange_vec_dec v__473 6 2 in + andb + (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : regbits := subrange_vec_dec v__473 11 7 in + let nzi5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzi40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_ADDI + ((concat_vec (nzi5 : bits 1) (nzi40 : bits 5), rsd)) + else if ((andb + (let rsd : regbits := subrange_vec_dec v__473 11 7 in + neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B0;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : regbits := subrange_vec_dec v__473 11 7 in + let imm5 : bits 1 := subrange_vec_dec v__473 12 12 in + let imm40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_ADDIW + ((concat_vec (imm5 : bits 1) (imm40 : bits 5), rsd)) + else if ((andb + (let rd : regbits := subrange_vec_dec v__473 11 7 in + neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rd : regbits := subrange_vec_dec v__473 11 7 in + let imm5 : bits 1 := subrange_vec_dec v__473 12 12 in + let imm40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_LI + ((concat_vec (imm5 : bits 1) (imm40 : bits 5), rd)) + else if sumbool_of_bool ((andb + (let nzi9 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzi87 : bits 2 := subrange_vec_dec v__473 4 3 in + let nzi6 : bits 1 := subrange_vec_dec v__473 5 5 in + let nzi5 : bits 1 := subrange_vec_dec v__473 2 2 in + let nzi4 : bits 1 := subrange_vec_dec v__473 6 6 in + neq_vec + (concat_vec nzi9 + (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4)))) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1)))))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (andb + (Z.eqb + (projT1 (regbits_to_regno (subrange_vec_dec v__473 11 7))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)))) + (eq_vec (subrange_vec_dec v__473 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then + let nzi9 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzi87 : bits 2 := subrange_vec_dec v__473 4 3 in + let nzi6 : bits 1 := subrange_vec_dec v__473 5 5 in + let nzi5 : bits 1 := subrange_vec_dec v__473 2 2 in + let nzi4 : bits 1 := subrange_vec_dec v__473 6 6 in + C_ADDI16SP + (concat_vec (nzi9 : bits 1) + (concat_vec (nzi87 : bits 2) + (concat_vec (nzi6 : bits 1) (concat_vec (nzi5 : bits 1) (nzi4 : bits 1))))) + else if ((andb + (let rd : regbits := subrange_vec_dec v__473 11 7 in + let imm17 : bits 1 := subrange_vec_dec v__473 12 12 in + let imm1612 : bits 5 := subrange_vec_dec v__473 6 2 in + andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno sp))) + (neq_vec (concat_vec imm17 imm1612) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rd : regbits := subrange_vec_dec v__473 11 7 in + let imm17 : bits 1 := subrange_vec_dec v__473 12 12 in + let imm1612 : bits 5 := subrange_vec_dec v__473 6 2 in + C_LUI + ((concat_vec (imm17 : bits 1) (imm1612 : bits 5), rd)) + else if ((andb + (let nzui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__473 6 2 in + neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 11 10) + (vec_of_bits [B0;B0] : mword (11 - 10 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let nzui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_SRLI + ((concat_vec (nzui5 : bits 1) (nzui40 : bits 5), rsd)) + else if ((andb + (let nzui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__473 6 2 in + neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 11 10) + (vec_of_bits [B0;B1] : mword (11 - 10 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let nzui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_SRAI + ((concat_vec (nzui5 : bits 1) (nzui40 : bits 5), rsd)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 11 10) + (vec_of_bits [B1;B0] : mword (11 - 10 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let i5 : bits 1 := subrange_vec_dec v__473 12 12 in + let i40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_ANDI + ((concat_vec (i5 : bits 1) (i40 : bits 5), rsd)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 6 5) (vec_of_bits [B0;B0] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + C_SUB + ((rsd, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 6 5) (vec_of_bits [B0;B1] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + C_XOR + ((rsd, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 6 5) (vec_of_bits [B1;B0] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + C_OR + ((rsd, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 6 5) (vec_of_bits [B1;B1] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + C_AND + ((rsd, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 10) + (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 6 5) (vec_of_bits [B0;B0] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + C_SUBW + ((rsd, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 10) + (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__473 6 5) (vec_of_bits [B0;B1] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + let rsd : cregbits := subrange_vec_dec v__473 9 7 in + let rs2 : cregbits := subrange_vec_dec v__473 4 2 in + C_ADDW + ((rsd, rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B0;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + let i98 : bits 2 := subrange_vec_dec v__473 10 9 in + let i7 : bits 1 := subrange_vec_dec v__473 6 6 in + let i6 : bits 1 := subrange_vec_dec v__473 7 7 in + let i5 : bits 1 := subrange_vec_dec v__473 2 2 in + let i4 : bits 1 := subrange_vec_dec v__473 11 11 in + let i31 : bits 3 := subrange_vec_dec v__473 5 3 in + let i11 : bits 1 := subrange_vec_dec v__473 12 12 in + let i10 : bits 1 := subrange_vec_dec v__473 8 8 in + C_J + (concat_vec (i11 : bits 1) + (concat_vec (i10 : bits 1) + (concat_vec (i98 : bits 2) + (concat_vec (i7 : bits 1) + (concat_vec (i6 : bits 1) + (concat_vec (i5 : bits 1) (concat_vec (i4 : bits 1) (i31 : bits 3)))))))) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + let rs : cregbits := subrange_vec_dec v__473 9 7 in + let i8 : bits 1 := subrange_vec_dec v__473 12 12 in + let i76 : bits 2 := subrange_vec_dec v__473 6 5 in + let i5 : bits 1 := subrange_vec_dec v__473 2 2 in + let i43 : bits 2 := subrange_vec_dec v__473 11 10 in + let i21 : bits 2 := subrange_vec_dec v__473 4 3 in + C_BEQZ + ((concat_vec (i8 : bits 1) + (concat_vec (i76 : bits 2) + (concat_vec (i5 : bits 1) (concat_vec (i43 : bits 2) (i21 : bits 2)))), rs)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + let rs : cregbits := subrange_vec_dec v__473 9 7 in + let i8 : bits 1 := subrange_vec_dec v__473 12 12 in + let i76 : bits 2 := subrange_vec_dec v__473 6 5 in + let i5 : bits 1 := subrange_vec_dec v__473 2 2 in + let i43 : bits 2 := subrange_vec_dec v__473 11 10 in + let i21 : bits 2 := subrange_vec_dec v__473 4 3 in + C_BNEZ + ((concat_vec (i8 : bits 1) + (concat_vec (i76 : bits 2) + (concat_vec (i5 : bits 1) (concat_vec (i43 : bits 2) (i21 : bits 2)))), rs)) + else if ((andb + (let rsd : regbits := subrange_vec_dec v__473 11 7 in + let nzui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__473 6 2 in + andb + (neq_vec (concat_vec nzui5 nzui40) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + let rsd : regbits := subrange_vec_dec v__473 11 7 in + let nzui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__473 6 2 in + C_SLLI + ((concat_vec (nzui5 : bits 1) (nzui40 : bits 5), rsd)) + else if ((andb + (let rd : regbits := subrange_vec_dec v__473 11 7 in + neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + let ui76 : bits 2 := subrange_vec_dec v__473 3 2 in + let ui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let ui42 : bits 3 := subrange_vec_dec v__473 6 4 in + let rd : regbits := subrange_vec_dec v__473 11 7 in + C_LWSP + ((concat_vec (ui76 : bits 2) (concat_vec (ui5 : bits 1) (ui42 : bits 3)), rd)) + else if ((andb + (let rd : regbits := subrange_vec_dec v__473 11 7 in + neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + let ui86 : bits 3 := subrange_vec_dec v__473 4 2 in + let ui5 : bits 1 := subrange_vec_dec v__473 12 12 in + let ui43 : bits 2 := subrange_vec_dec v__473 6 5 in + let rd : regbits := subrange_vec_dec v__473 11 7 in + C_LDSP + ((concat_vec (ui86 : bits 3) (concat_vec (ui5 : bits 1) (ui43 : bits 2)), rd)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + let ui76 : bits 2 := subrange_vec_dec v__473 8 7 in + let ui52 : bits 4 := subrange_vec_dec v__473 12 9 in + let rs2 : regbits := subrange_vec_dec v__473 6 2 in + C_SWSP + ((concat_vec (ui76 : bits 2) (ui52 : bits 4), rs2)) + else if ((andb + (eq_vec (subrange_vec_dec v__473 15 13) + (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + let ui86 : bits 3 := subrange_vec_dec v__473 9 7 in + let ui53 : bits 3 := subrange_vec_dec v__473 12 10 in + let rs2 : regbits := subrange_vec_dec v__473 6 2 in + C_SDSP + ((concat_vec (ui86 : bits 3) (ui53 : bits 3), rs2)) + else if ((andb + (let rs1 : regbits := subrange_vec_dec v__473 11 7 in + neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__473 15 12) + (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__473 6 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1)))))) then + let rs1 : regbits := subrange_vec_dec v__473 11 7 in + C_JR + (rs1) + else if ((andb + (let rs1 : regbits := subrange_vec_dec v__473 11 7 in + neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__473 15 12) + (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__473 6 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1)))))) then + let rs1 : regbits := subrange_vec_dec v__473 11 7 in + C_JALR + (rs1) + else if ((andb + (let rs2 : regbits := subrange_vec_dec v__473 6 2 in + let rd : regbits := subrange_vec_dec v__473 11 7 in + andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__473 15 12) + (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + let rs2 : regbits := subrange_vec_dec v__473 6 2 in + let rd : regbits := subrange_vec_dec v__473 11 7 in + C_MV + ((rd, rs2)) + else if ((eq_vec v__473 + (vec_of_bits [B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 16))) then + C_EBREAK + (tt) + else if ((andb + (let rsd : regbits := subrange_vec_dec v__473 11 7 in + let rs2 : regbits := subrange_vec_dec v__473 6 2 in + andb (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__473 15 12) + (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__473 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + let rsd : regbits := subrange_vec_dec v__473 11 7 in + let rs2 : regbits := subrange_vec_dec v__473 6 2 in + C_ADD + ((rsd, rs2)) + else C_ILLEGAL (v__473). + +Definition encdec_compressed_forwards_matches (arg_ : ast) +: bool := + + match arg_ with + | C_NOP (tt) => true + | C_ADDI4SPN (rd,v__606) => + if ((let nz96 : bits 4 := subrange_vec_dec v__606 7 4 in + let nz96 : bits 4 := subrange_vec_dec v__606 7 4 in + let nz54 : bits 2 := subrange_vec_dec v__606 3 2 in + let nz3 : bits 1 := subrange_vec_dec v__606 1 1 in + let nz2 : bits 1 := subrange_vec_dec v__606 0 0 in + neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2))) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1)))))) then + true + else + let g__35 := C_ADDI4SPN ((rd, v__606)) in + false + | C_LW (v__607,rs1,rd) => true + | C_LD (v__608,rs1,rd) => true + | C_SW (v__609,rs1,rs2) => true + | C_SD (v__610,rs1,rs2) => true + | C_ADDI (v__611,rsd) => + if ((let nzi5 : bits 1 := subrange_vec_dec v__611 5 5 in + let nzi5 : bits 1 := subrange_vec_dec v__611 5 5 in + let nzi40 : bits 5 := subrange_vec_dec v__611 4 0 in + andb (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__35 := C_ADDI ((v__611, rsd)) in + false + | C_ADDIW (v__612,rsd) => + if ((neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__35 := C_ADDIW ((v__612, rsd)) in + false + | C_LI (v__613,rd) => + if ((neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__35 := C_LI ((v__613, rd)) in + false + | C_ADDI16SP (v__614) => + if ((let nzi9 : bits 1 := subrange_vec_dec v__614 5 5 in + let nzi9 : bits 1 := subrange_vec_dec v__614 5 5 in + let nzi87 : bits 2 := subrange_vec_dec v__614 4 3 in + let nzi6 : bits 1 := subrange_vec_dec v__614 2 2 in + let nzi5 : bits 1 := subrange_vec_dec v__614 1 1 in + let nzi4 : bits 1 := subrange_vec_dec v__614 0 0 in + neq_vec (concat_vec nzi9 (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4)))) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1))))))) then + true + else + let g__35 := C_ADDI16SP (v__614) in + false + | C_LUI (v__615,rd) => + if ((let imm17 : bits 1 := subrange_vec_dec v__615 5 5 in + let imm17 : bits 1 := subrange_vec_dec v__615 5 5 in + let imm1612 : bits 5 := subrange_vec_dec v__615 4 0 in + andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno sp))) + (neq_vec (concat_vec imm17 imm1612) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))))) + then + true + else + let g__35 := C_LUI ((v__615, rd)) in + false + | C_SRLI (v__616,rsd) => + if ((let nzui5 : bits 1 := subrange_vec_dec v__616 5 5 in + let nzui5 : bits 1 := subrange_vec_dec v__616 5 5 in + let nzui40 : bits 5 := subrange_vec_dec v__616 4 0 in + neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))) then + true + else + let g__35 := C_SRLI ((v__616, rsd)) in + false + | C_SRAI (v__617,rsd) => + if ((let nzui5 : bits 1 := subrange_vec_dec v__617 5 5 in + let nzui5 : bits 1 := subrange_vec_dec v__617 5 5 in + let nzui40 : bits 5 := subrange_vec_dec v__617 4 0 in + neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5)))) then + true + else + let g__35 := C_SRAI ((v__617, rsd)) in + false + | C_ANDI (v__618,rsd) => true + | C_SUB (rsd,rs2) => true + | C_XOR (rsd,rs2) => true + | C_OR (rsd,rs2) => true + | C_AND (rsd,rs2) => true + | C_SUBW (rsd,rs2) => true + | C_ADDW (rsd,rs2) => true + | C_J (v__619) => true + | C_BEQZ (v__620,rs) => true + | C_BNEZ (v__621,rs) => true + | C_SLLI (v__622,rsd) => + if ((let nzui5 : bits 1 := subrange_vec_dec v__622 5 5 in + let nzui5 : bits 1 := subrange_vec_dec v__622 5 5 in + let nzui40 : bits 5 := subrange_vec_dec v__622 4 0 in + andb (neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__35 := C_SLLI ((v__622, rsd)) in + false + | C_LWSP (v__623,rd) => + if ((neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__35 := C_LWSP ((v__623, rd)) in + false + | C_LDSP (v__624,rd) => + if ((neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__35 := C_LDSP ((v__624, rd)) in + false + | C_SWSP (v__625,rs2) => true + | C_SDSP (v__626,rs2) => true + | C_JR (rs1) => + if ((neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__35 := C_JR (rs1) in + false + | C_JALR (rs1) => + if ((neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__35 := C_JALR (rs1) in + false + | C_MV (rd,rs2) => + if ((andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__35 := C_MV ((rd, rs2)) in + false + | C_EBREAK (tt) => true + | C_ADD (rsd,rs2) => + if ((andb (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__35 := C_ADD ((rsd, rs2)) in + false + | C_ILLEGAL (s) => true + | g__35 => false + end. + +Definition encdec_compressed_backwards_matches (arg_ : mword 16) +: bool := + + let v__627 := arg_ in + if ((eq_vec v__627 (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1] : mword 16))) + then + true + else if ((andb + (let nz96 : bits 4 := subrange_vec_dec v__627 10 7 in + let nz54 : bits 2 := subrange_vec_dec v__627 12 11 in + let nz3 : bits 1 := subrange_vec_dec v__627 5 5 in + let nz2 : bits 1 := subrange_vec_dec v__627 6 6 in + neq_vec (concat_vec nz96 (concat_vec nz54 (concat_vec nz3 nz2))) + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword (4 + (2 + (1 + 1))))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (let rsd : regbits := subrange_vec_dec v__627 11 7 in + let nzi5 : bits 1 := subrange_vec_dec v__627 12 12 in + let nzi40 : bits 5 := subrange_vec_dec v__627 6 2 in + andb + (neq_vec (concat_vec nzi5 nzi40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (let rsd : regbits := subrange_vec_dec v__627 11 7 in + neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B0;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (let rd : regbits := subrange_vec_dec v__627 11 7 in + neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if sumbool_of_bool ((andb + (let nzi9 : bits 1 := subrange_vec_dec v__627 12 12 in + let nzi87 : bits 2 := subrange_vec_dec v__627 4 3 in + let nzi6 : bits 1 := subrange_vec_dec v__627 5 5 in + let nzi5 : bits 1 := subrange_vec_dec v__627 2 2 in + let nzi4 : bits 1 := subrange_vec_dec v__627 6 6 in + neq_vec + (concat_vec nzi9 + (concat_vec nzi87 (concat_vec nzi6 (concat_vec nzi5 nzi4)))) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + (2 + (1 + (1 + 1)))))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (andb + (Z.eqb + (projT1 (regbits_to_regno (subrange_vec_dec v__627 11 7))) + (projT1 (regbits_to_regno + (vec_of_bits [B0;B0;B0;B1;B0] : mword 5)))) + (eq_vec (subrange_vec_dec v__627 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then + true + else if ((andb + (let rd : regbits := subrange_vec_dec v__627 11 7 in + let imm17 : bits 1 := subrange_vec_dec v__627 12 12 in + let imm1612 : bits 5 := subrange_vec_dec v__627 6 2 in + andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno sp))) + (neq_vec (concat_vec imm17 imm1612) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (let nzui5 : bits 1 := subrange_vec_dec v__627 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__627 6 2 in + neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 11 10) + (vec_of_bits [B0;B0] : mword (11 - 10 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then + true + else if ((andb + (let nzui5 : bits 1 := subrange_vec_dec v__627 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__627 6 2 in + neq_vec (concat_vec nzui5 nzui40) (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 11 10) + (vec_of_bits [B0;B1] : mword (11 - 10 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))))) then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B0;B0] : mword (15 - 13 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 11 10) + (vec_of_bits [B1;B0] : mword (11 - 10 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 6 5) (vec_of_bits [B0;B0] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 6 5) (vec_of_bits [B0;B1] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 6 5) (vec_of_bits [B1;B0] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 10) + (vec_of_bits [B1;B0;B0;B0;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 6 5) (vec_of_bits [B1;B1] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 10) + (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 6 5) (vec_of_bits [B0;B0] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 10) + (vec_of_bits [B1;B0;B0;B1;B1;B1] : mword (15 - 10 + 1))) + (andb + (eq_vec (subrange_vec_dec v__627 6 5) (vec_of_bits [B0;B1] : mword (6 - 5 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B0;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (let rsd : regbits := subrange_vec_dec v__627 11 7 in + let nzui5 : bits 1 := subrange_vec_dec v__627 12 12 in + let nzui40 : bits 5 := subrange_vec_dec v__627 6 2 in + andb + (neq_vec (concat_vec nzui5 nzui40) + (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword (1 + 5))) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B0;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (let rd : regbits := subrange_vec_dec v__627 11 7 in + neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (let rd : regbits := subrange_vec_dec v__627 11 7 in + neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B0;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B1;B0] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (eq_vec (subrange_vec_dec v__627 15 13) + (vec_of_bits [B1;B1;B1] : mword (15 - 13 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + true + else if ((andb + (let rs1 : regbits := subrange_vec_dec v__627 11 7 in + neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__627 15 12) + (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__627 6 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (let rs1 : regbits := subrange_vec_dec v__627 11 7 in + neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg))) + (andb + (eq_vec (subrange_vec_dec v__627 15 12) + (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__627 6 0) + (vec_of_bits [B0;B0;B0;B0;B0;B1;B0] : mword (6 - 0 + 1)))))) then + true + else if ((andb + (let rs2 : regbits := subrange_vec_dec v__627 6 2 in + let rd : regbits := subrange_vec_dec v__627 11 7 in + andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__627 15 12) + (vec_of_bits [B1;B0;B0;B0] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + true + else if ((eq_vec v__627 + (vec_of_bits [B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0] : mword 16))) then + true + else if ((andb + (let rsd : regbits := subrange_vec_dec v__627 11 7 in + let rs2 : regbits := subrange_vec_dec v__627 6 2 in + andb (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg)))) + (andb + (eq_vec (subrange_vec_dec v__627 15 12) + (vec_of_bits [B1;B0;B0;B1] : mword (15 - 12 + 1))) + (eq_vec (subrange_vec_dec v__627 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1)))))) + then + true + else true. + +Definition assembly_forwards (arg_ : ast) +: M (string) := + + (match arg_ with + | UTYPE (imm,rd,op) => + returnm ((string_append (utype_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | RISCV_JAL (imm,rd) => + returnm ((string_append "jal" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | RISCV_JALR (imm,rs1,rd) => + returnm ((string_append "jalr" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))))) + : string) + | BTYPE (imm,rs2,rs1,op) => + returnm ((string_append (btype_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))))) + : string) + | ITYPE (imm,rs1,rd,op) => + returnm ((string_append (itype_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))))) + : string) + | SHIFTIOP (shamt,rs1,rd,op) => + returnm ((string_append (shiftiop_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (decimal_string_of_bits shamt) "")))))) + : string) + | RTYPE (rs2,rs1,rd,op) => + returnm ((string_append (rtype_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))) + : string) + | LOAD (imm,rs1,rd,is_unsigned,size,aq,rl) => + returnm ((string_append "l" + (string_append (size_mnemonic_forwards size) + (string_append (maybe_u_forwards is_unsigned) + (string_append (maybe_aq_forwards aq) + (string_append (maybe_rl_forwards rl) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))))))))) + : string) + | STORE (imm,rs1,rd,size,aq,rl) => + returnm ((string_append "s" + (string_append (size_mnemonic_forwards size) + (string_append (maybe_aq_forwards aq) + (string_append (maybe_rl_forwards rl) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) "")))))))))) + : string) + | ADDIW (imm,rs1,rd) => + returnm ((string_append "addiw" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))))) + : string) + | SHIFTW (shamt,rs1,rd,op) => + returnm ((string_append (shiftw_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits shamt) ""))))))) + : string) + | RTYPEW (rs2,rs1,rd,op) => + returnm ((string_append (rtypew_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))) + : string) + | SHIFTIWOP (shamt,rs1,rd,op) => + returnm ((string_append (shiftiwop_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (decimal_string_of_bits shamt) "")))))) + : string) + | MUL (rs2,rs1,rd,high,signed1,signed2) => + (mul_mnemonic_forwards (high, signed1, signed2)) >>= fun w__0 : string => + returnm ((string_append w__0 + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))) + : string) + | DIV (rs2,rs1,rd,s) => + returnm ((string_append "div" + (string_append (maybe_not_u_forwards s) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) "")))))))) + : string) + | REM (rs2,rs1,rd,s) => + returnm ((string_append "rem" + (string_append (maybe_not_u_forwards s) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) "")))))))) + : string) + | MULW (rs2,rs1,rd) => + returnm ((string_append "mulw" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))) + : string) + | DIVW (rs2,rs1,rd,s) => + returnm ((string_append "div" + (string_append (maybe_not_u_forwards s) + (string_append "w" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))))) + : string) + | REMW (rs2,rs1,rd,s) => + returnm ((string_append "rem" + (string_append (maybe_not_u_forwards s) + (string_append "w" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))))) + : string) + | FENCE (pred,succ) => + returnm ((string_append "fence" + (string_append (spc_forwards tt) + (string_append (fence_bits_forwards pred) + (string_append (sep_forwards tt) + (string_append (fence_bits_forwards succ) ""))))) + : string) + | FENCE_TSO (pred,succ) => + returnm ((string_append "fence.tso" + (string_append (spc_forwards tt) + (string_append (fence_bits_forwards pred) + (string_append (sep_forwards tt) + (string_append (fence_bits_forwards succ) ""))))) + : string) + | FENCEI (tt) => returnm ("fence.i" : string) + | ECALL (tt) => returnm ("ecall" : string) + | MRET (tt) => returnm ("mret" : string) + | SRET (tt) => returnm ("sret" : string) + | EBREAK (tt) => returnm ("ebreak" : string) + | WFI (tt) => returnm ("wfi" : string) + | SFENCE_VMA (rs1,rs2) => + returnm ((string_append "sfence.vma" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) (string_append (reg_name_forwards rs2) ""))))) + : string) + | LOADRES (aq,rl,rs1,size,rd) => + returnm ((string_append "lr." + (string_append (size_mnemonic_forwards size) + (string_append (maybe_aq_forwards aq) + (string_append (maybe_rl_forwards rl) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) "")))))))) + : string) + | STORECON (aq,rl,rs2,rs1,size,rd) => + returnm ((string_append "sc." + (string_append (size_mnemonic_forwards size) + (string_append (maybe_aq_forwards aq) + (string_append (maybe_rl_forwards rl) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) "")))))))))) + : string) + | AMO (op,aq,rl,rs2,rs1,width,rd) => + returnm ((string_append (amo_mnemonic_forwards op) + (string_append "." + (string_append (size_mnemonic_forwards width) + (string_append (maybe_aq_forwards aq) + (string_append (maybe_rl_forwards rl) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs2) ""))))))))))) + : string) + | CSR (csr,rs1,rd,true,op) => + returnm ((string_append (csr_mnemonic_forwards op) + (string_append "i" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits rs1) + (string_append (sep_forwards tt) + (string_append (csr_name_map_forwards csr) "")))))))) + : string) + | CSR (csr,rs1,rd,false,op) => + returnm ((string_append (csr_mnemonic_forwards op) + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (reg_name_forwards rs1) + (string_append (sep_forwards tt) + (string_append (csr_name_map_forwards csr) ""))))))) + : string) + | C_NOP (tt) => returnm ("c.nop" : string) + | C_ADDI4SPN (rdc,nzimm) => + returnm ((string_append "c.addi4spn" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rdc) + (string_append (sep_forwards tt) + (string_append + (decimal_string_of_bits + (concat_vec (nzimm : mword 8) (vec_of_bits [B0;B0] : mword 2))) + ""))))) + : string) + | C_LW (uimm,rsc,rdc) => + returnm ((string_append "c.lw" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rdc) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rsc) + (string_append (sep_forwards tt) + (string_append + (decimal_string_of_bits + (concat_vec (uimm : mword 5) + (vec_of_bits [B0;B0] : mword 2))) ""))))))) + : string) + | C_LD (uimm,rsc,rdc) => + returnm ((string_append "c.ld" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rdc) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rsc) + (string_append (sep_forwards tt) + (string_append + (decimal_string_of_bits + (concat_vec (uimm : mword 5) + (vec_of_bits [B0;B0;B0] : mword 3))) ""))))))) + : string) + | C_SW (uimm,rsc1,rsc2) => + returnm ((string_append "c.sw" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsc1) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rsc2) + (string_append (sep_forwards tt) + (string_append + (decimal_string_of_bits + (concat_vec (uimm : mword 5) + (vec_of_bits [B0;B0] : mword 2))) ""))))))) + : string) + | C_SD (uimm,rsc1,rsc2) => + returnm ((string_append "c.sd" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsc1) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rsc2) + (string_append (sep_forwards tt) + (string_append + (decimal_string_of_bits + (concat_vec (uimm : mword 5) + (vec_of_bits [B0;B0;B0] : mword 3))) ""))))))) + : string) + | C_ADDI (nzi,rsd) => + returnm ((string_append "c.addi" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits nzi) ""))))) + : string) + | C_JAL (imm) => + returnm ((string_append "c.jal" + (string_append (spc_forwards tt) + (string_append + (decimal_string_of_bits + (concat_vec (imm : mword 11) (vec_of_bits [B0] : mword 1))) ""))) + : string) + | C_ADDIW (imm,rsd) => + returnm ((string_append "c.addiw" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | C_LI (imm,rd) => + returnm ((string_append "c.li" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | C_ADDI16SP (imm) => + returnm ((string_append "c.addi16sp" + (string_append (spc_forwards tt) (string_append (decimal_string_of_bits imm) ""))) + : string) + | C_LUI (imm,rd) => + returnm ((string_append "c.lui" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | C_SRLI (shamt,rsd) => + returnm ((string_append "c.srli" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits shamt) ""))))) + : string) + | C_SRAI (shamt,rsd) => + returnm ((string_append "c.srai" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits shamt) ""))))) + : string) + | C_ANDI (imm,rsd) => + returnm ((string_append "c.andi" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | C_SUB (rsd,rs2) => + returnm ((string_append "c.sub" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rs2) ""))))) + : string) + | C_XOR (rsd,rs2) => + returnm ((string_append "c.xor" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rs2) ""))))) + : string) + | C_OR (rsd,rs2) => + returnm ((string_append "c.or" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rs2) ""))))) + : string) + | C_AND (rsd,rs2) => + returnm ((string_append "c.and" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rs2) ""))))) + : string) + | C_SUBW (rsd,rs2) => + returnm ((string_append "c.subw" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rs2) ""))))) + : string) + | C_ADDW (rsd,rs2) => + returnm ((string_append "c.addw" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (creg_name_forwards rs2) ""))))) + : string) + | C_J (imm) => + returnm ((string_append "c.j" + (string_append (spc_forwards tt) (string_append (decimal_string_of_bits imm) ""))) + : string) + | C_BEQZ (imm,rs) => + returnm ((string_append "c.beqz" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rs) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | C_BNEZ (imm,rs) => + returnm ((string_append "c.bnez" + (string_append (spc_forwards tt) + (string_append (creg_name_forwards rs) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits imm) ""))))) + : string) + | C_SLLI (shamt,rsd) => + returnm ((string_append "c.slli" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rsd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits shamt) ""))))) + : string) + | C_LWSP (uimm,rd) => + returnm ((string_append "c.lwsp" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits uimm) ""))))) + : string) + | C_LDSP (uimm,rd) => + returnm ((string_append "c.ldsp" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits uimm) ""))))) + : string) + | C_SWSP (uimm,rd) => + returnm ((string_append "c.swsp" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits uimm) ""))))) + : string) + | C_SDSP (uimm,rs2) => + returnm ((string_append "c.sdsp" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rs2) + (string_append (sep_forwards tt) + (string_append (decimal_string_of_bits uimm) ""))))) + : string) + | C_JR (rs1) => + returnm ((string_append "c.jr" + (string_append (spc_forwards tt) (string_append (reg_name_forwards rs1) ""))) + : string) + | C_JALR (rs1) => + returnm ((string_append "c.jalr" + (string_append (spc_forwards tt) (string_append (reg_name_forwards rs1) ""))) + : string) + | C_MV (rd,rs2) => + returnm ((string_append "c.mv" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rd) + (string_append (sep_forwards tt) (string_append (reg_name_forwards rs2) ""))))) + : string) + | C_EBREAK (tt) => returnm ("c.ebreak" : string) + | C_ADD (rsd,rs2) => + returnm ((string_append "c.add" + (string_append (spc_forwards tt) + (string_append (reg_name_forwards rsd) + (string_append (sep_forwards tt) (string_append (reg_name_forwards rs2) ""))))) + : string) + | STOP_FETCHING (tt) => returnm ("stop_fetching" : string) + | THREAD_START (tt) => returnm ("thread_start" : string) + | ILLEGAL (s) => + returnm ((string_append "illegal" + (string_append (spc_forwards tt) (string_append (decimal_string_of_bits s) ""))) + : string) + | C_ILLEGAL (s) => + returnm ((string_append "c.illegal" + (string_append (spc_forwards tt) (string_append (decimal_string_of_bits s) ""))) + : string) + end) + : M (string). + +Definition _s1661_ (_s1662_ : string) +: M (option (mword 16)) := + + let _s1663_ := _s1662_ in + (if ((string_startswith _s1663_ "c.illegal")) then + (match (string_drop _s1663_ (projT1 (string_length "c.illegal"))) with + | _s1664_ => + (spc_matches_prefix _s1664_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s1665_ _)) => + match (string_drop _s1664_ _s1665_) with + | _s1666_ => + match (hex_bits_16_matches_prefix _s1666_) with + | Some (s,(existT _ _s1667_ _)) => + let p0_ := string_drop _s1666_ _s1667_ in + if ((generic_eq p0_ "")) then Some (s) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 16)) + end) + : M (option (mword 16)) + else returnm (None : option (mword 16))) + : M (option (mword 16)). + +Definition _s1653_ (_s1654_ : string) +: M (option (mword 32)) := + + let _s1655_ := _s1654_ in + (if ((string_startswith _s1655_ "illegal")) then + (match (string_drop _s1655_ (projT1 (string_length "illegal"))) with + | _s1656_ => + (spc_matches_prefix _s1656_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s1657_ _)) => + match (string_drop _s1656_ _s1657_) with + | _s1658_ => + match (hex_bits_32_matches_prefix _s1658_) with + | Some (s,(existT _ _s1659_ _)) => + let p0_ := string_drop _s1658_ _s1659_ in + if ((generic_eq p0_ "")) then Some (s) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 32)) + end) + : M (option (mword 32)) + else returnm (None : option (mword 32))) + : M (option (mword 32)). + +Definition _s1641_ (_s1642_ : string) +: M (option ((mword 5 * mword 5))) := + + let _s1643_ := _s1642_ in + (if ((string_startswith _s1643_ "c.add")) then + (match (string_drop _s1643_ (projT1 (string_length "c.add"))) with + | _s1644_ => + (spc_matches_prefix _s1644_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1645_ _)) => + (match (string_drop _s1644_ _s1645_) with + | _s1646_ => + (reg_name_matches_prefix _s1646_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1647_ _)) => + (match (string_drop _s1646_ _s1647_) with + | _s1648_ => + (sep_matches_prefix _s1648_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1649_ _)) => + (match (string_drop _s1648_ _s1649_) with + | _s1650_ => + (reg_name_matches_prefix _s1650_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1651_ _)) => + let p0_ := string_drop _s1650_ _s1651_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5))). + +Definition _s1629_ (_s1630_ : string) +: M (option ((mword 5 * mword 5))) := + + let _s1631_ := _s1630_ in + (if ((string_startswith _s1631_ "c.mv")) then + (match (string_drop _s1631_ (projT1 (string_length "c.mv"))) with + | _s1632_ => + (spc_matches_prefix _s1632_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1633_ _)) => + (match (string_drop _s1632_ _s1633_) with + | _s1634_ => + (reg_name_matches_prefix _s1634_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1635_ _)) => + (match (string_drop _s1634_ _s1635_) with + | _s1636_ => + (sep_matches_prefix _s1636_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1637_ _)) => + (match (string_drop _s1636_ _s1637_) with + | _s1638_ => + (reg_name_matches_prefix _s1638_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1639_ _)) => + let p0_ := string_drop _s1638_ _s1639_ in + if ((generic_eq p0_ "")) then Some ((rd, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5))). + +Definition _s1621_ (_s1622_ : string) +: M (option (mword 5)) := + + let _s1623_ := _s1622_ in + (if ((string_startswith _s1623_ "c.jalr")) then + (match (string_drop _s1623_ (projT1 (string_length "c.jalr"))) with + | _s1624_ => + (spc_matches_prefix _s1624_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1625_ _)) => + (match (string_drop _s1624_ _s1625_) with + | _s1626_ => + (reg_name_matches_prefix _s1626_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (rs1,(existT _ _s1627_ _)) => + let p0_ := string_drop _s1626_ _s1627_ in + if ((generic_eq p0_ "")) then Some (rs1) + else None + | _ => None + end) + : option (mword 5)) + end) + : M (option (mword 5)) + | _ => returnm (None : option (mword 5)) + end) + : M (option (mword 5)) + end) + : M (option (mword 5)) + else returnm (None : option (mword 5))) + : M (option (mword 5)). + +Definition _s1613_ (_s1614_ : string) +: M (option (mword 5)) := + + let _s1615_ := _s1614_ in + (if ((string_startswith _s1615_ "c.jr")) then + (match (string_drop _s1615_ (projT1 (string_length "c.jr"))) with + | _s1616_ => + (spc_matches_prefix _s1616_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1617_ _)) => + (match (string_drop _s1616_ _s1617_) with + | _s1618_ => + (reg_name_matches_prefix _s1618_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (rs1,(existT _ _s1619_ _)) => + let p0_ := string_drop _s1618_ _s1619_ in + if ((generic_eq p0_ "")) then Some (rs1) + else None + | _ => None + end) + : option (mword 5)) + end) + : M (option (mword 5)) + | _ => returnm (None : option (mword 5)) + end) + : M (option (mword 5)) + end) + : M (option (mword 5)) + else returnm (None : option (mword 5))) + : M (option (mword 5)). + +Definition _s1601_ (_s1602_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1603_ := _s1602_ in + (if ((string_startswith _s1603_ "c.sdsp")) then + (match (string_drop _s1603_ (projT1 (string_length "c.sdsp"))) with + | _s1604_ => + (spc_matches_prefix _s1604_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1605_ _)) => + (match (string_drop _s1604_ _s1605_) with + | _s1606_ => + (reg_name_matches_prefix _s1606_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs2,(existT _ _s1607_ _)) => + (match (string_drop _s1606_ _s1607_) with + | _s1608_ => + (sep_matches_prefix _s1608_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1609_ _)) => + match (string_drop _s1608_ _s1609_) with + | _s1610_ => + match (hex_bits_6_matches_prefix _s1610_) with + | Some (uimm,(existT _ _s1611_ _)) => + let p0_ := string_drop _s1610_ _s1611_ in + if ((generic_eq p0_ "")) then Some ((rs2, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1589_ (_s1590_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1591_ := _s1590_ in + (if ((string_startswith _s1591_ "c.swsp")) then + (match (string_drop _s1591_ (projT1 (string_length "c.swsp"))) with + | _s1592_ => + (spc_matches_prefix _s1592_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1593_ _)) => + (match (string_drop _s1592_ _s1593_) with + | _s1594_ => + (reg_name_matches_prefix _s1594_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1595_ _)) => + (match (string_drop _s1594_ _s1595_) with + | _s1596_ => + (sep_matches_prefix _s1596_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1597_ _)) => + match (string_drop _s1596_ _s1597_) with + | _s1598_ => + match (hex_bits_6_matches_prefix _s1598_) with + | Some (uimm,(existT _ _s1599_ _)) => + let p0_ := string_drop _s1598_ _s1599_ in + if ((generic_eq p0_ "")) then Some ((rd, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1577_ (_s1578_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1579_ := _s1578_ in + (if ((string_startswith _s1579_ "c.ldsp")) then + (match (string_drop _s1579_ (projT1 (string_length "c.ldsp"))) with + | _s1580_ => + (spc_matches_prefix _s1580_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1581_ _)) => + (match (string_drop _s1580_ _s1581_) with + | _s1582_ => + (reg_name_matches_prefix _s1582_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1583_ _)) => + (match (string_drop _s1582_ _s1583_) with + | _s1584_ => + (sep_matches_prefix _s1584_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1585_ _)) => + match (string_drop _s1584_ _s1585_) with + | _s1586_ => + match (hex_bits_6_matches_prefix _s1586_) with + | Some (uimm,(existT _ _s1587_ _)) => + let p0_ := string_drop _s1586_ _s1587_ in + if ((generic_eq p0_ "")) then Some ((rd, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1565_ (_s1566_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1567_ := _s1566_ in + (if ((string_startswith _s1567_ "c.lwsp")) then + (match (string_drop _s1567_ (projT1 (string_length "c.lwsp"))) with + | _s1568_ => + (spc_matches_prefix _s1568_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1569_ _)) => + (match (string_drop _s1568_ _s1569_) with + | _s1570_ => + (reg_name_matches_prefix _s1570_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1571_ _)) => + (match (string_drop _s1570_ _s1571_) with + | _s1572_ => + (sep_matches_prefix _s1572_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1573_ _)) => + match (string_drop _s1572_ _s1573_) with + | _s1574_ => + match (hex_bits_6_matches_prefix _s1574_) with + | Some (uimm,(existT _ _s1575_ _)) => + let p0_ := string_drop _s1574_ _s1575_ in + if ((generic_eq p0_ "")) then Some ((rd, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1553_ (_s1554_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1555_ := _s1554_ in + (if ((string_startswith _s1555_ "c.slli")) then + (match (string_drop _s1555_ (projT1 (string_length "c.slli"))) with + | _s1556_ => + (spc_matches_prefix _s1556_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1557_ _)) => + (match (string_drop _s1556_ _s1557_) with + | _s1558_ => + (reg_name_matches_prefix _s1558_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1559_ _)) => + (match (string_drop _s1558_ _s1559_) with + | _s1560_ => + (sep_matches_prefix _s1560_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1561_ _)) => + match (string_drop _s1560_ _s1561_) with + | _s1562_ => + match (hex_bits_6_matches_prefix _s1562_) with + | Some (shamt,(existT _ _s1563_ _)) => + let p0_ := string_drop _s1562_ _s1563_ in + if ((generic_eq p0_ "")) then Some ((rsd, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1541_ (_s1542_ : string) +: M (option ((mword 3 * mword 8))) := + + let _s1543_ := _s1542_ in + (if ((string_startswith _s1543_ "c.bnez")) then + (match (string_drop _s1543_ (projT1 (string_length "c.bnez"))) with + | _s1544_ => + (spc_matches_prefix _s1544_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1545_ _)) => + (match (string_drop _s1544_ _s1545_) with + | _s1546_ => + (creg_name_matches_prefix _s1546_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs,(existT _ _s1547_ _)) => + (match (string_drop _s1546_ _s1547_) with + | _s1548_ => + (sep_matches_prefix _s1548_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1549_ _)) => + match (string_drop _s1548_ _s1549_) with + | _s1550_ => + match (hex_bits_8_matches_prefix _s1550_) with + | Some (imm,(existT _ _s1551_ _)) => + let p0_ := string_drop _s1550_ _s1551_ in + if ((generic_eq p0_ "")) then Some ((rs, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + else returnm (None : option ((mword 3 * mword 8)))) + : M (option ((mword 3 * mword 8))). + +Definition _s1529_ (_s1530_ : string) +: M (option ((mword 3 * mword 8))) := + + let _s1531_ := _s1530_ in + (if ((string_startswith _s1531_ "c.beqz")) then + (match (string_drop _s1531_ (projT1 (string_length "c.beqz"))) with + | _s1532_ => + (spc_matches_prefix _s1532_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1533_ _)) => + (match (string_drop _s1532_ _s1533_) with + | _s1534_ => + (creg_name_matches_prefix _s1534_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs,(existT _ _s1535_ _)) => + (match (string_drop _s1534_ _s1535_) with + | _s1536_ => + (sep_matches_prefix _s1536_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1537_ _)) => + match (string_drop _s1536_ _s1537_) with + | _s1538_ => + match (hex_bits_8_matches_prefix _s1538_) with + | Some (imm,(existT _ _s1539_ _)) => + let p0_ := string_drop _s1538_ _s1539_ in + if ((generic_eq p0_ "")) then Some ((rs, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + else returnm (None : option ((mword 3 * mword 8)))) + : M (option ((mword 3 * mword 8))). + +Definition _s1521_ (_s1522_ : string) +: M (option (mword 11)) := + + let _s1523_ := _s1522_ in + (if ((string_startswith _s1523_ "c.j")) then + (match (string_drop _s1523_ (projT1 (string_length "c.j"))) with + | _s1524_ => + (spc_matches_prefix _s1524_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s1525_ _)) => + match (string_drop _s1524_ _s1525_) with + | _s1526_ => + match (hex_bits_11_matches_prefix _s1526_) with + | Some (imm,(existT _ _s1527_ _)) => + let p0_ := string_drop _s1526_ _s1527_ in + if ((generic_eq p0_ "")) then Some (imm) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 11)) + end) + : M (option (mword 11)) + else returnm (None : option (mword 11))) + : M (option (mword 11)). + +Definition _s1509_ (_s1510_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s1511_ := _s1510_ in + (if ((string_startswith _s1511_ "c.addw")) then + (match (string_drop _s1511_ (projT1 (string_length "c.addw"))) with + | _s1512_ => + (spc_matches_prefix _s1512_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1513_ _)) => + (match (string_drop _s1512_ _s1513_) with + | _s1514_ => + (creg_name_matches_prefix _s1514_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1515_ _)) => + (match (string_drop _s1514_ _s1515_) with + | _s1516_ => + (sep_matches_prefix _s1516_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1517_ _)) => + (match (string_drop _s1516_ _s1517_) with + | _s1518_ => + (creg_name_matches_prefix _s1518_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1519_ _)) => + let p0_ := string_drop _s1518_ _s1519_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s1497_ (_s1498_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s1499_ := _s1498_ in + (if ((string_startswith _s1499_ "c.subw")) then + (match (string_drop _s1499_ (projT1 (string_length "c.subw"))) with + | _s1500_ => + (spc_matches_prefix _s1500_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1501_ _)) => + (match (string_drop _s1500_ _s1501_) with + | _s1502_ => + (creg_name_matches_prefix _s1502_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1503_ _)) => + (match (string_drop _s1502_ _s1503_) with + | _s1504_ => + (sep_matches_prefix _s1504_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1505_ _)) => + (match (string_drop _s1504_ _s1505_) with + | _s1506_ => + (creg_name_matches_prefix _s1506_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1507_ _)) => + let p0_ := string_drop _s1506_ _s1507_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s1485_ (_s1486_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s1487_ := _s1486_ in + (if ((string_startswith _s1487_ "c.and")) then + (match (string_drop _s1487_ (projT1 (string_length "c.and"))) with + | _s1488_ => + (spc_matches_prefix _s1488_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1489_ _)) => + (match (string_drop _s1488_ _s1489_) with + | _s1490_ => + (creg_name_matches_prefix _s1490_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1491_ _)) => + (match (string_drop _s1490_ _s1491_) with + | _s1492_ => + (sep_matches_prefix _s1492_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1493_ _)) => + (match (string_drop _s1492_ _s1493_) with + | _s1494_ => + (creg_name_matches_prefix _s1494_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1495_ _)) => + let p0_ := string_drop _s1494_ _s1495_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s1473_ (_s1474_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s1475_ := _s1474_ in + (if ((string_startswith _s1475_ "c.or")) then + (match (string_drop _s1475_ (projT1 (string_length "c.or"))) with + | _s1476_ => + (spc_matches_prefix _s1476_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1477_ _)) => + (match (string_drop _s1476_ _s1477_) with + | _s1478_ => + (creg_name_matches_prefix _s1478_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1479_ _)) => + (match (string_drop _s1478_ _s1479_) with + | _s1480_ => + (sep_matches_prefix _s1480_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1481_ _)) => + (match (string_drop _s1480_ _s1481_) with + | _s1482_ => + (creg_name_matches_prefix _s1482_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1483_ _)) => + let p0_ := string_drop _s1482_ _s1483_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s1461_ (_s1462_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s1463_ := _s1462_ in + (if ((string_startswith _s1463_ "c.xor")) then + (match (string_drop _s1463_ (projT1 (string_length "c.xor"))) with + | _s1464_ => + (spc_matches_prefix _s1464_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1465_ _)) => + (match (string_drop _s1464_ _s1465_) with + | _s1466_ => + (creg_name_matches_prefix _s1466_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1467_ _)) => + (match (string_drop _s1466_ _s1467_) with + | _s1468_ => + (sep_matches_prefix _s1468_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1469_ _)) => + (match (string_drop _s1468_ _s1469_) with + | _s1470_ => + (creg_name_matches_prefix _s1470_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1471_ _)) => + let p0_ := string_drop _s1470_ _s1471_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s1449_ (_s1450_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s1451_ := _s1450_ in + (if ((string_startswith _s1451_ "c.sub")) then + (match (string_drop _s1451_ (projT1 (string_length "c.sub"))) with + | _s1452_ => + (spc_matches_prefix _s1452_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1453_ _)) => + (match (string_drop _s1452_ _s1453_) with + | _s1454_ => + (creg_name_matches_prefix _s1454_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1455_ _)) => + (match (string_drop _s1454_ _s1455_) with + | _s1456_ => + (sep_matches_prefix _s1456_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1457_ _)) => + (match (string_drop _s1456_ _s1457_) with + | _s1458_ => + (creg_name_matches_prefix _s1458_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1459_ _)) => + let p0_ := string_drop _s1458_ _s1459_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s1437_ (_s1438_ : string) +: M (option ((mword 3 * mword 6))) := + + let _s1439_ := _s1438_ in + (if ((string_startswith _s1439_ "c.andi")) then + (match (string_drop _s1439_ (projT1 (string_length "c.andi"))) with + | _s1440_ => + (spc_matches_prefix _s1440_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1441_ _)) => + (match (string_drop _s1440_ _s1441_) with + | _s1442_ => + (creg_name_matches_prefix _s1442_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1443_ _)) => + (match (string_drop _s1442_ _s1443_) with + | _s1444_ => + (sep_matches_prefix _s1444_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1445_ _)) => + match (string_drop _s1444_ _s1445_) with + | _s1446_ => + match (hex_bits_6_matches_prefix _s1446_) with + | Some (imm,(existT _ _s1447_ _)) => + let p0_ := string_drop _s1446_ _s1447_ in + if ((generic_eq p0_ "")) then Some ((rsd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + else returnm (None : option ((mword 3 * mword 6)))) + : M (option ((mword 3 * mword 6))). + +Definition _s1425_ (_s1426_ : string) +: M (option ((mword 3 * mword 6))) := + + let _s1427_ := _s1426_ in + (if ((string_startswith _s1427_ "c.srai")) then + (match (string_drop _s1427_ (projT1 (string_length "c.srai"))) with + | _s1428_ => + (spc_matches_prefix _s1428_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1429_ _)) => + (match (string_drop _s1428_ _s1429_) with + | _s1430_ => + (creg_name_matches_prefix _s1430_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1431_ _)) => + (match (string_drop _s1430_ _s1431_) with + | _s1432_ => + (sep_matches_prefix _s1432_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1433_ _)) => + match (string_drop _s1432_ _s1433_) with + | _s1434_ => + match (hex_bits_6_matches_prefix _s1434_) with + | Some (shamt,(existT _ _s1435_ _)) => + let p0_ := string_drop _s1434_ _s1435_ in + if ((generic_eq p0_ "")) then Some ((rsd, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + else returnm (None : option ((mword 3 * mword 6)))) + : M (option ((mword 3 * mword 6))). + +Definition _s1413_ (_s1414_ : string) +: M (option ((mword 3 * mword 6))) := + + let _s1415_ := _s1414_ in + (if ((string_startswith _s1415_ "c.srli")) then + (match (string_drop _s1415_ (projT1 (string_length "c.srli"))) with + | _s1416_ => + (spc_matches_prefix _s1416_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1417_ _)) => + (match (string_drop _s1416_ _s1417_) with + | _s1418_ => + (creg_name_matches_prefix _s1418_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1419_ _)) => + (match (string_drop _s1418_ _s1419_) with + | _s1420_ => + (sep_matches_prefix _s1420_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1421_ _)) => + match (string_drop _s1420_ _s1421_) with + | _s1422_ => + match (hex_bits_6_matches_prefix _s1422_) with + | Some (shamt,(existT _ _s1423_ _)) => + let p0_ := string_drop _s1422_ _s1423_ in + if ((generic_eq p0_ "")) then Some ((rsd, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + else returnm (None : option ((mword 3 * mword 6)))) + : M (option ((mword 3 * mword 6))). + +Definition _s1401_ (_s1402_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1403_ := _s1402_ in + (if ((string_startswith _s1403_ "c.lui")) then + (match (string_drop _s1403_ (projT1 (string_length "c.lui"))) with + | _s1404_ => + (spc_matches_prefix _s1404_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1405_ _)) => + (match (string_drop _s1404_ _s1405_) with + | _s1406_ => + (reg_name_matches_prefix _s1406_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1407_ _)) => + (match (string_drop _s1406_ _s1407_) with + | _s1408_ => + (sep_matches_prefix _s1408_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1409_ _)) => + match (string_drop _s1408_ _s1409_) with + | _s1410_ => + match (hex_bits_6_matches_prefix _s1410_) with + | Some (imm,(existT _ _s1411_ _)) => + let p0_ := string_drop _s1410_ _s1411_ in + if ((generic_eq p0_ "")) then Some ((rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1393_ (_s1394_ : string) +: M (option (mword 6)) := + + let _s1395_ := _s1394_ in + (if ((string_startswith _s1395_ "c.addi16sp")) then + (match (string_drop _s1395_ (projT1 (string_length "c.addi16sp"))) with + | _s1396_ => + (spc_matches_prefix _s1396_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s1397_ _)) => + match (string_drop _s1396_ _s1397_) with + | _s1398_ => + match (hex_bits_6_matches_prefix _s1398_) with + | Some (imm,(existT _ _s1399_ _)) => + let p0_ := string_drop _s1398_ _s1399_ in + if ((generic_eq p0_ "")) then Some (imm) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 6)) + end) + : M (option (mword 6)) + else returnm (None : option (mword 6))) + : M (option (mword 6)). + +Definition _s1381_ (_s1382_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1383_ := _s1382_ in + (if ((string_startswith _s1383_ "c.li")) then + (match (string_drop _s1383_ (projT1 (string_length "c.li"))) with + | _s1384_ => + (spc_matches_prefix _s1384_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1385_ _)) => + (match (string_drop _s1384_ _s1385_) with + | _s1386_ => + (reg_name_matches_prefix _s1386_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1387_ _)) => + (match (string_drop _s1386_ _s1387_) with + | _s1388_ => + (sep_matches_prefix _s1388_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1389_ _)) => + match (string_drop _s1388_ _s1389_) with + | _s1390_ => + match (hex_bits_6_matches_prefix _s1390_) with + | Some (imm,(existT _ _s1391_ _)) => + let p0_ := string_drop _s1390_ _s1391_ in + if ((generic_eq p0_ "")) then Some ((rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1369_ (_s1370_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1371_ := _s1370_ in + (if ((string_startswith _s1371_ "c.addiw")) then + (match (string_drop _s1371_ (projT1 (string_length "c.addiw"))) with + | _s1372_ => + (spc_matches_prefix _s1372_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1373_ _)) => + (match (string_drop _s1372_ _s1373_) with + | _s1374_ => + (reg_name_matches_prefix _s1374_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1375_ _)) => + (match (string_drop _s1374_ _s1375_) with + | _s1376_ => + (sep_matches_prefix _s1376_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1377_ _)) => + match (string_drop _s1376_ _s1377_) with + | _s1378_ => + match (hex_bits_6_matches_prefix _s1378_) with + | Some (imm,(existT _ _s1379_ _)) => + let p0_ := string_drop _s1378_ _s1379_ in + if ((generic_eq p0_ "")) then Some ((rsd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1361_ (_s1362_ : string) +: M (option (mword 11)) := + + let _s1363_ := _s1362_ in + (if ((string_startswith _s1363_ "c.jal")) then + (match (string_drop _s1363_ (projT1 (string_length "c.jal"))) with + | _s1364_ => + (spc_matches_prefix _s1364_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s1365_ _)) => + match (string_drop _s1364_ _s1365_) with + | _s1366_ => + match (hex_bits_12_matches_prefix _s1366_) with + | Some (v__760,(existT _ _s1367_ _)) => + if ((eq_vec (subrange_vec_dec v__760 0 0) + (vec_of_bits [B0] : mword (0 - 0 + 1)))) then + let imm : mword 11 := subrange_vec_dec v__760 11 1 in + let imm : mword 11 := subrange_vec_dec v__760 11 1 in + let p0_ := string_drop _s1366_ _s1367_ in + if ((generic_eq p0_ "")) then Some (imm) + else None + else + let g__34 := Some ((v__760, _s1367_)) in + None + | g__34 => None + end + end + | _ => None + end) + : option (mword 11)) + end) + : M (option (mword 11)) + else returnm (None : option (mword 11))) + : M (option (mword 11)). + +Definition _s1349_ (_s1350_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s1351_ := _s1350_ in + (if ((string_startswith _s1351_ "c.addi")) then + (match (string_drop _s1351_ (projT1 (string_length "c.addi"))) with + | _s1352_ => + (spc_matches_prefix _s1352_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1353_ _)) => + (match (string_drop _s1352_ _s1353_) with + | _s1354_ => + (reg_name_matches_prefix _s1354_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s1355_ _)) => + (match (string_drop _s1354_ _s1355_) with + | _s1356_ => + (sep_matches_prefix _s1356_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1357_ _)) => + match (string_drop _s1356_ _s1357_) with + | _s1358_ => + match (hex_bits_6_matches_prefix _s1358_) with + | Some (nzi,(existT _ _s1359_ _)) => + let p0_ := string_drop _s1358_ _s1359_ in + if ((generic_eq p0_ "")) then Some ((rsd, nzi)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s1333_ (_s1334_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s1335_ := _s1334_ in + (if ((string_startswith _s1335_ "c.sd")) then + (match (string_drop _s1335_ (projT1 (string_length "c.sd"))) with + | _s1336_ => + (spc_matches_prefix _s1336_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1337_ _)) => + (match (string_drop _s1336_ _s1337_) with + | _s1338_ => + (creg_name_matches_prefix _s1338_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsc1,(existT _ _s1339_ _)) => + (match (string_drop _s1338_ _s1339_) with + | _s1340_ => + (sep_matches_prefix _s1340_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1341_ _)) => + (match (string_drop _s1340_ _s1341_) with + | _s1342_ => + (creg_name_matches_prefix _s1342_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc2,(existT _ _s1343_ _)) => + (match (string_drop _s1342_ _s1343_) with + | _s1344_ => + (sep_matches_prefix _s1344_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s1345_ _)) => + match (string_drop _s1344_ _s1345_) with + | _s1346_ => + match (hex_bits_8_matches_prefix _s1346_) with + | Some (v__762,(existT _ _s1347_ _)) => + if ((eq_vec + (subrange_vec_dec v__762 2 0) + (vec_of_bits [B0;B0;B0] + : mword (2 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__762 7 3 in + let uimm : mword 5 := + subrange_vec_dec v__762 7 3 in + let p0_ := + string_drop _s1346_ _s1347_ in + if ((generic_eq p0_ "")) then + Some + ((rsc1, rsc2, uimm)) + else None + else + let g__33 := Some ((v__762, _s1347_)) in + None + | g__33 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s1317_ (_s1318_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s1319_ := _s1318_ in + (if ((string_startswith _s1319_ "c.sw")) then + (match (string_drop _s1319_ (projT1 (string_length "c.sw"))) with + | _s1320_ => + (spc_matches_prefix _s1320_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1321_ _)) => + (match (string_drop _s1320_ _s1321_) with + | _s1322_ => + (creg_name_matches_prefix _s1322_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsc1,(existT _ _s1323_ _)) => + (match (string_drop _s1322_ _s1323_) with + | _s1324_ => + (sep_matches_prefix _s1324_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1325_ _)) => + (match (string_drop _s1324_ _s1325_) with + | _s1326_ => + (creg_name_matches_prefix _s1326_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc2,(existT _ _s1327_ _)) => + (match (string_drop _s1326_ _s1327_) with + | _s1328_ => + (sep_matches_prefix _s1328_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s1329_ _)) => + match (string_drop _s1328_ _s1329_) with + | _s1330_ => + match (hex_bits_7_matches_prefix _s1330_) with + | Some (v__764,(existT _ _s1331_ _)) => + if ((eq_vec + (subrange_vec_dec v__764 1 0) + (vec_of_bits [B0;B0] + : mword (1 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__764 6 2 in + let uimm : mword 5 := + subrange_vec_dec v__764 6 2 in + let p0_ := + string_drop _s1330_ _s1331_ in + if ((generic_eq p0_ "")) then + Some + ((rsc1, rsc2, uimm)) + else None + else + let g__32 := Some ((v__764, _s1331_)) in + None + | g__32 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s1301_ (_s1302_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s1303_ := _s1302_ in + (if ((string_startswith _s1303_ "c.ld")) then + (match (string_drop _s1303_ (projT1 (string_length "c.ld"))) with + | _s1304_ => + (spc_matches_prefix _s1304_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1305_ _)) => + (match (string_drop _s1304_ _s1305_) with + | _s1306_ => + (creg_name_matches_prefix _s1306_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s1307_ _)) => + (match (string_drop _s1306_ _s1307_) with + | _s1308_ => + (sep_matches_prefix _s1308_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1309_ _)) => + (match (string_drop _s1308_ _s1309_) with + | _s1310_ => + (creg_name_matches_prefix _s1310_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc,(existT _ _s1311_ _)) => + (match (string_drop _s1310_ _s1311_) with + | _s1312_ => + (sep_matches_prefix _s1312_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s1313_ _)) => + match (string_drop _s1312_ _s1313_) with + | _s1314_ => + match (hex_bits_8_matches_prefix _s1314_) with + | Some (v__766,(existT _ _s1315_ _)) => + if ((eq_vec + (subrange_vec_dec v__766 2 0) + (vec_of_bits [B0;B0;B0] + : mword (2 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__766 7 3 in + let uimm : mword 5 := + subrange_vec_dec v__766 7 3 in + let p0_ := + string_drop _s1314_ _s1315_ in + if ((generic_eq p0_ "")) then + Some + ((rdc, rsc, uimm)) + else None + else + let g__31 := Some ((v__766, _s1315_)) in + None + | g__31 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s1285_ (_s1286_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s1287_ := _s1286_ in + (if ((string_startswith _s1287_ "c.lw")) then + (match (string_drop _s1287_ (projT1 (string_length "c.lw"))) with + | _s1288_ => + (spc_matches_prefix _s1288_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1289_ _)) => + (match (string_drop _s1288_ _s1289_) with + | _s1290_ => + (creg_name_matches_prefix _s1290_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s1291_ _)) => + (match (string_drop _s1290_ _s1291_) with + | _s1292_ => + (sep_matches_prefix _s1292_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1293_ _)) => + (match (string_drop _s1292_ _s1293_) with + | _s1294_ => + (creg_name_matches_prefix _s1294_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc,(existT _ _s1295_ _)) => + (match (string_drop _s1294_ _s1295_) with + | _s1296_ => + (sep_matches_prefix _s1296_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s1297_ _)) => + match (string_drop _s1296_ _s1297_) with + | _s1298_ => + match (hex_bits_7_matches_prefix _s1298_) with + | Some (v__768,(existT _ _s1299_ _)) => + if ((eq_vec + (subrange_vec_dec v__768 1 0) + (vec_of_bits [B0;B0] + : mword (1 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__768 6 2 in + let uimm : mword 5 := + subrange_vec_dec v__768 6 2 in + let p0_ := + string_drop _s1298_ _s1299_ in + if ((generic_eq p0_ "")) then + Some + ((rdc, rsc, uimm)) + else None + else + let g__30 := Some ((v__768, _s1299_)) in + None + | g__30 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s1273_ (_s1274_ : string) +: M (option ((mword 3 * mword 8))) := + + let _s1275_ := _s1274_ in + (if ((string_startswith _s1275_ "c.addi4spn")) then + (match (string_drop _s1275_ (projT1 (string_length "c.addi4spn"))) with + | _s1276_ => + (spc_matches_prefix _s1276_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1277_ _)) => + (match (string_drop _s1276_ _s1277_) with + | _s1278_ => + (creg_name_matches_prefix _s1278_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s1279_ _)) => + (match (string_drop _s1278_ _s1279_) with + | _s1280_ => + (sep_matches_prefix _s1280_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1281_ _)) => + match (string_drop _s1280_ _s1281_) with + | _s1282_ => + match (hex_bits_10_matches_prefix _s1282_) with + | Some (v__770,(existT _ _s1283_ _)) => + if ((eq_vec (subrange_vec_dec v__770 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) + then + let nzimm : mword 8 := subrange_vec_dec v__770 9 2 in + let nzimm : mword 8 := subrange_vec_dec v__770 9 2 in + let p0_ := string_drop _s1282_ _s1283_ in + if ((generic_eq p0_ "")) then Some ((rdc, nzimm)) + else None + else + let g__29 := Some ((v__770, _s1283_)) in + None + | g__29 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + else returnm (None : option ((mword 3 * mword 8)))) + : M (option ((mword 3 * mword 8))). + +Definition _s1256_ (_s1257_ : string) +: M (option ((csrop * mword 5 * mword 5 * mword 12))) := + + (match _s1257_ with + | _s1258_ => + (csr_mnemonic_matches_prefix _s1258_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1259_ _)) => + (match (string_drop _s1258_ _s1259_) with + | _s1260_ => + (spc_matches_prefix _s1260_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1261_ _)) => + (match (string_drop _s1260_ _s1261_) with + | _s1262_ => + (reg_name_matches_prefix _s1262_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1263_ _)) => + (match (string_drop _s1262_ _s1263_) with + | _s1264_ => + (sep_matches_prefix _s1264_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1265_ _)) => + (match (string_drop _s1264_ _s1265_) with + | _s1266_ => + (reg_name_matches_prefix _s1266_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1267_ _)) => + (match (string_drop _s1266_ _s1267_) with + | _s1268_ => + (sep_matches_prefix _s1268_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1269_ _)) => + (match (string_drop _s1268_ _s1269_) with + | _s1270_ => + (csr_name_map_matches_prefix _s1270_) >>= fun w__6 : option ((mword 12 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (csr,(existT _ _s1271_ _)) => + let p0_ := + string_drop _s1270_ _s1271_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, csr)) + else None + | _ => None + end) + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))). + +Definition _s1238_ (_s1239_ : string) +: M (option ((csrop * mword 5 * mword 5 * mword 12))) := + + (match _s1239_ with + | _s1240_ => + (csr_mnemonic_matches_prefix _s1240_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1241_ _)) => + let _s1242_ := string_drop _s1240_ _s1241_ in + (if ((string_startswith _s1242_ "i")) then + (match (string_drop _s1242_ (projT1 (string_length "i"))) with + | _s1243_ => + (spc_matches_prefix _s1243_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1244_ _)) => + (match (string_drop _s1243_ _s1244_) with + | _s1245_ => + (reg_name_matches_prefix _s1245_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1246_ _)) => + (match (string_drop _s1245_ _s1246_) with + | _s1247_ => + (sep_matches_prefix _s1247_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1248_ _)) => + (match (string_drop _s1247_ _s1248_) with + | _s1249_ => + (match (hex_bits_5_matches_prefix _s1249_) with + | Some (rs1,(existT _ _s1250_ _)) => + (match (string_drop _s1249_ _s1250_) with + | _s1251_ => + (sep_matches_prefix _s1251_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s1252_ _)) => + (match (string_drop _s1251_ _s1252_) with + | _s1253_ => + (csr_name_map_matches_prefix _s1253_) >>= fun w__5 : option ((mword 12 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some + (csr,(existT _ _s1254_ _)) => + let p0_ := + string_drop _s1253_ _s1254_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, csr)) + else None + | _ => None + end) + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + else returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))). + +Definition _s1214_ (_s1215_ : string) +: M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) := + + (match _s1215_ with + | _s1216_ => + (amo_mnemonic_matches_prefix _s1216_) >>= fun w__0 : option ((amoop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1217_ _)) => + let _s1218_ := string_drop _s1216_ _s1217_ in + (if ((string_startswith _s1218_ ".")) then + (match (string_drop _s1218_ (projT1 (string_length "."))) with + | _s1219_ => + (size_mnemonic_matches_prefix _s1219_) >>= fun w__1 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (width,(existT _ _s1220_ _)) => + (match (string_drop _s1219_ _s1220_) with + | _s1221_ => + (maybe_aq_matches_prefix _s1221_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (aq,(existT _ _s1222_ _)) => + (match (string_drop _s1221_ _s1222_) with + | _s1223_ => + (maybe_rl_matches_prefix _s1223_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rl,(existT _ _s1224_ _)) => + (match (string_drop _s1223_ _s1224_) with + | _s1225_ => + (spc_matches_prefix _s1225_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s1226_ _)) => + (match (string_drop _s1225_ _s1226_) with + | _s1227_ => + (reg_name_matches_prefix _s1227_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (rd,(existT _ _s1228_ _)) => + (match (string_drop _s1227_ _s1228_) with + | _s1229_ => + (sep_matches_prefix _s1229_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (tt,(existT _ _s1230_ _)) => + (match (string_drop _s1229_ _s1230_) with + | _s1231_ => + (reg_name_matches_prefix _s1231_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (rs1,(existT _ _s1232_ _)) => + (match (string_drop _s1231_ + _s1232_) with + | _s1233_ => + (sep_matches_prefix + _s1233_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__8 with + | Some + (tt,(existT _ _s1234_ _)) => + (match (string_drop + _s1233_ + _s1234_) with + | _s1235_ => + (reg_name_matches_prefix + _s1235_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__9 with + | Some + (rs2,(existT _ _s1236_ _)) => + let p0_ := + string_drop + _s1235_ + _s1236_ in + if ((generic_eq + p0_ + "")) + then + Some + ((op, width, aq, rl, rd, rs1, rs2)) + else + None + | _ => + None + end) + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + else + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))). + +Definition _s1192_ (_s1193_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) := + + let _s1194_ := _s1193_ in + (if ((string_startswith _s1194_ "sc.")) then + (match (string_drop _s1194_ (projT1 (string_length "sc."))) with + | _s1195_ => + (size_mnemonic_matches_prefix _s1195_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s1196_ _)) => + (match (string_drop _s1195_ _s1196_) with + | _s1197_ => + (maybe_aq_matches_prefix _s1197_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s1198_ _)) => + (match (string_drop _s1197_ _s1198_) with + | _s1199_ => + (maybe_rl_matches_prefix _s1199_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s1200_ _)) => + (match (string_drop _s1199_ _s1200_) with + | _s1201_ => + (spc_matches_prefix _s1201_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1202_ _)) => + (match (string_drop _s1201_ _s1202_) with + | _s1203_ => + (reg_name_matches_prefix _s1203_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s1204_ _)) => + (match (string_drop _s1203_ _s1204_) with + | _s1205_ => + (sep_matches_prefix _s1205_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1206_ _)) => + (match (string_drop _s1205_ _s1206_) with + | _s1207_ => + (reg_name_matches_prefix _s1207_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (rs1,(existT _ _s1208_ _)) => + (match (string_drop _s1207_ _s1208_) with + | _s1209_ => + (sep_matches_prefix _s1209_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (tt,(existT _ _s1210_ _)) => + (match (string_drop _s1209_ + _s1210_) with + | _s1211_ => + (reg_name_matches_prefix + _s1211_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__8 with + | Some + (rs2,(existT _ _s1212_ _)) => + let p0_ := + string_drop + _s1211_ + _s1212_ in + if ((generic_eq + p0_ "")) + then + Some + ((size, aq, rl, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))). + +Definition _s1174_ (_s1175_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5))) := + + let _s1176_ := _s1175_ in + (if ((string_startswith _s1176_ "lr.")) then + (match (string_drop _s1176_ (projT1 (string_length "lr."))) with + | _s1177_ => + (size_mnemonic_matches_prefix _s1177_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s1178_ _)) => + (match (string_drop _s1177_ _s1178_) with + | _s1179_ => + (maybe_aq_matches_prefix _s1179_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s1180_ _)) => + (match (string_drop _s1179_ _s1180_) with + | _s1181_ => + (maybe_rl_matches_prefix _s1181_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s1182_ _)) => + (match (string_drop _s1181_ _s1182_) with + | _s1183_ => + (spc_matches_prefix _s1183_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1184_ _)) => + (match (string_drop _s1183_ _s1184_) with + | _s1185_ => + (reg_name_matches_prefix _s1185_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s1186_ _)) => + (match (string_drop _s1185_ _s1186_) with + | _s1187_ => + (sep_matches_prefix _s1187_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1188_ _)) => + (match (string_drop _s1187_ _s1188_) with + | _s1189_ => + (reg_name_matches_prefix _s1189_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs1,(existT _ _s1190_ _)) => + let p0_ := + string_drop _s1189_ _s1190_ in + if ((generic_eq p0_ "")) then + Some + ((size, aq, rl, rd, rs1)) + else None + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5))). + +Definition _s1162_ (_s1163_ : string) +: M (option ((mword 5 * mword 5))) := + + let _s1164_ := _s1163_ in + (if ((string_startswith _s1164_ "sfence.vma")) then + (match (string_drop _s1164_ (projT1 (string_length "sfence.vma"))) with + | _s1165_ => + (spc_matches_prefix _s1165_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1166_ _)) => + (match (string_drop _s1165_ _s1166_) with + | _s1167_ => + (reg_name_matches_prefix _s1167_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs1,(existT _ _s1168_ _)) => + (match (string_drop _s1167_ _s1168_) with + | _s1169_ => + (sep_matches_prefix _s1169_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1170_ _)) => + (match (string_drop _s1169_ _s1170_) with + | _s1171_ => + (reg_name_matches_prefix _s1171_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s1172_ _)) => + let p0_ := string_drop _s1171_ _s1172_ in + if ((generic_eq p0_ "")) then Some ((rs1, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5))). + +Definition _s1150_ (_s1151_ : string) +: M (option ((mword 4 * mword 4))) := + + let _s1152_ := _s1151_ in + (if ((string_startswith _s1152_ "fence.tso")) then + (match (string_drop _s1152_ (projT1 (string_length "fence.tso"))) with + | _s1153_ => + (spc_matches_prefix _s1153_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1154_ _)) => + (match (string_drop _s1153_ _s1154_) with + | _s1155_ => + (fence_bits_matches_prefix _s1155_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (pred,(existT _ _s1156_ _)) => + (match (string_drop _s1155_ _s1156_) with + | _s1157_ => + (sep_matches_prefix _s1157_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1158_ _)) => + (match (string_drop _s1157_ _s1158_) with + | _s1159_ => + (fence_bits_matches_prefix _s1159_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (succ,(existT _ _s1160_ _)) => + let p0_ := string_drop _s1159_ _s1160_ in + if ((generic_eq p0_ "")) then Some ((pred, succ)) + else None + | _ => None + end) + : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + else returnm (None : option ((mword 4 * mword 4)))) + : M (option ((mword 4 * mword 4))). + +Definition _s1138_ (_s1139_ : string) +: M (option ((mword 4 * mword 4))) := + + let _s1140_ := _s1139_ in + (if ((string_startswith _s1140_ "fence")) then + (match (string_drop _s1140_ (projT1 (string_length "fence"))) with + | _s1141_ => + (spc_matches_prefix _s1141_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1142_ _)) => + (match (string_drop _s1141_ _s1142_) with + | _s1143_ => + (fence_bits_matches_prefix _s1143_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (pred,(existT _ _s1144_ _)) => + (match (string_drop _s1143_ _s1144_) with + | _s1145_ => + (sep_matches_prefix _s1145_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1146_ _)) => + (match (string_drop _s1145_ _s1146_) with + | _s1147_ => + (fence_bits_matches_prefix _s1147_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (succ,(existT _ _s1148_ _)) => + let p0_ := string_drop _s1147_ _s1148_ in + if ((generic_eq p0_ "")) then Some ((pred, succ)) + else None + | _ => None + end) + : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + else returnm (None : option ((mword 4 * mword 4)))) + : M (option ((mword 4 * mword 4))). + +Definition _s1119_ (_s1120_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1121_ := _s1120_ in + (if ((string_startswith _s1121_ "rem")) then + (match (string_drop _s1121_ (projT1 (string_length "rem"))) with + | _s1122_ => + (maybe_not_u_matches_prefix _s1122_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1123_ _)) => + let _s1124_ := string_drop _s1122_ _s1123_ in + (if ((string_startswith _s1124_ "w")) then + (match (string_drop _s1124_ (projT1 (string_length "w"))) with + | _s1125_ => + (spc_matches_prefix _s1125_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1126_ _)) => + (match (string_drop _s1125_ _s1126_) with + | _s1127_ => + (reg_name_matches_prefix _s1127_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1128_ _)) => + (match (string_drop _s1127_ _s1128_) with + | _s1129_ => + (sep_matches_prefix _s1129_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1130_ _)) => + (match (string_drop _s1129_ _s1130_) with + | _s1131_ => + (reg_name_matches_prefix _s1131_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1132_ _)) => + (match (string_drop _s1131_ _s1132_) with + | _s1133_ => + (sep_matches_prefix _s1133_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1134_ _)) => + (match (string_drop _s1133_ _s1134_) with + | _s1135_ => + (reg_name_matches_prefix _s1135_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1136_ _)) => + let p0_ := + string_drop _s1135_ + _s1136_ in + if ((generic_eq p0_ "")) + then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1100_ (_s1101_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1102_ := _s1101_ in + (if ((string_startswith _s1102_ "div")) then + (match (string_drop _s1102_ (projT1 (string_length "div"))) with + | _s1103_ => + (maybe_not_u_matches_prefix _s1103_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1104_ _)) => + let _s1105_ := string_drop _s1103_ _s1104_ in + (if ((string_startswith _s1105_ "w")) then + (match (string_drop _s1105_ (projT1 (string_length "w"))) with + | _s1106_ => + (spc_matches_prefix _s1106_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1107_ _)) => + (match (string_drop _s1106_ _s1107_) with + | _s1108_ => + (reg_name_matches_prefix _s1108_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1109_ _)) => + (match (string_drop _s1108_ _s1109_) with + | _s1110_ => + (sep_matches_prefix _s1110_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1111_ _)) => + (match (string_drop _s1110_ _s1111_) with + | _s1112_ => + (reg_name_matches_prefix _s1112_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1113_ _)) => + (match (string_drop _s1112_ _s1113_) with + | _s1114_ => + (sep_matches_prefix _s1114_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1115_ _)) => + (match (string_drop _s1114_ _s1115_) with + | _s1116_ => + (reg_name_matches_prefix _s1116_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1117_ _)) => + let p0_ := + string_drop _s1116_ + _s1117_ in + if ((generic_eq p0_ "")) + then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1084_ (_s1085_ : string) +: M (option ((mword 5 * mword 5 * mword 5))) := + + let _s1086_ := _s1085_ in + (if ((string_startswith _s1086_ "mulw")) then + (match (string_drop _s1086_ (projT1 (string_length "mulw"))) with + | _s1087_ => + (spc_matches_prefix _s1087_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1088_ _)) => + (match (string_drop _s1087_ _s1088_) with + | _s1089_ => + (reg_name_matches_prefix _s1089_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1090_ _)) => + (match (string_drop _s1089_ _s1090_) with + | _s1091_ => + (sep_matches_prefix _s1091_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1092_ _)) => + (match (string_drop _s1091_ _s1092_) with + | _s1093_ => + (reg_name_matches_prefix _s1093_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s1094_ _)) => + (match (string_drop _s1093_ _s1094_) with + | _s1095_ => + (sep_matches_prefix _s1095_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s1096_ _)) => + (match (string_drop _s1095_ _s1096_) with + | _s1097_ => + (reg_name_matches_prefix _s1097_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (rs2,(existT _ _s1098_ _)) => + let p0_ := + string_drop _s1097_ _s1098_ in + if ((generic_eq p0_ "")) then + Some + ((rd, rs1, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5 * mword 5))). + +Definition _s1066_ (_s1067_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1068_ := _s1067_ in + (if ((string_startswith _s1068_ "rem")) then + (match (string_drop _s1068_ (projT1 (string_length "rem"))) with + | _s1069_ => + (maybe_not_u_matches_prefix _s1069_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1070_ _)) => + (match (string_drop _s1069_ _s1070_) with + | _s1071_ => + (spc_matches_prefix _s1071_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1072_ _)) => + (match (string_drop _s1071_ _s1072_) with + | _s1073_ => + (reg_name_matches_prefix _s1073_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1074_ _)) => + (match (string_drop _s1073_ _s1074_) with + | _s1075_ => + (sep_matches_prefix _s1075_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1076_ _)) => + (match (string_drop _s1075_ _s1076_) with + | _s1077_ => + (reg_name_matches_prefix _s1077_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1078_ _)) => + (match (string_drop _s1077_ _s1078_) with + | _s1079_ => + (sep_matches_prefix _s1079_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1080_ _)) => + (match (string_drop _s1079_ _s1080_) with + | _s1081_ => + (reg_name_matches_prefix _s1081_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1082_ _)) => + let p0_ := + string_drop _s1081_ _s1082_ in + if ((generic_eq p0_ "")) then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1048_ (_s1049_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1050_ := _s1049_ in + (if ((string_startswith _s1050_ "div")) then + (match (string_drop _s1050_ (projT1 (string_length "div"))) with + | _s1051_ => + (maybe_not_u_matches_prefix _s1051_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1052_ _)) => + (match (string_drop _s1051_ _s1052_) with + | _s1053_ => + (spc_matches_prefix _s1053_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1054_ _)) => + (match (string_drop _s1053_ _s1054_) with + | _s1055_ => + (reg_name_matches_prefix _s1055_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1056_ _)) => + (match (string_drop _s1055_ _s1056_) with + | _s1057_ => + (sep_matches_prefix _s1057_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1058_ _)) => + (match (string_drop _s1057_ _s1058_) with + | _s1059_ => + (reg_name_matches_prefix _s1059_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1060_ _)) => + (match (string_drop _s1059_ _s1060_) with + | _s1061_ => + (sep_matches_prefix _s1061_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1062_ _)) => + (match (string_drop _s1061_ _s1062_) with + | _s1063_ => + (reg_name_matches_prefix _s1063_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1064_ _)) => + let p0_ := + string_drop _s1063_ _s1064_ in + if ((generic_eq p0_ "")) then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1031_ (_s1032_ : string) +: M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) := + + (match _s1032_ with + | _s1033_ => + (mul_mnemonic_matches_prefix _s1033_) >>= fun w__0 : option (((bool * bool * bool) * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some ((high, signed1, signed2),(existT _ _s1034_ _)) => + (match (string_drop _s1033_ _s1034_) with + | _s1035_ => + (spc_matches_prefix _s1035_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1036_ _)) => + (match (string_drop _s1035_ _s1036_) with + | _s1037_ => + (reg_name_matches_prefix _s1037_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1038_ _)) => + (match (string_drop _s1037_ _s1038_) with + | _s1039_ => + (sep_matches_prefix _s1039_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1040_ _)) => + (match (string_drop _s1039_ _s1040_) with + | _s1041_ => + (reg_name_matches_prefix _s1041_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1042_ _)) => + (match (string_drop _s1041_ _s1042_) with + | _s1043_ => + (sep_matches_prefix _s1043_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1044_ _)) => + (match (string_drop _s1043_ _s1044_) with + | _s1045_ => + (reg_name_matches_prefix _s1045_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s1046_ _)) => + let p0_ := + string_drop _s1045_ _s1046_ in + if ((generic_eq p0_ "")) then + Some + ((high, signed1, signed2, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))). + +Definition _s1016_ (_s1017_ : string) +: M (option ((sopw * mword 5 * mword 5 * mword 5))) := + + (match _s1017_ with + | _s1018_ => + (shiftiwop_mnemonic_matches_prefix _s1018_) >>= fun w__0 : option ((sopw * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1019_ _)) => + (match (string_drop _s1018_ _s1019_) with + | _s1020_ => + (spc_matches_prefix _s1020_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1021_ _)) => + (match (string_drop _s1020_ _s1021_) with + | _s1022_ => + (reg_name_matches_prefix _s1022_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1023_ _)) => + (match (string_drop _s1022_ _s1023_) with + | _s1024_ => + (sep_matches_prefix _s1024_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1025_ _)) => + (match (string_drop _s1024_ _s1025_) with + | _s1026_ => + (reg_name_matches_prefix _s1026_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (rs1,(existT _ _s1027_ _)) => + match (string_drop _s1026_ _s1027_) with + | _s1028_ => + match (hex_bits_5_matches_prefix _s1028_) with + | Some (shamt,(existT _ _s1029_ _)) => + let p0_ := string_drop _s1028_ _s1029_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))). + +Definition _s999_ (_s1000_ : string) +: M (option ((ropw * mword 5 * mword 5 * mword 5))) := + + (match _s1000_ with + | _s1001_ => + (rtypew_mnemonic_matches_prefix _s1001_) >>= fun w__0 : option ((ropw * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1002_ _)) => + (match (string_drop _s1001_ _s1002_) with + | _s1003_ => + (spc_matches_prefix _s1003_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1004_ _)) => + (match (string_drop _s1003_ _s1004_) with + | _s1005_ => + (reg_name_matches_prefix _s1005_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1006_ _)) => + (match (string_drop _s1005_ _s1006_) with + | _s1007_ => + (sep_matches_prefix _s1007_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1008_ _)) => + (match (string_drop _s1007_ _s1008_) with + | _s1009_ => + (reg_name_matches_prefix _s1009_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1010_ _)) => + (match (string_drop _s1009_ _s1010_) with + | _s1011_ => + (sep_matches_prefix _s1011_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1012_ _)) => + (match (string_drop _s1011_ _s1012_) with + | _s1013_ => + (reg_name_matches_prefix _s1013_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s1014_ _)) => + let p0_ := + string_drop _s1013_ _s1014_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))). + +Definition _s982_ (_s983_ : string) +: M (option ((sop * mword 5 * mword 5 * mword 5))) := + + (match _s983_ with + | _s984_ => + (shiftw_mnemonic_matches_prefix _s984_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s985_ _)) => + (match (string_drop _s984_ _s985_) with + | _s986_ => + (spc_matches_prefix _s986_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__1 with + | Some (tt,(existT _ _s987_ _)) => + (match (string_drop _s986_ _s987_) with + | _s988_ => + (reg_name_matches_prefix _s988_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s989_ _)) => + (match (string_drop _s988_ _s989_) with + | _s990_ => + (sep_matches_prefix _s990_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s991_ _)) => + (match (string_drop _s990_ _s991_) with + | _s992_ => + (reg_name_matches_prefix _s992_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s993_ _)) => + (match (string_drop _s992_ _s993_) with + | _s994_ => + (sep_matches_prefix _s994_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s995_ _)) => + match (string_drop _s994_ _s995_) with + | _s996_ => + match (hex_bits_5_matches_prefix + _s996_) with + | Some (shamt,(existT _ _s997_ _)) => + let p0_ := + string_drop _s996_ _s997_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))). + +Definition _s966_ (_s967_ : string) +: M (option ((mword 5 * mword 5 * mword 12))) := + + let _s968_ := _s967_ in + (if ((string_startswith _s968_ "addiw")) then + (match (string_drop _s968_ (projT1 (string_length "addiw"))) with + | _s969_ => + (spc_matches_prefix _s969_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s970_ _)) => + (match (string_drop _s969_ _s970_) with + | _s971_ => + (reg_name_matches_prefix _s971_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s972_ _)) => + (match (string_drop _s971_ _s972_) with + | _s973_ => + (sep_matches_prefix _s973_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s974_ _)) => + (match (string_drop _s973_ _s974_) with + | _s975_ => + (reg_name_matches_prefix _s975_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s976_ _)) => + (match (string_drop _s975_ _s976_) with + | _s977_ => + (sep_matches_prefix _s977_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s978_ _)) => + match (string_drop _s977_ _s978_) with + | _s979_ => + match (hex_bits_12_matches_prefix _s979_) with + | Some (imm,(existT _ _s980_ _)) => + let p0_ := string_drop _s979_ _s980_ in + if ((generic_eq p0_ "")) then + Some + ((rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + else returnm (None : option ((mword 5 * mword 5 * mword 12)))) + : M (option ((mword 5 * mword 5 * mword 12))). + +Definition _s944_ (_s945_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) := + + let _s946_ := _s945_ in + (if ((string_startswith _s946_ "s")) then + (match (string_drop _s946_ (projT1 (string_length "s"))) with + | _s947_ => + (size_mnemonic_matches_prefix _s947_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s948_ _)) => + (match (string_drop _s947_ _s948_) with + | _s949_ => + (maybe_aq_matches_prefix _s949_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s950_ _)) => + (match (string_drop _s949_ _s950_) with + | _s951_ => + (maybe_rl_matches_prefix _s951_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s952_ _)) => + (match (string_drop _s951_ _s952_) with + | _s953_ => + (spc_matches_prefix _s953_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s954_ _)) => + (match (string_drop _s953_ _s954_) with + | _s955_ => + (reg_name_matches_prefix _s955_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s956_ _)) => + (match (string_drop _s955_ _s956_) with + | _s957_ => + (sep_matches_prefix _s957_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s958_ _)) => + (match (string_drop _s957_ _s958_) with + | _s959_ => + (reg_name_matches_prefix _s959_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (rs1,(existT _ _s960_ _)) => + (match (string_drop _s959_ _s960_) with + | _s961_ => + (sep_matches_prefix _s961_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__7 with + | Some + (tt,(existT _ _s962_ _)) => + match (string_drop + _s961_ + _s962_) with + | _s963_ => + match (hex_bits_12_matches_prefix + _s963_) with + | Some + (imm,(existT _ _s964_ _)) => + let p0_ := + string_drop + _s963_ + _s964_ in + if ((generic_eq + p0_ "")) + then + Some + ((size, aq, rl, rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))). + +Definition _s920_ (_s921_ : string) +: M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) := + + let _s922_ := _s921_ in + (if ((string_startswith _s922_ "l")) then + (match (string_drop _s922_ (projT1 (string_length "l"))) with + | _s923_ => + (size_mnemonic_matches_prefix _s923_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s924_ _)) => + (match (string_drop _s923_ _s924_) with + | _s925_ => + (maybe_u_matches_prefix _s925_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (is_unsigned,(existT _ _s926_ _)) => + (match (string_drop _s925_ _s926_) with + | _s927_ => + (maybe_aq_matches_prefix _s927_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (aq,(existT _ _s928_ _)) => + (match (string_drop _s927_ _s928_) with + | _s929_ => + (maybe_rl_matches_prefix _s929_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rl,(existT _ _s930_ _)) => + (match (string_drop _s929_ _s930_) with + | _s931_ => + (spc_matches_prefix _s931_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s932_ _)) => + (match (string_drop _s931_ _s932_) with + | _s933_ => + (reg_name_matches_prefix _s933_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (rd,(existT _ _s934_ _)) => + (match (string_drop _s933_ _s934_) with + | _s935_ => + (sep_matches_prefix _s935_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (tt,(existT _ _s936_ _)) => + (match (string_drop _s935_ _s936_) with + | _s937_ => + (reg_name_matches_prefix _s937_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (rs1,(existT _ _s938_ _)) => + (match (string_drop _s937_ + _s938_) with + | _s939_ => + (sep_matches_prefix _s939_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__8 with + | Some + (tt,(existT _ _s940_ _)) => + match (string_drop + _s939_ + _s940_) with + | _s941_ => + match (hex_bits_12_matches_prefix + _s941_) with + | Some + (imm,(existT _ _s942_ _)) => + let p0_ := + string_drop + _s941_ + _s942_ in + if ((generic_eq + p0_ + "")) + then + Some + ((size, is_unsigned, aq, rl, rd, rs1, imm)) + else + None + | _ => + None + end + end + | _ => None + end) + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + else returnm (None : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12)))) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))). + +Definition _s903_ (_s904_ : string) +: M (option ((rop * mword 5 * mword 5 * mword 5))) := + + (match _s904_ with + | _s905_ => + (rtype_mnemonic_matches_prefix _s905_) >>= fun w__0 : option ((rop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s906_ _)) => + (match (string_drop _s905_ _s906_) with + | _s907_ => + (spc_matches_prefix _s907_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__1 with + | Some (tt,(existT _ _s908_ _)) => + (match (string_drop _s907_ _s908_) with + | _s909_ => + (reg_name_matches_prefix _s909_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s910_ _)) => + (match (string_drop _s909_ _s910_) with + | _s911_ => + (sep_matches_prefix _s911_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s912_ _)) => + (match (string_drop _s911_ _s912_) with + | _s913_ => + (reg_name_matches_prefix _s913_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s914_ _)) => + (match (string_drop _s913_ _s914_) with + | _s915_ => + (sep_matches_prefix _s915_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s916_ _)) => + (match (string_drop _s915_ _s916_) with + | _s917_ => + (reg_name_matches_prefix _s917_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s918_ _)) => + let p0_ := + string_drop _s917_ _s918_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))). + +Definition _s888_ (_s889_ : string) +: M (option ((sop * mword 5 * mword 5 * mword 6))) := + + (match _s889_ with + | _s890_ => + (shiftiop_mnemonic_matches_prefix _s890_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s891_ _)) => + (match (string_drop _s890_ _s891_) with + | _s892_ => + (spc_matches_prefix _s892_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__1 with + | Some (tt,(existT _ _s893_ _)) => + (match (string_drop _s892_ _s893_) with + | _s894_ => + (reg_name_matches_prefix _s894_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s895_ _)) => + (match (string_drop _s894_ _s895_) with + | _s896_ => + (sep_matches_prefix _s896_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s897_ _)) => + (match (string_drop _s896_ _s897_) with + | _s898_ => + (reg_name_matches_prefix _s898_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (rs1,(existT _ _s899_ _)) => + match (string_drop _s898_ _s899_) with + | _s900_ => + match (hex_bits_6_matches_prefix _s900_) with + | Some (shamt,(existT _ _s901_ _)) => + let p0_ := string_drop _s900_ _s901_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => + returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))). + +Definition _s871_ (_s872_ : string) +: M (option ((iop * mword 5 * mword 5 * mword 12))) := + + (match _s872_ with + | _s873_ => + (itype_mnemonic_matches_prefix _s873_) >>= fun w__0 : option ((iop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s874_ _)) => + (match (string_drop _s873_ _s874_) with + | _s875_ => + (spc_matches_prefix _s875_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__1 with + | Some (tt,(existT _ _s876_ _)) => + (match (string_drop _s875_ _s876_) with + | _s877_ => + (reg_name_matches_prefix _s877_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s878_ _)) => + (match (string_drop _s877_ _s878_) with + | _s879_ => + (sep_matches_prefix _s879_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s880_ _)) => + (match (string_drop _s879_ _s880_) with + | _s881_ => + (reg_name_matches_prefix _s881_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s882_ _)) => + (match (string_drop _s881_ _s882_) with + | _s883_ => + (sep_matches_prefix _s883_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s884_ _)) => + match (string_drop _s883_ _s884_) with + | _s885_ => + match (hex_bits_12_matches_prefix + _s885_) with + | Some (imm,(existT _ _s886_ _)) => + let p0_ := + string_drop _s885_ _s886_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))). + +Definition _s854_ (_s855_ : string) +: M (option ((bop * mword 5 * mword 5 * mword 13))) := + + (match _s855_ with + | _s856_ => + (btype_mnemonic_matches_prefix _s856_) >>= fun w__0 : option ((bop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s857_ _)) => + (match (string_drop _s856_ _s857_) with + | _s858_ => + (spc_matches_prefix _s858_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__1 with + | Some (tt,(existT _ _s859_ _)) => + (match (string_drop _s858_ _s859_) with + | _s860_ => + (reg_name_matches_prefix _s860_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rs1,(existT _ _s861_ _)) => + (match (string_drop _s860_ _s861_) with + | _s862_ => + (sep_matches_prefix _s862_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s863_ _)) => + (match (string_drop _s862_ _s863_) with + | _s864_ => + (reg_name_matches_prefix _s864_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs2,(existT _ _s865_ _)) => + (match (string_drop _s864_ _s865_) with + | _s866_ => + (sep_matches_prefix _s866_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s867_ _)) => + match (string_drop _s866_ _s867_) with + | _s868_ => + match (hex_bits_13_matches_prefix + _s868_) with + | Some (imm,(existT _ _s869_ _)) => + let p0_ := + string_drop _s868_ _s869_ in + if ((generic_eq p0_ "")) then + Some + ((op, rs1, rs2, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => + returnm (None + : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => + returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))). + +Definition _s838_ (_s839_ : string) +: M (option ((mword 5 * mword 5 * mword 12))) := + + let _s840_ := _s839_ in + (if ((string_startswith _s840_ "jalr")) then + (match (string_drop _s840_ (projT1 (string_length "jalr"))) with + | _s841_ => + (spc_matches_prefix _s841_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s842_ _)) => + (match (string_drop _s841_ _s842_) with + | _s843_ => + (reg_name_matches_prefix _s843_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s844_ _)) => + (match (string_drop _s843_ _s844_) with + | _s845_ => + (sep_matches_prefix _s845_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s846_ _)) => + (match (string_drop _s845_ _s846_) with + | _s847_ => + (reg_name_matches_prefix _s847_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s848_ _)) => + (match (string_drop _s847_ _s848_) with + | _s849_ => + (sep_matches_prefix _s849_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s850_ _)) => + match (string_drop _s849_ _s850_) with + | _s851_ => + match (hex_bits_12_matches_prefix _s851_) with + | Some (imm,(existT _ _s852_ _)) => + let p0_ := string_drop _s851_ _s852_ in + if ((generic_eq p0_ "")) then + Some + ((rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + else returnm (None : option ((mword 5 * mword 5 * mword 12)))) + : M (option ((mword 5 * mword 5 * mword 12))). + +Definition _s826_ (_s827_ : string) +: M (option ((mword 5 * mword 21))) := + + let _s828_ := _s827_ in + (if ((string_startswith _s828_ "jal")) then + (match (string_drop _s828_ (projT1 (string_length "jal"))) with + | _s829_ => + (spc_matches_prefix _s829_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s830_ _)) => + (match (string_drop _s829_ _s830_) with + | _s831_ => + (reg_name_matches_prefix _s831_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s832_ _)) => + (match (string_drop _s831_ _s832_) with + | _s833_ => + (sep_matches_prefix _s833_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s834_ _)) => + match (string_drop _s833_ _s834_) with + | _s835_ => + match (hex_bits_21_matches_prefix _s835_) with + | Some (imm,(existT _ _s836_ _)) => + let p0_ := string_drop _s835_ _s836_ in + if ((generic_eq p0_ "")) then Some ((rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + | _ => returnm (None : option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + | _ => returnm (None : option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + else returnm (None : option ((mword 5 * mword 21)))) + : M (option ((mword 5 * mword 21))). + +Definition _s813_ (_s814_ : string) +: M (option ((uop * mword 5 * mword 20))) := + + (match _s814_ with + | _s815_ => + (utype_mnemonic_matches_prefix _s815_) >>= fun w__0 : option ((uop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s816_ _)) => + (match (string_drop _s815_ _s816_) with + | _s817_ => + (spc_matches_prefix _s817_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__1 with + | Some (tt,(existT _ _s818_ _)) => + (match (string_drop _s817_ _s818_) with + | _s819_ => + (reg_name_matches_prefix _s819_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s820_ _)) => + (match (string_drop _s819_ _s820_) with + | _s821_ => + (sep_matches_prefix _s821_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (tt,(existT _ _s822_ _)) => + match (string_drop _s821_ _s822_) with + | _s823_ => + match (hex_bits_20_matches_prefix _s823_) with + | Some (imm,(existT _ _s824_ _)) => + let p0_ := string_drop _s823_ _s824_ in + if ((generic_eq p0_ "")) then Some ((op, rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + | _ => returnm (None : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + | _ => returnm (None : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + | _ => returnm (None : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))). + +Definition assembly_backwards (arg_ : string) +: M (ast) := + + let _s825_ := arg_ in + (_s813_ _s825_) >>= fun w__0 : option ((uop * mword 5 * mword 20)) => + (if ((match w__0 with | Some (op,rd,imm) => true | _ => false end)) then + (_s813_ _s825_) >>= fun w__1 : option ((uop * mword 5 * mword 20)) => + (match w__1 with + | Some (op,rd,imm) => returnm ((UTYPE ((imm, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s826_ _s825_) >>= fun w__4 : option ((mword 5 * mword 21)) => + (if ((match w__4 with | Some (rd,imm) => true | _ => false end)) then + (_s826_ _s825_) >>= fun w__5 : option ((mword 5 * mword 21)) => + (match w__5 with + | Some (rd,imm) => returnm ((RISCV_JAL ((imm, rd))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s838_ _s825_) >>= fun w__8 : option ((mword 5 * mword 5 * mword 12)) => + (if ((match w__8 with | Some (rd,rs1,imm) => true | _ => false end)) then + (_s838_ _s825_) >>= fun w__9 : option ((mword 5 * mword 5 * mword 12)) => + (match w__9 with + | Some (rd,rs1,imm) => returnm ((RISCV_JALR ((imm, rs1, rd))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s854_ _s825_) >>= fun w__12 : option ((bop * mword 5 * mword 5 * mword 13)) => + (if ((match w__12 with | Some (op,rs1,rs2,imm) => true | _ => false end)) then + (_s854_ _s825_) >>= fun w__13 : option ((bop * mword 5 * mword 5 * mword 13)) => + (match w__13 with + | Some (op,rs1,rs2,imm) => returnm ((BTYPE ((imm, rs2, rs1, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s871_ _s825_) >>= fun w__16 : option ((iop * mword 5 * mword 5 * mword 12)) => + (if ((match w__16 with | Some (op,rd,rs1,imm) => true | _ => false end)) then + (_s871_ _s825_) >>= fun w__17 : option ((iop * mword 5 * mword 5 * mword 12)) => + (match w__17 with + | Some (op,rd,rs1,imm) => returnm ((ITYPE ((imm, rs1, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s888_ _s825_) >>= fun w__20 : option ((sop * mword 5 * mword 5 * mword 6)) => + (if ((match w__20 with | Some (op,rd,rs1,shamt) => true | _ => false end)) then + (_s888_ _s825_) >>= fun w__21 : option ((sop * mword 5 * mword 5 * mword 6)) => + (match w__21 with + | Some (op,rd,rs1,shamt) => + returnm ((SHIFTIOP ((shamt, rs1, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s903_ _s825_) >>= fun w__24 : option ((rop * mword 5 * mword 5 * mword 5)) => + (if ((match w__24 with | Some (op,rd,rs1,rs2) => true | _ => false end)) then + (_s903_ _s825_) >>= fun w__25 : option ((rop * mword 5 * mword 5 * mword 5)) => + (match w__25 with + | Some (op,rd,rs1,rs2) => returnm ((RTYPE ((rs2, rs1, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s920_ _s825_) >>= fun w__28 : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12)) => + (if ((match w__28 with + | Some (size,is_unsigned,aq,rl,rd,rs1,imm) => true + | _ => false + end)) then + (_s920_ _s825_) >>= fun w__29 : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12)) => + (match w__29 with + | Some (size,is_unsigned,aq,rl,rd,rs1,imm) => + returnm ((LOAD ((imm, rs1, rd, is_unsigned, size, aq, rl))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s944_ _s825_) >>= fun w__32 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12)) => + (if ((match w__32 with + | Some (size,aq,rl,rd,rs1,imm) => true + | _ => false + end)) then + (_s944_ _s825_) >>= fun w__33 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12)) => + (match w__33 with + | Some (size,aq,rl,rd,rs1,imm) => + returnm ((STORE ((imm, rs1, rd, size, aq, rl))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s966_ _s825_) >>= fun w__36 : option ((mword 5 * mword 5 * mword 12)) => + (if ((match w__36 with | Some (rd,rs1,imm) => true | _ => false end)) + then + (_s966_ _s825_) >>= fun w__37 : option ((mword 5 * mword 5 * mword 12)) => + (match w__37 with + | Some (rd,rs1,imm) => returnm ((ADDIW ((imm, rs1, rd))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s982_ _s825_) >>= fun w__40 : option ((sop * mword 5 * mword 5 * mword 5)) => + (if ((match w__40 with + | Some (op,rd,rs1,shamt) => true + | _ => false + end)) then + (_s982_ _s825_) >>= fun w__41 : option ((sop * mword 5 * mword 5 * mword 5)) => + (match w__41 with + | Some (op,rd,rs1,shamt) => + returnm ((SHIFTW ((shamt, rs1, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s999_ _s825_) >>= fun w__44 : option ((ropw * mword 5 * mword 5 * mword 5)) => + (if ((match w__44 with + | Some (op,rd,rs1,rs2) => true + | _ => false + end)) then + (_s999_ _s825_) >>= fun w__45 : option ((ropw * mword 5 * mword 5 * mword 5)) => + (match w__45 with + | Some (op,rd,rs1,rs2) => + returnm ((RTYPEW ((rs2, rs1, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1016_ _s825_) >>= fun w__48 : option ((sopw * mword 5 * mword 5 * mword 5)) => + (if ((match w__48 with + | Some (op,rd,rs1,shamt) => true + | _ => false + end)) then + (_s1016_ _s825_) >>= fun w__49 : option ((sopw * mword 5 * mword 5 * mword 5)) => + (match w__49 with + | Some (op,rd,rs1,shamt) => + returnm ((SHIFTIWOP ((shamt, rs1, rd, op))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1031_ _s825_) >>= fun w__52 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__52 with + | Some (high,signed1,signed2,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1031_ _s825_) >>= fun w__53 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) => + (match w__53 with + | Some (high,signed1,signed2,rd,rs1,rs2) => + returnm ((MUL + ((rs2, rs1, rd, high, signed1, signed2))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1048_ _s825_) >>= fun w__56 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__56 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1048_ _s825_) >>= fun w__57 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__57 with + | Some (s,rd,rs1,rs2) => + returnm ((DIV ((rs2, rs1, rd, s))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1066_ _s825_) >>= fun w__60 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__60 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1066_ _s825_) >>= fun w__61 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__61 with + | Some (s,rd,rs1,rs2) => + returnm ((REM ((rs2, rs1, rd, s))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1084_ _s825_) >>= fun w__64 : option ((mword 5 * mword 5 * mword 5)) => + (if ((match w__64 with + | Some (rd,rs1,rs2) => true + | _ => false + end)) then + (_s1084_ _s825_) >>= fun w__65 : option ((mword 5 * mword 5 * mword 5)) => + (match w__65 with + | Some (rd,rs1,rs2) => + returnm ((MULW ((rs2, rs1, rd))) : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1100_ _s825_) >>= fun w__68 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__68 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1100_ _s825_) >>= fun w__69 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__69 with + | Some (s,rd,rs1,rs2) => + returnm ((DIVW + ((rs2, rs1, rd, s))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1119_ _s825_) >>= fun w__72 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__72 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1119_ _s825_) >>= fun w__73 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__73 with + | Some (s,rd,rs1,rs2) => + returnm ((REMW + ((rs2, rs1, rd, s))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1138_ _s825_) >>= fun w__76 : option ((mword 4 * mword 4)) => + (if ((match w__76 with + | Some (pred,succ) => true + | _ => false + end)) then + (_s1138_ _s825_) >>= fun w__77 : option ((mword 4 * mword 4)) => + (match w__77 with + | Some (pred,succ) => + returnm ((FENCE + ((pred, succ))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1150_ _s825_) >>= fun w__80 : option ((mword 4 * mword 4)) => + (if ((match w__80 with + | Some (pred,succ) => true + | _ => false + end)) then + (_s1150_ _s825_) >>= fun w__81 : option ((mword 4 * mword 4)) => + (match w__81 with + | Some (pred,succ) => + returnm ((FENCE_TSO + ((pred, succ))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else if ((generic_eq _s825_ + "fence.i")) then + returnm ((FENCEI + (tt)) + : ast ) + else if ((generic_eq _s825_ "ecall")) + then + returnm ((ECALL + (tt)) + : ast ) + else if ((generic_eq _s825_ "mret")) + then + returnm ((MRET + (tt)) + : ast ) + else if ((generic_eq _s825_ "sret")) + then + returnm ((SRET + (tt)) + : ast ) + else if ((generic_eq _s825_ "ebreak")) + then + returnm ((EBREAK + (tt)) + : ast ) + else if ((generic_eq _s825_ "wfi")) + then + returnm ((WFI + (tt)) + : ast ) + else + (_s1162_ _s825_) >>= fun w__84 : option ((mword 5 * mword 5)) => + (if ((match w__84 with + | Some (rs1,rs2) => true + | _ => false + end)) then + (_s1162_ _s825_) >>= fun w__85 : option ((mword 5 * mword 5)) => + (match w__85 with + | Some (rs1,rs2) => + returnm ((SFENCE_VMA + ((rs1, rs2))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1174_ _s825_) >>= fun w__88 : option ((word_width * bool * bool * mword 5 * mword 5)) => + (if ((match w__88 with + | Some + (size,aq,rl,rd,rs1) => + true + | _ => false + end)) then + (_s1174_ _s825_) >>= fun w__89 : option ((word_width * bool * bool * mword 5 * mword 5)) => + (match w__89 with + | Some (size,aq,rl,rd,rs1) => + returnm ((LOADRES + ((aq, rl, rs1, size, rd))) + : ast ) + | _ => exit tt : M (ast) + end) + : M (ast) + else + (_s1192_ _s825_) >>= fun w__92 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__92 with + | Some + (size,aq,rl,rd,rs1,rs2) => + true + | _ => false + end)) then + (_s1192_ _s825_) >>= fun w__93 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (match w__93 with + | Some + (size,aq,rl,rd,rs1,rs2) => + returnm ((STORECON + ((aq, rl, rs2, rs1, size, rd))) + : ast ) + | _ => + exit tt : M (ast) + end) + : M (ast) + else + (_s1214_ _s825_) >>= fun w__96 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__96 with + | Some + (op,width,aq,rl,rd,rs1,rs2) => + true + | _ => false + end)) then + (_s1214_ _s825_) >>= fun w__97 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (match w__97 with + | Some + (op,width,aq,rl,rd,rs1,rs2) => + returnm ((AMO + ((op, aq, rl, rs2, rs1, width, rd))) + : ast ) + | _ => + exit tt : M (ast) + end) + : M (ast) + else + (_s1238_ _s825_) >>= fun w__100 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (if ((match w__100 with + | Some + (op,rd,rs1,csr) => + true + | _ => false + end)) then + (_s1238_ _s825_) >>= fun w__101 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (match w__101 with + | Some + (op,rd,rs1,csr) => + returnm ((CSR + ((csr, rs1, rd, true, op))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1256_ _s825_) >>= fun w__104 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (if ((match w__104 with + | Some + (op,rd,rs1,csr) => + true + | _ => false + end)) then + (_s1256_ _s825_) >>= fun w__105 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (match w__105 with + | Some + (op,rd,rs1,csr) => + returnm ((CSR + ((csr, rs1, rd, false, op))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else if ((generic_eq + _s825_ + "c.nop")) + then + returnm ((C_NOP + (tt)) + : ast ) + else + (_s1273_ _s825_) >>= fun w__108 : option ((mword 3 * mword 8)) => + (if ((match w__108 with + | Some + (rdc,nzimm) => + neq_vec + nzimm + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : mword 8) + | _ => + false + end)) then + (_s1273_ + _s825_) >>= fun w__109 : option ((mword 3 * mword 8)) => + (match w__109 with + | Some + (rdc,nzimm) => + returnm ((C_ADDI4SPN + ((rdc, nzimm))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1285_ + _s825_) >>= fun w__112 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__112 with + | Some + (rdc,rsc,uimm) => + true + | _ => + false + end)) + then + (_s1285_ + _s825_) >>= fun w__113 : option ((mword 3 * mword 3 * mword 5)) => + (match w__113 with + | Some + (rdc,rsc,uimm) => + returnm ((C_LW + ((uimm, rsc, rdc))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1301_ + _s825_) >>= fun w__116 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__116 with + | Some + (rdc,rsc,uimm) => + true + | _ => + false + end)) + then + (_s1301_ + _s825_) >>= fun w__117 : option ((mword 3 * mword 3 * mword 5)) => + (match w__117 with + | Some + (rdc,rsc,uimm) => + returnm ((C_LD + ((uimm, rsc, rdc))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1317_ + _s825_) >>= fun w__120 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__120 with + | Some + (rsc1,rsc2,uimm) => + true + | _ => + false + end)) + then + (_s1317_ + _s825_) >>= fun w__121 : option ((mword 3 * mword 3 * mword 5)) => + (match w__121 with + | Some + (rsc1,rsc2,uimm) => + returnm ((C_SW + ((uimm, rsc1, rsc2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1333_ + _s825_) >>= fun w__124 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__124 with + | Some + (rsc1,rsc2,uimm) => + true + | _ => + false + end)) + then + (_s1333_ + _s825_) >>= fun w__125 : option ((mword 3 * mword 3 * mword 5)) => + (match w__125 with + | Some + (rsc1,rsc2,uimm) => + returnm ((C_SD + ((uimm, rsc1, rsc2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1349_ + _s825_) >>= fun w__128 : option ((mword 5 * mword 6)) => + (if + ((match w__128 with + | Some + (rsd,nzi) => + andb + (neq_vec + nzi + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6)) + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s1349_ + _s825_) >>= fun w__129 : option ((mword 5 * mword 6)) => + (match w__129 with + | Some + (rsd,nzi) => + returnm ((C_ADDI + ((nzi, rsd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1361_ + _s825_) >>= fun w__132 : option (mword 11) => + (if + ((match w__132 with + | Some + (imm) => + true + | _ => + false + end)) + then + (_s1361_ + _s825_) >>= fun w__133 : option (mword 11) => + (match w__133 with + | Some + (imm) => + returnm ((C_JAL + (imm)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1369_ + _s825_) >>= fun w__136 : option ((mword 5 * mword 6)) => + (if + ((match w__136 with + | Some + (rsd,imm) => + true + | _ => + false + end)) + then + (_s1369_ + _s825_) >>= fun w__137 : option ((mword 5 * mword 6)) => + (match w__137 with + | Some + (rsd,imm) => + returnm ((C_ADDIW + ((imm, rsd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1381_ + _s825_) >>= fun w__140 : option ((mword 5 * mword 6)) => + (if + ((match w__140 with + | Some + (rd,imm) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s1381_ + _s825_) >>= fun w__141 : option ((mword 5 * mword 6)) => + (match w__141 with + | Some + (rd,imm) => + returnm ((C_LI + ((imm, rd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1393_ + _s825_) >>= fun w__144 : option (mword 6) => + (if + ((match w__144 with + | Some + (imm) => + neq_vec + imm + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s1393_ + _s825_) >>= fun w__145 : option (mword 6) => + (match w__145 with + | Some + (imm) => + returnm ((C_ADDI16SP + (imm)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1401_ + _s825_) >>= fun w__148 : option ((mword 5 * mword 6)) => + (if + ((match w__148 with + | Some + (rd,imm) => + andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg))) + (andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + sp))) + (neq_vec + imm + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6))) + | _ => + false + end)) + then + (_s1401_ + _s825_) >>= fun w__149 : option ((mword 5 * mword 6)) => + (match w__149 with + | Some + (rd,imm) => + returnm ((C_LUI + ((imm, rd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1413_ + _s825_) >>= fun w__152 : option ((mword 3 * mword 6)) => + (if + ((match w__152 with + | Some + (rsd,shamt) => + neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s1413_ + _s825_) >>= fun w__153 : option ((mword 3 * mword 6)) => + (match w__153 with + | Some + (rsd,shamt) => + returnm ((C_SRLI + ((shamt, rsd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1425_ + _s825_) >>= fun w__156 : option ((mword 3 * mword 6)) => + (if + ((match w__156 with + | Some + (rsd,shamt) => + neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s1425_ + _s825_) >>= fun w__157 : option ((mword 3 * mword 6)) => + (match w__157 with + | Some + (rsd,shamt) => + returnm ((C_SRAI + ((shamt, rsd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1437_ + _s825_) >>= fun w__160 : option ((mword 3 * mword 6)) => + (if + ((match w__160 with + | Some + (rsd,imm) => + true + | _ => + false + end)) + then + (_s1437_ + _s825_) >>= fun w__161 : option ((mword 3 * mword 6)) => + (match w__161 with + | Some + (rsd,imm) => + returnm ((C_ANDI + ((imm, rsd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1449_ + _s825_) >>= fun w__164 : option ((mword 3 * mword 3)) => + (if + ((match w__164 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s1449_ + _s825_) >>= fun w__165 : option ((mword 3 * mword 3)) => + (match w__165 with + | Some + (rsd,rs2) => + returnm ((C_SUB + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1461_ + _s825_) >>= fun w__168 : option ((mword 3 * mword 3)) => + (if + ((match w__168 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s1461_ + _s825_) >>= fun w__169 : option ((mword 3 * mword 3)) => + (match w__169 with + | Some + (rsd,rs2) => + returnm ((C_XOR + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1473_ + _s825_) >>= fun w__172 : option ((mword 3 * mword 3)) => + (if + ((match w__172 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s1473_ + _s825_) >>= fun w__173 : option ((mword 3 * mword 3)) => + (match w__173 with + | Some + (rsd,rs2) => + returnm ((C_OR + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1485_ + _s825_) >>= fun w__176 : option ((mword 3 * mword 3)) => + (if + ((match w__176 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s1485_ + _s825_) >>= fun w__177 : option ((mword 3 * mword 3)) => + (match w__177 with + | Some + (rsd,rs2) => + returnm ((C_AND + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1497_ + _s825_) >>= fun w__180 : option ((mword 3 * mword 3)) => + (if + ((match w__180 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s1497_ + _s825_) >>= fun w__181 : option ((mword 3 * mword 3)) => + (match w__181 with + | Some + (rsd,rs2) => + returnm ((C_SUBW + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1509_ + _s825_) >>= fun w__184 : option ((mword 3 * mword 3)) => + (if + ((match w__184 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s1509_ + _s825_) >>= fun w__185 : option ((mword 3 * mword 3)) => + (match w__185 with + | Some + (rsd,rs2) => + returnm ((C_ADDW + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1521_ + _s825_) >>= fun w__188 : option (mword 11) => + (if + ((match w__188 with + | Some + (imm) => + true + | _ => + false + end)) + then + (_s1521_ + _s825_) >>= fun w__189 : option (mword 11) => + (match w__189 with + | Some + (imm) => + returnm ((C_J + (imm)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1529_ + _s825_) >>= fun w__192 : option ((mword 3 * mword 8)) => + (if + ((match w__192 with + | Some + (rs,imm) => + true + | _ => + false + end)) + then + (_s1529_ + _s825_) >>= fun w__193 : option ((mword 3 * mword 8)) => + (match w__193 with + | Some + (rs,imm) => + returnm ((C_BEQZ + ((imm, rs))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1541_ + _s825_) >>= fun w__196 : option ((mword 3 * mword 8)) => + (if + ((match w__196 with + | Some + (rs,imm) => + true + | _ => + false + end)) + then + (_s1541_ + _s825_) >>= fun w__197 : option ((mword 3 * mword 8)) => + (match w__197 with + | Some + (rs,imm) => + returnm ((C_BNEZ + ((imm, rs))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1553_ + _s825_) >>= fun w__200 : option ((mword 5 * mword 6)) => + (if + ((match w__200 with + | Some + (rsd,shamt) => + andb + (neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6)) + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s1553_ + _s825_) >>= fun w__201 : option ((mword 5 * mword 6)) => + (match w__201 with + | Some + (rsd,shamt) => + returnm ((C_SLLI + ((shamt, rsd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1565_ + _s825_) >>= fun w__204 : option ((mword 5 * mword 6)) => + (if + ((match w__204 with + | Some + (rd,uimm) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s1565_ + _s825_) >>= fun w__205 : option ((mword 5 * mword 6)) => + (match w__205 with + | Some + (rd,uimm) => + returnm ((C_LWSP + ((uimm, rd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1577_ + _s825_) >>= fun w__208 : option ((mword 5 * mword 6)) => + (if + ((match w__208 with + | Some + (rd,uimm) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s1577_ + _s825_) >>= fun w__209 : option ((mword 5 * mword 6)) => + (match w__209 with + | Some + (rd,uimm) => + returnm ((C_LDSP + ((uimm, rd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1589_ + _s825_) >>= fun w__212 : option ((mword 5 * mword 6)) => + (if + ((match w__212 with + | Some + (rd,uimm) => + true + | _ => + false + end)) + then + (_s1589_ + _s825_) >>= fun w__213 : option ((mword 5 * mword 6)) => + (match w__213 with + | Some + (rd,uimm) => + returnm ((C_SWSP + ((uimm, rd))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1601_ + _s825_) >>= fun w__216 : option ((mword 5 * mword 6)) => + (if + ((match w__216 with + | Some + (rs2,uimm) => + true + | _ => + false + end)) + then + (_s1601_ + _s825_) >>= fun w__217 : option ((mword 5 * mword 6)) => + (match w__217 with + | Some + (rs2,uimm) => + returnm ((C_SDSP + ((uimm, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1613_ + _s825_) >>= fun w__220 : option (mword 5) => + (if + ((match w__220 with + | Some + (rs1) => + neq_int + (projT1 (regbits_to_regno + rs1)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s1613_ + _s825_) >>= fun w__221 : option (mword 5) => + (match w__221 with + | Some + (rs1) => + returnm ((C_JR + (rs1)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1621_ + _s825_) >>= fun w__224 : option (mword 5) => + (if + ((match w__224 with + | Some + (rs1) => + neq_int + (projT1 (regbits_to_regno + rs1)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s1621_ + _s825_) >>= fun w__225 : option (mword 5) => + (match w__225 with + | Some + (rs1) => + returnm ((C_JALR + (rs1)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1629_ + _s825_) >>= fun w__228 : option ((mword 5 * mword 5)) => + (if + ((match w__228 with + | Some + (rd,rs2) => + andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg))) + (neq_int + (projT1 (regbits_to_regno + rs2)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s1629_ + _s825_) >>= fun w__229 : option ((mword 5 * mword 5)) => + (match w__229 with + | Some + (rd,rs2) => + returnm ((C_MV + ((rd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else if + ((generic_eq + _s825_ + "c.ebreak")) + then + returnm ((C_EBREAK + (tt)) + : ast ) + else + (_s1641_ + _s825_) >>= fun w__232 : option ((mword 5 * mword 5)) => + (if + ((match w__232 with + | Some + (rsd,rs2) => + andb + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + (neq_int + (projT1 (regbits_to_regno + rs2)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s1641_ + _s825_) >>= fun w__233 : option ((mword 5 * mword 5)) => + (match w__233 with + | Some + (rsd,rs2) => + returnm ((C_ADD + ((rsd, rs2))) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else if + ((generic_eq + _s825_ + "stop_fetching")) + then + returnm ((STOP_FETCHING + (tt)) + : ast ) + else if + ((generic_eq + _s825_ + "thread_start")) + then + returnm ((THREAD_START + (tt)) + : ast ) + else + (_s1653_ + _s825_) >>= fun w__236 : option (mword 32) => + (if + ((match w__236 with + | Some + (s) => + true + | _ => + false + end)) + then + (_s1653_ + _s825_) >>= fun w__237 : option (mword 32) => + (match w__237 with + | Some + (s) => + returnm ((ILLEGAL + (s)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast) + else + (_s1661_ + _s825_) >>= fun w__240 : option (mword 16) => + (match w__240 with + | Some + (s) => + returnm ((C_ILLEGAL + (s)) + : ast ) + | _ => + exit tt + : M (ast) + end) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast)) + : M (ast). + +Definition assembly_forwards_matches (arg_ : ast) +: bool := + + match arg_ with + | UTYPE (imm,rd,op) => true + | RISCV_JAL (imm,rd) => true + | RISCV_JALR (imm,rs1,rd) => true + | BTYPE (imm,rs2,rs1,op) => true + | ITYPE (imm,rs1,rd,op) => true + | SHIFTIOP (shamt,rs1,rd,op) => true + | RTYPE (rs2,rs1,rd,op) => true + | LOAD (imm,rs1,rd,is_unsigned,size,aq,rl) => true + | STORE (imm,rs1,rd,size,aq,rl) => true + | ADDIW (imm,rs1,rd) => true + | SHIFTW (shamt,rs1,rd,op) => true + | RTYPEW (rs2,rs1,rd,op) => true + | SHIFTIWOP (shamt,rs1,rd,op) => true + | MUL (rs2,rs1,rd,high,signed1,signed2) => true + | DIV (rs2,rs1,rd,s) => true + | REM (rs2,rs1,rd,s) => true + | MULW (rs2,rs1,rd) => true + | DIVW (rs2,rs1,rd,s) => true + | REMW (rs2,rs1,rd,s) => true + | FENCE (pred,succ) => true + | FENCE_TSO (pred,succ) => true + | FENCEI (tt) => true + | ECALL (tt) => true + | MRET (tt) => true + | SRET (tt) => true + | EBREAK (tt) => true + | WFI (tt) => true + | SFENCE_VMA (rs1,rs2) => true + | LOADRES (aq,rl,rs1,size,rd) => true + | STORECON (aq,rl,rs2,rs1,size,rd) => true + | AMO (op,aq,rl,rs2,rs1,width,rd) => true + | CSR (csr,rs1,rd,true,op) => true + | CSR (csr,rs1,rd,false,op) => true + | C_NOP (tt) => true + | C_ADDI4SPN (rdc,nzimm) => + if ((neq_vec nzimm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] : mword 8))) then true + else + let g__28 := C_ADDI4SPN ((rdc, nzimm)) in + false + | C_LW (uimm,rsc,rdc) => true + | C_LD (uimm,rsc,rdc) => true + | C_SW (uimm,rsc1,rsc2) => true + | C_SD (uimm,rsc1,rsc2) => true + | C_ADDI (nzi,rsd) => + if ((andb (neq_vec nzi (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__28 := C_ADDI ((nzi, rsd)) in + false + | C_JAL (imm) => true + | C_ADDIW (imm,rsd) => true + | C_LI (imm,rd) => + if ((neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__28 := C_LI ((imm, rd)) in + false + | C_ADDI16SP (imm) => + if ((neq_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then true + else + let g__28 := C_ADDI16SP (imm) in + false + | C_LUI (imm,rd) => + if ((andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno sp))) + (neq_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))))) then + true + else + let g__28 := C_LUI ((imm, rd)) in + false + | C_SRLI (shamt,rsd) => + if ((neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then true + else + let g__28 := C_SRLI ((shamt, rsd)) in + false + | C_SRAI (shamt,rsd) => + if ((neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6))) then true + else + let g__28 := C_SRAI ((shamt, rsd)) in + false + | C_ANDI (imm,rsd) => true + | C_SUB (rsd,rs2) => true + | C_XOR (rsd,rs2) => true + | C_OR (rsd,rs2) => true + | C_AND (rsd,rs2) => true + | C_SUBW (rsd,rs2) => true + | C_ADDW (rsd,rs2) => true + | C_J (imm) => true + | C_BEQZ (imm,rs) => true + | C_BNEZ (imm,rs) => true + | C_SLLI (shamt,rsd) => + if ((andb (neq_vec shamt (vec_of_bits [B0;B0;B0;B0;B0;B0] : mword 6)) + (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__28 := C_SLLI ((shamt, rsd)) in + false + | C_LWSP (uimm,rd) => + if ((neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__28 := C_LWSP ((uimm, rd)) in + false + | C_LDSP (uimm,rd) => + if ((neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__28 := C_LDSP ((uimm, rd)) in + false + | C_SWSP (uimm,rd) => true + | C_SDSP (uimm,rs2) => true + | C_JR (rs1) => + if ((neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__28 := C_JR (rs1) in + false + | C_JALR (rs1) => + if ((neq_int (projT1 (regbits_to_regno rs1)) (projT1 (regbits_to_regno zreg)))) then true + else + let g__28 := C_JALR (rs1) in + false + | C_MV (rd,rs2) => + if ((andb (neq_int (projT1 (regbits_to_regno rd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__28 := C_MV ((rd, rs2)) in + false + | C_EBREAK (tt) => true + | C_ADD (rsd,rs2) => + if ((andb (neq_int (projT1 (regbits_to_regno rsd)) (projT1 (regbits_to_regno zreg))) + (neq_int (projT1 (regbits_to_regno rs2)) (projT1 (regbits_to_regno zreg))))) then + true + else + let g__28 := C_ADD ((rsd, rs2)) in + false + | STOP_FETCHING (tt) => true + | THREAD_START (tt) => true + | ILLEGAL (s) => true + | C_ILLEGAL (s) => true + end. + +Definition _s2517_ (_s2518_ : string) +: M (option (mword 16)) := + + let _s2519_ := _s2518_ in + (if ((string_startswith _s2519_ "c.illegal")) then + (match (string_drop _s2519_ (projT1 (string_length "c.illegal"))) with + | _s2520_ => + (spc_matches_prefix _s2520_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s2521_ _)) => + match (string_drop _s2520_ _s2521_) with + | _s2522_ => + match (hex_bits_16_matches_prefix _s2522_) with + | Some (s,(existT _ _s2523_ _)) => + let p0_ := string_drop _s2522_ _s2523_ in + if ((generic_eq p0_ "")) then Some (s) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 16)) + end) + : M (option (mword 16)) + else returnm (None : option (mword 16))) + : M (option (mword 16)). + +Definition _s2509_ (_s2510_ : string) +: M (option (mword 32)) := + + let _s2511_ := _s2510_ in + (if ((string_startswith _s2511_ "illegal")) then + (match (string_drop _s2511_ (projT1 (string_length "illegal"))) with + | _s2512_ => + (spc_matches_prefix _s2512_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s2513_ _)) => + match (string_drop _s2512_ _s2513_) with + | _s2514_ => + match (hex_bits_32_matches_prefix _s2514_) with + | Some (s,(existT _ _s2515_ _)) => + let p0_ := string_drop _s2514_ _s2515_ in + if ((generic_eq p0_ "")) then Some (s) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 32)) + end) + : M (option (mword 32)) + else returnm (None : option (mword 32))) + : M (option (mword 32)). + +Definition _s2497_ (_s2498_ : string) +: M (option ((mword 5 * mword 5))) := + + let _s2499_ := _s2498_ in + (if ((string_startswith _s2499_ "c.add")) then + (match (string_drop _s2499_ (projT1 (string_length "c.add"))) with + | _s2500_ => + (spc_matches_prefix _s2500_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2501_ _)) => + (match (string_drop _s2500_ _s2501_) with + | _s2502_ => + (reg_name_matches_prefix _s2502_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2503_ _)) => + (match (string_drop _s2502_ _s2503_) with + | _s2504_ => + (sep_matches_prefix _s2504_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2505_ _)) => + (match (string_drop _s2504_ _s2505_) with + | _s2506_ => + (reg_name_matches_prefix _s2506_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2507_ _)) => + let p0_ := string_drop _s2506_ _s2507_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5))). + +Definition _s2485_ (_s2486_ : string) +: M (option ((mword 5 * mword 5))) := + + let _s2487_ := _s2486_ in + (if ((string_startswith _s2487_ "c.mv")) then + (match (string_drop _s2487_ (projT1 (string_length "c.mv"))) with + | _s2488_ => + (spc_matches_prefix _s2488_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2489_ _)) => + (match (string_drop _s2488_ _s2489_) with + | _s2490_ => + (reg_name_matches_prefix _s2490_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2491_ _)) => + (match (string_drop _s2490_ _s2491_) with + | _s2492_ => + (sep_matches_prefix _s2492_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2493_ _)) => + (match (string_drop _s2492_ _s2493_) with + | _s2494_ => + (reg_name_matches_prefix _s2494_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2495_ _)) => + let p0_ := string_drop _s2494_ _s2495_ in + if ((generic_eq p0_ "")) then Some ((rd, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5))). + +Definition _s2477_ (_s2478_ : string) +: M (option (mword 5)) := + + let _s2479_ := _s2478_ in + (if ((string_startswith _s2479_ "c.jalr")) then + (match (string_drop _s2479_ (projT1 (string_length "c.jalr"))) with + | _s2480_ => + (spc_matches_prefix _s2480_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2481_ _)) => + (match (string_drop _s2480_ _s2481_) with + | _s2482_ => + (reg_name_matches_prefix _s2482_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (rs1,(existT _ _s2483_ _)) => + let p0_ := string_drop _s2482_ _s2483_ in + if ((generic_eq p0_ "")) then Some (rs1) + else None + | _ => None + end) + : option (mword 5)) + end) + : M (option (mword 5)) + | _ => returnm (None : option (mword 5)) + end) + : M (option (mword 5)) + end) + : M (option (mword 5)) + else returnm (None : option (mword 5))) + : M (option (mword 5)). + +Definition _s2469_ (_s2470_ : string) +: M (option (mword 5)) := + + let _s2471_ := _s2470_ in + (if ((string_startswith _s2471_ "c.jr")) then + (match (string_drop _s2471_ (projT1 (string_length "c.jr"))) with + | _s2472_ => + (spc_matches_prefix _s2472_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2473_ _)) => + (match (string_drop _s2472_ _s2473_) with + | _s2474_ => + (reg_name_matches_prefix _s2474_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (rs1,(existT _ _s2475_ _)) => + let p0_ := string_drop _s2474_ _s2475_ in + if ((generic_eq p0_ "")) then Some (rs1) + else None + | _ => None + end) + : option (mword 5)) + end) + : M (option (mword 5)) + | _ => returnm (None : option (mword 5)) + end) + : M (option (mword 5)) + end) + : M (option (mword 5)) + else returnm (None : option (mword 5))) + : M (option (mword 5)). + +Definition _s2457_ (_s2458_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2459_ := _s2458_ in + (if ((string_startswith _s2459_ "c.sdsp")) then + (match (string_drop _s2459_ (projT1 (string_length "c.sdsp"))) with + | _s2460_ => + (spc_matches_prefix _s2460_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2461_ _)) => + (match (string_drop _s2460_ _s2461_) with + | _s2462_ => + (reg_name_matches_prefix _s2462_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs2,(existT _ _s2463_ _)) => + (match (string_drop _s2462_ _s2463_) with + | _s2464_ => + (sep_matches_prefix _s2464_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2465_ _)) => + match (string_drop _s2464_ _s2465_) with + | _s2466_ => + match (hex_bits_6_matches_prefix _s2466_) with + | Some (uimm,(existT _ _s2467_ _)) => + let p0_ := string_drop _s2466_ _s2467_ in + if ((generic_eq p0_ "")) then Some ((rs2, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2445_ (_s2446_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2447_ := _s2446_ in + (if ((string_startswith _s2447_ "c.swsp")) then + (match (string_drop _s2447_ (projT1 (string_length "c.swsp"))) with + | _s2448_ => + (spc_matches_prefix _s2448_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2449_ _)) => + (match (string_drop _s2448_ _s2449_) with + | _s2450_ => + (reg_name_matches_prefix _s2450_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2451_ _)) => + (match (string_drop _s2450_ _s2451_) with + | _s2452_ => + (sep_matches_prefix _s2452_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2453_ _)) => + match (string_drop _s2452_ _s2453_) with + | _s2454_ => + match (hex_bits_6_matches_prefix _s2454_) with + | Some (uimm,(existT _ _s2455_ _)) => + let p0_ := string_drop _s2454_ _s2455_ in + if ((generic_eq p0_ "")) then Some ((rd, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2433_ (_s2434_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2435_ := _s2434_ in + (if ((string_startswith _s2435_ "c.ldsp")) then + (match (string_drop _s2435_ (projT1 (string_length "c.ldsp"))) with + | _s2436_ => + (spc_matches_prefix _s2436_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2437_ _)) => + (match (string_drop _s2436_ _s2437_) with + | _s2438_ => + (reg_name_matches_prefix _s2438_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2439_ _)) => + (match (string_drop _s2438_ _s2439_) with + | _s2440_ => + (sep_matches_prefix _s2440_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2441_ _)) => + match (string_drop _s2440_ _s2441_) with + | _s2442_ => + match (hex_bits_6_matches_prefix _s2442_) with + | Some (uimm,(existT _ _s2443_ _)) => + let p0_ := string_drop _s2442_ _s2443_ in + if ((generic_eq p0_ "")) then Some ((rd, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2421_ (_s2422_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2423_ := _s2422_ in + (if ((string_startswith _s2423_ "c.lwsp")) then + (match (string_drop _s2423_ (projT1 (string_length "c.lwsp"))) with + | _s2424_ => + (spc_matches_prefix _s2424_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2425_ _)) => + (match (string_drop _s2424_ _s2425_) with + | _s2426_ => + (reg_name_matches_prefix _s2426_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2427_ _)) => + (match (string_drop _s2426_ _s2427_) with + | _s2428_ => + (sep_matches_prefix _s2428_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2429_ _)) => + match (string_drop _s2428_ _s2429_) with + | _s2430_ => + match (hex_bits_6_matches_prefix _s2430_) with + | Some (uimm,(existT _ _s2431_ _)) => + let p0_ := string_drop _s2430_ _s2431_ in + if ((generic_eq p0_ "")) then Some ((rd, uimm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2409_ (_s2410_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2411_ := _s2410_ in + (if ((string_startswith _s2411_ "c.slli")) then + (match (string_drop _s2411_ (projT1 (string_length "c.slli"))) with + | _s2412_ => + (spc_matches_prefix _s2412_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2413_ _)) => + (match (string_drop _s2412_ _s2413_) with + | _s2414_ => + (reg_name_matches_prefix _s2414_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2415_ _)) => + (match (string_drop _s2414_ _s2415_) with + | _s2416_ => + (sep_matches_prefix _s2416_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2417_ _)) => + match (string_drop _s2416_ _s2417_) with + | _s2418_ => + match (hex_bits_6_matches_prefix _s2418_) with + | Some (shamt,(existT _ _s2419_ _)) => + let p0_ := string_drop _s2418_ _s2419_ in + if ((generic_eq p0_ "")) then Some ((rsd, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2397_ (_s2398_ : string) +: M (option ((mword 3 * mword 8))) := + + let _s2399_ := _s2398_ in + (if ((string_startswith _s2399_ "c.bnez")) then + (match (string_drop _s2399_ (projT1 (string_length "c.bnez"))) with + | _s2400_ => + (spc_matches_prefix _s2400_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2401_ _)) => + (match (string_drop _s2400_ _s2401_) with + | _s2402_ => + (creg_name_matches_prefix _s2402_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs,(existT _ _s2403_ _)) => + (match (string_drop _s2402_ _s2403_) with + | _s2404_ => + (sep_matches_prefix _s2404_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2405_ _)) => + match (string_drop _s2404_ _s2405_) with + | _s2406_ => + match (hex_bits_8_matches_prefix _s2406_) with + | Some (imm,(existT _ _s2407_ _)) => + let p0_ := string_drop _s2406_ _s2407_ in + if ((generic_eq p0_ "")) then Some ((rs, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + else returnm (None : option ((mword 3 * mword 8)))) + : M (option ((mword 3 * mword 8))). + +Definition _s2385_ (_s2386_ : string) +: M (option ((mword 3 * mword 8))) := + + let _s2387_ := _s2386_ in + (if ((string_startswith _s2387_ "c.beqz")) then + (match (string_drop _s2387_ (projT1 (string_length "c.beqz"))) with + | _s2388_ => + (spc_matches_prefix _s2388_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2389_ _)) => + (match (string_drop _s2388_ _s2389_) with + | _s2390_ => + (creg_name_matches_prefix _s2390_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs,(existT _ _s2391_ _)) => + (match (string_drop _s2390_ _s2391_) with + | _s2392_ => + (sep_matches_prefix _s2392_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2393_ _)) => + match (string_drop _s2392_ _s2393_) with + | _s2394_ => + match (hex_bits_8_matches_prefix _s2394_) with + | Some (imm,(existT _ _s2395_ _)) => + let p0_ := string_drop _s2394_ _s2395_ in + if ((generic_eq p0_ "")) then Some ((rs, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + else returnm (None : option ((mword 3 * mword 8)))) + : M (option ((mword 3 * mword 8))). + +Definition _s2377_ (_s2378_ : string) +: M (option (mword 11)) := + + let _s2379_ := _s2378_ in + (if ((string_startswith _s2379_ "c.j")) then + (match (string_drop _s2379_ (projT1 (string_length "c.j"))) with + | _s2380_ => + (spc_matches_prefix _s2380_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s2381_ _)) => + match (string_drop _s2380_ _s2381_) with + | _s2382_ => + match (hex_bits_11_matches_prefix _s2382_) with + | Some (imm,(existT _ _s2383_ _)) => + let p0_ := string_drop _s2382_ _s2383_ in + if ((generic_eq p0_ "")) then Some (imm) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 11)) + end) + : M (option (mword 11)) + else returnm (None : option (mword 11))) + : M (option (mword 11)). + +Definition _s2365_ (_s2366_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s2367_ := _s2366_ in + (if ((string_startswith _s2367_ "c.addw")) then + (match (string_drop _s2367_ (projT1 (string_length "c.addw"))) with + | _s2368_ => + (spc_matches_prefix _s2368_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2369_ _)) => + (match (string_drop _s2368_ _s2369_) with + | _s2370_ => + (creg_name_matches_prefix _s2370_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2371_ _)) => + (match (string_drop _s2370_ _s2371_) with + | _s2372_ => + (sep_matches_prefix _s2372_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2373_ _)) => + (match (string_drop _s2372_ _s2373_) with + | _s2374_ => + (creg_name_matches_prefix _s2374_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2375_ _)) => + let p0_ := string_drop _s2374_ _s2375_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s2353_ (_s2354_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s2355_ := _s2354_ in + (if ((string_startswith _s2355_ "c.subw")) then + (match (string_drop _s2355_ (projT1 (string_length "c.subw"))) with + | _s2356_ => + (spc_matches_prefix _s2356_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2357_ _)) => + (match (string_drop _s2356_ _s2357_) with + | _s2358_ => + (creg_name_matches_prefix _s2358_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2359_ _)) => + (match (string_drop _s2358_ _s2359_) with + | _s2360_ => + (sep_matches_prefix _s2360_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2361_ _)) => + (match (string_drop _s2360_ _s2361_) with + | _s2362_ => + (creg_name_matches_prefix _s2362_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2363_ _)) => + let p0_ := string_drop _s2362_ _s2363_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s2341_ (_s2342_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s2343_ := _s2342_ in + (if ((string_startswith _s2343_ "c.and")) then + (match (string_drop _s2343_ (projT1 (string_length "c.and"))) with + | _s2344_ => + (spc_matches_prefix _s2344_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2345_ _)) => + (match (string_drop _s2344_ _s2345_) with + | _s2346_ => + (creg_name_matches_prefix _s2346_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2347_ _)) => + (match (string_drop _s2346_ _s2347_) with + | _s2348_ => + (sep_matches_prefix _s2348_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2349_ _)) => + (match (string_drop _s2348_ _s2349_) with + | _s2350_ => + (creg_name_matches_prefix _s2350_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2351_ _)) => + let p0_ := string_drop _s2350_ _s2351_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s2329_ (_s2330_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s2331_ := _s2330_ in + (if ((string_startswith _s2331_ "c.or")) then + (match (string_drop _s2331_ (projT1 (string_length "c.or"))) with + | _s2332_ => + (spc_matches_prefix _s2332_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2333_ _)) => + (match (string_drop _s2332_ _s2333_) with + | _s2334_ => + (creg_name_matches_prefix _s2334_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2335_ _)) => + (match (string_drop _s2334_ _s2335_) with + | _s2336_ => + (sep_matches_prefix _s2336_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2337_ _)) => + (match (string_drop _s2336_ _s2337_) with + | _s2338_ => + (creg_name_matches_prefix _s2338_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2339_ _)) => + let p0_ := string_drop _s2338_ _s2339_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s2317_ (_s2318_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s2319_ := _s2318_ in + (if ((string_startswith _s2319_ "c.xor")) then + (match (string_drop _s2319_ (projT1 (string_length "c.xor"))) with + | _s2320_ => + (spc_matches_prefix _s2320_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2321_ _)) => + (match (string_drop _s2320_ _s2321_) with + | _s2322_ => + (creg_name_matches_prefix _s2322_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2323_ _)) => + (match (string_drop _s2322_ _s2323_) with + | _s2324_ => + (sep_matches_prefix _s2324_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2325_ _)) => + (match (string_drop _s2324_ _s2325_) with + | _s2326_ => + (creg_name_matches_prefix _s2326_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2327_ _)) => + let p0_ := string_drop _s2326_ _s2327_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s2305_ (_s2306_ : string) +: M (option ((mword 3 * mword 3))) := + + let _s2307_ := _s2306_ in + (if ((string_startswith _s2307_ "c.sub")) then + (match (string_drop _s2307_ (projT1 (string_length "c.sub"))) with + | _s2308_ => + (spc_matches_prefix _s2308_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2309_ _)) => + (match (string_drop _s2308_ _s2309_) with + | _s2310_ => + (creg_name_matches_prefix _s2310_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2311_ _)) => + (match (string_drop _s2310_ _s2311_) with + | _s2312_ => + (sep_matches_prefix _s2312_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2313_ _)) => + (match (string_drop _s2312_ _s2313_) with + | _s2314_ => + (creg_name_matches_prefix _s2314_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2315_ _)) => + let p0_ := string_drop _s2314_ _s2315_ in + if ((generic_eq p0_ "")) then Some ((rsd, rs2)) + else None + | _ => None + end) + : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + | _ => returnm (None : option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + end) + : M (option ((mword 3 * mword 3))) + else returnm (None : option ((mword 3 * mword 3)))) + : M (option ((mword 3 * mword 3))). + +Definition _s2293_ (_s2294_ : string) +: M (option ((mword 3 * mword 6))) := + + let _s2295_ := _s2294_ in + (if ((string_startswith _s2295_ "c.andi")) then + (match (string_drop _s2295_ (projT1 (string_length "c.andi"))) with + | _s2296_ => + (spc_matches_prefix _s2296_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2297_ _)) => + (match (string_drop _s2296_ _s2297_) with + | _s2298_ => + (creg_name_matches_prefix _s2298_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2299_ _)) => + (match (string_drop _s2298_ _s2299_) with + | _s2300_ => + (sep_matches_prefix _s2300_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2301_ _)) => + match (string_drop _s2300_ _s2301_) with + | _s2302_ => + match (hex_bits_6_matches_prefix _s2302_) with + | Some (imm,(existT _ _s2303_ _)) => + let p0_ := string_drop _s2302_ _s2303_ in + if ((generic_eq p0_ "")) then Some ((rsd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + else returnm (None : option ((mword 3 * mword 6)))) + : M (option ((mword 3 * mword 6))). + +Definition _s2281_ (_s2282_ : string) +: M (option ((mword 3 * mword 6))) := + + let _s2283_ := _s2282_ in + (if ((string_startswith _s2283_ "c.srai")) then + (match (string_drop _s2283_ (projT1 (string_length "c.srai"))) with + | _s2284_ => + (spc_matches_prefix _s2284_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2285_ _)) => + (match (string_drop _s2284_ _s2285_) with + | _s2286_ => + (creg_name_matches_prefix _s2286_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2287_ _)) => + (match (string_drop _s2286_ _s2287_) with + | _s2288_ => + (sep_matches_prefix _s2288_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2289_ _)) => + match (string_drop _s2288_ _s2289_) with + | _s2290_ => + match (hex_bits_6_matches_prefix _s2290_) with + | Some (shamt,(existT _ _s2291_ _)) => + let p0_ := string_drop _s2290_ _s2291_ in + if ((generic_eq p0_ "")) then Some ((rsd, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + else returnm (None : option ((mword 3 * mword 6)))) + : M (option ((mword 3 * mword 6))). + +Definition _s2269_ (_s2270_ : string) +: M (option ((mword 3 * mword 6))) := + + let _s2271_ := _s2270_ in + (if ((string_startswith _s2271_ "c.srli")) then + (match (string_drop _s2271_ (projT1 (string_length "c.srli"))) with + | _s2272_ => + (spc_matches_prefix _s2272_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2273_ _)) => + (match (string_drop _s2272_ _s2273_) with + | _s2274_ => + (creg_name_matches_prefix _s2274_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2275_ _)) => + (match (string_drop _s2274_ _s2275_) with + | _s2276_ => + (sep_matches_prefix _s2276_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2277_ _)) => + match (string_drop _s2276_ _s2277_) with + | _s2278_ => + match (hex_bits_6_matches_prefix _s2278_) with + | Some (shamt,(existT _ _s2279_ _)) => + let p0_ := string_drop _s2278_ _s2279_ in + if ((generic_eq p0_ "")) then Some ((rsd, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + | _ => returnm (None : option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + end) + : M (option ((mword 3 * mword 6))) + else returnm (None : option ((mword 3 * mword 6)))) + : M (option ((mword 3 * mword 6))). + +Definition _s2257_ (_s2258_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2259_ := _s2258_ in + (if ((string_startswith _s2259_ "c.lui")) then + (match (string_drop _s2259_ (projT1 (string_length "c.lui"))) with + | _s2260_ => + (spc_matches_prefix _s2260_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2261_ _)) => + (match (string_drop _s2260_ _s2261_) with + | _s2262_ => + (reg_name_matches_prefix _s2262_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2263_ _)) => + (match (string_drop _s2262_ _s2263_) with + | _s2264_ => + (sep_matches_prefix _s2264_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2265_ _)) => + match (string_drop _s2264_ _s2265_) with + | _s2266_ => + match (hex_bits_6_matches_prefix _s2266_) with + | Some (imm,(existT _ _s2267_ _)) => + let p0_ := string_drop _s2266_ _s2267_ in + if ((generic_eq p0_ "")) then Some ((rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2249_ (_s2250_ : string) +: M (option (mword 6)) := + + let _s2251_ := _s2250_ in + (if ((string_startswith _s2251_ "c.addi16sp")) then + (match (string_drop _s2251_ (projT1 (string_length "c.addi16sp"))) with + | _s2252_ => + (spc_matches_prefix _s2252_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s2253_ _)) => + match (string_drop _s2252_ _s2253_) with + | _s2254_ => + match (hex_bits_6_matches_prefix _s2254_) with + | Some (imm,(existT _ _s2255_ _)) => + let p0_ := string_drop _s2254_ _s2255_ in + if ((generic_eq p0_ "")) then Some (imm) + else None + | _ => None + end + end + | _ => None + end) + : option (mword 6)) + end) + : M (option (mword 6)) + else returnm (None : option (mword 6))) + : M (option (mword 6)). + +Definition _s2237_ (_s2238_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2239_ := _s2238_ in + (if ((string_startswith _s2239_ "c.li")) then + (match (string_drop _s2239_ (projT1 (string_length "c.li"))) with + | _s2240_ => + (spc_matches_prefix _s2240_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2241_ _)) => + (match (string_drop _s2240_ _s2241_) with + | _s2242_ => + (reg_name_matches_prefix _s2242_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2243_ _)) => + (match (string_drop _s2242_ _s2243_) with + | _s2244_ => + (sep_matches_prefix _s2244_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2245_ _)) => + match (string_drop _s2244_ _s2245_) with + | _s2246_ => + match (hex_bits_6_matches_prefix _s2246_) with + | Some (imm,(existT _ _s2247_ _)) => + let p0_ := string_drop _s2246_ _s2247_ in + if ((generic_eq p0_ "")) then Some ((rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2225_ (_s2226_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2227_ := _s2226_ in + (if ((string_startswith _s2227_ "c.addiw")) then + (match (string_drop _s2227_ (projT1 (string_length "c.addiw"))) with + | _s2228_ => + (spc_matches_prefix _s2228_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2229_ _)) => + (match (string_drop _s2228_ _s2229_) with + | _s2230_ => + (reg_name_matches_prefix _s2230_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2231_ _)) => + (match (string_drop _s2230_ _s2231_) with + | _s2232_ => + (sep_matches_prefix _s2232_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2233_ _)) => + match (string_drop _s2232_ _s2233_) with + | _s2234_ => + match (hex_bits_6_matches_prefix _s2234_) with + | Some (imm,(existT _ _s2235_ _)) => + let p0_ := string_drop _s2234_ _s2235_ in + if ((generic_eq p0_ "")) then Some ((rsd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2217_ (_s2218_ : string) +: M (option (mword 11)) := + + let _s2219_ := _s2218_ in + (if ((string_startswith _s2219_ "c.jal")) then + (match (string_drop _s2219_ (projT1 (string_length "c.jal"))) with + | _s2220_ => + (spc_matches_prefix _s2220_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s2221_ _)) => + match (string_drop _s2220_ _s2221_) with + | _s2222_ => + match (hex_bits_12_matches_prefix _s2222_) with + | Some (v__772,(existT _ _s2223_ _)) => + if ((eq_vec (subrange_vec_dec v__772 0 0) + (vec_of_bits [B0] : mword (0 - 0 + 1)))) then + let imm : mword 11 := subrange_vec_dec v__772 11 1 in + let imm : mword 11 := subrange_vec_dec v__772 11 1 in + let p0_ := string_drop _s2222_ _s2223_ in + if ((generic_eq p0_ "")) then Some (imm) + else None + else + let g__27 := Some ((v__772, _s2223_)) in + None + | g__27 => None + end + end + | _ => None + end) + : option (mword 11)) + end) + : M (option (mword 11)) + else returnm (None : option (mword 11))) + : M (option (mword 11)). + +Definition _s2205_ (_s2206_ : string) +: M (option ((mword 5 * mword 6))) := + + let _s2207_ := _s2206_ in + (if ((string_startswith _s2207_ "c.addi")) then + (match (string_drop _s2207_ (projT1 (string_length "c.addi"))) with + | _s2208_ => + (spc_matches_prefix _s2208_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2209_ _)) => + (match (string_drop _s2208_ _s2209_) with + | _s2210_ => + (reg_name_matches_prefix _s2210_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s2211_ _)) => + (match (string_drop _s2210_ _s2211_) with + | _s2212_ => + (sep_matches_prefix _s2212_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2213_ _)) => + match (string_drop _s2212_ _s2213_) with + | _s2214_ => + match (hex_bits_6_matches_prefix _s2214_) with + | Some (nzi,(existT _ _s2215_ _)) => + let p0_ := string_drop _s2214_ _s2215_ in + if ((generic_eq p0_ "")) then Some ((rsd, nzi)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + | _ => returnm (None : option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + end) + : M (option ((mword 5 * mword 6))) + else returnm (None : option ((mword 5 * mword 6)))) + : M (option ((mword 5 * mword 6))). + +Definition _s2189_ (_s2190_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s2191_ := _s2190_ in + (if ((string_startswith _s2191_ "c.sd")) then + (match (string_drop _s2191_ (projT1 (string_length "c.sd"))) with + | _s2192_ => + (spc_matches_prefix _s2192_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2193_ _)) => + (match (string_drop _s2192_ _s2193_) with + | _s2194_ => + (creg_name_matches_prefix _s2194_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsc1,(existT _ _s2195_ _)) => + (match (string_drop _s2194_ _s2195_) with + | _s2196_ => + (sep_matches_prefix _s2196_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2197_ _)) => + (match (string_drop _s2196_ _s2197_) with + | _s2198_ => + (creg_name_matches_prefix _s2198_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc2,(existT _ _s2199_ _)) => + (match (string_drop _s2198_ _s2199_) with + | _s2200_ => + (sep_matches_prefix _s2200_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s2201_ _)) => + match (string_drop _s2200_ _s2201_) with + | _s2202_ => + match (hex_bits_8_matches_prefix _s2202_) with + | Some (v__774,(existT _ _s2203_ _)) => + if ((eq_vec + (subrange_vec_dec v__774 2 0) + (vec_of_bits [B0;B0;B0] + : mword (2 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__774 7 3 in + let uimm : mword 5 := + subrange_vec_dec v__774 7 3 in + let p0_ := + string_drop _s2202_ _s2203_ in + if ((generic_eq p0_ "")) then + Some + ((rsc1, rsc2, uimm)) + else None + else + let g__26 := Some ((v__774, _s2203_)) in + None + | g__26 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s2173_ (_s2174_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s2175_ := _s2174_ in + (if ((string_startswith _s2175_ "c.sw")) then + (match (string_drop _s2175_ (projT1 (string_length "c.sw"))) with + | _s2176_ => + (spc_matches_prefix _s2176_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2177_ _)) => + (match (string_drop _s2176_ _s2177_) with + | _s2178_ => + (creg_name_matches_prefix _s2178_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsc1,(existT _ _s2179_ _)) => + (match (string_drop _s2178_ _s2179_) with + | _s2180_ => + (sep_matches_prefix _s2180_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2181_ _)) => + (match (string_drop _s2180_ _s2181_) with + | _s2182_ => + (creg_name_matches_prefix _s2182_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc2,(existT _ _s2183_ _)) => + (match (string_drop _s2182_ _s2183_) with + | _s2184_ => + (sep_matches_prefix _s2184_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s2185_ _)) => + match (string_drop _s2184_ _s2185_) with + | _s2186_ => + match (hex_bits_7_matches_prefix _s2186_) with + | Some (v__776,(existT _ _s2187_ _)) => + if ((eq_vec + (subrange_vec_dec v__776 1 0) + (vec_of_bits [B0;B0] + : mword (1 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__776 6 2 in + let uimm : mword 5 := + subrange_vec_dec v__776 6 2 in + let p0_ := + string_drop _s2186_ _s2187_ in + if ((generic_eq p0_ "")) then + Some + ((rsc1, rsc2, uimm)) + else None + else + let g__25 := Some ((v__776, _s2187_)) in + None + | g__25 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s2157_ (_s2158_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s2159_ := _s2158_ in + (if ((string_startswith _s2159_ "c.ld")) then + (match (string_drop _s2159_ (projT1 (string_length "c.ld"))) with + | _s2160_ => + (spc_matches_prefix _s2160_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2161_ _)) => + (match (string_drop _s2160_ _s2161_) with + | _s2162_ => + (creg_name_matches_prefix _s2162_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s2163_ _)) => + (match (string_drop _s2162_ _s2163_) with + | _s2164_ => + (sep_matches_prefix _s2164_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2165_ _)) => + (match (string_drop _s2164_ _s2165_) with + | _s2166_ => + (creg_name_matches_prefix _s2166_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc,(existT _ _s2167_ _)) => + (match (string_drop _s2166_ _s2167_) with + | _s2168_ => + (sep_matches_prefix _s2168_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s2169_ _)) => + match (string_drop _s2168_ _s2169_) with + | _s2170_ => + match (hex_bits_8_matches_prefix _s2170_) with + | Some (v__778,(existT _ _s2171_ _)) => + if ((eq_vec + (subrange_vec_dec v__778 2 0) + (vec_of_bits [B0;B0;B0] + : mword (2 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__778 7 3 in + let uimm : mword 5 := + subrange_vec_dec v__778 7 3 in + let p0_ := + string_drop _s2170_ _s2171_ in + if ((generic_eq p0_ "")) then + Some + ((rdc, rsc, uimm)) + else None + else + let g__24 := Some ((v__778, _s2171_)) in + None + | g__24 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s2141_ (_s2142_ : string) +: M (option ((mword 3 * mword 3 * mword 5))) := + + let _s2143_ := _s2142_ in + (if ((string_startswith _s2143_ "c.lw")) then + (match (string_drop _s2143_ (projT1 (string_length "c.lw"))) with + | _s2144_ => + (spc_matches_prefix _s2144_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2145_ _)) => + (match (string_drop _s2144_ _s2145_) with + | _s2146_ => + (creg_name_matches_prefix _s2146_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s2147_ _)) => + (match (string_drop _s2146_ _s2147_) with + | _s2148_ => + (sep_matches_prefix _s2148_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2149_ _)) => + (match (string_drop _s2148_ _s2149_) with + | _s2150_ => + (creg_name_matches_prefix _s2150_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc,(existT _ _s2151_ _)) => + (match (string_drop _s2150_ _s2151_) with + | _s2152_ => + (sep_matches_prefix _s2152_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s2153_ _)) => + match (string_drop _s2152_ _s2153_) with + | _s2154_ => + match (hex_bits_7_matches_prefix _s2154_) with + | Some (v__780,(existT _ _s2155_ _)) => + if ((eq_vec + (subrange_vec_dec v__780 1 0) + (vec_of_bits [B0;B0] + : mword (1 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__780 6 2 in + let uimm : mword 5 := + subrange_vec_dec v__780 6 2 in + let p0_ := + string_drop _s2154_ _s2155_ in + if ((generic_eq p0_ "")) then + Some + ((rdc, rsc, uimm)) + else None + else + let g__23 := Some ((v__780, _s2155_)) in + None + | g__23 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + end) + : M (option ((mword 3 * mword 3 * mword 5))) + else returnm (None : option ((mword 3 * mword 3 * mword 5)))) + : M (option ((mword 3 * mword 3 * mword 5))). + +Definition _s2129_ (_s2130_ : string) +: M (option ((mword 3 * mword 8))) := + + let _s2131_ := _s2130_ in + (if ((string_startswith _s2131_ "c.addi4spn")) then + (match (string_drop _s2131_ (projT1 (string_length "c.addi4spn"))) with + | _s2132_ => + (spc_matches_prefix _s2132_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2133_ _)) => + (match (string_drop _s2132_ _s2133_) with + | _s2134_ => + (creg_name_matches_prefix _s2134_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s2135_ _)) => + (match (string_drop _s2134_ _s2135_) with + | _s2136_ => + (sep_matches_prefix _s2136_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2137_ _)) => + match (string_drop _s2136_ _s2137_) with + | _s2138_ => + match (hex_bits_10_matches_prefix _s2138_) with + | Some (v__782,(existT _ _s2139_ _)) => + if ((eq_vec (subrange_vec_dec v__782 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) + then + let nzimm : mword 8 := subrange_vec_dec v__782 9 2 in + let nzimm : mword 8 := subrange_vec_dec v__782 9 2 in + let p0_ := string_drop _s2138_ _s2139_ in + if ((generic_eq p0_ "")) then Some ((rdc, nzimm)) + else None + else + let g__22 := Some ((v__782, _s2139_)) in + None + | g__22 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + | _ => returnm (None : option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + end) + : M (option ((mword 3 * mword 8))) + else returnm (None : option ((mword 3 * mword 8)))) + : M (option ((mword 3 * mword 8))). + +Definition _s2112_ (_s2113_ : string) +: M (option ((csrop * mword 5 * mword 5 * mword 12))) := + + (match _s2113_ with + | _s2114_ => + (csr_mnemonic_matches_prefix _s2114_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2115_ _)) => + (match (string_drop _s2114_ _s2115_) with + | _s2116_ => + (spc_matches_prefix _s2116_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2117_ _)) => + (match (string_drop _s2116_ _s2117_) with + | _s2118_ => + (reg_name_matches_prefix _s2118_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2119_ _)) => + (match (string_drop _s2118_ _s2119_) with + | _s2120_ => + (sep_matches_prefix _s2120_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2121_ _)) => + (match (string_drop _s2120_ _s2121_) with + | _s2122_ => + (reg_name_matches_prefix _s2122_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2123_ _)) => + (match (string_drop _s2122_ _s2123_) with + | _s2124_ => + (sep_matches_prefix _s2124_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2125_ _)) => + (match (string_drop _s2124_ _s2125_) with + | _s2126_ => + (csr_name_map_matches_prefix _s2126_) >>= fun w__6 : option ((mword 12 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (csr,(existT _ _s2127_ _)) => + let p0_ := + string_drop _s2126_ _s2127_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, csr)) + else None + | _ => None + end) + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))). + +Definition _s2094_ (_s2095_ : string) +: M (option ((csrop * mword 5 * mword 5 * mword 12))) := + + (match _s2095_ with + | _s2096_ => + (csr_mnemonic_matches_prefix _s2096_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2097_ _)) => + let _s2098_ := string_drop _s2096_ _s2097_ in + (if ((string_startswith _s2098_ "i")) then + (match (string_drop _s2098_ (projT1 (string_length "i"))) with + | _s2099_ => + (spc_matches_prefix _s2099_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2100_ _)) => + (match (string_drop _s2099_ _s2100_) with + | _s2101_ => + (reg_name_matches_prefix _s2101_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2102_ _)) => + (match (string_drop _s2101_ _s2102_) with + | _s2103_ => + (sep_matches_prefix _s2103_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2104_ _)) => + (match (string_drop _s2103_ _s2104_) with + | _s2105_ => + (match (hex_bits_5_matches_prefix _s2105_) with + | Some (rs1,(existT _ _s2106_ _)) => + (match (string_drop _s2105_ _s2106_) with + | _s2107_ => + (sep_matches_prefix _s2107_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s2108_ _)) => + (match (string_drop _s2107_ _s2108_) with + | _s2109_ => + (csr_name_map_matches_prefix _s2109_) >>= fun w__5 : option ((mword 12 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some + (csr,(existT _ _s2110_ _)) => + let p0_ := + string_drop _s2109_ _s2110_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, csr)) + else None + | _ => None + end) + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + else returnm (None : option ((csrop * mword 5 * mword 5 * mword 12)))) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12))). + +Definition _s2070_ (_s2071_ : string) +: M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) := + + (match _s2071_ with + | _s2072_ => + (amo_mnemonic_matches_prefix _s2072_) >>= fun w__0 : option ((amoop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2073_ _)) => + let _s2074_ := string_drop _s2072_ _s2073_ in + (if ((string_startswith _s2074_ ".")) then + (match (string_drop _s2074_ (projT1 (string_length "."))) with + | _s2075_ => + (size_mnemonic_matches_prefix _s2075_) >>= fun w__1 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (width,(existT _ _s2076_ _)) => + (match (string_drop _s2075_ _s2076_) with + | _s2077_ => + (maybe_aq_matches_prefix _s2077_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (aq,(existT _ _s2078_ _)) => + (match (string_drop _s2077_ _s2078_) with + | _s2079_ => + (maybe_rl_matches_prefix _s2079_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rl,(existT _ _s2080_ _)) => + (match (string_drop _s2079_ _s2080_) with + | _s2081_ => + (spc_matches_prefix _s2081_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s2082_ _)) => + (match (string_drop _s2081_ _s2082_) with + | _s2083_ => + (reg_name_matches_prefix _s2083_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (rd,(existT _ _s2084_ _)) => + (match (string_drop _s2083_ _s2084_) with + | _s2085_ => + (sep_matches_prefix _s2085_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (tt,(existT _ _s2086_ _)) => + (match (string_drop _s2085_ _s2086_) with + | _s2087_ => + (reg_name_matches_prefix _s2087_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (rs1,(existT _ _s2088_ _)) => + (match (string_drop _s2087_ + _s2088_) with + | _s2089_ => + (sep_matches_prefix + _s2089_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__8 with + | Some + (tt,(existT _ _s2090_ _)) => + (match (string_drop + _s2089_ + _s2090_) with + | _s2091_ => + (reg_name_matches_prefix + _s2091_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__9 with + | Some + (rs2,(existT _ _s2092_ _)) => + let p0_ := + string_drop + _s2091_ + _s2092_ in + if ((generic_eq + p0_ + "")) + then + Some + ((op, width, aq, rl, rd, rs1, rs2)) + else + None + | _ => + None + end) + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + else + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)))) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5))). + +Definition _s2048_ (_s2049_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) := + + let _s2050_ := _s2049_ in + (if ((string_startswith _s2050_ "sc.")) then + (match (string_drop _s2050_ (projT1 (string_length "sc."))) with + | _s2051_ => + (size_mnemonic_matches_prefix _s2051_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s2052_ _)) => + (match (string_drop _s2051_ _s2052_) with + | _s2053_ => + (maybe_aq_matches_prefix _s2053_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s2054_ _)) => + (match (string_drop _s2053_ _s2054_) with + | _s2055_ => + (maybe_rl_matches_prefix _s2055_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s2056_ _)) => + (match (string_drop _s2055_ _s2056_) with + | _s2057_ => + (spc_matches_prefix _s2057_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2058_ _)) => + (match (string_drop _s2057_ _s2058_) with + | _s2059_ => + (reg_name_matches_prefix _s2059_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s2060_ _)) => + (match (string_drop _s2059_ _s2060_) with + | _s2061_ => + (sep_matches_prefix _s2061_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2062_ _)) => + (match (string_drop _s2061_ _s2062_) with + | _s2063_ => + (reg_name_matches_prefix _s2063_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (rs1,(existT _ _s2064_ _)) => + (match (string_drop _s2063_ _s2064_) with + | _s2065_ => + (sep_matches_prefix _s2065_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (tt,(existT _ _s2066_ _)) => + (match (string_drop _s2065_ + _s2066_) with + | _s2067_ => + (reg_name_matches_prefix + _s2067_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__8 with + | Some + (rs2,(existT _ _s2068_ _)) => + let p0_ := + string_drop + _s2067_ + _s2068_ in + if ((generic_eq + p0_ "")) + then + Some + ((size, aq, rl, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5))). + +Definition _s2030_ (_s2031_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5))) := + + let _s2032_ := _s2031_ in + (if ((string_startswith _s2032_ "lr.")) then + (match (string_drop _s2032_ (projT1 (string_length "lr."))) with + | _s2033_ => + (size_mnemonic_matches_prefix _s2033_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s2034_ _)) => + (match (string_drop _s2033_ _s2034_) with + | _s2035_ => + (maybe_aq_matches_prefix _s2035_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s2036_ _)) => + (match (string_drop _s2035_ _s2036_) with + | _s2037_ => + (maybe_rl_matches_prefix _s2037_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s2038_ _)) => + (match (string_drop _s2037_ _s2038_) with + | _s2039_ => + (spc_matches_prefix _s2039_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2040_ _)) => + (match (string_drop _s2039_ _s2040_) with + | _s2041_ => + (reg_name_matches_prefix _s2041_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s2042_ _)) => + (match (string_drop _s2041_ _s2042_) with + | _s2043_ => + (sep_matches_prefix _s2043_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2044_ _)) => + (match (string_drop _s2043_ _s2044_) with + | _s2045_ => + (reg_name_matches_prefix _s2045_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs1,(existT _ _s2046_ _)) => + let p0_ := + string_drop _s2045_ _s2046_ in + if ((generic_eq p0_ "")) then + Some + ((size, aq, rl, rd, rs1)) + else None + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5))). + +Definition _s2018_ (_s2019_ : string) +: M (option ((mword 5 * mword 5))) := + + let _s2020_ := _s2019_ in + (if ((string_startswith _s2020_ "sfence.vma")) then + (match (string_drop _s2020_ (projT1 (string_length "sfence.vma"))) with + | _s2021_ => + (spc_matches_prefix _s2021_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2022_ _)) => + (match (string_drop _s2021_ _s2022_) with + | _s2023_ => + (reg_name_matches_prefix _s2023_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs1,(existT _ _s2024_ _)) => + (match (string_drop _s2023_ _s2024_) with + | _s2025_ => + (sep_matches_prefix _s2025_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2026_ _)) => + (match (string_drop _s2025_ _s2026_) with + | _s2027_ => + (reg_name_matches_prefix _s2027_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2028_ _)) => + let p0_ := string_drop _s2027_ _s2028_ in + if ((generic_eq p0_ "")) then Some ((rs1, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5))). + +Definition _s2006_ (_s2007_ : string) +: M (option ((mword 4 * mword 4))) := + + let _s2008_ := _s2007_ in + (if ((string_startswith _s2008_ "fence.tso")) then + (match (string_drop _s2008_ (projT1 (string_length "fence.tso"))) with + | _s2009_ => + (spc_matches_prefix _s2009_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2010_ _)) => + (match (string_drop _s2009_ _s2010_) with + | _s2011_ => + (fence_bits_matches_prefix _s2011_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (pred,(existT _ _s2012_ _)) => + (match (string_drop _s2011_ _s2012_) with + | _s2013_ => + (sep_matches_prefix _s2013_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2014_ _)) => + (match (string_drop _s2013_ _s2014_) with + | _s2015_ => + (fence_bits_matches_prefix _s2015_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (succ,(existT _ _s2016_ _)) => + let p0_ := string_drop _s2015_ _s2016_ in + if ((generic_eq p0_ "")) then Some ((pred, succ)) + else None + | _ => None + end) + : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + else returnm (None : option ((mword 4 * mword 4)))) + : M (option ((mword 4 * mword 4))). + +Definition _s1994_ (_s1995_ : string) +: M (option ((mword 4 * mword 4))) := + + let _s1996_ := _s1995_ in + (if ((string_startswith _s1996_ "fence")) then + (match (string_drop _s1996_ (projT1 (string_length "fence"))) with + | _s1997_ => + (spc_matches_prefix _s1997_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1998_ _)) => + (match (string_drop _s1997_ _s1998_) with + | _s1999_ => + (fence_bits_matches_prefix _s1999_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (pred,(existT _ _s2000_ _)) => + (match (string_drop _s1999_ _s2000_) with + | _s2001_ => + (sep_matches_prefix _s2001_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2002_ _)) => + (match (string_drop _s2001_ _s2002_) with + | _s2003_ => + (fence_bits_matches_prefix _s2003_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (succ,(existT _ _s2004_ _)) => + let p0_ := string_drop _s2003_ _s2004_ in + if ((generic_eq p0_ "")) then Some ((pred, succ)) + else None + | _ => None + end) + : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + | _ => returnm (None : option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + end) + : M (option ((mword 4 * mword 4))) + else returnm (None : option ((mword 4 * mword 4)))) + : M (option ((mword 4 * mword 4))). + +Definition _s1975_ (_s1976_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1977_ := _s1976_ in + (if ((string_startswith _s1977_ "rem")) then + (match (string_drop _s1977_ (projT1 (string_length "rem"))) with + | _s1978_ => + (maybe_not_u_matches_prefix _s1978_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1979_ _)) => + let _s1980_ := string_drop _s1978_ _s1979_ in + (if ((string_startswith _s1980_ "w")) then + (match (string_drop _s1980_ (projT1 (string_length "w"))) with + | _s1981_ => + (spc_matches_prefix _s1981_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1982_ _)) => + (match (string_drop _s1981_ _s1982_) with + | _s1983_ => + (reg_name_matches_prefix _s1983_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1984_ _)) => + (match (string_drop _s1983_ _s1984_) with + | _s1985_ => + (sep_matches_prefix _s1985_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1986_ _)) => + (match (string_drop _s1985_ _s1986_) with + | _s1987_ => + (reg_name_matches_prefix _s1987_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1988_ _)) => + (match (string_drop _s1987_ _s1988_) with + | _s1989_ => + (sep_matches_prefix _s1989_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1990_ _)) => + (match (string_drop _s1989_ _s1990_) with + | _s1991_ => + (reg_name_matches_prefix _s1991_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1992_ _)) => + let p0_ := + string_drop _s1991_ + _s1992_ in + if ((generic_eq p0_ "")) + then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1956_ (_s1957_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1958_ := _s1957_ in + (if ((string_startswith _s1958_ "div")) then + (match (string_drop _s1958_ (projT1 (string_length "div"))) with + | _s1959_ => + (maybe_not_u_matches_prefix _s1959_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1960_ _)) => + let _s1961_ := string_drop _s1959_ _s1960_ in + (if ((string_startswith _s1961_ "w")) then + (match (string_drop _s1961_ (projT1 (string_length "w"))) with + | _s1962_ => + (spc_matches_prefix _s1962_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1963_ _)) => + (match (string_drop _s1962_ _s1963_) with + | _s1964_ => + (reg_name_matches_prefix _s1964_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1965_ _)) => + (match (string_drop _s1964_ _s1965_) with + | _s1966_ => + (sep_matches_prefix _s1966_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1967_ _)) => + (match (string_drop _s1966_ _s1967_) with + | _s1968_ => + (reg_name_matches_prefix _s1968_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1969_ _)) => + (match (string_drop _s1968_ _s1969_) with + | _s1970_ => + (sep_matches_prefix _s1970_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1971_ _)) => + (match (string_drop _s1970_ _s1971_) with + | _s1972_ => + (reg_name_matches_prefix _s1972_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1973_ _)) => + let p0_ := + string_drop _s1972_ + _s1973_ in + if ((generic_eq p0_ "")) + then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1940_ (_s1941_ : string) +: M (option ((mword 5 * mword 5 * mword 5))) := + + let _s1942_ := _s1941_ in + (if ((string_startswith _s1942_ "mulw")) then + (match (string_drop _s1942_ (projT1 (string_length "mulw"))) with + | _s1943_ => + (spc_matches_prefix _s1943_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1944_ _)) => + (match (string_drop _s1943_ _s1944_) with + | _s1945_ => + (reg_name_matches_prefix _s1945_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1946_ _)) => + (match (string_drop _s1945_ _s1946_) with + | _s1947_ => + (sep_matches_prefix _s1947_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1948_ _)) => + (match (string_drop _s1947_ _s1948_) with + | _s1949_ => + (reg_name_matches_prefix _s1949_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s1950_ _)) => + (match (string_drop _s1949_ _s1950_) with + | _s1951_ => + (sep_matches_prefix _s1951_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s1952_ _)) => + (match (string_drop _s1951_ _s1952_) with + | _s1953_ => + (reg_name_matches_prefix _s1953_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (rs2,(existT _ _s1954_ _)) => + let p0_ := + string_drop _s1953_ _s1954_ in + if ((generic_eq p0_ "")) then + Some + ((rd, rs1, rs2)) + else None + | _ => None + end) + : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + end) + : M (option ((mword 5 * mword 5 * mword 5))) + else returnm (None : option ((mword 5 * mword 5 * mword 5)))) + : M (option ((mword 5 * mword 5 * mword 5))). + +Definition _s1922_ (_s1923_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1924_ := _s1923_ in + (if ((string_startswith _s1924_ "rem")) then + (match (string_drop _s1924_ (projT1 (string_length "rem"))) with + | _s1925_ => + (maybe_not_u_matches_prefix _s1925_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1926_ _)) => + (match (string_drop _s1925_ _s1926_) with + | _s1927_ => + (spc_matches_prefix _s1927_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1928_ _)) => + (match (string_drop _s1927_ _s1928_) with + | _s1929_ => + (reg_name_matches_prefix _s1929_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1930_ _)) => + (match (string_drop _s1929_ _s1930_) with + | _s1931_ => + (sep_matches_prefix _s1931_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1932_ _)) => + (match (string_drop _s1931_ _s1932_) with + | _s1933_ => + (reg_name_matches_prefix _s1933_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1934_ _)) => + (match (string_drop _s1933_ _s1934_) with + | _s1935_ => + (sep_matches_prefix _s1935_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1936_ _)) => + (match (string_drop _s1935_ _s1936_) with + | _s1937_ => + (reg_name_matches_prefix _s1937_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1938_ _)) => + let p0_ := + string_drop _s1937_ _s1938_ in + if ((generic_eq p0_ "")) then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1904_ (_s1905_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5))) := + + let _s1906_ := _s1905_ in + (if ((string_startswith _s1906_ "div")) then + (match (string_drop _s1906_ (projT1 (string_length "div"))) with + | _s1907_ => + (maybe_not_u_matches_prefix _s1907_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s1908_ _)) => + (match (string_drop _s1907_ _s1908_) with + | _s1909_ => + (spc_matches_prefix _s1909_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1910_ _)) => + (match (string_drop _s1909_ _s1910_) with + | _s1911_ => + (reg_name_matches_prefix _s1911_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1912_ _)) => + (match (string_drop _s1911_ _s1912_) with + | _s1913_ => + (sep_matches_prefix _s1913_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1914_ _)) => + (match (string_drop _s1913_ _s1914_) with + | _s1915_ => + (reg_name_matches_prefix _s1915_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1916_ _)) => + (match (string_drop _s1915_ _s1916_) with + | _s1917_ => + (sep_matches_prefix _s1917_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1918_ _)) => + (match (string_drop _s1917_ _s1918_) with + | _s1919_ => + (reg_name_matches_prefix _s1919_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s1920_ _)) => + let p0_ := + string_drop _s1919_ _s1920_ in + if ((generic_eq p0_ "")) then + Some + ((s, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5)))) + : M (option ((bool * mword 5 * mword 5 * mword 5))). + +Definition _s1887_ (_s1888_ : string) +: M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) := + + (match _s1888_ with + | _s1889_ => + (mul_mnemonic_matches_prefix _s1889_) >>= fun w__0 : option (((bool * bool * bool) * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some ((high, signed1, signed2),(existT _ _s1890_ _)) => + (match (string_drop _s1889_ _s1890_) with + | _s1891_ => + (spc_matches_prefix _s1891_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1892_ _)) => + (match (string_drop _s1891_ _s1892_) with + | _s1893_ => + (reg_name_matches_prefix _s1893_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1894_ _)) => + (match (string_drop _s1893_ _s1894_) with + | _s1895_ => + (sep_matches_prefix _s1895_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1896_ _)) => + (match (string_drop _s1895_ _s1896_) with + | _s1897_ => + (reg_name_matches_prefix _s1897_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1898_ _)) => + (match (string_drop _s1897_ _s1898_) with + | _s1899_ => + (sep_matches_prefix _s1899_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1900_ _)) => + (match (string_drop _s1899_ _s1900_) with + | _s1901_ => + (reg_name_matches_prefix _s1901_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s1902_ _)) => + let p0_ := + string_drop _s1901_ _s1902_ in + if ((generic_eq p0_ "")) then + Some + ((high, signed1, signed2, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5))). + +Definition _s1872_ (_s1873_ : string) +: M (option ((sopw * mword 5 * mword 5 * mword 5))) := + + (match _s1873_ with + | _s1874_ => + (shiftiwop_mnemonic_matches_prefix _s1874_) >>= fun w__0 : option ((sopw * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1875_ _)) => + (match (string_drop _s1874_ _s1875_) with + | _s1876_ => + (spc_matches_prefix _s1876_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1877_ _)) => + (match (string_drop _s1876_ _s1877_) with + | _s1878_ => + (reg_name_matches_prefix _s1878_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1879_ _)) => + (match (string_drop _s1878_ _s1879_) with + | _s1880_ => + (sep_matches_prefix _s1880_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1881_ _)) => + (match (string_drop _s1880_ _s1881_) with + | _s1882_ => + (reg_name_matches_prefix _s1882_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (rs1,(existT _ _s1883_ _)) => + match (string_drop _s1882_ _s1883_) with + | _s1884_ => + match (hex_bits_5_matches_prefix _s1884_) with + | Some (shamt,(existT _ _s1885_ _)) => + let p0_ := string_drop _s1884_ _s1885_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5))). + +Definition _s1855_ (_s1856_ : string) +: M (option ((ropw * mword 5 * mword 5 * mword 5))) := + + (match _s1856_ with + | _s1857_ => + (rtypew_mnemonic_matches_prefix _s1857_) >>= fun w__0 : option ((ropw * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1858_ _)) => + (match (string_drop _s1857_ _s1858_) with + | _s1859_ => + (spc_matches_prefix _s1859_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1860_ _)) => + (match (string_drop _s1859_ _s1860_) with + | _s1861_ => + (reg_name_matches_prefix _s1861_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1862_ _)) => + (match (string_drop _s1861_ _s1862_) with + | _s1863_ => + (sep_matches_prefix _s1863_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1864_ _)) => + (match (string_drop _s1863_ _s1864_) with + | _s1865_ => + (reg_name_matches_prefix _s1865_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1866_ _)) => + (match (string_drop _s1865_ _s1866_) with + | _s1867_ => + (sep_matches_prefix _s1867_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1868_ _)) => + (match (string_drop _s1867_ _s1868_) with + | _s1869_ => + (reg_name_matches_prefix _s1869_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s1870_ _)) => + let p0_ := + string_drop _s1869_ _s1870_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5))). + +Definition _s1838_ (_s1839_ : string) +: M (option ((sop * mword 5 * mword 5 * mword 5))) := + + (match _s1839_ with + | _s1840_ => + (shiftw_mnemonic_matches_prefix _s1840_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1841_ _)) => + (match (string_drop _s1840_ _s1841_) with + | _s1842_ => + (spc_matches_prefix _s1842_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1843_ _)) => + (match (string_drop _s1842_ _s1843_) with + | _s1844_ => + (reg_name_matches_prefix _s1844_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1845_ _)) => + (match (string_drop _s1844_ _s1845_) with + | _s1846_ => + (sep_matches_prefix _s1846_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1847_ _)) => + (match (string_drop _s1846_ _s1847_) with + | _s1848_ => + (reg_name_matches_prefix _s1848_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1849_ _)) => + (match (string_drop _s1848_ _s1849_) with + | _s1850_ => + (sep_matches_prefix _s1850_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s1851_ _)) => + match (string_drop _s1850_ _s1851_) with + | _s1852_ => + match (hex_bits_5_matches_prefix + _s1852_) with + | Some (shamt,(existT _ _s1853_ _)) => + let p0_ := + string_drop _s1852_ _s1853_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5))). + +Definition _s1822_ (_s1823_ : string) +: M (option ((mword 5 * mword 5 * mword 12))) := + + let _s1824_ := _s1823_ in + (if ((string_startswith _s1824_ "addiw")) then + (match (string_drop _s1824_ (projT1 (string_length "addiw"))) with + | _s1825_ => + (spc_matches_prefix _s1825_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1826_ _)) => + (match (string_drop _s1825_ _s1826_) with + | _s1827_ => + (reg_name_matches_prefix _s1827_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1828_ _)) => + (match (string_drop _s1827_ _s1828_) with + | _s1829_ => + (sep_matches_prefix _s1829_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1830_ _)) => + (match (string_drop _s1829_ _s1830_) with + | _s1831_ => + (reg_name_matches_prefix _s1831_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s1832_ _)) => + (match (string_drop _s1831_ _s1832_) with + | _s1833_ => + (sep_matches_prefix _s1833_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s1834_ _)) => + match (string_drop _s1833_ _s1834_) with + | _s1835_ => + match (hex_bits_12_matches_prefix _s1835_) with + | Some (imm,(existT _ _s1836_ _)) => + let p0_ := string_drop _s1835_ _s1836_ in + if ((generic_eq p0_ "")) then + Some + ((rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + else returnm (None : option ((mword 5 * mword 5 * mword 12)))) + : M (option ((mword 5 * mword 5 * mword 12))). + +Definition _s1800_ (_s1801_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) := + + let _s1802_ := _s1801_ in + (if ((string_startswith _s1802_ "s")) then + (match (string_drop _s1802_ (projT1 (string_length "s"))) with + | _s1803_ => + (size_mnemonic_matches_prefix _s1803_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s1804_ _)) => + (match (string_drop _s1803_ _s1804_) with + | _s1805_ => + (maybe_aq_matches_prefix _s1805_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s1806_ _)) => + (match (string_drop _s1805_ _s1806_) with + | _s1807_ => + (maybe_rl_matches_prefix _s1807_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s1808_ _)) => + (match (string_drop _s1807_ _s1808_) with + | _s1809_ => + (spc_matches_prefix _s1809_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1810_ _)) => + (match (string_drop _s1809_ _s1810_) with + | _s1811_ => + (reg_name_matches_prefix _s1811_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s1812_ _)) => + (match (string_drop _s1811_ _s1812_) with + | _s1813_ => + (sep_matches_prefix _s1813_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1814_ _)) => + (match (string_drop _s1813_ _s1814_) with + | _s1815_ => + (reg_name_matches_prefix _s1815_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (rs1,(existT _ _s1816_ _)) => + (match (string_drop _s1815_ _s1816_) with + | _s1817_ => + (sep_matches_prefix _s1817_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__7 with + | Some + (tt,(existT _ _s1818_ _)) => + match (string_drop + _s1817_ + _s1818_) with + | _s1819_ => + match (hex_bits_12_matches_prefix + _s1819_) with + | Some + (imm,(existT _ _s1820_ _)) => + let p0_ := + string_drop + _s1819_ + _s1820_ in + if ((generic_eq + p0_ "")) + then + Some + ((size, aq, rl, rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12))). + +Definition _s1776_ (_s1777_ : string) +: M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) := + + let _s1778_ := _s1777_ in + (if ((string_startswith _s1778_ "l")) then + (match (string_drop _s1778_ (projT1 (string_length "l"))) with + | _s1779_ => + (size_mnemonic_matches_prefix _s1779_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s1780_ _)) => + (match (string_drop _s1779_ _s1780_) with + | _s1781_ => + (maybe_u_matches_prefix _s1781_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (is_unsigned,(existT _ _s1782_ _)) => + (match (string_drop _s1781_ _s1782_) with + | _s1783_ => + (maybe_aq_matches_prefix _s1783_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (aq,(existT _ _s1784_ _)) => + (match (string_drop _s1783_ _s1784_) with + | _s1785_ => + (maybe_rl_matches_prefix _s1785_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rl,(existT _ _s1786_ _)) => + (match (string_drop _s1785_ _s1786_) with + | _s1787_ => + (spc_matches_prefix _s1787_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s1788_ _)) => + (match (string_drop _s1787_ _s1788_) with + | _s1789_ => + (reg_name_matches_prefix _s1789_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (rd,(existT _ _s1790_ _)) => + (match (string_drop _s1789_ _s1790_) with + | _s1791_ => + (sep_matches_prefix _s1791_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (tt,(existT _ _s1792_ _)) => + (match (string_drop _s1791_ _s1792_) with + | _s1793_ => + (reg_name_matches_prefix _s1793_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (rs1,(existT _ _s1794_ _)) => + (match (string_drop _s1793_ + _s1794_) with + | _s1795_ => + (sep_matches_prefix + _s1795_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__8 with + | Some + (tt,(existT _ _s1796_ _)) => + match (string_drop + _s1795_ + _s1796_) with + | _s1797_ => + match (hex_bits_12_matches_prefix + _s1797_) with + | Some + (imm,(existT _ _s1798_ _)) => + let p0_ := + string_drop + _s1797_ + _s1798_ in + if ((generic_eq + p0_ + "")) + then + Some + ((size, is_unsigned, aq, rl, rd, rs1, imm)) + else + None + | _ => + None + end + end + | _ => None + end) + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))) + else returnm (None : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12)))) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12))). + +Definition _s1759_ (_s1760_ : string) +: M (option ((rop * mword 5 * mword 5 * mword 5))) := + + (match _s1760_ with + | _s1761_ => + (rtype_mnemonic_matches_prefix _s1761_) >>= fun w__0 : option ((rop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1762_ _)) => + (match (string_drop _s1761_ _s1762_) with + | _s1763_ => + (spc_matches_prefix _s1763_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1764_ _)) => + (match (string_drop _s1763_ _s1764_) with + | _s1765_ => + (reg_name_matches_prefix _s1765_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1766_ _)) => + (match (string_drop _s1765_ _s1766_) with + | _s1767_ => + (sep_matches_prefix _s1767_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1768_ _)) => + (match (string_drop _s1767_ _s1768_) with + | _s1769_ => + (reg_name_matches_prefix _s1769_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1770_ _)) => + (match (string_drop _s1769_ _s1770_) with + | _s1771_ => + (sep_matches_prefix _s1771_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s1772_ _)) => + (match (string_drop _s1771_ _s1772_) with + | _s1773_ => + (reg_name_matches_prefix _s1773_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s1774_ _)) => + let p0_ := + string_drop _s1773_ _s1774_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, rs2)) + else None + | _ => None + end) + : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => + returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5))). + +Definition _s1744_ (_s1745_ : string) +: M (option ((sop * mword 5 * mword 5 * mword 6))) := + + (match _s1745_ with + | _s1746_ => + (shiftiop_mnemonic_matches_prefix _s1746_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1747_ _)) => + (match (string_drop _s1746_ _s1747_) with + | _s1748_ => + (spc_matches_prefix _s1748_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1749_ _)) => + (match (string_drop _s1748_ _s1749_) with + | _s1750_ => + (reg_name_matches_prefix _s1750_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1751_ _)) => + (match (string_drop _s1750_ _s1751_) with + | _s1752_ => + (sep_matches_prefix _s1752_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1753_ _)) => + (match (string_drop _s1752_ _s1753_) with + | _s1754_ => + (reg_name_matches_prefix _s1754_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (rs1,(existT _ _s1755_ _)) => + match (string_drop _s1754_ _s1755_) with + | _s1756_ => + match (hex_bits_6_matches_prefix _s1756_) with + | Some (shamt,(existT _ _s1757_ _)) => + let p0_ := string_drop _s1756_ _s1757_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, shamt)) + else None + | _ => None + end + end + | _ => None + end) + : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => + returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6))). + +Definition _s1727_ (_s1728_ : string) +: M (option ((iop * mword 5 * mword 5 * mword 12))) := + + (match _s1728_ with + | _s1729_ => + (itype_mnemonic_matches_prefix _s1729_) >>= fun w__0 : option ((iop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1730_ _)) => + (match (string_drop _s1729_ _s1730_) with + | _s1731_ => + (spc_matches_prefix _s1731_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1732_ _)) => + (match (string_drop _s1731_ _s1732_) with + | _s1733_ => + (reg_name_matches_prefix _s1733_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1734_ _)) => + (match (string_drop _s1733_ _s1734_) with + | _s1735_ => + (sep_matches_prefix _s1735_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1736_ _)) => + (match (string_drop _s1735_ _s1736_) with + | _s1737_ => + (reg_name_matches_prefix _s1737_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s1738_ _)) => + (match (string_drop _s1737_ _s1738_) with + | _s1739_ => + (sep_matches_prefix _s1739_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s1740_ _)) => + match (string_drop _s1739_ _s1740_) with + | _s1741_ => + match (hex_bits_12_matches_prefix + _s1741_) with + | Some (imm,(existT _ _s1742_ _)) => + let p0_ := + string_drop _s1741_ _s1742_ in + if ((generic_eq p0_ "")) then + Some + ((op, rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None + : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => + returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12))). + +Definition _s1710_ (_s1711_ : string) +: M (option ((bop * mword 5 * mword 5 * mword 13))) := + + (match _s1711_ with + | _s1712_ => + (btype_mnemonic_matches_prefix _s1712_) >>= fun w__0 : option ((bop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1713_ _)) => + (match (string_drop _s1712_ _s1713_) with + | _s1714_ => + (spc_matches_prefix _s1714_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1715_ _)) => + (match (string_drop _s1714_ _s1715_) with + | _s1716_ => + (reg_name_matches_prefix _s1716_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rs1,(existT _ _s1717_ _)) => + (match (string_drop _s1716_ _s1717_) with + | _s1718_ => + (sep_matches_prefix _s1718_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s1719_ _)) => + (match (string_drop _s1718_ _s1719_) with + | _s1720_ => + (reg_name_matches_prefix _s1720_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs2,(existT _ _s1721_ _)) => + (match (string_drop _s1720_ _s1721_) with + | _s1722_ => + (sep_matches_prefix _s1722_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s1723_ _)) => + match (string_drop _s1722_ _s1723_) with + | _s1724_ => + match (hex_bits_13_matches_prefix + _s1724_) with + | Some (imm,(existT _ _s1725_ _)) => + let p0_ := + string_drop _s1724_ _s1725_ in + if ((generic_eq p0_ "")) then + Some + ((op, rs1, rs2, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => + returnm (None + : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => + returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13))). + +Definition _s1694_ (_s1695_ : string) +: M (option ((mword 5 * mword 5 * mword 12))) := + + let _s1696_ := _s1695_ in + (if ((string_startswith _s1696_ "jalr")) then + (match (string_drop _s1696_ (projT1 (string_length "jalr"))) with + | _s1697_ => + (spc_matches_prefix _s1697_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1698_ _)) => + (match (string_drop _s1697_ _s1698_) with + | _s1699_ => + (reg_name_matches_prefix _s1699_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1700_ _)) => + (match (string_drop _s1699_ _s1700_) with + | _s1701_ => + (sep_matches_prefix _s1701_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s1702_ _)) => + (match (string_drop _s1701_ _s1702_) with + | _s1703_ => + (reg_name_matches_prefix _s1703_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s1704_ _)) => + (match (string_drop _s1703_ _s1704_) with + | _s1705_ => + (sep_matches_prefix _s1705_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s1706_ _)) => + match (string_drop _s1705_ _s1706_) with + | _s1707_ => + match (hex_bits_12_matches_prefix _s1707_) with + | Some (imm,(existT _ _s1708_ _)) => + let p0_ := string_drop _s1707_ _s1708_ in + if ((generic_eq p0_ "")) then + Some + ((rd, rs1, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + end) + : M (option ((mword 5 * mword 5 * mword 12))) + else returnm (None : option ((mword 5 * mword 5 * mword 12)))) + : M (option ((mword 5 * mword 5 * mword 12))). + +Definition _s1682_ (_s1683_ : string) +: M (option ((mword 5 * mword 21))) := + + let _s1684_ := _s1683_ in + (if ((string_startswith _s1684_ "jal")) then + (match (string_drop _s1684_ (projT1 (string_length "jal"))) with + | _s1685_ => + (spc_matches_prefix _s1685_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s1686_ _)) => + (match (string_drop _s1685_ _s1686_) with + | _s1687_ => + (reg_name_matches_prefix _s1687_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s1688_ _)) => + (match (string_drop _s1687_ _s1688_) with + | _s1689_ => + (sep_matches_prefix _s1689_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s1690_ _)) => + match (string_drop _s1689_ _s1690_) with + | _s1691_ => + match (hex_bits_21_matches_prefix _s1691_) with + | Some (imm,(existT _ _s1692_ _)) => + let p0_ := string_drop _s1691_ _s1692_ in + if ((generic_eq p0_ "")) then Some ((rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + | _ => returnm (None : option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + | _ => returnm (None : option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + end) + : M (option ((mword 5 * mword 21))) + else returnm (None : option ((mword 5 * mword 21)))) + : M (option ((mword 5 * mword 21))). + +Definition _s1669_ (_s1670_ : string) +: M (option ((uop * mword 5 * mword 20))) := + + (match _s1670_ with + | _s1671_ => + (utype_mnemonic_matches_prefix _s1671_) >>= fun w__0 : option ((uop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s1672_ _)) => + (match (string_drop _s1671_ _s1672_) with + | _s1673_ => + (spc_matches_prefix _s1673_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s1674_ _)) => + (match (string_drop _s1673_ _s1674_) with + | _s1675_ => + (reg_name_matches_prefix _s1675_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s1676_ _)) => + (match (string_drop _s1675_ _s1676_) with + | _s1677_ => + (sep_matches_prefix _s1677_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (tt,(existT _ _s1678_ _)) => + match (string_drop _s1677_ _s1678_) with + | _s1679_ => + match (hex_bits_20_matches_prefix _s1679_) with + | Some (imm,(existT _ _s1680_ _)) => + let p0_ := string_drop _s1679_ _s1680_ in + if ((generic_eq p0_ "")) then Some ((op, rd, imm)) + else None + | _ => None + end + end + | _ => None + end) + : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + | _ => returnm (None : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + | _ => returnm (None : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + | _ => returnm (None : option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))) + end) + : M (option ((uop * mword 5 * mword 20))). + +Definition assembly_backwards_matches (arg_ : string) +: M (bool) := + + let _s1681_ := arg_ in + (_s1669_ _s1681_) >>= fun w__0 : option ((uop * mword 5 * mword 20)) => + (if ((match w__0 with | Some (op,rd,imm) => true | _ => false end)) then + (_s1669_ _s1681_) >>= fun w__1 : option ((uop * mword 5 * mword 20)) => + (match w__1 with | Some (op,rd,imm) => returnm (true : bool) | _ => exit tt : M (bool) end) + : M (bool) + else + (_s1682_ _s1681_) >>= fun w__4 : option ((mword 5 * mword 21)) => + (if ((match w__4 with | Some (rd,imm) => true | _ => false end)) then + (_s1682_ _s1681_) >>= fun w__5 : option ((mword 5 * mword 21)) => + (match w__5 with | Some (rd,imm) => returnm (true : bool) | _ => exit tt : M (bool) end) + : M (bool) + else + (_s1694_ _s1681_) >>= fun w__8 : option ((mword 5 * mword 5 * mword 12)) => + (if ((match w__8 with | Some (rd,rs1,imm) => true | _ => false end)) then + (_s1694_ _s1681_) >>= fun w__9 : option ((mword 5 * mword 5 * mword 12)) => + (match w__9 with + | Some (rd,rs1,imm) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1710_ _s1681_) >>= fun w__12 : option ((bop * mword 5 * mword 5 * mword 13)) => + (if ((match w__12 with | Some (op,rs1,rs2,imm) => true | _ => false end)) then + (_s1710_ _s1681_) >>= fun w__13 : option ((bop * mword 5 * mword 5 * mword 13)) => + (match w__13 with + | Some (op,rs1,rs2,imm) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1727_ _s1681_) >>= fun w__16 : option ((iop * mword 5 * mword 5 * mword 12)) => + (if ((match w__16 with | Some (op,rd,rs1,imm) => true | _ => false end)) then + (_s1727_ _s1681_) >>= fun w__17 : option ((iop * mword 5 * mword 5 * mword 12)) => + (match w__17 with + | Some (op,rd,rs1,imm) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1744_ _s1681_) >>= fun w__20 : option ((sop * mword 5 * mword 5 * mword 6)) => + (if ((match w__20 with | Some (op,rd,rs1,shamt) => true | _ => false end)) then + (_s1744_ _s1681_) >>= fun w__21 : option ((sop * mword 5 * mword 5 * mword 6)) => + (match w__21 with + | Some (op,rd,rs1,shamt) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1759_ _s1681_) >>= fun w__24 : option ((rop * mword 5 * mword 5 * mword 5)) => + (if ((match w__24 with | Some (op,rd,rs1,rs2) => true | _ => false end)) then + (_s1759_ _s1681_) >>= fun w__25 : option ((rop * mword 5 * mword 5 * mword 5)) => + (match w__25 with + | Some (op,rd,rs1,rs2) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1776_ _s1681_) >>= fun w__28 : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12)) => + (if ((match w__28 with + | Some (size,is_unsigned,aq,rl,rd,rs1,imm) => true + | _ => false + end)) then + (_s1776_ _s1681_) >>= fun w__29 : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12)) => + (match w__29 with + | Some (size,is_unsigned,aq,rl,rd,rs1,imm) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1800_ _s1681_) >>= fun w__32 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12)) => + (if ((match w__32 with + | Some (size,aq,rl,rd,rs1,imm) => true + | _ => false + end)) then + (_s1800_ _s1681_) >>= fun w__33 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12)) => + (match w__33 with + | Some (size,aq,rl,rd,rs1,imm) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1822_ _s1681_) >>= fun w__36 : option ((mword 5 * mword 5 * mword 12)) => + (if ((match w__36 with | Some (rd,rs1,imm) => true | _ => false end)) + then + (_s1822_ _s1681_) >>= fun w__37 : option ((mword 5 * mword 5 * mword 12)) => + (match w__37 with + | Some (rd,rs1,imm) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1838_ _s1681_) >>= fun w__40 : option ((sop * mword 5 * mword 5 * mword 5)) => + (if ((match w__40 with + | Some (op,rd,rs1,shamt) => true + | _ => false + end)) then + (_s1838_ _s1681_) >>= fun w__41 : option ((sop * mword 5 * mword 5 * mword 5)) => + (match w__41 with + | Some (op,rd,rs1,shamt) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1855_ _s1681_) >>= fun w__44 : option ((ropw * mword 5 * mword 5 * mword 5)) => + (if ((match w__44 with + | Some (op,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1855_ _s1681_) >>= fun w__45 : option ((ropw * mword 5 * mword 5 * mword 5)) => + (match w__45 with + | Some (op,rd,rs1,rs2) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1872_ _s1681_) >>= fun w__48 : option ((sopw * mword 5 * mword 5 * mword 5)) => + (if ((match w__48 with + | Some (op,rd,rs1,shamt) => true + | _ => false + end)) then + (_s1872_ _s1681_) >>= fun w__49 : option ((sopw * mword 5 * mword 5 * mword 5)) => + (match w__49 with + | Some (op,rd,rs1,shamt) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1887_ _s1681_) >>= fun w__52 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__52 with + | Some (high,signed1,signed2,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1887_ _s1681_) >>= fun w__53 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5)) => + (match w__53 with + | Some (high,signed1,signed2,rd,rs1,rs2) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1904_ _s1681_) >>= fun w__56 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__56 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1904_ _s1681_) >>= fun w__57 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__57 with + | Some (s,rd,rs1,rs2) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1922_ _s1681_) >>= fun w__60 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__60 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1922_ _s1681_) >>= fun w__61 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__61 with + | Some (s,rd,rs1,rs2) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1940_ _s1681_) >>= fun w__64 : option ((mword 5 * mword 5 * mword 5)) => + (if ((match w__64 with + | Some (rd,rs1,rs2) => true + | _ => false + end)) then + (_s1940_ _s1681_) >>= fun w__65 : option ((mword 5 * mword 5 * mword 5)) => + (match w__65 with + | Some (rd,rs1,rs2) => returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1956_ _s1681_) >>= fun w__68 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__68 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1956_ _s1681_) >>= fun w__69 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__69 with + | Some (s,rd,rs1,rs2) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1975_ _s1681_) >>= fun w__72 : option ((bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__72 with + | Some (s,rd,rs1,rs2) => true + | _ => false + end)) then + (_s1975_ _s1681_) >>= fun w__73 : option ((bool * mword 5 * mword 5 * mword 5)) => + (match w__73 with + | Some (s,rd,rs1,rs2) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s1994_ _s1681_) >>= fun w__76 : option ((mword 4 * mword 4)) => + (if ((match w__76 with + | Some (pred,succ) => true + | _ => false + end)) then + (_s1994_ _s1681_) >>= fun w__77 : option ((mword 4 * mword 4)) => + (match w__77 with + | Some (pred,succ) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s2006_ _s1681_) >>= fun w__80 : option ((mword 4 * mword 4)) => + (if ((match w__80 with + | Some (pred,succ) => true + | _ => false + end)) then + (_s2006_ _s1681_) >>= fun w__81 : option ((mword 4 * mword 4)) => + (match w__81 with + | Some (pred,succ) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else if ((generic_eq _s1681_ + "fence.i")) then + returnm (true + : bool) + else if ((generic_eq _s1681_ "ecall")) + then + returnm (true + : bool) + else if ((generic_eq _s1681_ "mret")) + then + returnm (true + : bool) + else if ((generic_eq _s1681_ "sret")) + then + returnm (true + : bool) + else if ((generic_eq _s1681_ + "ebreak")) then + returnm (true + : bool) + else if ((generic_eq _s1681_ "wfi")) + then + returnm (true + : bool) + else + (_s2018_ _s1681_) >>= fun w__84 : option ((mword 5 * mword 5)) => + (if ((match w__84 with + | Some (rs1,rs2) => true + | _ => false + end)) then + (_s2018_ _s1681_) >>= fun w__85 : option ((mword 5 * mword 5)) => + (match w__85 with + | Some (rs1,rs2) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s2030_ _s1681_) >>= fun w__88 : option ((word_width * bool * bool * mword 5 * mword 5)) => + (if ((match w__88 with + | Some + (size,aq,rl,rd,rs1) => + true + | _ => false + end)) then + (_s2030_ _s1681_) >>= fun w__89 : option ((word_width * bool * bool * mword 5 * mword 5)) => + (match w__89 with + | Some (size,aq,rl,rd,rs1) => + returnm (true : bool) + | _ => exit tt : M (bool) + end) + : M (bool) + else + (_s2048_ _s1681_) >>= fun w__92 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__92 with + | Some + (size,aq,rl,rd,rs1,rs2) => + true + | _ => false + end)) then + (_s2048_ _s1681_) >>= fun w__93 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (match w__93 with + | Some + (size,aq,rl,rd,rs1,rs2) => + returnm (true + : bool) + | _ => + exit tt : M (bool) + end) + : M (bool) + else + (_s2070_ _s1681_) >>= fun w__96 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (if ((match w__96 with + | Some + (op,width,aq,rl,rd,rs1,rs2) => + true + | _ => false + end)) then + (_s2070_ _s1681_) >>= fun w__97 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5)) => + (match w__97 with + | Some + (op,width,aq,rl,rd,rs1,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2094_ _s1681_) >>= fun w__100 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (if ((match w__100 with + | Some + (op,rd,rs1,csr) => + true + | _ => false + end)) then + (_s2094_ _s1681_) >>= fun w__101 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (match w__101 with + | Some + (op,rd,rs1,csr) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2112_ _s1681_) >>= fun w__104 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (if ((match w__104 with + | Some + (op,rd,rs1,csr) => + true + | _ => false + end)) then + (_s2112_ _s1681_) >>= fun w__105 : option ((csrop * mword 5 * mword 5 * mword 12)) => + (match w__105 with + | Some + (op,rd,rs1,csr) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else if ((generic_eq + _s1681_ + "c.nop")) + then + returnm (true + : bool) + else + (_s2129_ _s1681_) >>= fun w__108 : option ((mword 3 * mword 8)) => + (if ((match w__108 with + | Some + (rdc,nzimm) => + neq_vec + nzimm + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : mword 8) + | _ => + false + end)) then + (_s2129_ + _s1681_) >>= fun w__109 : option ((mword 3 * mword 8)) => + (match w__109 with + | Some + (rdc,nzimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2141_ + _s1681_) >>= fun w__112 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__112 with + | Some + (rdc,rsc,uimm) => + true + | _ => + false + end)) + then + (_s2141_ + _s1681_) >>= fun w__113 : option ((mword 3 * mword 3 * mword 5)) => + (match w__113 with + | Some + (rdc,rsc,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2157_ + _s1681_) >>= fun w__116 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__116 with + | Some + (rdc,rsc,uimm) => + true + | _ => + false + end)) + then + (_s2157_ + _s1681_) >>= fun w__117 : option ((mword 3 * mword 3 * mword 5)) => + (match w__117 with + | Some + (rdc,rsc,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2173_ + _s1681_) >>= fun w__120 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__120 with + | Some + (rsc1,rsc2,uimm) => + true + | _ => + false + end)) + then + (_s2173_ + _s1681_) >>= fun w__121 : option ((mword 3 * mword 3 * mword 5)) => + (match w__121 with + | Some + (rsc1,rsc2,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2189_ + _s1681_) >>= fun w__124 : option ((mword 3 * mword 3 * mword 5)) => + (if ((match w__124 with + | Some + (rsc1,rsc2,uimm) => + true + | _ => + false + end)) + then + (_s2189_ + _s1681_) >>= fun w__125 : option ((mword 3 * mword 3 * mword 5)) => + (match w__125 with + | Some + (rsc1,rsc2,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2205_ + _s1681_) >>= fun w__128 : option ((mword 5 * mword 6)) => + (if + ((match w__128 with + | Some + (rsd,nzi) => + andb + (neq_vec + nzi + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6)) + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s2205_ + _s1681_) >>= fun w__129 : option ((mword 5 * mword 6)) => + (match w__129 with + | Some + (rsd,nzi) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2217_ + _s1681_) >>= fun w__132 : option (mword 11) => + (if + ((match w__132 with + | Some + (imm) => + true + | _ => + false + end)) + then + (_s2217_ + _s1681_) >>= fun w__133 : option (mword 11) => + (match w__133 with + | Some + (imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2225_ + _s1681_) >>= fun w__136 : option ((mword 5 * mword 6)) => + (if + ((match w__136 with + | Some + (rsd,imm) => + true + | _ => + false + end)) + then + (_s2225_ + _s1681_) >>= fun w__137 : option ((mword 5 * mword 6)) => + (match w__137 with + | Some + (rsd,imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2237_ + _s1681_) >>= fun w__140 : option ((mword 5 * mword 6)) => + (if + ((match w__140 with + | Some + (rd,imm) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s2237_ + _s1681_) >>= fun w__141 : option ((mword 5 * mword 6)) => + (match w__141 with + | Some + (rd,imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2249_ + _s1681_) >>= fun w__144 : option (mword 6) => + (if + ((match w__144 with + | Some + (imm) => + neq_vec + imm + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s2249_ + _s1681_) >>= fun w__145 : option (mword 6) => + (match w__145 with + | Some + (imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2257_ + _s1681_) >>= fun w__148 : option ((mword 5 * mword 6)) => + (if + ((match w__148 with + | Some + (rd,imm) => + andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg))) + (andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + sp))) + (neq_vec + imm + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6))) + | _ => + false + end)) + then + (_s2257_ + _s1681_) >>= fun w__149 : option ((mword 5 * mword 6)) => + (match w__149 with + | Some + (rd,imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2269_ + _s1681_) >>= fun w__152 : option ((mword 3 * mword 6)) => + (if + ((match w__152 with + | Some + (rsd,shamt) => + neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s2269_ + _s1681_) >>= fun w__153 : option ((mword 3 * mword 6)) => + (match w__153 with + | Some + (rsd,shamt) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2281_ + _s1681_) >>= fun w__156 : option ((mword 3 * mword 6)) => + (if + ((match w__156 with + | Some + (rsd,shamt) => + neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s2281_ + _s1681_) >>= fun w__157 : option ((mword 3 * mword 6)) => + (match w__157 with + | Some + (rsd,shamt) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2293_ + _s1681_) >>= fun w__160 : option ((mword 3 * mword 6)) => + (if + ((match w__160 with + | Some + (rsd,imm) => + true + | _ => + false + end)) + then + (_s2293_ + _s1681_) >>= fun w__161 : option ((mword 3 * mword 6)) => + (match w__161 with + | Some + (rsd,imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2305_ + _s1681_) >>= fun w__164 : option ((mword 3 * mword 3)) => + (if + ((match w__164 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s2305_ + _s1681_) >>= fun w__165 : option ((mword 3 * mword 3)) => + (match w__165 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2317_ + _s1681_) >>= fun w__168 : option ((mword 3 * mword 3)) => + (if + ((match w__168 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s2317_ + _s1681_) >>= fun w__169 : option ((mword 3 * mword 3)) => + (match w__169 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2329_ + _s1681_) >>= fun w__172 : option ((mword 3 * mword 3)) => + (if + ((match w__172 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s2329_ + _s1681_) >>= fun w__173 : option ((mword 3 * mword 3)) => + (match w__173 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2341_ + _s1681_) >>= fun w__176 : option ((mword 3 * mword 3)) => + (if + ((match w__176 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s2341_ + _s1681_) >>= fun w__177 : option ((mword 3 * mword 3)) => + (match w__177 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2353_ + _s1681_) >>= fun w__180 : option ((mword 3 * mword 3)) => + (if + ((match w__180 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s2353_ + _s1681_) >>= fun w__181 : option ((mword 3 * mword 3)) => + (match w__181 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2365_ + _s1681_) >>= fun w__184 : option ((mword 3 * mword 3)) => + (if + ((match w__184 with + | Some + (rsd,rs2) => + true + | _ => + false + end)) + then + (_s2365_ + _s1681_) >>= fun w__185 : option ((mword 3 * mword 3)) => + (match w__185 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2377_ + _s1681_) >>= fun w__188 : option (mword 11) => + (if + ((match w__188 with + | Some + (imm) => + true + | _ => + false + end)) + then + (_s2377_ + _s1681_) >>= fun w__189 : option (mword 11) => + (match w__189 with + | Some + (imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2385_ + _s1681_) >>= fun w__192 : option ((mword 3 * mword 8)) => + (if + ((match w__192 with + | Some + (rs,imm) => + true + | _ => + false + end)) + then + (_s2385_ + _s1681_) >>= fun w__193 : option ((mword 3 * mword 8)) => + (match w__193 with + | Some + (rs,imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2397_ + _s1681_) >>= fun w__196 : option ((mword 3 * mword 8)) => + (if + ((match w__196 with + | Some + (rs,imm) => + true + | _ => + false + end)) + then + (_s2397_ + _s1681_) >>= fun w__197 : option ((mword 3 * mword 8)) => + (match w__197 with + | Some + (rs,imm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2409_ + _s1681_) >>= fun w__200 : option ((mword 5 * mword 6)) => + (if + ((match w__200 with + | Some + (rsd,shamt) => + andb + (neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6)) + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s2409_ + _s1681_) >>= fun w__201 : option ((mword 5 * mword 6)) => + (match w__201 with + | Some + (rsd,shamt) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2421_ + _s1681_) >>= fun w__204 : option ((mword 5 * mword 6)) => + (if + ((match w__204 with + | Some + (rd,uimm) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s2421_ + _s1681_) >>= fun w__205 : option ((mword 5 * mword 6)) => + (match w__205 with + | Some + (rd,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2433_ + _s1681_) >>= fun w__208 : option ((mword 5 * mword 6)) => + (if + ((match w__208 with + | Some + (rd,uimm) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s2433_ + _s1681_) >>= fun w__209 : option ((mword 5 * mword 6)) => + (match w__209 with + | Some + (rd,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2445_ + _s1681_) >>= fun w__212 : option ((mword 5 * mword 6)) => + (if + ((match w__212 with + | Some + (rd,uimm) => + true + | _ => + false + end)) + then + (_s2445_ + _s1681_) >>= fun w__213 : option ((mword 5 * mword 6)) => + (match w__213 with + | Some + (rd,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2457_ + _s1681_) >>= fun w__216 : option ((mword 5 * mword 6)) => + (if + ((match w__216 with + | Some + (rs2,uimm) => + true + | _ => + false + end)) + then + (_s2457_ + _s1681_) >>= fun w__217 : option ((mword 5 * mword 6)) => + (match w__217 with + | Some + (rs2,uimm) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2469_ + _s1681_) >>= fun w__220 : option (mword 5) => + (if + ((match w__220 with + | Some + (rs1) => + neq_int + (projT1 (regbits_to_regno + rs1)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s2469_ + _s1681_) >>= fun w__221 : option (mword 5) => + (match w__221 with + | Some + (rs1) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2477_ + _s1681_) >>= fun w__224 : option (mword 5) => + (if + ((match w__224 with + | Some + (rs1) => + neq_int + (projT1 (regbits_to_regno + rs1)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s2477_ + _s1681_) >>= fun w__225 : option (mword 5) => + (match w__225 with + | Some + (rs1) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2485_ + _s1681_) >>= fun w__228 : option ((mword 5 * mword 5)) => + (if + ((match w__228 with + | Some + (rd,rs2) => + andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg))) + (neq_int + (projT1 (regbits_to_regno + rs2)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s2485_ + _s1681_) >>= fun w__229 : option ((mword 5 * mword 5)) => + (match w__229 with + | Some + (rd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else if + ((generic_eq + _s1681_ + "c.ebreak")) + then + returnm (true + : bool) + else + (_s2497_ + _s1681_) >>= fun w__232 : option ((mword 5 * mword 5)) => + (if + ((match w__232 with + | Some + (rsd,rs2) => + andb + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + (neq_int + (projT1 (regbits_to_regno + rs2)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s2497_ + _s1681_) >>= fun w__233 : option ((mword 5 * mword 5)) => + (match w__233 with + | Some + (rsd,rs2) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else if + ((generic_eq + _s1681_ + "stop_fetching")) + then + returnm (true + : bool) + else if + ((generic_eq + _s1681_ + "thread_start")) + then + returnm (true + : bool) + else + (_s2509_ + _s1681_) >>= fun w__236 : option (mword 32) => + (if + ((match w__236 with + | Some + (s) => + true + | _ => + false + end)) + then + (_s2509_ + _s1681_) >>= fun w__237 : option (mword 32) => + (match w__237 with + | Some + (s) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + (_s2517_ + _s1681_) >>= fun w__240 : option (mword 16) => + (if + ((match w__240 with + | Some + (s) => + true + | _ => + false + end)) + then + (_s2517_ + _s1681_) >>= fun w__241 : option (mword 16) => + (match w__241 with + | Some + (s) => + returnm (true + : bool) + | _ => + exit tt + : M (bool) + end) + : M (bool) + else + returnm (false + : bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool)) + : M (bool). + +Definition _s3413_ (_s3414_ : string) +: M (option ((mword 16 * string))) := + + let _s3415_ := _s3414_ in + (if ((string_startswith _s3415_ "c.illegal")) then + (match (string_drop _s3415_ (projT1 (string_length "c.illegal"))) with + | _s3416_ => + (spc_matches_prefix _s3416_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s3417_ _)) => + match (string_drop _s3416_ _s3417_) with + | _s3418_ => + match (hex_bits_16_matches_prefix _s3418_) with + | Some (s,(existT _ _s3419_ _)) => + match (string_drop _s3418_ _s3419_) with | s_ => Some ((s, s_)) end + | _ => None + end + end + | _ => None + end) + : option ((mword 16 * string))) + end) + : M (option ((mword 16 * string))) + else returnm (None : option ((mword 16 * string)))) + : M (option ((mword 16 * string))). + +Definition _s3405_ (_s3406_ : string) +: M (option ((mword 32 * string))) := + + let _s3407_ := _s3406_ in + (if ((string_startswith _s3407_ "illegal")) then + (match (string_drop _s3407_ (projT1 (string_length "illegal"))) with + | _s3408_ => + (spc_matches_prefix _s3408_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s3409_ _)) => + match (string_drop _s3408_ _s3409_) with + | _s3410_ => + match (hex_bits_32_matches_prefix _s3410_) with + | Some (s,(existT _ _s3411_ _)) => + match (string_drop _s3410_ _s3411_) with | s_ => Some ((s, s_)) end + | _ => None + end + end + | _ => None + end) + : option ((mword 32 * string))) + end) + : M (option ((mword 32 * string))) + else returnm (None : option ((mword 32 * string)))) + : M (option ((mword 32 * string))). + +Definition _s3401_ (_s3402_ : string) +: option string := + + let _s3403_ := _s3402_ in + if ((string_startswith _s3403_ "thread_start")) then + match (string_drop _s3403_ (projT1 (string_length "thread_start"))) with | s_ => Some (s_) end + else None. + +Definition _s3397_ (_s3398_ : string) +: option string := + + let _s3399_ := _s3398_ in + if ((string_startswith _s3399_ "stop_fetching")) then + match (string_drop _s3399_ (projT1 (string_length "stop_fetching"))) with | s_ => Some (s_) end + else None. + +Definition _s3385_ (_s3386_ : string) +: M (option ((mword 5 * mword 5 * string))) := + + let _s3387_ := _s3386_ in + (if ((string_startswith _s3387_ "c.add")) then + (match (string_drop _s3387_ (projT1 (string_length "c.add"))) with + | _s3388_ => + (spc_matches_prefix _s3388_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3389_ _)) => + (match (string_drop _s3388_ _s3389_) with + | _s3390_ => + (reg_name_matches_prefix _s3390_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3391_ _)) => + (match (string_drop _s3390_ _s3391_) with + | _s3392_ => + (sep_matches_prefix _s3392_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3393_ _)) => + (match (string_drop _s3392_ _s3393_) with + | _s3394_ => + (reg_name_matches_prefix _s3394_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3395_ _)) => + match (string_drop _s3394_ _s3395_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + else returnm (None : option ((mword 5 * mword 5 * string)))) + : M (option ((mword 5 * mword 5 * string))). + +Definition _s3381_ (_s3382_ : string) +: option string := + + let _s3383_ := _s3382_ in + if ((string_startswith _s3383_ "c.ebreak")) then + match (string_drop _s3383_ (projT1 (string_length "c.ebreak"))) with | s_ => Some (s_) end + else None. + +Definition _s3369_ (_s3370_ : string) +: M (option ((mword 5 * mword 5 * string))) := + + let _s3371_ := _s3370_ in + (if ((string_startswith _s3371_ "c.mv")) then + (match (string_drop _s3371_ (projT1 (string_length "c.mv"))) with + | _s3372_ => + (spc_matches_prefix _s3372_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3373_ _)) => + (match (string_drop _s3372_ _s3373_) with + | _s3374_ => + (reg_name_matches_prefix _s3374_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s3375_ _)) => + (match (string_drop _s3374_ _s3375_) with + | _s3376_ => + (sep_matches_prefix _s3376_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3377_ _)) => + (match (string_drop _s3376_ _s3377_) with + | _s3378_ => + (reg_name_matches_prefix _s3378_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3379_ _)) => + match (string_drop _s3378_ _s3379_) with + | s_ => Some ((rd, rs2, s_)) + end + | _ => None + end) + : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + else returnm (None : option ((mword 5 * mword 5 * string)))) + : M (option ((mword 5 * mword 5 * string))). + +Definition _s3361_ (_s3362_ : string) +: M (option ((mword 5 * string))) := + + let _s3363_ := _s3362_ in + (if ((string_startswith _s3363_ "c.jalr")) then + (match (string_drop _s3363_ (projT1 (string_length "c.jalr"))) with + | _s3364_ => + (spc_matches_prefix _s3364_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3365_ _)) => + (match (string_drop _s3364_ _s3365_) with + | _s3366_ => + (reg_name_matches_prefix _s3366_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (rs1,(existT _ _s3367_ _)) => + match (string_drop _s3366_ _s3367_) with | s_ => Some ((rs1, s_)) end + | _ => None + end) + : option ((mword 5 * string))) + end) + : M (option ((mword 5 * string))) + | _ => returnm (None : option ((mword 5 * string))) + end) + : M (option ((mword 5 * string))) + end) + : M (option ((mword 5 * string))) + else returnm (None : option ((mword 5 * string)))) + : M (option ((mword 5 * string))). + +Definition _s3353_ (_s3354_ : string) +: M (option ((mword 5 * string))) := + + let _s3355_ := _s3354_ in + (if ((string_startswith _s3355_ "c.jr")) then + (match (string_drop _s3355_ (projT1 (string_length "c.jr"))) with + | _s3356_ => + (spc_matches_prefix _s3356_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3357_ _)) => + (match (string_drop _s3356_ _s3357_) with + | _s3358_ => + (reg_name_matches_prefix _s3358_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__1 with + | Some (rs1,(existT _ _s3359_ _)) => + match (string_drop _s3358_ _s3359_) with | s_ => Some ((rs1, s_)) end + | _ => None + end) + : option ((mword 5 * string))) + end) + : M (option ((mword 5 * string))) + | _ => returnm (None : option ((mword 5 * string))) + end) + : M (option ((mword 5 * string))) + end) + : M (option ((mword 5 * string))) + else returnm (None : option ((mword 5 * string)))) + : M (option ((mword 5 * string))). + +Definition _s3341_ (_s3342_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3343_ := _s3342_ in + (if ((string_startswith _s3343_ "c.sdsp")) then + (match (string_drop _s3343_ (projT1 (string_length "c.sdsp"))) with + | _s3344_ => + (spc_matches_prefix _s3344_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3345_ _)) => + (match (string_drop _s3344_ _s3345_) with + | _s3346_ => + (reg_name_matches_prefix _s3346_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs2,(existT _ _s3347_ _)) => + (match (string_drop _s3346_ _s3347_) with + | _s3348_ => + (sep_matches_prefix _s3348_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3349_ _)) => + match (string_drop _s3348_ _s3349_) with + | _s3350_ => + match (hex_bits_6_matches_prefix _s3350_) with + | Some (uimm,(existT _ _s3351_ _)) => + match (string_drop _s3350_ _s3351_) with + | s_ => Some ((rs2, uimm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3329_ (_s3330_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3331_ := _s3330_ in + (if ((string_startswith _s3331_ "c.swsp")) then + (match (string_drop _s3331_ (projT1 (string_length "c.swsp"))) with + | _s3332_ => + (spc_matches_prefix _s3332_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3333_ _)) => + (match (string_drop _s3332_ _s3333_) with + | _s3334_ => + (reg_name_matches_prefix _s3334_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s3335_ _)) => + (match (string_drop _s3334_ _s3335_) with + | _s3336_ => + (sep_matches_prefix _s3336_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3337_ _)) => + match (string_drop _s3336_ _s3337_) with + | _s3338_ => + match (hex_bits_6_matches_prefix _s3338_) with + | Some (uimm,(existT _ _s3339_ _)) => + match (string_drop _s3338_ _s3339_) with + | s_ => Some ((rd, uimm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3317_ (_s3318_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3319_ := _s3318_ in + (if ((string_startswith _s3319_ "c.ldsp")) then + (match (string_drop _s3319_ (projT1 (string_length "c.ldsp"))) with + | _s3320_ => + (spc_matches_prefix _s3320_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3321_ _)) => + (match (string_drop _s3320_ _s3321_) with + | _s3322_ => + (reg_name_matches_prefix _s3322_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s3323_ _)) => + (match (string_drop _s3322_ _s3323_) with + | _s3324_ => + (sep_matches_prefix _s3324_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3325_ _)) => + match (string_drop _s3324_ _s3325_) with + | _s3326_ => + match (hex_bits_6_matches_prefix _s3326_) with + | Some (uimm,(existT _ _s3327_ _)) => + match (string_drop _s3326_ _s3327_) with + | s_ => Some ((rd, uimm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3305_ (_s3306_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3307_ := _s3306_ in + (if ((string_startswith _s3307_ "c.lwsp")) then + (match (string_drop _s3307_ (projT1 (string_length "c.lwsp"))) with + | _s3308_ => + (spc_matches_prefix _s3308_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3309_ _)) => + (match (string_drop _s3308_ _s3309_) with + | _s3310_ => + (reg_name_matches_prefix _s3310_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s3311_ _)) => + (match (string_drop _s3310_ _s3311_) with + | _s3312_ => + (sep_matches_prefix _s3312_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3313_ _)) => + match (string_drop _s3312_ _s3313_) with + | _s3314_ => + match (hex_bits_6_matches_prefix _s3314_) with + | Some (uimm,(existT _ _s3315_ _)) => + match (string_drop _s3314_ _s3315_) with + | s_ => Some ((rd, uimm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3293_ (_s3294_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3295_ := _s3294_ in + (if ((string_startswith _s3295_ "c.slli")) then + (match (string_drop _s3295_ (projT1 (string_length "c.slli"))) with + | _s3296_ => + (spc_matches_prefix _s3296_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3297_ _)) => + (match (string_drop _s3296_ _s3297_) with + | _s3298_ => + (reg_name_matches_prefix _s3298_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3299_ _)) => + (match (string_drop _s3298_ _s3299_) with + | _s3300_ => + (sep_matches_prefix _s3300_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3301_ _)) => + match (string_drop _s3300_ _s3301_) with + | _s3302_ => + match (hex_bits_6_matches_prefix _s3302_) with + | Some (shamt,(existT _ _s3303_ _)) => + match (string_drop _s3302_ _s3303_) with + | s_ => Some ((rsd, shamt, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3281_ (_s3282_ : string) +: M (option ((mword 3 * mword 8 * string))) := + + let _s3283_ := _s3282_ in + (if ((string_startswith _s3283_ "c.bnez")) then + (match (string_drop _s3283_ (projT1 (string_length "c.bnez"))) with + | _s3284_ => + (spc_matches_prefix _s3284_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3285_ _)) => + (match (string_drop _s3284_ _s3285_) with + | _s3286_ => + (creg_name_matches_prefix _s3286_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs,(existT _ _s3287_ _)) => + (match (string_drop _s3286_ _s3287_) with + | _s3288_ => + (sep_matches_prefix _s3288_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3289_ _)) => + match (string_drop _s3288_ _s3289_) with + | _s3290_ => + match (hex_bits_8_matches_prefix _s3290_) with + | Some (imm,(existT _ _s3291_ _)) => + match (string_drop _s3290_ _s3291_) with + | s_ => Some ((rs, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + | _ => returnm (None : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + | _ => returnm (None : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + else returnm (None : option ((mword 3 * mword 8 * string)))) + : M (option ((mword 3 * mword 8 * string))). + +Definition _s3269_ (_s3270_ : string) +: M (option ((mword 3 * mword 8 * string))) := + + let _s3271_ := _s3270_ in + (if ((string_startswith _s3271_ "c.beqz")) then + (match (string_drop _s3271_ (projT1 (string_length "c.beqz"))) with + | _s3272_ => + (spc_matches_prefix _s3272_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3273_ _)) => + (match (string_drop _s3272_ _s3273_) with + | _s3274_ => + (creg_name_matches_prefix _s3274_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs,(existT _ _s3275_ _)) => + (match (string_drop _s3274_ _s3275_) with + | _s3276_ => + (sep_matches_prefix _s3276_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3277_ _)) => + match (string_drop _s3276_ _s3277_) with + | _s3278_ => + match (hex_bits_8_matches_prefix _s3278_) with + | Some (imm,(existT _ _s3279_ _)) => + match (string_drop _s3278_ _s3279_) with + | s_ => Some ((rs, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + | _ => returnm (None : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + | _ => returnm (None : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + else returnm (None : option ((mword 3 * mword 8 * string)))) + : M (option ((mword 3 * mword 8 * string))). + +Definition _s3261_ (_s3262_ : string) +: M (option ((mword 11 * string))) := + + let _s3263_ := _s3262_ in + (if ((string_startswith _s3263_ "c.j")) then + (match (string_drop _s3263_ (projT1 (string_length "c.j"))) with + | _s3264_ => + (spc_matches_prefix _s3264_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s3265_ _)) => + match (string_drop _s3264_ _s3265_) with + | _s3266_ => + match (hex_bits_11_matches_prefix _s3266_) with + | Some (imm,(existT _ _s3267_ _)) => + match (string_drop _s3266_ _s3267_) with | s_ => Some ((imm, s_)) end + | _ => None + end + end + | _ => None + end) + : option ((mword 11 * string))) + end) + : M (option ((mword 11 * string))) + else returnm (None : option ((mword 11 * string)))) + : M (option ((mword 11 * string))). + +Definition _s3249_ (_s3250_ : string) +: M (option ((mword 3 * mword 3 * string))) := + + let _s3251_ := _s3250_ in + (if ((string_startswith _s3251_ "c.addw")) then + (match (string_drop _s3251_ (projT1 (string_length "c.addw"))) with + | _s3252_ => + (spc_matches_prefix _s3252_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3253_ _)) => + (match (string_drop _s3252_ _s3253_) with + | _s3254_ => + (creg_name_matches_prefix _s3254_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3255_ _)) => + (match (string_drop _s3254_ _s3255_) with + | _s3256_ => + (sep_matches_prefix _s3256_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3257_ _)) => + (match (string_drop _s3256_ _s3257_) with + | _s3258_ => + (creg_name_matches_prefix _s3258_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3259_ _)) => + match (string_drop _s3258_ _s3259_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + else returnm (None : option ((mword 3 * mword 3 * string)))) + : M (option ((mword 3 * mword 3 * string))). + +Definition _s3237_ (_s3238_ : string) +: M (option ((mword 3 * mword 3 * string))) := + + let _s3239_ := _s3238_ in + (if ((string_startswith _s3239_ "c.subw")) then + (match (string_drop _s3239_ (projT1 (string_length "c.subw"))) with + | _s3240_ => + (spc_matches_prefix _s3240_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3241_ _)) => + (match (string_drop _s3240_ _s3241_) with + | _s3242_ => + (creg_name_matches_prefix _s3242_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3243_ _)) => + (match (string_drop _s3242_ _s3243_) with + | _s3244_ => + (sep_matches_prefix _s3244_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3245_ _)) => + (match (string_drop _s3244_ _s3245_) with + | _s3246_ => + (creg_name_matches_prefix _s3246_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3247_ _)) => + match (string_drop _s3246_ _s3247_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + else returnm (None : option ((mword 3 * mword 3 * string)))) + : M (option ((mword 3 * mword 3 * string))). + +Definition _s3225_ (_s3226_ : string) +: M (option ((mword 3 * mword 3 * string))) := + + let _s3227_ := _s3226_ in + (if ((string_startswith _s3227_ "c.and")) then + (match (string_drop _s3227_ (projT1 (string_length "c.and"))) with + | _s3228_ => + (spc_matches_prefix _s3228_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3229_ _)) => + (match (string_drop _s3228_ _s3229_) with + | _s3230_ => + (creg_name_matches_prefix _s3230_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3231_ _)) => + (match (string_drop _s3230_ _s3231_) with + | _s3232_ => + (sep_matches_prefix _s3232_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3233_ _)) => + (match (string_drop _s3232_ _s3233_) with + | _s3234_ => + (creg_name_matches_prefix _s3234_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3235_ _)) => + match (string_drop _s3234_ _s3235_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + else returnm (None : option ((mword 3 * mword 3 * string)))) + : M (option ((mword 3 * mword 3 * string))). + +Definition _s3213_ (_s3214_ : string) +: M (option ((mword 3 * mword 3 * string))) := + + let _s3215_ := _s3214_ in + (if ((string_startswith _s3215_ "c.or")) then + (match (string_drop _s3215_ (projT1 (string_length "c.or"))) with + | _s3216_ => + (spc_matches_prefix _s3216_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3217_ _)) => + (match (string_drop _s3216_ _s3217_) with + | _s3218_ => + (creg_name_matches_prefix _s3218_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3219_ _)) => + (match (string_drop _s3218_ _s3219_) with + | _s3220_ => + (sep_matches_prefix _s3220_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3221_ _)) => + (match (string_drop _s3220_ _s3221_) with + | _s3222_ => + (creg_name_matches_prefix _s3222_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3223_ _)) => + match (string_drop _s3222_ _s3223_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + else returnm (None : option ((mword 3 * mword 3 * string)))) + : M (option ((mword 3 * mword 3 * string))). + +Definition _s3201_ (_s3202_ : string) +: M (option ((mword 3 * mword 3 * string))) := + + let _s3203_ := _s3202_ in + (if ((string_startswith _s3203_ "c.xor")) then + (match (string_drop _s3203_ (projT1 (string_length "c.xor"))) with + | _s3204_ => + (spc_matches_prefix _s3204_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3205_ _)) => + (match (string_drop _s3204_ _s3205_) with + | _s3206_ => + (creg_name_matches_prefix _s3206_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3207_ _)) => + (match (string_drop _s3206_ _s3207_) with + | _s3208_ => + (sep_matches_prefix _s3208_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3209_ _)) => + (match (string_drop _s3208_ _s3209_) with + | _s3210_ => + (creg_name_matches_prefix _s3210_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3211_ _)) => + match (string_drop _s3210_ _s3211_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + else returnm (None : option ((mword 3 * mword 3 * string)))) + : M (option ((mword 3 * mword 3 * string))). + +Definition _s3189_ (_s3190_ : string) +: M (option ((mword 3 * mword 3 * string))) := + + let _s3191_ := _s3190_ in + (if ((string_startswith _s3191_ "c.sub")) then + (match (string_drop _s3191_ (projT1 (string_length "c.sub"))) with + | _s3192_ => + (spc_matches_prefix _s3192_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3193_ _)) => + (match (string_drop _s3192_ _s3193_) with + | _s3194_ => + (creg_name_matches_prefix _s3194_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3195_ _)) => + (match (string_drop _s3194_ _s3195_) with + | _s3196_ => + (sep_matches_prefix _s3196_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3197_ _)) => + (match (string_drop _s3196_ _s3197_) with + | _s3198_ => + (creg_name_matches_prefix _s3198_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s3199_ _)) => + match (string_drop _s3198_ _s3199_) with + | s_ => Some ((rsd, rs2, s_)) + end + | _ => None + end) + : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + end) + : M (option ((mword 3 * mword 3 * string))) + else returnm (None : option ((mword 3 * mword 3 * string)))) + : M (option ((mword 3 * mword 3 * string))). + +Definition _s3177_ (_s3178_ : string) +: M (option ((mword 3 * mword 6 * string))) := + + let _s3179_ := _s3178_ in + (if ((string_startswith _s3179_ "c.andi")) then + (match (string_drop _s3179_ (projT1 (string_length "c.andi"))) with + | _s3180_ => + (spc_matches_prefix _s3180_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3181_ _)) => + (match (string_drop _s3180_ _s3181_) with + | _s3182_ => + (creg_name_matches_prefix _s3182_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3183_ _)) => + (match (string_drop _s3182_ _s3183_) with + | _s3184_ => + (sep_matches_prefix _s3184_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3185_ _)) => + match (string_drop _s3184_ _s3185_) with + | _s3186_ => + match (hex_bits_6_matches_prefix _s3186_) with + | Some (imm,(existT _ _s3187_ _)) => + match (string_drop _s3186_ _s3187_) with + | s_ => Some ((rsd, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + | _ => returnm (None : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + | _ => returnm (None : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + else returnm (None : option ((mword 3 * mword 6 * string)))) + : M (option ((mword 3 * mword 6 * string))). + +Definition _s3165_ (_s3166_ : string) +: M (option ((mword 3 * mword 6 * string))) := + + let _s3167_ := _s3166_ in + (if ((string_startswith _s3167_ "c.srai")) then + (match (string_drop _s3167_ (projT1 (string_length "c.srai"))) with + | _s3168_ => + (spc_matches_prefix _s3168_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3169_ _)) => + (match (string_drop _s3168_ _s3169_) with + | _s3170_ => + (creg_name_matches_prefix _s3170_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3171_ _)) => + (match (string_drop _s3170_ _s3171_) with + | _s3172_ => + (sep_matches_prefix _s3172_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3173_ _)) => + match (string_drop _s3172_ _s3173_) with + | _s3174_ => + match (hex_bits_6_matches_prefix _s3174_) with + | Some (shamt,(existT _ _s3175_ _)) => + match (string_drop _s3174_ _s3175_) with + | s_ => Some ((rsd, shamt, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + | _ => returnm (None : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + | _ => returnm (None : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + else returnm (None : option ((mword 3 * mword 6 * string)))) + : M (option ((mword 3 * mword 6 * string))). + +Definition _s3153_ (_s3154_ : string) +: M (option ((mword 3 * mword 6 * string))) := + + let _s3155_ := _s3154_ in + (if ((string_startswith _s3155_ "c.srli")) then + (match (string_drop _s3155_ (projT1 (string_length "c.srli"))) with + | _s3156_ => + (spc_matches_prefix _s3156_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3157_ _)) => + (match (string_drop _s3156_ _s3157_) with + | _s3158_ => + (creg_name_matches_prefix _s3158_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3159_ _)) => + (match (string_drop _s3158_ _s3159_) with + | _s3160_ => + (sep_matches_prefix _s3160_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3161_ _)) => + match (string_drop _s3160_ _s3161_) with + | _s3162_ => + match (hex_bits_6_matches_prefix _s3162_) with + | Some (shamt,(existT _ _s3163_ _)) => + match (string_drop _s3162_ _s3163_) with + | s_ => Some ((rsd, shamt, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + | _ => returnm (None : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + | _ => returnm (None : option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + end) + : M (option ((mword 3 * mword 6 * string))) + else returnm (None : option ((mword 3 * mword 6 * string)))) + : M (option ((mword 3 * mword 6 * string))). + +Definition _s3141_ (_s3142_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3143_ := _s3142_ in + (if ((string_startswith _s3143_ "c.lui")) then + (match (string_drop _s3143_ (projT1 (string_length "c.lui"))) with + | _s3144_ => + (spc_matches_prefix _s3144_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3145_ _)) => + (match (string_drop _s3144_ _s3145_) with + | _s3146_ => + (reg_name_matches_prefix _s3146_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s3147_ _)) => + (match (string_drop _s3146_ _s3147_) with + | _s3148_ => + (sep_matches_prefix _s3148_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3149_ _)) => + match (string_drop _s3148_ _s3149_) with + | _s3150_ => + match (hex_bits_6_matches_prefix _s3150_) with + | Some (imm,(existT _ _s3151_ _)) => + match (string_drop _s3150_ _s3151_) with + | s_ => Some ((rd, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3133_ (_s3134_ : string) +: M (option ((mword 6 * string))) := + + let _s3135_ := _s3134_ in + (if ((string_startswith _s3135_ "c.addi16sp")) then + (match (string_drop _s3135_ (projT1 (string_length "c.addi16sp"))) with + | _s3136_ => + (spc_matches_prefix _s3136_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s3137_ _)) => + match (string_drop _s3136_ _s3137_) with + | _s3138_ => + match (hex_bits_6_matches_prefix _s3138_) with + | Some (imm,(existT _ _s3139_ _)) => + match (string_drop _s3138_ _s3139_) with | s_ => Some ((imm, s_)) end + | _ => None + end + end + | _ => None + end) + : option ((mword 6 * string))) + end) + : M (option ((mword 6 * string))) + else returnm (None : option ((mword 6 * string)))) + : M (option ((mword 6 * string))). + +Definition _s3121_ (_s3122_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3123_ := _s3122_ in + (if ((string_startswith _s3123_ "c.li")) then + (match (string_drop _s3123_ (projT1 (string_length "c.li"))) with + | _s3124_ => + (spc_matches_prefix _s3124_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3125_ _)) => + (match (string_drop _s3124_ _s3125_) with + | _s3126_ => + (reg_name_matches_prefix _s3126_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s3127_ _)) => + (match (string_drop _s3126_ _s3127_) with + | _s3128_ => + (sep_matches_prefix _s3128_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3129_ _)) => + match (string_drop _s3128_ _s3129_) with + | _s3130_ => + match (hex_bits_6_matches_prefix _s3130_) with + | Some (imm,(existT _ _s3131_ _)) => + match (string_drop _s3130_ _s3131_) with + | s_ => Some ((rd, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3109_ (_s3110_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3111_ := _s3110_ in + (if ((string_startswith _s3111_ "c.addiw")) then + (match (string_drop _s3111_ (projT1 (string_length "c.addiw"))) with + | _s3112_ => + (spc_matches_prefix _s3112_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3113_ _)) => + (match (string_drop _s3112_ _s3113_) with + | _s3114_ => + (reg_name_matches_prefix _s3114_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3115_ _)) => + (match (string_drop _s3114_ _s3115_) with + | _s3116_ => + (sep_matches_prefix _s3116_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3117_ _)) => + match (string_drop _s3116_ _s3117_) with + | _s3118_ => + match (hex_bits_6_matches_prefix _s3118_) with + | Some (imm,(existT _ _s3119_ _)) => + match (string_drop _s3118_ _s3119_) with + | s_ => Some ((rsd, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3101_ (_s3102_ : string) +: M (option ((mword 11 * string))) := + + let _s3103_ := _s3102_ in + (if ((string_startswith _s3103_ "c.jal")) then + (match (string_drop _s3103_ (projT1 (string_length "c.jal"))) with + | _s3104_ => + (spc_matches_prefix _s3104_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + returnm ((match w__0 with + | Some (tt,(existT _ _s3105_ _)) => + match (string_drop _s3104_ _s3105_) with + | _s3106_ => + match (hex_bits_12_matches_prefix _s3106_) with + | Some (v__784,(existT _ _s3107_ _)) => + if ((eq_vec (subrange_vec_dec v__784 0 0) + (vec_of_bits [B0] : mword (0 - 0 + 1)))) then + let imm : mword 11 := subrange_vec_dec v__784 11 1 in + let imm : mword 11 := subrange_vec_dec v__784 11 1 in + match (string_drop _s3106_ _s3107_) with | s_ => Some ((imm, s_)) end + else + let g__21 := Some ((v__784, _s3107_)) in + None + | g__21 => None + end + end + | _ => None + end) + : option ((mword 11 * string))) + end) + : M (option ((mword 11 * string))) + else returnm (None : option ((mword 11 * string)))) + : M (option ((mword 11 * string))). + +Definition _s3089_ (_s3090_ : string) +: M (option ((mword 5 * mword 6 * string))) := + + let _s3091_ := _s3090_ in + (if ((string_startswith _s3091_ "c.addi")) then + (match (string_drop _s3091_ (projT1 (string_length "c.addi"))) with + | _s3092_ => + (spc_matches_prefix _s3092_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3093_ _)) => + (match (string_drop _s3092_ _s3093_) with + | _s3094_ => + (reg_name_matches_prefix _s3094_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsd,(existT _ _s3095_ _)) => + (match (string_drop _s3094_ _s3095_) with + | _s3096_ => + (sep_matches_prefix _s3096_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3097_ _)) => + match (string_drop _s3096_ _s3097_) with + | _s3098_ => + match (hex_bits_6_matches_prefix _s3098_) with + | Some (nzi,(existT _ _s3099_ _)) => + match (string_drop _s3098_ _s3099_) with + | s_ => Some ((rsd, nzi, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + | _ => returnm (None : option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + end) + : M (option ((mword 5 * mword 6 * string))) + else returnm (None : option ((mword 5 * mword 6 * string)))) + : M (option ((mword 5 * mword 6 * string))). + +Definition _s3073_ (_s3074_ : string) +: M (option ((mword 3 * mword 3 * mword 5 * string))) := + + let _s3075_ := _s3074_ in + (if ((string_startswith _s3075_ "c.sd")) then + (match (string_drop _s3075_ (projT1 (string_length "c.sd"))) with + | _s3076_ => + (spc_matches_prefix _s3076_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3077_ _)) => + (match (string_drop _s3076_ _s3077_) with + | _s3078_ => + (creg_name_matches_prefix _s3078_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsc1,(existT _ _s3079_ _)) => + (match (string_drop _s3078_ _s3079_) with + | _s3080_ => + (sep_matches_prefix _s3080_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3081_ _)) => + (match (string_drop _s3080_ _s3081_) with + | _s3082_ => + (creg_name_matches_prefix _s3082_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc2,(existT _ _s3083_ _)) => + (match (string_drop _s3082_ _s3083_) with + | _s3084_ => + (sep_matches_prefix _s3084_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s3085_ _)) => + match (string_drop _s3084_ _s3085_) with + | _s3086_ => + match (hex_bits_8_matches_prefix _s3086_) with + | Some (v__786,(existT _ _s3087_ _)) => + if ((eq_vec + (subrange_vec_dec v__786 2 0) + (vec_of_bits [B0;B0;B0] + : mword (2 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__786 7 3 in + let uimm : mword 5 := + subrange_vec_dec v__786 7 3 in + match (string_drop _s3086_ _s3087_) with + | s_ => Some ((rsc1, rsc2, uimm, s_)) + end + else + let g__20 := Some ((v__786, _s3087_)) in + None + | g__20 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => + returnm (None + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + else returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))) + : M (option ((mword 3 * mword 3 * mword 5 * string))). + +Definition _s3057_ (_s3058_ : string) +: M (option ((mword 3 * mword 3 * mword 5 * string))) := + + let _s3059_ := _s3058_ in + (if ((string_startswith _s3059_ "c.sw")) then + (match (string_drop _s3059_ (projT1 (string_length "c.sw"))) with + | _s3060_ => + (spc_matches_prefix _s3060_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3061_ _)) => + (match (string_drop _s3060_ _s3061_) with + | _s3062_ => + (creg_name_matches_prefix _s3062_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rsc1,(existT _ _s3063_ _)) => + (match (string_drop _s3062_ _s3063_) with + | _s3064_ => + (sep_matches_prefix _s3064_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3065_ _)) => + (match (string_drop _s3064_ _s3065_) with + | _s3066_ => + (creg_name_matches_prefix _s3066_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc2,(existT _ _s3067_ _)) => + (match (string_drop _s3066_ _s3067_) with + | _s3068_ => + (sep_matches_prefix _s3068_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s3069_ _)) => + match (string_drop _s3068_ _s3069_) with + | _s3070_ => + match (hex_bits_7_matches_prefix _s3070_) with + | Some (v__788,(existT _ _s3071_ _)) => + if ((eq_vec + (subrange_vec_dec v__788 1 0) + (vec_of_bits [B0;B0] + : mword (1 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__788 6 2 in + let uimm : mword 5 := + subrange_vec_dec v__788 6 2 in + match (string_drop _s3070_ _s3071_) with + | s_ => Some ((rsc1, rsc2, uimm, s_)) + end + else + let g__19 := Some ((v__788, _s3071_)) in + None + | g__19 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => + returnm (None + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + else returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))) + : M (option ((mword 3 * mword 3 * mword 5 * string))). + +Definition _s3041_ (_s3042_ : string) +: M (option ((mword 3 * mword 3 * mword 5 * string))) := + + let _s3043_ := _s3042_ in + (if ((string_startswith _s3043_ "c.ld")) then + (match (string_drop _s3043_ (projT1 (string_length "c.ld"))) with + | _s3044_ => + (spc_matches_prefix _s3044_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3045_ _)) => + (match (string_drop _s3044_ _s3045_) with + | _s3046_ => + (creg_name_matches_prefix _s3046_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s3047_ _)) => + (match (string_drop _s3046_ _s3047_) with + | _s3048_ => + (sep_matches_prefix _s3048_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3049_ _)) => + (match (string_drop _s3048_ _s3049_) with + | _s3050_ => + (creg_name_matches_prefix _s3050_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc,(existT _ _s3051_ _)) => + (match (string_drop _s3050_ _s3051_) with + | _s3052_ => + (sep_matches_prefix _s3052_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s3053_ _)) => + match (string_drop _s3052_ _s3053_) with + | _s3054_ => + match (hex_bits_8_matches_prefix _s3054_) with + | Some (v__790,(existT _ _s3055_ _)) => + if ((eq_vec + (subrange_vec_dec v__790 2 0) + (vec_of_bits [B0;B0;B0] + : mword (2 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__790 7 3 in + let uimm : mword 5 := + subrange_vec_dec v__790 7 3 in + match (string_drop _s3054_ _s3055_) with + | s_ => Some ((rdc, rsc, uimm, s_)) + end + else + let g__18 := Some ((v__790, _s3055_)) in + None + | g__18 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => + returnm (None + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + else returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))) + : M (option ((mword 3 * mword 3 * mword 5 * string))). + +Definition _s3025_ (_s3026_ : string) +: M (option ((mword 3 * mword 3 * mword 5 * string))) := + + let _s3027_ := _s3026_ in + (if ((string_startswith _s3027_ "c.lw")) then + (match (string_drop _s3027_ (projT1 (string_length "c.lw"))) with + | _s3028_ => + (spc_matches_prefix _s3028_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3029_ _)) => + (match (string_drop _s3028_ _s3029_) with + | _s3030_ => + (creg_name_matches_prefix _s3030_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s3031_ _)) => + (match (string_drop _s3030_ _s3031_) with + | _s3032_ => + (sep_matches_prefix _s3032_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s3033_ _)) => + (match (string_drop _s3032_ _s3033_) with + | _s3034_ => + (creg_name_matches_prefix _s3034_) >>= fun w__3 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rsc,(existT _ _s3035_ _)) => + (match (string_drop _s3034_ _s3035_) with + | _s3036_ => + (sep_matches_prefix _s3036_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s3037_ _)) => + match (string_drop _s3036_ _s3037_) with + | _s3038_ => + match (hex_bits_7_matches_prefix _s3038_) with + | Some (v__792,(existT _ _s3039_ _)) => + if ((eq_vec + (subrange_vec_dec v__792 1 0) + (vec_of_bits [B0;B0] + : mword (1 - 0 + 1)))) then + let uimm : mword 5 := + subrange_vec_dec v__792 6 2 in + let uimm : mword 5 := + subrange_vec_dec v__792 6 2 in + match (string_drop _s3038_ _s3039_) with + | s_ => Some ((rdc, rsc, uimm, s_)) + end + else + let g__17 := Some ((v__792, _s3039_)) in + None + | g__17 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => + returnm (None + : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + | _ => returnm (None : option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + end) + : M (option ((mword 3 * mword 3 * mword 5 * string))) + else returnm (None : option ((mword 3 * mword 3 * mword 5 * string)))) + : M (option ((mword 3 * mword 3 * mword 5 * string))). + +Definition _s3013_ (_s3014_ : string) +: M (option ((mword 3 * mword 8 * string))) := + + let _s3015_ := _s3014_ in + (if ((string_startswith _s3015_ "c.addi4spn")) then + (match (string_drop _s3015_ (projT1 (string_length "c.addi4spn"))) with + | _s3016_ => + (spc_matches_prefix _s3016_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s3017_ _)) => + (match (string_drop _s3016_ _s3017_) with + | _s3018_ => + (creg_name_matches_prefix _s3018_) >>= fun w__1 : option ((mword 3 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rdc,(existT _ _s3019_ _)) => + (match (string_drop _s3018_ _s3019_) with + | _s3020_ => + (sep_matches_prefix _s3020_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s3021_ _)) => + match (string_drop _s3020_ _s3021_) with + | _s3022_ => + match (hex_bits_10_matches_prefix _s3022_) with + | Some (v__794,(existT _ _s3023_ _)) => + if ((eq_vec (subrange_vec_dec v__794 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1)))) + then + let nzimm : mword 8 := subrange_vec_dec v__794 9 2 in + let nzimm : mword 8 := subrange_vec_dec v__794 9 2 in + match (string_drop _s3022_ _s3023_) with + | s_ => Some ((rdc, nzimm, s_)) + end + else + let g__16 := Some ((v__794, _s3023_)) in + None + | g__16 => None + end + end + | _ => None + end) + : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + | _ => returnm (None : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + | _ => returnm (None : option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + end) + : M (option ((mword 3 * mword 8 * string))) + else returnm (None : option ((mword 3 * mword 8 * string)))) + : M (option ((mword 3 * mword 8 * string))). + +Definition _s3009_ (_s3010_ : string) +: option string := + + let _s3011_ := _s3010_ in + if ((string_startswith _s3011_ "c.nop")) then + match (string_drop _s3011_ (projT1 (string_length "c.nop"))) with | s_ => Some (s_) end + else None. + +Definition _s2992_ (_s2993_ : string) +: M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) := + + (match _s2993_ with + | _s2994_ => + (csr_mnemonic_matches_prefix _s2994_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2995_ _)) => + (match (string_drop _s2994_ _s2995_) with + | _s2996_ => + (spc_matches_prefix _s2996_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2997_ _)) => + (match (string_drop _s2996_ _s2997_) with + | _s2998_ => + (reg_name_matches_prefix _s2998_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2999_ _)) => + (match (string_drop _s2998_ _s2999_) with + | _s3000_ => + (sep_matches_prefix _s3000_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s3001_ _)) => + (match (string_drop _s3000_ _s3001_) with + | _s3002_ => + (reg_name_matches_prefix _s3002_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s3003_ _)) => + (match (string_drop _s3002_ _s3003_) with + | _s3004_ => + (sep_matches_prefix _s3004_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s3005_ _)) => + (match (string_drop _s3004_ _s3005_) with + | _s3006_ => + (csr_name_map_matches_prefix _s3006_) >>= fun w__6 : option ((mword 12 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (csr,(existT _ _s3007_ _)) => + match (string_drop _s3006_ + _s3007_) with + | s_ => + Some ((op, rd, rs1, csr, s_)) + end + | _ => None + end) + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))). + +Definition _s2974_ (_s2975_ : string) +: M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) := + + (match _s2975_ with + | _s2976_ => + (csr_mnemonic_matches_prefix _s2976_) >>= fun w__0 : option ((csrop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2977_ _)) => + let _s2978_ := string_drop _s2976_ _s2977_ in + (if ((string_startswith _s2978_ "i")) then + (match (string_drop _s2978_ (projT1 (string_length "i"))) with + | _s2979_ => + (spc_matches_prefix _s2979_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2980_ _)) => + (match (string_drop _s2979_ _s2980_) with + | _s2981_ => + (reg_name_matches_prefix _s2981_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2982_ _)) => + (match (string_drop _s2981_ _s2982_) with + | _s2983_ => + (sep_matches_prefix _s2983_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2984_ _)) => + (match (string_drop _s2983_ _s2984_) with + | _s2985_ => + (match (hex_bits_5_matches_prefix _s2985_) with + | Some (rs1,(existT _ _s2986_ _)) => + (match (string_drop _s2985_ _s2986_) with + | _s2987_ => + (sep_matches_prefix _s2987_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s2988_ _)) => + (match (string_drop _s2987_ _s2988_) with + | _s2989_ => + (csr_name_map_matches_prefix _s2989_) >>= fun w__5 : option ((mword 12 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some + (csr,(existT _ _s2990_ _)) => + match (string_drop _s2989_ + _s2990_) with + | s_ => + Some + ((op, rd, rs1, csr, s_)) + end + | _ => None + end) + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + else returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string)))) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((csrop * mword 5 * mword 5 * mword 12 * string))). + +Definition _s2950_ (_s2951_ : string) +: M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) := + + (match _s2951_ with + | _s2952_ => + (amo_mnemonic_matches_prefix _s2952_) >>= fun w__0 : option ((amoop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2953_ _)) => + let _s2954_ := string_drop _s2952_ _s2953_ in + (if ((string_startswith _s2954_ ".")) then + (match (string_drop _s2954_ (projT1 (string_length "."))) with + | _s2955_ => + (size_mnemonic_matches_prefix _s2955_) >>= fun w__1 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (width,(existT _ _s2956_ _)) => + (match (string_drop _s2955_ _s2956_) with + | _s2957_ => + (maybe_aq_matches_prefix _s2957_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (aq,(existT _ _s2958_ _)) => + (match (string_drop _s2957_ _s2958_) with + | _s2959_ => + (maybe_rl_matches_prefix _s2959_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rl,(existT _ _s2960_ _)) => + (match (string_drop _s2959_ _s2960_) with + | _s2961_ => + (spc_matches_prefix _s2961_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s2962_ _)) => + (match (string_drop _s2961_ _s2962_) with + | _s2963_ => + (reg_name_matches_prefix _s2963_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (rd,(existT _ _s2964_ _)) => + (match (string_drop _s2963_ _s2964_) with + | _s2965_ => + (sep_matches_prefix _s2965_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (tt,(existT _ _s2966_ _)) => + (match (string_drop _s2965_ _s2966_) with + | _s2967_ => + (reg_name_matches_prefix _s2967_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (rs1,(existT _ _s2968_ _)) => + (match (string_drop _s2967_ + _s2968_) with + | _s2969_ => + (sep_matches_prefix + _s2969_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__8 with + | Some + (tt,(existT _ _s2970_ _)) => + (match (string_drop + _s2969_ + _s2970_) with + | _s2971_ => + (reg_name_matches_prefix + _s2971_) >>= fun w__9 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__9 with + | Some + (rs2,(existT _ _s2972_ _)) => + match (string_drop + _s2971_ + _s2972_) with + | s_ => + Some + ((op, width, aq, rl, rd, rs1, rs2, s_)) + end + | _ => + None + end) + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + else + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2928_ (_s2929_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) := + + let _s2930_ := _s2929_ in + (if ((string_startswith _s2930_ "sc.")) then + (match (string_drop _s2930_ (projT1 (string_length "sc."))) with + | _s2931_ => + (size_mnemonic_matches_prefix _s2931_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s2932_ _)) => + (match (string_drop _s2931_ _s2932_) with + | _s2933_ => + (maybe_aq_matches_prefix _s2933_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s2934_ _)) => + (match (string_drop _s2933_ _s2934_) with + | _s2935_ => + (maybe_rl_matches_prefix _s2935_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s2936_ _)) => + (match (string_drop _s2935_ _s2936_) with + | _s2937_ => + (spc_matches_prefix _s2937_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2938_ _)) => + (match (string_drop _s2937_ _s2938_) with + | _s2939_ => + (reg_name_matches_prefix _s2939_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s2940_ _)) => + (match (string_drop _s2939_ _s2940_) with + | _s2941_ => + (sep_matches_prefix _s2941_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2942_ _)) => + (match (string_drop _s2941_ _s2942_) with + | _s2943_ => + (reg_name_matches_prefix _s2943_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (rs1,(existT _ _s2944_ _)) => + (match (string_drop _s2943_ _s2944_) with + | _s2945_ => + (sep_matches_prefix _s2945_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (tt,(existT _ _s2946_ _)) => + (match (string_drop _s2945_ + _s2946_) with + | _s2947_ => + (reg_name_matches_prefix + _s2947_) >>= fun w__8 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__8 with + | Some + (rs2,(existT _ _s2948_ _)) => + match (string_drop + _s2947_ + _s2948_) with + | s_ => + Some + ((size, aq, rl, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))) + else + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2910_ (_s2911_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) := + + let _s2912_ := _s2911_ in + (if ((string_startswith _s2912_ "lr.")) then + (match (string_drop _s2912_ (projT1 (string_length "lr."))) with + | _s2913_ => + (size_mnemonic_matches_prefix _s2913_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s2914_ _)) => + (match (string_drop _s2913_ _s2914_) with + | _s2915_ => + (maybe_aq_matches_prefix _s2915_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s2916_ _)) => + (match (string_drop _s2915_ _s2916_) with + | _s2917_ => + (maybe_rl_matches_prefix _s2917_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s2918_ _)) => + (match (string_drop _s2917_ _s2918_) with + | _s2919_ => + (spc_matches_prefix _s2919_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2920_ _)) => + (match (string_drop _s2919_ _s2920_) with + | _s2921_ => + (reg_name_matches_prefix _s2921_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s2922_ _)) => + (match (string_drop _s2921_ _s2922_) with + | _s2923_ => + (sep_matches_prefix _s2923_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2924_ _)) => + (match (string_drop _s2923_ _s2924_) with + | _s2925_ => + (reg_name_matches_prefix _s2925_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs1,(existT _ _s2926_ _)) => + match (string_drop _s2925_ + _s2926_) with + | s_ => + Some + ((size, aq, rl, rd, rs1, s_)) + end + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))) + else returnm (None : option ((word_width * bool * bool * mword 5 * mword 5 * string)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * string))). + +Definition _s2898_ (_s2899_ : string) +: M (option ((mword 5 * mword 5 * string))) := + + let _s2900_ := _s2899_ in + (if ((string_startswith _s2900_ "sfence.vma")) then + (match (string_drop _s2900_ (projT1 (string_length "sfence.vma"))) with + | _s2901_ => + (spc_matches_prefix _s2901_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2902_ _)) => + (match (string_drop _s2901_ _s2902_) with + | _s2903_ => + (reg_name_matches_prefix _s2903_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rs1,(existT _ _s2904_ _)) => + (match (string_drop _s2903_ _s2904_) with + | _s2905_ => + (sep_matches_prefix _s2905_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2906_ _)) => + (match (string_drop _s2905_ _s2906_) with + | _s2907_ => + (reg_name_matches_prefix _s2907_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (rs2,(existT _ _s2908_ _)) => + match (string_drop _s2907_ _s2908_) with + | s_ => Some ((rs1, rs2, s_)) + end + | _ => None + end) + : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * string))) + else returnm (None : option ((mword 5 * mword 5 * string)))) + : M (option ((mword 5 * mword 5 * string))). + +Definition _s2894_ (_s2895_ : string) +: option string := + + let _s2896_ := _s2895_ in + if ((string_startswith _s2896_ "wfi")) then + match (string_drop _s2896_ (projT1 (string_length "wfi"))) with | s_ => Some (s_) end + else None. + +Definition _s2890_ (_s2891_ : string) +: option string := + + let _s2892_ := _s2891_ in + if ((string_startswith _s2892_ "ebreak")) then + match (string_drop _s2892_ (projT1 (string_length "ebreak"))) with | s_ => Some (s_) end + else None. + +Definition _s2886_ (_s2887_ : string) +: option string := + + let _s2888_ := _s2887_ in + if ((string_startswith _s2888_ "sret")) then + match (string_drop _s2888_ (projT1 (string_length "sret"))) with | s_ => Some (s_) end + else None. + +Definition _s2882_ (_s2883_ : string) +: option string := + + let _s2884_ := _s2883_ in + if ((string_startswith _s2884_ "mret")) then + match (string_drop _s2884_ (projT1 (string_length "mret"))) with | s_ => Some (s_) end + else None. + +Definition _s2878_ (_s2879_ : string) +: option string := + + let _s2880_ := _s2879_ in + if ((string_startswith _s2880_ "ecall")) then + match (string_drop _s2880_ (projT1 (string_length "ecall"))) with | s_ => Some (s_) end + else None. + +Definition _s2874_ (_s2875_ : string) +: option string := + + let _s2876_ := _s2875_ in + if ((string_startswith _s2876_ "fence.i")) then + match (string_drop _s2876_ (projT1 (string_length "fence.i"))) with | s_ => Some (s_) end + else None. + +Definition _s2862_ (_s2863_ : string) +: M (option ((mword 4 * mword 4 * string))) := + + let _s2864_ := _s2863_ in + (if ((string_startswith _s2864_ "fence.tso")) then + (match (string_drop _s2864_ (projT1 (string_length "fence.tso"))) with + | _s2865_ => + (spc_matches_prefix _s2865_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2866_ _)) => + (match (string_drop _s2865_ _s2866_) with + | _s2867_ => + (fence_bits_matches_prefix _s2867_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (pred,(existT _ _s2868_ _)) => + (match (string_drop _s2867_ _s2868_) with + | _s2869_ => + (sep_matches_prefix _s2869_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2870_ _)) => + (match (string_drop _s2869_ _s2870_) with + | _s2871_ => + (fence_bits_matches_prefix _s2871_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (succ,(existT _ _s2872_ _)) => + match (string_drop _s2871_ _s2872_) with + | s_ => Some ((pred, succ, s_)) + end + | _ => None + end) + : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + | _ => returnm (None : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + | _ => returnm (None : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + | _ => returnm (None : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + else returnm (None : option ((mword 4 * mword 4 * string)))) + : M (option ((mword 4 * mword 4 * string))). + +Definition _s2850_ (_s2851_ : string) +: M (option ((mword 4 * mword 4 * string))) := + + let _s2852_ := _s2851_ in + (if ((string_startswith _s2852_ "fence")) then + (match (string_drop _s2852_ (projT1 (string_length "fence"))) with + | _s2853_ => + (spc_matches_prefix _s2853_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2854_ _)) => + (match (string_drop _s2853_ _s2854_) with + | _s2855_ => + (fence_bits_matches_prefix _s2855_) >>= fun w__1 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (pred,(existT _ _s2856_ _)) => + (match (string_drop _s2855_ _s2856_) with + | _s2857_ => + (sep_matches_prefix _s2857_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2858_ _)) => + (match (string_drop _s2857_ _s2858_) with + | _s2859_ => + (fence_bits_matches_prefix _s2859_) >>= fun w__3 : option ((mword 4 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (succ,(existT _ _s2860_ _)) => + match (string_drop _s2859_ _s2860_) with + | s_ => Some ((pred, succ, s_)) + end + | _ => None + end) + : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + | _ => returnm (None : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + | _ => returnm (None : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + | _ => returnm (None : option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + end) + : M (option ((mword 4 * mword 4 * string))) + else returnm (None : option ((mword 4 * mword 4 * string)))) + : M (option ((mword 4 * mword 4 * string))). + +Definition _s2831_ (_s2832_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) := + + let _s2833_ := _s2832_ in + (if ((string_startswith _s2833_ "rem")) then + (match (string_drop _s2833_ (projT1 (string_length "rem"))) with + | _s2834_ => + (maybe_not_u_matches_prefix _s2834_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s2835_ _)) => + let _s2836_ := string_drop _s2834_ _s2835_ in + (if ((string_startswith _s2836_ "w")) then + (match (string_drop _s2836_ (projT1 (string_length "w"))) with + | _s2837_ => + (spc_matches_prefix _s2837_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2838_ _)) => + (match (string_drop _s2837_ _s2838_) with + | _s2839_ => + (reg_name_matches_prefix _s2839_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2840_ _)) => + (match (string_drop _s2839_ _s2840_) with + | _s2841_ => + (sep_matches_prefix _s2841_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2842_ _)) => + (match (string_drop _s2841_ _s2842_) with + | _s2843_ => + (reg_name_matches_prefix _s2843_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2844_ _)) => + (match (string_drop _s2843_ _s2844_) with + | _s2845_ => + (sep_matches_prefix _s2845_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2846_ _)) => + (match (string_drop _s2845_ _s2846_) with + | _s2847_ => + (reg_name_matches_prefix _s2847_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s2848_ _)) => + match (string_drop _s2847_ + _s2848_) with + | s_ => + Some + ((s, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2812_ (_s2813_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) := + + let _s2814_ := _s2813_ in + (if ((string_startswith _s2814_ "div")) then + (match (string_drop _s2814_ (projT1 (string_length "div"))) with + | _s2815_ => + (maybe_not_u_matches_prefix _s2815_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s2816_ _)) => + let _s2817_ := string_drop _s2815_ _s2816_ in + (if ((string_startswith _s2817_ "w")) then + (match (string_drop _s2817_ (projT1 (string_length "w"))) with + | _s2818_ => + (spc_matches_prefix _s2818_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2819_ _)) => + (match (string_drop _s2818_ _s2819_) with + | _s2820_ => + (reg_name_matches_prefix _s2820_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2821_ _)) => + (match (string_drop _s2820_ _s2821_) with + | _s2822_ => + (sep_matches_prefix _s2822_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2823_ _)) => + (match (string_drop _s2822_ _s2823_) with + | _s2824_ => + (reg_name_matches_prefix _s2824_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2825_ _)) => + (match (string_drop _s2824_ _s2825_) with + | _s2826_ => + (sep_matches_prefix _s2826_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2827_ _)) => + (match (string_drop _s2826_ _s2827_) with + | _s2828_ => + (reg_name_matches_prefix _s2828_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s2829_ _)) => + match (string_drop _s2828_ + _s2829_) with + | s_ => + Some + ((s, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2796_ (_s2797_ : string) +: M (option ((mword 5 * mword 5 * mword 5 * string))) := + + let _s2798_ := _s2797_ in + (if ((string_startswith _s2798_ "mulw")) then + (match (string_drop _s2798_ (projT1 (string_length "mulw"))) with + | _s2799_ => + (spc_matches_prefix _s2799_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2800_ _)) => + (match (string_drop _s2799_ _s2800_) with + | _s2801_ => + (reg_name_matches_prefix _s2801_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2802_ _)) => + (match (string_drop _s2801_ _s2802_) with + | _s2803_ => + (sep_matches_prefix _s2803_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2804_ _)) => + (match (string_drop _s2803_ _s2804_) with + | _s2805_ => + (reg_name_matches_prefix _s2805_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s2806_ _)) => + (match (string_drop _s2805_ _s2806_) with + | _s2807_ => + (sep_matches_prefix _s2807_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s2808_ _)) => + (match (string_drop _s2807_ _s2808_) with + | _s2809_ => + (reg_name_matches_prefix _s2809_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (rs2,(existT _ _s2810_ _)) => + match (string_drop _s2809_ _s2810_) with + | s_ => Some ((rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((mword 5 * mword 5 * mword 5 * string)))) + : M (option ((mword 5 * mword 5 * mword 5 * string))). + +Definition _s2778_ (_s2779_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) := + + let _s2780_ := _s2779_ in + (if ((string_startswith _s2780_ "rem")) then + (match (string_drop _s2780_ (projT1 (string_length "rem"))) with + | _s2781_ => + (maybe_not_u_matches_prefix _s2781_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s2782_ _)) => + (match (string_drop _s2781_ _s2782_) with + | _s2783_ => + (spc_matches_prefix _s2783_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2784_ _)) => + (match (string_drop _s2783_ _s2784_) with + | _s2785_ => + (reg_name_matches_prefix _s2785_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2786_ _)) => + (match (string_drop _s2785_ _s2786_) with + | _s2787_ => + (sep_matches_prefix _s2787_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2788_ _)) => + (match (string_drop _s2787_ _s2788_) with + | _s2789_ => + (reg_name_matches_prefix _s2789_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2790_ _)) => + (match (string_drop _s2789_ _s2790_) with + | _s2791_ => + (sep_matches_prefix _s2791_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2792_ _)) => + (match (string_drop _s2791_ _s2792_) with + | _s2793_ => + (reg_name_matches_prefix _s2793_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s2794_ _)) => + match (string_drop _s2793_ + _s2794_) with + | s_ => + Some + ((s, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2760_ (_s2761_ : string) +: M (option ((bool * mword 5 * mword 5 * mword 5 * string))) := + + let _s2762_ := _s2761_ in + (if ((string_startswith _s2762_ "div")) then + (match (string_drop _s2762_ (projT1 (string_length "div"))) with + | _s2763_ => + (maybe_not_u_matches_prefix _s2763_) >>= fun w__0 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (s,(existT _ _s2764_ _)) => + (match (string_drop _s2763_ _s2764_) with + | _s2765_ => + (spc_matches_prefix _s2765_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2766_ _)) => + (match (string_drop _s2765_ _s2766_) with + | _s2767_ => + (reg_name_matches_prefix _s2767_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2768_ _)) => + (match (string_drop _s2767_ _s2768_) with + | _s2769_ => + (sep_matches_prefix _s2769_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2770_ _)) => + (match (string_drop _s2769_ _s2770_) with + | _s2771_ => + (reg_name_matches_prefix _s2771_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2772_ _)) => + (match (string_drop _s2771_ _s2772_) with + | _s2773_ => + (sep_matches_prefix _s2773_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2774_ _)) => + (match (string_drop _s2773_ _s2774_) with + | _s2775_ => + (reg_name_matches_prefix _s2775_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some + (rs2,(existT _ _s2776_ _)) => + match (string_drop _s2775_ + _s2776_) with + | s_ => + Some + ((s, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))) + else returnm (None : option ((bool * mword 5 * mword 5 * mword 5 * string)))) + : M (option ((bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2743_ (_s2744_ : string) +: M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) := + + (match _s2744_ with + | _s2745_ => + (mul_mnemonic_matches_prefix _s2745_) >>= fun w__0 : option (((bool * bool * bool) * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some ((high, signed1, signed2),(existT _ _s2746_ _)) => + (match (string_drop _s2745_ _s2746_) with + | _s2747_ => + (spc_matches_prefix _s2747_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2748_ _)) => + (match (string_drop _s2747_ _s2748_) with + | _s2749_ => + (reg_name_matches_prefix _s2749_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2750_ _)) => + (match (string_drop _s2749_ _s2750_) with + | _s2751_ => + (sep_matches_prefix _s2751_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2752_ _)) => + (match (string_drop _s2751_ _s2752_) with + | _s2753_ => + (reg_name_matches_prefix _s2753_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2754_ _)) => + (match (string_drop _s2753_ _s2754_) with + | _s2755_ => + (sep_matches_prefix _s2755_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2756_ _)) => + (match (string_drop _s2755_ _s2756_) with + | _s2757_ => + (reg_name_matches_prefix _s2757_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s2758_ _)) => + match (string_drop _s2757_ + _s2758_) with + | s_ => + Some + ((high, signed1, signed2, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2728_ (_s2729_ : string) +: M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) := + + (match _s2729_ with + | _s2730_ => + (shiftiwop_mnemonic_matches_prefix _s2730_) >>= fun w__0 : option ((sopw * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2731_ _)) => + (match (string_drop _s2730_ _s2731_) with + | _s2732_ => + (spc_matches_prefix _s2732_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2733_ _)) => + (match (string_drop _s2732_ _s2733_) with + | _s2734_ => + (reg_name_matches_prefix _s2734_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2735_ _)) => + (match (string_drop _s2734_ _s2735_) with + | _s2736_ => + (sep_matches_prefix _s2736_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2737_ _)) => + (match (string_drop _s2736_ _s2737_) with + | _s2738_ => + (reg_name_matches_prefix _s2738_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (rs1,(existT _ _s2739_ _)) => + match (string_drop _s2738_ _s2739_) with + | _s2740_ => + match (hex_bits_5_matches_prefix _s2740_) with + | Some (shamt,(existT _ _s2741_ _)) => + match (string_drop _s2740_ _s2741_) with + | s_ => Some ((op, rd, rs1, shamt, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sopw * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2711_ (_s2712_ : string) +: M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) := + + (match _s2712_ with + | _s2713_ => + (rtypew_mnemonic_matches_prefix _s2713_) >>= fun w__0 : option ((ropw * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2714_ _)) => + (match (string_drop _s2713_ _s2714_) with + | _s2715_ => + (spc_matches_prefix _s2715_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2716_ _)) => + (match (string_drop _s2715_ _s2716_) with + | _s2717_ => + (reg_name_matches_prefix _s2717_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2718_ _)) => + (match (string_drop _s2717_ _s2718_) with + | _s2719_ => + (sep_matches_prefix _s2719_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2720_ _)) => + (match (string_drop _s2719_ _s2720_) with + | _s2721_ => + (reg_name_matches_prefix _s2721_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2722_ _)) => + (match (string_drop _s2721_ _s2722_) with + | _s2723_ => + (sep_matches_prefix _s2723_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2724_ _)) => + (match (string_drop _s2723_ _s2724_) with + | _s2725_ => + (reg_name_matches_prefix _s2725_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s2726_ _)) => + match (string_drop _s2725_ + _s2726_) with + | s_ => + Some ((op, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((ropw * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2694_ (_s2695_ : string) +: M (option ((sop * mword 5 * mword 5 * mword 5 * string))) := + + (match _s2695_ with + | _s2696_ => + (shiftw_mnemonic_matches_prefix _s2696_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2697_ _)) => + (match (string_drop _s2696_ _s2697_) with + | _s2698_ => + (spc_matches_prefix _s2698_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2699_ _)) => + (match (string_drop _s2698_ _s2699_) with + | _s2700_ => + (reg_name_matches_prefix _s2700_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2701_ _)) => + (match (string_drop _s2700_ _s2701_) with + | _s2702_ => + (sep_matches_prefix _s2702_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2703_ _)) => + (match (string_drop _s2702_ _s2703_) with + | _s2704_ => + (reg_name_matches_prefix _s2704_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2705_ _)) => + (match (string_drop _s2704_ _s2705_) with + | _s2706_ => + (sep_matches_prefix _s2706_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s2707_ _)) => + match (string_drop _s2706_ _s2707_) with + | _s2708_ => + match (hex_bits_5_matches_prefix + _s2708_) with + | Some (shamt,(existT _ _s2709_ _)) => + match (string_drop _s2708_ _s2709_) with + | s_ => + Some ((op, rd, rs1, shamt, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2678_ (_s2679_ : string) +: M (option ((mword 5 * mword 5 * mword 12 * string))) := + + let _s2680_ := _s2679_ in + (if ((string_startswith _s2680_ "addiw")) then + (match (string_drop _s2680_ (projT1 (string_length "addiw"))) with + | _s2681_ => + (spc_matches_prefix _s2681_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2682_ _)) => + (match (string_drop _s2681_ _s2682_) with + | _s2683_ => + (reg_name_matches_prefix _s2683_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2684_ _)) => + (match (string_drop _s2683_ _s2684_) with + | _s2685_ => + (sep_matches_prefix _s2685_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2686_ _)) => + (match (string_drop _s2685_ _s2686_) with + | _s2687_ => + (reg_name_matches_prefix _s2687_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s2688_ _)) => + (match (string_drop _s2687_ _s2688_) with + | _s2689_ => + (sep_matches_prefix _s2689_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s2690_ _)) => + match (string_drop _s2689_ _s2690_) with + | _s2691_ => + match (hex_bits_12_matches_prefix _s2691_) with + | Some (imm,(existT _ _s2692_ _)) => + match (string_drop _s2691_ _s2692_) with + | s_ => Some ((rd, rs1, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + else returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))) + : M (option ((mword 5 * mword 5 * mword 12 * string))). + +Definition _s2656_ (_s2657_ : string) +: M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) := + + let _s2658_ := _s2657_ in + (if ((string_startswith _s2658_ "s")) then + (match (string_drop _s2658_ (projT1 (string_length "s"))) with + | _s2659_ => + (size_mnemonic_matches_prefix _s2659_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s2660_ _)) => + (match (string_drop _s2659_ _s2660_) with + | _s2661_ => + (maybe_aq_matches_prefix _s2661_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (aq,(existT _ _s2662_ _)) => + (match (string_drop _s2661_ _s2662_) with + | _s2663_ => + (maybe_rl_matches_prefix _s2663_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rl,(existT _ _s2664_ _)) => + (match (string_drop _s2663_ _s2664_) with + | _s2665_ => + (spc_matches_prefix _s2665_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2666_ _)) => + (match (string_drop _s2665_ _s2666_) with + | _s2667_ => + (reg_name_matches_prefix _s2667_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rd,(existT _ _s2668_ _)) => + (match (string_drop _s2667_ _s2668_) with + | _s2669_ => + (sep_matches_prefix _s2669_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2670_ _)) => + (match (string_drop _s2669_ _s2670_) with + | _s2671_ => + (reg_name_matches_prefix _s2671_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (rs1,(existT _ _s2672_ _)) => + (match (string_drop _s2671_ _s2672_) with + | _s2673_ => + (sep_matches_prefix _s2673_) >>= fun w__7 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__7 with + | Some + (tt,(existT _ _s2674_ _)) => + match (string_drop + _s2673_ + _s2674_) with + | _s2675_ => + match (hex_bits_12_matches_prefix + _s2675_) with + | Some + (imm,(existT _ _s2676_ _)) => + match (string_drop + _s2675_ + _s2676_) with + | s_ => + Some + ((size, aq, rl, rd, rs1, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))) + else + returnm (None + : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string)))) + : M (option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string))). + +Definition _s2632_ (_s2633_ : string) +: M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) := + + let _s2634_ := _s2633_ in + (if ((string_startswith _s2634_ "l")) then + (match (string_drop _s2634_ (projT1 (string_length "l"))) with + | _s2635_ => + (size_mnemonic_matches_prefix _s2635_) >>= fun w__0 : option ((word_width * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (size,(existT _ _s2636_ _)) => + (match (string_drop _s2635_ _s2636_) with + | _s2637_ => + (maybe_u_matches_prefix _s2637_) >>= fun w__1 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (is_unsigned,(existT _ _s2638_ _)) => + (match (string_drop _s2637_ _s2638_) with + | _s2639_ => + (maybe_aq_matches_prefix _s2639_) >>= fun w__2 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (aq,(existT _ _s2640_ _)) => + (match (string_drop _s2639_ _s2640_) with + | _s2641_ => + (maybe_rl_matches_prefix _s2641_) >>= fun w__3 : option ((bool * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rl,(existT _ _s2642_ _)) => + (match (string_drop _s2641_ _s2642_) with + | _s2643_ => + (spc_matches_prefix _s2643_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (tt,(existT _ _s2644_ _)) => + (match (string_drop _s2643_ _s2644_) with + | _s2645_ => + (reg_name_matches_prefix _s2645_) >>= fun w__5 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (rd,(existT _ _s2646_ _)) => + (match (string_drop _s2645_ _s2646_) with + | _s2647_ => + (sep_matches_prefix _s2647_) >>= fun w__6 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__6 with + | Some (tt,(existT _ _s2648_ _)) => + (match (string_drop _s2647_ _s2648_) with + | _s2649_ => + (reg_name_matches_prefix _s2649_) >>= fun w__7 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__7 with + | Some (rs1,(existT _ _s2650_ _)) => + (match (string_drop _s2649_ + _s2650_) with + | _s2651_ => + (sep_matches_prefix + _s2651_) >>= fun w__8 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__8 with + | Some + (tt,(existT _ _s2652_ _)) => + match (string_drop + _s2651_ + _s2652_) with + | _s2653_ => + match (hex_bits_12_matches_prefix + _s2653_) with + | Some + (imm,(existT _ _s2654_ _)) => + match (string_drop + _s2653_ + _s2654_) with + | s_ => + Some + ((size, is_unsigned, aq, rl, rd, rs1, imm, s_)) + end + | _ => + None + end + end + | _ => None + end) + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))) + else + returnm (None + : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string)))) + : M (option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string))). + +Definition _s2615_ (_s2616_ : string) +: M (option ((rop * mword 5 * mword 5 * mword 5 * string))) := + + (match _s2616_ with + | _s2617_ => + (rtype_mnemonic_matches_prefix _s2617_) >>= fun w__0 : option ((rop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2618_ _)) => + (match (string_drop _s2617_ _s2618_) with + | _s2619_ => + (spc_matches_prefix _s2619_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2620_ _)) => + (match (string_drop _s2619_ _s2620_) with + | _s2621_ => + (reg_name_matches_prefix _s2621_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2622_ _)) => + (match (string_drop _s2621_ _s2622_) with + | _s2623_ => + (sep_matches_prefix _s2623_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2624_ _)) => + (match (string_drop _s2623_ _s2624_) with + | _s2625_ => + (reg_name_matches_prefix _s2625_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2626_ _)) => + (match (string_drop _s2625_ _s2626_) with + | _s2627_ => + (sep_matches_prefix _s2627_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__5 with + | Some (tt,(existT _ _s2628_ _)) => + (match (string_drop _s2627_ _s2628_) with + | _s2629_ => + (reg_name_matches_prefix _s2629_) >>= fun w__6 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__6 with + | Some (rs2,(existT _ _s2630_ _)) => + match (string_drop _s2629_ + _s2630_) with + | s_ => + Some ((op, rd, rs1, rs2, s_)) + end + | _ => None + end) + : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None + : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + | _ => + returnm (None : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + | _ => returnm (None : option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))) + end) + : M (option ((rop * mword 5 * mword 5 * mword 5 * string))). + +Definition _s2600_ (_s2601_ : string) +: M (option ((sop * mword 5 * mword 5 * mword 6 * string))) := + + (match _s2601_ with + | _s2602_ => + (shiftiop_mnemonic_matches_prefix _s2602_) >>= fun w__0 : option ((sop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2603_ _)) => + (match (string_drop _s2602_ _s2603_) with + | _s2604_ => + (spc_matches_prefix _s2604_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2605_ _)) => + (match (string_drop _s2604_ _s2605_) with + | _s2606_ => + (reg_name_matches_prefix _s2606_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2607_ _)) => + (match (string_drop _s2606_ _s2607_) with + | _s2608_ => + (sep_matches_prefix _s2608_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2609_ _)) => + (match (string_drop _s2608_ _s2609_) with + | _s2610_ => + (reg_name_matches_prefix _s2610_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (rs1,(existT _ _s2611_ _)) => + match (string_drop _s2610_ _s2611_) with + | _s2612_ => + match (hex_bits_6_matches_prefix _s2612_) with + | Some (shamt,(existT _ _s2613_ _)) => + match (string_drop _s2612_ _s2613_) with + | s_ => Some ((op, rd, rs1, shamt, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + | _ => + returnm (None + : option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + | _ => + returnm (None : option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + | _ => returnm (None : option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))) + end) + : M (option ((sop * mword 5 * mword 5 * mword 6 * string))). + +Definition _s2583_ (_s2584_ : string) +: M (option ((iop * mword 5 * mword 5 * mword 12 * string))) := + + (match _s2584_ with + | _s2585_ => + (itype_mnemonic_matches_prefix _s2585_) >>= fun w__0 : option ((iop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2586_ _)) => + (match (string_drop _s2585_ _s2586_) with + | _s2587_ => + (spc_matches_prefix _s2587_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2588_ _)) => + (match (string_drop _s2587_ _s2588_) with + | _s2589_ => + (reg_name_matches_prefix _s2589_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2590_ _)) => + (match (string_drop _s2589_ _s2590_) with + | _s2591_ => + (sep_matches_prefix _s2591_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2592_ _)) => + (match (string_drop _s2591_ _s2592_) with + | _s2593_ => + (reg_name_matches_prefix _s2593_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs1,(existT _ _s2594_ _)) => + (match (string_drop _s2593_ _s2594_) with + | _s2595_ => + (sep_matches_prefix _s2595_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s2596_ _)) => + match (string_drop _s2595_ _s2596_) with + | _s2597_ => + match (hex_bits_12_matches_prefix + _s2597_) with + | Some (imm,(existT _ _s2598_ _)) => + match (string_drop _s2597_ _s2598_) with + | s_ => + Some ((op, rd, rs1, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None : option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((iop * mword 5 * mword 5 * mword 12 * string))). + +Definition _s2566_ (_s2567_ : string) +: M (option ((bop * mword 5 * mword 5 * mword 13 * string))) := + + (match _s2567_ with + | _s2568_ => + (btype_mnemonic_matches_prefix _s2568_) >>= fun w__0 : option ((bop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2569_ _)) => + (match (string_drop _s2568_ _s2569_) with + | _s2570_ => + (spc_matches_prefix _s2570_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2571_ _)) => + (match (string_drop _s2570_ _s2571_) with + | _s2572_ => + (reg_name_matches_prefix _s2572_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rs1,(existT _ _s2573_ _)) => + (match (string_drop _s2572_ _s2573_) with + | _s2574_ => + (sep_matches_prefix _s2574_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (tt,(existT _ _s2575_ _)) => + (match (string_drop _s2574_ _s2575_) with + | _s2576_ => + (reg_name_matches_prefix _s2576_) >>= fun w__4 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__4 with + | Some (rs2,(existT _ _s2577_ _)) => + (match (string_drop _s2576_ _s2577_) with + | _s2578_ => + (sep_matches_prefix _s2578_) >>= fun w__5 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__5 with + | Some (tt,(existT _ _s2579_ _)) => + match (string_drop _s2578_ _s2579_) with + | _s2580_ => + match (hex_bits_13_matches_prefix + _s2580_) with + | Some (imm,(existT _ _s2581_ _)) => + match (string_drop _s2580_ _s2581_) with + | s_ => + Some ((op, rs1, rs2, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + | _ => + returnm (None + : option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + | _ => + returnm (None + : option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + | _ => + returnm (None : option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + | _ => returnm (None : option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))) + end) + : M (option ((bop * mword 5 * mword 5 * mword 13 * string))). + +Definition _s2550_ (_s2551_ : string) +: M (option ((mword 5 * mword 5 * mword 12 * string))) := + + let _s2552_ := _s2551_ in + (if ((string_startswith _s2552_ "jalr")) then + (match (string_drop _s2552_ (projT1 (string_length "jalr"))) with + | _s2553_ => + (spc_matches_prefix _s2553_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2554_ _)) => + (match (string_drop _s2553_ _s2554_) with + | _s2555_ => + (reg_name_matches_prefix _s2555_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2556_ _)) => + (match (string_drop _s2555_ _s2556_) with + | _s2557_ => + (sep_matches_prefix _s2557_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (tt,(existT _ _s2558_ _)) => + (match (string_drop _s2557_ _s2558_) with + | _s2559_ => + (reg_name_matches_prefix _s2559_) >>= fun w__3 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__3 with + | Some (rs1,(existT _ _s2560_ _)) => + (match (string_drop _s2559_ _s2560_) with + | _s2561_ => + (sep_matches_prefix _s2561_) >>= fun w__4 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__4 with + | Some (tt,(existT _ _s2562_ _)) => + match (string_drop _s2561_ _s2562_) with + | _s2563_ => + match (hex_bits_12_matches_prefix _s2563_) with + | Some (imm,(existT _ _s2564_ _)) => + match (string_drop _s2563_ _s2564_) with + | s_ => Some ((rd, rs1, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => + returnm (None + : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + | _ => returnm (None : option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + end) + : M (option ((mword 5 * mword 5 * mword 12 * string))) + else returnm (None : option ((mword 5 * mword 5 * mword 12 * string)))) + : M (option ((mword 5 * mword 5 * mword 12 * string))). + +Definition _s2538_ (_s2539_ : string) +: M (option ((mword 5 * mword 21 * string))) := + + let _s2540_ := _s2539_ in + (if ((string_startswith _s2540_ "jal")) then + (match (string_drop _s2540_ (projT1 (string_length "jal"))) with + | _s2541_ => + (spc_matches_prefix _s2541_) >>= fun w__0 : option ((unit * {n : Z & ArithFact (n >= 0)})) => + (match w__0 with + | Some (tt,(existT _ _s2542_ _)) => + (match (string_drop _s2541_ _s2542_) with + | _s2543_ => + (reg_name_matches_prefix _s2543_) >>= fun w__1 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (rd,(existT _ _s2544_ _)) => + (match (string_drop _s2543_ _s2544_) with + | _s2545_ => + (sep_matches_prefix _s2545_) >>= fun w__2 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__2 with + | Some (tt,(existT _ _s2546_ _)) => + match (string_drop _s2545_ _s2546_) with + | _s2547_ => + match (hex_bits_21_matches_prefix _s2547_) with + | Some (imm,(existT _ _s2548_ _)) => + match (string_drop _s2547_ _s2548_) with + | s_ => Some ((rd, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((mword 5 * mword 21 * string))) + end) + : M (option ((mword 5 * mword 21 * string))) + | _ => returnm (None : option ((mword 5 * mword 21 * string))) + end) + : M (option ((mword 5 * mword 21 * string))) + end) + : M (option ((mword 5 * mword 21 * string))) + | _ => returnm (None : option ((mword 5 * mword 21 * string))) + end) + : M (option ((mword 5 * mword 21 * string))) + end) + : M (option ((mword 5 * mword 21 * string))) + else returnm (None : option ((mword 5 * mword 21 * string)))) + : M (option ((mword 5 * mword 21 * string))). + +Definition _s2525_ (_s2526_ : string) +: M (option ((uop * mword 5 * mword 20 * string))) := + + (match _s2526_ with + | _s2527_ => + (utype_mnemonic_matches_prefix _s2527_) >>= fun w__0 : option ((uop * {n : Z & ArithFact (n >= + 0)})) => + (match w__0 with + | Some (op,(existT _ _s2528_ _)) => + (match (string_drop _s2527_ _s2528_) with + | _s2529_ => + (spc_matches_prefix _s2529_) >>= fun w__1 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + (match w__1 with + | Some (tt,(existT _ _s2530_ _)) => + (match (string_drop _s2529_ _s2530_) with + | _s2531_ => + (reg_name_matches_prefix _s2531_) >>= fun w__2 : option ((mword 5 * {n : Z & ArithFact (n >= + 0)})) => + (match w__2 with + | Some (rd,(existT _ _s2532_ _)) => + (match (string_drop _s2531_ _s2532_) with + | _s2533_ => + (sep_matches_prefix _s2533_) >>= fun w__3 : option ((unit * {n : Z & ArithFact (n >= + 0)})) => + returnm ((match w__3 with + | Some (tt,(existT _ _s2534_ _)) => + match (string_drop _s2533_ _s2534_) with + | _s2535_ => + match (hex_bits_20_matches_prefix _s2535_) with + | Some (imm,(existT _ _s2536_ _)) => + match (string_drop _s2535_ _s2536_) with + | s_ => Some ((op, rd, imm, s_)) + end + | _ => None + end + end + | _ => None + end) + : option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))) + | _ => returnm (None : option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))) + | _ => returnm (None : option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))) + | _ => returnm (None : option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))) + end) + : M (option ((uop * mword 5 * mword 20 * string))). + +Definition assembly_matches_prefix (arg_ : string) +: M (option ((ast * {n : Z & ArithFact (n >= 0)}))) := + + let _s2537_ := arg_ in + (_s2525_ _s2537_) >>= fun w__0 : option ((uop * mword 5 * mword 20 * string)) => + (if ((match w__0 with | Some (op,rd,imm,s_) => true | _ => false end)) then + (_s2525_ _s2537_) >>= fun w__1 : option ((uop * mword 5 * mword 20 * string)) => + (match w__1 with + | Some (op,rd,imm,s_) => + returnm ((Some + ((UTYPE + ((imm, rd, op)), build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2538_ _s2537_) >>= fun w__4 : option ((mword 5 * mword 21 * string)) => + (if ((match w__4 with | Some (rd,imm,s_) => true | _ => false end)) then + (_s2538_ _s2537_) >>= fun w__5 : option ((mword 5 * mword 21 * string)) => + (match w__5 with + | Some (rd,imm,s_) => + returnm ((Some + ((RISCV_JAL + ((imm, rd)), build_ex (projT1 (sub_nat (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2550_ _s2537_) >>= fun w__8 : option ((mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__8 with | Some (rd,rs1,imm,s_) => true | _ => false end)) then + (_s2550_ _s2537_) >>= fun w__9 : option ((mword 5 * mword 5 * mword 12 * string)) => + (match w__9 with + | Some (rd,rs1,imm,s_) => + returnm ((Some + ((RISCV_JALR + ((imm, rs1, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length arg_)) + (projT1 (string_length s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2566_ _s2537_) >>= fun w__12 : option ((bop * mword 5 * mword 5 * mword 13 * string)) => + (if ((match w__12 with | Some (op,rs1,rs2,imm,s_) => true | _ => false end)) then + (_s2566_ _s2537_) >>= fun w__13 : option ((bop * mword 5 * mword 5 * mword 13 * string)) => + (match w__13 with + | Some (op,rs1,rs2,imm,s_) => + returnm ((Some + ((BTYPE + ((imm, rs2, rs1, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2583_ _s2537_) >>= fun w__16 : option ((iop * mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__16 with | Some (op,rd,rs1,imm,s_) => true | _ => false end)) then + (_s2583_ _s2537_) >>= fun w__17 : option ((iop * mword 5 * mword 5 * mword 12 * string)) => + (match w__17 with + | Some (op,rd,rs1,imm,s_) => + returnm ((Some + ((ITYPE + ((imm, rs1, rd, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2600_ _s2537_) >>= fun w__20 : option ((sop * mword 5 * mword 5 * mword 6 * string)) => + (if ((match w__20 with | Some (op,rd,rs1,shamt,s_) => true | _ => false end)) then + (_s2600_ _s2537_) >>= fun w__21 : option ((sop * mword 5 * mword 5 * mword 6 * string)) => + (match w__21 with + | Some (op,rd,rs1,shamt,s_) => + returnm ((Some + ((SHIFTIOP + ((shamt, rs1, rd, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2615_ _s2537_) >>= fun w__24 : option ((rop * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__24 with | Some (op,rd,rs1,rs2,s_) => true | _ => false end)) + then + (_s2615_ _s2537_) >>= fun w__25 : option ((rop * mword 5 * mword 5 * mword 5 * string)) => + (match w__25 with + | Some (op,rd,rs1,rs2,s_) => + returnm ((Some + ((RTYPE + ((rs2, rs1, rd, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2632_ _s2537_) >>= fun w__28 : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__28 with + | Some (size,is_unsigned,aq,rl,rd,rs1,imm,s_) => true + | _ => false + end)) then + (_s2632_ _s2537_) >>= fun w__29 : option ((word_width * bool * bool * bool * mword 5 * mword 5 * mword 12 * string)) => + (match w__29 with + | Some (size,is_unsigned,aq,rl,rd,rs1,imm,s_) => + returnm ((Some + ((LOAD + ((imm, rs1, rd, is_unsigned, size, aq, rl)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2656_ _s2537_) >>= fun w__32 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__32 with + | Some (size,aq,rl,rd,rs1,imm,s_) => true + | _ => false + end)) then + (_s2656_ _s2537_) >>= fun w__33 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 12 * string)) => + (match w__33 with + | Some (size,aq,rl,rd,rs1,imm,s_) => + returnm ((Some + ((STORE + ((imm, rs1, rd, size, aq, rl)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2678_ _s2537_) >>= fun w__36 : option ((mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__36 with | Some (rd,rs1,imm,s_) => true | _ => false end)) + then + (_s2678_ _s2537_) >>= fun w__37 : option ((mword 5 * mword 5 * mword 12 * string)) => + (match w__37 with + | Some (rd,rs1,imm,s_) => + returnm ((Some + ((ADDIW + ((imm, rs1, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2694_ _s2537_) >>= fun w__40 : option ((sop * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__40 with + | Some (op,rd,rs1,shamt,s_) => true + | _ => false + end)) then + (_s2694_ _s2537_) >>= fun w__41 : option ((sop * mword 5 * mword 5 * mword 5 * string)) => + (match w__41 with + | Some (op,rd,rs1,shamt,s_) => + returnm ((Some + ((SHIFTW + ((shamt, rs1, rd, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2711_ _s2537_) >>= fun w__44 : option ((ropw * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__44 with + | Some (op,rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2711_ _s2537_) >>= fun w__45 : option ((ropw * mword 5 * mword 5 * mword 5 * string)) => + (match w__45 with + | Some (op,rd,rs1,rs2,s_) => + returnm ((Some + ((RTYPEW + ((rs2, rs1, rd, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2728_ _s2537_) >>= fun w__48 : option ((sopw * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__48 with + | Some (op,rd,rs1,shamt,s_) => true + | _ => false + end)) then + (_s2728_ _s2537_) >>= fun w__49 : option ((sopw * mword 5 * mword 5 * mword 5 * string)) => + (match w__49 with + | Some (op,rd,rs1,shamt,s_) => + returnm ((Some + ((SHIFTIWOP + ((shamt, rs1, rd, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2743_ _s2537_) >>= fun w__52 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__52 with + | Some (high,signed1,signed2,rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2743_ _s2537_) >>= fun w__53 : option ((bool * bool * bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__53 with + | Some (high,signed1,signed2,rd,rs1,rs2,s_) => + returnm ((Some + ((MUL + ((rs2, rs1, rd, high, signed1, signed2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2760_ _s2537_) >>= fun w__56 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__56 with + | Some (s,rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2760_ _s2537_) >>= fun w__57 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__57 with + | Some (s,rd,rs1,rs2,s_) => + returnm ((Some + ((DIV + ((rs2, rs1, rd, s)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2778_ _s2537_) >>= fun w__60 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__60 with + | Some (s,rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2778_ _s2537_) >>= fun w__61 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__61 with + | Some (s,rd,rs1,rs2,s_) => + returnm ((Some + ((REM + ((rs2, rs1, rd, s)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))) + else + (_s2796_ _s2537_) >>= fun w__64 : option ((mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__64 with + | Some (rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2796_ _s2537_) >>= fun w__65 : option ((mword 5 * mword 5 * mword 5 * string)) => + (match w__65 with + | Some (rd,rs1,rs2,s_) => + returnm ((Some + ((MULW + ((rs2, rs1, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2812_ _s2537_) >>= fun w__68 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__68 with + | Some (s,rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2812_ _s2537_) >>= fun w__69 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__69 with + | Some (s,rd,rs1,rs2,s_) => + returnm ((Some + ((DIVW + ((rs2, rs1, rd, s)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2831_ _s2537_) >>= fun w__72 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__72 with + | Some (s,rd,rs1,rs2,s_) => true + | _ => false + end)) then + (_s2831_ _s2537_) >>= fun w__73 : option ((bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__73 with + | Some (s,rd,rs1,rs2,s_) => + returnm ((Some + ((REMW + ((rs2, rs1, rd, s)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2850_ _s2537_) >>= fun w__76 : option ((mword 4 * mword 4 * string)) => + (if ((match w__76 with + | Some (pred,succ,s_) => true + | _ => false + end)) then + (_s2850_ _s2537_) >>= fun w__77 : option ((mword 4 * mword 4 * string)) => + (match w__77 with + | Some (pred,succ,s_) => + returnm ((Some + ((FENCE + ((pred, succ)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2862_ _s2537_) >>= fun w__80 : option ((mword 4 * mword 4 * string)) => + (if ((match w__80 with + | Some (pred,succ,s_) => true + | _ => false + end)) then + (_s2862_ _s2537_) >>= fun w__81 : option ((mword 4 * mword 4 * string)) => + (match w__81 with + | Some (pred,succ,s_) => + returnm ((Some + ((FENCE_TSO + ((pred, succ)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s2874_ _s2537_) with + | Some (s_) => true + | _ => false + end)) then + (match (_s2874_ _s2537_) with + | Some (s_) => + returnm ((Some + ((FENCEI + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s2878_ _s2537_) with + | Some (s_) => true + | _ => false + end)) then + (match (_s2878_ _s2537_) with + | Some (s_) => + returnm ((Some + ((ECALL + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s2882_ _s2537_) with + | Some (s_) => true + | _ => false + end)) then + (match (_s2882_ _s2537_) with + | Some (s_) => + returnm ((Some + ((MRET + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s2886_ _s2537_) with + | Some (s_) => true + | _ => false + end)) then + (match (_s2886_ _s2537_) with + | Some (s_) => + returnm ((Some + ((SRET + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s2890_ _s2537_) with + | Some (s_) => true + | _ => false + end)) then + (match (_s2890_ _s2537_) with + | Some (s_) => + returnm ((Some + ((EBREAK + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s2894_ _s2537_) with + | Some (s_) => true + | _ => false + end)) then + (match (_s2894_ _s2537_) with + | Some (s_) => + returnm ((Some + ((WFI + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2898_ _s2537_) >>= fun w__96 : option ((mword 5 * mword 5 * string)) => + (if ((match w__96 with + | Some (rs1,rs2,s_) => true + | _ => false + end)) then + (_s2898_ _s2537_) >>= fun w__97 : option ((mword 5 * mword 5 * string)) => + (match w__97 with + | Some (rs1,rs2,s_) => + returnm ((Some + ((SFENCE_VMA + ((rs1, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2910_ _s2537_) >>= fun w__100 : option ((word_width * bool * bool * mword 5 * mword 5 * string)) => + (if ((match w__100 with + | Some + (size,aq,rl,rd,rs1,s_) => + true + | _ => false + end)) then + (_s2910_ _s2537_) >>= fun w__101 : option ((word_width * bool * bool * mword 5 * mword 5 * string)) => + (match w__101 with + | Some + (size,aq,rl,rd,rs1,s_) => + returnm ((Some + ((LOADRES + ((aq, rl, rs1, size, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2928_ _s2537_) >>= fun w__104 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__104 with + | Some + (size,aq,rl,rd,rs1,rs2,s_) => + true + | _ => false + end)) then + (_s2928_ _s2537_) >>= fun w__105 : option ((word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__105 with + | Some + (size,aq,rl,rd,rs1,rs2,s_) => + returnm ((Some + ((STORECON + ((aq, rl, rs2, rs1, size, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2950_ _s2537_) >>= fun w__108 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) => + (if ((match w__108 with + | Some + (op,width,aq,rl,rd,rs1,rs2,s_) => + true + | _ => false + end)) then + (_s2950_ _s2537_) >>= fun w__109 : option ((amoop * word_width * bool * bool * mword 5 * mword 5 * mword 5 * string)) => + (match w__109 with + | Some + (op,width,aq,rl,rd,rs1,rs2,s_) => + returnm ((Some + ((AMO + ((op, aq, rl, rs2, rs1, width, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2974_ _s2537_) >>= fun w__112 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__112 with + | Some + (op,rd,rs1,csr,s_) => + true + | _ => false + end)) then + (_s2974_ _s2537_) >>= fun w__113 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) => + (match w__113 with + | Some + (op,rd,rs1,csr,s_) => + returnm ((Some + ((CSR + ((csr, rs1, rd, true, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s2992_ _s2537_) >>= fun w__116 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) => + (if ((match w__116 with + | Some + (op,rd,rs1,csr,s_) => + true + | _ => false + end)) then + (_s2992_ _s2537_) >>= fun w__117 : option ((csrop * mword 5 * mword 5 * mword 12 * string)) => + (match w__117 with + | Some + (op,rd,rs1,csr,s_) => + returnm ((Some + ((CSR + ((csr, rs1, rd, false, op)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if ((match (_s3009_ + _s2537_) with + | Some + (s_) => + true + | _ => + false + end)) + then + (match (_s3009_ + _s2537_) with + | Some (s_) => + returnm ((Some + ((C_NOP + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3013_ _s2537_) >>= fun w__122 : option ((mword 3 * mword 8 * string)) => + (if ((match w__122 with + | Some + (rdc,nzimm,s_) => + neq_vec + nzimm + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0] + : mword 8) + | _ => + false + end)) then + (_s3013_ + _s2537_) >>= fun w__123 : option ((mword 3 * mword 8 * string)) => + (match w__123 with + | Some + (rdc,nzimm,s_) => + returnm ((Some + ((C_ADDI4SPN + ((rdc, nzimm)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3025_ + _s2537_) >>= fun w__126 : option ((mword 3 * mword 3 * mword 5 * string)) => + (if ((match w__126 with + | Some + (rdc,rsc,uimm,s_) => + true + | _ => + false + end)) + then + (_s3025_ + _s2537_) >>= fun w__127 : option ((mword 3 * mword 3 * mword 5 * string)) => + (match w__127 with + | Some + (rdc,rsc,uimm,s_) => + returnm ((Some + ((C_LW + ((uimm, rsc, rdc)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3041_ + _s2537_) >>= fun w__130 : option ((mword 3 * mword 3 * mword 5 * string)) => + (if ((match w__130 with + | Some + (rdc,rsc,uimm,s_) => + true + | _ => + false + end)) + then + (_s3041_ + _s2537_) >>= fun w__131 : option ((mword 3 * mword 3 * mword 5 * string)) => + (match w__131 with + | Some + (rdc,rsc,uimm,s_) => + returnm ((Some + ((C_LD + ((uimm, rsc, rdc)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3057_ + _s2537_) >>= fun w__134 : option ((mword 3 * mword 3 * mword 5 * string)) => + (if ((match w__134 with + | Some + (rsc1,rsc2,uimm,s_) => + true + | _ => + false + end)) + then + (_s3057_ + _s2537_) >>= fun w__135 : option ((mword 3 * mword 3 * mword 5 * string)) => + (match w__135 with + | Some + (rsc1,rsc2,uimm,s_) => + returnm ((Some + ((C_SW + ((uimm, rsc1, rsc2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3073_ + _s2537_) >>= fun w__138 : option ((mword 3 * mword 3 * mword 5 * string)) => + (if ((match w__138 with + | Some + (rsc1,rsc2,uimm,s_) => + true + | _ => + false + end)) + then + (_s3073_ + _s2537_) >>= fun w__139 : option ((mword 3 * mword 3 * mword 5 * string)) => + (match w__139 with + | Some + (rsc1,rsc2,uimm,s_) => + returnm ((Some + ((C_SD + ((uimm, rsc1, rsc2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3089_ + _s2537_) >>= fun w__142 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__142 with + | Some + (rsd,nzi,s_) => + andb + (neq_vec + nzi + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6)) + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s3089_ + _s2537_) >>= fun w__143 : option ((mword 5 * mword 6 * string)) => + (match w__143 with + | Some + (rsd,nzi,s_) => + returnm ((Some + ((C_ADDI + ((nzi, rsd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3101_ + _s2537_) >>= fun w__146 : option ((mword 11 * string)) => + (if + ((match w__146 with + | Some + (imm,s_) => + true + | _ => + false + end)) + then + (_s3101_ + _s2537_) >>= fun w__147 : option ((mword 11 * string)) => + (match w__147 with + | Some + (imm,s_) => + returnm ((Some + ((C_JAL + (imm), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3109_ + _s2537_) >>= fun w__150 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__150 with + | Some + (rsd,imm,s_) => + true + | _ => + false + end)) + then + (_s3109_ + _s2537_) >>= fun w__151 : option ((mword 5 * mword 6 * string)) => + (match w__151 with + | Some + (rsd,imm,s_) => + returnm ((Some + ((C_ADDIW + ((imm, rsd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3121_ + _s2537_) >>= fun w__154 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__154 with + | Some + (rd,imm,s_) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s3121_ + _s2537_) >>= fun w__155 : option ((mword 5 * mword 6 * string)) => + (match w__155 with + | Some + (rd,imm,s_) => + returnm ((Some + ((C_LI + ((imm, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3133_ + _s2537_) >>= fun w__158 : option ((mword 6 * string)) => + (if + ((match w__158 with + | Some + (imm,s_) => + neq_vec + imm + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s3133_ + _s2537_) >>= fun w__159 : option ((mword 6 * string)) => + (match w__159 with + | Some + (imm,s_) => + returnm ((Some + ((C_ADDI16SP + (imm), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3141_ + _s2537_) >>= fun w__162 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__162 with + | Some + (rd,imm,s_) => + andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg))) + (andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + sp))) + (neq_vec + imm + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6))) + | _ => + false + end)) + then + (_s3141_ + _s2537_) >>= fun w__163 : option ((mword 5 * mword 6 * string)) => + (match w__163 with + | Some + (rd,imm,s_) => + returnm ((Some + ((C_LUI + ((imm, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3153_ + _s2537_) >>= fun w__166 : option ((mword 3 * mword 6 * string)) => + (if + ((match w__166 with + | Some + (rsd,shamt,s_) => + neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s3153_ + _s2537_) >>= fun w__167 : option ((mword 3 * mword 6 * string)) => + (match w__167 with + | Some + (rsd,shamt,s_) => + returnm ((Some + ((C_SRLI + ((shamt, rsd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3165_ + _s2537_) >>= fun w__170 : option ((mword 3 * mword 6 * string)) => + (if + ((match w__170 with + | Some + (rsd,shamt,s_) => + neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6) + | _ => + false + end)) + then + (_s3165_ + _s2537_) >>= fun w__171 : option ((mword 3 * mword 6 * string)) => + (match w__171 with + | Some + (rsd,shamt,s_) => + returnm ((Some + ((C_SRAI + ((shamt, rsd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3177_ + _s2537_) >>= fun w__174 : option ((mword 3 * mword 6 * string)) => + (if + ((match w__174 with + | Some + (rsd,imm,s_) => + true + | _ => + false + end)) + then + (_s3177_ + _s2537_) >>= fun w__175 : option ((mword 3 * mword 6 * string)) => + (match w__175 with + | Some + (rsd,imm,s_) => + returnm ((Some + ((C_ANDI + ((imm, rsd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3189_ + _s2537_) >>= fun w__178 : option ((mword 3 * mword 3 * string)) => + (if + ((match w__178 with + | Some + (rsd,rs2,s_) => + true + | _ => + false + end)) + then + (_s3189_ + _s2537_) >>= fun w__179 : option ((mword 3 * mword 3 * string)) => + (match w__179 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_SUB + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3201_ + _s2537_) >>= fun w__182 : option ((mword 3 * mword 3 * string)) => + (if + ((match w__182 with + | Some + (rsd,rs2,s_) => + true + | _ => + false + end)) + then + (_s3201_ + _s2537_) >>= fun w__183 : option ((mword 3 * mword 3 * string)) => + (match w__183 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_XOR + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3213_ + _s2537_) >>= fun w__186 : option ((mword 3 * mword 3 * string)) => + (if + ((match w__186 with + | Some + (rsd,rs2,s_) => + true + | _ => + false + end)) + then + (_s3213_ + _s2537_) >>= fun w__187 : option ((mword 3 * mword 3 * string)) => + (match w__187 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_OR + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3225_ + _s2537_) >>= fun w__190 : option ((mword 3 * mword 3 * string)) => + (if + ((match w__190 with + | Some + (rsd,rs2,s_) => + true + | _ => + false + end)) + then + (_s3225_ + _s2537_) >>= fun w__191 : option ((mword 3 * mword 3 * string)) => + (match w__191 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_AND + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3237_ + _s2537_) >>= fun w__194 : option ((mword 3 * mword 3 * string)) => + (if + ((match w__194 with + | Some + (rsd,rs2,s_) => + true + | _ => + false + end)) + then + (_s3237_ + _s2537_) >>= fun w__195 : option ((mword 3 * mword 3 * string)) => + (match w__195 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_SUBW + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3249_ + _s2537_) >>= fun w__198 : option ((mword 3 * mword 3 * string)) => + (if + ((match w__198 with + | Some + (rsd,rs2,s_) => + true + | _ => + false + end)) + then + (_s3249_ + _s2537_) >>= fun w__199 : option ((mword 3 * mword 3 * string)) => + (match w__199 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_ADDW + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3261_ + _s2537_) >>= fun w__202 : option ((mword 11 * string)) => + (if + ((match w__202 with + | Some + (imm,s_) => + true + | _ => + false + end)) + then + (_s3261_ + _s2537_) >>= fun w__203 : option ((mword 11 * string)) => + (match w__203 with + | Some + (imm,s_) => + returnm ((Some + ((C_J + (imm), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3269_ + _s2537_) >>= fun w__206 : option ((mword 3 * mword 8 * string)) => + (if + ((match w__206 with + | Some + (rs,imm,s_) => + true + | _ => + false + end)) + then + (_s3269_ + _s2537_) >>= fun w__207 : option ((mword 3 * mword 8 * string)) => + (match w__207 with + | Some + (rs,imm,s_) => + returnm ((Some + ((C_BEQZ + ((imm, rs)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3281_ + _s2537_) >>= fun w__210 : option ((mword 3 * mword 8 * string)) => + (if + ((match w__210 with + | Some + (rs,imm,s_) => + true + | _ => + false + end)) + then + (_s3281_ + _s2537_) >>= fun w__211 : option ((mword 3 * mword 8 * string)) => + (match w__211 with + | Some + (rs,imm,s_) => + returnm ((Some + ((C_BNEZ + ((imm, rs)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3293_ + _s2537_) >>= fun w__214 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__214 with + | Some + (rsd,shamt,s_) => + andb + (neq_vec + shamt + (vec_of_bits [B0;B0;B0;B0;B0;B0] + : mword 6)) + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s3293_ + _s2537_) >>= fun w__215 : option ((mword 5 * mword 6 * string)) => + (match w__215 with + | Some + (rsd,shamt,s_) => + returnm ((Some + ((C_SLLI + ((shamt, rsd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3305_ + _s2537_) >>= fun w__218 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__218 with + | Some + (rd,uimm,s_) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s3305_ + _s2537_) >>= fun w__219 : option ((mword 5 * mword 6 * string)) => + (match w__219 with + | Some + (rd,uimm,s_) => + returnm ((Some + ((C_LWSP + ((uimm, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3317_ + _s2537_) >>= fun w__222 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__222 with + | Some + (rd,uimm,s_) => + neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s3317_ + _s2537_) >>= fun w__223 : option ((mword 5 * mword 6 * string)) => + (match w__223 with + | Some + (rd,uimm,s_) => + returnm ((Some + ((C_LDSP + ((uimm, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3329_ + _s2537_) >>= fun w__226 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__226 with + | Some + (rd,uimm,s_) => + true + | _ => + false + end)) + then + (_s3329_ + _s2537_) >>= fun w__227 : option ((mword 5 * mword 6 * string)) => + (match w__227 with + | Some + (rd,uimm,s_) => + returnm ((Some + ((C_SWSP + ((uimm, rd)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3341_ + _s2537_) >>= fun w__230 : option ((mword 5 * mword 6 * string)) => + (if + ((match w__230 with + | Some + (rs2,uimm,s_) => + true + | _ => + false + end)) + then + (_s3341_ + _s2537_) >>= fun w__231 : option ((mword 5 * mword 6 * string)) => + (match w__231 with + | Some + (rs2,uimm,s_) => + returnm ((Some + ((C_SDSP + ((uimm, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3353_ + _s2537_) >>= fun w__234 : option ((mword 5 * string)) => + (if + ((match w__234 with + | Some + (rs1,s_) => + neq_int + (projT1 (regbits_to_regno + rs1)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s3353_ + _s2537_) >>= fun w__235 : option ((mword 5 * string)) => + (match w__235 with + | Some + (rs1,s_) => + returnm ((Some + ((C_JR + (rs1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3361_ + _s2537_) >>= fun w__238 : option ((mword 5 * string)) => + (if + ((match w__238 with + | Some + (rs1,s_) => + neq_int + (projT1 (regbits_to_regno + rs1)) + (projT1 (regbits_to_regno + zreg)) + | _ => + false + end)) + then + (_s3361_ + _s2537_) >>= fun w__239 : option ((mword 5 * string)) => + (match w__239 with + | Some + (rs1,s_) => + returnm ((Some + ((C_JALR + (rs1), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3369_ + _s2537_) >>= fun w__242 : option ((mword 5 * mword 5 * string)) => + (if + ((match w__242 with + | Some + (rd,rs2,s_) => + andb + (neq_int + (projT1 (regbits_to_regno + rd)) + (projT1 (regbits_to_regno + zreg))) + (neq_int + (projT1 (regbits_to_regno + rs2)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s3369_ + _s2537_) >>= fun w__243 : option ((mword 5 * mword 5 * string)) => + (match w__243 with + | Some + (rd,rs2,s_) => + returnm ((Some + ((C_MV + ((rd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if + ((match (_s3381_ + _s2537_) with + | Some + (s_) => + true + | _ => + false + end)) + then + (match (_s3381_ + _s2537_) with + | Some + (s_) => + returnm ((Some + ((C_EBREAK + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3385_ + _s2537_) >>= fun w__248 : option ((mword 5 * mword 5 * string)) => + (if + ((match w__248 with + | Some + (rsd,rs2,s_) => + andb + (neq_int + (projT1 (regbits_to_regno + rsd)) + (projT1 (regbits_to_regno + zreg))) + (neq_int + (projT1 (regbits_to_regno + rs2)) + (projT1 (regbits_to_regno + zreg))) + | _ => + false + end)) + then + (_s3385_ + _s2537_) >>= fun w__249 : option ((mword 5 * mword 5 * string)) => + (match w__249 with + | Some + (rsd,rs2,s_) => + returnm ((Some + ((C_ADD + ((rsd, rs2)), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if + ((match (_s3397_ + _s2537_) with + | Some + (s_) => + true + | _ => + false + end)) + then + (match (_s3397_ + _s2537_) with + | Some + (s_) => + returnm ((Some + ((STOP_FETCHING + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else if + ((match (_s3401_ + _s2537_) with + | Some + (s_) => + true + | _ => + false + end)) + then + (match (_s3401_ + _s2537_) with + | Some + (s_) => + returnm ((Some + ((THREAD_START + (tt), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3405_ + _s2537_) >>= fun w__256 : option ((mword 32 * string)) => + (if + ((match w__256 with + | Some + (s,s_) => + true + | _ => + false + end)) + then + (_s3405_ + _s2537_) >>= fun w__257 : option ((mword 32 * string)) => + (match w__257 with + | Some + (s,s_) => + returnm ((Some + ((ILLEGAL + (s), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + (_s3413_ + _s2537_) >>= fun w__260 : option ((mword 16 * string)) => + (if + ((match w__260 with + | Some + (s,s_) => + true + | _ => + false + end)) + then + (_s3413_ + _s2537_) >>= fun w__261 : option ((mword 16 * string)) => + (match w__261 with + | Some + (s,s_) => + returnm ((Some + ((C_ILLEGAL + (s), build_ex (projT1 (sub_nat + (projT1 (string_length + arg_)) + (projT1 (string_length + s_))))))) + : option ((ast * {n : Z & ArithFact (n >= + 0)}))) + | _ => + exit tt + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + end) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)}))) + else + returnm (None + : option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= + 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)})))) + : M (option ((ast * {n : Z & ArithFact (n >= 0)}))). + +Definition execute_WFI '(tt : unit) +: M (bool) := + + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + (match w__0 with + | Machine => (platform_wfi tt) >> returnm (true : bool) + | Supervisor => + read_reg mstatus_ref >>= fun w__1 : Mstatus => + (if ((eq_vec (_get_Mstatus_TW w__1) ((bool_to_bits true) : mword 1))) then + (handle_illegal tt) >> returnm (false : bool) + else (platform_wfi tt) >> returnm (true : bool)) + : M (bool) + | User => (handle_illegal tt) >> returnm (false : bool) + end) + : M (bool). + +Definition execute_UTYPE (imm : mword 20) (rd : mword 5) (op : uop) +: M (bool) := + + let off : xlenbits := + EXTS 64 (concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : mword 12)) in + (match op with + | RISCV_LUI => returnm (off : xlenbits) + | RISCV_AUIPC => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + returnm ((add_vec w__0 off) + : mword 64) + end) >>= fun ret : xlenbits => + (wX (projT1 (regbits_to_regno rd)) ret) >> returnm (true : bool). + +Definition execute_THREAD_START '(tt : unit) : bool := true. + +Definition execute_STORECON +(aq : bool) (rl : bool) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) (rd : mword 5) +: M (bool) := + + (speculate_conditional tt) >>= fun w__0 : bool => + (if ((Bool.eqb w__0 false)) then + (wX (projT1 (regbits_to_regno rd)) (EXTZ 64 (vec_of_bits [B1] : mword 1))) >> + returnm (true + : bool) + else + (rX (projT1 (regbits_to_regno rs1))) >>= fun vaddr : xlenbits => + (match width with + | BYTE => returnm (true : bool) + | HALF => + (cast_unit_vec (access_vec_dec vaddr 0)) >>= fun w__1 : mword 1 => + returnm ((eq_vec w__1 (vec_of_bits [B0] : mword 1)) + : bool) + | WORD => + returnm ((eq_vec (subrange_vec_dec vaddr 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))) + : bool) + | DOUBLE => + returnm ((eq_vec (subrange_vec_dec vaddr 2 0) + (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1))) + : bool) + end) >>= fun aligned : bool => + (if ((negb aligned)) then + (handle_mem_exception vaddr E_SAMO_Addr_Align) >> returnm (false : bool) + else if ((Bool.eqb (match_reservation vaddr) false)) then + (wX (projT1 (regbits_to_regno rd)) (EXTZ 64 (vec_of_bits [B1] : mword 1))) >> + returnm (true + : bool) + else + (translateAddr vaddr Write Data) >>= fun w__2 : TR_Result => + (match w__2 with + | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (false : bool) + | TR_Address (addr) => + (match width with + | WORD => (mem_write_ea addr 4 aq rl true) : M (MemoryOpResult unit) + | DOUBLE => (mem_write_ea addr 8 aq rl true) : M (MemoryOpResult unit) + | _ => (internal_error "STORECON expected word or double") : M (MemoryOpResult unit) + end) >>= fun eares : MemoryOpResult unit => + (match eares with + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + | MemValue (_) => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + (match width with + | WORD => + (mem_write_value addr 4 (subrange_vec_dec rs2_val 31 0) aq rl true) + : M (MemoryOpResult bool) + | DOUBLE => (mem_write_value addr 8 rs2_val aq rl true) : M (MemoryOpResult bool) + | _ => + (internal_error "STORECON expected word or double") : M (MemoryOpResult bool) + end) >>= fun res : MemoryOpResult bool => + (match res with + | MemValue (true) => + (wX (projT1 (regbits_to_regno rd)) (EXTZ 64 (vec_of_bits [B0] : mword 1))) >> + let '_ := (cancel_reservation tt) : unit in + returnm (true + : bool) + | MemValue (false) => + (wX (projT1 (regbits_to_regno rd)) (EXTZ 64 (vec_of_bits [B1] : mword 1))) >> + let '_ := (cancel_reservation tt) : unit in + returnm (true + : bool) + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + end) + : M (bool) + end) + : M (bool) + end) + : M (bool)) + : M (bool)) + : M (bool). + +Definition execute_STORE +(imm : mword 12) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) (aq : bool) (rl : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let vaddr : xlenbits := add_vec w__0 (EXTS 64 imm) in + (check_misaligned vaddr width) >>= fun w__1 : bool => + (if (w__1) then (handle_mem_exception vaddr E_SAMO_Addr_Align) >> returnm (false : bool) + else + (translateAddr vaddr Write Data) >>= fun w__2 : TR_Result => + (match w__2 with + | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (false : bool) + | TR_Address (addr) => + (match width with + | BYTE => (mem_write_ea addr 1 aq rl false) : M (MemoryOpResult unit) + | HALF => (mem_write_ea addr 2 aq rl false) : M (MemoryOpResult unit) + | WORD => (mem_write_ea addr 4 aq rl false) : M (MemoryOpResult unit) + | DOUBLE => (mem_write_ea addr 8 aq rl false) : M (MemoryOpResult unit) + end) >>= fun eares : MemoryOpResult unit => + (match eares with + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + | MemValue (_) => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + (match width with + | BYTE => + (mem_write_value addr 1 (subrange_vec_dec rs2_val 7 0) aq rl false) + : M (MemoryOpResult bool) + | HALF => + (mem_write_value addr 2 (subrange_vec_dec rs2_val 15 0) aq rl false) + : M (MemoryOpResult bool) + | WORD => + (mem_write_value addr 4 (subrange_vec_dec rs2_val 31 0) aq rl false) + : M (MemoryOpResult bool) + | DOUBLE => (mem_write_value addr 8 rs2_val aq rl false) : M (MemoryOpResult bool) + end) >>= fun res : MemoryOpResult bool => + (match res with + | MemValue (true) => returnm (true : bool) + | MemValue (false) => + (internal_error "store got false from mem_write_value") : M (bool) + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + end) + : M (bool) + end) + : M (bool) + end) + : M (bool)) + : M (bool). + +Definition execute_STOP_FETCHING '(tt : unit) : bool := true. + +Definition execute_SRET '(tt : unit) +: M (bool) := + + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + (match w__0 with + | User => (handle_illegal tt) : M (unit) + | Supervisor => + read_reg mstatus_ref >>= fun w__1 : Mstatus => + (if ((eq_vec (_get_Mstatus_TSR w__1) ((bool_to_bits true) : mword 1))) then + (handle_illegal tt) + : M (unit) + else + read_reg cur_privilege_ref >>= fun w__2 : Privilege => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__3 : xlenbits => + (handle_exception w__2 (CTL_SRET (tt)) w__3) >>= fun w__4 : mword 64 => + write_reg nextPC_ref w__4 + : M (unit)) + : M (unit) + | Machine => + read_reg cur_privilege_ref >>= fun w__5 : Privilege => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__6 : xlenbits => + (handle_exception w__5 (CTL_SRET (tt)) w__6) >>= fun w__7 : mword 64 => + write_reg nextPC_ref w__7 + : M (unit) + end) >> + returnm (false + : bool). + +Definition execute_SHIFTW (shamt : mword 5) (rs1 : mword 5) (rd : mword 5) (op : sop) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let rs1_val := subrange_vec_dec w__0 31 0 in + let result : bits 32 := + match op with + | RISCV_SLLI => shift_bits_left rs1_val shamt + | RISCV_SRLI => shift_bits_right rs1_val shamt + | RISCV_SRAI => shift_right_arith32 rs1_val shamt + end in + (wX (projT1 (regbits_to_regno rd)) (EXTS 64 result)) >> returnm (true : bool). + +Definition execute_SHIFTIWOP (shamt : mword 5) (rs1 : mword 5) (rd : mword 5) (op : sopw) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + let result : xlenbits := + match op with + | RISCV_SLLIW => EXTS 64 (shift_bits_left (subrange_vec_dec rs1_val 31 0) shamt) + | RISCV_SRLIW => EXTS 64 (shift_bits_right (subrange_vec_dec rs1_val 31 0) shamt) + | RISCV_SRAIW => EXTS 64 (shift_right_arith32 (subrange_vec_dec rs1_val 31 0) shamt) + end in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool). + +Definition execute_SHIFTIOP (shamt : mword 6) (rs1 : mword 5) (rd : mword 5) (op : sop) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + let result : xlenbits := + match op with + | RISCV_SLLI => shift_bits_left rs1_val shamt + | RISCV_SRLI => shift_bits_right rs1_val shamt + | RISCV_SRAI => shift_right_arith64 rs1_val shamt + end in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool). + +Definition execute_SFENCE_VMA (rs1 : mword 5) (rs2 : mword 5) +: M (bool) := + + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + (if ((eq_vec (privLevel_to_bits w__0) ((privLevel_to_bits User) : mword 2))) then + (handle_illegal tt) >> returnm (false : bool) + else + read_reg mstatus_ref >>= fun w__1 : Mstatus => + read_reg mstatus_ref >>= fun w__2 : Mstatus => + let p__15 := (architecture (_get_Mstatus_SXL w__1), _get_Mstatus_TVM w__2) in + (match p__15 with + | (Some (RV64), v_0) => + (if ((eq_vec v_0 ((bool_to_bits true) : mword 1))) then + (handle_illegal tt) >> returnm (false : bool) + else if ((eq_vec v_0 ((bool_to_bits false) : mword 1))) then + (if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then + returnm (None + : option (mword 39)) + else + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__3 : mword 64 => + returnm ((Some + (subrange_vec_dec w__3 38 0)) + : option (mword 39))) >>= fun addr : option vaddr39 => + (if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then + returnm (None + : option (mword 16)) + else + (rX (projT1 (regbits_to_regno rs2))) >>= fun w__4 : mword 64 => + returnm ((Some + (subrange_vec_dec w__4 15 0)) + : option (mword 16))) >>= fun asid : option asid64 => + (flushTLB asid addr) >> returnm (true : bool) + else + (match (Some + (RV64), v_0) with + | (g__13, g__14) => (internal_error "unimplemented sfence architecture") : M (bool) + end) + : M (bool)) + : M (bool) + | (g__13, g__14) => (internal_error "unimplemented sfence architecture") : M (bool) + end) + : M (bool)) + : M (bool). + +Definition execute_RTYPEW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (op : ropw) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let rs1_val := subrange_vec_dec w__0 31 0 in + (rX (projT1 (regbits_to_regno rs2))) >>= fun w__1 : mword 64 => + let rs2_val := subrange_vec_dec w__1 31 0 in + let result : bits 32 := + match op with + | RISCV_ADDW => add_vec rs1_val rs2_val + | RISCV_SUBW => sub_vec rs1_val rs2_val + | RISCV_SLLW => shift_bits_left rs1_val (subrange_vec_dec rs2_val 4 0) + | RISCV_SRLW => shift_bits_right rs1_val (subrange_vec_dec rs2_val 4 0) + | RISCV_SRAW => shift_right_arith32 rs1_val (subrange_vec_dec rs2_val 4 0) + end in + (wX (projT1 (regbits_to_regno rd)) (EXTS 64 result)) >> returnm (true : bool). + +Definition execute_RTYPE (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (op : rop) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + let result : xlenbits := + match op with + | RISCV_ADD => add_vec rs1_val rs2_val + | RISCV_SUB => sub_vec rs1_val rs2_val + | RISCV_SLL => shift_bits_left rs1_val (subrange_vec_dec rs2_val 5 0) + | RISCV_SLT => EXTZ 64 (bool_to_bits (zopz0zI_s rs1_val rs2_val)) + | RISCV_SLTU => EXTZ 64 (bool_to_bits (zopz0zI_u rs1_val rs2_val)) + | RISCV_XOR => xor_vec rs1_val rs2_val + | RISCV_SRL => shift_bits_right rs1_val (subrange_vec_dec rs2_val 5 0) + | RISCV_SRA => shift_right_arith64 rs1_val (subrange_vec_dec rs2_val 5 0) + | RISCV_OR => or_vec rs1_val rs2_val + | RISCV_AND => and_vec rs1_val rs2_val + end in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool). + +Definition execute_RISCV_JALR (imm : mword 12) (rs1 : mword 5) (rd : mword 5) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let newPC : xlenbits := + concat_vec (subrange_vec_dec (add_vec w__0 (EXTS 64 imm)) 63 1) (vec_of_bits [B0] : mword 1) in + (and_boolM ((bit_to_bool (access_vec_dec newPC 1)) : M (bool)) + ((haveRVC tt) >>= fun w__2 : bool => returnm ((negb w__2) : bool))) >>= fun w__3 : bool => + (if (w__3) then (handle_mem_exception newPC E_Fetch_Addr_Align) >> returnm (false : bool) + else + ((read_reg nextPC_ref) : M (mword 64)) >>= fun w__4 : xlenbits => + (wX (projT1 (regbits_to_regno rd)) w__4) >> + write_reg nextPC_ref newPC >> returnm (true : bool)) + : M (bool). + +Definition execute_RISCV_JAL (imm : mword 21) (rd : mword 5) +: M (bool) := + + ((read_reg PC_ref) : M (mword 64)) >>= fun pc : xlenbits => + let newPC : xlenbits := add_vec pc (EXTS 64 imm) in + (and_boolM ((bit_to_bool (access_vec_dec newPC 1)) : M (bool)) + ((haveRVC tt) >>= fun w__1 : bool => returnm ((negb w__1) : bool))) >>= fun w__2 : bool => + (if (w__2) then (handle_mem_exception newPC E_Fetch_Addr_Align) >> returnm (false : bool) + else + ((read_reg nextPC_ref) : M (mword 64)) >>= fun w__3 : xlenbits => + (wX (projT1 (regbits_to_regno rd)) w__3) >> + write_reg nextPC_ref newPC >> returnm (true : bool)) + : M (bool). + +Definition execute_REMW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let rs1_val := subrange_vec_dec w__0 31 0 in + (rX (projT1 (regbits_to_regno rs2))) >>= fun w__1 : mword 64 => + let rs2_val := subrange_vec_dec w__1 31 0 in + let rs1_int : Z := if (s) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in + let rs2_int : Z := if (s) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in + let r : Z := + if sumbool_of_bool ((Z.eqb rs2_int 0)) then rs1_int + else rem_round_zero rs1_int rs2_int in + (wX (projT1 (regbits_to_regno rd)) (EXTS 64 (to_bits 32 r))) >> returnm (true : bool). + +Definition execute_REM (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + let rs1_int : Z := if (s) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in + let rs2_int : Z := if (s) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in + let r : Z := + if sumbool_of_bool ((Z.eqb rs2_int 0)) then rs1_int + else rem_round_zero rs1_int rs2_int in + (wX (projT1 (regbits_to_regno rd)) (to_bits xlen r)) >> returnm (true : bool). + +Definition execute_MULW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let rs1_val := subrange_vec_dec w__0 31 0 in + (rX (projT1 (regbits_to_regno rs2))) >>= fun w__1 : mword 64 => + let rs2_val := subrange_vec_dec w__1 31 0 in + let rs1_int : Z := projT1 (sint rs1_val) in + let rs2_int : Z := projT1 (sint rs2_val) in + let result32 := subrange_vec_dec (to_bits 64 (Z.mul rs1_int rs2_int)) 31 0 in + let result : xlenbits := EXTS 64 result32 in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool). + +Definition execute_MUL +(rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (high : bool) (signed1 : bool) (signed2 : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + let rs1_int : Z := if (signed1) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in + let rs2_int : Z := if (signed2) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in + let result128 := to_bits 128 (Z.mul rs1_int rs2_int) in + let result := + if (high) then subrange_vec_dec result128 127 64 + else subrange_vec_dec result128 63 0 in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool). + +Definition execute_MRET '(tt : unit) +: M (bool) := + + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + (if ((eq_vec (privLevel_to_bits w__0) ((privLevel_to_bits Machine) : mword 2))) then + read_reg cur_privilege_ref >>= fun w__1 : Privilege => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : xlenbits => + (handle_exception w__1 (CTL_MRET (tt)) w__2) >>= fun w__3 : mword 64 => + write_reg nextPC_ref w__3 + : M (unit) + else (handle_illegal tt) : M (unit)) >> + returnm (false + : bool). + +Definition execute_LOADRES +(aq : bool) (rl : bool) (rs1 : mword 5) (width : word_width) (rd : mword 5) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun vaddr : xlenbits => + (match width with + | BYTE => returnm (true : bool) + | HALF => + (cast_unit_vec (access_vec_dec vaddr 0)) >>= fun w__0 : mword 1 => + returnm ((eq_vec w__0 (vec_of_bits [B0] : mword 1)) + : bool) + | WORD => + returnm ((eq_vec (subrange_vec_dec vaddr 1 0) (vec_of_bits [B0;B0] : mword (1 - 0 + 1))) + : bool) + | DOUBLE => + returnm ((eq_vec (subrange_vec_dec vaddr 2 0) (vec_of_bits [B0;B0;B0] : mword (2 - 0 + 1))) + : bool) + end) >>= fun aligned : bool => + (if ((negb aligned)) then + (handle_mem_exception vaddr E_Load_Addr_Align) >> returnm (false : bool) + else + (translateAddr vaddr Read Data) >>= fun w__1 : TR_Result => + (match w__1 with + | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (false : bool) + | TR_Address (addr) => + (match width with + | WORD => + (mem_read addr 4 aq rl true) >>= fun w__2 : MemoryOpResult (mword (8 * 4)) => + (process_loadres rd vaddr w__2 false) + : M (bool) + | DOUBLE => + (mem_read addr 8 aq rl true) >>= fun w__4 : MemoryOpResult (mword (8 * 8)) => + (process_loadres rd vaddr w__4 false) + : M (bool) + | _ => (internal_error "LOADRES expected WORD or DOUBLE") : M (bool) + end) + : M (bool) + end) + : M (bool)) + : M (bool). + +Definition execute_LOAD +(imm : mword 12) (rs1 : mword 5) (rd : mword 5) (is_unsigned : bool) (width : word_width) +(aq : bool) (rl : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let vaddr : xlenbits := add_vec w__0 (EXTS 64 imm) in + (check_misaligned vaddr width) >>= fun w__1 : bool => + (if (w__1) then (handle_mem_exception vaddr E_Load_Addr_Align) >> returnm (false : bool) + else + (translateAddr vaddr Read Data) >>= fun w__2 : TR_Result => + (match w__2 with + | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (false : bool) + | TR_Address (addr) => + (match width with + | BYTE => + (mem_read addr 1 aq rl false) >>= fun w__3 : MemoryOpResult (mword (8 * 1)) => + (process_load rd vaddr w__3 is_unsigned) + : M (bool) + | HALF => + (mem_read addr 2 aq rl false) >>= fun w__5 : MemoryOpResult (mword (8 * 2)) => + (process_load rd vaddr w__5 is_unsigned) + : M (bool) + | WORD => + (mem_read addr 4 aq rl false) >>= fun w__7 : MemoryOpResult (mword (8 * 4)) => + (process_load rd vaddr w__7 is_unsigned) + : M (bool) + | DOUBLE => + (mem_read addr 8 aq rl false) >>= fun w__9 : MemoryOpResult (mword (8 * 8)) => + (process_load rd vaddr w__9 is_unsigned) + : M (bool) + end) + : M (bool) + end) + : M (bool)) + : M (bool). + +Definition execute_ITYPE (imm : mword 12) (rs1 : mword 5) (rd : mword 5) (op : iop) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + let immext : xlenbits := EXTS 64 imm in + let result : xlenbits := + match op with + | RISCV_ADDI => add_vec rs1_val immext + | RISCV_SLTI => EXTZ 64 (bool_to_bits (zopz0zI_s rs1_val immext)) + | RISCV_SLTIU => EXTZ 64 (bool_to_bits (zopz0zI_u rs1_val immext)) + | RISCV_XORI => xor_vec rs1_val immext + | RISCV_ORI => or_vec rs1_val immext + | RISCV_ANDI => and_vec rs1_val immext + end in + (wX (projT1 (regbits_to_regno rd)) result) >> returnm (true : bool). + +Definition execute_ILLEGAL (s : mword 32) +: M (bool) := + + (handle_illegal tt) >> returnm (false : bool). + +Definition execute_FENCE_TSO (pred : mword 4) (succ : mword 4) +: M (bool) := + + (match (pred, succ) with + | (v__836, v__837) => + (if ((andb (eq_vec (subrange_vec_dec v__836 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__837 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_tso tt) + : M (unit) + else + returnm ((if ((andb + (eq_vec (subrange_vec_dec v__836 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__837 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) then + tt + else + let '_ := (print_endline "FIXME: unsupported fence") : unit in + tt) + : unit)) + : M (unit) + end) >> + returnm (true + : bool). + +Definition execute_FENCEI '(tt : unit) : bool := true. + +Definition execute_FENCE (pred : mword 4) (succ : mword 4) +: M (bool) := + + (match (pred, succ) with + | (v__796, v__797) => + (if ((andb (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_rw_rw tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_r_rw tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + (MEM_fence_r_r tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_rw_w tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_w_w tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_w_rw tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + (MEM_fence_rw_r tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) + then + (MEM_fence_r_w tt) + : M (unit) + else if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) (vec_of_bits [B0;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) + then + (MEM_fence_w_r tt) + : M (unit) + else + returnm ((if ((andb + (eq_vec (subrange_vec_dec v__796 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__797 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) then + tt + else + let '_ := (print_endline "FIXME: unsupported fence") : unit in + tt) + : unit)) + : M (unit) + end) >> + returnm (true + : bool). + +Definition execute_ECALL '(tt : unit) +: M (bool) := + + read_reg cur_privilege_ref >>= fun w__0 : Privilege => + let t : sync_exception := + {| sync_exception_trap := + (match w__0 with + | User => E_U_EnvCall + | Supervisor => E_S_EnvCall + | Machine => E_M_EnvCall + end); + sync_exception_excinfo := (None : option xlenbits) |} in + read_reg cur_privilege_ref >>= fun w__1 : Privilege => + ((read_reg PC_ref) : M (mword 64)) >>= fun w__2 : xlenbits => + (handle_exception w__1 (CTL_TRAP (t)) w__2) >>= fun w__3 : mword 64 => + write_reg nextPC_ref w__3 >> returnm (false : bool). + +Definition execute_EBREAK '(tt : unit) +: M (bool) := + + ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + (handle_mem_exception w__0 E_Breakpoint) >> returnm (false : bool). + +Definition execute_DIVW (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let rs1_val := subrange_vec_dec w__0 31 0 in + (rX (projT1 (regbits_to_regno rs2))) >>= fun w__1 : mword 64 => + let rs2_val := subrange_vec_dec w__1 31 0 in + let rs1_int : Z := if (s) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in + let rs2_int : Z := if (s) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in + let q : Z := + if sumbool_of_bool ((Z.eqb rs2_int 0)) then (-1) + else quot_round_zero rs1_int rs2_int in + let q' : Z := + if sumbool_of_bool ((andb s (Z.gtb q (Z.sub (projT1 (pow2 31)) 1)))) then Z.sub 0 (pow 2 31) + else q in + (wX (projT1 (regbits_to_regno rd)) (EXTS 64 (to_bits 32 q'))) >> returnm (true : bool). + +Definition execute_DIV (rs2 : mword 5) (rs1 : mword 5) (rd : mword 5) (s : bool) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + let rs1_int : Z := if (s) then projT1 (sint rs1_val) else projT1 (uint rs1_val) in + let rs2_int : Z := if (s) then projT1 (sint rs2_val) else projT1 (uint rs2_val) in + let q : Z := + if sumbool_of_bool ((Z.eqb rs2_int 0)) then (-1) + else quot_round_zero rs1_int rs2_int in + let q' : Z := if sumbool_of_bool ((andb s (Z.gtb q xlen_max_signed))) then xlen_min_signed else q in + (wX (projT1 (regbits_to_regno rd)) (to_bits xlen q')) >> returnm (true : bool). + +Definition execute_C_NOP '(tt : unit) : bool := true. + +Definition execute_C_ILLEGAL (s : mword 16) +: M (bool) := + + (handle_illegal tt) >> returnm (false : bool). + +Definition execute_C_ADDIW (imm : mword 6) (rsd : mword 5) +: M (bool) := + + let imm : bits 32 := EXTS 32 imm in + (rX (projT1 (regbits_to_regno rsd))) >>= fun rs_val => + let res : bits 32 := add_vec (subrange_vec_dec rs_val 31 0) imm in + (wX (projT1 (regbits_to_regno rsd)) (EXTS 64 res)) >> returnm (true : bool). + +Definition execute_CSR (csr : mword 12) (rs1 : mword 5) (rd : mword 5) (is_imm : bool) (op : csrop) +: M (bool) := + + (if (is_imm) then returnm ((EXTZ 64 rs1) : mword 64) + else (rX (projT1 (regbits_to_regno rs1))) : M (mword 64)) >>= fun rs1_val : xlenbits => + let isWrite : bool := + match op with + | CSRRW => true + | _ => if (is_imm) then neq_int (projT1 (uint rs1_val)) 0 else neq_int (projT1 (uint rs1)) 0 + end in + read_reg cur_privilege_ref >>= fun w__1 : Privilege => + (check_CSR csr w__1 isWrite) >>= fun w__2 : bool => + (if ((negb w__2)) then (handle_illegal tt) >> returnm (false : bool) + else + (readCSR csr) >>= fun csr_val => + (if (isWrite) then + let new_val : xlenbits := + match op with + | CSRRW => rs1_val + | CSRRS => or_vec csr_val rs1_val + | CSRRC => and_vec csr_val (not_vec rs1_val) + end in + (writeCSR csr new_val) + : M (unit) + else returnm (tt : unit)) >> + (wX (projT1 (regbits_to_regno rd)) csr_val) >> returnm (true : bool)) + : M (bool). + +Definition execute_BTYPE (imm : mword 13) (rs2 : mword 5) (rs1 : mword 5) (op : bop) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun rs1_val => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val => + let taken : bool := + match op with + | RISCV_BEQ => eq_vec rs1_val rs2_val + | RISCV_BNE => neq_vec rs1_val rs2_val + | RISCV_BLT => zopz0zI_s rs1_val rs2_val + | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val + | RISCV_BLTU => zopz0zI_u rs1_val rs2_val + | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val + end in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let newPC := add_vec w__0 (EXTS 64 imm) in + (if (taken) then + (and_boolM ((bit_to_bool (access_vec_dec newPC 1)) : M (bool)) + ((haveRVC tt) >>= fun w__2 : bool => returnm ((negb w__2) : bool))) >>= fun w__3 : bool => + (if (w__3) then (handle_mem_exception newPC E_Fetch_Addr_Align) >> returnm (false : bool) + else write_reg nextPC_ref newPC >> returnm (true : bool)) + : M (bool) + else returnm (true : bool)) + : M (bool). + +Definition execute_AMO +(op : amoop) (aq : bool) (rl : bool) (rs2 : mword 5) (rs1 : mword 5) (width : word_width) +(rd : mword 5) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun vaddr : xlenbits => + (translateAddr vaddr ReadWrite Data) >>= fun w__0 : TR_Result => + (match w__0 with + | TR_Failure (e) => (handle_mem_exception vaddr e) >> returnm (false : bool) + | TR_Address (addr) => + (match width with + | WORD => (mem_write_ea addr 4 (andb aq rl) rl true) : M (MemoryOpResult unit) + | DOUBLE => (mem_write_ea addr 8 (andb aq rl) rl true) : M (MemoryOpResult unit) + | _ => (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult unit) + end) >>= fun eares : MemoryOpResult unit => + (match eares with + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + | MemValue (_) => + (match width with + | WORD => + (mem_read addr 4 aq (andb aq rl) true) >>= fun w__4 : MemoryOpResult (mword (8 * 4)) => + returnm ((extend_value false w__4) + : MemoryOpResult (mword 64)) + | DOUBLE => + (mem_read addr 8 aq (andb aq rl) true) >>= fun w__5 : MemoryOpResult (mword (8 * 8)) => + returnm ((extend_value false w__5) + : MemoryOpResult (mword 64)) + | _ => (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult (mword 64)) + end) >>= fun rval : MemoryOpResult xlenbits => + (match rval with + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + | MemValue (loaded) => + (rX (projT1 (regbits_to_regno rs2))) >>= fun rs2_val : xlenbits => + let result : xlenbits := + match op with + | AMOSWAP => rs2_val + | AMOADD => add_vec rs2_val loaded + | AMOXOR => xor_vec rs2_val loaded + | AMOAND => and_vec rs2_val loaded + | AMOOR => or_vec rs2_val loaded + | AMOMIN => vector64 (Z.min (projT1 (sint rs2_val)) (projT1 (sint loaded))) + | AMOMAX => vector64 (Z.max (projT1 (sint rs2_val)) (projT1 (sint loaded))) + | AMOMINU => + vector64 (projT1 (min_nat (projT1 (uint rs2_val)) (projT1 (uint loaded)))) + | AMOMAXU => + vector64 (projT1 (max_nat (projT1 (uint rs2_val)) (projT1 (uint loaded)))) + end in + (match width with + | WORD => + (mem_write_value addr 4 (subrange_vec_dec result 31 0) (andb aq rl) rl true) + : M (MemoryOpResult bool) + | DOUBLE => + (mem_write_value addr 8 result (andb aq rl) rl true) : M (MemoryOpResult bool) + | _ => (internal_error "AMO expected WORD or DOUBLE") : M (MemoryOpResult bool) + end) >>= fun wval : MemoryOpResult bool => + (match wval with + | MemValue (true) => + (wX (projT1 (regbits_to_regno rd)) loaded) >> returnm (true : bool) + | MemValue (false) => + (internal_error "AMO got false from mem_write_value") : M (bool) + | MemException (e) => (handle_mem_exception addr e) >> returnm (false : bool) + end) + : M (bool) + end) + : M (bool) + end) + : M (bool) + end) + : M (bool). + +Definition execute_ADDIW (imm : mword 12) (rs1 : mword 5) (rd : mword 5) +: M (bool) := + + (rX (projT1 (regbits_to_regno rs1))) >>= fun w__0 : mword 64 => + let result : xlenbits := add_vec (EXTS 64 imm) w__0 in + (wX (projT1 (regbits_to_regno rd)) (EXTS 64 (subrange_vec_dec result 31 0))) >> + returnm (true + : bool). + +Definition compressed_measure (instr : ast) +: Z := + + match instr with + | C_ADDI4SPN (rdc,nzimm) => 1 + | C_LW (uimm,rsc,rdc) => 1 + | C_LD (uimm,rsc,rdc) => 1 + | C_SW (uimm,rsc1,rsc2) => 1 + | C_SD (uimm,rsc1,rsc2) => 1 + | C_ADDI (nzi,rsd) => 1 + | C_JAL (imm) => 1 + | C_LI (imm,rd) => 1 + | C_ADDI16SP (imm) => 1 + | C_LUI (imm,rd) => 1 + | C_SRLI (shamt,rsd) => 1 + | C_SRAI (shamt,rsd) => 1 + | C_ANDI (imm,rsd) => 1 + | C_SUB (rsd,rs2) => 1 + | C_XOR (rsd,rs2) => 1 + | C_OR (rsd,rs2) => 1 + | C_AND (rsd,rs2) => 1 + | C_SUBW (rsd,rs2) => 1 + | C_ADDW (rsd,rs2) => 1 + | C_J (imm) => 1 + | C_BEQZ (imm,rs) => 1 + | C_BNEZ (imm,rs) => 1 + | C_SLLI (shamt,rsd) => 1 + | C_LWSP (uimm,rd) => 1 + | C_LDSP (uimm,rd) => 1 + | C_SWSP (uimm,rs2) => 1 + | C_SDSP (uimm,rs2) => 1 + | C_JR (rs1) => 1 + | C_JALR (rs1) => 1 + | C_MV (rd,rs2) => 1 + | C_EBREAK (tt') => 1 + | C_ADD (rsd,rs2) => 1 + | _ => 0 + end. + +Fixpoint _rec_execute (merge_var : ast) (_reclimit : Z) (_acc : Acc (Zwf 0) _reclimit) +{struct _acc} : M (bool) := + + assert_exp' (Z.geb _reclimit 0) "recursion limit reached" >>= fun _ => + (match merge_var with + | C_ADDI4SPN (rdc,nzimm) => + let imm : bits 12 := + concat_vec (vec_of_bits [B0;B0] : mword 2) + (concat_vec nzimm (vec_of_bits [B0;B0] : mword 2)) in + let rd := creg2reg_bits rdc in + (_rec_execute (ITYPE ((imm, sp, rd, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_LW (uimm,rsc,rdc) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in + let rd := creg2reg_bits rdc in + let rs := creg2reg_bits rsc in + (_rec_execute (LOAD ((imm, rs, rd, false, WORD, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_LD (uimm,rsc,rdc) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in + let rd := creg2reg_bits rdc in + let rs := creg2reg_bits rsc in + (_rec_execute (LOAD ((imm, rs, rd, false, DOUBLE, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_SW (uimm,rsc1,rsc2) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in + let rs1 := creg2reg_bits rsc1 in + let rs2 := creg2reg_bits rsc2 in + (_rec_execute (STORE ((imm, rs2, rs1, WORD, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_SD (uimm,rsc1,rsc2) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in + let rs1 := creg2reg_bits rsc1 in + let rs2 := creg2reg_bits rsc2 in + (_rec_execute (STORE ((imm, rs2, rs1, DOUBLE, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_ADDI (nzi,rsd) => + let imm : bits 12 := EXTS 12 nzi in + (_rec_execute (ITYPE ((imm, rsd, rsd, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_JAL (imm) => + (_rec_execute (RISCV_JAL ((EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), ra))) + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_LI (imm,rd) => + let imm : bits 12 := EXTS 12 imm in + (_rec_execute (ITYPE ((imm, zreg, rd, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_ADDI16SP (imm) => + let imm : bits 12 := EXTS 12 (concat_vec imm (vec_of_bits [B0;B0;B0;B0] : mword 4)) in + (_rec_execute (ITYPE ((imm, sp, sp, RISCV_ADDI))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_LUI (imm,rd) => + let res : bits 20 := EXTS 20 imm in + (_rec_execute (UTYPE ((res, rd, RISCV_LUI))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_SRLI (shamt,rsd) => + let rsd := creg2reg_bits rsd in + (_rec_execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SRLI))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_SRAI (shamt,rsd) => + let rsd := creg2reg_bits rsd in + (_rec_execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SRAI))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_ANDI (imm,rsd) => + let rsd := creg2reg_bits rsd in + (_rec_execute (ITYPE ((EXTS 12 imm, rsd, rsd, RISCV_ANDI))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_SUB (rsd,rs2) => + let rsd := creg2reg_bits rsd in + let rs2 := creg2reg_bits rs2 in + (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_SUB))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_XOR (rsd,rs2) => + let rsd := creg2reg_bits rsd in + let rs2 := creg2reg_bits rs2 in + (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_XOR))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_OR (rsd,rs2) => + let rsd := creg2reg_bits rsd in + let rs2 := creg2reg_bits rs2 in + (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_OR))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_AND (rsd,rs2) => + let rsd := creg2reg_bits rsd in + let rs2 := creg2reg_bits rs2 in + (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_AND))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_SUBW (rsd,rs2) => + let rsd := creg2reg_bits rsd in + let rs2 := creg2reg_bits rs2 in + (_rec_execute (RTYPEW ((rs2, rsd, rsd, RISCV_SUBW))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_ADDW (rsd,rs2) => + let rsd := creg2reg_bits rsd in + let rs2 := creg2reg_bits rs2 in + (_rec_execute (RTYPEW ((rs2, rsd, rsd, RISCV_ADDW))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_J (imm) => + (_rec_execute (RISCV_JAL ((EXTS 21 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg))) + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_BEQZ (imm,rs) => + (_rec_execute + (BTYPE + ((EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_bits rs, RISCV_BEQ))) + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_BNEZ (imm,rs) => + (_rec_execute + (BTYPE + ((EXTS 13 (concat_vec imm (vec_of_bits [B0] : mword 1)), zreg, creg2reg_bits rs, RISCV_BNE))) + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_SLLI (shamt,rsd) => + (_rec_execute (SHIFTIOP ((shamt, rsd, rsd, RISCV_SLLI))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_LWSP (uimm,rd) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in + (_rec_execute (LOAD ((imm, sp, rd, false, WORD, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_LDSP (uimm,rd) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in + (_rec_execute (LOAD ((imm, sp, rd, false, DOUBLE, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_SWSP (uimm,rs2) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0] : mword 2)) in + (_rec_execute (STORE ((imm, rs2, sp, WORD, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_SDSP (uimm,rs2) => + let imm : bits 12 := EXTZ 12 (concat_vec uimm (vec_of_bits [B0;B0;B0] : mword 3)) in + (_rec_execute (STORE ((imm, rs2, sp, DOUBLE, false, false))) (Z.sub _reclimit 1) + (_limit_reduces _acc)) + : M (bool) + | C_JR (rs1) => + (_rec_execute (RISCV_JALR ((EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, zreg))) + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_JALR (rs1) => + (_rec_execute (RISCV_JALR ((EXTZ 12 (vec_of_bits [B0] : mword 1), rs1, ra))) + (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_MV (rd,rs2) => + (_rec_execute (RTYPE ((rs2, zreg, rd, RISCV_ADD))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | C_EBREAK (tt) => + (_rec_execute (EBREAK (tt)) (Z.sub _reclimit 1) (_limit_reduces _acc)) : M (bool) + | C_ADD (rsd,rs2) => + (_rec_execute (RTYPE ((rs2, rsd, rsd, RISCV_ADD))) (Z.sub _reclimit 1) (_limit_reduces _acc)) + : M (bool) + | UTYPE (imm,rd,op) => (execute_UTYPE imm rd op) : M (bool) + | RISCV_JAL (imm,rd) => (execute_RISCV_JAL imm rd) : M (bool) + | BTYPE (imm,rs2,rs1,op) => (execute_BTYPE imm rs2 rs1 op) : M (bool) + | ITYPE (imm,rs1,rd,op) => (execute_ITYPE imm rs1 rd op) : M (bool) + | SHIFTIOP (shamt,rs1,rd,op) => (execute_SHIFTIOP shamt rs1 rd op) : M (bool) + | RTYPE (rs2,rs1,rd,op) => (execute_RTYPE rs2 rs1 rd op) : M (bool) + | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) => + (execute_LOAD imm rs1 rd is_unsigned width aq rl) : M (bool) + | STORE (imm,rs2,rs1,width,aq,rl) => (execute_STORE imm rs2 rs1 width aq rl) : M (bool) + | ADDIW (imm,rs1,rd) => (execute_ADDIW imm rs1 rd) : M (bool) + | SHIFTW (shamt,rs1,rd,op) => (execute_SHIFTW shamt rs1 rd op) : M (bool) + | RTYPEW (rs2,rs1,rd,op) => (execute_RTYPEW rs2 rs1 rd op) : M (bool) + | SHIFTIWOP (shamt,rs1,rd,op) => (execute_SHIFTIWOP shamt rs1 rd op) : M (bool) + | MUL (rs2,rs1,rd,high,signed1,signed2) => + (execute_MUL rs2 rs1 rd high signed1 signed2) : M (bool) + | DIV (rs2,rs1,rd,s) => (execute_DIV rs2 rs1 rd s) : M (bool) + | REM (rs2,rs1,rd,s) => (execute_REM rs2 rs1 rd s) : M (bool) + | MULW (rs2,rs1,rd) => (execute_MULW rs2 rs1 rd) : M (bool) + | DIVW (rs2,rs1,rd,s) => (execute_DIVW rs2 rs1 rd s) : M (bool) + | REMW (rs2,rs1,rd,s) => (execute_REMW rs2 rs1 rd s) : M (bool) + | FENCE (pred,succ) => (execute_FENCE pred succ) : M (bool) + | FENCE_TSO (pred,succ) => (execute_FENCE_TSO pred succ) : M (bool) + | FENCEI (arg0) => returnm ((execute_FENCEI arg0) : bool) + | ECALL (arg0) => (execute_ECALL arg0) : M (bool) + | MRET (arg0) => (execute_MRET arg0) : M (bool) + | SRET (arg0) => (execute_SRET arg0) : M (bool) + | EBREAK (arg0) => (execute_EBREAK arg0) : M (bool) + | WFI (arg0) => (execute_WFI arg0) : M (bool) + | SFENCE_VMA (rs1,rs2) => (execute_SFENCE_VMA rs1 rs2) : M (bool) + | LOADRES (aq,rl,rs1,width,rd) => (execute_LOADRES aq rl rs1 width rd) : M (bool) + | STORECON (aq,rl,rs2,rs1,width,rd) => (execute_STORECON aq rl rs2 rs1 width rd) : M (bool) + | AMO (op,aq,rl,rs2,rs1,width,rd) => (execute_AMO op aq rl rs2 rs1 width rd) : M (bool) + | CSR (csr,rs1,rd,is_imm,op) => (execute_CSR csr rs1 rd is_imm op) : M (bool) + | C_NOP (arg0) => returnm ((execute_C_NOP arg0) : bool) + | C_ADDIW (imm,rsd) => (execute_C_ADDIW imm rsd) : M (bool) + | STOP_FETCHING (arg0) => returnm ((execute_STOP_FETCHING arg0) : bool) + | THREAD_START (arg0) => returnm ((execute_THREAD_START arg0) : bool) + | ILLEGAL (s) => (execute_ILLEGAL s) : M (bool) + | C_ILLEGAL (s) => (execute_C_ILLEGAL s) : M (bool) + | RISCV_JALR (imm,rs1,rd) => (execute_RISCV_JALR imm rs1 rd) : M (bool) + end) + : M (bool). + +Definition execute (i : ast) +: M (bool) := + + (_rec_execute i ((compressed_measure i) : Z) (Zwf_guarded _)) + : M (bool). + +Definition print_insn (insn : ast) : M (string) := (assembly_forwards insn) : M (string). + +Definition decode (bv : mword 32) : option ast := Some (encdec_backwards bv). + +Definition decodeCompressed (bv : mword 16) : option ast := Some (encdec_compressed_backwards bv). + +Definition read_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 11)} +: read_kind := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Read_plain + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Read_reserve + else if sumbool_of_bool ((Z.eqb p0_ 2)) then Read_acquire + else if sumbool_of_bool ((Z.eqb p0_ 3)) then Read_exclusive + else if sumbool_of_bool ((Z.eqb p0_ 4)) then Read_exclusive_acquire + else if sumbool_of_bool ((Z.eqb p0_ 5)) then Read_stream + else if sumbool_of_bool ((Z.eqb p0_ 6)) then Read_RISCV_acquire + else if sumbool_of_bool ((Z.eqb p0_ 7)) then Read_RISCV_strong_acquire + else if sumbool_of_bool ((Z.eqb p0_ 8)) then Read_RISCV_reserved + else if sumbool_of_bool ((Z.eqb p0_ 9)) then Read_RISCV_reserved_acquire + else if sumbool_of_bool ((Z.eqb p0_ 10)) then Read_RISCV_reserved_strong_acquire + else Read_X86_locked. + +Definition num_of_read_kind (arg_ : read_kind) +: {e : Z & ArithFact (0 <= e /\ e <= 11)} := + + build_ex(match arg_ with + | Read_plain => 0 + | Read_reserve => 1 + | Read_acquire => 2 + | Read_exclusive => 3 + | Read_exclusive_acquire => 4 + | Read_stream => 5 + | Read_RISCV_acquire => 6 + | Read_RISCV_strong_acquire => 7 + | Read_RISCV_reserved => 8 + | Read_RISCV_reserved_acquire => 9 + | Read_RISCV_reserved_strong_acquire => 10 + | Read_X86_locked => 11 + end). + +Definition write_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 10)} +: write_kind := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Write_plain + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Write_conditional + else if sumbool_of_bool ((Z.eqb p0_ 2)) then Write_release + else if sumbool_of_bool ((Z.eqb p0_ 3)) then Write_exclusive + else if sumbool_of_bool ((Z.eqb p0_ 4)) then Write_exclusive_release + else if sumbool_of_bool ((Z.eqb p0_ 5)) then Write_RISCV_release + else if sumbool_of_bool ((Z.eqb p0_ 6)) then Write_RISCV_strong_release + else if sumbool_of_bool ((Z.eqb p0_ 7)) then Write_RISCV_conditional + else if sumbool_of_bool ((Z.eqb p0_ 8)) then Write_RISCV_conditional_release + else if sumbool_of_bool ((Z.eqb p0_ 9)) then Write_RISCV_conditional_strong_release + else Write_X86_locked. + +Definition num_of_write_kind (arg_ : write_kind) +: {e : Z & ArithFact (0 <= e /\ e <= 10)} := + + build_ex(match arg_ with + | Write_plain => 0 + | Write_conditional => 1 + | Write_release => 2 + | Write_exclusive => 3 + | Write_exclusive_release => 4 + | Write_RISCV_release => 5 + | Write_RISCV_strong_release => 6 + | Write_RISCV_conditional => 7 + | Write_RISCV_conditional_release => 8 + | Write_RISCV_conditional_strong_release => 9 + | Write_X86_locked => 10 + end). + +Definition barrier_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 23)} +: barrier_kind := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Barrier_Sync + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Barrier_LwSync + else if sumbool_of_bool ((Z.eqb p0_ 2)) then Barrier_Eieio + else if sumbool_of_bool ((Z.eqb p0_ 3)) then Barrier_Isync + else if sumbool_of_bool ((Z.eqb p0_ 4)) then Barrier_DMB + else if sumbool_of_bool ((Z.eqb p0_ 5)) then Barrier_DMB_ST + else if sumbool_of_bool ((Z.eqb p0_ 6)) then Barrier_DMB_LD + else if sumbool_of_bool ((Z.eqb p0_ 7)) then Barrier_DSB + else if sumbool_of_bool ((Z.eqb p0_ 8)) then Barrier_DSB_ST + else if sumbool_of_bool ((Z.eqb p0_ 9)) then Barrier_DSB_LD + else if sumbool_of_bool ((Z.eqb p0_ 10)) then Barrier_ISB + else if sumbool_of_bool ((Z.eqb p0_ 11)) then Barrier_MIPS_SYNC + else if sumbool_of_bool ((Z.eqb p0_ 12)) then Barrier_RISCV_rw_rw + else if sumbool_of_bool ((Z.eqb p0_ 13)) then Barrier_RISCV_r_rw + else if sumbool_of_bool ((Z.eqb p0_ 14)) then Barrier_RISCV_r_r + else if sumbool_of_bool ((Z.eqb p0_ 15)) then Barrier_RISCV_rw_w + else if sumbool_of_bool ((Z.eqb p0_ 16)) then Barrier_RISCV_w_w + else if sumbool_of_bool ((Z.eqb p0_ 17)) then Barrier_RISCV_w_rw + else if sumbool_of_bool ((Z.eqb p0_ 18)) then Barrier_RISCV_rw_r + else if sumbool_of_bool ((Z.eqb p0_ 19)) then Barrier_RISCV_r_w + else if sumbool_of_bool ((Z.eqb p0_ 20)) then Barrier_RISCV_w_r + else if sumbool_of_bool ((Z.eqb p0_ 21)) then Barrier_RISCV_tso + else if sumbool_of_bool ((Z.eqb p0_ 22)) then Barrier_RISCV_i + else Barrier_x86_MFENCE. + +Definition num_of_barrier_kind (arg_ : barrier_kind) +: {e : Z & ArithFact (0 <= e /\ e <= 23)} := + + build_ex(match arg_ with + | Barrier_Sync => 0 + | Barrier_LwSync => 1 + | Barrier_Eieio => 2 + | Barrier_Isync => 3 + | Barrier_DMB => 4 + | Barrier_DMB_ST => 5 + | Barrier_DMB_LD => 6 + | Barrier_DSB => 7 + | Barrier_DSB_ST => 8 + | Barrier_DSB_LD => 9 + | Barrier_ISB => 10 + | Barrier_MIPS_SYNC => 11 + | Barrier_RISCV_rw_rw => 12 + | Barrier_RISCV_r_rw => 13 + | Barrier_RISCV_r_r => 14 + | Barrier_RISCV_rw_w => 15 + | Barrier_RISCV_w_w => 16 + | Barrier_RISCV_w_rw => 17 + | Barrier_RISCV_rw_r => 18 + | Barrier_RISCV_r_w => 19 + | Barrier_RISCV_w_r => 20 + | Barrier_RISCV_tso => 21 + | Barrier_RISCV_i => 22 + | Barrier_x86_MFENCE => 23 + end). + +Definition trans_kind_of_num (arg_ : Z) `{ArithFact (0 <= arg_ /\ arg_ <= 2)} +: trans_kind := + + let p0_ := arg_ in + if sumbool_of_bool ((Z.eqb p0_ 0)) then Transaction_start + else if sumbool_of_bool ((Z.eqb p0_ 1)) then Transaction_commit + else Transaction_abort. + +Definition num_of_trans_kind (arg_ : trans_kind) +: {e : Z & ArithFact (0 <= e /\ e <= 2)} := + + build_ex(match arg_ with + | Transaction_start => 0 + | Transaction_commit => 1 + | Transaction_abort => 2 + end). + +Definition GPRstr : vec string 32 := +vec_of_list_len ["x31";"x30";"x29";"x28";"x27";"x26";"x25";"x24";"x23";"x22";"x21";"x20";"x19";"x18";"x17";"x16";"x15";"x14";"x13";"x12";"x11"; + "x10";"x9";"x8";"x7";"x6";"x5";"x4";"x3";"x2";"x1";"x0"]. +Hint Unfold GPRstr : sail. +Definition CIA_fp := RFull ("CIA"). +Hint Unfold CIA_fp : sail. +Definition NIA_fp := RFull ("NIA"). +Hint Unfold NIA_fp : sail. +Definition initial_analysis (instr : ast) +: M ((list regfp * list regfp * list regfp * list niafp * diafp * instruction_kind)) := + + let iR := [] : regfps in + let oR := [] : regfps in + let aR := [] : regfps in + let ik := (IK_simple (tt)) : instruction_kind in + let Nias := [NIAFP_successor (tt)] : niafps in + let Dia := (DIAFP_none (tt)) : diafp in + (match instr with + | EBREAK (tt) => returnm (Nias, aR, iR, ik, oR) + | UTYPE (imm,rd,op) => + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | RISCV_JAL (imm,rd) => + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + let offset : bits 64 := EXTS 64 imm in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__0 : xlenbits => + let Nias : niafps := [NIAFP_concrete_address (add_vec w__0 offset)] in + let ik : instruction_kind := IK_branch (tt) in + returnm (Nias, aR, iR, ik, oR) + | RISCV_JALR (imm,rs,rd) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + let offset : bits 64 := EXTS 64 imm in + let Nias : niafps := [NIAFP_indirect_address (tt)] in + let ik : instruction_kind := IK_branch (tt) in + returnm (Nias, aR, iR, ik, oR) + | BTYPE (imm,rs2,rs1,op) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs2)))) :: iR in + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let ik := (IK_branch (tt)) : instruction_kind in + let offset : bits 64 := EXTS 64 imm in + ((read_reg PC_ref) : M (mword 64)) >>= fun w__1 : xlenbits => + let Nias : niafps := [NIAFP_concrete_address (add_vec w__1 offset);NIAFP_successor (tt)] in + returnm (Nias, aR, iR, ik, oR) + | ITYPE (imm,rs,rd,op) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | SHIFTIOP (imm,rs,rd,op) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | RTYPE (rs2,rs1,rd,op) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs2)))) :: iR in + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | CSR (csr,rs1,rd,is_imm,op) => + let isWrite : bool := + match op with + | CSRRW => true + | _ => if (is_imm) then neq_int (projT1 (uint rs1)) 0 else neq_int (projT1 (uint rs1)) 0 + end in + let iR : regfps := (RFull (csr_name csr)) :: iR in + let iR : regfps := + if ((negb is_imm)) then + (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR + else iR in + let oR : regfps := if (isWrite) then (RFull (csr_name csr)) :: oR else oR in + let oR : regfps := (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | LOAD (imm,rs,rd,unsign,width,aq,rl) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + let aR := iR : regfps in + (match (aq, rl) with + | (false, false) => returnm ((IK_mem_read (Read_plain)) : instruction_kind ) + | (true, false) => returnm ((IK_mem_read (Read_RISCV_acquire)) : instruction_kind ) + | (true, true) => returnm ((IK_mem_read (Read_RISCV_strong_acquire)) : instruction_kind ) + | _ => + (internal_error "LOAD type not implemented in initial_analysis") : M (instruction_kind) + end) >>= fun w__3 : instruction_kind => + let ik : instruction_kind := w__3 in + returnm (Nias, aR, iR, ik, oR) + | STORE (imm,rs2,rs1,width,aq,rl) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs2)))) :: iR in + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let aR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then aR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: aR in + (match (aq, rl) with + | (false, false) => returnm ((IK_mem_write (Write_plain)) : instruction_kind ) + | (false, true) => returnm ((IK_mem_write (Write_RISCV_release)) : instruction_kind ) + | (true, true) => returnm ((IK_mem_write (Write_RISCV_strong_release)) : instruction_kind ) + | _ => + (internal_error "STORE type not implemented in initial_analysis") : M (instruction_kind) + end) >>= fun w__5 : instruction_kind => + let ik : instruction_kind := w__5 in + returnm (Nias, aR, iR, ik, oR) + | ADDIW (imm,rs,rd) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | SHIFTW (imm,rs,rd,op) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | RTYPEW (rs2,rs1,rd,op) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs2)))) :: iR in + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + returnm (Nias, aR, iR, ik, oR) + | FENCE (pred,succ) => + (match (pred, succ) with + | (v__844, v__845) => + (if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) + then + returnm ((IK_barrier + (Barrier_RISCV_rw_rw)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B1;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_r_rw)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B1;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_r_r)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_rw_w)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_w_w)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_w_rw)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_rw_r)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B1;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_r_w)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B0;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B1;B0] : mword (1 - 0 + 1))))) then + returnm ((IK_barrier + (Barrier_RISCV_w_r)) + : instruction_kind ) + else if ((andb + (eq_vec (subrange_vec_dec v__844 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__845 1 0) + (vec_of_bits [B0;B0] : mword (1 - 0 + 1))))) then + returnm ((IK_simple + (tt)) + : instruction_kind ) + else + (internal_error "barrier type not implemented in initial_analysis") + : M (instruction_kind)) + : M (instruction_kind) + end) >>= fun w__17 : instruction_kind => + let ik : instruction_kind := w__17 in + returnm (Nias, aR, iR, ik, oR) + | FENCE_TSO (pred,succ) => + (match (pred, succ) with + | (v__884, v__885) => + (if ((andb + (eq_vec (subrange_vec_dec v__884 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))) + (eq_vec (subrange_vec_dec v__885 1 0) (vec_of_bits [B1;B1] : mword (1 - 0 + 1))))) + then + returnm ((IK_barrier + (Barrier_RISCV_tso)) + : instruction_kind ) + else + (internal_error "barrier type not implemented in initial_analysis") + : M (instruction_kind)) + : M (instruction_kind) + end) >>= fun w__20 : instruction_kind => + let ik : instruction_kind := w__20 in + returnm (Nias, aR, iR, ik, oR) + | FENCEI (tt) => + let ik : instruction_kind := IK_simple (tt) in + returnm (Nias, aR, iR, ik, oR) + | LOADRES (aq,rl,rs1,width,rd) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + let aR := iR : regfps in + (match (aq, rl) with + | (false, false) => returnm ((IK_mem_read (Read_RISCV_reserved)) : instruction_kind ) + | (true, false) => + returnm ((IK_mem_read (Read_RISCV_reserved_acquire)) : instruction_kind ) + | (true, true) => + returnm ((IK_mem_read (Read_RISCV_reserved_strong_acquire)) : instruction_kind ) + | (false, true) => + (internal_error "LOADRES type not implemented in initial_analysis") + : M (instruction_kind) + end) >>= fun w__22 : instruction_kind => + let ik : instruction_kind := w__22 in + returnm (Nias, aR, iR, ik, oR) + | STORECON (aq,rl,rs2,rs1,width,rd) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs2)))) :: iR in + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let aR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then aR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: aR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + (match (aq, rl) with + | (false, false) => returnm ((IK_mem_write (Write_RISCV_conditional)) : instruction_kind ) + | (false, true) => + returnm ((IK_mem_write (Write_RISCV_conditional_release)) : instruction_kind ) + | (true, true) => + returnm ((IK_mem_write (Write_RISCV_conditional_strong_release)) : instruction_kind ) + | (true, false) => + (internal_error "STORECON type not implemented in initial_analysis") + : M (instruction_kind) + end) >>= fun w__24 : instruction_kind => + let ik : instruction_kind := w__24 in + returnm (Nias, aR, iR, ik, oR) + | AMO (op,aq,rl,rs2,rs1,width,rd) => + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs2)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs2)))) :: iR in + let iR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then iR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: iR in + let aR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rs1)) 0)) then aR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rs1)))) :: aR in + let oR : regfps := + if sumbool_of_bool ((Z.eqb (projT1 (regbits_to_regno rd)) 0)) then oR + else (RFull (vec_access_dec GPRstr (projT1 (regbits_to_regno rd)))) :: oR in + let ik : instruction_kind := + match (aq, rl) with + | (false, false) => IK_mem_rmw ((Read_RISCV_reserved, Write_RISCV_conditional)) + | (false, true) => IK_mem_rmw ((Read_RISCV_reserved, Write_RISCV_conditional_release)) + | (true, false) => IK_mem_rmw ((Read_RISCV_reserved_acquire, Write_RISCV_conditional)) + | (true, true) => + IK_mem_rmw ((Read_RISCV_reserved_acquire, Write_RISCV_conditional_release)) + end in + returnm (Nias, aR, iR, ik, oR) + | _ => returnm (Nias, aR, iR, ik, oR) + end) >>= fun '(Nias, aR, iR, ik, oR) => + returnm (iR, oR, aR, Nias, Dia, ik). + +Definition initial_regstate : regstate := +{| tlb39 := None; + htif_exit_code := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + htif_done := false; + htif_tohost := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mtimecmp := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + tselect := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + stval := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + scause := + ({| Mcause_Mcause_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + sepc := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + sscratch := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + stvec := + ({| Mtvec_Mtvec_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + satp := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + sideleg := + ({| Sinterrupts_Sinterrupts_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + sedeleg := + ({| Sedeleg_Sedeleg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + pmpcfg0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + pmpaddr0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mhartid := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + marchid := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mimpid := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mvendorid := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + minstret_written := false; + minstret := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mtime := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mcycle := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + scounteren := + ({| Counteren_Counteren_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) |}); + mcounteren := + ({| Counteren_Counteren_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] + : mword 32) |}); + mscratch := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mtval := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mepc := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + mcause := + ({| Mcause_Mcause_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + mtvec := + ({| Mtvec_Mtvec_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + medeleg := + ({| Medeleg_Medeleg_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + mideleg := + ({| Minterrupts_Minterrupts_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + mie := + ({| Minterrupts_Minterrupts_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + mip := + ({| Minterrupts_Minterrupts_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + mstatus := + ({| Mstatus_Mstatus_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + misa := + ({| Misa_Misa_chunk_0 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}); + cur_inst := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + cur_privilege := User; + x31 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x30 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x29 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x28 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x27 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x26 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x25 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x24 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x23 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x22 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x21 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x20 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x19 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x18 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x17 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x16 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x15 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x14 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x13 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x12 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x11 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x10 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x9 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x8 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x7 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x6 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x5 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x4 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x3 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x2 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + x1 := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + Xs := + (vec_of_list_len [(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64);(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64)]); + instbits := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + nextPC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64); + PC := + (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0; + B0] + : mword 64) |}. +Hint Unfold initial_regstate : sail. + +End Content. diff --git a/snapshots/coq/riscv/riscv_extras.v b/snapshots/coq/riscv/riscv_extras.v new file mode 100644 index 00000000..ff235a98 --- /dev/null +++ b/snapshots/coq/riscv/riscv_extras.v @@ -0,0 +1,145 @@ +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import String. +Require Import List. +Import List.ListNotations. + +Axiom real : Type. + +Definition MEM_fence_rw_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_rw. +Definition MEM_fence_r_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_rw. +Definition MEM_fence_r_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_r. +Definition MEM_fence_rw_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_w. +Definition MEM_fence_w_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_w. +Definition MEM_fence_w_rw {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_rw. +Definition MEM_fence_rw_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_rw_r. +Definition MEM_fence_r_w {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_r_w. +Definition MEM_fence_w_r {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_w_r. +Definition MEM_fence_tso {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_tso. +Definition MEM_fence_i {rv e} (_:unit) : monad rv unit e := barrier Barrier_RISCV_i. +(* +val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e +val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e +val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e +val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e +val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e +val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e +*) +Definition MEMea {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_plain addr size. +Definition MEMea_release {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_release addr size. +Definition MEMea_strong_release {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_strong_release addr size. +Definition MEMea_conditional {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional addr size. +Definition MEMea_conditional_release {rv a e} (addr : mword a) size : monad rv unit e := write_mem_ea Write_RISCV_conditional_release addr size. +Definition MEMea_conditional_strong_release {rv a e} (addr : mword a) size : monad rv unit e + := write_mem_ea Write_RISCV_conditional_strong_release addr size. + + +(* Some wrappers copied from aarch64_extras *) +(* TODO: Harmonise into a common library *) +(* +Definition get_slice_int_bl len n lo := + (* TODO: Is this the intended behaviour? *) + let hi := lo + len - 1 in + let bs := bools_of_int (hi + 1) n in + subrange_list false bs hi lo + +val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a +Definition get_slice_int len n lo := of_bools (get_slice_int_bl len n lo) +*) +Definition write_ram {rv e} m size (hexRAM : mword m) (addr : mword m) (data : mword (8 * size)) : monad rv bool e := + write_mem_val data. + +Definition read_ram {rv e} m size `{ArithFact (size >= 0)} (_ : mword m) (addr : mword m) : monad rv (mword (8 * size)) e := + read_mem Read_plain addr size. +(* +Definition string_of_bits bs := string_of_bv (bits_of bs). +Definition string_of_int := show + +Definition _sign_extend bits len := maybe_failwith (of_bits (exts_bv len bits)) +Definition _zero_extend bits len := maybe_failwith (of_bits (extz_bv len bits)) +*) +Definition shift_bits_left {a b} (v : mword a) (n : mword b) : mword a := + shiftl v (int_of_mword false n). + +Definition shift_bits_right {a b} (v : mword a) (n : mword b) : mword a := + shiftr v (int_of_mword false n). + +Definition shift_bits_right_arith {a b} (v : mword a) (n : mword b) : mword a := + arith_shiftr v (int_of_mword false n). + +(* Use constants for undefined values for now *) +Definition internal_pick {rv a e} (vs : list a) : monad rv a e := +match vs with +| (h::_) => returnm h +| _ => Fail "empty list in internal_pick" +end. +Definition undefined_string {rv e} (_:unit) : monad rv string e := returnm ""%string. +Definition undefined_unit {rv e} (_:unit) : monad rv unit e := returnm tt. +Definition undefined_int {rv e} (_:unit) : monad rv Z e := returnm (0:ii). +(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) +Definition undefined_vector {rv a e} len (u : a) `{ArithFact (len >= 0)} : monad rv (vec a len) e := returnm (vec_init u len). +(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +Definition undefined_bitvector {rv e} len `{ArithFact (len >= 0)} : monad rv (mword len) e := returnm (mword_of_int 0). +(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +Definition undefined_bits {rv e} := @undefined_bitvector rv e. +Definition undefined_bit {rv e} (_:unit) : monad rv bitU e := returnm BU. +(*Definition undefined_real {rv e} (_:unit) : monad rv real e := returnm (realFromFrac 0 1).*) +Definition undefined_range {rv e} i j `{ArithFact (i <= j)} : monad rv {z : Z & ArithFact (i <= z /\ z <= j)} e := returnm (build_ex i). +Definition undefined_atom {rv e} i : monad rv Z e := returnm i. +Definition undefined_nat {rv e} (_:unit) : monad rv Z e := returnm (0:ii). + +Definition skip {rv e} (_:unit) : monad rv unit e := returnm tt. + +(*val elf_entry : unit -> integer*) +Definition elf_entry (_:unit) : Z := 0. +(*declare ocaml target_rep function elf_entry := `Elf_loader.elf_entry`*) + +Definition print_bits {n} msg (bs : mword n) := prerr_endline (msg ++ (string_of_bits bs)). + +(*val get_time_ns : unit -> integer*) +Definition get_time_ns (_:unit) : Z := 0. +(*declare ocaml target_rep function get_time_ns := `(fun () -> Big_int.of_int (int_of_float (1e9 *. Unix.gettimeofday ())))`*) + +Definition eq_bit (x : bitU) (y : bitU) : bool := + match x, y with + | B0, B0 => true + | B1, B1 => true + | BU, BU => true + | _,_ => false + end. + +Require Import Zeuclid. +Definition euclid_modulo (m n : Z) `{ArithFact (n > 0)} : {z : Z & ArithFact (0 <= z <= n-1)}. +apply existT with (x := ZEuclid.modulo m n). +constructor. +destruct H. +assert (Z.abs n = n). { rewrite Z.abs_eq; auto with zarith. } +rewrite <- H at 3. +lapply (ZEuclid.mod_always_pos m n); omega. +Qed. + +(* Override the more general version *) + +Definition mults_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mults_vec l r. +Definition mult_vec {n} (l : mword n) (r : mword n) : mword (2 * n) := mult_vec l r. + + +Definition print_endline (_:string) : unit := tt. +Definition prerr_endline (_:string) : unit := tt. +Definition prerr_string (_:string) : unit := tt. +Definition putchar {T} (_:T) : unit := tt. +Require DecimalString. +Definition string_of_int z := DecimalString.NilZero.string_of_int (Z.to_int z). + +(* The constraint solver can do this itself, but a Coq bug puts + anonymous_subproof into the term instead of an actual subproof. *) +Lemma n_leading_spaces_fact {w__0} : + w__0 >= 0 -> exists ex17629_ : Z, 1 + w__0 = 1 + ex17629_ /\ 0 <= ex17629_. +intro. +exists w__0. +omega. +Qed. +Hint Resolve n_leading_spaces_fact : sail. diff --git a/snapshots/coq/riscv/riscv_types.v b/snapshots/coq/riscv/riscv_types.v new file mode 100644 index 00000000..963f498d --- /dev/null +++ b/snapshots/coq/riscv/riscv_types.v @@ -0,0 +1,1428 @@ +(*Generated by Sail from riscv.*) +Require Import Sail2_instr_kinds. +Require Import Sail2_values. +Require Import Sail2_string. +Require Import Sail2_real. +Require Import Sail2_operators_mwords. +Require Import Sail2_prompt_monad. +Require Import Sail2_prompt. +Require Import Sail2_state. +Definition bits (n : Z) : Type := mword n. + + + +Definition xlenbits : Type := bits 64. + +Definition half : Type := bits 16. + +Definition word : Type := bits 32. + +Definition regbits : Type := bits 5. + +Definition cregbits : Type := bits 3. + +Definition csreg : Type := bits 12. + +Definition regno (n : Z)`{ArithFact (0 <= n /\ (n + 1) <= 32)} : Type := Z. + +Definition opcode : Type := bits 7. + +Definition imm12 : Type := bits 12. + +Definition imm20 : Type := bits 20. + +Definition amo : Type := bits 1. + +Inductive Architecture := RV32 | RV64 | RV128. +Scheme Equality for Architecture. +Instance Decidable_eq_Architecture : +forall (x y : Architecture), Decidable (x = y) := +Decidable_eq_from_dec Architecture_eq_dec. + + +Definition arch_xlen : Type := bits 2. + +Definition priv_level : Type := bits 2. + +Inductive Privilege := User | Supervisor | Machine. +Scheme Equality for Privilege. +Instance Decidable_eq_Privilege : +forall (x y : Privilege), Decidable (x = y) := +Decidable_eq_from_dec Privilege_eq_dec. + + +Inductive AccessType := Read | Write | ReadWrite | Execute. +Scheme Equality for AccessType. +Instance Decidable_eq_AccessType : +forall (x y : AccessType), Decidable (x = y) := +Decidable_eq_from_dec AccessType_eq_dec. + + +Inductive ReadType := Instruction | Data. +Scheme Equality for ReadType. +Instance Decidable_eq_ReadType : +forall (x y : ReadType), Decidable (x = y) := +Decidable_eq_from_dec ReadType_eq_dec. + + +Inductive word_width := BYTE | HALF | WORD | DOUBLE. +Scheme Equality for word_width. +Instance Decidable_eq_word_width : +forall (x y : word_width), Decidable (x = y) := +Decidable_eq_from_dec word_width_eq_dec. + + +Definition exc_code : Type := bits 4. + +Inductive InterruptType := + I_U_Software + | I_S_Software + | I_M_Software + | I_U_Timer + | I_S_Timer + | I_M_Timer + | I_U_External + | I_S_External + | I_M_External. +Scheme Equality for InterruptType. +Instance Decidable_eq_InterruptType : +forall (x y : InterruptType), Decidable (x = y) := +Decidable_eq_from_dec InterruptType_eq_dec. + + +Inductive ExceptionType := + E_Fetch_Addr_Align + | E_Fetch_Access_Fault + | E_Illegal_Instr + | E_Breakpoint + | E_Load_Addr_Align + | E_Load_Access_Fault + | E_SAMO_Addr_Align + | E_SAMO_Access_Fault + | E_U_EnvCall + | E_S_EnvCall + | E_Reserved_10 + | E_M_EnvCall + | E_Fetch_Page_Fault + | E_Load_Page_Fault + | E_Reserved_14 + | E_SAMO_Page_Fault. +Scheme Equality for ExceptionType. +Instance Decidable_eq_ExceptionType : +forall (x y : ExceptionType), Decidable (x = y) := +Decidable_eq_from_dec ExceptionType_eq_dec. + + +Inductive exception := + Error_not_implemented : string -> exception | Error_internal_error : unit -> exception. +Arguments exception : clear implicits. + + + +Definition tv_mode : Type := bits 2. + +Inductive TrapVectorMode := TV_Direct | TV_Vector | TV_Reserved. +Scheme Equality for TrapVectorMode. +Instance Decidable_eq_TrapVectorMode : +forall (x y : TrapVectorMode), Decidable (x = y) := +Decidable_eq_from_dec TrapVectorMode_eq_dec. + + +Definition ext_status : Type := bits 2. + +Inductive ExtStatus := Off | Initial | Clean | Dirty. +Scheme Equality for ExtStatus. +Instance Decidable_eq_ExtStatus : +forall (x y : ExtStatus), Decidable (x = y) := +Decidable_eq_from_dec ExtStatus_eq_dec. + + +Definition satp_mode : Type := bits 4. + +Inductive SATPMode := Sbare | Sv32 | Sv39. +Scheme Equality for SATPMode. +Instance Decidable_eq_SATPMode : +forall (x y : SATPMode), Decidable (x = y) := +Decidable_eq_from_dec SATPMode_eq_dec. + + +Definition csrRW : Type := bits 2. + +Inductive uop := RISCV_LUI | RISCV_AUIPC. +Scheme Equality for uop. +Instance Decidable_eq_uop : +forall (x y : uop), Decidable (x = y) := +Decidable_eq_from_dec uop_eq_dec. + + +Inductive bop := RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU. +Scheme Equality for bop. +Instance Decidable_eq_bop : +forall (x y : bop), Decidable (x = y) := +Decidable_eq_from_dec bop_eq_dec. + + +Inductive iop := RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI. +Scheme Equality for iop. +Instance Decidable_eq_iop : +forall (x y : iop), Decidable (x = y) := +Decidable_eq_from_dec iop_eq_dec. + + +Inductive sop := RISCV_SLLI | RISCV_SRLI | RISCV_SRAI. +Scheme Equality for sop. +Instance Decidable_eq_sop : +forall (x y : sop), Decidable (x = y) := +Decidable_eq_from_dec sop_eq_dec. + + +Inductive rop := + RISCV_ADD + | RISCV_SUB + | RISCV_SLL + | RISCV_SLT + | RISCV_SLTU + | RISCV_XOR + | RISCV_SRL + | RISCV_SRA + | RISCV_OR + | RISCV_AND. +Scheme Equality for rop. +Instance Decidable_eq_rop : +forall (x y : rop), Decidable (x = y) := +Decidable_eq_from_dec rop_eq_dec. + + +Inductive ropw := RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW. +Scheme Equality for ropw. +Instance Decidable_eq_ropw : +forall (x y : ropw), Decidable (x = y) := +Decidable_eq_from_dec ropw_eq_dec. + + +Inductive sopw := RISCV_SLLIW | RISCV_SRLIW | RISCV_SRAIW. +Scheme Equality for sopw. +Instance Decidable_eq_sopw : +forall (x y : sopw), Decidable (x = y) := +Decidable_eq_from_dec sopw_eq_dec. + + +Inductive amoop := AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU. +Scheme Equality for amoop. +Instance Decidable_eq_amoop : +forall (x y : amoop), Decidable (x = y) := +Decidable_eq_from_dec amoop_eq_dec. + + +Inductive csrop := CSRRW | CSRRS | CSRRC. +Scheme Equality for csrop. +Instance Decidable_eq_csrop : +forall (x y : csrop), Decidable (x = y) := +Decidable_eq_from_dec csrop_eq_dec. + + +Record Misa := { Misa_Misa_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Misa_Misa_chunk_0' := e ]}" := ({| Misa_Misa_chunk_0 := e |}). + +Record SV39_PTE := { SV39_PTE_SV39_PTE_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'SV39_PTE_SV39_PTE_chunk_0' := e ]}" := ({| SV39_PTE_SV39_PTE_chunk_0 := e |}). + +Record PTE_Bits := { PTE_Bits_PTE_Bits_chunk_0 : mword 8; }. +Notation "{[ r 'with' 'PTE_Bits_PTE_Bits_chunk_0' := e ]}" := ({| PTE_Bits_PTE_Bits_chunk_0 := e |}). + +Record Mstatus := { Mstatus_Mstatus_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Mstatus_Mstatus_chunk_0' := e ]}" := ({| Mstatus_Mstatus_chunk_0 := e |}). + +Record Sstatus := { Sstatus_Sstatus_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Sstatus_Sstatus_chunk_0' := e ]}" := ({| Sstatus_Sstatus_chunk_0 := e |}). + +Record Minterrupts := { Minterrupts_Minterrupts_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Minterrupts_Minterrupts_chunk_0' := e ]}" := ({| Minterrupts_Minterrupts_chunk_0 := e |}). + +Record Sinterrupts := { Sinterrupts_Sinterrupts_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Sinterrupts_Sinterrupts_chunk_0' := e ]}" := ({| Sinterrupts_Sinterrupts_chunk_0 := e |}). + +Record Medeleg := { Medeleg_Medeleg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Medeleg_Medeleg_chunk_0' := e ]}" := ({| Medeleg_Medeleg_chunk_0 := e |}). + +Record Sedeleg := { Sedeleg_Sedeleg_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Sedeleg_Sedeleg_chunk_0' := e ]}" := ({| Sedeleg_Sedeleg_chunk_0 := e |}). + +Record Mtvec := { Mtvec_Mtvec_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Mtvec_Mtvec_chunk_0' := e ]}" := ({| Mtvec_Mtvec_chunk_0 := e |}). + +Record Satp64 := { Satp64_Satp64_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Satp64_Satp64_chunk_0' := e ]}" := ({| Satp64_Satp64_chunk_0 := e |}). + +Record Mcause := { Mcause_Mcause_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'Mcause_Mcause_chunk_0' := e ]}" := ({| Mcause_Mcause_chunk_0 := e |}). + +Record Counteren := { Counteren_Counteren_chunk_0 : mword 32; }. +Notation "{[ r 'with' 'Counteren_Counteren_chunk_0' := e ]}" := ({| Counteren_Counteren_chunk_0 := e |}). + +Record sync_exception := + { sync_exception_trap : ExceptionType; sync_exception_excinfo : option xlenbits; }. +Notation "{[ r 'with' 'sync_exception_trap' := e ]}" := ({| sync_exception_trap := e; sync_exception_excinfo := sync_exception_excinfo r |}). +Notation "{[ r 'with' 'sync_exception_excinfo' := e ]}" := ({| sync_exception_excinfo := e; sync_exception_trap := sync_exception_trap r |}). + +Inductive ctl_result := + CTL_TRAP : sync_exception -> ctl_result + | CTL_SRET : unit -> ctl_result + | CTL_MRET : unit -> ctl_result. +Arguments ctl_result : clear implicits. + + + +Inductive MemoryOpResult {a : Type} := + MemValue : a -> MemoryOpResult | MemException : ExceptionType -> MemoryOpResult. +Arguments MemoryOpResult : clear implicits. + + + +Record htif_cmd := { htif_cmd_htif_cmd_chunk_0 : mword 64; }. +Notation "{[ r 'with' 'htif_cmd_htif_cmd_chunk_0' := e ]}" := ({| htif_cmd_htif_cmd_chunk_0 := e |}). + +Definition pteAttribs : Type := bits 8. + +Inductive PTW_Error := + PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update. +Scheme Equality for PTW_Error. +Instance Decidable_eq_PTW_Error : +forall (x y : PTW_Error), Decidable (x = y) := +Decidable_eq_from_dec PTW_Error_eq_dec. + + +Definition vaddr39 : Type := bits 39. + +Definition paddr39 : Type := bits 56. + +Definition pte39 : Type := xlenbits. + +Record SV39_Vaddr := { SV39_Vaddr_SV39_Vaddr_chunk_0 : mword 39; }. +Notation "{[ r 'with' 'SV39_Vaddr_SV39_Vaddr_chunk_0' := e ]}" := ({| SV39_Vaddr_SV39_Vaddr_chunk_0 := e |}). + +Record SV39_Paddr := { SV39_Paddr_SV39_Paddr_chunk_0 : mword 56; }. +Notation "{[ r 'with' 'SV39_Paddr_SV39_Paddr_chunk_0' := e ]}" := ({| SV39_Paddr_SV39_Paddr_chunk_0 := e |}). + +Definition asid64 : Type := bits 16. + +Inductive PTW_Result := + PTW_Success : (paddr39 * SV39_PTE * paddr39 * {n : Z & ArithFact (n >= 0)} * bool) -> PTW_Result + | PTW_Failure : PTW_Error -> PTW_Result. +Arguments PTW_Result : clear implicits. + + + +Record TLB39_Entry := + { TLB39_Entry_asid : asid64; + TLB39_Entry_global : bool; + TLB39_Entry_vAddr : vaddr39; + TLB39_Entry_pAddr : paddr39; + TLB39_Entry_vMatchMask : vaddr39; + TLB39_Entry_vAddrMask : vaddr39; + TLB39_Entry_pte : SV39_PTE; + TLB39_Entry_pteAddr : paddr39; + TLB39_Entry_age : xlenbits; }. +Notation "{[ r 'with' 'TLB39_Entry_asid' := e ]}" := ({| TLB39_Entry_asid := e; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_global' := e ]}" := ({| TLB39_Entry_global := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_vAddr' := e ]}" := ({| TLB39_Entry_vAddr := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_pAddr' := e ]}" := ({| TLB39_Entry_pAddr := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_vMatchMask' := e ]}" := ({| TLB39_Entry_vMatchMask := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_vAddrMask' := e ]}" := ({| TLB39_Entry_vAddrMask := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_pte' := e ]}" := ({| TLB39_Entry_pte := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_pteAddr' := e ]}" := ({| TLB39_Entry_pteAddr := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_age := TLB39_Entry_age r |}). +Notation "{[ r 'with' 'TLB39_Entry_age' := e ]}" := ({| TLB39_Entry_age := e; TLB39_Entry_asid := TLB39_Entry_asid r; TLB39_Entry_global := TLB39_Entry_global r; TLB39_Entry_vAddr := TLB39_Entry_vAddr r; TLB39_Entry_pAddr := TLB39_Entry_pAddr r; TLB39_Entry_vMatchMask := TLB39_Entry_vMatchMask r; TLB39_Entry_vAddrMask := TLB39_Entry_vAddrMask r; TLB39_Entry_pte := TLB39_Entry_pte r; TLB39_Entry_pteAddr := TLB39_Entry_pteAddr r |}). + +Inductive TR39_Result := + TR39_Address : paddr39 -> TR39_Result | TR39_Failure : PTW_Error -> TR39_Result. +Arguments TR39_Result : clear implicits. + + + +Inductive TR_Result := TR_Address : xlenbits -> TR_Result | TR_Failure : ExceptionType -> TR_Result. +Arguments TR_Result : clear implicits. + + + +Inductive ast := + UTYPE : (bits 20 * regbits * uop) -> ast + | RISCV_JAL : (bits 21 * regbits) -> ast + | RISCV_JALR : (bits 12 * regbits * regbits) -> ast + | BTYPE : (bits 13 * regbits * regbits * bop) -> ast + | ITYPE : (bits 12 * regbits * regbits * iop) -> ast + | SHIFTIOP : (bits 6 * regbits * regbits * sop) -> ast + | RTYPE : (regbits * regbits * regbits * rop) -> ast + | LOAD : (bits 12 * regbits * regbits * bool * word_width * bool * bool) -> ast + | STORE : (bits 12 * regbits * regbits * word_width * bool * bool) -> ast + | ADDIW : (bits 12 * regbits * regbits) -> ast + | SHIFTW : (bits 5 * regbits * regbits * sop) -> ast + | RTYPEW : (regbits * regbits * regbits * ropw) -> ast + | SHIFTIWOP : (bits 5 * regbits * regbits * sopw) -> ast + | MUL : (regbits * regbits * regbits * bool * bool * bool) -> ast + | DIV : (regbits * regbits * regbits * bool) -> ast + | REM : (regbits * regbits * regbits * bool) -> ast + | MULW : (regbits * regbits * regbits) -> ast + | DIVW : (regbits * regbits * regbits * bool) -> ast + | REMW : (regbits * regbits * regbits * bool) -> ast + | FENCE : (bits 4 * bits 4) -> ast + | FENCE_TSO : (bits 4 * bits 4) -> ast + | FENCEI : unit -> ast + | ECALL : unit -> ast + | MRET : unit -> ast + | SRET : unit -> ast + | EBREAK : unit -> ast + | WFI : unit -> ast + | SFENCE_VMA : (regbits * regbits) -> ast + | LOADRES : (bool * bool * regbits * word_width * regbits) -> ast + | STORECON : (bool * bool * regbits * regbits * word_width * regbits) -> ast + | AMO : (amoop * bool * bool * regbits * regbits * word_width * regbits) -> ast + | CSR : (bits 12 * regbits * regbits * bool * csrop) -> ast + | C_NOP : unit -> ast + | C_ADDI4SPN : (cregbits * bits 8) -> ast + | C_LW : (bits 5 * cregbits * cregbits) -> ast + | C_LD : (bits 5 * cregbits * cregbits) -> ast + | C_SW : (bits 5 * cregbits * cregbits) -> ast + | C_SD : (bits 5 * cregbits * cregbits) -> ast + | C_ADDI : (bits 6 * regbits) -> ast + | C_JAL : bits 11 -> ast + | C_ADDIW : (bits 6 * regbits) -> ast + | C_LI : (bits 6 * regbits) -> ast + | C_ADDI16SP : bits 6 -> ast + | C_LUI : (bits 6 * regbits) -> ast + | C_SRLI : (bits 6 * cregbits) -> ast + | C_SRAI : (bits 6 * cregbits) -> ast + | C_ANDI : (bits 6 * cregbits) -> ast + | C_SUB : (cregbits * cregbits) -> ast + | C_XOR : (cregbits * cregbits) -> ast + | C_OR : (cregbits * cregbits) -> ast + | C_AND : (cregbits * cregbits) -> ast + | C_SUBW : (cregbits * cregbits) -> ast + | C_ADDW : (cregbits * cregbits) -> ast + | C_J : bits 11 -> ast + | C_BEQZ : (bits 8 * cregbits) -> ast + | C_BNEZ : (bits 8 * cregbits) -> ast + | C_SLLI : (bits 6 * regbits) -> ast + | C_LWSP : (bits 6 * regbits) -> ast + | C_LDSP : (bits 6 * regbits) -> ast + | C_SWSP : (bits 6 * regbits) -> ast + | C_SDSP : (bits 6 * regbits) -> ast + | C_JR : regbits -> ast + | C_JALR : regbits -> ast + | C_MV : (regbits * regbits) -> ast + | C_EBREAK : unit -> ast + | C_ADD : (regbits * regbits) -> ast + | STOP_FETCHING : unit -> ast + | THREAD_START : unit -> ast + | ILLEGAL : word -> ast + | C_ILLEGAL : half -> ast. +Arguments ast : clear implicits. + + + +Inductive regfp := + RFull : string -> regfp + | RSlice : (string * {n : Z & ArithFact (n >= 0)} * {n : Z & ArithFact (n >= 0)}) -> regfp + | RSliceBit : (string * {n : Z & ArithFact (n >= 0)}) -> regfp + | RField : (string * string) -> regfp. +Arguments regfp : clear implicits. + + + +Definition regfps : Type := list regfp. + +Inductive niafp := + NIAFP_successor : unit -> niafp + | NIAFP_concrete_address : bits 64 -> niafp + | NIAFP_indirect_address : unit -> niafp. +Arguments niafp : clear implicits. + + + +Definition niafps : Type := list niafp. + +Inductive diafp := + DIAFP_none : unit -> diafp | DIAFP_concrete : bits 64 -> diafp | DIAFP_reg : regfp -> diafp. +Arguments diafp : clear implicits. + + + + + + + + + + + + + +Inductive register_value := + Regval_vector : (Z * bool * list register_value) -> register_value + | Regval_list : list register_value -> register_value + | Regval_option : option register_value -> register_value + | Regval_Counteren : Counteren -> register_value + | Regval_Mcause : Mcause -> register_value + | Regval_Medeleg : Medeleg -> register_value + | Regval_Minterrupts : Minterrupts -> register_value + | Regval_Misa : Misa -> register_value + | Regval_Mstatus : Mstatus -> register_value + | Regval_Mtvec : Mtvec -> register_value + | Regval_Privilege : Privilege -> register_value + | Regval_Sedeleg : Sedeleg -> register_value + | Regval_Sinterrupts : Sinterrupts -> register_value + | Regval_TLB39_Entry : TLB39_Entry -> register_value + | Regval_bool : bool -> register_value + | Regval_vector_64_dec_bit : mword 64 -> register_value. +Arguments register_value : clear implicits. + + + +Record regstate := + { tlb39 : option TLB39_Entry; + htif_exit_code : mword 64; + htif_done : bool; + htif_tohost : mword 64; + mtimecmp : mword 64; + tselect : mword 64; + stval : mword 64; + scause : Mcause; + sepc : mword 64; + sscratch : mword 64; + stvec : Mtvec; + satp : mword 64; + sideleg : Sinterrupts; + sedeleg : Sedeleg; + pmpcfg0 : mword 64; + pmpaddr0 : mword 64; + mhartid : mword 64; + marchid : mword 64; + mimpid : mword 64; + mvendorid : mword 64; + minstret_written : bool; + minstret : mword 64; + mtime : mword 64; + mcycle : mword 64; + scounteren : Counteren; + mcounteren : Counteren; + mscratch : mword 64; + mtval : mword 64; + mepc : mword 64; + mcause : Mcause; + mtvec : Mtvec; + medeleg : Medeleg; + mideleg : Minterrupts; + mie : Minterrupts; + mip : Minterrupts; + mstatus : Mstatus; + misa : Misa; + cur_inst : mword 64; + cur_privilege : Privilege; + x31 : mword 64; + x30 : mword 64; + x29 : mword 64; + x28 : mword 64; + x27 : mword 64; + x26 : mword 64; + x25 : mword 64; + x24 : mword 64; + x23 : mword 64; + x22 : mword 64; + x21 : mword 64; + x20 : mword 64; + x19 : mword 64; + x18 : mword 64; + x17 : mword 64; + x16 : mword 64; + x15 : mword 64; + x14 : mword 64; + x13 : mword 64; + x12 : mword 64; + x11 : mword 64; + x10 : mword 64; + x9 : mword 64; + x8 : mword 64; + x7 : mword 64; + x6 : mword 64; + x5 : mword 64; + x4 : mword 64; + x3 : mword 64; + x2 : mword 64; + x1 : mword 64; + Xs : vec (mword 64) 32; + instbits : mword 64; + nextPC : mword 64; + PC : mword 64; }. +Notation "{[ r 'with' 'tlb39' := e ]}" := ({| tlb39 := e; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'htif_exit_code' := e ]}" := ({| htif_exit_code := e; tlb39 := tlb39 r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'htif_done' := e ]}" := ({| htif_done := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'htif_tohost' := e ]}" := ({| htif_tohost := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mtimecmp' := e ]}" := ({| mtimecmp := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'tselect' := e ]}" := ({| tselect := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'stval' := e ]}" := ({| stval := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'scause' := e ]}" := ({| scause := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'sepc' := e ]}" := ({| sepc := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'sscratch' := e ]}" := ({| sscratch := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'stvec' := e ]}" := ({| stvec := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'satp' := e ]}" := ({| satp := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'sideleg' := e ]}" := ({| sideleg := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'sedeleg' := e ]}" := ({| sedeleg := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'pmpcfg0' := e ]}" := ({| pmpcfg0 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'pmpaddr0' := e ]}" := ({| pmpaddr0 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mhartid' := e ]}" := ({| mhartid := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'marchid' := e ]}" := ({| marchid := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mimpid' := e ]}" := ({| mimpid := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mvendorid' := e ]}" := ({| mvendorid := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'minstret_written' := e ]}" := ({| minstret_written := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'minstret' := e ]}" := ({| minstret := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mtime' := e ]}" := ({| mtime := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mcycle' := e ]}" := ({| mcycle := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'scounteren' := e ]}" := ({| scounteren := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mcounteren' := e ]}" := ({| mcounteren := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mscratch' := e ]}" := ({| mscratch := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mtval' := e ]}" := ({| mtval := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mepc' := e ]}" := ({| mepc := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mcause' := e ]}" := ({| mcause := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mtvec' := e ]}" := ({| mtvec := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'medeleg' := e ]}" := ({| medeleg := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mideleg' := e ]}" := ({| mideleg := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mie' := e ]}" := ({| mie := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mip' := e ]}" := ({| mip := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'mstatus' := e ]}" := ({| mstatus := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'misa' := e ]}" := ({| misa := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'cur_inst' := e ]}" := ({| cur_inst := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'cur_privilege' := e ]}" := ({| cur_privilege := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x31' := e ]}" := ({| x31 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x30' := e ]}" := ({| x30 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x29' := e ]}" := ({| x29 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x28' := e ]}" := ({| x28 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x27' := e ]}" := ({| x27 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x26' := e ]}" := ({| x26 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x25' := e ]}" := ({| x25 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x24' := e ]}" := ({| x24 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x23' := e ]}" := ({| x23 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x22' := e ]}" := ({| x22 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x21' := e ]}" := ({| x21 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x20' := e ]}" := ({| x20 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x19' := e ]}" := ({| x19 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x18' := e ]}" := ({| x18 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x17' := e ]}" := ({| x17 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x16' := e ]}" := ({| x16 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x15' := e ]}" := ({| x15 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x14' := e ]}" := ({| x14 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x13' := e ]}" := ({| x13 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x12' := e ]}" := ({| x12 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x11' := e ]}" := ({| x11 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x10' := e ]}" := ({| x10 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x9' := e ]}" := ({| x9 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x8' := e ]}" := ({| x8 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x7' := e ]}" := ({| x7 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x6' := e ]}" := ({| x6 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x5' := e ]}" := ({| x5 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x4' := e ]}" := ({| x4 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x3' := e ]}" := ({| x3 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x2' := e ]}" := ({| x2 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'x1' := e ]}" := ({| x1 := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'Xs' := e ]}" := ({| Xs := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; instbits := instbits r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'instbits' := e ]}" := ({| instbits := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; nextPC := nextPC r; PC := PC r |}). +Notation "{[ r 'with' 'nextPC' := e ]}" := ({| nextPC := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; PC := PC r |}). +Notation "{[ r 'with' 'PC' := e ]}" := ({| PC := e; tlb39 := tlb39 r; htif_exit_code := htif_exit_code r; htif_done := htif_done r; htif_tohost := htif_tohost r; mtimecmp := mtimecmp r; tselect := tselect r; stval := stval r; scause := scause r; sepc := sepc r; sscratch := sscratch r; stvec := stvec r; satp := satp r; sideleg := sideleg r; sedeleg := sedeleg r; pmpcfg0 := pmpcfg0 r; pmpaddr0 := pmpaddr0 r; mhartid := mhartid r; marchid := marchid r; mimpid := mimpid r; mvendorid := mvendorid r; minstret_written := minstret_written r; minstret := minstret r; mtime := mtime r; mcycle := mcycle r; scounteren := scounteren r; mcounteren := mcounteren r; mscratch := mscratch r; mtval := mtval r; mepc := mepc r; mcause := mcause r; mtvec := mtvec r; medeleg := medeleg r; mideleg := mideleg r; mie := mie r; mip := mip r; mstatus := mstatus r; misa := misa r; cur_inst := cur_inst r; cur_privilege := cur_privilege r; x31 := x31 r; x30 := x30 r; x29 := x29 r; x28 := x28 r; x27 := x27 r; x26 := x26 r; x25 := x25 r; x24 := x24 r; x23 := x23 r; x22 := x22 r; x21 := x21 r; x20 := x20 r; x19 := x19 r; x18 := x18 r; x17 := x17 r; x16 := x16 r; x15 := x15 r; x14 := x14 r; x13 := x13 r; x12 := x12 r; x11 := x11 r; x10 := x10 r; x9 := x9 r; x8 := x8 r; x7 := x7 r; x6 := x6 r; x5 := x5 r; x4 := x4 r; x3 := x3 r; x2 := x2 r; x1 := x1 r; Xs := Xs r; instbits := instbits r; nextPC := nextPC r |}). + + + +Definition Counteren_of_regval (merge_var : register_value) +: option Counteren := + + match merge_var with | Regval_Counteren (v) => Some (v) | g__12 => None end. + +Definition regval_of_Counteren (v : Counteren) : register_value := Regval_Counteren (v). + +Definition Mcause_of_regval (merge_var : register_value) +: option Mcause := + + match merge_var with | Regval_Mcause (v) => Some (v) | g__11 => None end. + +Definition regval_of_Mcause (v : Mcause) : register_value := Regval_Mcause (v). + +Definition Medeleg_of_regval (merge_var : register_value) +: option Medeleg := + + match merge_var with | Regval_Medeleg (v) => Some (v) | g__10 => None end. + +Definition regval_of_Medeleg (v : Medeleg) : register_value := Regval_Medeleg (v). + +Definition Minterrupts_of_regval (merge_var : register_value) +: option Minterrupts := + + match merge_var with | Regval_Minterrupts (v) => Some (v) | g__9 => None end. + +Definition regval_of_Minterrupts (v : Minterrupts) : register_value := Regval_Minterrupts (v). + +Definition Misa_of_regval (merge_var : register_value) +: option Misa := + + match merge_var with | Regval_Misa (v) => Some (v) | g__8 => None end. + +Definition regval_of_Misa (v : Misa) : register_value := Regval_Misa (v). + +Definition Mstatus_of_regval (merge_var : register_value) +: option Mstatus := + + match merge_var with | Regval_Mstatus (v) => Some (v) | g__7 => None end. + +Definition regval_of_Mstatus (v : Mstatus) : register_value := Regval_Mstatus (v). + +Definition Mtvec_of_regval (merge_var : register_value) +: option Mtvec := + + match merge_var with | Regval_Mtvec (v) => Some (v) | g__6 => None end. + +Definition regval_of_Mtvec (v : Mtvec) : register_value := Regval_Mtvec (v). + +Definition Privilege_of_regval (merge_var : register_value) +: option Privilege := + + match merge_var with | Regval_Privilege (v) => Some (v) | g__5 => None end. + +Definition regval_of_Privilege (v : Privilege) : register_value := Regval_Privilege (v). + +Definition Sedeleg_of_regval (merge_var : register_value) +: option Sedeleg := + + match merge_var with | Regval_Sedeleg (v) => Some (v) | g__4 => None end. + +Definition regval_of_Sedeleg (v : Sedeleg) : register_value := Regval_Sedeleg (v). + +Definition Sinterrupts_of_regval (merge_var : register_value) +: option Sinterrupts := + + match merge_var with | Regval_Sinterrupts (v) => Some (v) | g__3 => None end. + +Definition regval_of_Sinterrupts (v : Sinterrupts) : register_value := Regval_Sinterrupts (v). + +Definition TLB39_Entry_of_regval (merge_var : register_value) +: option TLB39_Entry := + + match merge_var with | Regval_TLB39_Entry (v) => Some (v) | g__2 => None end. + +Definition regval_of_TLB39_Entry (v : TLB39_Entry) : register_value := Regval_TLB39_Entry (v). + +Definition bool_of_regval (merge_var : register_value) +: option bool := + + match merge_var with | Regval_bool (v) => Some (v) | g__1 => None end. + +Definition regval_of_bool (v : bool) : register_value := Regval_bool (v). + +Definition vector_64_dec_bit_of_regval (merge_var : register_value) +: option (mword 64) := + + match merge_var with | Regval_vector_64_dec_bit (v) => Some (v) | g__0 => None end. + +Definition regval_of_vector_64_dec_bit (v : mword 64) +: register_value := + + Regval_vector_64_dec_bit + (v). + + + +Definition vector_of_regval {a} n (of_regval : register_value -> option a) (rv : register_value) : option (vec a n) := match rv with + | Regval_vector (n', _, v) => if n =? n' then map_bind (vec_of_list n) (just_list (List.map of_regval v)) else None + | _ => None +end. + +Definition regval_of_vector {a} (regval_of : a -> register_value) (size : Z) (is_inc : bool) (xs : vec a size) : register_value := Regval_vector (size, is_inc, List.map regval_of (list_of_vec xs)). + +Definition list_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (list a) := match rv with + | Regval_list v => just_list (List.map of_regval v) + | _ => None +end. + +Definition regval_of_list {a} (regval_of : a -> register_value) (xs : list a) : register_value := Regval_list (List.map regval_of xs). + +Definition option_of_regval {a} (of_regval : register_value -> option a) (rv : register_value) : option (option a) := match rv with + | Regval_option v => option_map of_regval v + | _ => None +end. + +Definition regval_of_option {a} (regval_of : a -> register_value) (v : option a) := Regval_option (option_map regval_of v). + + +Definition tlb39_ref := {| + name := "tlb39"; + read_from := (fun s => s.(tlb39)); + write_to := (fun v s => ({[ s with tlb39 := v ]})); + of_regval := (fun v => option_of_regval (fun v => TLB39_Entry_of_regval v) v); + regval_of := (fun v => regval_of_option (fun v => regval_of_TLB39_Entry v) v) |}. + +Definition htif_exit_code_ref := {| + name := "htif_exit_code"; + read_from := (fun s => s.(htif_exit_code)); + write_to := (fun v s => ({[ s with htif_exit_code := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition htif_done_ref := {| + name := "htif_done"; + read_from := (fun s => s.(htif_done)); + write_to := (fun v s => ({[ s with htif_done := v ]})); + of_regval := (fun v => bool_of_regval v); + regval_of := (fun v => regval_of_bool v) |}. + +Definition htif_tohost_ref := {| + name := "htif_tohost"; + read_from := (fun s => s.(htif_tohost)); + write_to := (fun v s => ({[ s with htif_tohost := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mtimecmp_ref := {| + name := "mtimecmp"; + read_from := (fun s => s.(mtimecmp)); + write_to := (fun v s => ({[ s with mtimecmp := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition tselect_ref := {| + name := "tselect"; + read_from := (fun s => s.(tselect)); + write_to := (fun v s => ({[ s with tselect := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition stval_ref := {| + name := "stval"; + read_from := (fun s => s.(stval)); + write_to := (fun v s => ({[ s with stval := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition scause_ref := {| + name := "scause"; + read_from := (fun s => s.(scause)); + write_to := (fun v s => ({[ s with scause := v ]})); + of_regval := (fun v => Mcause_of_regval v); + regval_of := (fun v => regval_of_Mcause v) |}. + +Definition sepc_ref := {| + name := "sepc"; + read_from := (fun s => s.(sepc)); + write_to := (fun v s => ({[ s with sepc := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition sscratch_ref := {| + name := "sscratch"; + read_from := (fun s => s.(sscratch)); + write_to := (fun v s => ({[ s with sscratch := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition stvec_ref := {| + name := "stvec"; + read_from := (fun s => s.(stvec)); + write_to := (fun v s => ({[ s with stvec := v ]})); + of_regval := (fun v => Mtvec_of_regval v); + regval_of := (fun v => regval_of_Mtvec v) |}. + +Definition satp_ref := {| + name := "satp"; + read_from := (fun s => s.(satp)); + write_to := (fun v s => ({[ s with satp := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition sideleg_ref := {| + name := "sideleg"; + read_from := (fun s => s.(sideleg)); + write_to := (fun v s => ({[ s with sideleg := v ]})); + of_regval := (fun v => Sinterrupts_of_regval v); + regval_of := (fun v => regval_of_Sinterrupts v) |}. + +Definition sedeleg_ref := {| + name := "sedeleg"; + read_from := (fun s => s.(sedeleg)); + write_to := (fun v s => ({[ s with sedeleg := v ]})); + of_regval := (fun v => Sedeleg_of_regval v); + regval_of := (fun v => regval_of_Sedeleg v) |}. + +Definition pmpcfg0_ref := {| + name := "pmpcfg0"; + read_from := (fun s => s.(pmpcfg0)); + write_to := (fun v s => ({[ s with pmpcfg0 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition pmpaddr0_ref := {| + name := "pmpaddr0"; + read_from := (fun s => s.(pmpaddr0)); + write_to := (fun v s => ({[ s with pmpaddr0 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mhartid_ref := {| + name := "mhartid"; + read_from := (fun s => s.(mhartid)); + write_to := (fun v s => ({[ s with mhartid := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition marchid_ref := {| + name := "marchid"; + read_from := (fun s => s.(marchid)); + write_to := (fun v s => ({[ s with marchid := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mimpid_ref := {| + name := "mimpid"; + read_from := (fun s => s.(mimpid)); + write_to := (fun v s => ({[ s with mimpid := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mvendorid_ref := {| + name := "mvendorid"; + read_from := (fun s => s.(mvendorid)); + write_to := (fun v s => ({[ s with mvendorid := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition minstret_written_ref := {| + name := "minstret_written"; + read_from := (fun s => s.(minstret_written)); + write_to := (fun v s => ({[ s with minstret_written := v ]})); + of_regval := (fun v => bool_of_regval v); + regval_of := (fun v => regval_of_bool v) |}. + +Definition minstret_ref := {| + name := "minstret"; + read_from := (fun s => s.(minstret)); + write_to := (fun v s => ({[ s with minstret := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mtime_ref := {| + name := "mtime"; + read_from := (fun s => s.(mtime)); + write_to := (fun v s => ({[ s with mtime := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mcycle_ref := {| + name := "mcycle"; + read_from := (fun s => s.(mcycle)); + write_to := (fun v s => ({[ s with mcycle := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition scounteren_ref := {| + name := "scounteren"; + read_from := (fun s => s.(scounteren)); + write_to := (fun v s => ({[ s with scounteren := v ]})); + of_regval := (fun v => Counteren_of_regval v); + regval_of := (fun v => regval_of_Counteren v) |}. + +Definition mcounteren_ref := {| + name := "mcounteren"; + read_from := (fun s => s.(mcounteren)); + write_to := (fun v s => ({[ s with mcounteren := v ]})); + of_regval := (fun v => Counteren_of_regval v); + regval_of := (fun v => regval_of_Counteren v) |}. + +Definition mscratch_ref := {| + name := "mscratch"; + read_from := (fun s => s.(mscratch)); + write_to := (fun v s => ({[ s with mscratch := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mtval_ref := {| + name := "mtval"; + read_from := (fun s => s.(mtval)); + write_to := (fun v s => ({[ s with mtval := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mepc_ref := {| + name := "mepc"; + read_from := (fun s => s.(mepc)); + write_to := (fun v s => ({[ s with mepc := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition mcause_ref := {| + name := "mcause"; + read_from := (fun s => s.(mcause)); + write_to := (fun v s => ({[ s with mcause := v ]})); + of_regval := (fun v => Mcause_of_regval v); + regval_of := (fun v => regval_of_Mcause v) |}. + +Definition mtvec_ref := {| + name := "mtvec"; + read_from := (fun s => s.(mtvec)); + write_to := (fun v s => ({[ s with mtvec := v ]})); + of_regval := (fun v => Mtvec_of_regval v); + regval_of := (fun v => regval_of_Mtvec v) |}. + +Definition medeleg_ref := {| + name := "medeleg"; + read_from := (fun s => s.(medeleg)); + write_to := (fun v s => ({[ s with medeleg := v ]})); + of_regval := (fun v => Medeleg_of_regval v); + regval_of := (fun v => regval_of_Medeleg v) |}. + +Definition mideleg_ref := {| + name := "mideleg"; + read_from := (fun s => s.(mideleg)); + write_to := (fun v s => ({[ s with mideleg := v ]})); + of_regval := (fun v => Minterrupts_of_regval v); + regval_of := (fun v => regval_of_Minterrupts v) |}. + +Definition mie_ref := {| + name := "mie"; + read_from := (fun s => s.(mie)); + write_to := (fun v s => ({[ s with mie := v ]})); + of_regval := (fun v => Minterrupts_of_regval v); + regval_of := (fun v => regval_of_Minterrupts v) |}. + +Definition mip_ref := {| + name := "mip"; + read_from := (fun s => s.(mip)); + write_to := (fun v s => ({[ s with mip := v ]})); + of_regval := (fun v => Minterrupts_of_regval v); + regval_of := (fun v => regval_of_Minterrupts v) |}. + +Definition mstatus_ref := {| + name := "mstatus"; + read_from := (fun s => s.(mstatus)); + write_to := (fun v s => ({[ s with mstatus := v ]})); + of_regval := (fun v => Mstatus_of_regval v); + regval_of := (fun v => regval_of_Mstatus v) |}. + +Definition misa_ref := {| + name := "misa"; + read_from := (fun s => s.(misa)); + write_to := (fun v s => ({[ s with misa := v ]})); + of_regval := (fun v => Misa_of_regval v); + regval_of := (fun v => regval_of_Misa v) |}. + +Definition cur_inst_ref := {| + name := "cur_inst"; + read_from := (fun s => s.(cur_inst)); + write_to := (fun v s => ({[ s with cur_inst := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition cur_privilege_ref := {| + name := "cur_privilege"; + read_from := (fun s => s.(cur_privilege)); + write_to := (fun v s => ({[ s with cur_privilege := v ]})); + of_regval := (fun v => Privilege_of_regval v); + regval_of := (fun v => regval_of_Privilege v) |}. + +Definition x31_ref := {| + name := "x31"; + read_from := (fun s => s.(x31)); + write_to := (fun v s => ({[ s with x31 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x30_ref := {| + name := "x30"; + read_from := (fun s => s.(x30)); + write_to := (fun v s => ({[ s with x30 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x29_ref := {| + name := "x29"; + read_from := (fun s => s.(x29)); + write_to := (fun v s => ({[ s with x29 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x28_ref := {| + name := "x28"; + read_from := (fun s => s.(x28)); + write_to := (fun v s => ({[ s with x28 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x27_ref := {| + name := "x27"; + read_from := (fun s => s.(x27)); + write_to := (fun v s => ({[ s with x27 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x26_ref := {| + name := "x26"; + read_from := (fun s => s.(x26)); + write_to := (fun v s => ({[ s with x26 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x25_ref := {| + name := "x25"; + read_from := (fun s => s.(x25)); + write_to := (fun v s => ({[ s with x25 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x24_ref := {| + name := "x24"; + read_from := (fun s => s.(x24)); + write_to := (fun v s => ({[ s with x24 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x23_ref := {| + name := "x23"; + read_from := (fun s => s.(x23)); + write_to := (fun v s => ({[ s with x23 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x22_ref := {| + name := "x22"; + read_from := (fun s => s.(x22)); + write_to := (fun v s => ({[ s with x22 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x21_ref := {| + name := "x21"; + read_from := (fun s => s.(x21)); + write_to := (fun v s => ({[ s with x21 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x20_ref := {| + name := "x20"; + read_from := (fun s => s.(x20)); + write_to := (fun v s => ({[ s with x20 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x19_ref := {| + name := "x19"; + read_from := (fun s => s.(x19)); + write_to := (fun v s => ({[ s with x19 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x18_ref := {| + name := "x18"; + read_from := (fun s => s.(x18)); + write_to := (fun v s => ({[ s with x18 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x17_ref := {| + name := "x17"; + read_from := (fun s => s.(x17)); + write_to := (fun v s => ({[ s with x17 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x16_ref := {| + name := "x16"; + read_from := (fun s => s.(x16)); + write_to := (fun v s => ({[ s with x16 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x15_ref := {| + name := "x15"; + read_from := (fun s => s.(x15)); + write_to := (fun v s => ({[ s with x15 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x14_ref := {| + name := "x14"; + read_from := (fun s => s.(x14)); + write_to := (fun v s => ({[ s with x14 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x13_ref := {| + name := "x13"; + read_from := (fun s => s.(x13)); + write_to := (fun v s => ({[ s with x13 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x12_ref := {| + name := "x12"; + read_from := (fun s => s.(x12)); + write_to := (fun v s => ({[ s with x12 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x11_ref := {| + name := "x11"; + read_from := (fun s => s.(x11)); + write_to := (fun v s => ({[ s with x11 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x10_ref := {| + name := "x10"; + read_from := (fun s => s.(x10)); + write_to := (fun v s => ({[ s with x10 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x9_ref := {| + name := "x9"; + read_from := (fun s => s.(x9)); + write_to := (fun v s => ({[ s with x9 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x8_ref := {| + name := "x8"; + read_from := (fun s => s.(x8)); + write_to := (fun v s => ({[ s with x8 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x7_ref := {| + name := "x7"; + read_from := (fun s => s.(x7)); + write_to := (fun v s => ({[ s with x7 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x6_ref := {| + name := "x6"; + read_from := (fun s => s.(x6)); + write_to := (fun v s => ({[ s with x6 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x5_ref := {| + name := "x5"; + read_from := (fun s => s.(x5)); + write_to := (fun v s => ({[ s with x5 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x4_ref := {| + name := "x4"; + read_from := (fun s => s.(x4)); + write_to := (fun v s => ({[ s with x4 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x3_ref := {| + name := "x3"; + read_from := (fun s => s.(x3)); + write_to := (fun v s => ({[ s with x3 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x2_ref := {| + name := "x2"; + read_from := (fun s => s.(x2)); + write_to := (fun v s => ({[ s with x2 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition x1_ref := {| + name := "x1"; + read_from := (fun s => s.(x1)); + write_to := (fun v s => ({[ s with x1 := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition Xs_ref := {| + name := "Xs"; + read_from := (fun s => s.(Xs)); + write_to := (fun v s => ({[ s with Xs := v ]})); + of_regval := (fun v => vector_of_regval 32 (fun v => vector_64_dec_bit_of_regval v) v); + regval_of := (fun v => regval_of_vector (fun v => regval_of_vector_64_dec_bit v) 32 false v) |}. + +Definition instbits_ref := {| + name := "instbits"; + read_from := (fun s => s.(instbits)); + write_to := (fun v s => ({[ s with instbits := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition nextPC_ref := {| + name := "nextPC"; + read_from := (fun s => s.(nextPC)); + write_to := (fun v s => ({[ s with nextPC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Definition PC_ref := {| + name := "PC"; + read_from := (fun s => s.(PC)); + write_to := (fun v s => ({[ s with PC := v ]})); + of_regval := (fun v => vector_64_dec_bit_of_regval v); + regval_of := (fun v => regval_of_vector_64_dec_bit v) |}. + +Local Open Scope string. +Definition get_regval (reg_name : string) (s : regstate) : option register_value := + if string_dec reg_name "tlb39" then Some (tlb39_ref.(regval_of) (tlb39_ref.(read_from) s)) else + if string_dec reg_name "htif_exit_code" then Some (htif_exit_code_ref.(regval_of) (htif_exit_code_ref.(read_from) s)) else + if string_dec reg_name "htif_done" then Some (htif_done_ref.(regval_of) (htif_done_ref.(read_from) s)) else + if string_dec reg_name "htif_tohost" then Some (htif_tohost_ref.(regval_of) (htif_tohost_ref.(read_from) s)) else + if string_dec reg_name "mtimecmp" then Some (mtimecmp_ref.(regval_of) (mtimecmp_ref.(read_from) s)) else + if string_dec reg_name "tselect" then Some (tselect_ref.(regval_of) (tselect_ref.(read_from) s)) else + if string_dec reg_name "stval" then Some (stval_ref.(regval_of) (stval_ref.(read_from) s)) else + if string_dec reg_name "scause" then Some (scause_ref.(regval_of) (scause_ref.(read_from) s)) else + if string_dec reg_name "sepc" then Some (sepc_ref.(regval_of) (sepc_ref.(read_from) s)) else + if string_dec reg_name "sscratch" then Some (sscratch_ref.(regval_of) (sscratch_ref.(read_from) s)) else + if string_dec reg_name "stvec" then Some (stvec_ref.(regval_of) (stvec_ref.(read_from) s)) else + if string_dec reg_name "satp" then Some (satp_ref.(regval_of) (satp_ref.(read_from) s)) else + if string_dec reg_name "sideleg" then Some (sideleg_ref.(regval_of) (sideleg_ref.(read_from) s)) else + if string_dec reg_name "sedeleg" then Some (sedeleg_ref.(regval_of) (sedeleg_ref.(read_from) s)) else + if string_dec reg_name "pmpcfg0" then Some (pmpcfg0_ref.(regval_of) (pmpcfg0_ref.(read_from) s)) else + if string_dec reg_name "pmpaddr0" then Some (pmpaddr0_ref.(regval_of) (pmpaddr0_ref.(read_from) s)) else + if string_dec reg_name "mhartid" then Some (mhartid_ref.(regval_of) (mhartid_ref.(read_from) s)) else + if string_dec reg_name "marchid" then Some (marchid_ref.(regval_of) (marchid_ref.(read_from) s)) else + if string_dec reg_name "mimpid" then Some (mimpid_ref.(regval_of) (mimpid_ref.(read_from) s)) else + if string_dec reg_name "mvendorid" then Some (mvendorid_ref.(regval_of) (mvendorid_ref.(read_from) s)) else + if string_dec reg_name "minstret_written" then Some (minstret_written_ref.(regval_of) (minstret_written_ref.(read_from) s)) else + if string_dec reg_name "minstret" then Some (minstret_ref.(regval_of) (minstret_ref.(read_from) s)) else + if string_dec reg_name "mtime" then Some (mtime_ref.(regval_of) (mtime_ref.(read_from) s)) else + if string_dec reg_name "mcycle" then Some (mcycle_ref.(regval_of) (mcycle_ref.(read_from) s)) else + if string_dec reg_name "scounteren" then Some (scounteren_ref.(regval_of) (scounteren_ref.(read_from) s)) else + if string_dec reg_name "mcounteren" then Some (mcounteren_ref.(regval_of) (mcounteren_ref.(read_from) s)) else + if string_dec reg_name "mscratch" then Some (mscratch_ref.(regval_of) (mscratch_ref.(read_from) s)) else + if string_dec reg_name "mtval" then Some (mtval_ref.(regval_of) (mtval_ref.(read_from) s)) else + if string_dec reg_name "mepc" then Some (mepc_ref.(regval_of) (mepc_ref.(read_from) s)) else + if string_dec reg_name "mcause" then Some (mcause_ref.(regval_of) (mcause_ref.(read_from) s)) else + if string_dec reg_name "mtvec" then Some (mtvec_ref.(regval_of) (mtvec_ref.(read_from) s)) else + if string_dec reg_name "medeleg" then Some (medeleg_ref.(regval_of) (medeleg_ref.(read_from) s)) else + if string_dec reg_name "mideleg" then Some (mideleg_ref.(regval_of) (mideleg_ref.(read_from) s)) else + if string_dec reg_name "mie" then Some (mie_ref.(regval_of) (mie_ref.(read_from) s)) else + if string_dec reg_name "mip" then Some (mip_ref.(regval_of) (mip_ref.(read_from) s)) else + if string_dec reg_name "mstatus" then Some (mstatus_ref.(regval_of) (mstatus_ref.(read_from) s)) else + if string_dec reg_name "misa" then Some (misa_ref.(regval_of) (misa_ref.(read_from) s)) else + if string_dec reg_name "cur_inst" then Some (cur_inst_ref.(regval_of) (cur_inst_ref.(read_from) s)) else + if string_dec reg_name "cur_privilege" then Some (cur_privilege_ref.(regval_of) (cur_privilege_ref.(read_from) s)) else + if string_dec reg_name "x31" then Some (x31_ref.(regval_of) (x31_ref.(read_from) s)) else + if string_dec reg_name "x30" then Some (x30_ref.(regval_of) (x30_ref.(read_from) s)) else + if string_dec reg_name "x29" then Some (x29_ref.(regval_of) (x29_ref.(read_from) s)) else + if string_dec reg_name "x28" then Some (x28_ref.(regval_of) (x28_ref.(read_from) s)) else + if string_dec reg_name "x27" then Some (x27_ref.(regval_of) (x27_ref.(read_from) s)) else + if string_dec reg_name "x26" then Some (x26_ref.(regval_of) (x26_ref.(read_from) s)) else + if string_dec reg_name "x25" then Some (x25_ref.(regval_of) (x25_ref.(read_from) s)) else + if string_dec reg_name "x24" then Some (x24_ref.(regval_of) (x24_ref.(read_from) s)) else + if string_dec reg_name "x23" then Some (x23_ref.(regval_of) (x23_ref.(read_from) s)) else + if string_dec reg_name "x22" then Some (x22_ref.(regval_of) (x22_ref.(read_from) s)) else + if string_dec reg_name "x21" then Some (x21_ref.(regval_of) (x21_ref.(read_from) s)) else + if string_dec reg_name "x20" then Some (x20_ref.(regval_of) (x20_ref.(read_from) s)) else + if string_dec reg_name "x19" then Some (x19_ref.(regval_of) (x19_ref.(read_from) s)) else + if string_dec reg_name "x18" then Some (x18_ref.(regval_of) (x18_ref.(read_from) s)) else + if string_dec reg_name "x17" then Some (x17_ref.(regval_of) (x17_ref.(read_from) s)) else + if string_dec reg_name "x16" then Some (x16_ref.(regval_of) (x16_ref.(read_from) s)) else + if string_dec reg_name "x15" then Some (x15_ref.(regval_of) (x15_ref.(read_from) s)) else + if string_dec reg_name "x14" then Some (x14_ref.(regval_of) (x14_ref.(read_from) s)) else + if string_dec reg_name "x13" then Some (x13_ref.(regval_of) (x13_ref.(read_from) s)) else + if string_dec reg_name "x12" then Some (x12_ref.(regval_of) (x12_ref.(read_from) s)) else + if string_dec reg_name "x11" then Some (x11_ref.(regval_of) (x11_ref.(read_from) s)) else + if string_dec reg_name "x10" then Some (x10_ref.(regval_of) (x10_ref.(read_from) s)) else + if string_dec reg_name "x9" then Some (x9_ref.(regval_of) (x9_ref.(read_from) s)) else + if string_dec reg_name "x8" then Some (x8_ref.(regval_of) (x8_ref.(read_from) s)) else + if string_dec reg_name "x7" then Some (x7_ref.(regval_of) (x7_ref.(read_from) s)) else + if string_dec reg_name "x6" then Some (x6_ref.(regval_of) (x6_ref.(read_from) s)) else + if string_dec reg_name "x5" then Some (x5_ref.(regval_of) (x5_ref.(read_from) s)) else + if string_dec reg_name "x4" then Some (x4_ref.(regval_of) (x4_ref.(read_from) s)) else + if string_dec reg_name "x3" then Some (x3_ref.(regval_of) (x3_ref.(read_from) s)) else + if string_dec reg_name "x2" then Some (x2_ref.(regval_of) (x2_ref.(read_from) s)) else + if string_dec reg_name "x1" then Some (x1_ref.(regval_of) (x1_ref.(read_from) s)) else + if string_dec reg_name "Xs" then Some (Xs_ref.(regval_of) (Xs_ref.(read_from) s)) else + if string_dec reg_name "instbits" then Some (instbits_ref.(regval_of) (instbits_ref.(read_from) s)) else + if string_dec reg_name "nextPC" then Some (nextPC_ref.(regval_of) (nextPC_ref.(read_from) s)) else + if string_dec reg_name "PC" then Some (PC_ref.(regval_of) (PC_ref.(read_from) s)) else + None. + +Definition set_regval (reg_name : string) (v : register_value) (s : regstate) : option regstate := + if string_dec reg_name "tlb39" then option_map (fun v => tlb39_ref.(write_to) v s) (tlb39_ref.(of_regval) v) else + if string_dec reg_name "htif_exit_code" then option_map (fun v => htif_exit_code_ref.(write_to) v s) (htif_exit_code_ref.(of_regval) v) else + if string_dec reg_name "htif_done" then option_map (fun v => htif_done_ref.(write_to) v s) (htif_done_ref.(of_regval) v) else + if string_dec reg_name "htif_tohost" then option_map (fun v => htif_tohost_ref.(write_to) v s) (htif_tohost_ref.(of_regval) v) else + if string_dec reg_name "mtimecmp" then option_map (fun v => mtimecmp_ref.(write_to) v s) (mtimecmp_ref.(of_regval) v) else + if string_dec reg_name "tselect" then option_map (fun v => tselect_ref.(write_to) v s) (tselect_ref.(of_regval) v) else + if string_dec reg_name "stval" then option_map (fun v => stval_ref.(write_to) v s) (stval_ref.(of_regval) v) else + if string_dec reg_name "scause" then option_map (fun v => scause_ref.(write_to) v s) (scause_ref.(of_regval) v) else + if string_dec reg_name "sepc" then option_map (fun v => sepc_ref.(write_to) v s) (sepc_ref.(of_regval) v) else + if string_dec reg_name "sscratch" then option_map (fun v => sscratch_ref.(write_to) v s) (sscratch_ref.(of_regval) v) else + if string_dec reg_name "stvec" then option_map (fun v => stvec_ref.(write_to) v s) (stvec_ref.(of_regval) v) else + if string_dec reg_name "satp" then option_map (fun v => satp_ref.(write_to) v s) (satp_ref.(of_regval) v) else + if string_dec reg_name "sideleg" then option_map (fun v => sideleg_ref.(write_to) v s) (sideleg_ref.(of_regval) v) else + if string_dec reg_name "sedeleg" then option_map (fun v => sedeleg_ref.(write_to) v s) (sedeleg_ref.(of_regval) v) else + if string_dec reg_name "pmpcfg0" then option_map (fun v => pmpcfg0_ref.(write_to) v s) (pmpcfg0_ref.(of_regval) v) else + if string_dec reg_name "pmpaddr0" then option_map (fun v => pmpaddr0_ref.(write_to) v s) (pmpaddr0_ref.(of_regval) v) else + if string_dec reg_name "mhartid" then option_map (fun v => mhartid_ref.(write_to) v s) (mhartid_ref.(of_regval) v) else + if string_dec reg_name "marchid" then option_map (fun v => marchid_ref.(write_to) v s) (marchid_ref.(of_regval) v) else + if string_dec reg_name "mimpid" then option_map (fun v => mimpid_ref.(write_to) v s) (mimpid_ref.(of_regval) v) else + if string_dec reg_name "mvendorid" then option_map (fun v => mvendorid_ref.(write_to) v s) (mvendorid_ref.(of_regval) v) else + if string_dec reg_name "minstret_written" then option_map (fun v => minstret_written_ref.(write_to) v s) (minstret_written_ref.(of_regval) v) else + if string_dec reg_name "minstret" then option_map (fun v => minstret_ref.(write_to) v s) (minstret_ref.(of_regval) v) else + if string_dec reg_name "mtime" then option_map (fun v => mtime_ref.(write_to) v s) (mtime_ref.(of_regval) v) else + if string_dec reg_name "mcycle" then option_map (fun v => mcycle_ref.(write_to) v s) (mcycle_ref.(of_regval) v) else + if string_dec reg_name "scounteren" then option_map (fun v => scounteren_ref.(write_to) v s) (scounteren_ref.(of_regval) v) else + if string_dec reg_name "mcounteren" then option_map (fun v => mcounteren_ref.(write_to) v s) (mcounteren_ref.(of_regval) v) else + if string_dec reg_name "mscratch" then option_map (fun v => mscratch_ref.(write_to) v s) (mscratch_ref.(of_regval) v) else + if string_dec reg_name "mtval" then option_map (fun v => mtval_ref.(write_to) v s) (mtval_ref.(of_regval) v) else + if string_dec reg_name "mepc" then option_map (fun v => mepc_ref.(write_to) v s) (mepc_ref.(of_regval) v) else + if string_dec reg_name "mcause" then option_map (fun v => mcause_ref.(write_to) v s) (mcause_ref.(of_regval) v) else + if string_dec reg_name "mtvec" then option_map (fun v => mtvec_ref.(write_to) v s) (mtvec_ref.(of_regval) v) else + if string_dec reg_name "medeleg" then option_map (fun v => medeleg_ref.(write_to) v s) (medeleg_ref.(of_regval) v) else + if string_dec reg_name "mideleg" then option_map (fun v => mideleg_ref.(write_to) v s) (mideleg_ref.(of_regval) v) else + if string_dec reg_name "mie" then option_map (fun v => mie_ref.(write_to) v s) (mie_ref.(of_regval) v) else + if string_dec reg_name "mip" then option_map (fun v => mip_ref.(write_to) v s) (mip_ref.(of_regval) v) else + if string_dec reg_name "mstatus" then option_map (fun v => mstatus_ref.(write_to) v s) (mstatus_ref.(of_regval) v) else + if string_dec reg_name "misa" then option_map (fun v => misa_ref.(write_to) v s) (misa_ref.(of_regval) v) else + if string_dec reg_name "cur_inst" then option_map (fun v => cur_inst_ref.(write_to) v s) (cur_inst_ref.(of_regval) v) else + if string_dec reg_name "cur_privilege" then option_map (fun v => cur_privilege_ref.(write_to) v s) (cur_privilege_ref.(of_regval) v) else + if string_dec reg_name "x31" then option_map (fun v => x31_ref.(write_to) v s) (x31_ref.(of_regval) v) else + if string_dec reg_name "x30" then option_map (fun v => x30_ref.(write_to) v s) (x30_ref.(of_regval) v) else + if string_dec reg_name "x29" then option_map (fun v => x29_ref.(write_to) v s) (x29_ref.(of_regval) v) else + if string_dec reg_name "x28" then option_map (fun v => x28_ref.(write_to) v s) (x28_ref.(of_regval) v) else + if string_dec reg_name "x27" then option_map (fun v => x27_ref.(write_to) v s) (x27_ref.(of_regval) v) else + if string_dec reg_name "x26" then option_map (fun v => x26_ref.(write_to) v s) (x26_ref.(of_regval) v) else + if string_dec reg_name "x25" then option_map (fun v => x25_ref.(write_to) v s) (x25_ref.(of_regval) v) else + if string_dec reg_name "x24" then option_map (fun v => x24_ref.(write_to) v s) (x24_ref.(of_regval) v) else + if string_dec reg_name "x23" then option_map (fun v => x23_ref.(write_to) v s) (x23_ref.(of_regval) v) else + if string_dec reg_name "x22" then option_map (fun v => x22_ref.(write_to) v s) (x22_ref.(of_regval) v) else + if string_dec reg_name "x21" then option_map (fun v => x21_ref.(write_to) v s) (x21_ref.(of_regval) v) else + if string_dec reg_name "x20" then option_map (fun v => x20_ref.(write_to) v s) (x20_ref.(of_regval) v) else + if string_dec reg_name "x19" then option_map (fun v => x19_ref.(write_to) v s) (x19_ref.(of_regval) v) else + if string_dec reg_name "x18" then option_map (fun v => x18_ref.(write_to) v s) (x18_ref.(of_regval) v) else + if string_dec reg_name "x17" then option_map (fun v => x17_ref.(write_to) v s) (x17_ref.(of_regval) v) else + if string_dec reg_name "x16" then option_map (fun v => x16_ref.(write_to) v s) (x16_ref.(of_regval) v) else + if string_dec reg_name "x15" then option_map (fun v => x15_ref.(write_to) v s) (x15_ref.(of_regval) v) else + if string_dec reg_name "x14" then option_map (fun v => x14_ref.(write_to) v s) (x14_ref.(of_regval) v) else + if string_dec reg_name "x13" then option_map (fun v => x13_ref.(write_to) v s) (x13_ref.(of_regval) v) else + if string_dec reg_name "x12" then option_map (fun v => x12_ref.(write_to) v s) (x12_ref.(of_regval) v) else + if string_dec reg_name "x11" then option_map (fun v => x11_ref.(write_to) v s) (x11_ref.(of_regval) v) else + if string_dec reg_name "x10" then option_map (fun v => x10_ref.(write_to) v s) (x10_ref.(of_regval) v) else + if string_dec reg_name "x9" then option_map (fun v => x9_ref.(write_to) v s) (x9_ref.(of_regval) v) else + if string_dec reg_name "x8" then option_map (fun v => x8_ref.(write_to) v s) (x8_ref.(of_regval) v) else + if string_dec reg_name "x7" then option_map (fun v => x7_ref.(write_to) v s) (x7_ref.(of_regval) v) else + if string_dec reg_name "x6" then option_map (fun v => x6_ref.(write_to) v s) (x6_ref.(of_regval) v) else + if string_dec reg_name "x5" then option_map (fun v => x5_ref.(write_to) v s) (x5_ref.(of_regval) v) else + if string_dec reg_name "x4" then option_map (fun v => x4_ref.(write_to) v s) (x4_ref.(of_regval) v) else + if string_dec reg_name "x3" then option_map (fun v => x3_ref.(write_to) v s) (x3_ref.(of_regval) v) else + if string_dec reg_name "x2" then option_map (fun v => x2_ref.(write_to) v s) (x2_ref.(of_regval) v) else + if string_dec reg_name "x1" then option_map (fun v => x1_ref.(write_to) v s) (x1_ref.(of_regval) v) else + if string_dec reg_name "Xs" then option_map (fun v => Xs_ref.(write_to) v s) (Xs_ref.(of_regval) v) else + if string_dec reg_name "instbits" then option_map (fun v => instbits_ref.(write_to) v s) (instbits_ref.(of_regval) v) else + if string_dec reg_name "nextPC" then option_map (fun v => nextPC_ref.(write_to) v s) (nextPC_ref.(of_regval) v) else + if string_dec reg_name "PC" then option_map (fun v => PC_ref.(write_to) v s) (PC_ref.(of_regval) v) else + None. + +Definition register_accessors := (get_regval, set_regval). + + +Definition MR a r := monadR register_value a r exception. +Definition M a := monad register_value a exception. |