diff options
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/main.sail | 5 | ||||
| -rw-r--r-- | riscv/riscv.sail | 4 | ||||
| -rw-r--r-- | riscv/riscv_step.sail | 27 | ||||
| -rw-r--r-- | riscv/riscv_sys.sail | 11 |
4 files changed, 27 insertions, 20 deletions
diff --git a/riscv/main.sail b/riscv/main.sail index 684aeff0..5d7b1108 100644 --- a/riscv/main.sail +++ b/riscv/main.sail @@ -8,10 +8,13 @@ val elf_tohost = { val loop : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg} function loop () = { let tohost = __GetSlice_int(64, elf_tohost(), 0); + i : int = 0; while true do { tick_clock(); - step(); + print_int("\nstep: ", i); + let retired : bool = step(); PC = nextPC; + if retired then i = i + 1; /* check htif exit */ let tohost_val = __ReadRAM(64, 4, 0x0000_0000_0000_0000, tohost); diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 2653269e..5b2c6f06 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -837,10 +837,6 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = None() => print_bits("unhandled write to CSR ", csr) } -function haveCSRPriv (csr : bits(12), isWrite : bool) -> bool = - let isRO = csr[11..10] == 0b11 in - ~ (isRO & isWrite) /* XXX TODO check priv */ - val signalIllegalInstruction : unit -> unit effect {escape} function signalIllegalInstruction () = not_implemented ("illegal instruction") diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail index b5d8e897..7783317a 100644 --- a/riscv/riscv_step.sail +++ b/riscv/riscv_step.sail @@ -41,27 +41,34 @@ function fetch() -> FetchResult = { } } -val step : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg} +/* returns whether an instruction was executed */ +val step : unit -> bool effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg} function step() = { match curInterrupt(mip, mie, mideleg) { Some(intr, priv) => { - print_bits("\nHandling interrupt: ", intr); - handle_interrupt(intr, priv) + print_bits("Handling interrupt: ", intr); + handle_interrupt(intr, priv); + false }, None() => { - print_bits("\nPC: ", PC); + print_bits("PC: ", PC); match fetch() { - F_Error(e, addr) => handle_mem_exception(addr, e), + F_Error(e, addr) => { + handle_mem_exception(addr, e); + false + }, F_RVC(h) => { match decodeCompressed(h) { None() => { print(BitStr(h) ^ " : <no-decode>"); - handle_decode_exception(EXTZ(h)) + handle_decode_exception(EXTZ(h)); + false }, Some(ast) => { print(BitStr(h) ^ " : " ^ ast); nextPC = PC + 2; - execute(ast) + execute(ast); + true } } }, @@ -69,12 +76,14 @@ function step() = { match decode(w) { None() => { print(BitStr(w) ^ " : <no-decode>"); - handle_decode_exception(EXTZ(w)) + handle_decode_exception(EXTZ(w)); + false }, Some(ast) => { print(BitStr(w) ^ " : " ^ ast); nextPC = PC + 4; - execute(ast) + execute(ast); + true } } } diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail index 89beea49..df08f4e6 100644 --- a/riscv/riscv_sys.sail +++ b/riscv/riscv_sys.sail @@ -218,7 +218,7 @@ function tvec_addr(m : Mtvec, c : Mcause) -> option(xlenbits) = { let base : xlenbits = m.Base() @ 0b00; match (trapVectorMode_of_bits(m.Mode())) { TV_Direct => Some(base), - TV_Vector => if mcause.IsInterrupt() == 0b1 /* FIXME: Why not already boolean? */ + TV_Vector => if c.IsInterrupt() == true then Some(base + (EXTZ(c.Cause()) << 0b10)) else Some(base), TV_Reserved => None() @@ -610,7 +610,6 @@ function tval(excinfo : option(xlenbits)) -> xlenbits = { union ctl_result = { CTL_TRAP : sync_exception, - CTL_INTR : (InterruptType, Privilege), CTL_SRET : unit, CTL_MRET : unit /* TODO: CTL_URET */ @@ -662,14 +661,13 @@ function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenb } function handle_exception(cur_priv : Privilege, ctl : ctl_result, - pc: xlenbits) -> xlenbits = + pc: xlenbits) -> xlenbits = { + print("handling exception ..."); match (cur_priv, ctl) { (_, CTL_TRAP(e)) => { let del_priv = exception_delegatee(e.trap, cur_priv); handle_trap(del_priv, false, e.trap, pc, e.excinfo) }, - (_, CTL_INTR(intr, del_priv)) => - handle_trap(del_priv, true, intr, pc, None()), (_, CTL_MRET()) => { mstatus->MIE() = mstatus.MPIE(); mstatus->MPIE() = true; @@ -685,6 +683,7 @@ function handle_exception(cur_priv : Privilege, ctl : ctl_result, sepc } } +} function handle_mem_exception(addr : xlenbits, e : ExceptionType) -> unit = { let t : sync_exception = struct { trap = e, @@ -699,7 +698,7 @@ function handle_decode_exception(instbits : xlenbits) -> unit = { } function handle_interrupt(i : InterruptType, del_priv : Privilege) -> unit = - nextPC = handle_trap(del_priv, false, i, PC, None()) + nextPC = handle_trap(del_priv, true, i, PC, None()) function init_sys() -> unit = { cur_privilege = Machine; |