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-rw-r--r--riscv/riscv_vmem.sail3
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail
index 26282d3e..7fddb047 100644
--- a/riscv/riscv_vmem.sail
+++ b/riscv/riscv_vmem.sail
@@ -194,7 +194,8 @@ val make_TLB39_Entry : (asid64, bool, vaddr39, paddr39, SV39_PTE, nat, paddr39)
function make_TLB39_Entry(asid, global, vAddr, pAddr, pte, level, pteAddr) = {
let shift : nat = PAGESIZE_BITS + (level * SV39_LEVEL_BITS);
- let vAddrMask : vaddr39 = shiftl(EXTZ(0b1), shift) - 1;
+ /* fixme hack: use a better idiom for masks */
+ let vAddrMask : vaddr39 = shiftl(vAddr ^ vAddr ^ EXTZ(0b1), shift) - 1;
let vMatchMask : vaddr39 = ~ (vAddrMask);
struct {
asid = asid,