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-rw-r--r--riscv/riscv_vmem.sail3
1 files changed, 2 insertions, 1 deletions
diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail
index 4fb7b5d5..d5efe252 100644
--- a/riscv/riscv_vmem.sail
+++ b/riscv/riscv_vmem.sail
@@ -131,7 +131,8 @@ function walk39(vaddr, ac, priv, mxr, do_sum, ptb, level, global) -> PTW_Result
let pt_ofs : paddr39 = shiftl(EXTZ(shiftr(va.VPNi(), (level * SV39_LEVEL_BITS))[(SV39_LEVEL_BITS - 1) .. 0]),
PTE39_LOG_SIZE);
let pte_addr = ptb + pt_ofs;
- match (checked_mem_read(Data, EXTZ(pte_addr), 8)) {
+ /* FIXME: we assume here that walks only access memory-backed addresses. */
+ match (phys_mem_read(Data, EXTZ(pte_addr), 8)) {
MemException(_) => PTW_Failure(PTW_Access),
MemValue(v) => {
let pte = Mk_SV39_PTE(v);