diff options
Diffstat (limited to 'riscv/riscv_sys.sail')
| -rw-r--r-- | riscv/riscv_sys.sail | 18 |
1 files changed, 5 insertions, 13 deletions
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail index 2669ee3f..818700b4 100644 --- a/riscv/riscv_sys.sail +++ b/riscv/riscv_sys.sail @@ -375,13 +375,17 @@ function lower_mstatus(m : Mstatus) -> Sstatus = { } function lift_sstatus(m : Mstatus, s : Sstatus) -> Mstatus = { - let m = update_SD(m, s.SD()); // FIXME: This should be parameterized by a platform setting. For now, match spike. // let m = update_UXL(m, s.UXL()); let m = update_MXR(m, s.MXR()); let m = update_SUM(m, s.SUM()); + + // FIXME: Should XS and FS check whether X and F|D are supported in misa? let m = update_XS(m, s.XS()); let m = update_FS(m, s.FS()); + let m = update_SD(m, extStatus_of_bits(m.FS()) == Dirty + | extStatus_of_bits(m.XS()) == Dirty); + let m = update_SPP(m, s.SPP()); let m = update_SPIE(m, s.SPIE()); let m = update_UPIE(m, s.UPIE()); @@ -990,21 +994,9 @@ function handle_mem_exception(addr : xlenbits, e : ExceptionType) -> unit = { nextPC = handle_exception(cur_privilege, CTL_TRAP(t), PC) } -function handle_decode_exception(instbits : xlenbits) -> unit = { - let t : sync_exception = struct { trap = E_Illegal_Instr, - excinfo = Some(instbits) }; - nextPC = handle_exception(cur_privilege, CTL_TRAP(t), PC) -} - function handle_interrupt(i : InterruptType, del_priv : Privilege) -> unit = nextPC = handle_trap(del_priv, true, i, PC, None()) -function handle_illegal() -> unit = { - let t : sync_exception = struct { trap = E_Illegal_Instr, - excinfo = None() }; - nextPC = handle_exception(cur_privilege, CTL_TRAP(t), PC) -} - /* state state initialization */ function init_sys() -> unit = { |