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Diffstat (limited to 'riscv/riscv_step.sail')
| -rw-r--r-- | riscv/riscv_step.sail | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail index e670e2b8..b5d8e897 100644 --- a/riscv/riscv_step.sail +++ b/riscv/riscv_step.sail @@ -43,12 +43,13 @@ function fetch() -> FetchResult = { val step : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg} function step() = { - tick_clock(); - match curInterrupt(mip, mie, mideleg) { - Some(intr, priv) => - handle_interrupt(intr, priv), + Some(intr, priv) => { + print_bits("\nHandling interrupt: ", intr); + handle_interrupt(intr, priv) + }, None() => { + print_bits("\nPC: ", PC); match fetch() { F_Error(e, addr) => handle_mem_exception(addr, e), F_RVC(h) => { |