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-rw-r--r--riscv/riscv_extras_sequential.lem4
1 files changed, 4 insertions, 0 deletions
diff --git a/riscv/riscv_extras_sequential.lem b/riscv/riscv_extras_sequential.lem
index 601f5008..b29fe545 100644
--- a/riscv/riscv_extras_sequential.lem
+++ b/riscv/riscv_extras_sequential.lem
@@ -13,6 +13,10 @@ let MEM_fence_r_rw () = barrier Barrier_RISCV_r_rw
let MEM_fence_r_r () = barrier Barrier_RISCV_r_r
let MEM_fence_rw_w () = barrier Barrier_RISCV_rw_w
let MEM_fence_w_w () = barrier Barrier_RISCV_w_w
+let MEM_fence_w_rw () = barrier Barrier_RISCV_w_rw
+let MEM_fence_rw_r () = barrier Barrier_RISCV_rw_r
+let MEM_fence_r_w () = barrier Barrier_RISCV_r_w
+let MEM_fence_w_r () = barrier Barrier_RISCV_w_r
let MEM_fence_i () = barrier Barrier_RISCV_i
val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e