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-rw-r--r--riscv/prelude.sail5
1 files changed, 4 insertions, 1 deletions
diff --git a/riscv/prelude.sail b/riscv/prelude.sail
index 754a5cec..ad74434c 100644
--- a/riscv/prelude.sail
+++ b/riscv/prelude.sail
@@ -159,7 +159,7 @@ val BitStr = "string_of_bits" : forall 'n. bits('n) -> string
val xor_vec = "xor_vec" : forall 'n. (bits('n), bits('n)) -> bits('n)
-val int_power = {lem: "pow"} : (int, int) -> int
+val int_power = {ocaml: "int_power", lem: "pow"} : (int, int) -> int
val real_power = {ocaml: "real_power", lem: "realPowInteger"} : (real, int) -> real
@@ -252,6 +252,9 @@ val quotient = {ocaml: "quotient", lem: "integerDiv"} : (int, int) -> int
overload operator / = {quotient_nat, quotient, quotient_real}
+val quot_round_zero = {ocaml: "quot_round_zero", lem: "hardware_quot"} : (int, int) -> int
+val rem_round_zero = {ocaml: "rem_round_zero", lem: "hardware_mod"} : (int, int) -> int
+
val modulus = {ocaml: "modulus", lem: "hardware_mod"} : (int, int) -> int
overload operator % = {modulus}