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-rw-r--r--riscv/platform.ml2
1 files changed, 2 insertions, 0 deletions
diff --git a/riscv/platform.ml b/riscv/platform.ml
index 092df80f..06486ca2 100644
--- a/riscv/platform.ml
+++ b/riscv/platform.ml
@@ -56,6 +56,7 @@ module Elf = Elf_loader;;
let config_enable_dirty_update = ref false
let config_enable_misaligned_access = ref false
+let config_mtval_has_illegal_inst_bits = ref false
(* Mapping to Sail externs *)
@@ -82,6 +83,7 @@ let make_rom start_pc =
let enable_dirty_update () = !config_enable_dirty_update
let enable_misaligned_access () = !config_enable_misaligned_access
+let mtval_has_illegal_inst_bits () = !config_mtval_has_illegal_inst_bits
let rom_base () = bits_of_int64 P.rom_base
let rom_size () = bits_of_int !rom_size_ref