diff options
Diffstat (limited to 'riscv/main_rvfi.sail')
| -rw-r--r-- | riscv/main_rvfi.sail | 32 |
1 files changed, 18 insertions, 14 deletions
diff --git a/riscv/main_rvfi.sail b/riscv/main_rvfi.sail index e1469f7f..0ba4acfc 100644 --- a/riscv/main_rvfi.sail +++ b/riscv/main_rvfi.sail @@ -2,20 +2,24 @@ val rvfi_fetch : unit -> FetchResult effect {escape, rmem, rreg, wmv, wreg} -function rvfi_fetch() = { - let i = rvfi_instruction.rvfi_insn(); - rvfi_exec->rvfi_order() = minstret; - rvfi_exec->rvfi_pc_rdata() = PC; - rvfi_exec->rvfi_insn() = zero_extend(i,64); - /* TODO: should we write these even if they're not really registers? */ - rvfi_exec->rvfi_rs1_data() = X(i[19 .. 15]); - rvfi_exec->rvfi_rs2_data() = X(i[24 .. 20]); - rvfi_exec->rvfi_rs1_addr() = zero_extend(i[19 .. 15],8); - rvfi_exec->rvfi_rs2_addr() = zero_extend(i[24 .. 20],8); - if (i[1 .. 0] == 0b11) - then F_Base(i) - else F_RVC(i[15 .. 0]) -} +function rvfi_fetch() = + /* check for legal PC */ + if (PC[0] != 0b0 | (PC[1] != 0b0 & (~ (haveRVC())))) + then F_Error(E_Fetch_Addr_Align, PC) + else { + let i = rvfi_instruction.rvfi_insn(); + rvfi_exec->rvfi_order() = minstret; + rvfi_exec->rvfi_pc_rdata() = PC; + rvfi_exec->rvfi_insn() = zero_extend(i,64); + /* TODO: should we write these even if they're not really registers? */ + rvfi_exec->rvfi_rs1_data() = X(i[19 .. 15]); + rvfi_exec->rvfi_rs2_data() = X(i[24 .. 20]); + rvfi_exec->rvfi_rs1_addr() = zero_extend(i[19 .. 15],8); + rvfi_exec->rvfi_rs2_addr() = zero_extend(i[24 .. 20],8); + if (i[1 .. 0] == 0b11) + then F_Base(i) + else F_RVC(i[15 .. 0]) + } // This should be kept in sync with the normal step - at the moment the only // changes are to replace fetch by rvfi_fetch and record the next PC. |