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-rw-r--r--risc-v/riscv_extras_embed_sequential.lem4
1 files changed, 4 insertions, 0 deletions
diff --git a/risc-v/riscv_extras_embed_sequential.lem b/risc-v/riscv_extras_embed_sequential.lem
index 93b5dfec..0fca7709 100644
--- a/risc-v/riscv_extras_embed_sequential.lem
+++ b/risc-v/riscv_extras_embed_sequential.lem
@@ -37,10 +37,14 @@ let MEMval_conditional_release (_,_,v) = write_mem_val v >>= fun b -> return (if
val MEM_fence_rw_rw : unit -> M unit
val MEM_fence_r_rw : unit -> M unit
val MEM_fence_rw_w : unit -> M unit
+val MEM_fence_w_w : unit -> M unit
+val MEM_fence_i : unit -> M unit
let MEM_fence_rw_rw () = barrier Barrier_RISCV_rw_rw
let MEM_fence_r_rw () = barrier Barrier_RISCV_r_rw
let MEM_fence_rw_w () = barrier Barrier_RISCV_rw_w
+let MEM_fence_w_w () = barrier Barrier_RISCV_w_w
+let MEM_fence_i () = barrier Barrier_RISCV_i
let duplicate (bit,len) =
let bits = repeat [bit] len in