diff options
Diffstat (limited to 'power/gen')
| -rw-r--r-- | power/gen/ast.gen | 202 | ||||
| -rw-r--r-- | power/gen/compile.gen | 2257 | ||||
| -rw-r--r-- | power/gen/fold.gen | 368 | ||||
| -rw-r--r-- | power/gen/herdtools_ast_to_shallow_ast.gen | 1312 | ||||
| -rw-r--r-- | power/gen/lexer.gen | 368 | ||||
| -rw-r--r-- | power/gen/map.gen | 368 | ||||
| -rw-r--r-- | power/gen/parser.gen | 736 | ||||
| -rw-r--r-- | power/gen/pretty.gen | 368 | ||||
| -rw-r--r-- | power/gen/sail_trans_out.gen | 1112 | ||||
| -rw-r--r-- | power/gen/sail_trans_out_types.hgen | 146 | ||||
| -rw-r--r-- | power/gen/shallow_ast_to_herdtools_ast.gen | 1112 | ||||
| -rw-r--r-- | power/gen/shallow_types_to_herdtools_types.hgen | 150 | ||||
| -rw-r--r-- | power/gen/tokens.gen | 368 | ||||
| -rw-r--r-- | power/gen/trans_sail.gen | 1516 | ||||
| -rw-r--r-- | power/gen/trans_sail_types.hgen | 61 |
15 files changed, 10444 insertions, 0 deletions
diff --git a/power/gen/ast.gen b/power/gen/ast.gen new file mode 100644 index 00000000..fdc12609 --- /dev/null +++ b/power/gen/ast.gen @@ -0,0 +1,202 @@ + | `Pb of setaa*setlk*k + | `Pbc of setaa*setlk*k*k*k + | `Pbclr of setlk*k*k*k + | `Pbcctr of setlk*k*k*k + | `Pcrand of k*k*k + | `Pcrnand of k*k*k + | `Pcror of k*k*k + | `Pcrxor of k*k*k + | `Pcrnor of k*k*k + | `Pcreqv of k*k*k + | `Pcrandc of k*k*k + | `Pcrorc of k*k*k + | `Pmcrf of crindex*k + | `Psc of k + | `Pscv of k + | `Plbz of reg*k*reg + | `Plbzx of reg*reg*reg + | `Plbzu of reg*k*reg + | `Plbzux of reg*reg*reg + | `Plhz of reg*k*reg + | `Plhzx of reg*reg*reg + | `Plhzu of reg*k*reg + | `Plhzux of reg*reg*reg + | `Plha of reg*k*reg + | `Plhax of reg*reg*reg + | `Plhau of reg*k*reg + | `Plhaux of reg*reg*reg + | `Plwz of reg*k*reg + | `Plwzx of reg*reg*reg + | `Plwzu of reg*k*reg + | `Plwzux of reg*reg*reg + | `Plwa of reg*ds*reg + | `Plwax of reg*reg*reg + | `Plwaux of reg*reg*reg + | `Pld of reg*ds*reg + | `Pldx of reg*reg*reg + | `Pldu of reg*ds*reg + | `Pldux of reg*reg*reg + | `Pstb of reg*k*reg + | `Pstbx of reg*reg*reg + | `Pstbu of reg*k*reg + | `Pstbux of reg*reg*reg + | `Psth of reg*k*reg + | `Psthx of reg*reg*reg + | `Psthu of reg*k*reg + | `Psthux of reg*reg*reg + | `Pstw of reg*k*reg + | `Pstwx of reg*reg*reg + | `Pstwu of reg*k*reg + | `Pstwux of reg*reg*reg + | `Pstd of reg*ds*reg + | `Pstdx of reg*reg*reg + | `Pstdu of reg*ds*reg + | `Pstdux of reg*reg*reg + | `Plq of k*k*reg*k + | `Pstq of k*ds*reg + | `Plhbrx of reg*reg*reg + | `Psthbrx of reg*reg*reg + | `Plwbrx of reg*reg*reg + | `Pstwbrx of reg*reg*reg + | `Pldbrx of reg*reg*reg + | `Pstdbrx of reg*reg*reg + | `Plmw of reg*k*reg + | `Pstmw of reg*k*reg + | `Plswi of k*reg*k + | `Plswx of reg*reg*reg + | `Pstswi of k*reg*k + | `Pstswx of k*reg*reg + | `Paddi of reg*reg*k + | `Paddis of reg*reg*k + | `Padd of setsoov*setcr0*reg*reg*reg + | `Psubf of setsoov*setcr0*reg*reg*reg + | `Paddic of reg*reg*k + | `Paddicdot of reg*reg*k + | `Psubfic of reg*reg*k + | `Paddc of setsoov*setcr0*reg*reg*reg + | `Psubfc of setsoov*setcr0*reg*reg*reg + | `Padde of setsoov*setcr0*reg*reg*reg + | `Psubfe of setsoov*setcr0*reg*reg*reg + | `Paddme of setsoov*setcr0*reg*reg + | `Psubfme of setsoov*setcr0*reg*reg + | `Paddze of setsoov*setcr0*reg*reg + | `Psubfze of setsoov*setcr0*reg*reg + | `Pneg of setsoov*setcr0*reg*reg + | `Pmulli of reg*reg*k + | `Pmullw of setsoov*setcr0*reg*reg*reg + | `Pmulhw of setcr0*reg*reg*reg + | `Pmulhwu of setcr0*reg*reg*reg + | `Pdivw of setsoov*setcr0*reg*reg*reg + | `Pdivwu of setsoov*setcr0*reg*reg*reg + | `Pdivwe of setsoov*setcr0*reg*reg*reg + | `Pdivweu of setsoov*setcr0*reg*reg*reg + | `Pmulld of setsoov*setcr0*reg*reg*reg + | `Pmulhd of setcr0*reg*reg*reg + | `Pmulhdu of setcr0*reg*reg*reg + | `Pdivd of setsoov*setcr0*reg*reg*reg + | `Pdivdu of setsoov*setcr0*reg*reg*reg + | `Pdivde of setsoov*setcr0*reg*reg*reg + | `Pdivdeu of setsoov*setcr0*reg*reg*reg + | `Pcmpi of crindex*k*reg*k + | `Pcmp of crindex*k*reg*reg + | `Pcmpli of crindex*k*reg*k + | `Pcmpl of crindex*k*reg*reg + | `Pisel of reg*reg*reg*k + | `Pandi of reg*reg*k + | `Pandis of reg*reg*k + | `Pori of reg*reg*k + | `Poris of reg*reg*k + | `Pxori of reg*reg*k + | `Pxoris of reg*reg*k + | `Pand of setcr0*reg*reg*reg + | `Pxor of setcr0*reg*reg*reg + | `Pnand of setcr0*reg*reg*reg + | `Por of setcr0*reg*reg*reg + | `Pnor of setcr0*reg*reg*reg + | `Peqv of setcr0*reg*reg*reg + | `Pandc of setcr0*reg*reg*reg + | `Porc of setcr0*reg*reg*reg + | `Pextsb of setcr0*reg*reg + | `Pextsh of setcr0*reg*reg + | `Pcntlzw of setcr0*reg*reg + | `Pcmpb of reg*k*reg + | `Ppopcntb of reg*reg + | `Ppopcntw of reg*reg + | `Pprtyd of reg*reg + | `Pprtyw of reg*reg + | `Pextsw of setcr0*reg*reg + | `Pcntlzd of setcr0*reg*reg + | `Ppopcntd of reg*reg + | `Pbpermd of reg*reg*reg + | `Prlwinm of setcr0*reg*reg*k*k*k + | `Prlwnm of setcr0*reg*reg*reg*k*k + | `Prlwimi of setcr0*reg*reg*k*k*k + | `Prldicl of setcr0*reg*reg*k*k + | `Prldicr of setcr0*reg*reg*k*k + | `Prldic of setcr0*reg*reg*k*k + | `Prldcl of setcr0*reg*reg*reg*k + | `Prldcr of setcr0*reg*reg*reg*k + | `Prldimi of setcr0*reg*reg*k*k + | `Pslw of setcr0*reg*reg*reg + | `Psrw of setcr0*reg*reg*reg + | `Psrawi of setcr0*reg*reg*k + | `Psraw of setcr0*reg*reg*reg + | `Psld of setcr0*reg*reg*reg + | `Psrd of setcr0*reg*reg*reg + | `Psradi of setcr0*reg*reg*k + | `Psrad of setcr0*reg*reg*reg + | `Pcdtbcd of reg*reg + | `Pcbcdtd of reg*reg + | `Paddg6s of reg*reg*reg + | `Pmtspr of k*reg + | `Pmfspr of reg*k + | `Pmtcrf of crmask*reg + | `Pmfcr of reg + | `Pmtocrf of crmask*reg + | `Pmfocrf of reg*crmask + | `Pmcrxr of crindex + | `Pdlmzb of setcr0*reg*reg*reg + | `Pmacchw of setsoov*setcr0*reg*reg*reg + | `Pmacchws of setsoov*setcr0*reg*reg*reg + | `Pmacchwu of setsoov*setcr0*reg*reg*reg + | `Pmacchwsu of setsoov*setcr0*reg*reg*reg + | `Pmachhw of setsoov*setcr0*reg*reg*reg + | `Pmachhws of setsoov*setcr0*reg*reg*reg + | `Pmachhwu of setsoov*setcr0*reg*reg*reg + | `Pmachhwsu of setsoov*setcr0*reg*reg*reg + | `Pmaclhw of setsoov*setcr0*reg*reg*reg + | `Pmaclhws of setsoov*setcr0*reg*reg*reg + | `Pmaclhwu of setsoov*setcr0*reg*reg*reg + | `Pmaclhwsu of setsoov*setcr0*reg*reg*reg + | `Pmulchw of setcr0*reg*reg*reg + | `Pmulchwu of setcr0*reg*reg*reg + | `Pmulhhw of setcr0*reg*reg*reg + | `Pmulhhwu of setcr0*reg*reg*reg + | `Pmullhw of setcr0*reg*reg*reg + | `Pmullhwu of setcr0*reg*reg*reg + | `Pnmacchw of setsoov*setcr0*reg*reg*reg + | `Pnmacchws of setsoov*setcr0*reg*reg*reg + | `Pnmachhw of setsoov*setcr0*reg*reg*reg + | `Pnmachhws of setsoov*setcr0*reg*reg*reg + | `Pnmaclhw of setsoov*setcr0*reg*reg*reg + | `Pnmaclhws of setsoov*setcr0*reg*reg*reg + | `Picbi of reg*reg + | `Picbt of k*reg*reg + | `Pdcba of reg*reg + | `Pdcbt of reg*reg*k + | `Pdcbtst of reg*reg*k + | `Pdcbz of reg*reg + | `Pdcbst of reg*reg + | `Pdcbf of reg*reg*k + | `Pisync + | `Plbarx of reg*reg*reg*k + | `Plharx of reg*reg*reg*k + | `Plwarx of reg*reg*reg*k + | `Pstbcx of reg*reg*reg + | `Psthcx of reg*reg*reg + | `Pstwcx of reg*reg*reg + | `Pldarx of reg*reg*reg*k + | `Pstdcx of reg*reg*reg + | `Psync of k + | `Peieio + | `Pwait of k diff --git a/power/gen/compile.gen b/power/gen/compile.gen new file mode 100644 index 00000000..d0af6e38 --- /dev/null +++ b/power/gen/compile.gen @@ -0,0 +1,2257 @@ +| `Pb (DontSetAA,DontSetLK,target_addr) -> + { empty_ins with + memo=sprintf "b %i" target_addr; + inputs=[]; + outputs=[]; }::k +| `Pb (SetAA,DontSetLK,target_addr) -> + { empty_ins with + memo=sprintf "ba %i" target_addr; + inputs=[]; + outputs=[]; }::k +| `Pb (DontSetAA,SetLK,target_addr) -> + { empty_ins with + memo=sprintf "bl %i" target_addr; + inputs=[]; + outputs=[]; }::k +| `Pb (SetAA,SetLK,target_addr) -> + { empty_ins with + memo=sprintf "bla %i" target_addr; + inputs=[]; + outputs=[]; }::k +| `Pbc (DontSetAA,DontSetLK,bO,bI,target_addr) -> + { empty_ins with + memo=sprintf "bc %i,%i,%i" bO bI target_addr; + inputs=[]; + outputs=[]; }::k +| `Pbc (SetAA,DontSetLK,bO,bI,target_addr) -> + { empty_ins with + memo=sprintf "bca %i,%i,%i" bO bI target_addr; + inputs=[]; + outputs=[]; }::k +| `Pbc (DontSetAA,SetLK,bO,bI,target_addr) -> + { empty_ins with + memo=sprintf "bcl %i,%i,%i" bO bI target_addr; + inputs=[]; + outputs=[]; }::k +| `Pbc (SetAA,SetLK,bO,bI,target_addr) -> + { empty_ins with + memo=sprintf "bcla %i,%i,%i" bO bI target_addr; + inputs=[]; + outputs=[]; }::k +| `Pbclr (DontSetLK,bO,bI,bH) -> + { empty_ins with + memo=sprintf "bclr %i,%i,%i" bO bI bH; + inputs=[]; + outputs=[]; }::k +| `Pbclr (SetLK,bO,bI,bH) -> + { empty_ins with + memo=sprintf "bclrl %i,%i,%i" bO bI bH; + inputs=[]; + outputs=[]; }::k +| `Pbcctr (DontSetLK,bO,bI,bH) -> + { empty_ins with + memo=sprintf "bcctr %i,%i,%i" bO bI bH; + inputs=[]; + outputs=[]; }::k +| `Pbcctr (SetLK,bO,bI,bH) -> + { empty_ins with + memo=sprintf "bcctrl %i,%i,%i" bO bI bH; + inputs=[]; + outputs=[]; }::k +| `Pcrand (bT,bA,bB) -> + { empty_ins with + memo=sprintf "crand %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcrnand (bT,bA,bB) -> + { empty_ins with + memo=sprintf "crnand %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcror (bT,bA,bB) -> + { empty_ins with + memo=sprintf "cror %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcrxor (bT,bA,bB) -> + { empty_ins with + memo=sprintf "crxor %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcrnor (bT,bA,bB) -> + { empty_ins with + memo=sprintf "crnor %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcreqv (bT,bA,bB) -> + { empty_ins with + memo=sprintf "creqv %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcrandc (bT,bA,bB) -> + { empty_ins with + memo=sprintf "crandc %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcrorc (bT,bA,bB) -> + { empty_ins with + memo=sprintf "crorc %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pmcrf (bF,bFA) -> + { empty_ins with + memo=sprintf "mcrf %i,%i" bF bFA; + inputs=[]; + outputs=[]; }::k +| `Psc (lEV) -> + { empty_ins with + memo=sprintf "sc %i" lEV; + inputs=[]; + outputs=[]; }::k +| `Pscv (lEV) -> + { empty_ins with + memo=sprintf "scv %i" lEV; + inputs=[]; + outputs=[]; }::k +| `Plbz (rT,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lbz ^o0,%i(0)" d + else sprintf "lbz ^o0,%i(^i0)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Plbzx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lbzx ^o0,0,^i0" + else sprintf "lbzx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plbzu (rT,d,rA) -> + { empty_ins with + memo=sprintf "lbzu ^o0,%i(^i0)" d; + inputs=[rA]; + outputs=[rT; rA]; }::k +| `Plbzux (rT,rA,rB) -> + { empty_ins with + memo=sprintf "lbzux ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT; rA]; }::k +| `Plhz (rT,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lhz ^o0,%i(0)" d + else sprintf "lhz ^o0,%i(^i0)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Plhzx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lhzx ^o0,0,^i0" + else sprintf "lhzx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plhzu (rT,d,rA) -> + { empty_ins with + memo=sprintf "lhzu ^o0,%i(^i0)" d; + inputs=[rA]; + outputs=[rT; rA]; }::k +| `Plhzux (rT,rA,rB) -> + { empty_ins with + memo=sprintf "lhzux ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT; rA]; }::k +| `Plha (rT,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lha ^o0,%i(0)" d + else sprintf "lha ^o0,%i(^i0)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Plhax (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lhax ^o0,0,^i0" + else sprintf "lhax ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plhau (rT,d,rA) -> + { empty_ins with + memo=sprintf "lhau ^o0,%i(^i0)" d; + inputs=[rA]; + outputs=[rT; rA]; }::k +| `Plhaux (rT,rA,rB) -> + { empty_ins with + memo=sprintf "lhaux ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT; rA]; }::k +| `Plwz (rT,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lwz ^o0,%i(0)" d + else sprintf "lwz ^o0,%i(^i0)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Plwzx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lwzx ^o0,0,^i0" + else sprintf "lwzx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plwzu (rT,d,rA) -> + { empty_ins with + memo=sprintf "lwzu ^o0,%i(^i0)" d; + inputs=[rA]; + outputs=[rT; rA]; }::k +| `Plwzux (rT,rA,rB) -> + { empty_ins with + memo=sprintf "lwzux ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT; rA]; }::k +| `Plwa (rT,dS,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lwa ^o0,%i(0)" (dS lsr 2) + else sprintf "lwa ^o0,%i(^i0)" (dS lsr 2); + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Plwax (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lwax ^o0,0,^i0" + else sprintf "lwax ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plwaux (rT,rA,rB) -> + { empty_ins with + memo=sprintf "lwaux ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT; rA]; }::k +| `Pld (rT,dS,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "ld ^o0,%i(0)" (dS lsr 2) + else sprintf "ld ^o0,%i(^i0)" (dS lsr 2); + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Pldx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "ldx ^o0,0,^i0" + else sprintf "ldx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pldu (rT,dS,rA) -> + { empty_ins with + memo=sprintf "ldu ^o0,%i(^i0)" (dS lsr 2); + inputs=[rA]; + outputs=[rT; rA]; }::k +| `Pldux (rT,rA,rB) -> + { empty_ins with + memo=sprintf "ldux ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT; rA]; }::k +| `Pstb (rS,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stb ^i0,%i(0)" d + else sprintf "stb ^i0,%i(^i1)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [rS] else [rS; rA]); + outputs=[]; }::k +| `Pstbx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stbx ^i0,0,^i1" + else sprintf "stbx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Pstbu (rS,d,rA) -> + { empty_ins with + memo=sprintf "stbu ^i0,%i(^i1)" d; + inputs=[rS; rA]; + outputs=[rA]; }::k +| `Pstbux (rS,rA,rB) -> + { empty_ins with + memo=sprintf "stbux ^i0,^i1,^i2" ; + inputs=[rS; rA; rB]; + outputs=[rA]; }::k +| `Psth (rS,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "sth ^i0,%i(0)" d + else sprintf "sth ^i0,%i(^i1)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [rS] else [rS; rA]); + outputs=[]; }::k +| `Psthx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "sthx ^i0,0,^i1" + else sprintf "sthx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Psthu (rS,d,rA) -> + { empty_ins with + memo=sprintf "sthu ^i0,%i(^i1)" d; + inputs=[rS; rA]; + outputs=[rA]; }::k +| `Psthux (rS,rA,rB) -> + { empty_ins with + memo=sprintf "sthux ^i0,^i1,^i2" ; + inputs=[rS; rA; rB]; + outputs=[rA]; }::k +| `Pstw (rS,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stw ^i0,%i(0)" d + else sprintf "stw ^i0,%i(^i1)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [rS] else [rS; rA]); + outputs=[]; }::k +| `Pstwx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stwx ^i0,0,^i1" + else sprintf "stwx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Pstwu (rS,d,rA) -> + { empty_ins with + memo=sprintf "stwu ^i0,%i(^i1)" d; + inputs=[rS; rA]; + outputs=[rA]; }::k +| `Pstwux (rS,rA,rB) -> + { empty_ins with + memo=sprintf "stwux ^i0,^i1,^i2" ; + inputs=[rS; rA; rB]; + outputs=[rA]; }::k +| `Pstd (rS,dS,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "std ^i0,%i(0)" (dS lsr 2) + else sprintf "std ^i0,%i(^i1)" (dS lsr 2); + inputs= + (if rA = A.Ireg A.GPR0 then [rS] else [rS; rA]); + outputs=[]; }::k +| `Pstdx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stdx ^i0,0,^i1" + else sprintf "stdx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Pstdu (rS,dS,rA) -> + { empty_ins with + memo=sprintf "stdu ^i0,%i(^i1)" (dS lsr 2); + inputs=[rS; rA]; + outputs=[rA]; }::k +| `Pstdux (rS,rA,rB) -> + { empty_ins with + memo=sprintf "stdux ^i0,^i1,^i2" ; + inputs=[rS; rA; rB]; + outputs=[rA]; }::k +| `Plq (rTp,dQ,rA,pT) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lq %i,%i(0),%i" rTp dQ pT + else sprintf "lq %i,%i(^i0),%i" rTp dQ pT; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rA]; }::k +| `Pstq (rSp,dS,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stq %i,%i(0)" rSp (dS lsr 2) + else sprintf "stq %i,%i(^i0)" rSp (dS lsr 2); + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[]; }::k +| `Plhbrx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lhbrx ^o0,0,^i0" + else sprintf "lhbrx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Psthbrx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "sthbrx ^i0,0,^i1" + else sprintf "sthbrx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Plwbrx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lwbrx ^o0,0,^i0" + else sprintf "lwbrx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pstwbrx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stwbrx ^i0,0,^i1" + else sprintf "stwbrx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Pldbrx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "ldbrx ^o0,0,^i0" + else sprintf "ldbrx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pstdbrx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stdbrx ^i0,0,^i1" + else sprintf "stdbrx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Plmw (rT,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lmw ^o0,%i(0)" d + else sprintf "lmw ^o0,%i(^i0)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[] @ (A.regs_interval rT); }::k +| `Pstmw (rS,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stmw ^i0,%i(0)" d + else sprintf "stmw ^i1,%i(^i0)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]) @ (A.regs_interval rS); + outputs=[]; }::k +| `Plswi (rT,rA,nB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lswi %i,0,%i" rT nB + else sprintf "lswi %i,^i0,%i" rT nB; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[]; }::k +| `Plswx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lswx ^o0,0,^i0" + else sprintf "lswx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pstswi (rS,rA,nB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stswi %i,0,%i" rS nB + else sprintf "stswi %i,^i0,%i" rS nB; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[]; }::k +| `Pstswx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stswx %i,0,^i0" rS + else sprintf "stswx %i,^i0,^i1" rS; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[]; }::k +| `Paddi (rT,rA,sI) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "addi ^o0,0,%i" sI + else sprintf "addi ^o0,^i0,%i" sI; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Paddis (rT,rA,sI) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "addis ^o0,0,%i" sI + else sprintf "addis ^o0,^i0,%i" sI; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Padd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "add ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padd (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "add. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padd (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padd (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubf (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subf ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubf (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subf. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubf (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubf (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Paddic (rT,rA,sI) -> + { empty_ins with + memo=sprintf "addic ^o0,^i0,%i" sI; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddicdot (rT,rA,sI) -> + { empty_ins with + memo=sprintf "addic. ^o0,^i0,%i" sI; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfic (rT,rA,sI) -> + { empty_ins with + memo=sprintf "subfic ^o0,^i0,%i" sI; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addc ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Paddc (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addc. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Paddc (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addco ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Paddc (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addco. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfc ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfc (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfc. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfc (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfco ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfc (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfco. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "adde ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padde (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "adde. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padde (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addeo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padde (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addeo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfe ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfe (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfe. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfe (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfeo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfe (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfeo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Paddme (DontSetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addme ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddme (DontSetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addme. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddme (SetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addmeo ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddme (SetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addmeo. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfme (DontSetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfme ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfme (DontSetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfme. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfme (SetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfmeo ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfme (SetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfmeo. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddze (DontSetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addze ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddze (DontSetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addze. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddze (SetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addzeo ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddze (SetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addzeo. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfze (DontSetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfze ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfze (DontSetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfze. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfze (SetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfzeo ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfze (SetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfzeo. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Pneg (DontSetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "neg ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Pneg (DontSetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "neg. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Pneg (SetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "nego ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Pneg (SetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "nego. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Pmulli (rT,rA,sI) -> + { empty_ins with + memo=sprintf "mulli ^o0,^i0,%i" sI; + inputs=[rA]; + outputs=[rT]; }::k +| `Pmullw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mullw ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmullw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mullw. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmullw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mullwo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmullw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mullwo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhw (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhw ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhw (SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhw. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhwu (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhwu ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhwu (SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhwu. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divw ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divw. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwu ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwu. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwuo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwuo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwe ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwe (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwe. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwe (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divweo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwe (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divweo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivweu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divweu ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivweu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divweu. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivweu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divweuo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivweu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divweuo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulld (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulld ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulld (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulld. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulld (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulldo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulld (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulldo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhd (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhd ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhd (SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhd. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhdu (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhdu ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhdu (SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhdu. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divd ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivd (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divd. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivd (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivd (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdu ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdu. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divduo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divduo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divde ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivde (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divde. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivde (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdeo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivde (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdeo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdeu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdeu ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdeu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdeu. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdeu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdeuo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdeu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdeuo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pcmpi (bF,l,rA,sI) -> + { empty_ins with + memo=sprintf "cmpi %i,%i,^i0,%i" bF l sI; + inputs=[rA]; + outputs=[]; }::k +| `Pcmp (bF,l,rA,rB) -> + { empty_ins with + memo=sprintf "cmp %i,%i,^i0,^i1" bF l; + inputs=[rA; rB]; + outputs=[]; }::k +| `Pcmpli (bF,l,rA,uI) -> + { empty_ins with + memo=sprintf "cmpli %i,%i,^i0,%i" bF l uI; + inputs=[rA]; + outputs=[]; }::k +| `Pcmpl (bF,l,rA,rB) -> + { empty_ins with + memo=sprintf "cmpl %i,%i,^i0,^i1" bF l; + inputs=[rA; rB]; + outputs=[]; }::k +| `Pisel (rT,rA,rB,bC) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "isel ^o0,0,^i0,%i" bC + else sprintf "isel ^o0,^i0,^i1,%i" bC; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pandi (rA,rS,uI) -> + { empty_ins with + memo=sprintf "andi. ^o0,^i0,%i" uI; + inputs=[rS]; + outputs=[rA]; }::k +| `Pandis (rA,rS,uI) -> + { empty_ins with + memo=sprintf "andis. ^o0,^i0,%i" uI; + inputs=[rS]; + outputs=[rA]; }::k +| `Pori (rA,rS,uI) -> + { empty_ins with + memo=sprintf "ori ^o0,^i0,%i" uI; + inputs=[rS]; + outputs=[rA]; }::k +| `Poris (rA,rS,uI) -> + { empty_ins with + memo=sprintf "oris ^o0,^i0,%i" uI; + inputs=[rS]; + outputs=[rA]; }::k +| `Pxori (rA,rS,uI) -> + { empty_ins with + memo=sprintf "xori ^o0,^i0,%i" uI; + inputs=[rS]; + outputs=[rA]; }::k +| `Pxoris (rA,rS,uI) -> + { empty_ins with + memo=sprintf "xoris ^o0,^i0,%i" uI; + inputs=[rS]; + outputs=[rA]; }::k +| `Pand (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "and ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pand (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "and. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pxor (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "xor ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pxor (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "xor. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pnand (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "nand ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pnand (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "nand. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Por (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "or ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Por (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "or. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pnor (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "nor ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pnor (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "nor. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Peqv (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "eqv ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Peqv (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "eqv. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pandc (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "andc ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pandc (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "andc. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Porc (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "orc ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Porc (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "orc. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pextsb (DontSetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "extsb ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pextsb (SetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "extsb. ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pextsh (DontSetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "extsh ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pextsh (SetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "extsh. ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pcntlzw (DontSetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "cntlzw ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pcntlzw (SetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "cntlzw. ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pcmpb (rA,rS,rB) -> + { empty_ins with + memo=sprintf "cmpb ^o0,%i,^i0" rS; + inputs=[rB]; + outputs=[rA]; }::k +| `Ppopcntb (rA,rS) -> + { empty_ins with + memo=sprintf "popcntb ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Ppopcntw (rA,rS) -> + { empty_ins with + memo=sprintf "popcntw ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pprtyd (rA,rS) -> + { empty_ins with + memo=sprintf "prtyd ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pprtyw (rA,rS) -> + { empty_ins with + memo=sprintf "prtyw ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pextsw (DontSetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "extsw ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pextsw (SetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "extsw. ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pcntlzd (DontSetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "cntlzd ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pcntlzd (SetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "cntlzd. ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Ppopcntd (rA,rS) -> + { empty_ins with + memo=sprintf "popcntd ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pbpermd (rA,rS,rB) -> + { empty_ins with + memo=sprintf "bpermd ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prlwinm (DontSetCR0,rA,rS,sH,mB,mE) -> + { empty_ins with + memo=sprintf "rlwinm ^o0,^i0,%i,%i,%i" sH mB mE; + inputs=[rS]; + outputs=[rA]; }::k +| `Prlwinm (SetCR0,rA,rS,sH,mB,mE) -> + { empty_ins with + memo=sprintf "rlwinm. ^o0,^i0,%i,%i,%i" sH mB mE; + inputs=[rS]; + outputs=[rA]; }::k +| `Prlwnm (DontSetCR0,rA,rS,rB,mB,mE) -> + { empty_ins with + memo=sprintf "rlwnm ^o0,^i0,^i1,%i,%i" mB mE; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prlwnm (SetCR0,rA,rS,rB,mB,mE) -> + { empty_ins with + memo=sprintf "rlwnm. ^o0,^i0,^i1,%i,%i" mB mE; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prlwimi (DontSetCR0,rA,rS,sH,mB,mE) -> + { empty_ins with + memo=sprintf "rlwimi ^i0,^i1,%i,%i,%i" sH mB mE; + inputs=[rA; rS]; + outputs=[rA]; }::k +| `Prlwimi (SetCR0,rA,rS,sH,mB,mE) -> + { empty_ins with + memo=sprintf "rlwimi. ^i0,^i1,%i,%i,%i" sH mB mE; + inputs=[rA; rS]; + outputs=[rA]; }::k +| `Prldicl (DontSetCR0,rA,rS,sH,mB) -> + { empty_ins with + memo=sprintf "rldicl ^o0,^i0,%i,%i" sH mB; + inputs=[rS]; + outputs=[rA]; }::k +| `Prldicl (SetCR0,rA,rS,sH,mB) -> + { empty_ins with + memo=sprintf "rldicl. ^o0,^i0,%i,%i" sH mB; + inputs=[rS]; + outputs=[rA]; }::k +| `Prldicr (DontSetCR0,rA,rS,sH,mE) -> + { empty_ins with + memo=sprintf "rldicr ^o0,^i0,%i,%i" sH mE; + inputs=[rS]; + outputs=[rA]; }::k +| `Prldicr (SetCR0,rA,rS,sH,mE) -> + { empty_ins with + memo=sprintf "rldicr. ^o0,^i0,%i,%i" sH mE; + inputs=[rS]; + outputs=[rA]; }::k +| `Prldic (DontSetCR0,rA,rS,sH,mB) -> + { empty_ins with + memo=sprintf "rldic ^o0,^i0,%i,%i" sH mB; + inputs=[rS]; + outputs=[rA]; }::k +| `Prldic (SetCR0,rA,rS,sH,mB) -> + { empty_ins with + memo=sprintf "rldic. ^o0,^i0,%i,%i" sH mB; + inputs=[rS]; + outputs=[rA]; }::k +| `Prldcl (DontSetCR0,rA,rS,rB,mB) -> + { empty_ins with + memo=sprintf "rldcl ^o0,^i0,^i1,%i" mB; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prldcl (SetCR0,rA,rS,rB,mB) -> + { empty_ins with + memo=sprintf "rldcl. ^o0,^i0,^i1,%i" mB; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prldcr (DontSetCR0,rA,rS,rB,mE) -> + { empty_ins with + memo=sprintf "rldcr ^o0,^i0,^i1,%i" mE; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prldcr (SetCR0,rA,rS,rB,mE) -> + { empty_ins with + memo=sprintf "rldcr. ^o0,^i0,^i1,%i" mE; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prldimi (DontSetCR0,rA,rS,sH,mB) -> + { empty_ins with + memo=sprintf "rldimi ^i0,^i1,%i,%i" sH mB; + inputs=[rA; rS]; + outputs=[rA]; }::k +| `Prldimi (SetCR0,rA,rS,sH,mB) -> + { empty_ins with + memo=sprintf "rldimi. ^i0,^i1,%i,%i" sH mB; + inputs=[rA; rS]; + outputs=[rA]; }::k +| `Pslw (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "slw ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pslw (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "slw. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psrw (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "srw ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psrw (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "srw. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psrawi (DontSetCR0,rA,rS,sH) -> + { empty_ins with + memo=sprintf "srawi ^o0,^i0,%i" sH; + inputs=[rS]; + outputs=[rA]; }::k +| `Psrawi (SetCR0,rA,rS,sH) -> + { empty_ins with + memo=sprintf "srawi. ^o0,^i0,%i" sH; + inputs=[rS]; + outputs=[rA]; }::k +| `Psraw (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "sraw ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psraw (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "sraw. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psld (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "sld ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psld (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "sld. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psrd (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "srd ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psrd (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "srd. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psradi (DontSetCR0,rA,rS,sH) -> + { empty_ins with + memo=sprintf "sradi ^o0,^i0,%i" sH; + inputs=[rS]; + outputs=[rA]; }::k +| `Psradi (SetCR0,rA,rS,sH) -> + { empty_ins with + memo=sprintf "sradi. ^o0,^i0,%i" sH; + inputs=[rS]; + outputs=[rA]; }::k +| `Psrad (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "srad ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psrad (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "srad. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pcdtbcd (rA,rS) -> + { empty_ins with + memo=sprintf "cdtbcd ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pcbcdtd (rA,rS) -> + { empty_ins with + memo=sprintf "cbcdtd ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Paddg6s (rT,rA,rB) -> + { empty_ins with + memo=sprintf "addg6s ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmtspr (sPR,rS) -> + { empty_ins with + memo=sprintf "mtspr %i,^i0" sPR; + inputs=[rS]; + outputs=[]; }::k +| `Pmfspr (rT,sPR) -> + { empty_ins with + memo=sprintf "mfspr ^o0,%i" sPR; + inputs=[]; + outputs=[rT]; }::k +| `Pmtcrf (fXM,rS) -> + { empty_ins with + memo=sprintf "mtcrf %i,^i0" fXM; + inputs=[rS]; + outputs=[]; }::k +| `Pmfcr (rT) -> + { empty_ins with + memo=sprintf "mfcr ^o0" ; + inputs=[]; + outputs=[rT]; }::k +| `Pmtocrf (fXM,rS) -> + { empty_ins with + memo=sprintf "mtocrf %i,^i0" fXM; + inputs=[rS]; + outputs=[]; }::k +| `Pmfocrf (rT,fXM) -> + { empty_ins with + memo=sprintf "mfocrf ^o0,%i" fXM; + inputs=[]; + outputs=[rT]; }::k +| `Pmcrxr (bF) -> + { empty_ins with + memo=sprintf "mcrxr %i" bF; + inputs=[]; + outputs=[]; }::k +| `Pdlmzb (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dlmzb 0,^o1,^o2" + else sprintf "dlmzb ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rS; rB]); + outputs=[rA; rS; rB]; }::k +| `Pdlmzb (SetCR0,rA,rS,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dlmzb. 0,^o1,^o2" + else sprintf "dlmzb. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rS; rB]); + outputs=[rA; rS; rB]; }::k +| `Pmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchw ^o0,0,^o2" + else sprintf "macchw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchw. ^o0,0,^o2" + else sprintf "macchw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwo ^o0,0,^o2" + else sprintf "macchwo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwo. ^o0,0,^o2" + else sprintf "macchwo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchws ^o0,0,^o2" + else sprintf "macchws ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchws. ^o0,0,^o2" + else sprintf "macchws. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwso ^o0,0,^o2" + else sprintf "macchwso ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchws (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwso. ^o0,0,^o2" + else sprintf "macchwso. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwu ^o0,0,^o2" + else sprintf "macchwu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwu. ^o0,0,^o2" + else sprintf "macchwu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwuo ^o0,0,^o2" + else sprintf "macchwuo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwuo. ^o0,0,^o2" + else sprintf "macchwuo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwsu ^o0,0,^o2" + else sprintf "macchwsu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwsu. ^o0,0,^o2" + else sprintf "macchwsu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwsuo ^o0,0,^o2" + else sprintf "macchwsuo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwsu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwsuo. ^o0,0,^o2" + else sprintf "macchwsuo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhw ^o0,0,^o2" + else sprintf "machhw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhw. ^o0,0,^o2" + else sprintf "machhw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwo ^o0,0,^o2" + else sprintf "machhwo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwo. ^o0,0,^o2" + else sprintf "machhwo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhws ^o0,0,^o2" + else sprintf "machhws ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhws. ^o0,0,^o2" + else sprintf "machhws. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwso ^o0,0,^o2" + else sprintf "machhwso ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhws (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwso. ^o0,0,^o2" + else sprintf "machhwso. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwu ^o0,0,^o2" + else sprintf "machhwu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwu. ^o0,0,^o2" + else sprintf "machhwu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwuo ^o0,0,^o2" + else sprintf "machhwuo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwuo. ^o0,0,^o2" + else sprintf "machhwuo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwsu ^o0,0,^o2" + else sprintf "machhwsu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwsu. ^o0,0,^o2" + else sprintf "machhwsu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwsuo ^o0,0,^o2" + else sprintf "machhwsuo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwsu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwsuo. ^o0,0,^o2" + else sprintf "machhwsuo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhw ^o0,0,^o2" + else sprintf "maclhw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhw. ^o0,0,^o2" + else sprintf "maclhw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwo ^o0,0,^o2" + else sprintf "maclhwo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwo. ^o0,0,^o2" + else sprintf "maclhwo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhws ^o0,0,^o2" + else sprintf "maclhws ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhws. ^o0,0,^o2" + else sprintf "maclhws. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwso ^o0,0,^o2" + else sprintf "maclhwso ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwso. ^o0,0,^o2" + else sprintf "maclhwso. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwu ^o0,0,^o2" + else sprintf "maclhwu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwu. ^o0,0,^o2" + else sprintf "maclhwu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwuo ^o0,0,^o2" + else sprintf "maclhwuo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwuo. ^o0,0,^o2" + else sprintf "maclhwuo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwsu ^o0,0,^o2" + else sprintf "maclhwsu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwsu. ^o0,0,^o2" + else sprintf "maclhwsu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwsuo ^o0,0,^o2" + else sprintf "maclhwsuo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwsu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwsuo. ^o0,0,^o2" + else sprintf "maclhwsuo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulchw (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulchw ^o0,0,^o2" + else sprintf "mulchw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulchw (SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulchw. ^o0,0,^o2" + else sprintf "mulchw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulchwu (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulchwu ^o0,0,^o2" + else sprintf "mulchwu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulchwu (SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulchwu. ^o0,0,^o2" + else sprintf "mulchwu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulhhw (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulhhw ^o0,0,^o2" + else sprintf "mulhhw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulhhw (SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulhhw. ^o0,0,^o2" + else sprintf "mulhhw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulhhwu (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulhhwu ^o0,0,^o2" + else sprintf "mulhhwu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulhhwu (SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulhhwu. ^o0,0,^o2" + else sprintf "mulhhwu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmullhw (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mullhw ^o0,0,^o2" + else sprintf "mullhw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmullhw (SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mullhw. ^o0,0,^o2" + else sprintf "mullhw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmullhwu (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mullhwu ^o0,0,^o2" + else sprintf "mullhwu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmullhwu (SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mullhwu. ^o0,0,^o2" + else sprintf "mullhwu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchw ^o0,0,^o2" + else sprintf "nmacchw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchw. ^o0,0,^o2" + else sprintf "nmacchw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchwo ^o0,0,^o2" + else sprintf "nmacchwo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchwo. ^o0,0,^o2" + else sprintf "nmacchwo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchws ^o0,0,^o2" + else sprintf "nmacchws ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchws. ^o0,0,^o2" + else sprintf "nmacchws. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchwso ^o0,0,^o2" + else sprintf "nmacchwso ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchws (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchwso. ^o0,0,^o2" + else sprintf "nmacchwso. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhw ^o0,0,^o2" + else sprintf "nmachhw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhw. ^o0,0,^o2" + else sprintf "nmachhw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhwo ^o0,0,^o2" + else sprintf "nmachhwo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhwo. ^o0,0,^o2" + else sprintf "nmachhwo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhws ^o0,0,^o2" + else sprintf "nmachhws ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhws. ^o0,0,^o2" + else sprintf "nmachhws. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhwso ^o0,0,^o2" + else sprintf "nmachhwso ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhws (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhwso. ^o0,0,^o2" + else sprintf "nmachhwso. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhw ^o0,0,^o2" + else sprintf "nmaclhw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhw. ^o0,0,^o2" + else sprintf "nmaclhw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhwo ^o0,0,^o2" + else sprintf "nmaclhwo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhwo. ^o0,0,^o2" + else sprintf "nmaclhwo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhws ^o0,0,^o2" + else sprintf "nmaclhws ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhws. ^o0,0,^o2" + else sprintf "nmaclhws. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhwso ^o0,0,^o2" + else sprintf "nmaclhwso ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhwso. ^o0,0,^o2" + else sprintf "nmaclhwso. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Picbi (rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "icbi 0,^o1" + else sprintf "icbi ^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Picbt (cT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "icbt %i,0,^o1" cT + else sprintf "icbt %i,^i0,^i1" cT; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pdcba (rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dcba 0,^o1" + else sprintf "dcba ^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pdcbt (rA,rB,tH) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dcbt 0,^o1,%i" tH + else sprintf "dcbt ^i0,^i1,%i" tH; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pdcbtst (rA,rB,tH) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dcbtst 0,^o1,%i" tH + else sprintf "dcbtst ^i0,^i1,%i" tH; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pdcbz (rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dcbz 0,^o1" + else sprintf "dcbz ^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pdcbst (rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dcbst 0,^o1" + else sprintf "dcbst ^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pdcbf (rA,rB,l) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dcbf 0,^o1,%i" l + else sprintf "dcbf ^i0,^i1,%i" l; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pisync -> + { empty_ins with + memo=sprintf "isync " ; + inputs=[]; + outputs=[]; }::k +| `Plbarx (rT,rA,rB,eH) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lbarx ^o0,0,^i0,%i" eH + else sprintf "lbarx ^o0,^i0,^i1,%i" eH; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plharx (rT,rA,rB,eH) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lharx ^o0,0,^i0,%i" eH + else sprintf "lharx ^o0,^i0,^i1,%i" eH; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plwarx (rT,rA,rB,eH) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lwarx ^o0,0,^i0,%i" eH + else sprintf "lwarx ^o0,^i0,^i1,%i" eH; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pstbcx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stbcx. ^o0,0,^o2" + else sprintf "stbcx. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rS; rA; rB]); + outputs=[rS; rA; rB]; }::k +| `Psthcx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "sthcx. ^o0,0,^o2" + else sprintf "sthcx. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rS; rA; rB]); + outputs=[rS; rA; rB]; }::k +| `Pstwcx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stwcx. ^o0,0,^o2" + else sprintf "stwcx. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rS; rA; rB]); + outputs=[rS; rA; rB]; }::k +| `Pldarx (rT,rA,rB,eH) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "ldarx ^o0,0,^i0,%i" eH + else sprintf "ldarx ^o0,^i0,^i1,%i" eH; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pstdcx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stdcx. ^o0,0,^o2" + else sprintf "stdcx. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rS; rA; rB]); + outputs=[rS; rA; rB]; }::k +| `Psync (l) -> + { empty_ins with + memo=sprintf "sync %i" l; + inputs=[]; + outputs=[]; }::k +| `Peieio -> + { empty_ins with + memo=sprintf "eieio " ; + inputs=[]; + outputs=[]; }::k +| `Pwait (wC) -> + { empty_ins with + memo=sprintf "wait %i" wC; + inputs=[]; + outputs=[]; }::k diff --git a/power/gen/fold.gen b/power/gen/fold.gen new file mode 100644 index 00000000..acec75ac --- /dev/null +++ b/power/gen/fold.gen @@ -0,0 +1,368 @@ +| `Pb (DontSetAA,DontSetLK,target_addr) -> y_reg, y_sreg +| `Pb (SetAA,DontSetLK,target_addr) -> y_reg, y_sreg +| `Pb (DontSetAA,SetLK,target_addr) -> y_reg, y_sreg +| `Pb (SetAA,SetLK,target_addr) -> y_reg, y_sreg +| `Pbc (DontSetAA,DontSetLK,bO,bI,target_addr) -> y_reg, y_sreg +| `Pbc (SetAA,DontSetLK,bO,bI,target_addr) -> y_reg, y_sreg +| `Pbc (DontSetAA,SetLK,bO,bI,target_addr) -> y_reg, y_sreg +| `Pbc (SetAA,SetLK,bO,bI,target_addr) -> y_reg, y_sreg +| `Pbclr (DontSetLK,bO,bI,bH) -> y_reg, y_sreg +| `Pbclr (SetLK,bO,bI,bH) -> y_reg, y_sreg +| `Pbcctr (DontSetLK,bO,bI,bH) -> y_reg, y_sreg +| `Pbcctr (SetLK,bO,bI,bH) -> y_reg, y_sreg +| `Pcrand (bT,bA,bB) -> y_reg, y_sreg +| `Pcrnand (bT,bA,bB) -> y_reg, y_sreg +| `Pcror (bT,bA,bB) -> y_reg, y_sreg +| `Pcrxor (bT,bA,bB) -> y_reg, y_sreg +| `Pcrnor (bT,bA,bB) -> y_reg, y_sreg +| `Pcreqv (bT,bA,bB) -> y_reg, y_sreg +| `Pcrandc (bT,bA,bB) -> y_reg, y_sreg +| `Pcrorc (bT,bA,bB) -> y_reg, y_sreg +| `Pmcrf (bF,bFA) -> y_reg, y_sreg +| `Psc (lEV) -> y_reg, y_sreg +| `Pscv (lEV) -> y_reg, y_sreg +| `Plbz (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plbzx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plbzu (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plbzux (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plhz (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plhzx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plhzu (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plhzux (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plha (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plhax (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plhau (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plhaux (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plwz (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plwzx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plwzu (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plwzux (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plwa (rT,dS,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plwax (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plwaux (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pld (rT,dS,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pldx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pldu (rT,dS,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pldux (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pstb (rS,d,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Pstbx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pstbu (rS,d,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Pstbux (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Psth (rS,d,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Psthx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Psthu (rS,d,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Psthux (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pstw (rS,d,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Pstwx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pstwu (rS,d,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Pstwux (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pstd (rS,dS,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Pstdx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pstdu (rS,dS,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Pstdux (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Plq (rTp,dQ,rA,pT) -> fold_reg rA (y_reg, y_sreg) +| `Pstq (rSp,dS,rA) -> fold_reg rA (y_reg, y_sreg) +| `Plhbrx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psthbrx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Plwbrx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pstwbrx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pldbrx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pstdbrx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Plmw (rT,d,rA) -> fold_reg rA (List.fold_right fold_reg (regs_interval rT) (y_reg, y_sreg)) +| `Pstmw (rS,d,rA) -> fold_reg rA (List.fold_right fold_reg (regs_interval rS) (y_reg, y_sreg)) +| `Plswi (rT,rA,nB) -> fold_reg rA (y_reg, y_sreg) +| `Plswx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pstswi (rS,rA,nB) -> fold_reg rA (y_reg, y_sreg) +| `Pstswx (rS,rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Paddi (rT,rA,sI) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddis (rT,rA,sI) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Padd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padd (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padd (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padd (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubf (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubf (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubf (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubf (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Paddic (rT,rA,sI) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddicdot (rT,rA,sI) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfic (rT,rA,sI) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Paddc (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Paddc (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Paddc (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfc (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfc (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfc (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padde (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padde (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padde (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfe (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfe (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfe (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Paddme (DontSetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddme (DontSetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddme (SetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddme (SetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfme (DontSetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfme (DontSetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfme (SetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfme (SetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddze (DontSetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddze (DontSetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddze (SetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddze (SetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfze (DontSetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfze (DontSetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfze (SetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfze (SetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pneg (DontSetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pneg (DontSetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pneg (SetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pneg (SetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pmulli (rT,rA,sI) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pmullw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhw (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhw (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhwu (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhwu (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwe (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwe (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwe (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivweu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivweu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivweu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivweu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulld (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulld (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulld (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulld (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhd (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhd (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhdu (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhdu (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivd (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivd (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivd (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivde (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivde (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivde (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdeu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdeu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdeu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdeu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pcmpi (bF,l,rA,sI) -> fold_reg rA (y_reg, y_sreg) +| `Pcmp (bF,l,rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pcmpli (bF,l,rA,uI) -> fold_reg rA (y_reg, y_sreg) +| `Pcmpl (bF,l,rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pisel (rT,rA,rB,bC) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pandi (rA,rS,uI) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pandis (rA,rS,uI) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pori (rA,rS,uI) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Poris (rA,rS,uI) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pxori (rA,rS,uI) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pxoris (rA,rS,uI) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pand (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pand (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pxor (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pxor (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pnand (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pnand (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Por (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Por (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pnor (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pnor (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Peqv (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Peqv (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pandc (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pandc (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Porc (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Porc (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pextsb (DontSetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pextsb (SetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pextsh (DontSetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pextsh (SetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pcntlzw (DontSetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pcntlzw (SetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pcmpb (rA,rS,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Ppopcntb (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Ppopcntw (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pprtyd (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pprtyw (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pextsw (DontSetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pextsw (SetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pcntlzd (DontSetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pcntlzd (SetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Ppopcntd (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pbpermd (rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prlwinm (DontSetCR0,rA,rS,sH,mB,mE) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prlwinm (SetCR0,rA,rS,sH,mB,mE) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prlwnm (DontSetCR0,rA,rS,rB,mB,mE) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prlwnm (SetCR0,rA,rS,rB,mB,mE) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prlwimi (DontSetCR0,rA,rS,sH,mB,mE) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prlwimi (SetCR0,rA,rS,sH,mB,mE) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldicl (DontSetCR0,rA,rS,sH,mB) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldicl (SetCR0,rA,rS,sH,mB) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldicr (DontSetCR0,rA,rS,sH,mE) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldicr (SetCR0,rA,rS,sH,mE) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldic (DontSetCR0,rA,rS,sH,mB) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldic (SetCR0,rA,rS,sH,mB) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldcl (DontSetCR0,rA,rS,rB,mB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prldcl (SetCR0,rA,rS,rB,mB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prldcr (DontSetCR0,rA,rS,rB,mE) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prldcr (SetCR0,rA,rS,rB,mE) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prldimi (DontSetCR0,rA,rS,sH,mB) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldimi (SetCR0,rA,rS,sH,mB) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pslw (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pslw (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psrw (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psrw (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psrawi (DontSetCR0,rA,rS,sH) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Psrawi (SetCR0,rA,rS,sH) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Psraw (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psraw (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psld (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psld (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psrd (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psrd (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psradi (DontSetCR0,rA,rS,sH) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Psradi (SetCR0,rA,rS,sH) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Psrad (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psrad (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pcdtbcd (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pcbcdtd (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Paddg6s (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmtspr (sPR,rS) -> fold_reg rS (y_reg, y_sreg) +| `Pmfspr (rT,sPR) -> fold_reg rT (y_reg, y_sreg) +| `Pmtcrf (fXM,rS) -> fold_reg rS (y_reg, y_sreg) +| `Pmfcr (rT) -> fold_reg rT (y_reg, y_sreg) +| `Pmtocrf (fXM,rS) -> fold_reg rS (y_reg, y_sreg) +| `Pmfocrf (rT,fXM) -> fold_reg rT (y_reg, y_sreg) +| `Pmcrxr (bF) -> y_reg, y_sreg +| `Pdlmzb (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pdlmzb (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchws (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwsu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhws (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwsu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwsu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulchw (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulchw (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulchwu (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulchwu (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhhw (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhhw (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhhwu (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhhwu (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullhw (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullhw (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullhwu (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullhwu (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchws (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhws (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Picbi (rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Picbt (cT,rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pdcba (rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pdcbt (rA,rB,tH) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pdcbtst (rA,rB,tH) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pdcbz (rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pdcbst (rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pdcbf (rA,rB,l) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pisync -> y_reg, y_sreg +| `Plbarx (rT,rA,rB,eH) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plharx (rT,rA,rB,eH) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plwarx (rT,rA,rB,eH) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pstbcx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Psthcx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pstwcx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pldarx (rT,rA,rB,eH) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pstdcx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Psync (l) -> y_reg, y_sreg +| `Peieio -> y_reg, y_sreg +| `Pwait (wC) -> y_reg, y_sreg diff --git a/power/gen/herdtools_ast_to_shallow_ast.gen b/power/gen/herdtools_ast_to_shallow_ast.gen new file mode 100644 index 00000000..e1de51f7 --- /dev/null +++ b/power/gen/herdtools_ast_to_shallow_ast.gen @@ -0,0 +1,1312 @@ + | `Pb(setaa0, setlk1, k2) -> + B + (Sail_values.to_vec0 true (Nat_big_num.of_int 24,Nat_big_num.of_int (trans_li_setaa_setlk_k setaa0 setlk1 k2)), + int_to_bit (trans_aa setaa0), + int_to_bit (trans_lk setlk1)) + + | `Pbc(setaa0, setlk1, k2, k3, k4) -> + Bc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int (trans_bd_setaa_setlk_k_k_k setaa0 setlk1 k2 k3 k4)), + int_to_bit (trans_aa setaa0), + int_to_bit (trans_lk setlk1)) + + | `Pbclr(setlk0, k1, k2, k3) -> + Bclr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2), + Sail_values.to_vec0 true (Nat_big_num.of_int 2,Nat_big_num.of_int k3), + int_to_bit (trans_lk setlk0)) + + | `Pbcctr(setlk0, k1, k2, k3) -> + Bcctr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2), + Sail_values.to_vec0 true (Nat_big_num.of_int 2,Nat_big_num.of_int k3), + int_to_bit (trans_lk setlk0)) + + | `Pcrand(k0, k1, k2) -> + Crand + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcrnand(k0, k1, k2) -> + Crnand + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcror(k0, k1, k2) -> + Cror + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcrxor(k0, k1, k2) -> + Crxor + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcrnor(k0, k1, k2) -> + Crnor + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcreqv(k0, k1, k2) -> + Creqv + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcrandc(k0, k1, k2) -> + Crandc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcrorc(k0, k1, k2) -> + Crorc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pmcrf(crindex0, k1) -> + Mcrf + (Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int crindex0), + Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int k1)) + + | `Psc(k0) -> + Sc + (Sail_values.to_vec0 true (Nat_big_num.of_int 7,Nat_big_num.of_int k0)) + + | `Pscv(k0) -> + Scv + (Sail_values.to_vec0 true (Nat_big_num.of_int 7,Nat_big_num.of_int k0)) + + | `Plbz(reg0, k1, reg2) -> + Lbz + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plbzx(reg0, reg1, reg2) -> + Lbzx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plbzu(reg0, k1, reg2) -> + Lbzu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plbzux(reg0, reg1, reg2) -> + Lbzux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plhz(reg0, k1, reg2) -> + Lhz + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plhzx(reg0, reg1, reg2) -> + Lhzx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plhzu(reg0, k1, reg2) -> + Lhzu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plhzux(reg0, reg1, reg2) -> + Lhzux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plha(reg0, k1, reg2) -> + Lha + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plhax(reg0, reg1, reg2) -> + Lhax + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plhau(reg0, k1, reg2) -> + Lhau + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plhaux(reg0, reg1, reg2) -> + Lhaux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plwz(reg0, k1, reg2) -> + Lwz + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plwzx(reg0, reg1, reg2) -> + Lwzx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plwzu(reg0, k1, reg2) -> + Lwzu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plwzux(reg0, reg1, reg2) -> + Lwzux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plwa(reg0, ds1, reg2) -> + Lwa + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int ds1)) + + | `Plwax(reg0, reg1, reg2) -> + Lwax + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plwaux(reg0, reg1, reg2) -> + Lwaux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pld(reg0, ds1, reg2) -> + Ld + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int ds1)) + + | `Pldx(reg0, reg1, reg2) -> + Ldx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pldu(reg0, ds1, reg2) -> + Ldu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int ds1)) + + | `Pldux(reg0, reg1, reg2) -> + Ldux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstb(reg0, k1, reg2) -> + Stb + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Pstbx(reg0, reg1, reg2) -> + Stbx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstbu(reg0, k1, reg2) -> + Stbu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Pstbux(reg0, reg1, reg2) -> + Stbux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Psth(reg0, k1, reg2) -> + Sth + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Psthx(reg0, reg1, reg2) -> + Sthx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Psthu(reg0, k1, reg2) -> + Sthu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Psthux(reg0, reg1, reg2) -> + Sthux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstw(reg0, k1, reg2) -> + Stw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Pstwx(reg0, reg1, reg2) -> + Stwx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstwu(reg0, k1, reg2) -> + Stwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Pstwux(reg0, reg1, reg2) -> + Stwux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstd(reg0, ds1, reg2) -> + Std + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int ds1)) + + | `Pstdx(reg0, reg1, reg2) -> + Stdx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstdu(reg0, ds1, reg2) -> + Stdu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int ds1)) + + | `Pstdux(reg0, reg1, reg2) -> + Stdux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plq(k0, k1, reg2, k3) -> + Lq + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 12,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 4,Nat_big_num.of_int k3)) + + | `Pstq(k0, ds1, reg2) -> + Stq + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int ds1)) + + | `Plhbrx(reg0, reg1, reg2) -> + Lhbrx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Psthbrx(reg0, reg1, reg2) -> + Sthbrx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plwbrx(reg0, reg1, reg2) -> + Lwbrx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstwbrx(reg0, reg1, reg2) -> + Stwbrx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pldbrx(reg0, reg1, reg2) -> + Ldbrx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstdbrx(reg0, reg1, reg2) -> + Stdbrx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plmw(reg0, k1, reg2) -> + Lmw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Pstmw(reg0, k1, reg2) -> + Stmw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plswi(k0, reg1, k2) -> + Lswi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Plswx(reg0, reg1, reg2) -> + Lswx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstswi(k0, reg1, k2) -> + Stswi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pstswx(k0, reg1, reg2) -> + Stswx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Paddi(reg0, reg1, k2) -> + Addi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Paddis(reg0, reg1, k2) -> + Addis + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Padd(setsoov0, setcr01, reg2, reg3, reg4) -> + Add + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Psubf(setsoov0, setcr01, reg2, reg3, reg4) -> + Subf + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Paddic(reg0, reg1, k2) -> + Addic + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Paddicdot(reg0, reg1, k2) -> + AddicDot + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Psubfic(reg0, reg1, k2) -> + Subfic + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Paddc(setsoov0, setcr01, reg2, reg3, reg4) -> + Addc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Psubfc(setsoov0, setcr01, reg2, reg3, reg4) -> + Subfc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Padde(setsoov0, setcr01, reg2, reg3, reg4) -> + Adde + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Psubfe(setsoov0, setcr01, reg2, reg3, reg4) -> + Subfe + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Paddme(setsoov0, setcr01, reg2, reg3) -> + Addme + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Psubfme(setsoov0, setcr01, reg2, reg3) -> + Subfme + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Paddze(setsoov0, setcr01, reg2, reg3) -> + Addze + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Psubfze(setsoov0, setcr01, reg2, reg3) -> + Subfze + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pneg(setsoov0, setcr01, reg2, reg3) -> + Neg + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmulli(reg0, reg1, k2) -> + Mulli + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Pmullw(setsoov0, setcr01, reg2, reg3, reg4) -> + Mullw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmulhw(setcr00, reg1, reg2, reg3) -> + Mulhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmulhwu(setcr00, reg1, reg2, reg3) -> + Mulhwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pdivw(setsoov0, setcr01, reg2, reg3, reg4) -> + Divw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pdivwu(setsoov0, setcr01, reg2, reg3, reg4) -> + Divwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pdivwe(setsoov0, setcr01, reg2, reg3, reg4) -> + Divwe + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pdivweu(setsoov0, setcr01, reg2, reg3, reg4) -> + Divweu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmulld(setsoov0, setcr01, reg2, reg3, reg4) -> + Mulld + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmulhd(setcr00, reg1, reg2, reg3) -> + Mulhd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmulhdu(setcr00, reg1, reg2, reg3) -> + Mulhdu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pdivd(setsoov0, setcr01, reg2, reg3, reg4) -> + Divd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pdivdu(setsoov0, setcr01, reg2, reg3, reg4) -> + Divdu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pdivde(setsoov0, setcr01, reg2, reg3, reg4) -> + Divde + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pdivdeu(setsoov0, setcr01, reg2, reg3, reg4) -> + Divdeu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pcmpi(crindex0, k1, reg2, k3) -> + Cmpi + (Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int crindex0), + int_to_bit k1, + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k3)) + + | `Pcmp(crindex0, k1, reg2, reg3) -> + Cmp + (Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int crindex0), + int_to_bit k1, + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3))) + + | `Pcmpli(crindex0, k1, reg2, k3) -> + Cmpli + (Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int crindex0), + int_to_bit k1, + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k3)) + + | `Pcmpl(crindex0, k1, reg2, reg3) -> + Cmpl + (Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int crindex0), + int_to_bit k1, + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3))) + + | `Pisel(reg0, reg1, reg2, k3) -> + Isel + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k3)) + + | `Pandi(reg0, reg1, k2) -> + Andi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Pandis(reg0, reg1, k2) -> + Andis + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Pori(reg0, reg1, k2) -> + Ori + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Poris(reg0, reg1, k2) -> + Oris + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Pxori(reg0, reg1, k2) -> + Xori + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Pxoris(reg0, reg1, k2) -> + Xoris + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Pand(setcr00, reg1, reg2, reg3) -> + And + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pxor(setcr00, reg1, reg2, reg3) -> + Xor + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pnand(setcr00, reg1, reg2, reg3) -> + Nand + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Por(setcr00, reg1, reg2, reg3) -> + Or + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pnor(setcr00, reg1, reg2, reg3) -> + Nor + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Peqv(setcr00, reg1, reg2, reg3) -> + Eqv + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pandc(setcr00, reg1, reg2, reg3) -> + Andc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Porc(setcr00, reg1, reg2, reg3) -> + Orc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pextsb(setcr00, reg1, reg2) -> + Extsb + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + int_to_bit (trans_cr0 setcr00)) + + | `Pextsh(setcr00, reg1, reg2) -> + Extsh + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + int_to_bit (trans_cr0 setcr00)) + + | `Pcntlzw(setcr00, reg1, reg2) -> + Cntlzw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + int_to_bit (trans_cr0 setcr00)) + + | `Pcmpb(reg0, k1, reg2) -> + Cmpb + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Ppopcntb(reg0, reg1) -> + Popcntb + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Ppopcntw(reg0, reg1) -> + Popcntw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Pprtyd(reg0, reg1) -> + Prtyd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Pprtyw(reg0, reg1) -> + Prtyw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Pextsw(setcr00, reg1, reg2) -> + Extsw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + int_to_bit (trans_cr0 setcr00)) + + | `Pcntlzd(setcr00, reg1, reg2) -> + Cntlzd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + int_to_bit (trans_cr0 setcr00)) + + | `Ppopcntd(reg0, reg1) -> + Popcntd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Pbpermd(reg0, reg1, reg2) -> + Bpermd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Prlwinm(setcr00, reg1, reg2, k3, k4, k5) -> + Rlwinm + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k4), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k5), + int_to_bit (trans_cr0 setcr00)) + + | `Prlwnm(setcr00, reg1, reg2, reg3, k4, k5) -> + Rlwnm + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k4), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k5), + int_to_bit (trans_cr0 setcr00)) + + | `Prlwimi(setcr00, reg1, reg2, k3, k4, k5) -> + Rlwimi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k4), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k5), + int_to_bit (trans_cr0 setcr00)) + + | `Prldicl(setcr00, reg1, reg2, k3, k4) -> + Rldicl + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k4), + int_to_bit (trans_cr0 setcr00)) + + | `Prldicr(setcr00, reg1, reg2, k3, k4) -> + Rldicr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k4), + int_to_bit (trans_cr0 setcr00)) + + | `Prldic(setcr00, reg1, reg2, k3, k4) -> + Rldic + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k4), + int_to_bit (trans_cr0 setcr00)) + + | `Prldcl(setcr00, reg1, reg2, reg3, k4) -> + Rldcl + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k4), + int_to_bit (trans_cr0 setcr00)) + + | `Prldcr(setcr00, reg1, reg2, reg3, k4) -> + Rldcr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k4), + int_to_bit (trans_cr0 setcr00)) + + | `Prldimi(setcr00, reg1, reg2, k3, k4) -> + Rldimi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k4), + int_to_bit (trans_cr0 setcr00)) + + | `Pslw(setcr00, reg1, reg2, reg3) -> + Slw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Psrw(setcr00, reg1, reg2, reg3) -> + Srw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Psrawi(setcr00, reg1, reg2, k3) -> + Srawi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k3), + int_to_bit (trans_cr0 setcr00)) + + | `Psraw(setcr00, reg1, reg2, reg3) -> + Sraw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Psld(setcr00, reg1, reg2, reg3) -> + Sld + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Psrd(setcr00, reg1, reg2, reg3) -> + Srd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Psradi(setcr00, reg1, reg2, k3) -> + Sradi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k3), + int_to_bit (trans_cr0 setcr00)) + + | `Psrad(setcr00, reg1, reg2, reg3) -> + Srad + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pcdtbcd(reg0, reg1) -> + Cdtbcd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Pcbcdtd(reg0, reg1) -> + Cbcdtd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Paddg6s(reg0, reg1, reg2) -> + Addg6s + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pmtspr(k0, reg1) -> + Mtspr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 10,Nat_big_num.of_int k0)) + + | `Pmfspr(reg0, k1) -> + Mfspr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 10,Nat_big_num.of_int k1)) + + | `Pmtcrf(crmask0, reg1) -> + Mtcrf + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 8,Nat_big_num.of_int crmask0)) + + | `Pmfcr(reg0) -> + Mfcr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Pmtocrf(crmask0, reg1) -> + Mtocrf + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 8,Nat_big_num.of_int crmask0)) + + | `Pmfocrf(reg0, crmask1) -> + Mfocrf + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 8,Nat_big_num.of_int crmask1)) + + | `Pmcrxr(crindex0) -> + Mcrxr + (Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int crindex0)) + + | `Pdlmzb(setcr00, reg1, reg2, reg3) -> + Dlmzb + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmacchw(setsoov0, setcr01, reg2, reg3, reg4) -> + Macchw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmacchws(setsoov0, setcr01, reg2, reg3, reg4) -> + Macchws + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmacchwu(setsoov0, setcr01, reg2, reg3, reg4) -> + Macchwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmacchwsu(setsoov0, setcr01, reg2, reg3, reg4) -> + Macchwsu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmachhw(setsoov0, setcr01, reg2, reg3, reg4) -> + Machhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmachhws(setsoov0, setcr01, reg2, reg3, reg4) -> + Machhws + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmachhwu(setsoov0, setcr01, reg2, reg3, reg4) -> + Machhwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmachhwsu(setsoov0, setcr01, reg2, reg3, reg4) -> + Machhwsu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmaclhw(setsoov0, setcr01, reg2, reg3, reg4) -> + Maclhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmaclhws(setsoov0, setcr01, reg2, reg3, reg4) -> + Maclhws + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmaclhwu(setsoov0, setcr01, reg2, reg3, reg4) -> + Maclhwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmaclhwsu(setsoov0, setcr01, reg2, reg3, reg4) -> + Maclhwsu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmulchw(setcr00, reg1, reg2, reg3) -> + Mulchw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmulchwu(setcr00, reg1, reg2, reg3) -> + Mulchwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmulhhw(setcr00, reg1, reg2, reg3) -> + Mulhhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmulhhwu(setcr00, reg1, reg2, reg3) -> + Mulhhwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmullhw(setcr00, reg1, reg2, reg3) -> + Mullhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmullhwu(setcr00, reg1, reg2, reg3) -> + Mullhwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pnmacchw(setsoov0, setcr01, reg2, reg3, reg4) -> + Nmacchw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pnmacchws(setsoov0, setcr01, reg2, reg3, reg4) -> + Nmacchws + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pnmachhw(setsoov0, setcr01, reg2, reg3, reg4) -> + Nmachhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pnmachhws(setsoov0, setcr01, reg2, reg3, reg4) -> + Nmachhws + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pnmaclhw(setsoov0, setcr01, reg2, reg3, reg4) -> + Nmaclhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pnmaclhws(setsoov0, setcr01, reg2, reg3, reg4) -> + Nmaclhws + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Picbi(reg0, reg1) -> + Icbi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Picbt(k0, reg1, reg2) -> + Icbt + (Sail_values.to_vec0 true (Nat_big_num.of_int 4,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pdcba(reg0, reg1) -> + Dcba + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Pdcbt(reg0, reg1, k2) -> + Dcbt + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Pdcbtst(reg0, reg1, k2) -> + Dcbtst + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Pdcbz(reg0, reg1) -> + Dcbz + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Pdcbst(reg0, reg1) -> + Dcbst + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Pdcbf(reg0, reg1, k2) -> + Dcbf + (Sail_values.to_vec0 true (Nat_big_num.of_int 2,Nat_big_num.of_int k2), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Pisync -> + Isync + + | `Plbarx(reg0, reg1, reg2, k3) -> + Lbarx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + int_to_bit k3) + + | `Plharx(reg0, reg1, reg2, k3) -> + Lharx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + int_to_bit k3) + + | `Plwarx(reg0, reg1, reg2, k3) -> + Lwarx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + int_to_bit k3) + + | `Pstbcx(reg0, reg1, reg2) -> + Stbcx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Psthcx(reg0, reg1, reg2) -> + Sthcx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstwcx(reg0, reg1, reg2) -> + Stwcx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pldarx(reg0, reg1, reg2, k3) -> + Ldarx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + int_to_bit k3) + + | `Pstdcx(reg0, reg1, reg2) -> + Stdcx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Psync(k0) -> + Sync + (Sail_values.to_vec0 true (Nat_big_num.of_int 2,Nat_big_num.of_int k0)) + + | `Peieio -> + Eieio + + | `Pwait(k0) -> + Wait + (Sail_values.to_vec0 true (Nat_big_num.of_int 2,Nat_big_num.of_int k0)) + diff --git a/power/gen/lexer.gen b/power/gen/lexer.gen new file mode 100644 index 00000000..a2100883 --- /dev/null +++ b/power/gen/lexer.gen @@ -0,0 +1,368 @@ + "b", B; + "ba", BA; + "bl", BL; + "bla", BLA; + "bc", BC; + "bca", BCA; + "bcl", BCL; + "bcla", BCLA; + "bclr", BCLR; + "bclrl", BCLRL; + "bcctr", BCCTR; + "bcctrl", BCCTRL; + "crand", CRAND; + "crnand", CRNAND; + "cror", CROR; + "crxor", CRXOR; + "crnor", CRNOR; + "creqv", CREQV; + "crandc", CRANDC; + "crorc", CRORC; + "mcrf", MCRF; + "sc", SC; + "scv", SCV; + "lbz", LBZ; + "lbzx", LBZX; + "lbzu", LBZU; + "lbzux", LBZUX; + "lhz", LHZ; + "lhzx", LHZX; + "lhzu", LHZU; + "lhzux", LHZUX; + "lha", LHA; + "lhax", LHAX; + "lhau", LHAU; + "lhaux", LHAUX; + "lwz", LWZ; + "lwzx", LWZX; + "lwzu", LWZU; + "lwzux", LWZUX; + "lwa", LWA; + "lwax", LWAX; + "lwaux", LWAUX; + "ld", LD; + "ldx", LDX; + "ldu", LDU; + "ldux", LDUX; + "stb", STB; + "stbx", STBX; + "stbu", STBU; + "stbux", STBUX; + "sth", STH; + "sthx", STHX; + "sthu", STHU; + "sthux", STHUX; + "stw", STW; + "stwx", STWX; + "stwu", STWU; + "stwux", STWUX; + "std", STD; + "stdx", STDX; + "stdu", STDU; + "stdux", STDUX; + "lq", LQ; + "stq", STQ; + "lhbrx", LHBRX; + "sthbrx", STHBRX; + "lwbrx", LWBRX; + "stwbrx", STWBRX; + "ldbrx", LDBRX; + "stdbrx", STDBRX; + "lmw", LMW; + "stmw", STMW; + "lswi", LSWI; + "lswx", LSWX; + "stswi", STSWI; + "stswx", STSWX; + "addi", ADDI; + "addis", ADDIS; + "add", ADD; + "add.", ADDDOT; + "addo", ADDO; + "addo.", ADDODOT; + "subf", SUBF; + "subf.", SUBFDOT; + "subfo", SUBFO; + "subfo.", SUBFODOT; + "addic", ADDIC; + "addic.", ADDICDOT; + "subfic", SUBFIC; + "addc", ADDC; + "addc.", ADDCDOT; + "addco", ADDCO; + "addco.", ADDCODOT; + "subfc", SUBFC; + "subfc.", SUBFCDOT; + "subfco", SUBFCO; + "subfco.", SUBFCODOT; + "adde", ADDE; + "adde.", ADDEDOT; + "addeo", ADDEO; + "addeo.", ADDEODOT; + "subfe", SUBFE; + "subfe.", SUBFEDOT; + "subfeo", SUBFEO; + "subfeo.", SUBFEODOT; + "addme", ADDME; + "addme.", ADDMEDOT; + "addmeo", ADDMEO; + "addmeo.", ADDMEODOT; + "subfme", SUBFME; + "subfme.", SUBFMEDOT; + "subfmeo", SUBFMEO; + "subfmeo.", SUBFMEODOT; + "addze", ADDZE; + "addze.", ADDZEDOT; + "addzeo", ADDZEO; + "addzeo.", ADDZEODOT; + "subfze", SUBFZE; + "subfze.", SUBFZEDOT; + "subfzeo", SUBFZEO; + "subfzeo.", SUBFZEODOT; + "neg", NEG; + "neg.", NEGDOT; + "nego", NEGO; + "nego.", NEGODOT; + "mulli", MULLI; + "mullw", MULLW; + "mullw.", MULLWDOT; + "mullwo", MULLWO; + "mullwo.", MULLWODOT; + "mulhw", MULHW; + "mulhw.", MULHWDOT; + "mulhwu", MULHWU; + "mulhwu.", MULHWUDOT; + "divw", DIVW; + "divw.", DIVWDOT; + "divwo", DIVWO; + "divwo.", DIVWODOT; + "divwu", DIVWU; + "divwu.", DIVWUDOT; + "divwuo", DIVWUO; + "divwuo.", DIVWUODOT; + "divwe", DIVWE; + "divwe.", DIVWEDOT; + "divweo", DIVWEO; + "divweo.", DIVWEODOT; + "divweu", DIVWEU; + "divweu.", DIVWEUDOT; + "divweuo", DIVWEUO; + "divweuo.", DIVWEUODOT; + "mulld", MULLD; + "mulld.", MULLDDOT; + "mulldo", MULLDO; + "mulldo.", MULLDODOT; + "mulhd", MULHD; + "mulhd.", MULHDDOT; + "mulhdu", MULHDU; + "mulhdu.", MULHDUDOT; + "divd", DIVD; + "divd.", DIVDDOT; + "divdo", DIVDO; + "divdo.", DIVDODOT; + "divdu", DIVDU; + "divdu.", DIVDUDOT; + "divduo", DIVDUO; + "divduo.", DIVDUODOT; + "divde", DIVDE; + "divde.", DIVDEDOT; + "divdeo", DIVDEO; + "divdeo.", DIVDEODOT; + "divdeu", DIVDEU; + "divdeu.", DIVDEUDOT; + "divdeuo", DIVDEUO; + "divdeuo.", DIVDEUODOT; + "cmpi", CMPI; + "cmp", CMP; + "cmpli", CMPLI; + "cmpl", CMPL; + "isel", ISEL; + "andi.", ANDIDOT; + "andis.", ANDISDOT; + "ori", ORI; + "oris", ORIS; + "xori", XORI; + "xoris", XORIS; + "and", AND; + "and.", ANDDOT; + "xor", XOR; + "xor.", XORDOT; + "nand", NAND; + "nand.", NANDDOT; + "or", OR; + "or.", ORDOT; + "nor", NOR; + "nor.", NORDOT; + "eqv", EQV; + "eqv.", EQVDOT; + "andc", ANDC; + "andc.", ANDCDOT; + "orc", ORC; + "orc.", ORCDOT; + "extsb", EXTSB; + "extsb.", EXTSBDOT; + "extsh", EXTSH; + "extsh.", EXTSHDOT; + "cntlzw", CNTLZW; + "cntlzw.", CNTLZWDOT; + "cmpb", CMPB; + "popcntb", POPCNTB; + "popcntw", POPCNTW; + "prtyd", PRTYD; + "prtyw", PRTYW; + "extsw", EXTSW; + "extsw.", EXTSWDOT; + "cntlzd", CNTLZD; + "cntlzd.", CNTLZDDOT; + "popcntd", POPCNTD; + "bpermd", BPERMD; + "rlwinm", RLWINM; + "rlwinm.", RLWINMDOT; + "rlwnm", RLWNM; + "rlwnm.", RLWNMDOT; + "rlwimi", RLWIMI; + "rlwimi.", RLWIMIDOT; + "rldicl", RLDICL; + "rldicl.", RLDICLDOT; + "rldicr", RLDICR; + "rldicr.", RLDICRDOT; + "rldic", RLDIC; + "rldic.", RLDICDOT; + "rldcl", RLDCL; + "rldcl.", RLDCLDOT; + "rldcr", RLDCR; + "rldcr.", RLDCRDOT; + "rldimi", RLDIMI; + "rldimi.", RLDIMIDOT; + "slw", SLW; + "slw.", SLWDOT; + "srw", SRW; + "srw.", SRWDOT; + "srawi", SRAWI; + "srawi.", SRAWIDOT; + "sraw", SRAW; + "sraw.", SRAWDOT; + "sld", SLD; + "sld.", SLDDOT; + "srd", SRD; + "srd.", SRDDOT; + "sradi", SRADI; + "sradi.", SRADIDOT; + "srad", SRAD; + "srad.", SRADDOT; + "cdtbcd", CDTBCD; + "cbcdtd", CBCDTD; + "addg6s", ADDG6S; + "mtspr", MTSPR; + "mfspr", MFSPR; + "mtcrf", MTCRF; + "mfcr", MFCR; + "mtocrf", MTOCRF; + "mfocrf", MFOCRF; + "mcrxr", MCRXR; + "dlmzb", DLMZB; + "dlmzb.", DLMZBDOT; + "macchw", MACCHW; + "macchw.", MACCHWDOT; + "macchwo", MACCHWO; + "macchwo.", MACCHWODOT; + "macchws", MACCHWS; + "macchws.", MACCHWSDOT; + "macchwso", MACCHWSO; + "macchwso.", MACCHWSODOT; + "macchwu", MACCHWU; + "macchwu.", MACCHWUDOT; + "macchwuo", MACCHWUO; + "macchwuo.", MACCHWUODOT; + "macchwsu", MACCHWSU; + "macchwsu.", MACCHWSUDOT; + "macchwsuo", MACCHWSUO; + "macchwsuo.", MACCHWSUODOT; + "machhw", MACHHW; + "machhw.", MACHHWDOT; + "machhwo", MACHHWO; + "machhwo.", MACHHWODOT; + "machhws", MACHHWS; + "machhws.", MACHHWSDOT; + "machhwso", MACHHWSO; + "machhwso.", MACHHWSODOT; + "machhwu", MACHHWU; + "machhwu.", MACHHWUDOT; + "machhwuo", MACHHWUO; + "machhwuo.", MACHHWUODOT; + "machhwsu", MACHHWSU; + "machhwsu.", MACHHWSUDOT; + "machhwsuo", MACHHWSUO; + "machhwsuo.", MACHHWSUODOT; + "maclhw", MACLHW; + "maclhw.", MACLHWDOT; + "maclhwo", MACLHWO; + "maclhwo.", MACLHWODOT; + "maclhws", MACLHWS; + "maclhws.", MACLHWSDOT; + "maclhwso", MACLHWSO; + "maclhwso.", MACLHWSODOT; + "maclhwu", MACLHWU; + "maclhwu.", MACLHWUDOT; + "maclhwuo", MACLHWUO; + "maclhwuo.", MACLHWUODOT; + "maclhwsu", MACLHWSU; + "maclhwsu.", MACLHWSUDOT; + "maclhwsuo", MACLHWSUO; + "maclhwsuo.", MACLHWSUODOT; + "mulchw", MULCHW; + "mulchw.", MULCHWDOT; + "mulchwu", MULCHWU; + "mulchwu.", MULCHWUDOT; + "mulhhw", MULHHW; + "mulhhw.", MULHHWDOT; + "mulhhwu", MULHHWU; + "mulhhwu.", MULHHWUDOT; + "mullhw", MULLHW; + "mullhw.", MULLHWDOT; + "mullhwu", MULLHWU; + "mullhwu.", MULLHWUDOT; + "nmacchw", NMACCHW; + "nmacchw.", NMACCHWDOT; + "nmacchwo", NMACCHWO; + "nmacchwo.", NMACCHWODOT; + "nmacchws", NMACCHWS; + "nmacchws.", NMACCHWSDOT; + "nmacchwso", NMACCHWSO; + "nmacchwso.", NMACCHWSODOT; + "nmachhw", NMACHHW; + "nmachhw.", NMACHHWDOT; + "nmachhwo", NMACHHWO; + "nmachhwo.", NMACHHWODOT; + "nmachhws", NMACHHWS; + "nmachhws.", NMACHHWSDOT; + "nmachhwso", NMACHHWSO; + "nmachhwso.", NMACHHWSODOT; + "nmaclhw", NMACLHW; + "nmaclhw.", NMACLHWDOT; + "nmaclhwo", NMACLHWO; + "nmaclhwo.", NMACLHWODOT; + "nmaclhws", NMACLHWS; + "nmaclhws.", NMACLHWSDOT; + "nmaclhwso", NMACLHWSO; + "nmaclhwso.", NMACLHWSODOT; + "icbi", ICBI; + "icbt", ICBT; + "dcba", DCBA; + "dcbt", DCBT; + "dcbtst", DCBTST; + "dcbz", DCBZ; + "dcbst", DCBST; + "dcbf", DCBF; + "isync", ISYNC; + "lbarx", LBARX; + "lharx", LHARX; + "lwarx", LWARX; + "stbcx.", STBCXDOT; + "sthcx.", STHCXDOT; + "stwcx.", STWCXDOT; + "ldarx", LDARX; + "stdcx.", STDCXDOT; + "sync", SYNC; + "eieio", EIEIO; + "wait", WAIT; diff --git a/power/gen/map.gen b/power/gen/map.gen new file mode 100644 index 00000000..27833b80 --- /dev/null +++ b/power/gen/map.gen @@ -0,0 +1,368 @@ +| `Pb (DontSetAA,DontSetLK,target_addr) -> `Pb(DontSetAA,DontSetLK,target_addr) +| `Pb (SetAA,DontSetLK,target_addr) -> `Pb(SetAA,DontSetLK,target_addr) +| `Pb (DontSetAA,SetLK,target_addr) -> `Pb(DontSetAA,SetLK,target_addr) +| `Pb (SetAA,SetLK,target_addr) -> `Pb(SetAA,SetLK,target_addr) +| `Pbc (DontSetAA,DontSetLK,bO,bI,target_addr) -> `Pbc(DontSetAA,DontSetLK,bO,bI,target_addr) +| `Pbc (SetAA,DontSetLK,bO,bI,target_addr) -> `Pbc(SetAA,DontSetLK,bO,bI,target_addr) +| `Pbc (DontSetAA,SetLK,bO,bI,target_addr) -> `Pbc(DontSetAA,SetLK,bO,bI,target_addr) +| `Pbc (SetAA,SetLK,bO,bI,target_addr) -> `Pbc(SetAA,SetLK,bO,bI,target_addr) +| `Pbclr (DontSetLK,bO,bI,bH) -> `Pbclr(DontSetLK,bO,bI,bH) +| `Pbclr (SetLK,bO,bI,bH) -> `Pbclr(SetLK,bO,bI,bH) +| `Pbcctr (DontSetLK,bO,bI,bH) -> `Pbcctr(DontSetLK,bO,bI,bH) +| `Pbcctr (SetLK,bO,bI,bH) -> `Pbcctr(SetLK,bO,bI,bH) +| `Pcrand (bT,bA,bB) -> `Pcrand(bT,bA,bB) +| `Pcrnand (bT,bA,bB) -> `Pcrnand(bT,bA,bB) +| `Pcror (bT,bA,bB) -> `Pcror(bT,bA,bB) +| `Pcrxor (bT,bA,bB) -> `Pcrxor(bT,bA,bB) +| `Pcrnor (bT,bA,bB) -> `Pcrnor(bT,bA,bB) +| `Pcreqv (bT,bA,bB) -> `Pcreqv(bT,bA,bB) +| `Pcrandc (bT,bA,bB) -> `Pcrandc(bT,bA,bB) +| `Pcrorc (bT,bA,bB) -> `Pcrorc(bT,bA,bB) +| `Pmcrf (bF,bFA) -> `Pmcrf(bF,bFA) +| `Psc (lEV) -> `Psc(lEV) +| `Pscv (lEV) -> `Pscv(lEV) +| `Plbz (rT,d,rA) -> `Plbz(map_reg rT,d,map_reg rA) +| `Plbzx (rT,rA,rB) -> `Plbzx(map_reg rT,map_reg rA,map_reg rB) +| `Plbzu (rT,d,rA) -> `Plbzu(map_reg rT,d,map_reg rA) +| `Plbzux (rT,rA,rB) -> `Plbzux(map_reg rT,map_reg rA,map_reg rB) +| `Plhz (rT,d,rA) -> `Plhz(map_reg rT,d,map_reg rA) +| `Plhzx (rT,rA,rB) -> `Plhzx(map_reg rT,map_reg rA,map_reg rB) +| `Plhzu (rT,d,rA) -> `Plhzu(map_reg rT,d,map_reg rA) +| `Plhzux (rT,rA,rB) -> `Plhzux(map_reg rT,map_reg rA,map_reg rB) +| `Plha (rT,d,rA) -> `Plha(map_reg rT,d,map_reg rA) +| `Plhax (rT,rA,rB) -> `Plhax(map_reg rT,map_reg rA,map_reg rB) +| `Plhau (rT,d,rA) -> `Plhau(map_reg rT,d,map_reg rA) +| `Plhaux (rT,rA,rB) -> `Plhaux(map_reg rT,map_reg rA,map_reg rB) +| `Plwz (rT,d,rA) -> `Plwz(map_reg rT,d,map_reg rA) +| `Plwzx (rT,rA,rB) -> `Plwzx(map_reg rT,map_reg rA,map_reg rB) +| `Plwzu (rT,d,rA) -> `Plwzu(map_reg rT,d,map_reg rA) +| `Plwzux (rT,rA,rB) -> `Plwzux(map_reg rT,map_reg rA,map_reg rB) +| `Plwa (rT,dS,rA) -> `Plwa(map_reg rT,dS,map_reg rA) +| `Plwax (rT,rA,rB) -> `Plwax(map_reg rT,map_reg rA,map_reg rB) +| `Plwaux (rT,rA,rB) -> `Plwaux(map_reg rT,map_reg rA,map_reg rB) +| `Pld (rT,dS,rA) -> `Pld(map_reg rT,dS,map_reg rA) +| `Pldx (rT,rA,rB) -> `Pldx(map_reg rT,map_reg rA,map_reg rB) +| `Pldu (rT,dS,rA) -> `Pldu(map_reg rT,dS,map_reg rA) +| `Pldux (rT,rA,rB) -> `Pldux(map_reg rT,map_reg rA,map_reg rB) +| `Pstb (rS,d,rA) -> `Pstb(map_reg rS,d,map_reg rA) +| `Pstbx (rS,rA,rB) -> `Pstbx(map_reg rS,map_reg rA,map_reg rB) +| `Pstbu (rS,d,rA) -> `Pstbu(map_reg rS,d,map_reg rA) +| `Pstbux (rS,rA,rB) -> `Pstbux(map_reg rS,map_reg rA,map_reg rB) +| `Psth (rS,d,rA) -> `Psth(map_reg rS,d,map_reg rA) +| `Psthx (rS,rA,rB) -> `Psthx(map_reg rS,map_reg rA,map_reg rB) +| `Psthu (rS,d,rA) -> `Psthu(map_reg rS,d,map_reg rA) +| `Psthux (rS,rA,rB) -> `Psthux(map_reg rS,map_reg rA,map_reg rB) +| `Pstw (rS,d,rA) -> `Pstw(map_reg rS,d,map_reg rA) +| `Pstwx (rS,rA,rB) -> `Pstwx(map_reg rS,map_reg rA,map_reg rB) +| `Pstwu (rS,d,rA) -> `Pstwu(map_reg rS,d,map_reg rA) +| `Pstwux (rS,rA,rB) -> `Pstwux(map_reg rS,map_reg rA,map_reg rB) +| `Pstd (rS,dS,rA) -> `Pstd(map_reg rS,dS,map_reg rA) +| `Pstdx (rS,rA,rB) -> `Pstdx(map_reg rS,map_reg rA,map_reg rB) +| `Pstdu (rS,dS,rA) -> `Pstdu(map_reg rS,dS,map_reg rA) +| `Pstdux (rS,rA,rB) -> `Pstdux(map_reg rS,map_reg rA,map_reg rB) +| `Plq (rTp,dQ,rA,pT) -> `Plq(rTp,dQ,map_reg rA,pT) +| `Pstq (rSp,dS,rA) -> `Pstq(rSp,dS,map_reg rA) +| `Plhbrx (rT,rA,rB) -> `Plhbrx(map_reg rT,map_reg rA,map_reg rB) +| `Psthbrx (rS,rA,rB) -> `Psthbrx(map_reg rS,map_reg rA,map_reg rB) +| `Plwbrx (rT,rA,rB) -> `Plwbrx(map_reg rT,map_reg rA,map_reg rB) +| `Pstwbrx (rS,rA,rB) -> `Pstwbrx(map_reg rS,map_reg rA,map_reg rB) +| `Pldbrx (rT,rA,rB) -> `Pldbrx(map_reg rT,map_reg rA,map_reg rB) +| `Pstdbrx (rS,rA,rB) -> `Pstdbrx(map_reg rS,map_reg rA,map_reg rB) +| `Plmw (rT,d,rA) -> `Plmw(rT,d,map_reg rA) +| `Pstmw (rS,d,rA) -> `Pstmw(rS,d,map_reg rA) +| `Plswi (rT,rA,nB) -> `Plswi(rT,map_reg rA,nB) +| `Plswx (rT,rA,rB) -> `Plswx(map_reg rT,map_reg rA,map_reg rB) +| `Pstswi (rS,rA,nB) -> `Pstswi(rS,map_reg rA,nB) +| `Pstswx (rS,rA,rB) -> `Pstswx(rS,map_reg rA,map_reg rB) +| `Paddi (rT,rA,sI) -> `Paddi(map_reg rT,map_reg rA,sI) +| `Paddis (rT,rA,sI) -> `Paddis(map_reg rT,map_reg rA,sI) +| `Padd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Padd(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padd (DontSetSOOV,SetCR0,rT,rA,rB) -> `Padd(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padd (SetSOOV,DontSetCR0,rT,rA,rB) -> `Padd(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padd (SetSOOV,SetCR0,rT,rA,rB) -> `Padd(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubf (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Psubf(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubf (DontSetSOOV,SetCR0,rT,rA,rB) -> `Psubf(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubf (SetSOOV,DontSetCR0,rT,rA,rB) -> `Psubf(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubf (SetSOOV,SetCR0,rT,rA,rB) -> `Psubf(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Paddic (rT,rA,sI) -> `Paddic(map_reg rT,map_reg rA,sI) +| `Paddicdot (rT,rA,sI) -> `Paddicdot(map_reg rT,map_reg rA,sI) +| `Psubfic (rT,rA,sI) -> `Psubfic(map_reg rT,map_reg rA,sI) +| `Paddc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Paddc(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Paddc (DontSetSOOV,SetCR0,rT,rA,rB) -> `Paddc(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Paddc (SetSOOV,DontSetCR0,rT,rA,rB) -> `Paddc(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Paddc (SetSOOV,SetCR0,rT,rA,rB) -> `Paddc(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Psubfc(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfc (DontSetSOOV,SetCR0,rT,rA,rB) -> `Psubfc(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfc (SetSOOV,DontSetCR0,rT,rA,rB) -> `Psubfc(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfc (SetSOOV,SetCR0,rT,rA,rB) -> `Psubfc(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Padde(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padde (DontSetSOOV,SetCR0,rT,rA,rB) -> `Padde(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padde (SetSOOV,DontSetCR0,rT,rA,rB) -> `Padde(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padde (SetSOOV,SetCR0,rT,rA,rB) -> `Padde(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Psubfe(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfe (DontSetSOOV,SetCR0,rT,rA,rB) -> `Psubfe(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfe (SetSOOV,DontSetCR0,rT,rA,rB) -> `Psubfe(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfe (SetSOOV,SetCR0,rT,rA,rB) -> `Psubfe(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Paddme (DontSetSOOV,DontSetCR0,rT,rA) -> `Paddme(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Paddme (DontSetSOOV,SetCR0,rT,rA) -> `Paddme(DontSetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Paddme (SetSOOV,DontSetCR0,rT,rA) -> `Paddme(SetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Paddme (SetSOOV,SetCR0,rT,rA) -> `Paddme(SetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Psubfme (DontSetSOOV,DontSetCR0,rT,rA) -> `Psubfme(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Psubfme (DontSetSOOV,SetCR0,rT,rA) -> `Psubfme(DontSetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Psubfme (SetSOOV,DontSetCR0,rT,rA) -> `Psubfme(SetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Psubfme (SetSOOV,SetCR0,rT,rA) -> `Psubfme(SetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Paddze (DontSetSOOV,DontSetCR0,rT,rA) -> `Paddze(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Paddze (DontSetSOOV,SetCR0,rT,rA) -> `Paddze(DontSetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Paddze (SetSOOV,DontSetCR0,rT,rA) -> `Paddze(SetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Paddze (SetSOOV,SetCR0,rT,rA) -> `Paddze(SetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Psubfze (DontSetSOOV,DontSetCR0,rT,rA) -> `Psubfze(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Psubfze (DontSetSOOV,SetCR0,rT,rA) -> `Psubfze(DontSetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Psubfze (SetSOOV,DontSetCR0,rT,rA) -> `Psubfze(SetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Psubfze (SetSOOV,SetCR0,rT,rA) -> `Psubfze(SetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Pneg (DontSetSOOV,DontSetCR0,rT,rA) -> `Pneg(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Pneg (DontSetSOOV,SetCR0,rT,rA) -> `Pneg(DontSetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Pneg (SetSOOV,DontSetCR0,rT,rA) -> `Pneg(SetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Pneg (SetSOOV,SetCR0,rT,rA) -> `Pneg(SetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Pmulli (rT,rA,sI) -> `Pmulli(map_reg rT,map_reg rA,sI) +| `Pmullw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmullw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmullw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmullw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullw (SetSOOV,SetCR0,rT,rA,rB) -> `Pmullw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhw (DontSetCR0,rT,rA,rB) -> `Pmulhw(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhw (SetCR0,rT,rA,rB) -> `Pmulhw(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhwu (DontSetCR0,rT,rA,rB) -> `Pmulhwu(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhwu (SetCR0,rT,rA,rB) -> `Pmulhwu(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivw (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivwu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivwu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivwu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwu (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivwu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivwe(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwe (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivwe(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwe (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivwe(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwe (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivwe(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivweu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivweu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivweu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivweu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivweu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivweu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivweu (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivweu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulld (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmulld(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulld (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmulld(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulld (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmulld(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulld (SetSOOV,SetCR0,rT,rA,rB) -> `Pmulld(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhd (DontSetCR0,rT,rA,rB) -> `Pmulhd(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhd (SetCR0,rT,rA,rB) -> `Pmulhd(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhdu (DontSetCR0,rT,rA,rB) -> `Pmulhdu(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhdu (SetCR0,rT,rA,rB) -> `Pmulhdu(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivd(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivd (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivd(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivd (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivd(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivd (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivd(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivdu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivdu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivdu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdu (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivdu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivde(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivde (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivde(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivde (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivde(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivde (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivde(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdeu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivdeu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdeu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivdeu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdeu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivdeu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdeu (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivdeu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pcmpi (bF,l,rA,sI) -> `Pcmpi(bF,l,map_reg rA,sI) +| `Pcmp (bF,l,rA,rB) -> `Pcmp(bF,l,map_reg rA,map_reg rB) +| `Pcmpli (bF,l,rA,uI) -> `Pcmpli(bF,l,map_reg rA,uI) +| `Pcmpl (bF,l,rA,rB) -> `Pcmpl(bF,l,map_reg rA,map_reg rB) +| `Pisel (rT,rA,rB,bC) -> `Pisel(map_reg rT,map_reg rA,map_reg rB,bC) +| `Pandi (rA,rS,uI) -> `Pandi(map_reg rA,map_reg rS,uI) +| `Pandis (rA,rS,uI) -> `Pandis(map_reg rA,map_reg rS,uI) +| `Pori (rA,rS,uI) -> `Pori(map_reg rA,map_reg rS,uI) +| `Poris (rA,rS,uI) -> `Poris(map_reg rA,map_reg rS,uI) +| `Pxori (rA,rS,uI) -> `Pxori(map_reg rA,map_reg rS,uI) +| `Pxoris (rA,rS,uI) -> `Pxoris(map_reg rA,map_reg rS,uI) +| `Pand (DontSetCR0,rA,rS,rB) -> `Pand(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pand (SetCR0,rA,rS,rB) -> `Pand(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pxor (DontSetCR0,rA,rS,rB) -> `Pxor(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pxor (SetCR0,rA,rS,rB) -> `Pxor(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pnand (DontSetCR0,rA,rS,rB) -> `Pnand(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pnand (SetCR0,rA,rS,rB) -> `Pnand(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Por (DontSetCR0,rA,rS,rB) -> `Por(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Por (SetCR0,rA,rS,rB) -> `Por(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pnor (DontSetCR0,rA,rS,rB) -> `Pnor(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pnor (SetCR0,rA,rS,rB) -> `Pnor(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Peqv (DontSetCR0,rA,rS,rB) -> `Peqv(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Peqv (SetCR0,rA,rS,rB) -> `Peqv(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pandc (DontSetCR0,rA,rS,rB) -> `Pandc(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pandc (SetCR0,rA,rS,rB) -> `Pandc(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Porc (DontSetCR0,rA,rS,rB) -> `Porc(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Porc (SetCR0,rA,rS,rB) -> `Porc(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pextsb (DontSetCR0,rA,rS) -> `Pextsb(DontSetCR0,map_reg rA,map_reg rS) +| `Pextsb (SetCR0,rA,rS) -> `Pextsb(SetCR0,map_reg rA,map_reg rS) +| `Pextsh (DontSetCR0,rA,rS) -> `Pextsh(DontSetCR0,map_reg rA,map_reg rS) +| `Pextsh (SetCR0,rA,rS) -> `Pextsh(SetCR0,map_reg rA,map_reg rS) +| `Pcntlzw (DontSetCR0,rA,rS) -> `Pcntlzw(DontSetCR0,map_reg rA,map_reg rS) +| `Pcntlzw (SetCR0,rA,rS) -> `Pcntlzw(SetCR0,map_reg rA,map_reg rS) +| `Pcmpb (rA,rS,rB) -> `Pcmpb(map_reg rA,rS,map_reg rB) +| `Ppopcntb (rA,rS) -> `Ppopcntb(map_reg rA,map_reg rS) +| `Ppopcntw (rA,rS) -> `Ppopcntw(map_reg rA,map_reg rS) +| `Pprtyd (rA,rS) -> `Pprtyd(map_reg rA,map_reg rS) +| `Pprtyw (rA,rS) -> `Pprtyw(map_reg rA,map_reg rS) +| `Pextsw (DontSetCR0,rA,rS) -> `Pextsw(DontSetCR0,map_reg rA,map_reg rS) +| `Pextsw (SetCR0,rA,rS) -> `Pextsw(SetCR0,map_reg rA,map_reg rS) +| `Pcntlzd (DontSetCR0,rA,rS) -> `Pcntlzd(DontSetCR0,map_reg rA,map_reg rS) +| `Pcntlzd (SetCR0,rA,rS) -> `Pcntlzd(SetCR0,map_reg rA,map_reg rS) +| `Ppopcntd (rA,rS) -> `Ppopcntd(map_reg rA,map_reg rS) +| `Pbpermd (rA,rS,rB) -> `Pbpermd(map_reg rA,map_reg rS,map_reg rB) +| `Prlwinm (DontSetCR0,rA,rS,sH,mB,mE) -> `Prlwinm(DontSetCR0,map_reg rA,map_reg rS,sH,mB,mE) +| `Prlwinm (SetCR0,rA,rS,sH,mB,mE) -> `Prlwinm(SetCR0,map_reg rA,map_reg rS,sH,mB,mE) +| `Prlwnm (DontSetCR0,rA,rS,rB,mB,mE) -> `Prlwnm(DontSetCR0,map_reg rA,map_reg rS,map_reg rB,mB,mE) +| `Prlwnm (SetCR0,rA,rS,rB,mB,mE) -> `Prlwnm(SetCR0,map_reg rA,map_reg rS,map_reg rB,mB,mE) +| `Prlwimi (DontSetCR0,rA,rS,sH,mB,mE) -> `Prlwimi(DontSetCR0,map_reg rA,map_reg rS,sH,mB,mE) +| `Prlwimi (SetCR0,rA,rS,sH,mB,mE) -> `Prlwimi(SetCR0,map_reg rA,map_reg rS,sH,mB,mE) +| `Prldicl (DontSetCR0,rA,rS,sH,mB) -> `Prldicl(DontSetCR0,map_reg rA,map_reg rS,sH,mB) +| `Prldicl (SetCR0,rA,rS,sH,mB) -> `Prldicl(SetCR0,map_reg rA,map_reg rS,sH,mB) +| `Prldicr (DontSetCR0,rA,rS,sH,mE) -> `Prldicr(DontSetCR0,map_reg rA,map_reg rS,sH,mE) +| `Prldicr (SetCR0,rA,rS,sH,mE) -> `Prldicr(SetCR0,map_reg rA,map_reg rS,sH,mE) +| `Prldic (DontSetCR0,rA,rS,sH,mB) -> `Prldic(DontSetCR0,map_reg rA,map_reg rS,sH,mB) +| `Prldic (SetCR0,rA,rS,sH,mB) -> `Prldic(SetCR0,map_reg rA,map_reg rS,sH,mB) +| `Prldcl (DontSetCR0,rA,rS,rB,mB) -> `Prldcl(DontSetCR0,map_reg rA,map_reg rS,map_reg rB,mB) +| `Prldcl (SetCR0,rA,rS,rB,mB) -> `Prldcl(SetCR0,map_reg rA,map_reg rS,map_reg rB,mB) +| `Prldcr (DontSetCR0,rA,rS,rB,mE) -> `Prldcr(DontSetCR0,map_reg rA,map_reg rS,map_reg rB,mE) +| `Prldcr (SetCR0,rA,rS,rB,mE) -> `Prldcr(SetCR0,map_reg rA,map_reg rS,map_reg rB,mE) +| `Prldimi (DontSetCR0,rA,rS,sH,mB) -> `Prldimi(DontSetCR0,map_reg rA,map_reg rS,sH,mB) +| `Prldimi (SetCR0,rA,rS,sH,mB) -> `Prldimi(SetCR0,map_reg rA,map_reg rS,sH,mB) +| `Pslw (DontSetCR0,rA,rS,rB) -> `Pslw(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pslw (SetCR0,rA,rS,rB) -> `Pslw(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psrw (DontSetCR0,rA,rS,rB) -> `Psrw(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psrw (SetCR0,rA,rS,rB) -> `Psrw(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psrawi (DontSetCR0,rA,rS,sH) -> `Psrawi(DontSetCR0,map_reg rA,map_reg rS,sH) +| `Psrawi (SetCR0,rA,rS,sH) -> `Psrawi(SetCR0,map_reg rA,map_reg rS,sH) +| `Psraw (DontSetCR0,rA,rS,rB) -> `Psraw(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psraw (SetCR0,rA,rS,rB) -> `Psraw(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psld (DontSetCR0,rA,rS,rB) -> `Psld(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psld (SetCR0,rA,rS,rB) -> `Psld(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psrd (DontSetCR0,rA,rS,rB) -> `Psrd(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psrd (SetCR0,rA,rS,rB) -> `Psrd(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psradi (DontSetCR0,rA,rS,sH) -> `Psradi(DontSetCR0,map_reg rA,map_reg rS,sH) +| `Psradi (SetCR0,rA,rS,sH) -> `Psradi(SetCR0,map_reg rA,map_reg rS,sH) +| `Psrad (DontSetCR0,rA,rS,rB) -> `Psrad(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psrad (SetCR0,rA,rS,rB) -> `Psrad(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pcdtbcd (rA,rS) -> `Pcdtbcd(map_reg rA,map_reg rS) +| `Pcbcdtd (rA,rS) -> `Pcbcdtd(map_reg rA,map_reg rS) +| `Paddg6s (rT,rA,rB) -> `Paddg6s(map_reg rT,map_reg rA,map_reg rB) +| `Pmtspr (sPR,rS) -> `Pmtspr(sPR,map_reg rS) +| `Pmfspr (rT,sPR) -> `Pmfspr(map_reg rT,sPR) +| `Pmtcrf (fXM,rS) -> `Pmtcrf(fXM,map_reg rS) +| `Pmfcr (rT) -> `Pmfcr(map_reg rT) +| `Pmtocrf (fXM,rS) -> `Pmtocrf(fXM,map_reg rS) +| `Pmfocrf (rT,fXM) -> `Pmfocrf(map_reg rT,fXM) +| `Pmcrxr (bF) -> `Pmcrxr(bF) +| `Pdlmzb (DontSetCR0,rA,rS,rB) -> `Pdlmzb(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pdlmzb (SetCR0,rA,rS,rB) -> `Pdlmzb(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmacchw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchw (SetSOOV,SetCR0,rT,rA,rB) -> `Pmacchw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchws(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmacchws(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchws(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchws (SetSOOV,SetCR0,rT,rA,rB) -> `Pmacchws(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchwu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmacchwu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchwu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwu (SetSOOV,SetCR0,rT,rA,rB) -> `Pmacchwu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchwsu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmacchwsu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchwsu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwsu (SetSOOV,SetCR0,rT,rA,rB) -> `Pmacchwsu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmachhw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhw (SetSOOV,SetCR0,rT,rA,rB) -> `Pmachhw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhws(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmachhws(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhws(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhws (SetSOOV,SetCR0,rT,rA,rB) -> `Pmachhws(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhwu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmachhwu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhwu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwu (SetSOOV,SetCR0,rT,rA,rB) -> `Pmachhwu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhwsu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmachhwsu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhwsu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwsu (SetSOOV,SetCR0,rT,rA,rB) -> `Pmachhwsu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhws(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhws(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhws(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhws(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhwu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhwu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhwu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwu (SetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhwu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhwsu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhwsu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhwsu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwsu (SetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhwsu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulchw (DontSetCR0,rT,rA,rB) -> `Pmulchw(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulchw (SetCR0,rT,rA,rB) -> `Pmulchw(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulchwu (DontSetCR0,rT,rA,rB) -> `Pmulchwu(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulchwu (SetCR0,rT,rA,rB) -> `Pmulchwu(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhhw (DontSetCR0,rT,rA,rB) -> `Pmulhhw(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhhw (SetCR0,rT,rA,rB) -> `Pmulhhw(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhhwu (DontSetCR0,rT,rA,rB) -> `Pmulhhwu(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhhwu (SetCR0,rT,rA,rB) -> `Pmulhhwu(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullhw (DontSetCR0,rT,rA,rB) -> `Pmullhw(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullhw (SetCR0,rT,rA,rB) -> `Pmullhw(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullhwu (DontSetCR0,rT,rA,rB) -> `Pmullhwu(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullhwu (SetCR0,rT,rA,rB) -> `Pmullhwu(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmacchw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pnmacchw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmacchw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchw (SetSOOV,SetCR0,rT,rA,rB) -> `Pnmacchw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmacchws(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pnmacchws(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmacchws(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchws (SetSOOV,SetCR0,rT,rA,rB) -> `Pnmacchws(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmachhw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pnmachhw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmachhw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhw (SetSOOV,SetCR0,rT,rA,rB) -> `Pnmachhw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmachhws(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pnmachhws(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmachhws(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhws (SetSOOV,SetCR0,rT,rA,rB) -> `Pnmachhws(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmaclhw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pnmaclhw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmaclhw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> `Pnmaclhw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmaclhws(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pnmaclhws(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmaclhws(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> `Pnmaclhws(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Picbi (rA,rB) -> `Picbi(map_reg rA,map_reg rB) +| `Picbt (cT,rA,rB) -> `Picbt(cT,map_reg rA,map_reg rB) +| `Pdcba (rA,rB) -> `Pdcba(map_reg rA,map_reg rB) +| `Pdcbt (rA,rB,tH) -> `Pdcbt(map_reg rA,map_reg rB,tH) +| `Pdcbtst (rA,rB,tH) -> `Pdcbtst(map_reg rA,map_reg rB,tH) +| `Pdcbz (rA,rB) -> `Pdcbz(map_reg rA,map_reg rB) +| `Pdcbst (rA,rB) -> `Pdcbst(map_reg rA,map_reg rB) +| `Pdcbf (rA,rB,l) -> `Pdcbf(map_reg rA,map_reg rB,l) +| `Pisync -> `Pisync +| `Plbarx (rT,rA,rB,eH) -> `Plbarx(map_reg rT,map_reg rA,map_reg rB,eH) +| `Plharx (rT,rA,rB,eH) -> `Plharx(map_reg rT,map_reg rA,map_reg rB,eH) +| `Plwarx (rT,rA,rB,eH) -> `Plwarx(map_reg rT,map_reg rA,map_reg rB,eH) +| `Pstbcx (rS,rA,rB) -> `Pstbcx(map_reg rS,map_reg rA,map_reg rB) +| `Psthcx (rS,rA,rB) -> `Psthcx(map_reg rS,map_reg rA,map_reg rB) +| `Pstwcx (rS,rA,rB) -> `Pstwcx(map_reg rS,map_reg rA,map_reg rB) +| `Pldarx (rT,rA,rB,eH) -> `Pldarx(map_reg rT,map_reg rA,map_reg rB,eH) +| `Pstdcx (rS,rA,rB) -> `Pstdcx(map_reg rS,map_reg rA,map_reg rB) +| `Psync (l) -> `Psync(l) +| `Peieio -> `Peieio +| `Pwait (wC) -> `Pwait(wC) diff --git a/power/gen/parser.gen b/power/gen/parser.gen new file mode 100644 index 00000000..298cd50f --- /dev/null +++ b/power/gen/parser.gen @@ -0,0 +1,736 @@ + | B k + { `Pb (DontSetAA,DontSetLK,$2) } + | BA k + { `Pb (SetAA,DontSetLK,$2) } + | BL k + { `Pb (DontSetAA,SetLK,$2) } + | BLA k + { `Pb (SetAA,SetLK,$2) } + | BC k COMMA k COMMA k + { `Pbc (DontSetAA,DontSetLK,$2,$4,$6) } + | BCA k COMMA k COMMA k + { `Pbc (SetAA,DontSetLK,$2,$4,$6) } + | BCL k COMMA k COMMA k + { `Pbc (DontSetAA,SetLK,$2,$4,$6) } + | BCLA k COMMA k COMMA k + { `Pbc (SetAA,SetLK,$2,$4,$6) } + | BCLR k COMMA k COMMA k + { `Pbclr (DontSetLK,$2,$4,$6) } + | BCLRL k COMMA k COMMA k + { `Pbclr (SetLK,$2,$4,$6) } + | BCCTR k COMMA k COMMA k + { `Pbcctr (DontSetLK,$2,$4,$6) } + | BCCTRL k COMMA k COMMA k + { `Pbcctr (SetLK,$2,$4,$6) } + | CRAND k COMMA k COMMA k + { `Pcrand ($2,$4,$6) } + | CRNAND k COMMA k COMMA k + { `Pcrnand ($2,$4,$6) } + | CROR k COMMA k COMMA k + { `Pcror ($2,$4,$6) } + | CRXOR k COMMA k COMMA k + { `Pcrxor ($2,$4,$6) } + | CRNOR k COMMA k COMMA k + { `Pcrnor ($2,$4,$6) } + | CREQV k COMMA k COMMA k + { `Pcreqv ($2,$4,$6) } + | CRANDC k COMMA k COMMA k + { `Pcrandc ($2,$4,$6) } + | CRORC k COMMA k COMMA k + { `Pcrorc ($2,$4,$6) } + | MCRF crindex COMMA k + { `Pmcrf ($2,$4) } + | SC k + { `Psc ($2) } + | SCV k + { `Pscv ($2) } + | LBZ reg COMMA k LPAR reg RPAR + { `Plbz ($2,$4,$6) } + | LBZX reg COMMA reg COMMA reg + { `Plbzx ($2,$4,$6) } + | LBZU reg COMMA k LPAR reg RPAR + { `Plbzu ($2,$4,$6) } + | LBZUX reg COMMA reg COMMA reg + { `Plbzux ($2,$4,$6) } + | LHZ reg COMMA k LPAR reg RPAR + { `Plhz ($2,$4,$6) } + | LHZX reg COMMA reg COMMA reg + { `Plhzx ($2,$4,$6) } + | LHZU reg COMMA k LPAR reg RPAR + { `Plhzu ($2,$4,$6) } + | LHZUX reg COMMA reg COMMA reg + { `Plhzux ($2,$4,$6) } + | LHA reg COMMA k LPAR reg RPAR + { `Plha ($2,$4,$6) } + | LHAX reg COMMA reg COMMA reg + { `Plhax ($2,$4,$6) } + | LHAU reg COMMA k LPAR reg RPAR + { `Plhau ($2,$4,$6) } + | LHAUX reg COMMA reg COMMA reg + { `Plhaux ($2,$4,$6) } + | LWZ reg COMMA k LPAR reg RPAR + { `Plwz ($2,$4,$6) } + | LWZX reg COMMA reg COMMA reg + { `Plwzx ($2,$4,$6) } + | LWZU reg COMMA k LPAR reg RPAR + { `Plwzu ($2,$4,$6) } + | LWZUX reg COMMA reg COMMA reg + { `Plwzux ($2,$4,$6) } + | LWA reg COMMA ds LPAR reg RPAR + { `Plwa ($2,$4,$6) } + | LWAX reg COMMA reg COMMA reg + { `Plwax ($2,$4,$6) } + | LWAUX reg COMMA reg COMMA reg + { `Plwaux ($2,$4,$6) } + | LD reg COMMA ds LPAR reg RPAR + { `Pld ($2,$4,$6) } + | LDX reg COMMA reg COMMA reg + { `Pldx ($2,$4,$6) } + | LDU reg COMMA ds LPAR reg RPAR + { `Pldu ($2,$4,$6) } + | LDUX reg COMMA reg COMMA reg + { `Pldux ($2,$4,$6) } + | STB reg COMMA k LPAR reg RPAR + { `Pstb ($2,$4,$6) } + | STBX reg COMMA reg COMMA reg + { `Pstbx ($2,$4,$6) } + | STBU reg COMMA k LPAR reg RPAR + { `Pstbu ($2,$4,$6) } + | STBUX reg COMMA reg COMMA reg + { `Pstbux ($2,$4,$6) } + | STH reg COMMA k LPAR reg RPAR + { `Psth ($2,$4,$6) } + | STHX reg COMMA reg COMMA reg + { `Psthx ($2,$4,$6) } + | STHU reg COMMA k LPAR reg RPAR + { `Psthu ($2,$4,$6) } + | STHUX reg COMMA reg COMMA reg + { `Psthux ($2,$4,$6) } + | STW reg COMMA k LPAR reg RPAR + { `Pstw ($2,$4,$6) } + | STWX reg COMMA reg COMMA reg + { `Pstwx ($2,$4,$6) } + | STWU reg COMMA k LPAR reg RPAR + { `Pstwu ($2,$4,$6) } + | STWUX reg COMMA reg COMMA reg + { `Pstwux ($2,$4,$6) } + | STD reg COMMA ds LPAR reg RPAR + { `Pstd ($2,$4,$6) } + | STDX reg COMMA reg COMMA reg + { `Pstdx ($2,$4,$6) } + | STDU reg COMMA ds LPAR reg RPAR + { `Pstdu ($2,$4,$6) } + | STDUX reg COMMA reg COMMA reg + { `Pstdux ($2,$4,$6) } + | LQ k COMMA k LPAR reg RPAR COMMA k + { `Plq ($2,$4,$6,$9) } + | STQ k COMMA ds LPAR reg RPAR + { `Pstq ($2,$4,$6) } + | LHBRX reg COMMA reg COMMA reg + { `Plhbrx ($2,$4,$6) } + | STHBRX reg COMMA reg COMMA reg + { `Psthbrx ($2,$4,$6) } + | LWBRX reg COMMA reg COMMA reg + { `Plwbrx ($2,$4,$6) } + | STWBRX reg COMMA reg COMMA reg + { `Pstwbrx ($2,$4,$6) } + | LDBRX reg COMMA reg COMMA reg + { `Pldbrx ($2,$4,$6) } + | STDBRX reg COMMA reg COMMA reg + { `Pstdbrx ($2,$4,$6) } + | LMW reg COMMA k LPAR reg RPAR + { `Plmw ($2,$4,$6) } + | STMW reg COMMA k LPAR reg RPAR + { `Pstmw ($2,$4,$6) } + | LSWI k COMMA reg COMMA k + { `Plswi ($2,$4,$6) } + | LSWX reg COMMA reg COMMA reg + { `Plswx ($2,$4,$6) } + | STSWI k COMMA reg COMMA k + { `Pstswi ($2,$4,$6) } + | STSWX k COMMA reg COMMA reg + { `Pstswx ($2,$4,$6) } + | ADDI reg COMMA reg COMMA k + { `Paddi ($2,$4,$6) } + | ADDIS reg COMMA reg COMMA k + { `Paddis ($2,$4,$6) } + | ADD reg COMMA reg COMMA reg + { `Padd (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | ADDDOT reg COMMA reg COMMA reg + { `Padd (DontSetSOOV,SetCR0,$2,$4,$6) } + | ADDO reg COMMA reg COMMA reg + { `Padd (SetSOOV,DontSetCR0,$2,$4,$6) } + | ADDODOT reg COMMA reg COMMA reg + { `Padd (SetSOOV,SetCR0,$2,$4,$6) } + | SUBF reg COMMA reg COMMA reg + { `Psubf (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | SUBFDOT reg COMMA reg COMMA reg + { `Psubf (DontSetSOOV,SetCR0,$2,$4,$6) } + | SUBFO reg COMMA reg COMMA reg + { `Psubf (SetSOOV,DontSetCR0,$2,$4,$6) } + | SUBFODOT reg COMMA reg COMMA reg + { `Psubf (SetSOOV,SetCR0,$2,$4,$6) } + | ADDIC reg COMMA reg COMMA k + { `Paddic ($2,$4,$6) } + | ADDICDOT reg COMMA reg COMMA k + { `Paddicdot ($2,$4,$6) } + | SUBFIC reg COMMA reg COMMA k + { `Psubfic ($2,$4,$6) } + | ADDC reg COMMA reg COMMA reg + { `Paddc (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | ADDCDOT reg COMMA reg COMMA reg + { `Paddc (DontSetSOOV,SetCR0,$2,$4,$6) } + | ADDCO reg COMMA reg COMMA reg + { `Paddc (SetSOOV,DontSetCR0,$2,$4,$6) } + | ADDCODOT reg COMMA reg COMMA reg + { `Paddc (SetSOOV,SetCR0,$2,$4,$6) } + | SUBFC reg COMMA reg COMMA reg + { `Psubfc (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | SUBFCDOT reg COMMA reg COMMA reg + { `Psubfc (DontSetSOOV,SetCR0,$2,$4,$6) } + | SUBFCO reg COMMA reg COMMA reg + { `Psubfc (SetSOOV,DontSetCR0,$2,$4,$6) } + | SUBFCODOT reg COMMA reg COMMA reg + { `Psubfc (SetSOOV,SetCR0,$2,$4,$6) } + | ADDE reg COMMA reg COMMA reg + { `Padde (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | ADDEDOT reg COMMA reg COMMA reg + { `Padde (DontSetSOOV,SetCR0,$2,$4,$6) } + | ADDEO reg COMMA reg COMMA reg + { `Padde (SetSOOV,DontSetCR0,$2,$4,$6) } + | ADDEODOT reg COMMA reg COMMA reg + { `Padde (SetSOOV,SetCR0,$2,$4,$6) } + | SUBFE reg COMMA reg COMMA reg + { `Psubfe (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | SUBFEDOT reg COMMA reg COMMA reg + { `Psubfe (DontSetSOOV,SetCR0,$2,$4,$6) } + | SUBFEO reg COMMA reg COMMA reg + { `Psubfe (SetSOOV,DontSetCR0,$2,$4,$6) } + | SUBFEODOT reg COMMA reg COMMA reg + { `Psubfe (SetSOOV,SetCR0,$2,$4,$6) } + | ADDME reg COMMA reg + { `Paddme (DontSetSOOV,DontSetCR0,$2,$4) } + | ADDMEDOT reg COMMA reg + { `Paddme (DontSetSOOV,SetCR0,$2,$4) } + | ADDMEO reg COMMA reg + { `Paddme (SetSOOV,DontSetCR0,$2,$4) } + | ADDMEODOT reg COMMA reg + { `Paddme (SetSOOV,SetCR0,$2,$4) } + | SUBFME reg COMMA reg + { `Psubfme (DontSetSOOV,DontSetCR0,$2,$4) } + | SUBFMEDOT reg COMMA reg + { `Psubfme (DontSetSOOV,SetCR0,$2,$4) } + | SUBFMEO reg COMMA reg + { `Psubfme (SetSOOV,DontSetCR0,$2,$4) } + | SUBFMEODOT reg COMMA reg + { `Psubfme (SetSOOV,SetCR0,$2,$4) } + | ADDZE reg COMMA reg + { `Paddze (DontSetSOOV,DontSetCR0,$2,$4) } + | ADDZEDOT reg COMMA reg + { `Paddze (DontSetSOOV,SetCR0,$2,$4) } + | ADDZEO reg COMMA reg + { `Paddze (SetSOOV,DontSetCR0,$2,$4) } + | ADDZEODOT reg COMMA reg + { `Paddze (SetSOOV,SetCR0,$2,$4) } + | SUBFZE reg COMMA reg + { `Psubfze (DontSetSOOV,DontSetCR0,$2,$4) } + | SUBFZEDOT reg COMMA reg + { `Psubfze (DontSetSOOV,SetCR0,$2,$4) } + | SUBFZEO reg COMMA reg + { `Psubfze (SetSOOV,DontSetCR0,$2,$4) } + | SUBFZEODOT reg COMMA reg + { `Psubfze (SetSOOV,SetCR0,$2,$4) } + | NEG reg COMMA reg + { `Pneg (DontSetSOOV,DontSetCR0,$2,$4) } + | NEGDOT reg COMMA reg + { `Pneg (DontSetSOOV,SetCR0,$2,$4) } + | NEGO reg COMMA reg + { `Pneg (SetSOOV,DontSetCR0,$2,$4) } + | NEGODOT reg COMMA reg + { `Pneg (SetSOOV,SetCR0,$2,$4) } + | MULLI reg COMMA reg COMMA k + { `Pmulli ($2,$4,$6) } + | MULLW reg COMMA reg COMMA reg + { `Pmullw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MULLWDOT reg COMMA reg COMMA reg + { `Pmullw (DontSetSOOV,SetCR0,$2,$4,$6) } + | MULLWO reg COMMA reg COMMA reg + { `Pmullw (SetSOOV,DontSetCR0,$2,$4,$6) } + | MULLWODOT reg COMMA reg COMMA reg + { `Pmullw (SetSOOV,SetCR0,$2,$4,$6) } + | MULHW reg COMMA reg COMMA reg + { `Pmulhw (DontSetCR0,$2,$4,$6) } + | MULHWDOT reg COMMA reg COMMA reg + { `Pmulhw (SetCR0,$2,$4,$6) } + | MULHWU reg COMMA reg COMMA reg + { `Pmulhwu (DontSetCR0,$2,$4,$6) } + | MULHWUDOT reg COMMA reg COMMA reg + { `Pmulhwu (SetCR0,$2,$4,$6) } + | DIVW reg COMMA reg COMMA reg + { `Pdivw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWDOT reg COMMA reg COMMA reg + { `Pdivw (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVWO reg COMMA reg COMMA reg + { `Pdivw (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWODOT reg COMMA reg COMMA reg + { `Pdivw (SetSOOV,SetCR0,$2,$4,$6) } + | DIVWU reg COMMA reg COMMA reg + { `Pdivwu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWUDOT reg COMMA reg COMMA reg + { `Pdivwu (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVWUO reg COMMA reg COMMA reg + { `Pdivwu (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWUODOT reg COMMA reg COMMA reg + { `Pdivwu (SetSOOV,SetCR0,$2,$4,$6) } + | DIVWE reg COMMA reg COMMA reg + { `Pdivwe (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWEDOT reg COMMA reg COMMA reg + { `Pdivwe (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVWEO reg COMMA reg COMMA reg + { `Pdivwe (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWEODOT reg COMMA reg COMMA reg + { `Pdivwe (SetSOOV,SetCR0,$2,$4,$6) } + | DIVWEU reg COMMA reg COMMA reg + { `Pdivweu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWEUDOT reg COMMA reg COMMA reg + { `Pdivweu (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVWEUO reg COMMA reg COMMA reg + { `Pdivweu (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWEUODOT reg COMMA reg COMMA reg + { `Pdivweu (SetSOOV,SetCR0,$2,$4,$6) } + | MULLD reg COMMA reg COMMA reg + { `Pmulld (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MULLDDOT reg COMMA reg COMMA reg + { `Pmulld (DontSetSOOV,SetCR0,$2,$4,$6) } + | MULLDO reg COMMA reg COMMA reg + { `Pmulld (SetSOOV,DontSetCR0,$2,$4,$6) } + | MULLDODOT reg COMMA reg COMMA reg + { `Pmulld (SetSOOV,SetCR0,$2,$4,$6) } + | MULHD reg COMMA reg COMMA reg + { `Pmulhd (DontSetCR0,$2,$4,$6) } + | MULHDDOT reg COMMA reg COMMA reg + { `Pmulhd (SetCR0,$2,$4,$6) } + | MULHDU reg COMMA reg COMMA reg + { `Pmulhdu (DontSetCR0,$2,$4,$6) } + | MULHDUDOT reg COMMA reg COMMA reg + { `Pmulhdu (SetCR0,$2,$4,$6) } + | DIVD reg COMMA reg COMMA reg + { `Pdivd (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDDOT reg COMMA reg COMMA reg + { `Pdivd (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVDO reg COMMA reg COMMA reg + { `Pdivd (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDODOT reg COMMA reg COMMA reg + { `Pdivd (SetSOOV,SetCR0,$2,$4,$6) } + | DIVDU reg COMMA reg COMMA reg + { `Pdivdu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDUDOT reg COMMA reg COMMA reg + { `Pdivdu (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVDUO reg COMMA reg COMMA reg + { `Pdivdu (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDUODOT reg COMMA reg COMMA reg + { `Pdivdu (SetSOOV,SetCR0,$2,$4,$6) } + | DIVDE reg COMMA reg COMMA reg + { `Pdivde (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDEDOT reg COMMA reg COMMA reg + { `Pdivde (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVDEO reg COMMA reg COMMA reg + { `Pdivde (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDEODOT reg COMMA reg COMMA reg + { `Pdivde (SetSOOV,SetCR0,$2,$4,$6) } + | DIVDEU reg COMMA reg COMMA reg + { `Pdivdeu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDEUDOT reg COMMA reg COMMA reg + { `Pdivdeu (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVDEUO reg COMMA reg COMMA reg + { `Pdivdeu (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDEUODOT reg COMMA reg COMMA reg + { `Pdivdeu (SetSOOV,SetCR0,$2,$4,$6) } + | CMPI crindex COMMA k COMMA reg COMMA k + { `Pcmpi ($2,$4,$6,$8) } + | CMP crindex COMMA k COMMA reg COMMA reg + { `Pcmp ($2,$4,$6,$8) } + | CMPLI crindex COMMA k COMMA reg COMMA k + { `Pcmpli ($2,$4,$6,$8) } + | CMPL crindex COMMA k COMMA reg COMMA reg + { `Pcmpl ($2,$4,$6,$8) } + | ISEL reg COMMA reg COMMA reg COMMA k + { `Pisel ($2,$4,$6,$8) } + | ANDIDOT reg COMMA reg COMMA k + { `Pandi ($2,$4,$6) } + | ANDISDOT reg COMMA reg COMMA k + { `Pandis ($2,$4,$6) } + | ORI reg COMMA reg COMMA k + { `Pori ($2,$4,$6) } + | ORIS reg COMMA reg COMMA k + { `Poris ($2,$4,$6) } + | XORI reg COMMA reg COMMA k + { `Pxori ($2,$4,$6) } + | XORIS reg COMMA reg COMMA k + { `Pxoris ($2,$4,$6) } + | AND reg COMMA reg COMMA reg + { `Pand (DontSetCR0,$2,$4,$6) } + | ANDDOT reg COMMA reg COMMA reg + { `Pand (SetCR0,$2,$4,$6) } + | XOR reg COMMA reg COMMA reg + { `Pxor (DontSetCR0,$2,$4,$6) } + | XORDOT reg COMMA reg COMMA reg + { `Pxor (SetCR0,$2,$4,$6) } + | NAND reg COMMA reg COMMA reg + { `Pnand (DontSetCR0,$2,$4,$6) } + | NANDDOT reg COMMA reg COMMA reg + { `Pnand (SetCR0,$2,$4,$6) } + | OR reg COMMA reg COMMA reg + { `Por (DontSetCR0,$2,$4,$6) } + | ORDOT reg COMMA reg COMMA reg + { `Por (SetCR0,$2,$4,$6) } + | NOR reg COMMA reg COMMA reg + { `Pnor (DontSetCR0,$2,$4,$6) } + | NORDOT reg COMMA reg COMMA reg + { `Pnor (SetCR0,$2,$4,$6) } + | EQV reg COMMA reg COMMA reg + { `Peqv (DontSetCR0,$2,$4,$6) } + | EQVDOT reg COMMA reg COMMA reg + { `Peqv (SetCR0,$2,$4,$6) } + | ANDC reg COMMA reg COMMA reg + { `Pandc (DontSetCR0,$2,$4,$6) } + | ANDCDOT reg COMMA reg COMMA reg + { `Pandc (SetCR0,$2,$4,$6) } + | ORC reg COMMA reg COMMA reg + { `Porc (DontSetCR0,$2,$4,$6) } + | ORCDOT reg COMMA reg COMMA reg + { `Porc (SetCR0,$2,$4,$6) } + | EXTSB reg COMMA reg + { `Pextsb (DontSetCR0,$2,$4) } + | EXTSBDOT reg COMMA reg + { `Pextsb (SetCR0,$2,$4) } + | EXTSH reg COMMA reg + { `Pextsh (DontSetCR0,$2,$4) } + | EXTSHDOT reg COMMA reg + { `Pextsh (SetCR0,$2,$4) } + | CNTLZW reg COMMA reg + { `Pcntlzw (DontSetCR0,$2,$4) } + | CNTLZWDOT reg COMMA reg + { `Pcntlzw (SetCR0,$2,$4) } + | CMPB reg COMMA k COMMA reg + { `Pcmpb ($2,$4,$6) } + | POPCNTB reg COMMA reg + { `Ppopcntb ($2,$4) } + | POPCNTW reg COMMA reg + { `Ppopcntw ($2,$4) } + | PRTYD reg COMMA reg + { `Pprtyd ($2,$4) } + | PRTYW reg COMMA reg + { `Pprtyw ($2,$4) } + | EXTSW reg COMMA reg + { `Pextsw (DontSetCR0,$2,$4) } + | EXTSWDOT reg COMMA reg + { `Pextsw (SetCR0,$2,$4) } + | CNTLZD reg COMMA reg + { `Pcntlzd (DontSetCR0,$2,$4) } + | CNTLZDDOT reg COMMA reg + { `Pcntlzd (SetCR0,$2,$4) } + | POPCNTD reg COMMA reg + { `Ppopcntd ($2,$4) } + | BPERMD reg COMMA reg COMMA reg + { `Pbpermd ($2,$4,$6) } + | RLWINM reg COMMA reg COMMA k COMMA k COMMA k + { `Prlwinm (DontSetCR0,$2,$4,$6,$8,$10) } + | RLWINMDOT reg COMMA reg COMMA k COMMA k COMMA k + { `Prlwinm (SetCR0,$2,$4,$6,$8,$10) } + | RLWNM reg COMMA reg COMMA reg COMMA k COMMA k + { `Prlwnm (DontSetCR0,$2,$4,$6,$8,$10) } + | RLWNMDOT reg COMMA reg COMMA reg COMMA k COMMA k + { `Prlwnm (SetCR0,$2,$4,$6,$8,$10) } + | RLWIMI reg COMMA reg COMMA k COMMA k COMMA k + { `Prlwimi (DontSetCR0,$2,$4,$6,$8,$10) } + | RLWIMIDOT reg COMMA reg COMMA k COMMA k COMMA k + { `Prlwimi (SetCR0,$2,$4,$6,$8,$10) } + | RLDICL reg COMMA reg COMMA k COMMA k + { `Prldicl (DontSetCR0,$2,$4,$6,$8) } + | RLDICLDOT reg COMMA reg COMMA k COMMA k + { `Prldicl (SetCR0,$2,$4,$6,$8) } + | RLDICR reg COMMA reg COMMA k COMMA k + { `Prldicr (DontSetCR0,$2,$4,$6,$8) } + | RLDICRDOT reg COMMA reg COMMA k COMMA k + { `Prldicr (SetCR0,$2,$4,$6,$8) } + | RLDIC reg COMMA reg COMMA k COMMA k + { `Prldic (DontSetCR0,$2,$4,$6,$8) } + | RLDICDOT reg COMMA reg COMMA k COMMA k + { `Prldic (SetCR0,$2,$4,$6,$8) } + | RLDCL reg COMMA reg COMMA reg COMMA k + { `Prldcl (DontSetCR0,$2,$4,$6,$8) } + | RLDCLDOT reg COMMA reg COMMA reg COMMA k + { `Prldcl (SetCR0,$2,$4,$6,$8) } + | RLDCR reg COMMA reg COMMA reg COMMA k + { `Prldcr (DontSetCR0,$2,$4,$6,$8) } + | RLDCRDOT reg COMMA reg COMMA reg COMMA k + { `Prldcr (SetCR0,$2,$4,$6,$8) } + | RLDIMI reg COMMA reg COMMA k COMMA k + { `Prldimi (DontSetCR0,$2,$4,$6,$8) } + | RLDIMIDOT reg COMMA reg COMMA k COMMA k + { `Prldimi (SetCR0,$2,$4,$6,$8) } + | SLW reg COMMA reg COMMA reg + { `Pslw (DontSetCR0,$2,$4,$6) } + | SLWDOT reg COMMA reg COMMA reg + { `Pslw (SetCR0,$2,$4,$6) } + | SRW reg COMMA reg COMMA reg + { `Psrw (DontSetCR0,$2,$4,$6) } + | SRWDOT reg COMMA reg COMMA reg + { `Psrw (SetCR0,$2,$4,$6) } + | SRAWI reg COMMA reg COMMA k + { `Psrawi (DontSetCR0,$2,$4,$6) } + | SRAWIDOT reg COMMA reg COMMA k + { `Psrawi (SetCR0,$2,$4,$6) } + | SRAW reg COMMA reg COMMA reg + { `Psraw (DontSetCR0,$2,$4,$6) } + | SRAWDOT reg COMMA reg COMMA reg + { `Psraw (SetCR0,$2,$4,$6) } + | SLD reg COMMA reg COMMA reg + { `Psld (DontSetCR0,$2,$4,$6) } + | SLDDOT reg COMMA reg COMMA reg + { `Psld (SetCR0,$2,$4,$6) } + | SRD reg COMMA reg COMMA reg + { `Psrd (DontSetCR0,$2,$4,$6) } + | SRDDOT reg COMMA reg COMMA reg + { `Psrd (SetCR0,$2,$4,$6) } + | SRADI reg COMMA reg COMMA k + { `Psradi (DontSetCR0,$2,$4,$6) } + | SRADIDOT reg COMMA reg COMMA k + { `Psradi (SetCR0,$2,$4,$6) } + | SRAD reg COMMA reg COMMA reg + { `Psrad (DontSetCR0,$2,$4,$6) } + | SRADDOT reg COMMA reg COMMA reg + { `Psrad (SetCR0,$2,$4,$6) } + | CDTBCD reg COMMA reg + { `Pcdtbcd ($2,$4) } + | CBCDTD reg COMMA reg + { `Pcbcdtd ($2,$4) } + | ADDG6S reg COMMA reg COMMA reg + { `Paddg6s ($2,$4,$6) } + | MTSPR k COMMA reg + { `Pmtspr ($2,$4) } + | MFSPR reg COMMA k + { `Pmfspr ($2,$4) } + | MTCRF crmask COMMA reg + { `Pmtcrf ($2,$4) } + | MFCR reg + { `Pmfcr ($2) } + | MTOCRF crmask COMMA reg + { `Pmtocrf ($2,$4) } + | MFOCRF reg COMMA crmask + { `Pmfocrf ($2,$4) } + | MCRXR crindex + { `Pmcrxr ($2) } + | DLMZB reg COMMA reg COMMA reg + { `Pdlmzb (DontSetCR0,$2,$4,$6) } + | DLMZBDOT reg COMMA reg COMMA reg + { `Pdlmzb (SetCR0,$2,$4,$6) } + | MACCHW reg COMMA reg COMMA reg + { `Pmacchw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWDOT reg COMMA reg COMMA reg + { `Pmacchw (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACCHWO reg COMMA reg COMMA reg + { `Pmacchw (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWODOT reg COMMA reg COMMA reg + { `Pmacchw (SetSOOV,SetCR0,$2,$4,$6) } + | MACCHWS reg COMMA reg COMMA reg + { `Pmacchws (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWSDOT reg COMMA reg COMMA reg + { `Pmacchws (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACCHWSO reg COMMA reg COMMA reg + { `Pmacchws (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWSODOT reg COMMA reg COMMA reg + { `Pmacchws (SetSOOV,SetCR0,$2,$4,$6) } + | MACCHWU reg COMMA reg COMMA reg + { `Pmacchwu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWUDOT reg COMMA reg COMMA reg + { `Pmacchwu (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACCHWUO reg COMMA reg COMMA reg + { `Pmacchwu (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWUODOT reg COMMA reg COMMA reg + { `Pmacchwu (SetSOOV,SetCR0,$2,$4,$6) } + | MACCHWSU reg COMMA reg COMMA reg + { `Pmacchwsu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWSUDOT reg COMMA reg COMMA reg + { `Pmacchwsu (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACCHWSUO reg COMMA reg COMMA reg + { `Pmacchwsu (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWSUODOT reg COMMA reg COMMA reg + { `Pmacchwsu (SetSOOV,SetCR0,$2,$4,$6) } + | MACHHW reg COMMA reg COMMA reg + { `Pmachhw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWDOT reg COMMA reg COMMA reg + { `Pmachhw (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACHHWO reg COMMA reg COMMA reg + { `Pmachhw (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWODOT reg COMMA reg COMMA reg + { `Pmachhw (SetSOOV,SetCR0,$2,$4,$6) } + | MACHHWS reg COMMA reg COMMA reg + { `Pmachhws (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWSDOT reg COMMA reg COMMA reg + { `Pmachhws (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACHHWSO reg COMMA reg COMMA reg + { `Pmachhws (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWSODOT reg COMMA reg COMMA reg + { `Pmachhws (SetSOOV,SetCR0,$2,$4,$6) } + | MACHHWU reg COMMA reg COMMA reg + { `Pmachhwu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWUDOT reg COMMA reg COMMA reg + { `Pmachhwu (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACHHWUO reg COMMA reg COMMA reg + { `Pmachhwu (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWUODOT reg COMMA reg COMMA reg + { `Pmachhwu (SetSOOV,SetCR0,$2,$4,$6) } + | MACHHWSU reg COMMA reg COMMA reg + { `Pmachhwsu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWSUDOT reg COMMA reg COMMA reg + { `Pmachhwsu (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACHHWSUO reg COMMA reg COMMA reg + { `Pmachhwsu (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWSUODOT reg COMMA reg COMMA reg + { `Pmachhwsu (SetSOOV,SetCR0,$2,$4,$6) } + | MACLHW reg COMMA reg COMMA reg + { `Pmaclhw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWDOT reg COMMA reg COMMA reg + { `Pmaclhw (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACLHWO reg COMMA reg COMMA reg + { `Pmaclhw (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWODOT reg COMMA reg COMMA reg + { `Pmaclhw (SetSOOV,SetCR0,$2,$4,$6) } + | MACLHWS reg COMMA reg COMMA reg + { `Pmaclhws (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWSDOT reg COMMA reg COMMA reg + { `Pmaclhws (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACLHWSO reg COMMA reg COMMA reg + { `Pmaclhws (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWSODOT reg COMMA reg COMMA reg + { `Pmaclhws (SetSOOV,SetCR0,$2,$4,$6) } + | MACLHWU reg COMMA reg COMMA reg + { `Pmaclhwu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWUDOT reg COMMA reg COMMA reg + { `Pmaclhwu (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACLHWUO reg COMMA reg COMMA reg + { `Pmaclhwu (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWUODOT reg COMMA reg COMMA reg + { `Pmaclhwu (SetSOOV,SetCR0,$2,$4,$6) } + | MACLHWSU reg COMMA reg COMMA reg + { `Pmaclhwsu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWSUDOT reg COMMA reg COMMA reg + { `Pmaclhwsu (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACLHWSUO reg COMMA reg COMMA reg + { `Pmaclhwsu (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWSUODOT reg COMMA reg COMMA reg + { `Pmaclhwsu (SetSOOV,SetCR0,$2,$4,$6) } + | MULCHW reg COMMA reg COMMA reg + { `Pmulchw (DontSetCR0,$2,$4,$6) } + | MULCHWDOT reg COMMA reg COMMA reg + { `Pmulchw (SetCR0,$2,$4,$6) } + | MULCHWU reg COMMA reg COMMA reg + { `Pmulchwu (DontSetCR0,$2,$4,$6) } + | MULCHWUDOT reg COMMA reg COMMA reg + { `Pmulchwu (SetCR0,$2,$4,$6) } + | MULHHW reg COMMA reg COMMA reg + { `Pmulhhw (DontSetCR0,$2,$4,$6) } + | MULHHWDOT reg COMMA reg COMMA reg + { `Pmulhhw (SetCR0,$2,$4,$6) } + | MULHHWU reg COMMA reg COMMA reg + { `Pmulhhwu (DontSetCR0,$2,$4,$6) } + | MULHHWUDOT reg COMMA reg COMMA reg + { `Pmulhhwu (SetCR0,$2,$4,$6) } + | MULLHW reg COMMA reg COMMA reg + { `Pmullhw (DontSetCR0,$2,$4,$6) } + | MULLHWDOT reg COMMA reg COMMA reg + { `Pmullhw (SetCR0,$2,$4,$6) } + | MULLHWU reg COMMA reg COMMA reg + { `Pmullhwu (DontSetCR0,$2,$4,$6) } + | MULLHWUDOT reg COMMA reg COMMA reg + { `Pmullhwu (SetCR0,$2,$4,$6) } + | NMACCHW reg COMMA reg COMMA reg + { `Pnmacchw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | NMACCHWDOT reg COMMA reg COMMA reg + { `Pnmacchw (DontSetSOOV,SetCR0,$2,$4,$6) } + | NMACCHWO reg COMMA reg COMMA reg + { `Pnmacchw (SetSOOV,DontSetCR0,$2,$4,$6) } + | NMACCHWODOT reg COMMA reg COMMA reg + { `Pnmacchw (SetSOOV,SetCR0,$2,$4,$6) } + | NMACCHWS reg COMMA reg COMMA reg + { `Pnmacchws (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | NMACCHWSDOT reg COMMA reg COMMA reg + { `Pnmacchws (DontSetSOOV,SetCR0,$2,$4,$6) } + | NMACCHWSO reg COMMA reg COMMA reg + { `Pnmacchws (SetSOOV,DontSetCR0,$2,$4,$6) } + | NMACCHWSODOT reg COMMA reg COMMA reg + { `Pnmacchws (SetSOOV,SetCR0,$2,$4,$6) } + | NMACHHW reg COMMA reg COMMA reg + { `Pnmachhw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | NMACHHWDOT reg COMMA reg COMMA reg + { `Pnmachhw (DontSetSOOV,SetCR0,$2,$4,$6) } + | NMACHHWO reg COMMA reg COMMA reg + { `Pnmachhw (SetSOOV,DontSetCR0,$2,$4,$6) } + | NMACHHWODOT reg COMMA reg COMMA reg + { `Pnmachhw (SetSOOV,SetCR0,$2,$4,$6) } + | NMACHHWS reg COMMA reg COMMA reg + { `Pnmachhws (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | NMACHHWSDOT reg COMMA reg COMMA reg + { `Pnmachhws (DontSetSOOV,SetCR0,$2,$4,$6) } + | NMACHHWSO reg COMMA reg COMMA reg + { `Pnmachhws (SetSOOV,DontSetCR0,$2,$4,$6) } + | NMACHHWSODOT reg COMMA reg COMMA reg + { `Pnmachhws (SetSOOV,SetCR0,$2,$4,$6) } + | NMACLHW reg COMMA reg COMMA reg + { `Pnmaclhw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | NMACLHWDOT reg COMMA reg COMMA reg + { `Pnmaclhw (DontSetSOOV,SetCR0,$2,$4,$6) } + | NMACLHWO reg COMMA reg COMMA reg + { `Pnmaclhw (SetSOOV,DontSetCR0,$2,$4,$6) } + | NMACLHWODOT reg COMMA reg COMMA reg + { `Pnmaclhw (SetSOOV,SetCR0,$2,$4,$6) } + | NMACLHWS reg COMMA reg COMMA reg + { `Pnmaclhws (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | NMACLHWSDOT reg COMMA reg COMMA reg + { `Pnmaclhws (DontSetSOOV,SetCR0,$2,$4,$6) } + | NMACLHWSO reg COMMA reg COMMA reg + { `Pnmaclhws (SetSOOV,DontSetCR0,$2,$4,$6) } + | NMACLHWSODOT reg COMMA reg COMMA reg + { `Pnmaclhws (SetSOOV,SetCR0,$2,$4,$6) } + | ICBI reg COMMA reg + { `Picbi ($2,$4) } + | ICBT k COMMA reg COMMA reg + { `Picbt ($2,$4,$6) } + | DCBA reg COMMA reg + { `Pdcba ($2,$4) } + | DCBT reg COMMA reg COMMA k + { `Pdcbt ($2,$4,$6) } + | DCBTST reg COMMA reg COMMA k + { `Pdcbtst ($2,$4,$6) } + | DCBZ reg COMMA reg + { `Pdcbz ($2,$4) } + | DCBST reg COMMA reg + { `Pdcbst ($2,$4) } + | DCBF reg COMMA reg COMMA k + { `Pdcbf ($2,$4,$6) } + | ISYNC + { `Pisync } + | LBARX reg COMMA reg COMMA reg COMMA k + { `Plbarx ($2,$4,$6,$8) } + | LHARX reg COMMA reg COMMA reg COMMA k + { `Plharx ($2,$4,$6,$8) } + | LWARX reg COMMA reg COMMA reg COMMA k + { `Plwarx ($2,$4,$6,$8) } + | STBCXDOT reg COMMA reg COMMA reg + { `Pstbcx ($2,$4,$6) } + | STHCXDOT reg COMMA reg COMMA reg + { `Psthcx ($2,$4,$6) } + | STWCXDOT reg COMMA reg COMMA reg + { `Pstwcx ($2,$4,$6) } + | LDARX reg COMMA reg COMMA reg COMMA k + { `Pldarx ($2,$4,$6,$8) } + | STDCXDOT reg COMMA reg COMMA reg + { `Pstdcx ($2,$4,$6) } + | SYNC k + { `Psync ($2) } + | EIEIO + { `Peieio } + | WAIT k + { `Pwait ($2) } diff --git a/power/gen/pretty.gen b/power/gen/pretty.gen new file mode 100644 index 00000000..4a7eff69 --- /dev/null +++ b/power/gen/pretty.gen @@ -0,0 +1,368 @@ +| `Pb (DontSetAA,DontSetLK,target_addr) -> sprintf "b %d" target_addr +| `Pb (SetAA,DontSetLK,target_addr) -> sprintf "ba %d" target_addr +| `Pb (DontSetAA,SetLK,target_addr) -> sprintf "bl %d" target_addr +| `Pb (SetAA,SetLK,target_addr) -> sprintf "bla %d" target_addr +| `Pbc (DontSetAA,DontSetLK,bO,bI,target_addr) -> sprintf "bc %d,%d,%d" bO bI target_addr +| `Pbc (SetAA,DontSetLK,bO,bI,target_addr) -> sprintf "bca %d,%d,%d" bO bI target_addr +| `Pbc (DontSetAA,SetLK,bO,bI,target_addr) -> sprintf "bcl %d,%d,%d" bO bI target_addr +| `Pbc (SetAA,SetLK,bO,bI,target_addr) -> sprintf "bcla %d,%d,%d" bO bI target_addr +| `Pbclr (DontSetLK,bO,bI,bH) -> sprintf "bclr %d,%d,%d" bO bI bH +| `Pbclr (SetLK,bO,bI,bH) -> sprintf "bclrl %d,%d,%d" bO bI bH +| `Pbcctr (DontSetLK,bO,bI,bH) -> sprintf "bcctr %d,%d,%d" bO bI bH +| `Pbcctr (SetLK,bO,bI,bH) -> sprintf "bcctrl %d,%d,%d" bO bI bH +| `Pcrand (bT,bA,bB) -> sprintf "crand %d,%d,%d" bT bA bB +| `Pcrnand (bT,bA,bB) -> sprintf "crnand %d,%d,%d" bT bA bB +| `Pcror (bT,bA,bB) -> sprintf "cror %d,%d,%d" bT bA bB +| `Pcrxor (bT,bA,bB) -> sprintf "crxor %d,%d,%d" bT bA bB +| `Pcrnor (bT,bA,bB) -> sprintf "crnor %d,%d,%d" bT bA bB +| `Pcreqv (bT,bA,bB) -> sprintf "creqv %d,%d,%d" bT bA bB +| `Pcrandc (bT,bA,bB) -> sprintf "crandc %d,%d,%d" bT bA bB +| `Pcrorc (bT,bA,bB) -> sprintf "crorc %d,%d,%d" bT bA bB +| `Pmcrf (bF,bFA) -> sprintf "mcrf %s,%d" (pp_crf bF) bFA +| `Psc (lEV) -> sprintf "sc %d" lEV +| `Pscv (lEV) -> sprintf "scv %d" lEV +| `Plbz (rT,d,rA) -> sprintf "lbz %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plbzx (rT,rA,rB) -> sprintf "lbzx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plbzu (rT,d,rA) -> sprintf "lbzu %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plbzux (rT,rA,rB) -> sprintf "lbzux %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plhz (rT,d,rA) -> sprintf "lhz %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plhzx (rT,rA,rB) -> sprintf "lhzx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plhzu (rT,d,rA) -> sprintf "lhzu %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plhzux (rT,rA,rB) -> sprintf "lhzux %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plha (rT,d,rA) -> sprintf "lha %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plhax (rT,rA,rB) -> sprintf "lhax %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plhau (rT,d,rA) -> sprintf "lhau %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plhaux (rT,rA,rB) -> sprintf "lhaux %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plwz (rT,d,rA) -> sprintf "lwz %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plwzx (rT,rA,rB) -> sprintf "lwzx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plwzu (rT,d,rA) -> sprintf "lwzu %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plwzux (rT,rA,rB) -> sprintf "lwzux %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plwa (rT,dS,rA) -> sprintf "lwa %s,%s(%s)" (pp_reg rT) (pp_ds dS) (pp_reg rA) +| `Plwax (rT,rA,rB) -> sprintf "lwax %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plwaux (rT,rA,rB) -> sprintf "lwaux %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pld (rT,dS,rA) -> sprintf "ld %s,%s(%s)" (pp_reg rT) (pp_ds dS) (pp_reg rA) +| `Pldx (rT,rA,rB) -> sprintf "ldx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pldu (rT,dS,rA) -> sprintf "ldu %s,%s(%s)" (pp_reg rT) (pp_ds dS) (pp_reg rA) +| `Pldux (rT,rA,rB) -> sprintf "ldux %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pstb (rS,d,rA) -> sprintf "stb %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Pstbx (rS,rA,rB) -> sprintf "stbx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pstbu (rS,d,rA) -> sprintf "stbu %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Pstbux (rS,rA,rB) -> sprintf "stbux %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Psth (rS,d,rA) -> sprintf "sth %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Psthx (rS,rA,rB) -> sprintf "sthx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Psthu (rS,d,rA) -> sprintf "sthu %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Psthux (rS,rA,rB) -> sprintf "sthux %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pstw (rS,d,rA) -> sprintf "stw %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Pstwx (rS,rA,rB) -> sprintf "stwx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pstwu (rS,d,rA) -> sprintf "stwu %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Pstwux (rS,rA,rB) -> sprintf "stwux %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pstd (rS,dS,rA) -> sprintf "std %s,%s(%s)" (pp_reg rS) (pp_ds dS) (pp_reg rA) +| `Pstdx (rS,rA,rB) -> sprintf "stdx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pstdu (rS,dS,rA) -> sprintf "stdu %s,%s(%s)" (pp_reg rS) (pp_ds dS) (pp_reg rA) +| `Pstdux (rS,rA,rB) -> sprintf "stdux %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Plq (rTp,dQ,rA,pT) -> sprintf "lq %d,%d(%s),%d" rTp dQ (pp_reg rA) pT +| `Pstq (rSp,dS,rA) -> sprintf "stq %d,%s(%s)" rSp (pp_ds dS) (pp_reg rA) +| `Plhbrx (rT,rA,rB) -> sprintf "lhbrx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psthbrx (rS,rA,rB) -> sprintf "sthbrx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Plwbrx (rT,rA,rB) -> sprintf "lwbrx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pstwbrx (rS,rA,rB) -> sprintf "stwbrx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pldbrx (rT,rA,rB) -> sprintf "ldbrx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pstdbrx (rS,rA,rB) -> sprintf "stdbrx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Plmw (rT,d,rA) -> sprintf "lmw %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Pstmw (rS,d,rA) -> sprintf "stmw %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Plswi (rT,rA,nB) -> sprintf "lswi %d,%s,%d" rT (pp_reg rA) nB +| `Plswx (rT,rA,rB) -> sprintf "lswx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pstswi (rS,rA,nB) -> sprintf "stswi %d,%s,%d" rS (pp_reg rA) nB +| `Pstswx (rS,rA,rB) -> sprintf "stswx %d,%s,%s" rS (pp_reg rA) (pp_reg rB) +| `Paddi (rT,rA,sI) -> sprintf "addi %s,%s,%d" (pp_reg rT) (pp_reg rA) sI +| `Paddis (rT,rA,sI) -> sprintf "addis %s,%s,%d" (pp_reg rT) (pp_reg rA) sI +| `Padd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "add %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padd (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "add. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padd (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "addo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padd (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "addo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubf (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "subf %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubf (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "subf. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubf (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "subfo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubf (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "subfo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Paddic (rT,rA,sI) -> sprintf "addic %s,%s,%d" (pp_reg rT) (pp_reg rA) sI +| `Paddicdot (rT,rA,sI) -> sprintf "addic. %s,%s,%d" (pp_reg rT) (pp_reg rA) sI +| `Psubfic (rT,rA,sI) -> sprintf "subfic %s,%s,%d" (pp_reg rT) (pp_reg rA) sI +| `Paddc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "addc %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Paddc (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "addc. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Paddc (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "addco %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Paddc (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "addco. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "subfc %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfc (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "subfc. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfc (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "subfco %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfc (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "subfco. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "adde %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padde (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "adde. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padde (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "addeo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padde (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "addeo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "subfe %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfe (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "subfe. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfe (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "subfeo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfe (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "subfeo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Paddme (DontSetSOOV,DontSetCR0,rT,rA) -> sprintf "addme %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddme (DontSetSOOV,SetCR0,rT,rA) -> sprintf "addme. %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddme (SetSOOV,DontSetCR0,rT,rA) -> sprintf "addmeo %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddme (SetSOOV,SetCR0,rT,rA) -> sprintf "addmeo. %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfme (DontSetSOOV,DontSetCR0,rT,rA) -> sprintf "subfme %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfme (DontSetSOOV,SetCR0,rT,rA) -> sprintf "subfme. %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfme (SetSOOV,DontSetCR0,rT,rA) -> sprintf "subfmeo %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfme (SetSOOV,SetCR0,rT,rA) -> sprintf "subfmeo. %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddze (DontSetSOOV,DontSetCR0,rT,rA) -> sprintf "addze %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddze (DontSetSOOV,SetCR0,rT,rA) -> sprintf "addze. %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddze (SetSOOV,DontSetCR0,rT,rA) -> sprintf "addzeo %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddze (SetSOOV,SetCR0,rT,rA) -> sprintf "addzeo. %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfze (DontSetSOOV,DontSetCR0,rT,rA) -> sprintf "subfze %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfze (DontSetSOOV,SetCR0,rT,rA) -> sprintf "subfze. %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfze (SetSOOV,DontSetCR0,rT,rA) -> sprintf "subfzeo %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfze (SetSOOV,SetCR0,rT,rA) -> sprintf "subfzeo. %s,%s" (pp_reg rT) (pp_reg rA) +| `Pneg (DontSetSOOV,DontSetCR0,rT,rA) -> sprintf "neg %s,%s" (pp_reg rT) (pp_reg rA) +| `Pneg (DontSetSOOV,SetCR0,rT,rA) -> sprintf "neg. %s,%s" (pp_reg rT) (pp_reg rA) +| `Pneg (SetSOOV,DontSetCR0,rT,rA) -> sprintf "nego %s,%s" (pp_reg rT) (pp_reg rA) +| `Pneg (SetSOOV,SetCR0,rT,rA) -> sprintf "nego. %s,%s" (pp_reg rT) (pp_reg rA) +| `Pmulli (rT,rA,sI) -> sprintf "mulli %s,%s,%d" (pp_reg rT) (pp_reg rA) sI +| `Pmullw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "mullw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "mullw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "mullwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "mullwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhw (DontSetCR0,rT,rA,rB) -> sprintf "mulhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhw (SetCR0,rT,rA,rB) -> sprintf "mulhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhwu (DontSetCR0,rT,rA,rB) -> sprintf "mulhwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhwu (SetCR0,rT,rA,rB) -> sprintf "mulhwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divwuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divwuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divwe %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwe (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divwe. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwe (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divweo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwe (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divweo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivweu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divweu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivweu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divweu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivweu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divweuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivweu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divweuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulld (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "mulld %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulld (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "mulld. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulld (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "mulldo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulld (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "mulldo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhd (DontSetCR0,rT,rA,rB) -> sprintf "mulhd %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhd (SetCR0,rT,rA,rB) -> sprintf "mulhd. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhdu (DontSetCR0,rT,rA,rB) -> sprintf "mulhdu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhdu (SetCR0,rT,rA,rB) -> sprintf "mulhdu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divd %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivd (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divd. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivd (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divdo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivd (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divdo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divdu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divdu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divduo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divduo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divde %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivde (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divde. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivde (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divdeo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivde (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divdeo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdeu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divdeu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdeu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divdeu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdeu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divdeuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdeu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divdeuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pcmpi (bF,l,rA,sI) -> sprintf "cmpi %s,%d,%s,%d" (pp_crf bF) l (pp_reg rA) sI +| `Pcmp (bF,l,rA,rB) -> sprintf "cmp %s,%d,%s,%s" (pp_crf bF) l (pp_reg rA) (pp_reg rB) +| `Pcmpli (bF,l,rA,uI) -> sprintf "cmpli %s,%d,%s,%d" (pp_crf bF) l (pp_reg rA) uI +| `Pcmpl (bF,l,rA,rB) -> sprintf "cmpl %s,%d,%s,%s" (pp_crf bF) l (pp_reg rA) (pp_reg rB) +| `Pisel (rT,rA,rB,bC) -> sprintf "isel %s,%s,%s,%d" (pp_reg rT) (pp_reg rA) (pp_reg rB) bC +| `Pandi (rA,rS,uI) -> sprintf "andi. %s,%s,%d" (pp_reg rA) (pp_reg rS) uI +| `Pandis (rA,rS,uI) -> sprintf "andis. %s,%s,%d" (pp_reg rA) (pp_reg rS) uI +| `Pori (rA,rS,uI) -> sprintf "ori %s,%s,%d" (pp_reg rA) (pp_reg rS) uI +| `Poris (rA,rS,uI) -> sprintf "oris %s,%s,%d" (pp_reg rA) (pp_reg rS) uI +| `Pxori (rA,rS,uI) -> sprintf "xori %s,%s,%d" (pp_reg rA) (pp_reg rS) uI +| `Pxoris (rA,rS,uI) -> sprintf "xoris %s,%s,%d" (pp_reg rA) (pp_reg rS) uI +| `Pand (DontSetCR0,rA,rS,rB) -> sprintf "and %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pand (SetCR0,rA,rS,rB) -> sprintf "and. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pxor (DontSetCR0,rA,rS,rB) -> sprintf "xor %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pxor (SetCR0,rA,rS,rB) -> sprintf "xor. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pnand (DontSetCR0,rA,rS,rB) -> sprintf "nand %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pnand (SetCR0,rA,rS,rB) -> sprintf "nand. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Por (DontSetCR0,rA,rS,rB) -> sprintf "or %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Por (SetCR0,rA,rS,rB) -> sprintf "or. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pnor (DontSetCR0,rA,rS,rB) -> sprintf "nor %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pnor (SetCR0,rA,rS,rB) -> sprintf "nor. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Peqv (DontSetCR0,rA,rS,rB) -> sprintf "eqv %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Peqv (SetCR0,rA,rS,rB) -> sprintf "eqv. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pandc (DontSetCR0,rA,rS,rB) -> sprintf "andc %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pandc (SetCR0,rA,rS,rB) -> sprintf "andc. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Porc (DontSetCR0,rA,rS,rB) -> sprintf "orc %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Porc (SetCR0,rA,rS,rB) -> sprintf "orc. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pextsb (DontSetCR0,rA,rS) -> sprintf "extsb %s,%s" (pp_reg rA) (pp_reg rS) +| `Pextsb (SetCR0,rA,rS) -> sprintf "extsb. %s,%s" (pp_reg rA) (pp_reg rS) +| `Pextsh (DontSetCR0,rA,rS) -> sprintf "extsh %s,%s" (pp_reg rA) (pp_reg rS) +| `Pextsh (SetCR0,rA,rS) -> sprintf "extsh. %s,%s" (pp_reg rA) (pp_reg rS) +| `Pcntlzw (DontSetCR0,rA,rS) -> sprintf "cntlzw %s,%s" (pp_reg rA) (pp_reg rS) +| `Pcntlzw (SetCR0,rA,rS) -> sprintf "cntlzw. %s,%s" (pp_reg rA) (pp_reg rS) +| `Pcmpb (rA,rS,rB) -> sprintf "cmpb %s,%d,%s" (pp_reg rA) rS (pp_reg rB) +| `Ppopcntb (rA,rS) -> sprintf "popcntb %s,%s" (pp_reg rA) (pp_reg rS) +| `Ppopcntw (rA,rS) -> sprintf "popcntw %s,%s" (pp_reg rA) (pp_reg rS) +| `Pprtyd (rA,rS) -> sprintf "prtyd %s,%s" (pp_reg rA) (pp_reg rS) +| `Pprtyw (rA,rS) -> sprintf "prtyw %s,%s" (pp_reg rA) (pp_reg rS) +| `Pextsw (DontSetCR0,rA,rS) -> sprintf "extsw %s,%s" (pp_reg rA) (pp_reg rS) +| `Pextsw (SetCR0,rA,rS) -> sprintf "extsw. %s,%s" (pp_reg rA) (pp_reg rS) +| `Pcntlzd (DontSetCR0,rA,rS) -> sprintf "cntlzd %s,%s" (pp_reg rA) (pp_reg rS) +| `Pcntlzd (SetCR0,rA,rS) -> sprintf "cntlzd. %s,%s" (pp_reg rA) (pp_reg rS) +| `Ppopcntd (rA,rS) -> sprintf "popcntd %s,%s" (pp_reg rA) (pp_reg rS) +| `Pbpermd (rA,rS,rB) -> sprintf "bpermd %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Prlwinm (DontSetCR0,rA,rS,sH,mB,mE) -> sprintf "rlwinm %s,%s,%d,%d,%d" (pp_reg rA) (pp_reg rS) sH mB mE +| `Prlwinm (SetCR0,rA,rS,sH,mB,mE) -> sprintf "rlwinm. %s,%s,%d,%d,%d" (pp_reg rA) (pp_reg rS) sH mB mE +| `Prlwnm (DontSetCR0,rA,rS,rB,mB,mE) -> sprintf "rlwnm %s,%s,%s,%d,%d" (pp_reg rA) (pp_reg rS) (pp_reg rB) mB mE +| `Prlwnm (SetCR0,rA,rS,rB,mB,mE) -> sprintf "rlwnm. %s,%s,%s,%d,%d" (pp_reg rA) (pp_reg rS) (pp_reg rB) mB mE +| `Prlwimi (DontSetCR0,rA,rS,sH,mB,mE) -> sprintf "rlwimi %s,%s,%d,%d,%d" (pp_reg rA) (pp_reg rS) sH mB mE +| `Prlwimi (SetCR0,rA,rS,sH,mB,mE) -> sprintf "rlwimi. %s,%s,%d,%d,%d" (pp_reg rA) (pp_reg rS) sH mB mE +| `Prldicl (DontSetCR0,rA,rS,sH,mB) -> sprintf "rldicl %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mB +| `Prldicl (SetCR0,rA,rS,sH,mB) -> sprintf "rldicl. %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mB +| `Prldicr (DontSetCR0,rA,rS,sH,mE) -> sprintf "rldicr %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mE +| `Prldicr (SetCR0,rA,rS,sH,mE) -> sprintf "rldicr. %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mE +| `Prldic (DontSetCR0,rA,rS,sH,mB) -> sprintf "rldic %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mB +| `Prldic (SetCR0,rA,rS,sH,mB) -> sprintf "rldic. %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mB +| `Prldcl (DontSetCR0,rA,rS,rB,mB) -> sprintf "rldcl %s,%s,%s,%d" (pp_reg rA) (pp_reg rS) (pp_reg rB) mB +| `Prldcl (SetCR0,rA,rS,rB,mB) -> sprintf "rldcl. %s,%s,%s,%d" (pp_reg rA) (pp_reg rS) (pp_reg rB) mB +| `Prldcr (DontSetCR0,rA,rS,rB,mE) -> sprintf "rldcr %s,%s,%s,%d" (pp_reg rA) (pp_reg rS) (pp_reg rB) mE +| `Prldcr (SetCR0,rA,rS,rB,mE) -> sprintf "rldcr. %s,%s,%s,%d" (pp_reg rA) (pp_reg rS) (pp_reg rB) mE +| `Prldimi (DontSetCR0,rA,rS,sH,mB) -> sprintf "rldimi %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mB +| `Prldimi (SetCR0,rA,rS,sH,mB) -> sprintf "rldimi. %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mB +| `Pslw (DontSetCR0,rA,rS,rB) -> sprintf "slw %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pslw (SetCR0,rA,rS,rB) -> sprintf "slw. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psrw (DontSetCR0,rA,rS,rB) -> sprintf "srw %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psrw (SetCR0,rA,rS,rB) -> sprintf "srw. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psrawi (DontSetCR0,rA,rS,sH) -> sprintf "srawi %s,%s,%d" (pp_reg rA) (pp_reg rS) sH +| `Psrawi (SetCR0,rA,rS,sH) -> sprintf "srawi. %s,%s,%d" (pp_reg rA) (pp_reg rS) sH +| `Psraw (DontSetCR0,rA,rS,rB) -> sprintf "sraw %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psraw (SetCR0,rA,rS,rB) -> sprintf "sraw. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psld (DontSetCR0,rA,rS,rB) -> sprintf "sld %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psld (SetCR0,rA,rS,rB) -> sprintf "sld. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psrd (DontSetCR0,rA,rS,rB) -> sprintf "srd %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psrd (SetCR0,rA,rS,rB) -> sprintf "srd. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psradi (DontSetCR0,rA,rS,sH) -> sprintf "sradi %s,%s,%d" (pp_reg rA) (pp_reg rS) sH +| `Psradi (SetCR0,rA,rS,sH) -> sprintf "sradi. %s,%s,%d" (pp_reg rA) (pp_reg rS) sH +| `Psrad (DontSetCR0,rA,rS,rB) -> sprintf "srad %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psrad (SetCR0,rA,rS,rB) -> sprintf "srad. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pcdtbcd (rA,rS) -> sprintf "cdtbcd %s,%s" (pp_reg rA) (pp_reg rS) +| `Pcbcdtd (rA,rS) -> sprintf "cbcdtd %s,%s" (pp_reg rA) (pp_reg rS) +| `Paddg6s (rT,rA,rB) -> sprintf "addg6s %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmtspr (sPR,rS) -> sprintf "mtspr %d,%s" sPR (pp_reg rS) +| `Pmfspr (rT,sPR) -> sprintf "mfspr %s,%d" (pp_reg rT) sPR +| `Pmtcrf (fXM,rS) -> sprintf "mtcrf %d,%s" fXM (pp_reg rS) +| `Pmfcr (rT) -> sprintf "mfcr %s" (pp_reg rT) +| `Pmtocrf (fXM,rS) -> sprintf "mtocrf %d,%s" fXM (pp_reg rS) +| `Pmfocrf (rT,fXM) -> sprintf "mfocrf %s,%d" (pp_reg rT) fXM +| `Pmcrxr (bF) -> sprintf "mcrxr %s" (pp_crf bF) +| `Pdlmzb (DontSetCR0,rA,rS,rB) -> sprintf "dlmzb %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pdlmzb (SetCR0,rA,rS,rB) -> sprintf "dlmzb. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchws %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchws. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchwso %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchws (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchwso. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchwuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchwuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchwsu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchwsu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchwsuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwsu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchwsuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhws %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhws. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhwso %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhws (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhwso. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhwuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhwuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhwsu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhwsu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhwsuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwsu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhwsuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhws %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhws. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhwso %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhwso. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhwuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhwuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhwsu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhwsu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhwsuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwsu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhwsuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulchw (DontSetCR0,rT,rA,rB) -> sprintf "mulchw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulchw (SetCR0,rT,rA,rB) -> sprintf "mulchw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulchwu (DontSetCR0,rT,rA,rB) -> sprintf "mulchwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulchwu (SetCR0,rT,rA,rB) -> sprintf "mulchwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhhw (DontSetCR0,rT,rA,rB) -> sprintf "mulhhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhhw (SetCR0,rT,rA,rB) -> sprintf "mulhhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhhwu (DontSetCR0,rT,rA,rB) -> sprintf "mulhhwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhhwu (SetCR0,rT,rA,rB) -> sprintf "mulhhwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullhw (DontSetCR0,rT,rA,rB) -> sprintf "mullhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullhw (SetCR0,rT,rA,rB) -> sprintf "mullhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullhwu (DontSetCR0,rT,rA,rB) -> sprintf "mullhwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullhwu (SetCR0,rT,rA,rB) -> sprintf "mullhwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmacchw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmacchw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmacchwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmacchwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmacchws %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmacchws. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmacchwso %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchws (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmacchwso. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmachhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmachhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmachhwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmachhwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmachhws %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmachhws. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmachhwso %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhws (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmachhwso. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmaclhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmaclhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmaclhwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmaclhwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmaclhws %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmaclhws. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmaclhwso %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmaclhwso. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Picbi (rA,rB) -> sprintf "icbi %s,%s" (pp_reg rA) (pp_reg rB) +| `Picbt (cT,rA,rB) -> sprintf "icbt %d,%s,%s" cT (pp_reg rA) (pp_reg rB) +| `Pdcba (rA,rB) -> sprintf "dcba %s,%s" (pp_reg rA) (pp_reg rB) +| `Pdcbt (rA,rB,tH) -> sprintf "dcbt %s,%s,%d" (pp_reg rA) (pp_reg rB) tH +| `Pdcbtst (rA,rB,tH) -> sprintf "dcbtst %s,%s,%d" (pp_reg rA) (pp_reg rB) tH +| `Pdcbz (rA,rB) -> sprintf "dcbz %s,%s" (pp_reg rA) (pp_reg rB) +| `Pdcbst (rA,rB) -> sprintf "dcbst %s,%s" (pp_reg rA) (pp_reg rB) +| `Pdcbf (rA,rB,l) -> sprintf "dcbf %s,%s,%d" (pp_reg rA) (pp_reg rB) l +| `Pisync -> sprintf "isync " +| `Plbarx (rT,rA,rB,eH) -> sprintf "lbarx %s,%s,%s,%d" (pp_reg rT) (pp_reg rA) (pp_reg rB) eH +| `Plharx (rT,rA,rB,eH) -> sprintf "lharx %s,%s,%s,%d" (pp_reg rT) (pp_reg rA) (pp_reg rB) eH +| `Plwarx (rT,rA,rB,eH) -> sprintf "lwarx %s,%s,%s,%d" (pp_reg rT) (pp_reg rA) (pp_reg rB) eH +| `Pstbcx (rS,rA,rB) -> sprintf "stbcx. %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Psthcx (rS,rA,rB) -> sprintf "sthcx. %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pstwcx (rS,rA,rB) -> sprintf "stwcx. %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pldarx (rT,rA,rB,eH) -> sprintf "ldarx %s,%s,%s,%d" (pp_reg rT) (pp_reg rA) (pp_reg rB) eH +| `Pstdcx (rS,rA,rB) -> sprintf "stdcx. %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Psync (l) -> sprintf "sync %d" l +| `Peieio -> sprintf "eieio " +| `Pwait (wC) -> sprintf "wait %d" wC diff --git a/power/gen/sail_trans_out.gen b/power/gen/sail_trans_out.gen new file mode 100644 index 00000000..09d3cdbf --- /dev/null +++ b/power/gen/sail_trans_out.gen @@ -0,0 +1,1112 @@ + | ("B", [li; aa; lk], _) -> + `Pb( + (trans_out_aa aa), + (trans_out_lk lk), + (trans_out_int (trans_out_li_setaa_setlk_k3 li aa lk))) + | ("Bc", [bo; bi; bd; aa; lk], _) -> + `Pbc( + (trans_out_aa aa), + (trans_out_lk lk), + (trans_out_int bo), + (trans_out_int bi), + (trans_out_int (trans_out_bd_setaa_setlk_k_k_k5 bo bi bd aa lk))) + | ("Bclr", [bo; bi; bh; lk], _) -> + `Pbclr( + (trans_out_lk lk), + (trans_out_int bo), + (trans_out_int bi), + (trans_out_int bh)) + | ("Bcctr", [bo; bi; bh; lk], _) -> + `Pbcctr( + (trans_out_lk lk), + (trans_out_int bo), + (trans_out_int bi), + (trans_out_int bh)) + | ("Crand", [bt; ba; bb], _) -> + `Pcrand( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Crnand", [bt; ba; bb], _) -> + `Pcrnand( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Cror", [bt; ba; bb], _) -> + `Pcror( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Crxor", [bt; ba; bb], _) -> + `Pcrxor( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Crnor", [bt; ba; bb], _) -> + `Pcrnor( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Creqv", [bt; ba; bb], _) -> + `Pcreqv( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Crandc", [bt; ba; bb], _) -> + `Pcrandc( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Crorc", [bt; ba; bb], _) -> + `Pcrorc( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Mcrf", [bf; bfa], _) -> + `Pmcrf( + (trans_out_int bf), + (trans_out_int bfa)) + | ("Sc", [lev], _) -> + `Psc( + (trans_out_int lev)) + | ("Scv", [lev], _) -> + `Pscv( + (trans_out_int lev)) + | ("Lbz", [rt; ra; d], _) -> + `Plbz( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lbzx", [rt; ra; rb], _) -> + `Plbzx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lbzu", [rt; ra; d], _) -> + `Plbzu( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lbzux", [rt; ra; rb], _) -> + `Plbzux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lhz", [rt; ra; d], _) -> + `Plhz( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lhzx", [rt; ra; rb], _) -> + `Plhzx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lhzu", [rt; ra; d], _) -> + `Plhzu( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lhzux", [rt; ra; rb], _) -> + `Plhzux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lha", [rt; ra; d], _) -> + `Plha( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lhax", [rt; ra; rb], _) -> + `Plhax( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lhau", [rt; ra; d], _) -> + `Plhau( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lhaux", [rt; ra; rb], _) -> + `Plhaux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lwz", [rt; ra; d], _) -> + `Plwz( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lwzx", [rt; ra; rb], _) -> + `Plwzx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lwzu", [rt; ra; d], _) -> + `Plwzu( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lwzux", [rt; ra; rb], _) -> + `Plwzux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lwa", [rt; ra; ds], _) -> + `Plwa( + (trans_out_reg rt), + (trans_out_int ds), + (trans_out_reg ra)) + | ("Lwax", [rt; ra; rb], _) -> + `Plwax( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lwaux", [rt; ra; rb], _) -> + `Plwaux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Ld", [rt; ra; ds], _) -> + `Pld( + (trans_out_reg rt), + (trans_out_int ds), + (trans_out_reg ra)) + | ("Ldx", [rt; ra; rb], _) -> + `Pldx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Ldu", [rt; ra; ds], _) -> + `Pldu( + (trans_out_reg rt), + (trans_out_int ds), + (trans_out_reg ra)) + | ("Ldux", [rt; ra; rb], _) -> + `Pldux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stb", [rs; ra; d], _) -> + `Pstb( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Stbx", [rs; ra; rb], _) -> + `Pstbx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stbu", [rs; ra; d], _) -> + `Pstbu( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Stbux", [rs; ra; rb], _) -> + `Pstbux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Sth", [rs; ra; d], _) -> + `Psth( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Sthx", [rs; ra; rb], _) -> + `Psthx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Sthu", [rs; ra; d], _) -> + `Psthu( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Sthux", [rs; ra; rb], _) -> + `Psthux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stw", [rs; ra; d], _) -> + `Pstw( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Stwx", [rs; ra; rb], _) -> + `Pstwx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stwu", [rs; ra; d], _) -> + `Pstwu( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Stwux", [rs; ra; rb], _) -> + `Pstwux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Std", [rs; ra; ds], _) -> + `Pstd( + (trans_out_reg rs), + (trans_out_int ds), + (trans_out_reg ra)) + | ("Stdx", [rs; ra; rb], _) -> + `Pstdx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stdu", [rs; ra; ds], _) -> + `Pstdu( + (trans_out_reg rs), + (trans_out_int ds), + (trans_out_reg ra)) + | ("Stdux", [rs; ra; rb], _) -> + `Pstdux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lq", [rtp; ra; dq; pt], _) -> + `Plq( + (trans_out_int rtp), + (trans_out_int dq), + (trans_out_reg ra), + (trans_out_int pt)) + | ("Stq", [rsp; ra; ds], _) -> + `Pstq( + (trans_out_int rsp), + (trans_out_int ds), + (trans_out_reg ra)) + | ("Lhbrx", [rt; ra; rb], _) -> + `Plhbrx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Sthbrx", [rs; ra; rb], _) -> + `Psthbrx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lwbrx", [rt; ra; rb], _) -> + `Plwbrx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stwbrx", [rs; ra; rb], _) -> + `Pstwbrx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Ldbrx", [rt; ra; rb], _) -> + `Pldbrx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stdbrx", [rs; ra; rb], _) -> + `Pstdbrx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lmw", [rt; ra; d], _) -> + `Plmw( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Stmw", [rs; ra; d], _) -> + `Pstmw( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lswi", [rt; ra; nb], _) -> + `Plswi( + (trans_out_int rt), + (trans_out_reg ra), + (trans_out_int nb)) + | ("Lswx", [rt; ra; rb], _) -> + `Plswx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stswi", [rs; ra; nb], _) -> + `Pstswi( + (trans_out_int rs), + (trans_out_reg ra), + (trans_out_int nb)) + | ("Stswx", [rs; ra; rb], _) -> + `Pstswx( + (trans_out_int rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Addi", [rt; ra; si], _) -> + `Paddi( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | ("Addis", [rt; ra; si], _) -> + `Paddis( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | ("Add", [rt; ra; rb; oe; rc], _) -> + `Padd( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Subf", [rt; ra; rb; oe; rc], _) -> + `Psubf( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Addic", [rt; ra; si], _) -> + `Paddic( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | ("AddicDot", [rt; ra; si], _) -> + `Paddicdot( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | ("Subfic", [rt; ra; si], _) -> + `Psubfic( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | ("Addc", [rt; ra; rb; oe; rc], _) -> + `Paddc( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Subfc", [rt; ra; rb; oe; rc], _) -> + `Psubfc( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Adde", [rt; ra; rb; oe; rc], _) -> + `Padde( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Subfe", [rt; ra; rb; oe; rc], _) -> + `Psubfe( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Addme", [rt; ra; oe; rc], _) -> + `Paddme( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | ("Subfme", [rt; ra; oe; rc], _) -> + `Psubfme( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | ("Addze", [rt; ra; oe; rc], _) -> + `Paddze( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | ("Subfze", [rt; ra; oe; rc], _) -> + `Psubfze( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | ("Neg", [rt; ra; oe; rc], _) -> + `Pneg( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | ("Mulli", [rt; ra; si], _) -> + `Pmulli( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | ("Mullw", [rt; ra; rb; oe; rc], _) -> + `Pmullw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulhw", [rt; ra; rb; rc], _) -> + `Pmulhw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulhwu", [rt; ra; rb; rc], _) -> + `Pmulhwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divw", [rt; ra; rb; oe; rc], _) -> + `Pdivw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divwu", [rt; ra; rb; oe; rc], _) -> + `Pdivwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divwe", [rt; ra; rb; oe; rc], _) -> + `Pdivwe( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divweu", [rt; ra; rb; oe; rc], _) -> + `Pdivweu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulld", [rt; ra; rb; oe; rc], _) -> + `Pmulld( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulhd", [rt; ra; rb; rc], _) -> + `Pmulhd( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulhdu", [rt; ra; rb; rc], _) -> + `Pmulhdu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divd", [rt; ra; rb; oe; rc], _) -> + `Pdivd( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divdu", [rt; ra; rb; oe; rc], _) -> + `Pdivdu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divde", [rt; ra; rb; oe; rc], _) -> + `Pdivde( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divdeu", [rt; ra; rb; oe; rc], _) -> + `Pdivdeu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Cmpi", [bf; l; ra; si], _) -> + `Pcmpi( + (trans_out_int bf), + (trans_out_int l), + (trans_out_reg ra), + (trans_out_int si)) + | ("Cmp", [bf; l; ra; rb], _) -> + `Pcmp( + (trans_out_int bf), + (trans_out_int l), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Cmpli", [bf; l; ra; ui], _) -> + `Pcmpli( + (trans_out_int bf), + (trans_out_int l), + (trans_out_reg ra), + (trans_out_int ui)) + | ("Cmpl", [bf; l; ra; rb], _) -> + `Pcmpl( + (trans_out_int bf), + (trans_out_int l), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Isel", [rt; ra; rb; bc], _) -> + `Pisel( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int bc)) + | ("Andi", [rs; ra; ui], _) -> + `Pandi( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | ("Andis", [rs; ra; ui], _) -> + `Pandis( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | ("Ori", [rs; ra; ui], _) -> + `Pori( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | ("Oris", [rs; ra; ui], _) -> + `Poris( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | ("Xori", [rs; ra; ui], _) -> + `Pxori( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | ("Xoris", [rs; ra; ui], _) -> + `Pxoris( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | ("And", [rs; ra; rb; rc], _) -> + `Pand( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Xor", [rs; ra; rb; rc], _) -> + `Pxor( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Nand", [rs; ra; rb; rc], _) -> + `Pnand( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Or", [rs; ra; rb; rc], _) -> + `Por( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Nor", [rs; ra; rb; rc], _) -> + `Pnor( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Eqv", [rs; ra; rb; rc], _) -> + `Peqv( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Andc", [rs; ra; rb; rc], _) -> + `Pandc( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Orc", [rs; ra; rb; rc], _) -> + `Porc( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Extsb", [rs; ra; rc], _) -> + `Pextsb( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Extsh", [rs; ra; rc], _) -> + `Pextsh( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Cntlzw", [rs; ra; rc], _) -> + `Pcntlzw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Cmpb", [rs; ra; rb], _) -> + `Pcmpb( + (trans_out_reg ra), + (trans_out_int rs), + (trans_out_reg rb)) + | ("Popcntb", [rs; ra], _) -> + `Ppopcntb( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Popcntw", [rs; ra], _) -> + `Ppopcntw( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Prtyd", [rs; ra], _) -> + `Pprtyd( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Prtyw", [rs; ra], _) -> + `Pprtyw( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Extsw", [rs; ra; rc], _) -> + `Pextsw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Cntlzd", [rs; ra; rc], _) -> + `Pcntlzd( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Popcntd", [rs; ra], _) -> + `Ppopcntd( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Bpermd", [rs; ra; rb], _) -> + `Pbpermd( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Rlwinm", [rs; ra; sh; mb; me; rc], _) -> + `Prlwinm( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb), + (trans_out_int me)) + | ("Rlwnm", [rs; ra; rb; mb; me; rc], _) -> + `Prlwnm( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb), + (trans_out_int mb), + (trans_out_int me)) + | ("Rlwimi", [rs; ra; sh; mb; me; rc], _) -> + `Prlwimi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb), + (trans_out_int me)) + | ("Rldicl", [rs; ra; sh; mb; rc], _) -> + `Prldicl( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb)) + | ("Rldicr", [rs; ra; sh; me; rc], _) -> + `Prldicr( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int me)) + | ("Rldic", [rs; ra; sh; mb; rc], _) -> + `Prldic( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb)) + | ("Rldcl", [rs; ra; rb; mb; rc], _) -> + `Prldcl( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb), + (trans_out_int mb)) + | ("Rldcr", [rs; ra; rb; me; rc], _) -> + `Prldcr( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb), + (trans_out_int me)) + | ("Rldimi", [rs; ra; sh; mb; rc], _) -> + `Prldimi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb)) + | ("Slw", [rs; ra; rb; rc], _) -> + `Pslw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Srw", [rs; ra; rb; rc], _) -> + `Psrw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Srawi", [rs; ra; sh; rc], _) -> + `Psrawi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh)) + | ("Sraw", [rs; ra; rb; rc], _) -> + `Psraw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Sld", [rs; ra; rb; rc], _) -> + `Psld( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Srd", [rs; ra; rb; rc], _) -> + `Psrd( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Sradi", [rs; ra; sh; rc], _) -> + `Psradi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh)) + | ("Srad", [rs; ra; rb; rc], _) -> + `Psrad( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Cdtbcd", [rs; ra], _) -> + `Pcdtbcd( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Cbcdtd", [rs; ra], _) -> + `Pcbcdtd( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Addg6s", [rt; ra; rb], _) -> + `Paddg6s( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mtspr", [rs; spr], _) -> + `Pmtspr( + (trans_out_int spr), + (trans_out_reg rs)) + | ("Mfspr", [rt; spr], _) -> + `Pmfspr( + (trans_out_reg rt), + (trans_out_int spr)) + | ("Mtcrf", [rs; fxm], _) -> + `Pmtcrf( + (trans_out_int fxm), + (trans_out_reg rs)) + | ("Mfcr", [rt], _) -> + `Pmfcr( + (trans_out_reg rt)) + | ("Mtocrf", [rs; fxm], _) -> + `Pmtocrf( + (trans_out_int fxm), + (trans_out_reg rs)) + | ("Mfocrf", [rt; fxm], _) -> + `Pmfocrf( + (trans_out_reg rt), + (trans_out_int fxm)) + | ("Mcrxr", [bf], _) -> + `Pmcrxr( + (trans_out_int bf)) + | ("Dlmzb", [rs; ra; rb; rc], _) -> + `Pdlmzb( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Macchw", [rt; ra; rb; oe; rc], _) -> + `Pmacchw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Macchws", [rt; ra; rb; oe; rc], _) -> + `Pmacchws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Macchwu", [rt; ra; rb; oe; rc], _) -> + `Pmacchwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Macchwsu", [rt; ra; rb; oe; rc], _) -> + `Pmacchwsu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Machhw", [rt; ra; rb; oe; rc], _) -> + `Pmachhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Machhws", [rt; ra; rb; oe; rc], _) -> + `Pmachhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Machhwu", [rt; ra; rb; oe; rc], _) -> + `Pmachhwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Machhwsu", [rt; ra; rb; oe; rc], _) -> + `Pmachhwsu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Maclhw", [rt; ra; rb; oe; rc], _) -> + `Pmaclhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Maclhws", [rt; ra; rb; oe; rc], _) -> + `Pmaclhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Maclhwu", [rt; ra; rb; oe; rc], _) -> + `Pmaclhwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Maclhwsu", [rt; ra; rb; oe; rc], _) -> + `Pmaclhwsu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulchw", [rt; ra; rb; rc], _) -> + `Pmulchw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulchwu", [rt; ra; rb; rc], _) -> + `Pmulchwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulhhw", [rt; ra; rb; rc], _) -> + `Pmulhhw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulhhwu", [rt; ra; rb; rc], _) -> + `Pmulhhwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mullhw", [rt; ra; rb; rc], _) -> + `Pmullhw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mullhwu", [rt; ra; rb; rc], _) -> + `Pmullhwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Nmacchw", [rt; ra; rb; oe; rc], _) -> + `Pnmacchw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Nmacchws", [rt; ra; rb; oe; rc], _) -> + `Pnmacchws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Nmachhw", [rt; ra; rb; oe; rc], _) -> + `Pnmachhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Nmachhws", [rt; ra; rb; oe; rc], _) -> + `Pnmachhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Nmaclhw", [rt; ra; rb; oe; rc], _) -> + `Pnmaclhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Nmaclhws", [rt; ra; rb; oe; rc], _) -> + `Pnmaclhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Icbi", [ra; rb], _) -> + `Picbi( + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Icbt", [ct; ra; rb], _) -> + `Picbt( + (trans_out_int ct), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Dcba", [ra; rb], _) -> + `Pdcba( + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Dcbt", [th; ra; rb], _) -> + `Pdcbt( + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int th)) + | ("Dcbtst", [th; ra; rb], _) -> + `Pdcbtst( + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int th)) + | ("Dcbz", [ra; rb], _) -> + `Pdcbz( + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Dcbst", [ra; rb], _) -> + `Pdcbst( + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Dcbf", [l; ra; rb], _) -> + `Pdcbf( + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int l)) + | ("Isync", [], _) -> + `Pisync + + | ("Lbarx", [rt; ra; rb; eh], _) -> + `Plbarx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int eh)) + | ("Lharx", [rt; ra; rb; eh], _) -> + `Plharx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int eh)) + | ("Lwarx", [rt; ra; rb; eh], _) -> + `Plwarx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int eh)) + | ("Stbcx", [rs; ra; rb], _) -> + `Pstbcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Sthcx", [rs; ra; rb], _) -> + `Psthcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stwcx", [rs; ra; rb], _) -> + `Pstwcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Ldarx", [rt; ra; rb; eh], _) -> + `Pldarx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int eh)) + | ("Stdcx", [rs; ra; rb], _) -> + `Pstdcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Sync", [l], _) -> + `Psync( + (trans_out_int l)) + | ("Eieio", [], _) -> + `Peieio + + | ("Wait", [wc], _) -> + `Pwait( + (trans_out_int wc)) diff --git a/power/gen/sail_trans_out_types.hgen b/power/gen/sail_trans_out_types.hgen new file mode 100644 index 00000000..08214129 --- /dev/null +++ b/power/gen/sail_trans_out_types.hgen @@ -0,0 +1,146 @@ +let trans_out_int ( _fname, _fsize, fbits ) = + Nat_big_num.to_int (SB.integer_of_bit_list fbits) + +let trans_out_reg flv = + let n = trans_out_int flv in + Ireg (match n with + | 0 -> GPR0 + | 1 -> GPR1 + | 2 -> GPR2 + | 3 -> GPR3 + | 4 -> GPR4 + | 5 -> GPR5 + | 6 -> GPR6 + | 7 -> GPR7 + | 8 -> GPR8 + | 9 -> GPR9 + | 10 -> GPR10 + | 11 -> GPR11 + | 12 -> GPR12 + | 13 -> GPR13 + | 14 -> GPR14 + | 15 -> GPR15 + | 16 -> GPR16 + | 17 -> GPR17 + | 18 -> GPR18 + | 19 -> GPR19 + | 20 -> GPR20 + | 21 -> GPR21 + | 22 -> GPR22 + | 23 -> GPR23 + | 24 -> GPR24 + | 25 -> GPR25 + | 26 -> GPR26 + | 27 -> GPR27 + | 28 -> GPR28 + | 29 -> GPR29 + | 30 -> GPR30 + | 31 -> GPR31 + | _ -> failwith "trans_out_reg given number not 0 to 31") + +let trans_out_soov ifv = + match trans_out_int ifv with + | 1 -> SetSOOV + | 0 -> DontSetSOOV + | _ -> failwith "trans_out_soov given number other than 0 and 1" + +let trans_out_cr0 ifv = + match trans_out_int ifv with + | 1 -> SetCR0 + | 0 -> DontSetCR0 + | _ -> failwith "trans_out_cr0 given number other than 0 and 1" + +let trans_out_aa ifv = + match trans_out_int ifv with + | 1 -> SetAA + | 0 -> DontSetAA + | _ -> failwith "trans_out_aa given number other than 0 and 1" + +let trans_out_lk ifv = + match trans_out_int ifv with + | 1 -> SetLK + | 0 -> DontSetLK + | _ -> failwith "trans_out_lk given number other than 0 and 1" + +(*These probably need to be checked that the shift is the correct thing to do*) +(* translating branch target addresses *) +(* CP: this does not seem to match with how the function is used, trying to fix + this now. *) +(* let trans_out_li_setaa_setlk_k3 setaa setlk li = + match li with + | (n,m,bits) -> + match bits with + | [] | [_] | [_;_] -> (n,m,bits) + | _ -> + (n,m, (let front,rest = List.hd bits, List.tl bits in + let second,rest = List.hd rest, List.tl rest in + rest @ [front;second])) *) +let trans_out_li_setaa_setlk_k3 li setaa setlk = + match li with + | (n,m,bits) -> (n,m, bits @ [Bitc_zero;Bitc_zero]) + +(* CP: this does not seem to match with how the function is used, trying to fix + this now. *) +(* let trans_out_bd_setaa_setlk_k_k_k5 setaa setlk bo bi bd = + match bd with + | (n,m,bits) -> + match bits with + | [] | [_] | [_;_] -> (n,m,bits) + | _ -> + (n,m, (let front,rest = List.hd bits, List.tl bits in + let second,rest = List.hd rest, List.tl rest in + rest @ [front;second])) *) +let trans_out_bd_setaa_setlk_k_k_k5 bo bi bd setaa setlk = + match bd with + | (n,m,bits) -> (n,m, bits @ [Bitc_zero;Bitc_zero]) + +(* translating vector-scalar floating-point ops *) +(* all of these translate a 6-bit value into a 5:1 bit pair, but differ + in number and type of arguments *) +(*this is probably wrong, probably I want to do a transformation on the bits then return, but unclear what translation*) +let trans_out_k xt = xt +let trans_out_xk xt = xt +let trans_out_t_k_k4 xt _ _ _ = trans_out_k xt +let trans_out_tx_k_k4 xt _ _ _ = trans_out_xk xt +let trans_out_t_k_reg_reg4 xt xa _ _ = trans_out_k xt +let trans_out_tx_k_reg_reg4 xt xa _ _ = trans_out_xk xt +let trans_out_s_k_reg_reg4 = trans_out_t_k_reg_reg4 +let trans_out_sx_k_reg_reg4 = trans_out_tx_k_reg_reg4 +let trans_out_t_k_k_k6 x _ _ _ _ _ = trans_out_k x +let trans_out_t_k_k_k5 x _ _ _ _ = trans_out_k x +let trans_out_tx_k_k_k6 x _ _ _ _ _= trans_out_k x +let trans_out_tx_k_k_k5 x _ _ _ _ = trans_out_k x +let trans_out_b_k_k4 = trans_out_t_k_k4 +let trans_out_bx_k_k4 = trans_out_tx_k_k4 +let trans_out_a_k_k_k6 xt xa xb _ _ _ = trans_out_k xa +let trans_out_ax_k_k_k6 xt xa xb _ _ _ = trans_out_xk xa +let trans_out_b_k_k_k6 xt xa xb _ _ _ = trans_out_k xb +let trans_out_b_k_k_k5 xt xa xb _ _ = trans_out_k xb +let trans_out_bx_k_k_k6 xt xa xb _ _ _ = trans_out_xk xb +let trans_out_bx_k_k_k5 xt xa xb _ _ = trans_out_xk xb +let trans_out_a_crindex_k_k5 bf xa xb _ _ = trans_out_k xa +let trans_out_ax_crindex_k_k5 bf xa xb _ _ = trans_out_xk xa +let trans_out_b_crindex_k_k5 bf xa xb _ _ = trans_out_k xb +let trans_out_bx_crindex_k_k5 bf xa xb _ _ = trans_out_xk xb +let trans_out_b_crindex_k3 bf xb _ = trans_out_k xb +let trans_out_bx_crindex_k3 bf xb _ = trans_out_xk xb +let trans_out_t_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_k xt +let trans_out_tx_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_xk xt +let trans_out_a_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_k xa +let trans_out_ax_setcr0_k_k_k7 setcr0 xt xa xb _ _ _= trans_out_xk xa +let trans_out_b_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_k xb +let trans_out_bx_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_xk xb +let trans_out_t_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_k xt +let trans_out_tx_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_xk xt +let trans_out_t_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_k xt +let trans_out_tx_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_xk xt +let trans_out_a_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_k xa +let trans_out_ax_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_xk xa +let trans_out_a_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_k xa +let trans_out_ax_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_xk xa +let trans_out_b_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_k xb +let trans_out_bx_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_xk xb +let trans_out_b_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_k xb +let trans_out_bx_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_xk xb +let trans_out_c_k_k_k_k8 xt xa xb xc _ _ _ _ = trans_out_k xc +let trans_out_cx_k_k_k_k8 xt xa xb xc _ _ _ _ = trans_out_xk xc
\ No newline at end of file diff --git a/power/gen/shallow_ast_to_herdtools_ast.gen b/power/gen/shallow_ast_to_herdtools_ast.gen new file mode 100644 index 00000000..1ab732f9 --- /dev/null +++ b/power/gen/shallow_ast_to_herdtools_ast.gen @@ -0,0 +1,1112 @@ + | B (li, aa, lk) -> + `Pb( + (trans_out_aa aa), + (trans_out_lk lk), + (trans_out_int (trans_out_li_setaa_setlk_k3 li aa lk))) + | Bc (bo, bi, bd, aa, lk) -> + `Pbc( + (trans_out_aa aa), + (trans_out_lk lk), + (trans_out_int bo), + (trans_out_int bi), + (trans_out_int (trans_out_bd_setaa_setlk_k_k_k5 bo bi bd aa lk))) + | Bclr (bo, bi, bh, lk) -> + `Pbclr( + (trans_out_lk lk), + (trans_out_int bo), + (trans_out_int bi), + (trans_out_int bh)) + | Bcctr (bo, bi, bh, lk) -> + `Pbcctr( + (trans_out_lk lk), + (trans_out_int bo), + (trans_out_int bi), + (trans_out_int bh)) + | Crand (bt, ba, bb) -> + `Pcrand( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Crnand (bt, ba, bb) -> + `Pcrnand( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Cror (bt, ba, bb) -> + `Pcror( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Crxor (bt, ba, bb) -> + `Pcrxor( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Crnor (bt, ba, bb) -> + `Pcrnor( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Creqv (bt, ba, bb) -> + `Pcreqv( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Crandc (bt, ba, bb) -> + `Pcrandc( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Crorc (bt, ba, bb) -> + `Pcrorc( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Mcrf (bf, bfa) -> + `Pmcrf( + (trans_out_int bf), + (trans_out_int bfa)) + | Sc (lev) -> + `Psc( + (trans_out_int lev)) + | Scv (lev) -> + `Pscv( + (trans_out_int lev)) + | Lbz (rt, ra, d) -> + `Plbz( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lbzx (rt, ra, rb) -> + `Plbzx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lbzu (rt, ra, d) -> + `Plbzu( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lbzux (rt, ra, rb) -> + `Plbzux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lhz (rt, ra, d) -> + `Plhz( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lhzx (rt, ra, rb) -> + `Plhzx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lhzu (rt, ra, d) -> + `Plhzu( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lhzux (rt, ra, rb) -> + `Plhzux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lha (rt, ra, d) -> + `Plha( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lhax (rt, ra, rb) -> + `Plhax( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lhau (rt, ra, d) -> + `Plhau( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lhaux (rt, ra, rb) -> + `Plhaux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lwz (rt, ra, d) -> + `Plwz( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lwzx (rt, ra, rb) -> + `Plwzx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lwzu (rt, ra, d) -> + `Plwzu( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lwzux (rt, ra, rb) -> + `Plwzux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lwa (rt, ra, ds) -> + `Plwa( + (trans_out_reg rt), + (trans_out_int ds), + (trans_out_reg ra)) + | Lwax (rt, ra, rb) -> + `Plwax( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lwaux (rt, ra, rb) -> + `Plwaux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Ld (rt, ra, ds) -> + `Pld( + (trans_out_reg rt), + (trans_out_int ds), + (trans_out_reg ra)) + | Ldx (rt, ra, rb) -> + `Pldx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Ldu (rt, ra, ds) -> + `Pldu( + (trans_out_reg rt), + (trans_out_int ds), + (trans_out_reg ra)) + | Ldux (rt, ra, rb) -> + `Pldux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stb (rs, ra, d) -> + `Pstb( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Stbx (rs, ra, rb) -> + `Pstbx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stbu (rs, ra, d) -> + `Pstbu( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Stbux (rs, ra, rb) -> + `Pstbux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Sth (rs, ra, d) -> + `Psth( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Sthx (rs, ra, rb) -> + `Psthx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Sthu (rs, ra, d) -> + `Psthu( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Sthux (rs, ra, rb) -> + `Psthux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stw (rs, ra, d) -> + `Pstw( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Stwx (rs, ra, rb) -> + `Pstwx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stwu (rs, ra, d) -> + `Pstwu( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Stwux (rs, ra, rb) -> + `Pstwux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Std (rs, ra, ds) -> + `Pstd( + (trans_out_reg rs), + (trans_out_int ds), + (trans_out_reg ra)) + | Stdx (rs, ra, rb) -> + `Pstdx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stdu (rs, ra, ds) -> + `Pstdu( + (trans_out_reg rs), + (trans_out_int ds), + (trans_out_reg ra)) + | Stdux (rs, ra, rb) -> + `Pstdux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lq (rtp, ra, dq, pt) -> + `Plq( + (trans_out_int rtp), + (trans_out_int dq), + (trans_out_reg ra), + (trans_out_int pt)) + | Stq (rsp, ra, ds) -> + `Pstq( + (trans_out_int rsp), + (trans_out_int ds), + (trans_out_reg ra)) + | Lhbrx (rt, ra, rb) -> + `Plhbrx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Sthbrx (rs, ra, rb) -> + `Psthbrx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lwbrx (rt, ra, rb) -> + `Plwbrx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stwbrx (rs, ra, rb) -> + `Pstwbrx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Ldbrx (rt, ra, rb) -> + `Pldbrx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stdbrx (rs, ra, rb) -> + `Pstdbrx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lmw (rt, ra, d) -> + `Plmw( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Stmw (rs, ra, d) -> + `Pstmw( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Lswi (rt, ra, nb) -> + `Plswi( + (trans_out_int rt), + (trans_out_reg ra), + (trans_out_int nb)) + | Lswx (rt, ra, rb) -> + `Plswx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stswi (rs, ra, nb) -> + `Pstswi( + (trans_out_int rs), + (trans_out_reg ra), + (trans_out_int nb)) + | Stswx (rs, ra, rb) -> + `Pstswx( + (trans_out_int rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Addi (rt, ra, si) -> + `Paddi( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | Addis (rt, ra, si) -> + `Paddis( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | Add (rt, ra, rb, oe, rc) -> + `Padd( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Subf (rt, ra, rb, oe, rc) -> + `Psubf( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Addic (rt, ra, si) -> + `Paddic( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | AddicDot (rt, ra, si) -> + `Paddicdot( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | Subfic (rt, ra, si) -> + `Psubfic( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | Addc (rt, ra, rb, oe, rc) -> + `Paddc( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Subfc (rt, ra, rb, oe, rc) -> + `Psubfc( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Adde (rt, ra, rb, oe, rc) -> + `Padde( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Subfe (rt, ra, rb, oe, rc) -> + `Psubfe( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Addme (rt, ra, oe, rc) -> + `Paddme( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | Subfme (rt, ra, oe, rc) -> + `Psubfme( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | Addze (rt, ra, oe, rc) -> + `Paddze( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | Subfze (rt, ra, oe, rc) -> + `Psubfze( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | Neg (rt, ra, oe, rc) -> + `Pneg( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | Mulli (rt, ra, si) -> + `Pmulli( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | Mullw (rt, ra, rb, oe, rc) -> + `Pmullw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulhw (rt, ra, rb, rc) -> + `Pmulhw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulhwu (rt, ra, rb, rc) -> + `Pmulhwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divw (rt, ra, rb, oe, rc) -> + `Pdivw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divwu (rt, ra, rb, oe, rc) -> + `Pdivwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divwe (rt, ra, rb, oe, rc) -> + `Pdivwe( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divweu (rt, ra, rb, oe, rc) -> + `Pdivweu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulld (rt, ra, rb, oe, rc) -> + `Pmulld( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulhd (rt, ra, rb, rc) -> + `Pmulhd( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulhdu (rt, ra, rb, rc) -> + `Pmulhdu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divd (rt, ra, rb, oe, rc) -> + `Pdivd( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divdu (rt, ra, rb, oe, rc) -> + `Pdivdu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divde (rt, ra, rb, oe, rc) -> + `Pdivde( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divdeu (rt, ra, rb, oe, rc) -> + `Pdivdeu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Cmpi (bf, l, ra, si) -> + `Pcmpi( + (trans_out_int bf), + (trans_out_bit l), + (trans_out_reg ra), + (trans_out_int si)) + | Cmp (bf, l, ra, rb) -> + `Pcmp( + (trans_out_int bf), + (trans_out_bit l), + (trans_out_reg ra), + (trans_out_reg rb)) + | Cmpli (bf, l, ra, ui) -> + `Pcmpli( + (trans_out_int bf), + (trans_out_bit l), + (trans_out_reg ra), + (trans_out_int ui)) + | Cmpl (bf, l, ra, rb) -> + `Pcmpl( + (trans_out_int bf), + (trans_out_bit l), + (trans_out_reg ra), + (trans_out_reg rb)) + | Isel (rt, ra, rb, bc) -> + `Pisel( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int bc)) + | Andi (rs, ra, ui) -> + `Pandi( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | Andis (rs, ra, ui) -> + `Pandis( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | Ori (rs, ra, ui) -> + `Pori( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | Oris (rs, ra, ui) -> + `Poris( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | Xori (rs, ra, ui) -> + `Pxori( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | Xoris (rs, ra, ui) -> + `Pxoris( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | And (rs, ra, rb, rc) -> + `Pand( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Xor (rs, ra, rb, rc) -> + `Pxor( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Nand (rs, ra, rb, rc) -> + `Pnand( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Or (rs, ra, rb, rc) -> + `Por( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Nor (rs, ra, rb, rc) -> + `Pnor( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Eqv (rs, ra, rb, rc) -> + `Peqv( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Andc (rs, ra, rb, rc) -> + `Pandc( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Orc (rs, ra, rb, rc) -> + `Porc( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Extsb (rs, ra, rc) -> + `Pextsb( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | Extsh (rs, ra, rc) -> + `Pextsh( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | Cntlzw (rs, ra, rc) -> + `Pcntlzw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | Cmpb (rs, ra, rb) -> + `Pcmpb( + (trans_out_reg ra), + (trans_out_int rs), + (trans_out_reg rb)) + | Popcntb (rs, ra) -> + `Ppopcntb( + (trans_out_reg ra), + (trans_out_reg rs)) + | Popcntw (rs, ra) -> + `Ppopcntw( + (trans_out_reg ra), + (trans_out_reg rs)) + | Prtyd (rs, ra) -> + `Pprtyd( + (trans_out_reg ra), + (trans_out_reg rs)) + | Prtyw (rs, ra) -> + `Pprtyw( + (trans_out_reg ra), + (trans_out_reg rs)) + | Extsw (rs, ra, rc) -> + `Pextsw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | Cntlzd (rs, ra, rc) -> + `Pcntlzd( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | Popcntd (rs, ra) -> + `Ppopcntd( + (trans_out_reg ra), + (trans_out_reg rs)) + | Bpermd (rs, ra, rb) -> + `Pbpermd( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Rlwinm (rs, ra, sh, mb, me, rc) -> + `Prlwinm( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb), + (trans_out_int me)) + | Rlwnm (rs, ra, rb, mb, me, rc) -> + `Prlwnm( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb), + (trans_out_int mb), + (trans_out_int me)) + | Rlwimi (rs, ra, sh, mb, me, rc) -> + `Prlwimi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb), + (trans_out_int me)) + | Rldicl (rs, ra, sh, mb, rc) -> + `Prldicl( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb)) + | Rldicr (rs, ra, sh, me, rc) -> + `Prldicr( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int me)) + | Rldic (rs, ra, sh, mb, rc) -> + `Prldic( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb)) + | Rldcl (rs, ra, rb, mb, rc) -> + `Prldcl( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb), + (trans_out_int mb)) + | Rldcr (rs, ra, rb, me, rc) -> + `Prldcr( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb), + (trans_out_int me)) + | Rldimi (rs, ra, sh, mb, rc) -> + `Prldimi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb)) + | Slw (rs, ra, rb, rc) -> + `Pslw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Srw (rs, ra, rb, rc) -> + `Psrw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Srawi (rs, ra, sh, rc) -> + `Psrawi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh)) + | Sraw (rs, ra, rb, rc) -> + `Psraw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Sld (rs, ra, rb, rc) -> + `Psld( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Srd (rs, ra, rb, rc) -> + `Psrd( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Sradi (rs, ra, sh, rc) -> + `Psradi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh)) + | Srad (rs, ra, rb, rc) -> + `Psrad( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Cdtbcd (rs, ra) -> + `Pcdtbcd( + (trans_out_reg ra), + (trans_out_reg rs)) + | Cbcdtd (rs, ra) -> + `Pcbcdtd( + (trans_out_reg ra), + (trans_out_reg rs)) + | Addg6s (rt, ra, rb) -> + `Paddg6s( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mtspr (rs, spr) -> + `Pmtspr( + (trans_out_int spr), + (trans_out_reg rs)) + | Mfspr (rt, spr) -> + `Pmfspr( + (trans_out_reg rt), + (trans_out_int spr)) + | Mtcrf (rs, fxm) -> + `Pmtcrf( + (trans_out_int fxm), + (trans_out_reg rs)) + | Mfcr (rt) -> + `Pmfcr( + (trans_out_reg rt)) + | Mtocrf (rs, fxm) -> + `Pmtocrf( + (trans_out_int fxm), + (trans_out_reg rs)) + | Mfocrf (rt, fxm) -> + `Pmfocrf( + (trans_out_reg rt), + (trans_out_int fxm)) + | Mcrxr (bf) -> + `Pmcrxr( + (trans_out_int bf)) + | Dlmzb (rs, ra, rb, rc) -> + `Pdlmzb( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Macchw (rt, ra, rb, oe, rc) -> + `Pmacchw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Macchws (rt, ra, rb, oe, rc) -> + `Pmacchws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Macchwu (rt, ra, rb, oe, rc) -> + `Pmacchwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Macchwsu (rt, ra, rb, oe, rc) -> + `Pmacchwsu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Machhw (rt, ra, rb, oe, rc) -> + `Pmachhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Machhws (rt, ra, rb, oe, rc) -> + `Pmachhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Machhwu (rt, ra, rb, oe, rc) -> + `Pmachhwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Machhwsu (rt, ra, rb, oe, rc) -> + `Pmachhwsu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Maclhw (rt, ra, rb, oe, rc) -> + `Pmaclhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Maclhws (rt, ra, rb, oe, rc) -> + `Pmaclhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Maclhwu (rt, ra, rb, oe, rc) -> + `Pmaclhwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Maclhwsu (rt, ra, rb, oe, rc) -> + `Pmaclhwsu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulchw (rt, ra, rb, rc) -> + `Pmulchw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulchwu (rt, ra, rb, rc) -> + `Pmulchwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulhhw (rt, ra, rb, rc) -> + `Pmulhhw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulhhwu (rt, ra, rb, rc) -> + `Pmulhhwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mullhw (rt, ra, rb, rc) -> + `Pmullhw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mullhwu (rt, ra, rb, rc) -> + `Pmullhwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Nmacchw (rt, ra, rb, oe, rc) -> + `Pnmacchw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Nmacchws (rt, ra, rb, oe, rc) -> + `Pnmacchws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Nmachhw (rt, ra, rb, oe, rc) -> + `Pnmachhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Nmachhws (rt, ra, rb, oe, rc) -> + `Pnmachhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Nmaclhw (rt, ra, rb, oe, rc) -> + `Pnmaclhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Nmaclhws (rt, ra, rb, oe, rc) -> + `Pnmaclhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Icbi (ra, rb) -> + `Picbi( + (trans_out_reg ra), + (trans_out_reg rb)) + | Icbt (ct, ra, rb) -> + `Picbt( + (trans_out_int ct), + (trans_out_reg ra), + (trans_out_reg rb)) + | Dcba (ra, rb) -> + `Pdcba( + (trans_out_reg ra), + (trans_out_reg rb)) + | Dcbt (th, ra, rb) -> + `Pdcbt( + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int th)) + | Dcbtst (th, ra, rb) -> + `Pdcbtst( + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int th)) + | Dcbz (ra, rb) -> + `Pdcbz( + (trans_out_reg ra), + (trans_out_reg rb)) + | Dcbst (ra, rb) -> + `Pdcbst( + (trans_out_reg ra), + (trans_out_reg rb)) + | Dcbf (l, ra, rb) -> + `Pdcbf( + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int l)) + | Isync -> + `Pisync + + | Lbarx (rt, ra, rb, eh) -> + `Plbarx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_bit eh)) + | Lharx (rt, ra, rb, eh) -> + `Plharx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_bit eh)) + | Lwarx (rt, ra, rb, eh) -> + `Plwarx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_bit eh)) + | Stbcx (rs, ra, rb) -> + `Pstbcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Sthcx (rs, ra, rb) -> + `Psthcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stwcx (rs, ra, rb) -> + `Pstwcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Ldarx (rt, ra, rb, eh) -> + `Pldarx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_bit eh)) + | Stdcx (rs, ra, rb) -> + `Pstdcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Sync (l) -> + `Psync( + (trans_out_int l)) + | Eieio -> + `Peieio + + | Wait (wc) -> + `Pwait( + (trans_out_int wc)) diff --git a/power/gen/shallow_types_to_herdtools_types.hgen b/power/gen/shallow_types_to_herdtools_types.hgen new file mode 100644 index 00000000..c08b0131 --- /dev/null +++ b/power/gen/shallow_types_to_herdtools_types.hgen @@ -0,0 +1,150 @@ +let trans_out_int fbits = + Nat_big_num.to_int (Sail_values.unsigned fbits) + +let trans_out_bit = function + | Sail_values.B1 -> 1 + | Sail_values.B0 -> 0 + | Sail_values.BU -> failwith "trans_out_bit given Undef bit" + + +let trans_out_reg flv = + let n = trans_out_int flv in + Ireg (match n with + | 0 -> GPR0 + | 1 -> GPR1 + | 2 -> GPR2 + | 3 -> GPR3 + | 4 -> GPR4 + | 5 -> GPR5 + | 6 -> GPR6 + | 7 -> GPR7 + | 8 -> GPR8 + | 9 -> GPR9 + | 10 -> GPR10 + | 11 -> GPR11 + | 12 -> GPR12 + | 13 -> GPR13 + | 14 -> GPR14 + | 15 -> GPR15 + | 16 -> GPR16 + | 17 -> GPR17 + | 18 -> GPR18 + | 19 -> GPR19 + | 20 -> GPR20 + | 21 -> GPR21 + | 22 -> GPR22 + | 23 -> GPR23 + | 24 -> GPR24 + | 25 -> GPR25 + | 26 -> GPR26 + | 27 -> GPR27 + | 28 -> GPR28 + | 29 -> GPR29 + | 30 -> GPR30 + | 31 -> GPR31 + | _ -> failwith "trans_out_reg given number not 0 to 31") + +let trans_out_soov = function + | Sail_values.B1 -> SetSOOV + | Sail_values.B0 -> DontSetSOOV + | _ -> failwith "trans_out_soov given undef bit" + +let trans_out_cr0 = function + | Sail_values.B1 -> SetCR0 + | Sail_values.B0 -> DontSetCR0 + | _ -> failwith "trans_out_cr0 given undef bit" + +let trans_out_aa = function + | Sail_values.B1 -> SetAA + | Sail_values.B0 -> DontSetAA + | _ -> failwith "trans_out_aa given undef bit" + +let trans_out_lk = function + | Sail_values.B1 -> SetLK + | Sail_values.B0 -> DontSetLK + | _ -> failwith "trans_out_lk given undef bit" + +(*These probably need to be checked that the shift is the correct thing to do*) +(* translating branch target addresses *) +(* CP: this seems to assume a different parameter order from how it's used, this + was undetected because the previous field value representation was "untyped", + trying to fix this now. *) +(* let trans_out_li_setaa_setlk_k3 setaa setlk li = + match li with + | (n,m,bits) -> + match bits with + | [] | [_] | [_;_] -> (n,m,bits) + | _ -> + (n,m, (let front,rest = List.hd bits, List.tl bits in + let second,rest = List.hd rest, List.tl rest in + rest @ [front;second])) *) +let trans_out_li_setaa_setlk_k3 li setaa setlk = + match li with + | Sail_values.Vector (bits,start,is_inc) -> + Sail_values.Vector (bits @ [Sail_values.B0;Sail_values.B0],start,is_inc) + +(* CP: same here *) +(* let trans_out_bd_setaa_setlk_k_k_k5 setaa setlk bo bi bd = + match bd with + | (n,m,bits) -> + match bits with + | [] | [_] | [_;_] -> (n,m,bits) + | _ -> + (n,m, (let front,rest = List.hd bits, List.tl bits in + let second,rest = List.hd rest, List.tl rest in + rest @ [front;second])) *) +let trans_out_bd_setaa_setlk_k_k_k5 bo bi bd setaa setlk = + match bd with + | Sail_values.Vector (bits,start,is_inc) -> + Sail_values.Vector (bits @ [Sail_values.B0;Sail_values.B0],start,is_inc) + +(* translating vector-scalar floating-point ops *) +(* all of these translate a 6-bit value into a 5:1 bit pair, but differ + in number and type of arguments *) +(*this is probably wrong, probably I want to do a transformation on the bits then return, but unclear what translation*) +let trans_out_k xt = xt +let trans_out_xk xt = xt +let trans_out_t_k_k4 xt _ _ _ = trans_out_k xt +let trans_out_tx_k_k4 xt _ _ _ = trans_out_xk xt +let trans_out_t_k_reg_reg4 xt xa _ _ = trans_out_k xt +let trans_out_tx_k_reg_reg4 xt xa _ _ = trans_out_xk xt +let trans_out_s_k_reg_reg4 = trans_out_t_k_reg_reg4 +let trans_out_sx_k_reg_reg4 = trans_out_tx_k_reg_reg4 +let trans_out_t_k_k_k6 x _ _ _ _ _ = trans_out_k x +let trans_out_t_k_k_k5 x _ _ _ _ = trans_out_k x +let trans_out_tx_k_k_k6 x _ _ _ _ _= trans_out_k x +let trans_out_tx_k_k_k5 x _ _ _ _ = trans_out_k x +let trans_out_b_k_k4 = trans_out_t_k_k4 +let trans_out_bx_k_k4 = trans_out_tx_k_k4 +let trans_out_a_k_k_k6 xt xa xb _ _ _ = trans_out_k xa +let trans_out_ax_k_k_k6 xt xa xb _ _ _ = trans_out_xk xa +let trans_out_b_k_k_k6 xt xa xb _ _ _ = trans_out_k xb +let trans_out_b_k_k_k5 xt xa xb _ _ = trans_out_k xb +let trans_out_bx_k_k_k6 xt xa xb _ _ _ = trans_out_xk xb +let trans_out_bx_k_k_k5 xt xa xb _ _ = trans_out_xk xb +let trans_out_a_crindex_k_k5 bf xa xb _ _ = trans_out_k xa +let trans_out_ax_crindex_k_k5 bf xa xb _ _ = trans_out_xk xa +let trans_out_b_crindex_k_k5 bf xa xb _ _ = trans_out_k xb +let trans_out_bx_crindex_k_k5 bf xa xb _ _ = trans_out_xk xb +let trans_out_b_crindex_k3 bf xb _ = trans_out_k xb +let trans_out_bx_crindex_k3 bf xb _ = trans_out_xk xb +let trans_out_t_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_k xt +let trans_out_tx_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_xk xt +let trans_out_a_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_k xa +let trans_out_ax_setcr0_k_k_k7 setcr0 xt xa xb _ _ _= trans_out_xk xa +let trans_out_b_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_k xb +let trans_out_bx_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_xk xb +let trans_out_t_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_k xt +let trans_out_tx_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_xk xt +let trans_out_t_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_k xt +let trans_out_tx_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_xk xt +let trans_out_a_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_k xa +let trans_out_ax_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_xk xa +let trans_out_a_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_k xa +let trans_out_ax_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_xk xa +let trans_out_b_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_k xb +let trans_out_bx_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_xk xb +let trans_out_b_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_k xb +let trans_out_bx_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_xk xb +let trans_out_c_k_k_k_k8 xt xa xb xc _ _ _ _ = trans_out_k xc +let trans_out_cx_k_k_k_k8 xt xa xb xc _ _ _ _ = trans_out_xk xc
\ No newline at end of file diff --git a/power/gen/tokens.gen b/power/gen/tokens.gen new file mode 100644 index 00000000..f9022936 --- /dev/null +++ b/power/gen/tokens.gen @@ -0,0 +1,368 @@ +%token B +%token BA +%token BL +%token BLA +%token BC +%token BCA +%token BCL +%token BCLA +%token BCLR +%token BCLRL +%token BCCTR +%token BCCTRL +%token CRAND +%token CRNAND +%token CROR +%token CRXOR +%token CRNOR +%token CREQV +%token CRANDC +%token CRORC +%token MCRF +%token SC +%token SCV +%token LBZ +%token LBZX +%token LBZU +%token LBZUX +%token LHZ +%token LHZX +%token LHZU +%token LHZUX +%token LHA +%token LHAX +%token LHAU +%token LHAUX +%token LWZ +%token LWZX +%token LWZU +%token LWZUX +%token LWA +%token LWAX +%token LWAUX +%token LD +%token LDX +%token LDU +%token LDUX +%token STB +%token STBX +%token STBU +%token STBUX +%token STH +%token STHX +%token STHU +%token STHUX +%token STW +%token STWX +%token STWU +%token STWUX +%token STD +%token STDX +%token STDU +%token STDUX +%token LQ +%token STQ +%token LHBRX +%token STHBRX +%token LWBRX +%token STWBRX +%token LDBRX +%token STDBRX +%token LMW +%token STMW +%token LSWI +%token LSWX +%token STSWI +%token STSWX +%token ADDI +%token ADDIS +%token ADD +%token ADDDOT +%token ADDO +%token ADDODOT +%token SUBF +%token SUBFDOT +%token SUBFO +%token SUBFODOT +%token ADDIC +%token ADDICDOT +%token SUBFIC +%token ADDC +%token ADDCDOT +%token ADDCO +%token ADDCODOT +%token SUBFC +%token SUBFCDOT +%token SUBFCO +%token SUBFCODOT +%token ADDE +%token ADDEDOT +%token ADDEO +%token ADDEODOT +%token SUBFE +%token SUBFEDOT +%token SUBFEO +%token SUBFEODOT +%token ADDME +%token ADDMEDOT +%token ADDMEO +%token ADDMEODOT +%token SUBFME +%token SUBFMEDOT +%token SUBFMEO +%token SUBFMEODOT +%token ADDZE +%token ADDZEDOT +%token ADDZEO +%token ADDZEODOT +%token SUBFZE +%token SUBFZEDOT +%token SUBFZEO +%token SUBFZEODOT +%token NEG +%token NEGDOT +%token NEGO +%token NEGODOT +%token MULLI +%token MULLW +%token MULLWDOT +%token MULLWO +%token MULLWODOT +%token MULHW +%token MULHWDOT +%token MULHWU +%token MULHWUDOT +%token DIVW +%token DIVWDOT +%token DIVWO +%token DIVWODOT +%token DIVWU +%token DIVWUDOT +%token DIVWUO +%token DIVWUODOT +%token DIVWE +%token DIVWEDOT +%token DIVWEO +%token DIVWEODOT +%token DIVWEU +%token DIVWEUDOT +%token DIVWEUO +%token DIVWEUODOT +%token MULLD +%token MULLDDOT +%token MULLDO +%token MULLDODOT +%token MULHD +%token MULHDDOT +%token MULHDU +%token MULHDUDOT +%token DIVD +%token DIVDDOT +%token DIVDO +%token DIVDODOT +%token DIVDU +%token DIVDUDOT +%token DIVDUO +%token DIVDUODOT +%token DIVDE +%token DIVDEDOT +%token DIVDEO +%token DIVDEODOT +%token DIVDEU +%token DIVDEUDOT +%token DIVDEUO +%token DIVDEUODOT +%token CMPI +%token CMP +%token CMPLI +%token CMPL +%token ISEL +%token ANDIDOT +%token ANDISDOT +%token ORI +%token ORIS +%token XORI +%token XORIS +%token AND +%token ANDDOT +%token XOR +%token XORDOT +%token NAND +%token NANDDOT +%token OR +%token ORDOT +%token NOR +%token NORDOT +%token EQV +%token EQVDOT +%token ANDC +%token ANDCDOT +%token ORC +%token ORCDOT +%token EXTSB +%token EXTSBDOT +%token EXTSH +%token EXTSHDOT +%token CNTLZW +%token CNTLZWDOT +%token CMPB +%token POPCNTB +%token POPCNTW +%token PRTYD +%token PRTYW +%token EXTSW +%token EXTSWDOT +%token CNTLZD +%token CNTLZDDOT +%token POPCNTD +%token BPERMD +%token RLWINM +%token RLWINMDOT +%token RLWNM +%token RLWNMDOT +%token RLWIMI +%token RLWIMIDOT +%token RLDICL +%token RLDICLDOT +%token RLDICR +%token RLDICRDOT +%token RLDIC +%token RLDICDOT +%token RLDCL +%token RLDCLDOT +%token RLDCR +%token RLDCRDOT +%token RLDIMI +%token RLDIMIDOT +%token SLW +%token SLWDOT +%token SRW +%token SRWDOT +%token SRAWI +%token SRAWIDOT +%token SRAW +%token SRAWDOT +%token SLD +%token SLDDOT +%token SRD +%token SRDDOT +%token SRADI +%token SRADIDOT +%token SRAD +%token SRADDOT +%token CDTBCD +%token CBCDTD +%token ADDG6S +%token MTSPR +%token MFSPR +%token MTCRF +%token MFCR +%token MTOCRF +%token MFOCRF +%token MCRXR +%token DLMZB +%token DLMZBDOT +%token MACCHW +%token MACCHWDOT +%token MACCHWO +%token MACCHWODOT +%token MACCHWS +%token MACCHWSDOT +%token MACCHWSO +%token MACCHWSODOT +%token MACCHWU +%token MACCHWUDOT +%token MACCHWUO +%token MACCHWUODOT +%token MACCHWSU +%token MACCHWSUDOT +%token MACCHWSUO +%token MACCHWSUODOT +%token MACHHW +%token MACHHWDOT +%token MACHHWO +%token MACHHWODOT +%token MACHHWS +%token MACHHWSDOT +%token MACHHWSO +%token MACHHWSODOT +%token MACHHWU +%token MACHHWUDOT +%token MACHHWUO +%token MACHHWUODOT +%token MACHHWSU +%token MACHHWSUDOT +%token MACHHWSUO +%token MACHHWSUODOT +%token MACLHW +%token MACLHWDOT +%token MACLHWO +%token MACLHWODOT +%token MACLHWS +%token MACLHWSDOT +%token MACLHWSO +%token MACLHWSODOT +%token MACLHWU +%token MACLHWUDOT +%token MACLHWUO +%token MACLHWUODOT +%token MACLHWSU +%token MACLHWSUDOT +%token MACLHWSUO +%token MACLHWSUODOT +%token MULCHW +%token MULCHWDOT +%token MULCHWU +%token MULCHWUDOT +%token MULHHW +%token MULHHWDOT +%token MULHHWU +%token MULHHWUDOT +%token MULLHW +%token MULLHWDOT +%token MULLHWU +%token MULLHWUDOT +%token NMACCHW +%token NMACCHWDOT +%token NMACCHWO +%token NMACCHWODOT +%token NMACCHWS +%token NMACCHWSDOT +%token NMACCHWSO +%token NMACCHWSODOT +%token NMACHHW +%token NMACHHWDOT +%token NMACHHWO +%token NMACHHWODOT +%token NMACHHWS +%token NMACHHWSDOT +%token NMACHHWSO +%token NMACHHWSODOT +%token NMACLHW +%token NMACLHWDOT +%token NMACLHWO +%token NMACLHWODOT +%token NMACLHWS +%token NMACLHWSDOT +%token NMACLHWSO +%token NMACLHWSODOT +%token ICBI +%token ICBT +%token DCBA +%token DCBT +%token DCBTST +%token DCBZ +%token DCBST +%token DCBF +%token ISYNC +%token LBARX +%token LHARX +%token LWARX +%token STBCXDOT +%token STHCXDOT +%token STWCXDOT +%token LDARX +%token STDCXDOT +%token SYNC +%token EIEIO +%token WAIT diff --git a/power/gen/trans_sail.gen b/power/gen/trans_sail.gen new file mode 100644 index 00000000..b6f406f2 --- /dev/null +++ b/power/gen/trans_sail.gen @@ -0,0 +1,1516 @@ + | `Pb(setaa0, setlk1, k2) -> + ("B", + [("LI", IInt.Bvector (Some 24), SB.bit_list_of_integer 24 (Nat_big_num.of_int (trans_li_setaa_setlk_k setaa0 setlk1 k2))); + ("AA", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_aa setaa0))); + ("LK", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_lk setlk1)))], + [(* always empty base effects*)] + ) + | `Pbc(setaa0, setlk1, k2, k3, k4) -> + ("Bc", + [("BO", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2)); + ("BI", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k3)); + ("BD", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int (trans_bd_setaa_setlk_k_k_k setaa0 setlk1 k2 k3 k4))); + ("AA", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_aa setaa0))); + ("LK", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_lk setlk1)))], + [(* always empty base effects*)] + ) + | `Pbclr(setlk0, k1, k2, k3) -> + ("Bclr", + [("BO", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BI", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2)); + ("BH", IInt.Bvector (Some 2), SB.bit_list_of_integer 2 (Nat_big_num.of_int k3)); + ("LK", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_lk setlk0)))], + [(* always empty base effects*)] + ) + | `Pbcctr(setlk0, k1, k2, k3) -> + ("Bcctr", + [("BO", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BI", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2)); + ("BH", IInt.Bvector (Some 2), SB.bit_list_of_integer 2 (Nat_big_num.of_int k3)); + ("LK", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_lk setlk0)))], + [(* always empty base effects*)] + ) + | `Pcrand(k0, k1, k2) -> + ("Crand", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcrnand(k0, k1, k2) -> + ("Crnand", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcror(k0, k1, k2) -> + ("Cror", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcrxor(k0, k1, k2) -> + ("Crxor", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcrnor(k0, k1, k2) -> + ("Crnor", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcreqv(k0, k1, k2) -> + ("Creqv", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcrandc(k0, k1, k2) -> + ("Crandc", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcrorc(k0, k1, k2) -> + ("Crorc", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pmcrf(crindex0, k1) -> + ("Mcrf", + [("BF", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int crindex0)); + ("BFA", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Psc(k0) -> + ("Sc", + [("LEV", IInt.Bvector (Some 7), SB.bit_list_of_integer 7 (Nat_big_num.of_int k0))], + [(* always empty base effects*)] + ) + | `Pscv(k0) -> + ("Scv", + [("LEV", IInt.Bvector (Some 7), SB.bit_list_of_integer 7 (Nat_big_num.of_int k0))], + [(* always empty base effects*)] + ) + | `Plbz(reg0, k1, reg2) -> + ("Lbz", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plbzx(reg0, reg1, reg2) -> + ("Lbzx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plbzu(reg0, k1, reg2) -> + ("Lbzu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plbzux(reg0, reg1, reg2) -> + ("Lbzux", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plhz(reg0, k1, reg2) -> + ("Lhz", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plhzx(reg0, reg1, reg2) -> + ("Lhzx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plhzu(reg0, k1, reg2) -> + ("Lhzu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plhzux(reg0, reg1, reg2) -> + ("Lhzux", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plha(reg0, k1, reg2) -> + ("Lha", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plhax(reg0, reg1, reg2) -> + ("Lhax", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plhau(reg0, k1, reg2) -> + ("Lhau", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plhaux(reg0, reg1, reg2) -> + ("Lhaux", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plwz(reg0, k1, reg2) -> + ("Lwz", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plwzx(reg0, reg1, reg2) -> + ("Lwzx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plwzu(reg0, k1, reg2) -> + ("Lwzu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plwzux(reg0, reg1, reg2) -> + ("Lwzux", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plwa(reg0, ds1, reg2) -> + ("Lwa", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DS", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int ds1))], + [(* always empty base effects*)] + ) + | `Plwax(reg0, reg1, reg2) -> + ("Lwax", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plwaux(reg0, reg1, reg2) -> + ("Lwaux", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pld(reg0, ds1, reg2) -> + ("Ld", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DS", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int ds1))], + [(* always empty base effects*)] + ) + | `Pldx(reg0, reg1, reg2) -> + ("Ldx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pldu(reg0, ds1, reg2) -> + ("Ldu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DS", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int ds1))], + [(* always empty base effects*)] + ) + | `Pldux(reg0, reg1, reg2) -> + ("Ldux", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstb(reg0, k1, reg2) -> + ("Stb", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Pstbx(reg0, reg1, reg2) -> + ("Stbx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstbu(reg0, k1, reg2) -> + ("Stbu", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Pstbux(reg0, reg1, reg2) -> + ("Stbux", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Psth(reg0, k1, reg2) -> + ("Sth", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Psthx(reg0, reg1, reg2) -> + ("Sthx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Psthu(reg0, k1, reg2) -> + ("Sthu", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Psthux(reg0, reg1, reg2) -> + ("Sthux", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstw(reg0, k1, reg2) -> + ("Stw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Pstwx(reg0, reg1, reg2) -> + ("Stwx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstwu(reg0, k1, reg2) -> + ("Stwu", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Pstwux(reg0, reg1, reg2) -> + ("Stwux", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstd(reg0, ds1, reg2) -> + ("Std", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DS", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int ds1))], + [(* always empty base effects*)] + ) + | `Pstdx(reg0, reg1, reg2) -> + ("Stdx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstdu(reg0, ds1, reg2) -> + ("Stdu", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DS", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int ds1))], + [(* always empty base effects*)] + ) + | `Pstdux(reg0, reg1, reg2) -> + ("Stdux", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plq(k0, k1, reg2, k3) -> + ("Lq", + [("RTp", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DQ", IInt.Bvector (Some 12), SB.bit_list_of_integer 12 (Nat_big_num.of_int k1)); + ("PT", IInt.Bvector (Some 4), SB.bit_list_of_integer 4 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Pstq(k0, ds1, reg2) -> + ("Stq", + [("RSp", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DS", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int ds1))], + [(* always empty base effects*)] + ) + | `Plhbrx(reg0, reg1, reg2) -> + ("Lhbrx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Psthbrx(reg0, reg1, reg2) -> + ("Sthbrx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plwbrx(reg0, reg1, reg2) -> + ("Lwbrx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstwbrx(reg0, reg1, reg2) -> + ("Stwbrx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pldbrx(reg0, reg1, reg2) -> + ("Ldbrx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstdbrx(reg0, reg1, reg2) -> + ("Stdbrx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plmw(reg0, k1, reg2) -> + ("Lmw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Pstmw(reg0, k1, reg2) -> + ("Stmw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plswi(k0, reg1, k2) -> + ("Lswi", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("NB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Plswx(reg0, reg1, reg2) -> + ("Lswx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstswi(k0, reg1, k2) -> + ("Stswi", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("NB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pstswx(k0, reg1, reg2) -> + ("Stswx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Paddi(reg0, reg1, k2) -> + ("Addi", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Paddis(reg0, reg1, k2) -> + ("Addis", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Padd(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Add", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Psubf(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Subf", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Paddic(reg0, reg1, k2) -> + ("Addic", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Paddicdot(reg0, reg1, k2) -> + ("AddicDot", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Psubfic(reg0, reg1, k2) -> + ("Subfic", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Paddc(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Addc", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Psubfc(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Subfc", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Padde(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Adde", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Psubfe(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Subfe", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Paddme(setsoov0, setcr01, reg2, reg3) -> + ("Addme", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Psubfme(setsoov0, setcr01, reg2, reg3) -> + ("Subfme", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Paddze(setsoov0, setcr01, reg2, reg3) -> + ("Addze", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Psubfze(setsoov0, setcr01, reg2, reg3) -> + ("Subfze", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pneg(setsoov0, setcr01, reg2, reg3) -> + ("Neg", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmulli(reg0, reg1, k2) -> + ("Mulli", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pmullw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Mullw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmulhw(setcr00, reg1, reg2, reg3) -> + ("Mulhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmulhwu(setcr00, reg1, reg2, reg3) -> + ("Mulhwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pdivw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pdivwu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pdivwe(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divwe", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pdivweu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divweu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmulld(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Mulld", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmulhd(setcr00, reg1, reg2, reg3) -> + ("Mulhd", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmulhdu(setcr00, reg1, reg2, reg3) -> + ("Mulhdu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pdivd(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divd", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pdivdu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divdu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pdivde(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divde", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pdivdeu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divdeu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pcmpi(crindex0, k1, reg2, k3) -> + ("Cmpi", + [("BF", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int crindex0)); + ("L", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k1)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Pcmp(crindex0, k1, reg2, reg3) -> + ("Cmp", + [("BF", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int crindex0)); + ("L", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k1)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3)))], + [(* always empty base effects*)] + ) + | `Pcmpli(crindex0, k1, reg2, k3) -> + ("Cmpli", + [("BF", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int crindex0)); + ("L", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k1)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Pcmpl(crindex0, k1, reg2, reg3) -> + ("Cmpl", + [("BF", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int crindex0)); + ("L", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k1)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3)))], + [(* always empty base effects*)] + ) + | `Pisel(reg0, reg1, reg2, k3) -> + ("Isel", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("BC", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Pandi(reg0, reg1, k2) -> + ("Andi", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pandis(reg0, reg1, k2) -> + ("Andis", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pori(reg0, reg1, k2) -> + ("Ori", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Poris(reg0, reg1, k2) -> + ("Oris", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pxori(reg0, reg1, k2) -> + ("Xori", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pxoris(reg0, reg1, k2) -> + ("Xoris", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pand(setcr00, reg1, reg2, reg3) -> + ("And", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pxor(setcr00, reg1, reg2, reg3) -> + ("Xor", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pnand(setcr00, reg1, reg2, reg3) -> + ("Nand", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Por(setcr00, reg1, reg2, reg3) -> + ("Or", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pnor(setcr00, reg1, reg2, reg3) -> + ("Nor", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Peqv(setcr00, reg1, reg2, reg3) -> + ("Eqv", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pandc(setcr00, reg1, reg2, reg3) -> + ("Andc", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Porc(setcr00, reg1, reg2, reg3) -> + ("Orc", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pextsb(setcr00, reg1, reg2) -> + ("Extsb", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pextsh(setcr00, reg1, reg2) -> + ("Extsh", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pcntlzw(setcr00, reg1, reg2) -> + ("Cntlzw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pcmpb(reg0, k1, reg2) -> + ("Cmpb", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Ppopcntb(reg0, reg1) -> + ("Popcntb", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Ppopcntw(reg0, reg1) -> + ("Popcntw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Pprtyd(reg0, reg1) -> + ("Prtyd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Pprtyw(reg0, reg1) -> + ("Prtyw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Pextsw(setcr00, reg1, reg2) -> + ("Extsw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pcntlzd(setcr00, reg1, reg2) -> + ("Cntlzd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Ppopcntd(reg0, reg1) -> + ("Popcntd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Pbpermd(reg0, reg1, reg2) -> + ("Bpermd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Prlwinm(setcr00, reg1, reg2, k3, k4, k5) -> + ("Rlwinm", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SH", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k3)); + ("MB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k4)); + ("ME", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k5)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prlwnm(setcr00, reg1, reg2, reg3, k4, k5) -> + ("Rlwnm", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("MB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k4)); + ("ME", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k5)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prlwimi(setcr00, reg1, reg2, k3, k4, k5) -> + ("Rlwimi", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SH", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k3)); + ("MB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k4)); + ("ME", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k5)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prldicl(setcr00, reg1, reg2, k3, k4) -> + ("Rldicl", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("sh", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k3)); + ("mb", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k4)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prldicr(setcr00, reg1, reg2, k3, k4) -> + ("Rldicr", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("sh", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k3)); + ("me", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k4)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prldic(setcr00, reg1, reg2, k3, k4) -> + ("Rldic", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("sh", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k3)); + ("mb", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k4)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prldcl(setcr00, reg1, reg2, reg3, k4) -> + ("Rldcl", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("mb", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k4)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prldcr(setcr00, reg1, reg2, reg3, k4) -> + ("Rldcr", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("me", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k4)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prldimi(setcr00, reg1, reg2, k3, k4) -> + ("Rldimi", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("sh", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k3)); + ("mb", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k4)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pslw(setcr00, reg1, reg2, reg3) -> + ("Slw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psrw(setcr00, reg1, reg2, reg3) -> + ("Srw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psrawi(setcr00, reg1, reg2, k3) -> + ("Srawi", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SH", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k3)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psraw(setcr00, reg1, reg2, reg3) -> + ("Sraw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psld(setcr00, reg1, reg2, reg3) -> + ("Sld", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psrd(setcr00, reg1, reg2, reg3) -> + ("Srd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psradi(setcr00, reg1, reg2, k3) -> + ("Sradi", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("sh", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k3)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psrad(setcr00, reg1, reg2, reg3) -> + ("Srad", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pcdtbcd(reg0, reg1) -> + ("Cdtbcd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Pcbcdtd(reg0, reg1) -> + ("Cbcdtd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Paddg6s(reg0, reg1, reg2) -> + ("Addg6s", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pmtspr(k0, reg1) -> + ("Mtspr", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("spr", IInt.Bvector (Some 10), SB.bit_list_of_integer 10 (Nat_big_num.of_int k0))], + [(* always empty base effects*)] + ) + | `Pmfspr(reg0, k1) -> + ("Mfspr", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("spr", IInt.Bvector (Some 10), SB.bit_list_of_integer 10 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Pmtcrf(crmask0, reg1) -> + ("Mtcrf", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("FXM", IInt.Bvector (Some 8), SB.bit_list_of_integer 8 (Nat_big_num.of_int crmask0))], + [(* always empty base effects*)] + ) + | `Pmfcr(reg0) -> + ("Mfcr", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Pmtocrf(crmask0, reg1) -> + ("Mtocrf", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("FXM", IInt.Bvector (Some 8), SB.bit_list_of_integer 8 (Nat_big_num.of_int crmask0))], + [(* always empty base effects*)] + ) + | `Pmfocrf(reg0, crmask1) -> + ("Mfocrf", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("FXM", IInt.Bvector (Some 8), SB.bit_list_of_integer 8 (Nat_big_num.of_int crmask1))], + [(* always empty base effects*)] + ) + | `Pmcrxr(crindex0) -> + ("Mcrxr", + [("BF", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int crindex0))], + [(* always empty base effects*)] + ) + | `Pdlmzb(setcr00, reg1, reg2, reg3) -> + ("Dlmzb", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmacchw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Macchw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmacchws(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Macchws", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmacchwu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Macchwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmacchwsu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Macchwsu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmachhw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Machhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmachhws(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Machhws", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmachhwu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Machhwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmachhwsu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Machhwsu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmaclhw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Maclhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmaclhws(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Maclhws", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmaclhwu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Maclhwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmaclhwsu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Maclhwsu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmulchw(setcr00, reg1, reg2, reg3) -> + ("Mulchw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmulchwu(setcr00, reg1, reg2, reg3) -> + ("Mulchwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmulhhw(setcr00, reg1, reg2, reg3) -> + ("Mulhhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmulhhwu(setcr00, reg1, reg2, reg3) -> + ("Mulhhwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmullhw(setcr00, reg1, reg2, reg3) -> + ("Mullhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmullhwu(setcr00, reg1, reg2, reg3) -> + ("Mullhwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pnmacchw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Nmacchw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pnmacchws(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Nmacchws", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pnmachhw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Nmachhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pnmachhws(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Nmachhws", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pnmaclhw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Nmaclhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pnmaclhws(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Nmaclhws", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Picbi(reg0, reg1) -> + ("Icbi", + [("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Picbt(k0, reg1, reg2) -> + ("Icbt", + [("CT", IInt.Bvector (Some 4), SB.bit_list_of_integer 4 (Nat_big_num.of_int k0)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pdcba(reg0, reg1) -> + ("Dcba", + [("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Pdcbt(reg0, reg1, k2) -> + ("Dcbt", + [("TH", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Pdcbtst(reg0, reg1, k2) -> + ("Dcbtst", + [("TH", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Pdcbz(reg0, reg1) -> + ("Dcbz", + [("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Pdcbst(reg0, reg1) -> + ("Dcbst", + [("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Pdcbf(reg0, reg1, k2) -> + ("Dcbf", + [("L", IInt.Bvector (Some 2), SB.bit_list_of_integer 2 (Nat_big_num.of_int k2)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Pisync -> + ("Isync", + [], + [(* always empty base effects*)] + ) + | `Plbarx(reg0, reg1, reg2, k3) -> + ("Lbarx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("EH", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Plharx(reg0, reg1, reg2, k3) -> + ("Lharx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("EH", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Plwarx(reg0, reg1, reg2, k3) -> + ("Lwarx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("EH", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Pstbcx(reg0, reg1, reg2) -> + ("Stbcx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Psthcx(reg0, reg1, reg2) -> + ("Sthcx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstwcx(reg0, reg1, reg2) -> + ("Stwcx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pldarx(reg0, reg1, reg2, k3) -> + ("Ldarx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("EH", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Pstdcx(reg0, reg1, reg2) -> + ("Stdcx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Psync(k0) -> + ("Sync", + [("L", IInt.Bvector (Some 2), SB.bit_list_of_integer 2 (Nat_big_num.of_int k0))], + [(* always empty base effects*)] + ) + | `Peieio -> + ("Eieio", + [], + [(* always empty base effects*)] + ) + | `Pwait(k0) -> + ("Wait", + [("WC", IInt.Bvector (Some 2), SB.bit_list_of_integer 2 (Nat_big_num.of_int k0))], + [(* always empty base effects*)] + ) diff --git a/power/gen/trans_sail_types.hgen b/power/gen/trans_sail_types.hgen new file mode 100644 index 00000000..380fd6e7 --- /dev/null +++ b/power/gen/trans_sail_types.hgen @@ -0,0 +1,61 @@ +(* SS: should re-check interpretation of 1 and 0 *) +let trans_soov = function + | SetSOOV -> 1 + | DontSetSOOV -> 0 + +let trans_cr0 = function + | SetCR0 -> 1 + | DontSetCR0 -> 0 + +let trans_aa = function + | SetAA -> 1 + | DontSetAA -> 0 + +let trans_lk = function + | SetLK -> 1 + | DontSetLK -> 0 + + +(* translating branch target addresses *) +let trans_li_setaa_setlk_k setaa setlk li = li asr 2 +let trans_bd_setaa_setlk_k_k_k setaa setlk bo bi bd = bd asr 2 + +(* translating vector-scalar floating-point ops *) +(* all of these translate a 6-bit value into a 5:1 bit pair, but differ + in number and type of arguments *) +let trans_k xt = xt land 0x1F +let trans_xk xt = xt land 0x20 +let trans_t_k_k xt _ = trans_k xt +let trans_tx_k_k xt _ = trans_xk xt +let trans_t_k_reg_reg xt xa _ = trans_k xt +let trans_tx_k_reg_reg xt xa _ = trans_xk xt +let trans_s_k_reg_reg = trans_t_k_reg_reg +let trans_sx_k_reg_reg = trans_tx_k_reg_reg +let trans_t_k_k_k = trans_t_k_reg_reg +let trans_tx_k_k_k = trans_tx_k_reg_reg +let trans_b_k_k = trans_t_k_k +let trans_bx_k_k = trans_tx_k_k +let trans_a_k_k_k xt xa xb = trans_k xa +let trans_ax_k_k_k xt xa xb = trans_xk xa +let trans_b_k_k_k xt xa xb = trans_k xb +let trans_bx_k_k_k xt xa xb = trans_xk xb +let trans_a_crindex_k_k bf xa xb = trans_k xa +let trans_ax_crindex_k_k bf xa xb = trans_xk xa +let trans_b_crindex_k_k bf xa xb = trans_k xb +let trans_bx_crindex_k_k bf xa xb = trans_xk xb +let trans_b_crindex_k bf xb = trans_k xb +let trans_bx_crindex_k bf xb = trans_xk xb +let trans_t_setcr0_k_k_k setcr0 xt xa xb = trans_k xt +let trans_tx_setcr0_k_k_k setcr0 xt xa xb = trans_xk xt +let trans_a_setcr0_k_k_k setcr0 xt xa xb = trans_k xa +let trans_ax_setcr0_k_k_k setcr0 xt xa xb = trans_xk xa +let trans_b_setcr0_k_k_k setcr0 xt xa xb = trans_k xb +let trans_bx_setcr0_k_k_k setcr0 xt xa xb = trans_xk xb +let trans_t_k_k_k_k xt xa xb dm = trans_k xt +let trans_tx_k_k_k_k xt xa xb dm = trans_xk xt +let trans_a_k_k_k_k xt xa xb dm = trans_k xa +let trans_ax_k_k_k_k xt xa xb dm = trans_xk xa +let trans_b_k_k_k_k xt xa xb dm = trans_k xb +let trans_bx_k_k_k_k xt xa xb dm = trans_xk xb +let trans_c_k_k_k_k xt xa xb xc = trans_k xc +let trans_cx_k_k_k_k xt xa xb xc = trans_xk xc
\ No newline at end of file |