diff options
Diffstat (limited to 'old')
45 files changed, 20926 insertions, 0 deletions
diff --git a/old/power/Makefile b/old/power/Makefile new file mode 100644 index 00000000..be97aa0b --- /dev/null +++ b/old/power/Makefile @@ -0,0 +1,45 @@ +SAIL:=../src/sail.native +LEM:=../../lem/lem + +SOURCES:=power.sail ../lib/regfp.sail power_regfp.sail + + +all: power.lem power.ml power_embed.lem + +power.lem: $(SOURCES) + $(SAIL) -lem_ast -o power $(SOURCES) + +power.ml: power.lem ../src/lem_interp/interp_ast.lem + $(LEM) -ocaml -lib ../src/lem_interp/ $< + + +power_embed.lem: $(SOURCES) +# also generates power_embed_sequential.lem, power_embed_types.lem, power_toFromInterp.lem + $(SAIL) -lem -lem_lib Power_extras_embed -o power $(SOURCES) + +clean: + rm -f power.lem power.ml + rm -f power_embed*.lem power_toFromInterp.lem + +###################################################################### +ETCDIR=../etc + +apply_header: + headache -c $(ETCDIR)/headache_config -h $(ETCDIR)/power_header *.sail +.PHONY: apply_header + +###################################################################### +IDLPOWER=../../../rsem/idl/power + +pull_from_idl: + cp -a $(IDLPOWER)/generated/power.sail ./ +# cp -a $(IDLPOWER)/generated/*.lem ./ +# cp -a $(IDLPOWER)/generated/power.ml ./ +# cp -a $(IDLPOWER)/generated/*.txt ./ + cp -a $(IDLPOWER)/extras/*.sail ./ + cp -a $(IDLPOWER)/extras/*.lem ./ + mkdir -p gen + cp -a $(IDLPOWER)/generated/*.gen gen/ + cp -a $(IDLPOWER)/*.hgen gen/ + $(MAKE) apply_header +.PHONY: pull_from_idl diff --git a/old/power/gen/ast.gen b/old/power/gen/ast.gen new file mode 100644 index 00000000..fdc12609 --- /dev/null +++ b/old/power/gen/ast.gen @@ -0,0 +1,202 @@ + | `Pb of setaa*setlk*k + | `Pbc of setaa*setlk*k*k*k + | `Pbclr of setlk*k*k*k + | `Pbcctr of setlk*k*k*k + | `Pcrand of k*k*k + | `Pcrnand of k*k*k + | `Pcror of k*k*k + | `Pcrxor of k*k*k + | `Pcrnor of k*k*k + | `Pcreqv of k*k*k + | `Pcrandc of k*k*k + | `Pcrorc of k*k*k + | `Pmcrf of crindex*k + | `Psc of k + | `Pscv of k + | `Plbz of reg*k*reg + | `Plbzx of reg*reg*reg + | `Plbzu of reg*k*reg + | `Plbzux of reg*reg*reg + | `Plhz of reg*k*reg + | `Plhzx of reg*reg*reg + | `Plhzu of reg*k*reg + | `Plhzux of reg*reg*reg + | `Plha of reg*k*reg + | `Plhax of reg*reg*reg + | `Plhau of reg*k*reg + | `Plhaux of reg*reg*reg + | `Plwz of reg*k*reg + | `Plwzx of reg*reg*reg + | `Plwzu of reg*k*reg + | `Plwzux of reg*reg*reg + | `Plwa of reg*ds*reg + | `Plwax of reg*reg*reg + | `Plwaux of reg*reg*reg + | `Pld of reg*ds*reg + | `Pldx of reg*reg*reg + | `Pldu of reg*ds*reg + | `Pldux of reg*reg*reg + | `Pstb of reg*k*reg + | `Pstbx of reg*reg*reg + | `Pstbu of reg*k*reg + | `Pstbux of reg*reg*reg + | `Psth of reg*k*reg + | `Psthx of reg*reg*reg + | `Psthu of reg*k*reg + | `Psthux of reg*reg*reg + | `Pstw of reg*k*reg + | `Pstwx of reg*reg*reg + | `Pstwu of reg*k*reg + | `Pstwux of reg*reg*reg + | `Pstd of reg*ds*reg + | `Pstdx of reg*reg*reg + | `Pstdu of reg*ds*reg + | `Pstdux of reg*reg*reg + | `Plq of k*k*reg*k + | `Pstq of k*ds*reg + | `Plhbrx of reg*reg*reg + | `Psthbrx of reg*reg*reg + | `Plwbrx of reg*reg*reg + | `Pstwbrx of reg*reg*reg + | `Pldbrx of reg*reg*reg + | `Pstdbrx of reg*reg*reg + | `Plmw of reg*k*reg + | `Pstmw of reg*k*reg + | `Plswi of k*reg*k + | `Plswx of reg*reg*reg + | `Pstswi of k*reg*k + | `Pstswx of k*reg*reg + | `Paddi of reg*reg*k + | `Paddis of reg*reg*k + | `Padd of setsoov*setcr0*reg*reg*reg + | `Psubf of setsoov*setcr0*reg*reg*reg + | `Paddic of reg*reg*k + | `Paddicdot of reg*reg*k + | `Psubfic of reg*reg*k + | `Paddc of setsoov*setcr0*reg*reg*reg + | `Psubfc of setsoov*setcr0*reg*reg*reg + | `Padde of setsoov*setcr0*reg*reg*reg + | `Psubfe of setsoov*setcr0*reg*reg*reg + | `Paddme of setsoov*setcr0*reg*reg + | `Psubfme of setsoov*setcr0*reg*reg + | `Paddze of setsoov*setcr0*reg*reg + | `Psubfze of setsoov*setcr0*reg*reg + | `Pneg of setsoov*setcr0*reg*reg + | `Pmulli of reg*reg*k + | `Pmullw of setsoov*setcr0*reg*reg*reg + | `Pmulhw of setcr0*reg*reg*reg + | `Pmulhwu of setcr0*reg*reg*reg + | `Pdivw of setsoov*setcr0*reg*reg*reg + | `Pdivwu of setsoov*setcr0*reg*reg*reg + | `Pdivwe of setsoov*setcr0*reg*reg*reg + | `Pdivweu of setsoov*setcr0*reg*reg*reg + | `Pmulld of setsoov*setcr0*reg*reg*reg + | `Pmulhd of setcr0*reg*reg*reg + | `Pmulhdu of setcr0*reg*reg*reg + | `Pdivd of setsoov*setcr0*reg*reg*reg + | `Pdivdu of setsoov*setcr0*reg*reg*reg + | `Pdivde of setsoov*setcr0*reg*reg*reg + | `Pdivdeu of setsoov*setcr0*reg*reg*reg + | `Pcmpi of crindex*k*reg*k + | `Pcmp of crindex*k*reg*reg + | `Pcmpli of crindex*k*reg*k + | `Pcmpl of crindex*k*reg*reg + | `Pisel of reg*reg*reg*k + | `Pandi of reg*reg*k + | `Pandis of reg*reg*k + | `Pori of reg*reg*k + | `Poris of reg*reg*k + | `Pxori of reg*reg*k + | `Pxoris of reg*reg*k + | `Pand of setcr0*reg*reg*reg + | `Pxor of setcr0*reg*reg*reg + | `Pnand of setcr0*reg*reg*reg + | `Por of setcr0*reg*reg*reg + | `Pnor of setcr0*reg*reg*reg + | `Peqv of setcr0*reg*reg*reg + | `Pandc of setcr0*reg*reg*reg + | `Porc of setcr0*reg*reg*reg + | `Pextsb of setcr0*reg*reg + | `Pextsh of setcr0*reg*reg + | `Pcntlzw of setcr0*reg*reg + | `Pcmpb of reg*k*reg + | `Ppopcntb of reg*reg + | `Ppopcntw of reg*reg + | `Pprtyd of reg*reg + | `Pprtyw of reg*reg + | `Pextsw of setcr0*reg*reg + | `Pcntlzd of setcr0*reg*reg + | `Ppopcntd of reg*reg + | `Pbpermd of reg*reg*reg + | `Prlwinm of setcr0*reg*reg*k*k*k + | `Prlwnm of setcr0*reg*reg*reg*k*k + | `Prlwimi of setcr0*reg*reg*k*k*k + | `Prldicl of setcr0*reg*reg*k*k + | `Prldicr of setcr0*reg*reg*k*k + | `Prldic of setcr0*reg*reg*k*k + | `Prldcl of setcr0*reg*reg*reg*k + | `Prldcr of setcr0*reg*reg*reg*k + | `Prldimi of setcr0*reg*reg*k*k + | `Pslw of setcr0*reg*reg*reg + | `Psrw of setcr0*reg*reg*reg + | `Psrawi of setcr0*reg*reg*k + | `Psraw of setcr0*reg*reg*reg + | `Psld of setcr0*reg*reg*reg + | `Psrd of setcr0*reg*reg*reg + | `Psradi of setcr0*reg*reg*k + | `Psrad of setcr0*reg*reg*reg + | `Pcdtbcd of reg*reg + | `Pcbcdtd of reg*reg + | `Paddg6s of reg*reg*reg + | `Pmtspr of k*reg + | `Pmfspr of reg*k + | `Pmtcrf of crmask*reg + | `Pmfcr of reg + | `Pmtocrf of crmask*reg + | `Pmfocrf of reg*crmask + | `Pmcrxr of crindex + | `Pdlmzb of setcr0*reg*reg*reg + | `Pmacchw of setsoov*setcr0*reg*reg*reg + | `Pmacchws of setsoov*setcr0*reg*reg*reg + | `Pmacchwu of setsoov*setcr0*reg*reg*reg + | `Pmacchwsu of setsoov*setcr0*reg*reg*reg + | `Pmachhw of setsoov*setcr0*reg*reg*reg + | `Pmachhws of setsoov*setcr0*reg*reg*reg + | `Pmachhwu of setsoov*setcr0*reg*reg*reg + | `Pmachhwsu of setsoov*setcr0*reg*reg*reg + | `Pmaclhw of setsoov*setcr0*reg*reg*reg + | `Pmaclhws of setsoov*setcr0*reg*reg*reg + | `Pmaclhwu of setsoov*setcr0*reg*reg*reg + | `Pmaclhwsu of setsoov*setcr0*reg*reg*reg + | `Pmulchw of setcr0*reg*reg*reg + | `Pmulchwu of setcr0*reg*reg*reg + | `Pmulhhw of setcr0*reg*reg*reg + | `Pmulhhwu of setcr0*reg*reg*reg + | `Pmullhw of setcr0*reg*reg*reg + | `Pmullhwu of setcr0*reg*reg*reg + | `Pnmacchw of setsoov*setcr0*reg*reg*reg + | `Pnmacchws of setsoov*setcr0*reg*reg*reg + | `Pnmachhw of setsoov*setcr0*reg*reg*reg + | `Pnmachhws of setsoov*setcr0*reg*reg*reg + | `Pnmaclhw of setsoov*setcr0*reg*reg*reg + | `Pnmaclhws of setsoov*setcr0*reg*reg*reg + | `Picbi of reg*reg + | `Picbt of k*reg*reg + | `Pdcba of reg*reg + | `Pdcbt of reg*reg*k + | `Pdcbtst of reg*reg*k + | `Pdcbz of reg*reg + | `Pdcbst of reg*reg + | `Pdcbf of reg*reg*k + | `Pisync + | `Plbarx of reg*reg*reg*k + | `Plharx of reg*reg*reg*k + | `Plwarx of reg*reg*reg*k + | `Pstbcx of reg*reg*reg + | `Psthcx of reg*reg*reg + | `Pstwcx of reg*reg*reg + | `Pldarx of reg*reg*reg*k + | `Pstdcx of reg*reg*reg + | `Psync of k + | `Peieio + | `Pwait of k diff --git a/old/power/gen/compile.gen b/old/power/gen/compile.gen new file mode 100644 index 00000000..d0af6e38 --- /dev/null +++ b/old/power/gen/compile.gen @@ -0,0 +1,2257 @@ +| `Pb (DontSetAA,DontSetLK,target_addr) -> + { empty_ins with + memo=sprintf "b %i" target_addr; + inputs=[]; + outputs=[]; }::k +| `Pb (SetAA,DontSetLK,target_addr) -> + { empty_ins with + memo=sprintf "ba %i" target_addr; + inputs=[]; + outputs=[]; }::k +| `Pb (DontSetAA,SetLK,target_addr) -> + { empty_ins with + memo=sprintf "bl %i" target_addr; + inputs=[]; + outputs=[]; }::k +| `Pb (SetAA,SetLK,target_addr) -> + { empty_ins with + memo=sprintf "bla %i" target_addr; + inputs=[]; + outputs=[]; }::k +| `Pbc (DontSetAA,DontSetLK,bO,bI,target_addr) -> + { empty_ins with + memo=sprintf "bc %i,%i,%i" bO bI target_addr; + inputs=[]; + outputs=[]; }::k +| `Pbc (SetAA,DontSetLK,bO,bI,target_addr) -> + { empty_ins with + memo=sprintf "bca %i,%i,%i" bO bI target_addr; + inputs=[]; + outputs=[]; }::k +| `Pbc (DontSetAA,SetLK,bO,bI,target_addr) -> + { empty_ins with + memo=sprintf "bcl %i,%i,%i" bO bI target_addr; + inputs=[]; + outputs=[]; }::k +| `Pbc (SetAA,SetLK,bO,bI,target_addr) -> + { empty_ins with + memo=sprintf "bcla %i,%i,%i" bO bI target_addr; + inputs=[]; + outputs=[]; }::k +| `Pbclr (DontSetLK,bO,bI,bH) -> + { empty_ins with + memo=sprintf "bclr %i,%i,%i" bO bI bH; + inputs=[]; + outputs=[]; }::k +| `Pbclr (SetLK,bO,bI,bH) -> + { empty_ins with + memo=sprintf "bclrl %i,%i,%i" bO bI bH; + inputs=[]; + outputs=[]; }::k +| `Pbcctr (DontSetLK,bO,bI,bH) -> + { empty_ins with + memo=sprintf "bcctr %i,%i,%i" bO bI bH; + inputs=[]; + outputs=[]; }::k +| `Pbcctr (SetLK,bO,bI,bH) -> + { empty_ins with + memo=sprintf "bcctrl %i,%i,%i" bO bI bH; + inputs=[]; + outputs=[]; }::k +| `Pcrand (bT,bA,bB) -> + { empty_ins with + memo=sprintf "crand %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcrnand (bT,bA,bB) -> + { empty_ins with + memo=sprintf "crnand %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcror (bT,bA,bB) -> + { empty_ins with + memo=sprintf "cror %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcrxor (bT,bA,bB) -> + { empty_ins with + memo=sprintf "crxor %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcrnor (bT,bA,bB) -> + { empty_ins with + memo=sprintf "crnor %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcreqv (bT,bA,bB) -> + { empty_ins with + memo=sprintf "creqv %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcrandc (bT,bA,bB) -> + { empty_ins with + memo=sprintf "crandc %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pcrorc (bT,bA,bB) -> + { empty_ins with + memo=sprintf "crorc %i,%i,%i" bT bA bB; + inputs=[]; + outputs=[]; }::k +| `Pmcrf (bF,bFA) -> + { empty_ins with + memo=sprintf "mcrf %i,%i" bF bFA; + inputs=[]; + outputs=[]; }::k +| `Psc (lEV) -> + { empty_ins with + memo=sprintf "sc %i" lEV; + inputs=[]; + outputs=[]; }::k +| `Pscv (lEV) -> + { empty_ins with + memo=sprintf "scv %i" lEV; + inputs=[]; + outputs=[]; }::k +| `Plbz (rT,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lbz ^o0,%i(0)" d + else sprintf "lbz ^o0,%i(^i0)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Plbzx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lbzx ^o0,0,^i0" + else sprintf "lbzx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plbzu (rT,d,rA) -> + { empty_ins with + memo=sprintf "lbzu ^o0,%i(^i0)" d; + inputs=[rA]; + outputs=[rT; rA]; }::k +| `Plbzux (rT,rA,rB) -> + { empty_ins with + memo=sprintf "lbzux ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT; rA]; }::k +| `Plhz (rT,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lhz ^o0,%i(0)" d + else sprintf "lhz ^o0,%i(^i0)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Plhzx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lhzx ^o0,0,^i0" + else sprintf "lhzx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plhzu (rT,d,rA) -> + { empty_ins with + memo=sprintf "lhzu ^o0,%i(^i0)" d; + inputs=[rA]; + outputs=[rT; rA]; }::k +| `Plhzux (rT,rA,rB) -> + { empty_ins with + memo=sprintf "lhzux ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT; rA]; }::k +| `Plha (rT,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lha ^o0,%i(0)" d + else sprintf "lha ^o0,%i(^i0)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Plhax (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lhax ^o0,0,^i0" + else sprintf "lhax ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plhau (rT,d,rA) -> + { empty_ins with + memo=sprintf "lhau ^o0,%i(^i0)" d; + inputs=[rA]; + outputs=[rT; rA]; }::k +| `Plhaux (rT,rA,rB) -> + { empty_ins with + memo=sprintf "lhaux ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT; rA]; }::k +| `Plwz (rT,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lwz ^o0,%i(0)" d + else sprintf "lwz ^o0,%i(^i0)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Plwzx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lwzx ^o0,0,^i0" + else sprintf "lwzx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plwzu (rT,d,rA) -> + { empty_ins with + memo=sprintf "lwzu ^o0,%i(^i0)" d; + inputs=[rA]; + outputs=[rT; rA]; }::k +| `Plwzux (rT,rA,rB) -> + { empty_ins with + memo=sprintf "lwzux ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT; rA]; }::k +| `Plwa (rT,dS,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lwa ^o0,%i(0)" (dS lsr 2) + else sprintf "lwa ^o0,%i(^i0)" (dS lsr 2); + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Plwax (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lwax ^o0,0,^i0" + else sprintf "lwax ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plwaux (rT,rA,rB) -> + { empty_ins with + memo=sprintf "lwaux ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT; rA]; }::k +| `Pld (rT,dS,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "ld ^o0,%i(0)" (dS lsr 2) + else sprintf "ld ^o0,%i(^i0)" (dS lsr 2); + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Pldx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "ldx ^o0,0,^i0" + else sprintf "ldx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pldu (rT,dS,rA) -> + { empty_ins with + memo=sprintf "ldu ^o0,%i(^i0)" (dS lsr 2); + inputs=[rA]; + outputs=[rT; rA]; }::k +| `Pldux (rT,rA,rB) -> + { empty_ins with + memo=sprintf "ldux ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT; rA]; }::k +| `Pstb (rS,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stb ^i0,%i(0)" d + else sprintf "stb ^i0,%i(^i1)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [rS] else [rS; rA]); + outputs=[]; }::k +| `Pstbx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stbx ^i0,0,^i1" + else sprintf "stbx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Pstbu (rS,d,rA) -> + { empty_ins with + memo=sprintf "stbu ^i0,%i(^i1)" d; + inputs=[rS; rA]; + outputs=[rA]; }::k +| `Pstbux (rS,rA,rB) -> + { empty_ins with + memo=sprintf "stbux ^i0,^i1,^i2" ; + inputs=[rS; rA; rB]; + outputs=[rA]; }::k +| `Psth (rS,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "sth ^i0,%i(0)" d + else sprintf "sth ^i0,%i(^i1)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [rS] else [rS; rA]); + outputs=[]; }::k +| `Psthx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "sthx ^i0,0,^i1" + else sprintf "sthx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Psthu (rS,d,rA) -> + { empty_ins with + memo=sprintf "sthu ^i0,%i(^i1)" d; + inputs=[rS; rA]; + outputs=[rA]; }::k +| `Psthux (rS,rA,rB) -> + { empty_ins with + memo=sprintf "sthux ^i0,^i1,^i2" ; + inputs=[rS; rA; rB]; + outputs=[rA]; }::k +| `Pstw (rS,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stw ^i0,%i(0)" d + else sprintf "stw ^i0,%i(^i1)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [rS] else [rS; rA]); + outputs=[]; }::k +| `Pstwx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stwx ^i0,0,^i1" + else sprintf "stwx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Pstwu (rS,d,rA) -> + { empty_ins with + memo=sprintf "stwu ^i0,%i(^i1)" d; + inputs=[rS; rA]; + outputs=[rA]; }::k +| `Pstwux (rS,rA,rB) -> + { empty_ins with + memo=sprintf "stwux ^i0,^i1,^i2" ; + inputs=[rS; rA; rB]; + outputs=[rA]; }::k +| `Pstd (rS,dS,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "std ^i0,%i(0)" (dS lsr 2) + else sprintf "std ^i0,%i(^i1)" (dS lsr 2); + inputs= + (if rA = A.Ireg A.GPR0 then [rS] else [rS; rA]); + outputs=[]; }::k +| `Pstdx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stdx ^i0,0,^i1" + else sprintf "stdx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Pstdu (rS,dS,rA) -> + { empty_ins with + memo=sprintf "stdu ^i0,%i(^i1)" (dS lsr 2); + inputs=[rS; rA]; + outputs=[rA]; }::k +| `Pstdux (rS,rA,rB) -> + { empty_ins with + memo=sprintf "stdux ^i0,^i1,^i2" ; + inputs=[rS; rA; rB]; + outputs=[rA]; }::k +| `Plq (rTp,dQ,rA,pT) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lq %i,%i(0),%i" rTp dQ pT + else sprintf "lq %i,%i(^i0),%i" rTp dQ pT; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rA]; }::k +| `Pstq (rSp,dS,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stq %i,%i(0)" rSp (dS lsr 2) + else sprintf "stq %i,%i(^i0)" rSp (dS lsr 2); + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[]; }::k +| `Plhbrx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lhbrx ^o0,0,^i0" + else sprintf "lhbrx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Psthbrx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "sthbrx ^i0,0,^i1" + else sprintf "sthbrx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Plwbrx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lwbrx ^o0,0,^i0" + else sprintf "lwbrx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pstwbrx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stwbrx ^i0,0,^i1" + else sprintf "stwbrx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Pldbrx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "ldbrx ^o0,0,^i0" + else sprintf "ldbrx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pstdbrx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stdbrx ^i0,0,^i1" + else sprintf "stdbrx ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rS; rB] else [rS; rA; rB]); + outputs=[]; }::k +| `Plmw (rT,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lmw ^o0,%i(0)" d + else sprintf "lmw ^o0,%i(^i0)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[] @ (A.regs_interval rT); }::k +| `Pstmw (rS,d,rA) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stmw ^i0,%i(0)" d + else sprintf "stmw ^i1,%i(^i0)" d; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]) @ (A.regs_interval rS); + outputs=[]; }::k +| `Plswi (rT,rA,nB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lswi %i,0,%i" rT nB + else sprintf "lswi %i,^i0,%i" rT nB; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[]; }::k +| `Plswx (rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lswx ^o0,0,^i0" + else sprintf "lswx ^o0,^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pstswi (rS,rA,nB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stswi %i,0,%i" rS nB + else sprintf "stswi %i,^i0,%i" rS nB; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[]; }::k +| `Pstswx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stswx %i,0,^i0" rS + else sprintf "stswx %i,^i0,^i1" rS; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[]; }::k +| `Paddi (rT,rA,sI) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "addi ^o0,0,%i" sI + else sprintf "addi ^o0,^i0,%i" sI; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Paddis (rT,rA,sI) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "addis ^o0,0,%i" sI + else sprintf "addis ^o0,^i0,%i" sI; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA]); + outputs=[rT]; }::k +| `Padd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "add ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padd (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "add. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padd (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padd (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubf (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subf ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubf (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subf. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubf (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubf (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Paddic (rT,rA,sI) -> + { empty_ins with + memo=sprintf "addic ^o0,^i0,%i" sI; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddicdot (rT,rA,sI) -> + { empty_ins with + memo=sprintf "addic. ^o0,^i0,%i" sI; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfic (rT,rA,sI) -> + { empty_ins with + memo=sprintf "subfic ^o0,^i0,%i" sI; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addc ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Paddc (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addc. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Paddc (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addco ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Paddc (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addco. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfc ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfc (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfc. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfc (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfco ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfc (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfco. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "adde ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padde (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "adde. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padde (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addeo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Padde (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "addeo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfe ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfe (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfe. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfe (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfeo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Psubfe (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "subfeo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Paddme (DontSetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addme ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddme (DontSetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addme. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddme (SetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addmeo ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddme (SetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addmeo. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfme (DontSetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfme ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfme (DontSetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfme. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfme (SetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfmeo ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfme (SetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfmeo. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddze (DontSetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addze ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddze (DontSetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addze. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddze (SetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addzeo ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Paddze (SetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "addzeo. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfze (DontSetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfze ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfze (DontSetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfze. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfze (SetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfzeo ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Psubfze (SetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "subfzeo. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Pneg (DontSetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "neg ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Pneg (DontSetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "neg. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Pneg (SetSOOV,DontSetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "nego ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Pneg (SetSOOV,SetCR0,rT,rA) -> + { empty_ins with + memo=sprintf "nego. ^o0,^i0" ; + inputs=[rA]; + outputs=[rT]; }::k +| `Pmulli (rT,rA,sI) -> + { empty_ins with + memo=sprintf "mulli ^o0,^i0,%i" sI; + inputs=[rA]; + outputs=[rT]; }::k +| `Pmullw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mullw ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmullw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mullw. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmullw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mullwo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmullw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mullwo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhw (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhw ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhw (SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhw. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhwu (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhwu ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhwu (SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhwu. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divw ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divw. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwu ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwu. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwuo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwuo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwe ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwe (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divwe. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwe (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divweo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivwe (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divweo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivweu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divweu ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivweu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divweu. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivweu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divweuo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivweu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divweuo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulld (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulld ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulld (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulld. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulld (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulldo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulld (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulldo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhd (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhd ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhd (SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhd. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhdu (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhdu ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmulhdu (SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "mulhdu. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divd ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivd (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divd. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivd (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivd (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdu ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdu. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divduo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divduo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divde ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivde (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divde. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivde (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdeo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivde (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdeo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdeu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdeu ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdeu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdeu. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdeu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdeuo ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pdivdeu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo=sprintf "divdeuo. ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pcmpi (bF,l,rA,sI) -> + { empty_ins with + memo=sprintf "cmpi %i,%i,^i0,%i" bF l sI; + inputs=[rA]; + outputs=[]; }::k +| `Pcmp (bF,l,rA,rB) -> + { empty_ins with + memo=sprintf "cmp %i,%i,^i0,^i1" bF l; + inputs=[rA; rB]; + outputs=[]; }::k +| `Pcmpli (bF,l,rA,uI) -> + { empty_ins with + memo=sprintf "cmpli %i,%i,^i0,%i" bF l uI; + inputs=[rA]; + outputs=[]; }::k +| `Pcmpl (bF,l,rA,rB) -> + { empty_ins with + memo=sprintf "cmpl %i,%i,^i0,^i1" bF l; + inputs=[rA; rB]; + outputs=[]; }::k +| `Pisel (rT,rA,rB,bC) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "isel ^o0,0,^i0,%i" bC + else sprintf "isel ^o0,^i0,^i1,%i" bC; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pandi (rA,rS,uI) -> + { empty_ins with + memo=sprintf "andi. ^o0,^i0,%i" uI; + inputs=[rS]; + outputs=[rA]; }::k +| `Pandis (rA,rS,uI) -> + { empty_ins with + memo=sprintf "andis. ^o0,^i0,%i" uI; + inputs=[rS]; + outputs=[rA]; }::k +| `Pori (rA,rS,uI) -> + { empty_ins with + memo=sprintf "ori ^o0,^i0,%i" uI; + inputs=[rS]; + outputs=[rA]; }::k +| `Poris (rA,rS,uI) -> + { empty_ins with + memo=sprintf "oris ^o0,^i0,%i" uI; + inputs=[rS]; + outputs=[rA]; }::k +| `Pxori (rA,rS,uI) -> + { empty_ins with + memo=sprintf "xori ^o0,^i0,%i" uI; + inputs=[rS]; + outputs=[rA]; }::k +| `Pxoris (rA,rS,uI) -> + { empty_ins with + memo=sprintf "xoris ^o0,^i0,%i" uI; + inputs=[rS]; + outputs=[rA]; }::k +| `Pand (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "and ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pand (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "and. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pxor (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "xor ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pxor (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "xor. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pnand (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "nand ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pnand (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "nand. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Por (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "or ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Por (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "or. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pnor (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "nor ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pnor (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "nor. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Peqv (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "eqv ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Peqv (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "eqv. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pandc (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "andc ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pandc (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "andc. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Porc (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "orc ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Porc (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "orc. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pextsb (DontSetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "extsb ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pextsb (SetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "extsb. ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pextsh (DontSetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "extsh ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pextsh (SetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "extsh. ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pcntlzw (DontSetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "cntlzw ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pcntlzw (SetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "cntlzw. ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pcmpb (rA,rS,rB) -> + { empty_ins with + memo=sprintf "cmpb ^o0,%i,^i0" rS; + inputs=[rB]; + outputs=[rA]; }::k +| `Ppopcntb (rA,rS) -> + { empty_ins with + memo=sprintf "popcntb ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Ppopcntw (rA,rS) -> + { empty_ins with + memo=sprintf "popcntw ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pprtyd (rA,rS) -> + { empty_ins with + memo=sprintf "prtyd ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pprtyw (rA,rS) -> + { empty_ins with + memo=sprintf "prtyw ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pextsw (DontSetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "extsw ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pextsw (SetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "extsw. ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pcntlzd (DontSetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "cntlzd ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pcntlzd (SetCR0,rA,rS) -> + { empty_ins with + memo=sprintf "cntlzd. ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Ppopcntd (rA,rS) -> + { empty_ins with + memo=sprintf "popcntd ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pbpermd (rA,rS,rB) -> + { empty_ins with + memo=sprintf "bpermd ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prlwinm (DontSetCR0,rA,rS,sH,mB,mE) -> + { empty_ins with + memo=sprintf "rlwinm ^o0,^i0,%i,%i,%i" sH mB mE; + inputs=[rS]; + outputs=[rA]; }::k +| `Prlwinm (SetCR0,rA,rS,sH,mB,mE) -> + { empty_ins with + memo=sprintf "rlwinm. ^o0,^i0,%i,%i,%i" sH mB mE; + inputs=[rS]; + outputs=[rA]; }::k +| `Prlwnm (DontSetCR0,rA,rS,rB,mB,mE) -> + { empty_ins with + memo=sprintf "rlwnm ^o0,^i0,^i1,%i,%i" mB mE; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prlwnm (SetCR0,rA,rS,rB,mB,mE) -> + { empty_ins with + memo=sprintf "rlwnm. ^o0,^i0,^i1,%i,%i" mB mE; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prlwimi (DontSetCR0,rA,rS,sH,mB,mE) -> + { empty_ins with + memo=sprintf "rlwimi ^i0,^i1,%i,%i,%i" sH mB mE; + inputs=[rA; rS]; + outputs=[rA]; }::k +| `Prlwimi (SetCR0,rA,rS,sH,mB,mE) -> + { empty_ins with + memo=sprintf "rlwimi. ^i0,^i1,%i,%i,%i" sH mB mE; + inputs=[rA; rS]; + outputs=[rA]; }::k +| `Prldicl (DontSetCR0,rA,rS,sH,mB) -> + { empty_ins with + memo=sprintf "rldicl ^o0,^i0,%i,%i" sH mB; + inputs=[rS]; + outputs=[rA]; }::k +| `Prldicl (SetCR0,rA,rS,sH,mB) -> + { empty_ins with + memo=sprintf "rldicl. ^o0,^i0,%i,%i" sH mB; + inputs=[rS]; + outputs=[rA]; }::k +| `Prldicr (DontSetCR0,rA,rS,sH,mE) -> + { empty_ins with + memo=sprintf "rldicr ^o0,^i0,%i,%i" sH mE; + inputs=[rS]; + outputs=[rA]; }::k +| `Prldicr (SetCR0,rA,rS,sH,mE) -> + { empty_ins with + memo=sprintf "rldicr. ^o0,^i0,%i,%i" sH mE; + inputs=[rS]; + outputs=[rA]; }::k +| `Prldic (DontSetCR0,rA,rS,sH,mB) -> + { empty_ins with + memo=sprintf "rldic ^o0,^i0,%i,%i" sH mB; + inputs=[rS]; + outputs=[rA]; }::k +| `Prldic (SetCR0,rA,rS,sH,mB) -> + { empty_ins with + memo=sprintf "rldic. ^o0,^i0,%i,%i" sH mB; + inputs=[rS]; + outputs=[rA]; }::k +| `Prldcl (DontSetCR0,rA,rS,rB,mB) -> + { empty_ins with + memo=sprintf "rldcl ^o0,^i0,^i1,%i" mB; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prldcl (SetCR0,rA,rS,rB,mB) -> + { empty_ins with + memo=sprintf "rldcl. ^o0,^i0,^i1,%i" mB; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prldcr (DontSetCR0,rA,rS,rB,mE) -> + { empty_ins with + memo=sprintf "rldcr ^o0,^i0,^i1,%i" mE; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prldcr (SetCR0,rA,rS,rB,mE) -> + { empty_ins with + memo=sprintf "rldcr. ^o0,^i0,^i1,%i" mE; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Prldimi (DontSetCR0,rA,rS,sH,mB) -> + { empty_ins with + memo=sprintf "rldimi ^i0,^i1,%i,%i" sH mB; + inputs=[rA; rS]; + outputs=[rA]; }::k +| `Prldimi (SetCR0,rA,rS,sH,mB) -> + { empty_ins with + memo=sprintf "rldimi. ^i0,^i1,%i,%i" sH mB; + inputs=[rA; rS]; + outputs=[rA]; }::k +| `Pslw (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "slw ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pslw (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "slw. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psrw (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "srw ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psrw (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "srw. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psrawi (DontSetCR0,rA,rS,sH) -> + { empty_ins with + memo=sprintf "srawi ^o0,^i0,%i" sH; + inputs=[rS]; + outputs=[rA]; }::k +| `Psrawi (SetCR0,rA,rS,sH) -> + { empty_ins with + memo=sprintf "srawi. ^o0,^i0,%i" sH; + inputs=[rS]; + outputs=[rA]; }::k +| `Psraw (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "sraw ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psraw (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "sraw. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psld (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "sld ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psld (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "sld. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psrd (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "srd ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psrd (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "srd. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psradi (DontSetCR0,rA,rS,sH) -> + { empty_ins with + memo=sprintf "sradi ^o0,^i0,%i" sH; + inputs=[rS]; + outputs=[rA]; }::k +| `Psradi (SetCR0,rA,rS,sH) -> + { empty_ins with + memo=sprintf "sradi. ^o0,^i0,%i" sH; + inputs=[rS]; + outputs=[rA]; }::k +| `Psrad (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "srad ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Psrad (SetCR0,rA,rS,rB) -> + { empty_ins with + memo=sprintf "srad. ^o0,^i0,^i1" ; + inputs=[rS; rB]; + outputs=[rA]; }::k +| `Pcdtbcd (rA,rS) -> + { empty_ins with + memo=sprintf "cdtbcd ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Pcbcdtd (rA,rS) -> + { empty_ins with + memo=sprintf "cbcdtd ^o0,^i0" ; + inputs=[rS]; + outputs=[rA]; }::k +| `Paddg6s (rT,rA,rB) -> + { empty_ins with + memo=sprintf "addg6s ^o0,^i0,^i1" ; + inputs=[rA; rB]; + outputs=[rT]; }::k +| `Pmtspr (sPR,rS) -> + { empty_ins with + memo=sprintf "mtspr %i,^i0" sPR; + inputs=[rS]; + outputs=[]; }::k +| `Pmfspr (rT,sPR) -> + { empty_ins with + memo=sprintf "mfspr ^o0,%i" sPR; + inputs=[]; + outputs=[rT]; }::k +| `Pmtcrf (fXM,rS) -> + { empty_ins with + memo=sprintf "mtcrf %i,^i0" fXM; + inputs=[rS]; + outputs=[]; }::k +| `Pmfcr (rT) -> + { empty_ins with + memo=sprintf "mfcr ^o0" ; + inputs=[]; + outputs=[rT]; }::k +| `Pmtocrf (fXM,rS) -> + { empty_ins with + memo=sprintf "mtocrf %i,^i0" fXM; + inputs=[rS]; + outputs=[]; }::k +| `Pmfocrf (rT,fXM) -> + { empty_ins with + memo=sprintf "mfocrf ^o0,%i" fXM; + inputs=[]; + outputs=[rT]; }::k +| `Pmcrxr (bF) -> + { empty_ins with + memo=sprintf "mcrxr %i" bF; + inputs=[]; + outputs=[]; }::k +| `Pdlmzb (DontSetCR0,rA,rS,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dlmzb 0,^o1,^o2" + else sprintf "dlmzb ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rS; rB]); + outputs=[rA; rS; rB]; }::k +| `Pdlmzb (SetCR0,rA,rS,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dlmzb. 0,^o1,^o2" + else sprintf "dlmzb. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rS; rB]); + outputs=[rA; rS; rB]; }::k +| `Pmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchw ^o0,0,^o2" + else sprintf "macchw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchw. ^o0,0,^o2" + else sprintf "macchw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwo ^o0,0,^o2" + else sprintf "macchwo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwo. ^o0,0,^o2" + else sprintf "macchwo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchws ^o0,0,^o2" + else sprintf "macchws ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchws. ^o0,0,^o2" + else sprintf "macchws. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwso ^o0,0,^o2" + else sprintf "macchwso ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchws (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwso. ^o0,0,^o2" + else sprintf "macchwso. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwu ^o0,0,^o2" + else sprintf "macchwu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwu. ^o0,0,^o2" + else sprintf "macchwu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwuo ^o0,0,^o2" + else sprintf "macchwuo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwuo. ^o0,0,^o2" + else sprintf "macchwuo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwsu ^o0,0,^o2" + else sprintf "macchwsu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwsu. ^o0,0,^o2" + else sprintf "macchwsu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwsuo ^o0,0,^o2" + else sprintf "macchwsuo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmacchwsu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "macchwsuo. ^o0,0,^o2" + else sprintf "macchwsuo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhw ^o0,0,^o2" + else sprintf "machhw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhw. ^o0,0,^o2" + else sprintf "machhw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwo ^o0,0,^o2" + else sprintf "machhwo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwo. ^o0,0,^o2" + else sprintf "machhwo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhws ^o0,0,^o2" + else sprintf "machhws ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhws. ^o0,0,^o2" + else sprintf "machhws. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwso ^o0,0,^o2" + else sprintf "machhwso ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhws (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwso. ^o0,0,^o2" + else sprintf "machhwso. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwu ^o0,0,^o2" + else sprintf "machhwu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwu. ^o0,0,^o2" + else sprintf "machhwu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwuo ^o0,0,^o2" + else sprintf "machhwuo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwuo. ^o0,0,^o2" + else sprintf "machhwuo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwsu ^o0,0,^o2" + else sprintf "machhwsu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwsu. ^o0,0,^o2" + else sprintf "machhwsu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwsuo ^o0,0,^o2" + else sprintf "machhwsuo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmachhwsu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "machhwsuo. ^o0,0,^o2" + else sprintf "machhwsuo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhw ^o0,0,^o2" + else sprintf "maclhw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhw. ^o0,0,^o2" + else sprintf "maclhw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwo ^o0,0,^o2" + else sprintf "maclhwo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwo. ^o0,0,^o2" + else sprintf "maclhwo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhws ^o0,0,^o2" + else sprintf "maclhws ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhws. ^o0,0,^o2" + else sprintf "maclhws. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwso ^o0,0,^o2" + else sprintf "maclhwso ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwso. ^o0,0,^o2" + else sprintf "maclhwso. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwu ^o0,0,^o2" + else sprintf "maclhwu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwu. ^o0,0,^o2" + else sprintf "maclhwu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwuo ^o0,0,^o2" + else sprintf "maclhwuo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwuo. ^o0,0,^o2" + else sprintf "maclhwuo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwsu ^o0,0,^o2" + else sprintf "maclhwsu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwsu. ^o0,0,^o2" + else sprintf "maclhwsu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwsuo ^o0,0,^o2" + else sprintf "maclhwsuo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmaclhwsu (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "maclhwsuo. ^o0,0,^o2" + else sprintf "maclhwsuo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulchw (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulchw ^o0,0,^o2" + else sprintf "mulchw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulchw (SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulchw. ^o0,0,^o2" + else sprintf "mulchw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulchwu (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulchwu ^o0,0,^o2" + else sprintf "mulchwu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulchwu (SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulchwu. ^o0,0,^o2" + else sprintf "mulchwu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulhhw (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulhhw ^o0,0,^o2" + else sprintf "mulhhw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulhhw (SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulhhw. ^o0,0,^o2" + else sprintf "mulhhw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulhhwu (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulhhwu ^o0,0,^o2" + else sprintf "mulhhwu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmulhhwu (SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mulhhwu. ^o0,0,^o2" + else sprintf "mulhhwu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmullhw (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mullhw ^o0,0,^o2" + else sprintf "mullhw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmullhw (SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mullhw. ^o0,0,^o2" + else sprintf "mullhw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmullhwu (DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mullhwu ^o0,0,^o2" + else sprintf "mullhwu ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pmullhwu (SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "mullhwu. ^o0,0,^o2" + else sprintf "mullhwu. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchw ^o0,0,^o2" + else sprintf "nmacchw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchw. ^o0,0,^o2" + else sprintf "nmacchw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchwo ^o0,0,^o2" + else sprintf "nmacchwo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchwo. ^o0,0,^o2" + else sprintf "nmacchwo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchws ^o0,0,^o2" + else sprintf "nmacchws ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchws. ^o0,0,^o2" + else sprintf "nmacchws. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchwso ^o0,0,^o2" + else sprintf "nmacchwso ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmacchws (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmacchwso. ^o0,0,^o2" + else sprintf "nmacchwso. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhw ^o0,0,^o2" + else sprintf "nmachhw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhw. ^o0,0,^o2" + else sprintf "nmachhw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhwo ^o0,0,^o2" + else sprintf "nmachhwo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhwo. ^o0,0,^o2" + else sprintf "nmachhwo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhws ^o0,0,^o2" + else sprintf "nmachhws ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhws. ^o0,0,^o2" + else sprintf "nmachhws. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhwso ^o0,0,^o2" + else sprintf "nmachhwso ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmachhws (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmachhwso. ^o0,0,^o2" + else sprintf "nmachhwso. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhw ^o0,0,^o2" + else sprintf "nmaclhw ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhw. ^o0,0,^o2" + else sprintf "nmaclhw. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhwo ^o0,0,^o2" + else sprintf "nmaclhwo ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhwo. ^o0,0,^o2" + else sprintf "nmaclhwo. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhws ^o0,0,^o2" + else sprintf "nmaclhws ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhws. ^o0,0,^o2" + else sprintf "nmaclhws. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhwso ^o0,0,^o2" + else sprintf "nmaclhwso ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Pnmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "nmaclhwso. ^o0,0,^o2" + else sprintf "nmaclhwso. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rT; rA; rB]); + outputs=[rT; rA; rB]; }::k +| `Picbi (rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "icbi 0,^o1" + else sprintf "icbi ^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Picbt (cT,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "icbt %i,0,^o1" cT + else sprintf "icbt %i,^i0,^i1" cT; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pdcba (rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dcba 0,^o1" + else sprintf "dcba ^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pdcbt (rA,rB,tH) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dcbt 0,^o1,%i" tH + else sprintf "dcbt ^i0,^i1,%i" tH; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pdcbtst (rA,rB,tH) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dcbtst 0,^o1,%i" tH + else sprintf "dcbtst ^i0,^i1,%i" tH; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pdcbz (rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dcbz 0,^o1" + else sprintf "dcbz ^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pdcbst (rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dcbst 0,^o1" + else sprintf "dcbst ^i0,^i1" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pdcbf (rA,rB,l) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "dcbf 0,^o1,%i" l + else sprintf "dcbf ^i0,^i1,%i" l; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rA; rB]); + outputs=[rA; rB]; }::k +| `Pisync -> + { empty_ins with + memo=sprintf "isync " ; + inputs=[]; + outputs=[]; }::k +| `Plbarx (rT,rA,rB,eH) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lbarx ^o0,0,^i0,%i" eH + else sprintf "lbarx ^o0,^i0,^i1,%i" eH; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plharx (rT,rA,rB,eH) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lharx ^o0,0,^i0,%i" eH + else sprintf "lharx ^o0,^i0,^i1,%i" eH; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Plwarx (rT,rA,rB,eH) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "lwarx ^o0,0,^i0,%i" eH + else sprintf "lwarx ^o0,^i0,^i1,%i" eH; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pstbcx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stbcx. ^o0,0,^o2" + else sprintf "stbcx. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rS; rA; rB]); + outputs=[rS; rA; rB]; }::k +| `Psthcx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "sthcx. ^o0,0,^o2" + else sprintf "sthcx. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rS; rA; rB]); + outputs=[rS; rA; rB]; }::k +| `Pstwcx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stwcx. ^o0,0,^o2" + else sprintf "stwcx. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rS; rA; rB]); + outputs=[rS; rA; rB]; }::k +| `Pldarx (rT,rA,rB,eH) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "ldarx ^o0,0,^i0,%i" eH + else sprintf "ldarx ^o0,^i0,^i1,%i" eH; + inputs= + (if rA = A.Ireg A.GPR0 then [rB] else [rA; rB]); + outputs=[rT]; }::k +| `Pstdcx (rS,rA,rB) -> + { empty_ins with + memo= if rA = A.Ireg A.GPR0 + then sprintf "stdcx. ^o0,0,^o2" + else sprintf "stdcx. ^i0,^i1,^i2" ; + inputs= + (if rA = A.Ireg A.GPR0 then [] else [rS; rA; rB]); + outputs=[rS; rA; rB]; }::k +| `Psync (l) -> + { empty_ins with + memo=sprintf "sync %i" l; + inputs=[]; + outputs=[]; }::k +| `Peieio -> + { empty_ins with + memo=sprintf "eieio " ; + inputs=[]; + outputs=[]; }::k +| `Pwait (wC) -> + { empty_ins with + memo=sprintf "wait %i" wC; + inputs=[]; + outputs=[]; }::k diff --git a/old/power/gen/fold.gen b/old/power/gen/fold.gen new file mode 100644 index 00000000..acec75ac --- /dev/null +++ b/old/power/gen/fold.gen @@ -0,0 +1,368 @@ +| `Pb (DontSetAA,DontSetLK,target_addr) -> y_reg, y_sreg +| `Pb (SetAA,DontSetLK,target_addr) -> y_reg, y_sreg +| `Pb (DontSetAA,SetLK,target_addr) -> y_reg, y_sreg +| `Pb (SetAA,SetLK,target_addr) -> y_reg, y_sreg +| `Pbc (DontSetAA,DontSetLK,bO,bI,target_addr) -> y_reg, y_sreg +| `Pbc (SetAA,DontSetLK,bO,bI,target_addr) -> y_reg, y_sreg +| `Pbc (DontSetAA,SetLK,bO,bI,target_addr) -> y_reg, y_sreg +| `Pbc (SetAA,SetLK,bO,bI,target_addr) -> y_reg, y_sreg +| `Pbclr (DontSetLK,bO,bI,bH) -> y_reg, y_sreg +| `Pbclr (SetLK,bO,bI,bH) -> y_reg, y_sreg +| `Pbcctr (DontSetLK,bO,bI,bH) -> y_reg, y_sreg +| `Pbcctr (SetLK,bO,bI,bH) -> y_reg, y_sreg +| `Pcrand (bT,bA,bB) -> y_reg, y_sreg +| `Pcrnand (bT,bA,bB) -> y_reg, y_sreg +| `Pcror (bT,bA,bB) -> y_reg, y_sreg +| `Pcrxor (bT,bA,bB) -> y_reg, y_sreg +| `Pcrnor (bT,bA,bB) -> y_reg, y_sreg +| `Pcreqv (bT,bA,bB) -> y_reg, y_sreg +| `Pcrandc (bT,bA,bB) -> y_reg, y_sreg +| `Pcrorc (bT,bA,bB) -> y_reg, y_sreg +| `Pmcrf (bF,bFA) -> y_reg, y_sreg +| `Psc (lEV) -> y_reg, y_sreg +| `Pscv (lEV) -> y_reg, y_sreg +| `Plbz (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plbzx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plbzu (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plbzux (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plhz (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plhzx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plhzu (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plhzux (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plha (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plhax (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plhau (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plhaux (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plwz (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plwzx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plwzu (rT,d,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plwzux (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plwa (rT,dS,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Plwax (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plwaux (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pld (rT,dS,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pldx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pldu (rT,dS,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pldux (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pstb (rS,d,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Pstbx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pstbu (rS,d,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Pstbux (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Psth (rS,d,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Psthx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Psthu (rS,d,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Psthux (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pstw (rS,d,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Pstwx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pstwu (rS,d,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Pstwux (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pstd (rS,dS,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Pstdx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pstdu (rS,dS,rA) -> fold_reg rA (fold_reg rS (y_reg, y_sreg)) +| `Pstdux (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Plq (rTp,dQ,rA,pT) -> fold_reg rA (y_reg, y_sreg) +| `Pstq (rSp,dS,rA) -> fold_reg rA (y_reg, y_sreg) +| `Plhbrx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psthbrx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Plwbrx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pstwbrx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pldbrx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pstdbrx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Plmw (rT,d,rA) -> fold_reg rA (List.fold_right fold_reg (regs_interval rT) (y_reg, y_sreg)) +| `Pstmw (rS,d,rA) -> fold_reg rA (List.fold_right fold_reg (regs_interval rS) (y_reg, y_sreg)) +| `Plswi (rT,rA,nB) -> fold_reg rA (y_reg, y_sreg) +| `Plswx (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pstswi (rS,rA,nB) -> fold_reg rA (y_reg, y_sreg) +| `Pstswx (rS,rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Paddi (rT,rA,sI) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddis (rT,rA,sI) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Padd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padd (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padd (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padd (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubf (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubf (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubf (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubf (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Paddic (rT,rA,sI) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddicdot (rT,rA,sI) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfic (rT,rA,sI) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Paddc (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Paddc (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Paddc (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfc (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfc (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfc (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padde (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padde (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Padde (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfe (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfe (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Psubfe (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Paddme (DontSetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddme (DontSetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddme (SetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddme (SetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfme (DontSetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfme (DontSetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfme (SetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfme (SetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddze (DontSetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddze (DontSetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddze (SetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Paddze (SetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfze (DontSetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfze (DontSetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfze (SetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Psubfze (SetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pneg (DontSetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pneg (DontSetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pneg (SetSOOV,DontSetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pneg (SetSOOV,SetCR0,rT,rA) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pmulli (rT,rA,sI) -> fold_reg rA (fold_reg rT (y_reg, y_sreg)) +| `Pmullw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhw (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhw (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhwu (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhwu (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwe (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwe (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivwe (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivweu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivweu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivweu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivweu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulld (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulld (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulld (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulld (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhd (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhd (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhdu (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhdu (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivd (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivd (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivd (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivde (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivde (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivde (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdeu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdeu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdeu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pdivdeu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pcmpi (bF,l,rA,sI) -> fold_reg rA (y_reg, y_sreg) +| `Pcmp (bF,l,rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pcmpli (bF,l,rA,uI) -> fold_reg rA (y_reg, y_sreg) +| `Pcmpl (bF,l,rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pisel (rT,rA,rB,bC) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pandi (rA,rS,uI) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pandis (rA,rS,uI) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pori (rA,rS,uI) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Poris (rA,rS,uI) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pxori (rA,rS,uI) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pxoris (rA,rS,uI) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pand (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pand (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pxor (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pxor (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pnand (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pnand (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Por (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Por (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pnor (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pnor (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Peqv (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Peqv (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pandc (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pandc (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Porc (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Porc (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pextsb (DontSetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pextsb (SetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pextsh (DontSetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pextsh (SetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pcntlzw (DontSetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pcntlzw (SetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pcmpb (rA,rS,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Ppopcntb (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Ppopcntw (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pprtyd (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pprtyw (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pextsw (DontSetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pextsw (SetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pcntlzd (DontSetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pcntlzd (SetCR0,rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Ppopcntd (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pbpermd (rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prlwinm (DontSetCR0,rA,rS,sH,mB,mE) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prlwinm (SetCR0,rA,rS,sH,mB,mE) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prlwnm (DontSetCR0,rA,rS,rB,mB,mE) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prlwnm (SetCR0,rA,rS,rB,mB,mE) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prlwimi (DontSetCR0,rA,rS,sH,mB,mE) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prlwimi (SetCR0,rA,rS,sH,mB,mE) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldicl (DontSetCR0,rA,rS,sH,mB) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldicl (SetCR0,rA,rS,sH,mB) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldicr (DontSetCR0,rA,rS,sH,mE) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldicr (SetCR0,rA,rS,sH,mE) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldic (DontSetCR0,rA,rS,sH,mB) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldic (SetCR0,rA,rS,sH,mB) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldcl (DontSetCR0,rA,rS,rB,mB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prldcl (SetCR0,rA,rS,rB,mB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prldcr (DontSetCR0,rA,rS,rB,mE) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prldcr (SetCR0,rA,rS,rB,mE) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Prldimi (DontSetCR0,rA,rS,sH,mB) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Prldimi (SetCR0,rA,rS,sH,mB) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pslw (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pslw (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psrw (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psrw (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psrawi (DontSetCR0,rA,rS,sH) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Psrawi (SetCR0,rA,rS,sH) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Psraw (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psraw (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psld (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psld (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psrd (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psrd (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psradi (DontSetCR0,rA,rS,sH) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Psradi (SetCR0,rA,rS,sH) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Psrad (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Psrad (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pcdtbcd (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Pcbcdtd (rA,rS) -> fold_reg rS (fold_reg rA (y_reg, y_sreg)) +| `Paddg6s (rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmtspr (sPR,rS) -> fold_reg rS (y_reg, y_sreg) +| `Pmfspr (rT,sPR) -> fold_reg rT (y_reg, y_sreg) +| `Pmtcrf (fXM,rS) -> fold_reg rS (y_reg, y_sreg) +| `Pmfcr (rT) -> fold_reg rT (y_reg, y_sreg) +| `Pmtocrf (fXM,rS) -> fold_reg rS (y_reg, y_sreg) +| `Pmfocrf (rT,fXM) -> fold_reg rT (y_reg, y_sreg) +| `Pmcrxr (bF) -> y_reg, y_sreg +| `Pdlmzb (DontSetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pdlmzb (SetCR0,rA,rS,rB) -> fold_reg rB (fold_reg rS (fold_reg rA (y_reg, y_sreg))) +| `Pmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchws (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmacchwsu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhws (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmachhwsu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmaclhwsu (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulchw (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulchw (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulchwu (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulchwu (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhhw (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhhw (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhhwu (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmulhhwu (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullhw (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullhw (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullhwu (DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pmullhwu (SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmacchws (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmachhws (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pnmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Picbi (rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Picbt (cT,rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pdcba (rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pdcbt (rA,rB,tH) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pdcbtst (rA,rB,tH) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pdcbz (rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pdcbst (rA,rB) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pdcbf (rA,rB,l) -> fold_reg rB (fold_reg rA (y_reg, y_sreg)) +| `Pisync -> y_reg, y_sreg +| `Plbarx (rT,rA,rB,eH) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plharx (rT,rA,rB,eH) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Plwarx (rT,rA,rB,eH) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pstbcx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Psthcx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pstwcx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Pldarx (rT,rA,rB,eH) -> fold_reg rB (fold_reg rA (fold_reg rT (y_reg, y_sreg))) +| `Pstdcx (rS,rA,rB) -> fold_reg rB (fold_reg rA (fold_reg rS (y_reg, y_sreg))) +| `Psync (l) -> y_reg, y_sreg +| `Peieio -> y_reg, y_sreg +| `Pwait (wC) -> y_reg, y_sreg diff --git a/old/power/gen/herdtools_ast_to_shallow_ast.gen b/old/power/gen/herdtools_ast_to_shallow_ast.gen new file mode 100644 index 00000000..e1de51f7 --- /dev/null +++ b/old/power/gen/herdtools_ast_to_shallow_ast.gen @@ -0,0 +1,1312 @@ + | `Pb(setaa0, setlk1, k2) -> + B + (Sail_values.to_vec0 true (Nat_big_num.of_int 24,Nat_big_num.of_int (trans_li_setaa_setlk_k setaa0 setlk1 k2)), + int_to_bit (trans_aa setaa0), + int_to_bit (trans_lk setlk1)) + + | `Pbc(setaa0, setlk1, k2, k3, k4) -> + Bc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int (trans_bd_setaa_setlk_k_k_k setaa0 setlk1 k2 k3 k4)), + int_to_bit (trans_aa setaa0), + int_to_bit (trans_lk setlk1)) + + | `Pbclr(setlk0, k1, k2, k3) -> + Bclr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2), + Sail_values.to_vec0 true (Nat_big_num.of_int 2,Nat_big_num.of_int k3), + int_to_bit (trans_lk setlk0)) + + | `Pbcctr(setlk0, k1, k2, k3) -> + Bcctr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2), + Sail_values.to_vec0 true (Nat_big_num.of_int 2,Nat_big_num.of_int k3), + int_to_bit (trans_lk setlk0)) + + | `Pcrand(k0, k1, k2) -> + Crand + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcrnand(k0, k1, k2) -> + Crnand + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcror(k0, k1, k2) -> + Cror + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcrxor(k0, k1, k2) -> + Crxor + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcrnor(k0, k1, k2) -> + Crnor + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcreqv(k0, k1, k2) -> + Creqv + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcrandc(k0, k1, k2) -> + Crandc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pcrorc(k0, k1, k2) -> + Crorc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pmcrf(crindex0, k1) -> + Mcrf + (Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int crindex0), + Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int k1)) + + | `Psc(k0) -> + Sc + (Sail_values.to_vec0 true (Nat_big_num.of_int 7,Nat_big_num.of_int k0)) + + | `Pscv(k0) -> + Scv + (Sail_values.to_vec0 true (Nat_big_num.of_int 7,Nat_big_num.of_int k0)) + + | `Plbz(reg0, k1, reg2) -> + Lbz + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plbzx(reg0, reg1, reg2) -> + Lbzx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plbzu(reg0, k1, reg2) -> + Lbzu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plbzux(reg0, reg1, reg2) -> + Lbzux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plhz(reg0, k1, reg2) -> + Lhz + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plhzx(reg0, reg1, reg2) -> + Lhzx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plhzu(reg0, k1, reg2) -> + Lhzu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plhzux(reg0, reg1, reg2) -> + Lhzux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plha(reg0, k1, reg2) -> + Lha + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plhax(reg0, reg1, reg2) -> + Lhax + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plhau(reg0, k1, reg2) -> + Lhau + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plhaux(reg0, reg1, reg2) -> + Lhaux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plwz(reg0, k1, reg2) -> + Lwz + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plwzx(reg0, reg1, reg2) -> + Lwzx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plwzu(reg0, k1, reg2) -> + Lwzu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plwzux(reg0, reg1, reg2) -> + Lwzux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plwa(reg0, ds1, reg2) -> + Lwa + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int ds1)) + + | `Plwax(reg0, reg1, reg2) -> + Lwax + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plwaux(reg0, reg1, reg2) -> + Lwaux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pld(reg0, ds1, reg2) -> + Ld + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int ds1)) + + | `Pldx(reg0, reg1, reg2) -> + Ldx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pldu(reg0, ds1, reg2) -> + Ldu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int ds1)) + + | `Pldux(reg0, reg1, reg2) -> + Ldux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstb(reg0, k1, reg2) -> + Stb + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Pstbx(reg0, reg1, reg2) -> + Stbx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstbu(reg0, k1, reg2) -> + Stbu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Pstbux(reg0, reg1, reg2) -> + Stbux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Psth(reg0, k1, reg2) -> + Sth + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Psthx(reg0, reg1, reg2) -> + Sthx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Psthu(reg0, k1, reg2) -> + Sthu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Psthux(reg0, reg1, reg2) -> + Sthux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstw(reg0, k1, reg2) -> + Stw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Pstwx(reg0, reg1, reg2) -> + Stwx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstwu(reg0, k1, reg2) -> + Stwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Pstwux(reg0, reg1, reg2) -> + Stwux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstd(reg0, ds1, reg2) -> + Std + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int ds1)) + + | `Pstdx(reg0, reg1, reg2) -> + Stdx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstdu(reg0, ds1, reg2) -> + Stdu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int ds1)) + + | `Pstdux(reg0, reg1, reg2) -> + Stdux + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plq(k0, k1, reg2, k3) -> + Lq + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 12,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 4,Nat_big_num.of_int k3)) + + | `Pstq(k0, ds1, reg2) -> + Stq + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 14,Nat_big_num.of_int ds1)) + + | `Plhbrx(reg0, reg1, reg2) -> + Lhbrx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Psthbrx(reg0, reg1, reg2) -> + Sthbrx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plwbrx(reg0, reg1, reg2) -> + Lwbrx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstwbrx(reg0, reg1, reg2) -> + Stwbrx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pldbrx(reg0, reg1, reg2) -> + Ldbrx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstdbrx(reg0, reg1, reg2) -> + Stdbrx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Plmw(reg0, k1, reg2) -> + Lmw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Pstmw(reg0, k1, reg2) -> + Stmw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k1)) + + | `Plswi(k0, reg1, k2) -> + Lswi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Plswx(reg0, reg1, reg2) -> + Lswx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstswi(k0, reg1, k2) -> + Stswi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2)) + + | `Pstswx(k0, reg1, reg2) -> + Stswx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Paddi(reg0, reg1, k2) -> + Addi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Paddis(reg0, reg1, k2) -> + Addis + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Padd(setsoov0, setcr01, reg2, reg3, reg4) -> + Add + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Psubf(setsoov0, setcr01, reg2, reg3, reg4) -> + Subf + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Paddic(reg0, reg1, k2) -> + Addic + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Paddicdot(reg0, reg1, k2) -> + AddicDot + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Psubfic(reg0, reg1, k2) -> + Subfic + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Paddc(setsoov0, setcr01, reg2, reg3, reg4) -> + Addc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Psubfc(setsoov0, setcr01, reg2, reg3, reg4) -> + Subfc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Padde(setsoov0, setcr01, reg2, reg3, reg4) -> + Adde + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Psubfe(setsoov0, setcr01, reg2, reg3, reg4) -> + Subfe + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Paddme(setsoov0, setcr01, reg2, reg3) -> + Addme + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Psubfme(setsoov0, setcr01, reg2, reg3) -> + Subfme + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Paddze(setsoov0, setcr01, reg2, reg3) -> + Addze + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Psubfze(setsoov0, setcr01, reg2, reg3) -> + Subfze + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pneg(setsoov0, setcr01, reg2, reg3) -> + Neg + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmulli(reg0, reg1, k2) -> + Mulli + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Pmullw(setsoov0, setcr01, reg2, reg3, reg4) -> + Mullw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmulhw(setcr00, reg1, reg2, reg3) -> + Mulhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmulhwu(setcr00, reg1, reg2, reg3) -> + Mulhwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pdivw(setsoov0, setcr01, reg2, reg3, reg4) -> + Divw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pdivwu(setsoov0, setcr01, reg2, reg3, reg4) -> + Divwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pdivwe(setsoov0, setcr01, reg2, reg3, reg4) -> + Divwe + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pdivweu(setsoov0, setcr01, reg2, reg3, reg4) -> + Divweu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmulld(setsoov0, setcr01, reg2, reg3, reg4) -> + Mulld + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmulhd(setcr00, reg1, reg2, reg3) -> + Mulhd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmulhdu(setcr00, reg1, reg2, reg3) -> + Mulhdu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pdivd(setsoov0, setcr01, reg2, reg3, reg4) -> + Divd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pdivdu(setsoov0, setcr01, reg2, reg3, reg4) -> + Divdu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pdivde(setsoov0, setcr01, reg2, reg3, reg4) -> + Divde + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pdivdeu(setsoov0, setcr01, reg2, reg3, reg4) -> + Divdeu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pcmpi(crindex0, k1, reg2, k3) -> + Cmpi + (Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int crindex0), + int_to_bit k1, + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k3)) + + | `Pcmp(crindex0, k1, reg2, reg3) -> + Cmp + (Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int crindex0), + int_to_bit k1, + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3))) + + | `Pcmpli(crindex0, k1, reg2, k3) -> + Cmpli + (Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int crindex0), + int_to_bit k1, + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k3)) + + | `Pcmpl(crindex0, k1, reg2, reg3) -> + Cmpl + (Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int crindex0), + int_to_bit k1, + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3))) + + | `Pisel(reg0, reg1, reg2, k3) -> + Isel + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k3)) + + | `Pandi(reg0, reg1, k2) -> + Andi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Pandis(reg0, reg1, k2) -> + Andis + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Pori(reg0, reg1, k2) -> + Ori + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Poris(reg0, reg1, k2) -> + Oris + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Pxori(reg0, reg1, k2) -> + Xori + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Pxoris(reg0, reg1, k2) -> + Xoris + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 16,Nat_big_num.of_int k2)) + + | `Pand(setcr00, reg1, reg2, reg3) -> + And + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pxor(setcr00, reg1, reg2, reg3) -> + Xor + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pnand(setcr00, reg1, reg2, reg3) -> + Nand + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Por(setcr00, reg1, reg2, reg3) -> + Or + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pnor(setcr00, reg1, reg2, reg3) -> + Nor + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Peqv(setcr00, reg1, reg2, reg3) -> + Eqv + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pandc(setcr00, reg1, reg2, reg3) -> + Andc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Porc(setcr00, reg1, reg2, reg3) -> + Orc + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pextsb(setcr00, reg1, reg2) -> + Extsb + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + int_to_bit (trans_cr0 setcr00)) + + | `Pextsh(setcr00, reg1, reg2) -> + Extsh + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + int_to_bit (trans_cr0 setcr00)) + + | `Pcntlzw(setcr00, reg1, reg2) -> + Cntlzw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + int_to_bit (trans_cr0 setcr00)) + + | `Pcmpb(reg0, k1, reg2) -> + Cmpb + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k1), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Ppopcntb(reg0, reg1) -> + Popcntb + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Ppopcntw(reg0, reg1) -> + Popcntw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Pprtyd(reg0, reg1) -> + Prtyd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Pprtyw(reg0, reg1) -> + Prtyw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Pextsw(setcr00, reg1, reg2) -> + Extsw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + int_to_bit (trans_cr0 setcr00)) + + | `Pcntlzd(setcr00, reg1, reg2) -> + Cntlzd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + int_to_bit (trans_cr0 setcr00)) + + | `Ppopcntd(reg0, reg1) -> + Popcntd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Pbpermd(reg0, reg1, reg2) -> + Bpermd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Prlwinm(setcr00, reg1, reg2, k3, k4, k5) -> + Rlwinm + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k4), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k5), + int_to_bit (trans_cr0 setcr00)) + + | `Prlwnm(setcr00, reg1, reg2, reg3, k4, k5) -> + Rlwnm + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k4), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k5), + int_to_bit (trans_cr0 setcr00)) + + | `Prlwimi(setcr00, reg1, reg2, k3, k4, k5) -> + Rlwimi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k4), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k5), + int_to_bit (trans_cr0 setcr00)) + + | `Prldicl(setcr00, reg1, reg2, k3, k4) -> + Rldicl + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k4), + int_to_bit (trans_cr0 setcr00)) + + | `Prldicr(setcr00, reg1, reg2, k3, k4) -> + Rldicr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k4), + int_to_bit (trans_cr0 setcr00)) + + | `Prldic(setcr00, reg1, reg2, k3, k4) -> + Rldic + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k4), + int_to_bit (trans_cr0 setcr00)) + + | `Prldcl(setcr00, reg1, reg2, reg3, k4) -> + Rldcl + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k4), + int_to_bit (trans_cr0 setcr00)) + + | `Prldcr(setcr00, reg1, reg2, reg3, k4) -> + Rldcr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k4), + int_to_bit (trans_cr0 setcr00)) + + | `Prldimi(setcr00, reg1, reg2, k3, k4) -> + Rldimi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k3), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k4), + int_to_bit (trans_cr0 setcr00)) + + | `Pslw(setcr00, reg1, reg2, reg3) -> + Slw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Psrw(setcr00, reg1, reg2, reg3) -> + Srw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Psrawi(setcr00, reg1, reg2, k3) -> + Srawi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k3), + int_to_bit (trans_cr0 setcr00)) + + | `Psraw(setcr00, reg1, reg2, reg3) -> + Sraw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Psld(setcr00, reg1, reg2, reg3) -> + Sld + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Psrd(setcr00, reg1, reg2, reg3) -> + Srd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Psradi(setcr00, reg1, reg2, k3) -> + Sradi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 6,Nat_big_num.of_int k3), + int_to_bit (trans_cr0 setcr00)) + + | `Psrad(setcr00, reg1, reg2, reg3) -> + Srad + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pcdtbcd(reg0, reg1) -> + Cdtbcd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Pcbcdtd(reg0, reg1) -> + Cbcdtd + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Paddg6s(reg0, reg1, reg2) -> + Addg6s + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pmtspr(k0, reg1) -> + Mtspr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 10,Nat_big_num.of_int k0)) + + | `Pmfspr(reg0, k1) -> + Mfspr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 10,Nat_big_num.of_int k1)) + + | `Pmtcrf(crmask0, reg1) -> + Mtcrf + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 8,Nat_big_num.of_int crmask0)) + + | `Pmfcr(reg0) -> + Mfcr + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0))) + + | `Pmtocrf(crmask0, reg1) -> + Mtocrf + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 8,Nat_big_num.of_int crmask0)) + + | `Pmfocrf(reg0, crmask1) -> + Mfocrf + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 8,Nat_big_num.of_int crmask1)) + + | `Pmcrxr(crindex0) -> + Mcrxr + (Sail_values.to_vec0 true (Nat_big_num.of_int 3,Nat_big_num.of_int crindex0)) + + | `Pdlmzb(setcr00, reg1, reg2, reg3) -> + Dlmzb + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmacchw(setsoov0, setcr01, reg2, reg3, reg4) -> + Macchw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmacchws(setsoov0, setcr01, reg2, reg3, reg4) -> + Macchws + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmacchwu(setsoov0, setcr01, reg2, reg3, reg4) -> + Macchwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmacchwsu(setsoov0, setcr01, reg2, reg3, reg4) -> + Macchwsu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmachhw(setsoov0, setcr01, reg2, reg3, reg4) -> + Machhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmachhws(setsoov0, setcr01, reg2, reg3, reg4) -> + Machhws + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmachhwu(setsoov0, setcr01, reg2, reg3, reg4) -> + Machhwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmachhwsu(setsoov0, setcr01, reg2, reg3, reg4) -> + Machhwsu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmaclhw(setsoov0, setcr01, reg2, reg3, reg4) -> + Maclhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmaclhws(setsoov0, setcr01, reg2, reg3, reg4) -> + Maclhws + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmaclhwu(setsoov0, setcr01, reg2, reg3, reg4) -> + Maclhwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmaclhwsu(setsoov0, setcr01, reg2, reg3, reg4) -> + Maclhwsu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pmulchw(setcr00, reg1, reg2, reg3) -> + Mulchw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmulchwu(setcr00, reg1, reg2, reg3) -> + Mulchwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmulhhw(setcr00, reg1, reg2, reg3) -> + Mulhhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmulhhwu(setcr00, reg1, reg2, reg3) -> + Mulhhwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmullhw(setcr00, reg1, reg2, reg3) -> + Mullhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pmullhwu(setcr00, reg1, reg2, reg3) -> + Mullhwu + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + int_to_bit (trans_cr0 setcr00)) + + | `Pnmacchw(setsoov0, setcr01, reg2, reg3, reg4) -> + Nmacchw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pnmacchws(setsoov0, setcr01, reg2, reg3, reg4) -> + Nmacchws + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pnmachhw(setsoov0, setcr01, reg2, reg3, reg4) -> + Nmachhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pnmachhws(setsoov0, setcr01, reg2, reg3, reg4) -> + Nmachhws + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pnmaclhw(setsoov0, setcr01, reg2, reg3, reg4) -> + Nmaclhw + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Pnmaclhws(setsoov0, setcr01, reg2, reg3, reg4) -> + Nmaclhws + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg3)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg4)), + int_to_bit (trans_soov setsoov0), + int_to_bit (trans_cr0 setcr01)) + + | `Picbi(reg0, reg1) -> + Icbi + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Picbt(k0, reg1, reg2) -> + Icbt + (Sail_values.to_vec0 true (Nat_big_num.of_int 4,Nat_big_num.of_int k0), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pdcba(reg0, reg1) -> + Dcba + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Pdcbt(reg0, reg1, k2) -> + Dcbt + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Pdcbtst(reg0, reg1, k2) -> + Dcbtst + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int k2), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Pdcbz(reg0, reg1) -> + Dcbz + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Pdcbst(reg0, reg1) -> + Dcbst + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Pdcbf(reg0, reg1, k2) -> + Dcbf + (Sail_values.to_vec0 true (Nat_big_num.of_int 2,Nat_big_num.of_int k2), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1))) + + | `Pisync -> + Isync + + | `Plbarx(reg0, reg1, reg2, k3) -> + Lbarx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + int_to_bit k3) + + | `Plharx(reg0, reg1, reg2, k3) -> + Lharx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + int_to_bit k3) + + | `Plwarx(reg0, reg1, reg2, k3) -> + Lwarx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + int_to_bit k3) + + | `Pstbcx(reg0, reg1, reg2) -> + Stbcx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Psthcx(reg0, reg1, reg2) -> + Sthcx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pstwcx(reg0, reg1, reg2) -> + Stwcx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Pldarx(reg0, reg1, reg2, k3) -> + Ldarx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2)), + int_to_bit k3) + + | `Pstdcx(reg0, reg1, reg2) -> + Stdcx + (Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg0)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg1)), + Sail_values.to_vec0 true (Nat_big_num.of_int 5,Nat_big_num.of_int (int_of_reg reg2))) + + | `Psync(k0) -> + Sync + (Sail_values.to_vec0 true (Nat_big_num.of_int 2,Nat_big_num.of_int k0)) + + | `Peieio -> + Eieio + + | `Pwait(k0) -> + Wait + (Sail_values.to_vec0 true (Nat_big_num.of_int 2,Nat_big_num.of_int k0)) + diff --git a/old/power/gen/lexer.gen b/old/power/gen/lexer.gen new file mode 100644 index 00000000..a2100883 --- /dev/null +++ b/old/power/gen/lexer.gen @@ -0,0 +1,368 @@ + "b", B; + "ba", BA; + "bl", BL; + "bla", BLA; + "bc", BC; + "bca", BCA; + "bcl", BCL; + "bcla", BCLA; + "bclr", BCLR; + "bclrl", BCLRL; + "bcctr", BCCTR; + "bcctrl", BCCTRL; + "crand", CRAND; + "crnand", CRNAND; + "cror", CROR; + "crxor", CRXOR; + "crnor", CRNOR; + "creqv", CREQV; + "crandc", CRANDC; + "crorc", CRORC; + "mcrf", MCRF; + "sc", SC; + "scv", SCV; + "lbz", LBZ; + "lbzx", LBZX; + "lbzu", LBZU; + "lbzux", LBZUX; + "lhz", LHZ; + "lhzx", LHZX; + "lhzu", LHZU; + "lhzux", LHZUX; + "lha", LHA; + "lhax", LHAX; + "lhau", LHAU; + "lhaux", LHAUX; + "lwz", LWZ; + "lwzx", LWZX; + "lwzu", LWZU; + "lwzux", LWZUX; + "lwa", LWA; + "lwax", LWAX; + "lwaux", LWAUX; + "ld", LD; + "ldx", LDX; + "ldu", LDU; + "ldux", LDUX; + "stb", STB; + "stbx", STBX; + "stbu", STBU; + "stbux", STBUX; + "sth", STH; + "sthx", STHX; + "sthu", STHU; + "sthux", STHUX; + "stw", STW; + "stwx", STWX; + "stwu", STWU; + "stwux", STWUX; + "std", STD; + "stdx", STDX; + "stdu", STDU; + "stdux", STDUX; + "lq", LQ; + "stq", STQ; + "lhbrx", LHBRX; + "sthbrx", STHBRX; + "lwbrx", LWBRX; + "stwbrx", STWBRX; + "ldbrx", LDBRX; + "stdbrx", STDBRX; + "lmw", LMW; + "stmw", STMW; + "lswi", LSWI; + "lswx", LSWX; + "stswi", STSWI; + "stswx", STSWX; + "addi", ADDI; + "addis", ADDIS; + "add", ADD; + "add.", ADDDOT; + "addo", ADDO; + "addo.", ADDODOT; + "subf", SUBF; + "subf.", SUBFDOT; + "subfo", SUBFO; + "subfo.", SUBFODOT; + "addic", ADDIC; + "addic.", ADDICDOT; + "subfic", SUBFIC; + "addc", ADDC; + "addc.", ADDCDOT; + "addco", ADDCO; + "addco.", ADDCODOT; + "subfc", SUBFC; + "subfc.", SUBFCDOT; + "subfco", SUBFCO; + "subfco.", SUBFCODOT; + "adde", ADDE; + "adde.", ADDEDOT; + "addeo", ADDEO; + "addeo.", ADDEODOT; + "subfe", SUBFE; + "subfe.", SUBFEDOT; + "subfeo", SUBFEO; + "subfeo.", SUBFEODOT; + "addme", ADDME; + "addme.", ADDMEDOT; + "addmeo", ADDMEO; + "addmeo.", ADDMEODOT; + "subfme", SUBFME; + "subfme.", SUBFMEDOT; + "subfmeo", SUBFMEO; + "subfmeo.", SUBFMEODOT; + "addze", ADDZE; + "addze.", ADDZEDOT; + "addzeo", ADDZEO; + "addzeo.", ADDZEODOT; + "subfze", SUBFZE; + "subfze.", SUBFZEDOT; + "subfzeo", SUBFZEO; + "subfzeo.", SUBFZEODOT; + "neg", NEG; + "neg.", NEGDOT; + "nego", NEGO; + "nego.", NEGODOT; + "mulli", MULLI; + "mullw", MULLW; + "mullw.", MULLWDOT; + "mullwo", MULLWO; + "mullwo.", MULLWODOT; + "mulhw", MULHW; + "mulhw.", MULHWDOT; + "mulhwu", MULHWU; + "mulhwu.", MULHWUDOT; + "divw", DIVW; + "divw.", DIVWDOT; + "divwo", DIVWO; + "divwo.", DIVWODOT; + "divwu", DIVWU; + "divwu.", DIVWUDOT; + "divwuo", DIVWUO; + "divwuo.", DIVWUODOT; + "divwe", DIVWE; + "divwe.", DIVWEDOT; + "divweo", DIVWEO; + "divweo.", DIVWEODOT; + "divweu", DIVWEU; + "divweu.", DIVWEUDOT; + "divweuo", DIVWEUO; + "divweuo.", DIVWEUODOT; + "mulld", MULLD; + "mulld.", MULLDDOT; + "mulldo", MULLDO; + "mulldo.", MULLDODOT; + "mulhd", MULHD; + "mulhd.", MULHDDOT; + "mulhdu", MULHDU; + "mulhdu.", MULHDUDOT; + "divd", DIVD; + "divd.", DIVDDOT; + "divdo", DIVDO; + "divdo.", DIVDODOT; + "divdu", DIVDU; + "divdu.", DIVDUDOT; + "divduo", DIVDUO; + "divduo.", DIVDUODOT; + "divde", DIVDE; + "divde.", DIVDEDOT; + "divdeo", DIVDEO; + "divdeo.", DIVDEODOT; + "divdeu", DIVDEU; + "divdeu.", DIVDEUDOT; + "divdeuo", DIVDEUO; + "divdeuo.", DIVDEUODOT; + "cmpi", CMPI; + "cmp", CMP; + "cmpli", CMPLI; + "cmpl", CMPL; + "isel", ISEL; + "andi.", ANDIDOT; + "andis.", ANDISDOT; + "ori", ORI; + "oris", ORIS; + "xori", XORI; + "xoris", XORIS; + "and", AND; + "and.", ANDDOT; + "xor", XOR; + "xor.", XORDOT; + "nand", NAND; + "nand.", NANDDOT; + "or", OR; + "or.", ORDOT; + "nor", NOR; + "nor.", NORDOT; + "eqv", EQV; + "eqv.", EQVDOT; + "andc", ANDC; + "andc.", ANDCDOT; + "orc", ORC; + "orc.", ORCDOT; + "extsb", EXTSB; + "extsb.", EXTSBDOT; + "extsh", EXTSH; + "extsh.", EXTSHDOT; + "cntlzw", CNTLZW; + "cntlzw.", CNTLZWDOT; + "cmpb", CMPB; + "popcntb", POPCNTB; + "popcntw", POPCNTW; + "prtyd", PRTYD; + "prtyw", PRTYW; + "extsw", EXTSW; + "extsw.", EXTSWDOT; + "cntlzd", CNTLZD; + "cntlzd.", CNTLZDDOT; + "popcntd", POPCNTD; + "bpermd", BPERMD; + "rlwinm", RLWINM; + "rlwinm.", RLWINMDOT; + "rlwnm", RLWNM; + "rlwnm.", RLWNMDOT; + "rlwimi", RLWIMI; + "rlwimi.", RLWIMIDOT; + "rldicl", RLDICL; + "rldicl.", RLDICLDOT; + "rldicr", RLDICR; + "rldicr.", RLDICRDOT; + "rldic", RLDIC; + "rldic.", RLDICDOT; + "rldcl", RLDCL; + "rldcl.", RLDCLDOT; + "rldcr", RLDCR; + "rldcr.", RLDCRDOT; + "rldimi", RLDIMI; + "rldimi.", RLDIMIDOT; + "slw", SLW; + "slw.", SLWDOT; + "srw", SRW; + "srw.", SRWDOT; + "srawi", SRAWI; + "srawi.", SRAWIDOT; + "sraw", SRAW; + "sraw.", SRAWDOT; + "sld", SLD; + "sld.", SLDDOT; + "srd", SRD; + "srd.", SRDDOT; + "sradi", SRADI; + "sradi.", SRADIDOT; + "srad", SRAD; + "srad.", SRADDOT; + "cdtbcd", CDTBCD; + "cbcdtd", CBCDTD; + "addg6s", ADDG6S; + "mtspr", MTSPR; + "mfspr", MFSPR; + "mtcrf", MTCRF; + "mfcr", MFCR; + "mtocrf", MTOCRF; + "mfocrf", MFOCRF; + "mcrxr", MCRXR; + "dlmzb", DLMZB; + "dlmzb.", DLMZBDOT; + "macchw", MACCHW; + "macchw.", MACCHWDOT; + "macchwo", MACCHWO; + "macchwo.", MACCHWODOT; + "macchws", MACCHWS; + "macchws.", MACCHWSDOT; + "macchwso", MACCHWSO; + "macchwso.", MACCHWSODOT; + "macchwu", MACCHWU; + "macchwu.", MACCHWUDOT; + "macchwuo", MACCHWUO; + "macchwuo.", MACCHWUODOT; + "macchwsu", MACCHWSU; + "macchwsu.", MACCHWSUDOT; + "macchwsuo", MACCHWSUO; + "macchwsuo.", MACCHWSUODOT; + "machhw", MACHHW; + "machhw.", MACHHWDOT; + "machhwo", MACHHWO; + "machhwo.", MACHHWODOT; + "machhws", MACHHWS; + "machhws.", MACHHWSDOT; + "machhwso", MACHHWSO; + "machhwso.", MACHHWSODOT; + "machhwu", MACHHWU; + "machhwu.", MACHHWUDOT; + "machhwuo", MACHHWUO; + "machhwuo.", MACHHWUODOT; + "machhwsu", MACHHWSU; + "machhwsu.", MACHHWSUDOT; + "machhwsuo", MACHHWSUO; + "machhwsuo.", MACHHWSUODOT; + "maclhw", MACLHW; + "maclhw.", MACLHWDOT; + "maclhwo", MACLHWO; + "maclhwo.", MACLHWODOT; + "maclhws", MACLHWS; + "maclhws.", MACLHWSDOT; + "maclhwso", MACLHWSO; + "maclhwso.", MACLHWSODOT; + "maclhwu", MACLHWU; + "maclhwu.", MACLHWUDOT; + "maclhwuo", MACLHWUO; + "maclhwuo.", MACLHWUODOT; + "maclhwsu", MACLHWSU; + "maclhwsu.", MACLHWSUDOT; + "maclhwsuo", MACLHWSUO; + "maclhwsuo.", MACLHWSUODOT; + "mulchw", MULCHW; + "mulchw.", MULCHWDOT; + "mulchwu", MULCHWU; + "mulchwu.", MULCHWUDOT; + "mulhhw", MULHHW; + "mulhhw.", MULHHWDOT; + "mulhhwu", MULHHWU; + "mulhhwu.", MULHHWUDOT; + "mullhw", MULLHW; + "mullhw.", MULLHWDOT; + "mullhwu", MULLHWU; + "mullhwu.", MULLHWUDOT; + "nmacchw", NMACCHW; + "nmacchw.", NMACCHWDOT; + "nmacchwo", NMACCHWO; + "nmacchwo.", NMACCHWODOT; + "nmacchws", NMACCHWS; + "nmacchws.", NMACCHWSDOT; + "nmacchwso", NMACCHWSO; + "nmacchwso.", NMACCHWSODOT; + "nmachhw", NMACHHW; + "nmachhw.", NMACHHWDOT; + "nmachhwo", NMACHHWO; + "nmachhwo.", NMACHHWODOT; + "nmachhws", NMACHHWS; + "nmachhws.", NMACHHWSDOT; + "nmachhwso", NMACHHWSO; + "nmachhwso.", NMACHHWSODOT; + "nmaclhw", NMACLHW; + "nmaclhw.", NMACLHWDOT; + "nmaclhwo", NMACLHWO; + "nmaclhwo.", NMACLHWODOT; + "nmaclhws", NMACLHWS; + "nmaclhws.", NMACLHWSDOT; + "nmaclhwso", NMACLHWSO; + "nmaclhwso.", NMACLHWSODOT; + "icbi", ICBI; + "icbt", ICBT; + "dcba", DCBA; + "dcbt", DCBT; + "dcbtst", DCBTST; + "dcbz", DCBZ; + "dcbst", DCBST; + "dcbf", DCBF; + "isync", ISYNC; + "lbarx", LBARX; + "lharx", LHARX; + "lwarx", LWARX; + "stbcx.", STBCXDOT; + "sthcx.", STHCXDOT; + "stwcx.", STWCXDOT; + "ldarx", LDARX; + "stdcx.", STDCXDOT; + "sync", SYNC; + "eieio", EIEIO; + "wait", WAIT; diff --git a/old/power/gen/map.gen b/old/power/gen/map.gen new file mode 100644 index 00000000..27833b80 --- /dev/null +++ b/old/power/gen/map.gen @@ -0,0 +1,368 @@ +| `Pb (DontSetAA,DontSetLK,target_addr) -> `Pb(DontSetAA,DontSetLK,target_addr) +| `Pb (SetAA,DontSetLK,target_addr) -> `Pb(SetAA,DontSetLK,target_addr) +| `Pb (DontSetAA,SetLK,target_addr) -> `Pb(DontSetAA,SetLK,target_addr) +| `Pb (SetAA,SetLK,target_addr) -> `Pb(SetAA,SetLK,target_addr) +| `Pbc (DontSetAA,DontSetLK,bO,bI,target_addr) -> `Pbc(DontSetAA,DontSetLK,bO,bI,target_addr) +| `Pbc (SetAA,DontSetLK,bO,bI,target_addr) -> `Pbc(SetAA,DontSetLK,bO,bI,target_addr) +| `Pbc (DontSetAA,SetLK,bO,bI,target_addr) -> `Pbc(DontSetAA,SetLK,bO,bI,target_addr) +| `Pbc (SetAA,SetLK,bO,bI,target_addr) -> `Pbc(SetAA,SetLK,bO,bI,target_addr) +| `Pbclr (DontSetLK,bO,bI,bH) -> `Pbclr(DontSetLK,bO,bI,bH) +| `Pbclr (SetLK,bO,bI,bH) -> `Pbclr(SetLK,bO,bI,bH) +| `Pbcctr (DontSetLK,bO,bI,bH) -> `Pbcctr(DontSetLK,bO,bI,bH) +| `Pbcctr (SetLK,bO,bI,bH) -> `Pbcctr(SetLK,bO,bI,bH) +| `Pcrand (bT,bA,bB) -> `Pcrand(bT,bA,bB) +| `Pcrnand (bT,bA,bB) -> `Pcrnand(bT,bA,bB) +| `Pcror (bT,bA,bB) -> `Pcror(bT,bA,bB) +| `Pcrxor (bT,bA,bB) -> `Pcrxor(bT,bA,bB) +| `Pcrnor (bT,bA,bB) -> `Pcrnor(bT,bA,bB) +| `Pcreqv (bT,bA,bB) -> `Pcreqv(bT,bA,bB) +| `Pcrandc (bT,bA,bB) -> `Pcrandc(bT,bA,bB) +| `Pcrorc (bT,bA,bB) -> `Pcrorc(bT,bA,bB) +| `Pmcrf (bF,bFA) -> `Pmcrf(bF,bFA) +| `Psc (lEV) -> `Psc(lEV) +| `Pscv (lEV) -> `Pscv(lEV) +| `Plbz (rT,d,rA) -> `Plbz(map_reg rT,d,map_reg rA) +| `Plbzx (rT,rA,rB) -> `Plbzx(map_reg rT,map_reg rA,map_reg rB) +| `Plbzu (rT,d,rA) -> `Plbzu(map_reg rT,d,map_reg rA) +| `Plbzux (rT,rA,rB) -> `Plbzux(map_reg rT,map_reg rA,map_reg rB) +| `Plhz (rT,d,rA) -> `Plhz(map_reg rT,d,map_reg rA) +| `Plhzx (rT,rA,rB) -> `Plhzx(map_reg rT,map_reg rA,map_reg rB) +| `Plhzu (rT,d,rA) -> `Plhzu(map_reg rT,d,map_reg rA) +| `Plhzux (rT,rA,rB) -> `Plhzux(map_reg rT,map_reg rA,map_reg rB) +| `Plha (rT,d,rA) -> `Plha(map_reg rT,d,map_reg rA) +| `Plhax (rT,rA,rB) -> `Plhax(map_reg rT,map_reg rA,map_reg rB) +| `Plhau (rT,d,rA) -> `Plhau(map_reg rT,d,map_reg rA) +| `Plhaux (rT,rA,rB) -> `Plhaux(map_reg rT,map_reg rA,map_reg rB) +| `Plwz (rT,d,rA) -> `Plwz(map_reg rT,d,map_reg rA) +| `Plwzx (rT,rA,rB) -> `Plwzx(map_reg rT,map_reg rA,map_reg rB) +| `Plwzu (rT,d,rA) -> `Plwzu(map_reg rT,d,map_reg rA) +| `Plwzux (rT,rA,rB) -> `Plwzux(map_reg rT,map_reg rA,map_reg rB) +| `Plwa (rT,dS,rA) -> `Plwa(map_reg rT,dS,map_reg rA) +| `Plwax (rT,rA,rB) -> `Plwax(map_reg rT,map_reg rA,map_reg rB) +| `Plwaux (rT,rA,rB) -> `Plwaux(map_reg rT,map_reg rA,map_reg rB) +| `Pld (rT,dS,rA) -> `Pld(map_reg rT,dS,map_reg rA) +| `Pldx (rT,rA,rB) -> `Pldx(map_reg rT,map_reg rA,map_reg rB) +| `Pldu (rT,dS,rA) -> `Pldu(map_reg rT,dS,map_reg rA) +| `Pldux (rT,rA,rB) -> `Pldux(map_reg rT,map_reg rA,map_reg rB) +| `Pstb (rS,d,rA) -> `Pstb(map_reg rS,d,map_reg rA) +| `Pstbx (rS,rA,rB) -> `Pstbx(map_reg rS,map_reg rA,map_reg rB) +| `Pstbu (rS,d,rA) -> `Pstbu(map_reg rS,d,map_reg rA) +| `Pstbux (rS,rA,rB) -> `Pstbux(map_reg rS,map_reg rA,map_reg rB) +| `Psth (rS,d,rA) -> `Psth(map_reg rS,d,map_reg rA) +| `Psthx (rS,rA,rB) -> `Psthx(map_reg rS,map_reg rA,map_reg rB) +| `Psthu (rS,d,rA) -> `Psthu(map_reg rS,d,map_reg rA) +| `Psthux (rS,rA,rB) -> `Psthux(map_reg rS,map_reg rA,map_reg rB) +| `Pstw (rS,d,rA) -> `Pstw(map_reg rS,d,map_reg rA) +| `Pstwx (rS,rA,rB) -> `Pstwx(map_reg rS,map_reg rA,map_reg rB) +| `Pstwu (rS,d,rA) -> `Pstwu(map_reg rS,d,map_reg rA) +| `Pstwux (rS,rA,rB) -> `Pstwux(map_reg rS,map_reg rA,map_reg rB) +| `Pstd (rS,dS,rA) -> `Pstd(map_reg rS,dS,map_reg rA) +| `Pstdx (rS,rA,rB) -> `Pstdx(map_reg rS,map_reg rA,map_reg rB) +| `Pstdu (rS,dS,rA) -> `Pstdu(map_reg rS,dS,map_reg rA) +| `Pstdux (rS,rA,rB) -> `Pstdux(map_reg rS,map_reg rA,map_reg rB) +| `Plq (rTp,dQ,rA,pT) -> `Plq(rTp,dQ,map_reg rA,pT) +| `Pstq (rSp,dS,rA) -> `Pstq(rSp,dS,map_reg rA) +| `Plhbrx (rT,rA,rB) -> `Plhbrx(map_reg rT,map_reg rA,map_reg rB) +| `Psthbrx (rS,rA,rB) -> `Psthbrx(map_reg rS,map_reg rA,map_reg rB) +| `Plwbrx (rT,rA,rB) -> `Plwbrx(map_reg rT,map_reg rA,map_reg rB) +| `Pstwbrx (rS,rA,rB) -> `Pstwbrx(map_reg rS,map_reg rA,map_reg rB) +| `Pldbrx (rT,rA,rB) -> `Pldbrx(map_reg rT,map_reg rA,map_reg rB) +| `Pstdbrx (rS,rA,rB) -> `Pstdbrx(map_reg rS,map_reg rA,map_reg rB) +| `Plmw (rT,d,rA) -> `Plmw(rT,d,map_reg rA) +| `Pstmw (rS,d,rA) -> `Pstmw(rS,d,map_reg rA) +| `Plswi (rT,rA,nB) -> `Plswi(rT,map_reg rA,nB) +| `Plswx (rT,rA,rB) -> `Plswx(map_reg rT,map_reg rA,map_reg rB) +| `Pstswi (rS,rA,nB) -> `Pstswi(rS,map_reg rA,nB) +| `Pstswx (rS,rA,rB) -> `Pstswx(rS,map_reg rA,map_reg rB) +| `Paddi (rT,rA,sI) -> `Paddi(map_reg rT,map_reg rA,sI) +| `Paddis (rT,rA,sI) -> `Paddis(map_reg rT,map_reg rA,sI) +| `Padd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Padd(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padd (DontSetSOOV,SetCR0,rT,rA,rB) -> `Padd(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padd (SetSOOV,DontSetCR0,rT,rA,rB) -> `Padd(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padd (SetSOOV,SetCR0,rT,rA,rB) -> `Padd(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubf (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Psubf(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubf (DontSetSOOV,SetCR0,rT,rA,rB) -> `Psubf(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubf (SetSOOV,DontSetCR0,rT,rA,rB) -> `Psubf(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubf (SetSOOV,SetCR0,rT,rA,rB) -> `Psubf(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Paddic (rT,rA,sI) -> `Paddic(map_reg rT,map_reg rA,sI) +| `Paddicdot (rT,rA,sI) -> `Paddicdot(map_reg rT,map_reg rA,sI) +| `Psubfic (rT,rA,sI) -> `Psubfic(map_reg rT,map_reg rA,sI) +| `Paddc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Paddc(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Paddc (DontSetSOOV,SetCR0,rT,rA,rB) -> `Paddc(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Paddc (SetSOOV,DontSetCR0,rT,rA,rB) -> `Paddc(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Paddc (SetSOOV,SetCR0,rT,rA,rB) -> `Paddc(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Psubfc(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfc (DontSetSOOV,SetCR0,rT,rA,rB) -> `Psubfc(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfc (SetSOOV,DontSetCR0,rT,rA,rB) -> `Psubfc(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfc (SetSOOV,SetCR0,rT,rA,rB) -> `Psubfc(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Padde(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padde (DontSetSOOV,SetCR0,rT,rA,rB) -> `Padde(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padde (SetSOOV,DontSetCR0,rT,rA,rB) -> `Padde(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Padde (SetSOOV,SetCR0,rT,rA,rB) -> `Padde(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Psubfe(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfe (DontSetSOOV,SetCR0,rT,rA,rB) -> `Psubfe(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfe (SetSOOV,DontSetCR0,rT,rA,rB) -> `Psubfe(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Psubfe (SetSOOV,SetCR0,rT,rA,rB) -> `Psubfe(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Paddme (DontSetSOOV,DontSetCR0,rT,rA) -> `Paddme(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Paddme (DontSetSOOV,SetCR0,rT,rA) -> `Paddme(DontSetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Paddme (SetSOOV,DontSetCR0,rT,rA) -> `Paddme(SetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Paddme (SetSOOV,SetCR0,rT,rA) -> `Paddme(SetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Psubfme (DontSetSOOV,DontSetCR0,rT,rA) -> `Psubfme(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Psubfme (DontSetSOOV,SetCR0,rT,rA) -> `Psubfme(DontSetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Psubfme (SetSOOV,DontSetCR0,rT,rA) -> `Psubfme(SetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Psubfme (SetSOOV,SetCR0,rT,rA) -> `Psubfme(SetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Paddze (DontSetSOOV,DontSetCR0,rT,rA) -> `Paddze(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Paddze (DontSetSOOV,SetCR0,rT,rA) -> `Paddze(DontSetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Paddze (SetSOOV,DontSetCR0,rT,rA) -> `Paddze(SetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Paddze (SetSOOV,SetCR0,rT,rA) -> `Paddze(SetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Psubfze (DontSetSOOV,DontSetCR0,rT,rA) -> `Psubfze(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Psubfze (DontSetSOOV,SetCR0,rT,rA) -> `Psubfze(DontSetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Psubfze (SetSOOV,DontSetCR0,rT,rA) -> `Psubfze(SetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Psubfze (SetSOOV,SetCR0,rT,rA) -> `Psubfze(SetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Pneg (DontSetSOOV,DontSetCR0,rT,rA) -> `Pneg(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Pneg (DontSetSOOV,SetCR0,rT,rA) -> `Pneg(DontSetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Pneg (SetSOOV,DontSetCR0,rT,rA) -> `Pneg(SetSOOV,DontSetCR0,map_reg rT,map_reg rA) +| `Pneg (SetSOOV,SetCR0,rT,rA) -> `Pneg(SetSOOV,SetCR0,map_reg rT,map_reg rA) +| `Pmulli (rT,rA,sI) -> `Pmulli(map_reg rT,map_reg rA,sI) +| `Pmullw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmullw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmullw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmullw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullw (SetSOOV,SetCR0,rT,rA,rB) -> `Pmullw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhw (DontSetCR0,rT,rA,rB) -> `Pmulhw(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhw (SetCR0,rT,rA,rB) -> `Pmulhw(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhwu (DontSetCR0,rT,rA,rB) -> `Pmulhwu(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhwu (SetCR0,rT,rA,rB) -> `Pmulhwu(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivw (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivwu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivwu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivwu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwu (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivwu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivwe(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwe (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivwe(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwe (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivwe(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivwe (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivwe(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivweu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivweu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivweu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivweu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivweu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivweu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivweu (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivweu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulld (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmulld(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulld (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmulld(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulld (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmulld(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulld (SetSOOV,SetCR0,rT,rA,rB) -> `Pmulld(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhd (DontSetCR0,rT,rA,rB) -> `Pmulhd(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhd (SetCR0,rT,rA,rB) -> `Pmulhd(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhdu (DontSetCR0,rT,rA,rB) -> `Pmulhdu(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhdu (SetCR0,rT,rA,rB) -> `Pmulhdu(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivd(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivd (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivd(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivd (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivd(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivd (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivd(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivdu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivdu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivdu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdu (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivdu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivde(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivde (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivde(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivde (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivde(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivde (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivde(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdeu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivdeu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdeu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pdivdeu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdeu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pdivdeu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pdivdeu (SetSOOV,SetCR0,rT,rA,rB) -> `Pdivdeu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pcmpi (bF,l,rA,sI) -> `Pcmpi(bF,l,map_reg rA,sI) +| `Pcmp (bF,l,rA,rB) -> `Pcmp(bF,l,map_reg rA,map_reg rB) +| `Pcmpli (bF,l,rA,uI) -> `Pcmpli(bF,l,map_reg rA,uI) +| `Pcmpl (bF,l,rA,rB) -> `Pcmpl(bF,l,map_reg rA,map_reg rB) +| `Pisel (rT,rA,rB,bC) -> `Pisel(map_reg rT,map_reg rA,map_reg rB,bC) +| `Pandi (rA,rS,uI) -> `Pandi(map_reg rA,map_reg rS,uI) +| `Pandis (rA,rS,uI) -> `Pandis(map_reg rA,map_reg rS,uI) +| `Pori (rA,rS,uI) -> `Pori(map_reg rA,map_reg rS,uI) +| `Poris (rA,rS,uI) -> `Poris(map_reg rA,map_reg rS,uI) +| `Pxori (rA,rS,uI) -> `Pxori(map_reg rA,map_reg rS,uI) +| `Pxoris (rA,rS,uI) -> `Pxoris(map_reg rA,map_reg rS,uI) +| `Pand (DontSetCR0,rA,rS,rB) -> `Pand(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pand (SetCR0,rA,rS,rB) -> `Pand(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pxor (DontSetCR0,rA,rS,rB) -> `Pxor(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pxor (SetCR0,rA,rS,rB) -> `Pxor(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pnand (DontSetCR0,rA,rS,rB) -> `Pnand(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pnand (SetCR0,rA,rS,rB) -> `Pnand(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Por (DontSetCR0,rA,rS,rB) -> `Por(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Por (SetCR0,rA,rS,rB) -> `Por(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pnor (DontSetCR0,rA,rS,rB) -> `Pnor(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pnor (SetCR0,rA,rS,rB) -> `Pnor(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Peqv (DontSetCR0,rA,rS,rB) -> `Peqv(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Peqv (SetCR0,rA,rS,rB) -> `Peqv(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pandc (DontSetCR0,rA,rS,rB) -> `Pandc(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pandc (SetCR0,rA,rS,rB) -> `Pandc(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Porc (DontSetCR0,rA,rS,rB) -> `Porc(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Porc (SetCR0,rA,rS,rB) -> `Porc(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pextsb (DontSetCR0,rA,rS) -> `Pextsb(DontSetCR0,map_reg rA,map_reg rS) +| `Pextsb (SetCR0,rA,rS) -> `Pextsb(SetCR0,map_reg rA,map_reg rS) +| `Pextsh (DontSetCR0,rA,rS) -> `Pextsh(DontSetCR0,map_reg rA,map_reg rS) +| `Pextsh (SetCR0,rA,rS) -> `Pextsh(SetCR0,map_reg rA,map_reg rS) +| `Pcntlzw (DontSetCR0,rA,rS) -> `Pcntlzw(DontSetCR0,map_reg rA,map_reg rS) +| `Pcntlzw (SetCR0,rA,rS) -> `Pcntlzw(SetCR0,map_reg rA,map_reg rS) +| `Pcmpb (rA,rS,rB) -> `Pcmpb(map_reg rA,rS,map_reg rB) +| `Ppopcntb (rA,rS) -> `Ppopcntb(map_reg rA,map_reg rS) +| `Ppopcntw (rA,rS) -> `Ppopcntw(map_reg rA,map_reg rS) +| `Pprtyd (rA,rS) -> `Pprtyd(map_reg rA,map_reg rS) +| `Pprtyw (rA,rS) -> `Pprtyw(map_reg rA,map_reg rS) +| `Pextsw (DontSetCR0,rA,rS) -> `Pextsw(DontSetCR0,map_reg rA,map_reg rS) +| `Pextsw (SetCR0,rA,rS) -> `Pextsw(SetCR0,map_reg rA,map_reg rS) +| `Pcntlzd (DontSetCR0,rA,rS) -> `Pcntlzd(DontSetCR0,map_reg rA,map_reg rS) +| `Pcntlzd (SetCR0,rA,rS) -> `Pcntlzd(SetCR0,map_reg rA,map_reg rS) +| `Ppopcntd (rA,rS) -> `Ppopcntd(map_reg rA,map_reg rS) +| `Pbpermd (rA,rS,rB) -> `Pbpermd(map_reg rA,map_reg rS,map_reg rB) +| `Prlwinm (DontSetCR0,rA,rS,sH,mB,mE) -> `Prlwinm(DontSetCR0,map_reg rA,map_reg rS,sH,mB,mE) +| `Prlwinm (SetCR0,rA,rS,sH,mB,mE) -> `Prlwinm(SetCR0,map_reg rA,map_reg rS,sH,mB,mE) +| `Prlwnm (DontSetCR0,rA,rS,rB,mB,mE) -> `Prlwnm(DontSetCR0,map_reg rA,map_reg rS,map_reg rB,mB,mE) +| `Prlwnm (SetCR0,rA,rS,rB,mB,mE) -> `Prlwnm(SetCR0,map_reg rA,map_reg rS,map_reg rB,mB,mE) +| `Prlwimi (DontSetCR0,rA,rS,sH,mB,mE) -> `Prlwimi(DontSetCR0,map_reg rA,map_reg rS,sH,mB,mE) +| `Prlwimi (SetCR0,rA,rS,sH,mB,mE) -> `Prlwimi(SetCR0,map_reg rA,map_reg rS,sH,mB,mE) +| `Prldicl (DontSetCR0,rA,rS,sH,mB) -> `Prldicl(DontSetCR0,map_reg rA,map_reg rS,sH,mB) +| `Prldicl (SetCR0,rA,rS,sH,mB) -> `Prldicl(SetCR0,map_reg rA,map_reg rS,sH,mB) +| `Prldicr (DontSetCR0,rA,rS,sH,mE) -> `Prldicr(DontSetCR0,map_reg rA,map_reg rS,sH,mE) +| `Prldicr (SetCR0,rA,rS,sH,mE) -> `Prldicr(SetCR0,map_reg rA,map_reg rS,sH,mE) +| `Prldic (DontSetCR0,rA,rS,sH,mB) -> `Prldic(DontSetCR0,map_reg rA,map_reg rS,sH,mB) +| `Prldic (SetCR0,rA,rS,sH,mB) -> `Prldic(SetCR0,map_reg rA,map_reg rS,sH,mB) +| `Prldcl (DontSetCR0,rA,rS,rB,mB) -> `Prldcl(DontSetCR0,map_reg rA,map_reg rS,map_reg rB,mB) +| `Prldcl (SetCR0,rA,rS,rB,mB) -> `Prldcl(SetCR0,map_reg rA,map_reg rS,map_reg rB,mB) +| `Prldcr (DontSetCR0,rA,rS,rB,mE) -> `Prldcr(DontSetCR0,map_reg rA,map_reg rS,map_reg rB,mE) +| `Prldcr (SetCR0,rA,rS,rB,mE) -> `Prldcr(SetCR0,map_reg rA,map_reg rS,map_reg rB,mE) +| `Prldimi (DontSetCR0,rA,rS,sH,mB) -> `Prldimi(DontSetCR0,map_reg rA,map_reg rS,sH,mB) +| `Prldimi (SetCR0,rA,rS,sH,mB) -> `Prldimi(SetCR0,map_reg rA,map_reg rS,sH,mB) +| `Pslw (DontSetCR0,rA,rS,rB) -> `Pslw(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pslw (SetCR0,rA,rS,rB) -> `Pslw(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psrw (DontSetCR0,rA,rS,rB) -> `Psrw(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psrw (SetCR0,rA,rS,rB) -> `Psrw(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psrawi (DontSetCR0,rA,rS,sH) -> `Psrawi(DontSetCR0,map_reg rA,map_reg rS,sH) +| `Psrawi (SetCR0,rA,rS,sH) -> `Psrawi(SetCR0,map_reg rA,map_reg rS,sH) +| `Psraw (DontSetCR0,rA,rS,rB) -> `Psraw(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psraw (SetCR0,rA,rS,rB) -> `Psraw(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psld (DontSetCR0,rA,rS,rB) -> `Psld(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psld (SetCR0,rA,rS,rB) -> `Psld(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psrd (DontSetCR0,rA,rS,rB) -> `Psrd(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psrd (SetCR0,rA,rS,rB) -> `Psrd(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psradi (DontSetCR0,rA,rS,sH) -> `Psradi(DontSetCR0,map_reg rA,map_reg rS,sH) +| `Psradi (SetCR0,rA,rS,sH) -> `Psradi(SetCR0,map_reg rA,map_reg rS,sH) +| `Psrad (DontSetCR0,rA,rS,rB) -> `Psrad(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Psrad (SetCR0,rA,rS,rB) -> `Psrad(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pcdtbcd (rA,rS) -> `Pcdtbcd(map_reg rA,map_reg rS) +| `Pcbcdtd (rA,rS) -> `Pcbcdtd(map_reg rA,map_reg rS) +| `Paddg6s (rT,rA,rB) -> `Paddg6s(map_reg rT,map_reg rA,map_reg rB) +| `Pmtspr (sPR,rS) -> `Pmtspr(sPR,map_reg rS) +| `Pmfspr (rT,sPR) -> `Pmfspr(map_reg rT,sPR) +| `Pmtcrf (fXM,rS) -> `Pmtcrf(fXM,map_reg rS) +| `Pmfcr (rT) -> `Pmfcr(map_reg rT) +| `Pmtocrf (fXM,rS) -> `Pmtocrf(fXM,map_reg rS) +| `Pmfocrf (rT,fXM) -> `Pmfocrf(map_reg rT,fXM) +| `Pmcrxr (bF) -> `Pmcrxr(bF) +| `Pdlmzb (DontSetCR0,rA,rS,rB) -> `Pdlmzb(DontSetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pdlmzb (SetCR0,rA,rS,rB) -> `Pdlmzb(SetCR0,map_reg rA,map_reg rS,map_reg rB) +| `Pmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmacchw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchw (SetSOOV,SetCR0,rT,rA,rB) -> `Pmacchw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchws(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmacchws(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchws(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchws (SetSOOV,SetCR0,rT,rA,rB) -> `Pmacchws(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchwu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmacchwu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchwu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwu (SetSOOV,SetCR0,rT,rA,rB) -> `Pmacchwu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchwsu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmacchwsu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmacchwsu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmacchwsu (SetSOOV,SetCR0,rT,rA,rB) -> `Pmacchwsu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmachhw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhw (SetSOOV,SetCR0,rT,rA,rB) -> `Pmachhw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhws(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmachhws(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhws(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhws (SetSOOV,SetCR0,rT,rA,rB) -> `Pmachhws(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhwu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmachhwu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhwu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwu (SetSOOV,SetCR0,rT,rA,rB) -> `Pmachhwu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhwsu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmachhwsu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmachhwsu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmachhwsu (SetSOOV,SetCR0,rT,rA,rB) -> `Pmachhwsu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhws(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhws(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhws(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhws(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhwu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhwu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhwu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwu (SetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhwu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhwsu(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhwsu(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pmaclhwsu(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmaclhwsu (SetSOOV,SetCR0,rT,rA,rB) -> `Pmaclhwsu(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulchw (DontSetCR0,rT,rA,rB) -> `Pmulchw(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulchw (SetCR0,rT,rA,rB) -> `Pmulchw(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulchwu (DontSetCR0,rT,rA,rB) -> `Pmulchwu(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulchwu (SetCR0,rT,rA,rB) -> `Pmulchwu(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhhw (DontSetCR0,rT,rA,rB) -> `Pmulhhw(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhhw (SetCR0,rT,rA,rB) -> `Pmulhhw(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhhwu (DontSetCR0,rT,rA,rB) -> `Pmulhhwu(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmulhhwu (SetCR0,rT,rA,rB) -> `Pmulhhwu(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullhw (DontSetCR0,rT,rA,rB) -> `Pmullhw(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullhw (SetCR0,rT,rA,rB) -> `Pmullhw(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullhwu (DontSetCR0,rT,rA,rB) -> `Pmullhwu(DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pmullhwu (SetCR0,rT,rA,rB) -> `Pmullhwu(SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmacchw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pnmacchw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmacchw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchw (SetSOOV,SetCR0,rT,rA,rB) -> `Pnmacchw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmacchws(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pnmacchws(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmacchws(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmacchws (SetSOOV,SetCR0,rT,rA,rB) -> `Pnmacchws(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmachhw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pnmachhw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmachhw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhw (SetSOOV,SetCR0,rT,rA,rB) -> `Pnmachhw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmachhws(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pnmachhws(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmachhws(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmachhws (SetSOOV,SetCR0,rT,rA,rB) -> `Pnmachhws(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmaclhw(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pnmaclhw(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmaclhw(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> `Pnmaclhw(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmaclhws(DontSetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> `Pnmaclhws(DontSetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> `Pnmaclhws(SetSOOV,DontSetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Pnmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> `Pnmaclhws(SetSOOV,SetCR0,map_reg rT,map_reg rA,map_reg rB) +| `Picbi (rA,rB) -> `Picbi(map_reg rA,map_reg rB) +| `Picbt (cT,rA,rB) -> `Picbt(cT,map_reg rA,map_reg rB) +| `Pdcba (rA,rB) -> `Pdcba(map_reg rA,map_reg rB) +| `Pdcbt (rA,rB,tH) -> `Pdcbt(map_reg rA,map_reg rB,tH) +| `Pdcbtst (rA,rB,tH) -> `Pdcbtst(map_reg rA,map_reg rB,tH) +| `Pdcbz (rA,rB) -> `Pdcbz(map_reg rA,map_reg rB) +| `Pdcbst (rA,rB) -> `Pdcbst(map_reg rA,map_reg rB) +| `Pdcbf (rA,rB,l) -> `Pdcbf(map_reg rA,map_reg rB,l) +| `Pisync -> `Pisync +| `Plbarx (rT,rA,rB,eH) -> `Plbarx(map_reg rT,map_reg rA,map_reg rB,eH) +| `Plharx (rT,rA,rB,eH) -> `Plharx(map_reg rT,map_reg rA,map_reg rB,eH) +| `Plwarx (rT,rA,rB,eH) -> `Plwarx(map_reg rT,map_reg rA,map_reg rB,eH) +| `Pstbcx (rS,rA,rB) -> `Pstbcx(map_reg rS,map_reg rA,map_reg rB) +| `Psthcx (rS,rA,rB) -> `Psthcx(map_reg rS,map_reg rA,map_reg rB) +| `Pstwcx (rS,rA,rB) -> `Pstwcx(map_reg rS,map_reg rA,map_reg rB) +| `Pldarx (rT,rA,rB,eH) -> `Pldarx(map_reg rT,map_reg rA,map_reg rB,eH) +| `Pstdcx (rS,rA,rB) -> `Pstdcx(map_reg rS,map_reg rA,map_reg rB) +| `Psync (l) -> `Psync(l) +| `Peieio -> `Peieio +| `Pwait (wC) -> `Pwait(wC) diff --git a/old/power/gen/parser.gen b/old/power/gen/parser.gen new file mode 100644 index 00000000..298cd50f --- /dev/null +++ b/old/power/gen/parser.gen @@ -0,0 +1,736 @@ + | B k + { `Pb (DontSetAA,DontSetLK,$2) } + | BA k + { `Pb (SetAA,DontSetLK,$2) } + | BL k + { `Pb (DontSetAA,SetLK,$2) } + | BLA k + { `Pb (SetAA,SetLK,$2) } + | BC k COMMA k COMMA k + { `Pbc (DontSetAA,DontSetLK,$2,$4,$6) } + | BCA k COMMA k COMMA k + { `Pbc (SetAA,DontSetLK,$2,$4,$6) } + | BCL k COMMA k COMMA k + { `Pbc (DontSetAA,SetLK,$2,$4,$6) } + | BCLA k COMMA k COMMA k + { `Pbc (SetAA,SetLK,$2,$4,$6) } + | BCLR k COMMA k COMMA k + { `Pbclr (DontSetLK,$2,$4,$6) } + | BCLRL k COMMA k COMMA k + { `Pbclr (SetLK,$2,$4,$6) } + | BCCTR k COMMA k COMMA k + { `Pbcctr (DontSetLK,$2,$4,$6) } + | BCCTRL k COMMA k COMMA k + { `Pbcctr (SetLK,$2,$4,$6) } + | CRAND k COMMA k COMMA k + { `Pcrand ($2,$4,$6) } + | CRNAND k COMMA k COMMA k + { `Pcrnand ($2,$4,$6) } + | CROR k COMMA k COMMA k + { `Pcror ($2,$4,$6) } + | CRXOR k COMMA k COMMA k + { `Pcrxor ($2,$4,$6) } + | CRNOR k COMMA k COMMA k + { `Pcrnor ($2,$4,$6) } + | CREQV k COMMA k COMMA k + { `Pcreqv ($2,$4,$6) } + | CRANDC k COMMA k COMMA k + { `Pcrandc ($2,$4,$6) } + | CRORC k COMMA k COMMA k + { `Pcrorc ($2,$4,$6) } + | MCRF crindex COMMA k + { `Pmcrf ($2,$4) } + | SC k + { `Psc ($2) } + | SCV k + { `Pscv ($2) } + | LBZ reg COMMA k LPAR reg RPAR + { `Plbz ($2,$4,$6) } + | LBZX reg COMMA reg COMMA reg + { `Plbzx ($2,$4,$6) } + | LBZU reg COMMA k LPAR reg RPAR + { `Plbzu ($2,$4,$6) } + | LBZUX reg COMMA reg COMMA reg + { `Plbzux ($2,$4,$6) } + | LHZ reg COMMA k LPAR reg RPAR + { `Plhz ($2,$4,$6) } + | LHZX reg COMMA reg COMMA reg + { `Plhzx ($2,$4,$6) } + | LHZU reg COMMA k LPAR reg RPAR + { `Plhzu ($2,$4,$6) } + | LHZUX reg COMMA reg COMMA reg + { `Plhzux ($2,$4,$6) } + | LHA reg COMMA k LPAR reg RPAR + { `Plha ($2,$4,$6) } + | LHAX reg COMMA reg COMMA reg + { `Plhax ($2,$4,$6) } + | LHAU reg COMMA k LPAR reg RPAR + { `Plhau ($2,$4,$6) } + | LHAUX reg COMMA reg COMMA reg + { `Plhaux ($2,$4,$6) } + | LWZ reg COMMA k LPAR reg RPAR + { `Plwz ($2,$4,$6) } + | LWZX reg COMMA reg COMMA reg + { `Plwzx ($2,$4,$6) } + | LWZU reg COMMA k LPAR reg RPAR + { `Plwzu ($2,$4,$6) } + | LWZUX reg COMMA reg COMMA reg + { `Plwzux ($2,$4,$6) } + | LWA reg COMMA ds LPAR reg RPAR + { `Plwa ($2,$4,$6) } + | LWAX reg COMMA reg COMMA reg + { `Plwax ($2,$4,$6) } + | LWAUX reg COMMA reg COMMA reg + { `Plwaux ($2,$4,$6) } + | LD reg COMMA ds LPAR reg RPAR + { `Pld ($2,$4,$6) } + | LDX reg COMMA reg COMMA reg + { `Pldx ($2,$4,$6) } + | LDU reg COMMA ds LPAR reg RPAR + { `Pldu ($2,$4,$6) } + | LDUX reg COMMA reg COMMA reg + { `Pldux ($2,$4,$6) } + | STB reg COMMA k LPAR reg RPAR + { `Pstb ($2,$4,$6) } + | STBX reg COMMA reg COMMA reg + { `Pstbx ($2,$4,$6) } + | STBU reg COMMA k LPAR reg RPAR + { `Pstbu ($2,$4,$6) } + | STBUX reg COMMA reg COMMA reg + { `Pstbux ($2,$4,$6) } + | STH reg COMMA k LPAR reg RPAR + { `Psth ($2,$4,$6) } + | STHX reg COMMA reg COMMA reg + { `Psthx ($2,$4,$6) } + | STHU reg COMMA k LPAR reg RPAR + { `Psthu ($2,$4,$6) } + | STHUX reg COMMA reg COMMA reg + { `Psthux ($2,$4,$6) } + | STW reg COMMA k LPAR reg RPAR + { `Pstw ($2,$4,$6) } + | STWX reg COMMA reg COMMA reg + { `Pstwx ($2,$4,$6) } + | STWU reg COMMA k LPAR reg RPAR + { `Pstwu ($2,$4,$6) } + | STWUX reg COMMA reg COMMA reg + { `Pstwux ($2,$4,$6) } + | STD reg COMMA ds LPAR reg RPAR + { `Pstd ($2,$4,$6) } + | STDX reg COMMA reg COMMA reg + { `Pstdx ($2,$4,$6) } + | STDU reg COMMA ds LPAR reg RPAR + { `Pstdu ($2,$4,$6) } + | STDUX reg COMMA reg COMMA reg + { `Pstdux ($2,$4,$6) } + | LQ k COMMA k LPAR reg RPAR COMMA k + { `Plq ($2,$4,$6,$9) } + | STQ k COMMA ds LPAR reg RPAR + { `Pstq ($2,$4,$6) } + | LHBRX reg COMMA reg COMMA reg + { `Plhbrx ($2,$4,$6) } + | STHBRX reg COMMA reg COMMA reg + { `Psthbrx ($2,$4,$6) } + | LWBRX reg COMMA reg COMMA reg + { `Plwbrx ($2,$4,$6) } + | STWBRX reg COMMA reg COMMA reg + { `Pstwbrx ($2,$4,$6) } + | LDBRX reg COMMA reg COMMA reg + { `Pldbrx ($2,$4,$6) } + | STDBRX reg COMMA reg COMMA reg + { `Pstdbrx ($2,$4,$6) } + | LMW reg COMMA k LPAR reg RPAR + { `Plmw ($2,$4,$6) } + | STMW reg COMMA k LPAR reg RPAR + { `Pstmw ($2,$4,$6) } + | LSWI k COMMA reg COMMA k + { `Plswi ($2,$4,$6) } + | LSWX reg COMMA reg COMMA reg + { `Plswx ($2,$4,$6) } + | STSWI k COMMA reg COMMA k + { `Pstswi ($2,$4,$6) } + | STSWX k COMMA reg COMMA reg + { `Pstswx ($2,$4,$6) } + | ADDI reg COMMA reg COMMA k + { `Paddi ($2,$4,$6) } + | ADDIS reg COMMA reg COMMA k + { `Paddis ($2,$4,$6) } + | ADD reg COMMA reg COMMA reg + { `Padd (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | ADDDOT reg COMMA reg COMMA reg + { `Padd (DontSetSOOV,SetCR0,$2,$4,$6) } + | ADDO reg COMMA reg COMMA reg + { `Padd (SetSOOV,DontSetCR0,$2,$4,$6) } + | ADDODOT reg COMMA reg COMMA reg + { `Padd (SetSOOV,SetCR0,$2,$4,$6) } + | SUBF reg COMMA reg COMMA reg + { `Psubf (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | SUBFDOT reg COMMA reg COMMA reg + { `Psubf (DontSetSOOV,SetCR0,$2,$4,$6) } + | SUBFO reg COMMA reg COMMA reg + { `Psubf (SetSOOV,DontSetCR0,$2,$4,$6) } + | SUBFODOT reg COMMA reg COMMA reg + { `Psubf (SetSOOV,SetCR0,$2,$4,$6) } + | ADDIC reg COMMA reg COMMA k + { `Paddic ($2,$4,$6) } + | ADDICDOT reg COMMA reg COMMA k + { `Paddicdot ($2,$4,$6) } + | SUBFIC reg COMMA reg COMMA k + { `Psubfic ($2,$4,$6) } + | ADDC reg COMMA reg COMMA reg + { `Paddc (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | ADDCDOT reg COMMA reg COMMA reg + { `Paddc (DontSetSOOV,SetCR0,$2,$4,$6) } + | ADDCO reg COMMA reg COMMA reg + { `Paddc (SetSOOV,DontSetCR0,$2,$4,$6) } + | ADDCODOT reg COMMA reg COMMA reg + { `Paddc (SetSOOV,SetCR0,$2,$4,$6) } + | SUBFC reg COMMA reg COMMA reg + { `Psubfc (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | SUBFCDOT reg COMMA reg COMMA reg + { `Psubfc (DontSetSOOV,SetCR0,$2,$4,$6) } + | SUBFCO reg COMMA reg COMMA reg + { `Psubfc (SetSOOV,DontSetCR0,$2,$4,$6) } + | SUBFCODOT reg COMMA reg COMMA reg + { `Psubfc (SetSOOV,SetCR0,$2,$4,$6) } + | ADDE reg COMMA reg COMMA reg + { `Padde (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | ADDEDOT reg COMMA reg COMMA reg + { `Padde (DontSetSOOV,SetCR0,$2,$4,$6) } + | ADDEO reg COMMA reg COMMA reg + { `Padde (SetSOOV,DontSetCR0,$2,$4,$6) } + | ADDEODOT reg COMMA reg COMMA reg + { `Padde (SetSOOV,SetCR0,$2,$4,$6) } + | SUBFE reg COMMA reg COMMA reg + { `Psubfe (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | SUBFEDOT reg COMMA reg COMMA reg + { `Psubfe (DontSetSOOV,SetCR0,$2,$4,$6) } + | SUBFEO reg COMMA reg COMMA reg + { `Psubfe (SetSOOV,DontSetCR0,$2,$4,$6) } + | SUBFEODOT reg COMMA reg COMMA reg + { `Psubfe (SetSOOV,SetCR0,$2,$4,$6) } + | ADDME reg COMMA reg + { `Paddme (DontSetSOOV,DontSetCR0,$2,$4) } + | ADDMEDOT reg COMMA reg + { `Paddme (DontSetSOOV,SetCR0,$2,$4) } + | ADDMEO reg COMMA reg + { `Paddme (SetSOOV,DontSetCR0,$2,$4) } + | ADDMEODOT reg COMMA reg + { `Paddme (SetSOOV,SetCR0,$2,$4) } + | SUBFME reg COMMA reg + { `Psubfme (DontSetSOOV,DontSetCR0,$2,$4) } + | SUBFMEDOT reg COMMA reg + { `Psubfme (DontSetSOOV,SetCR0,$2,$4) } + | SUBFMEO reg COMMA reg + { `Psubfme (SetSOOV,DontSetCR0,$2,$4) } + | SUBFMEODOT reg COMMA reg + { `Psubfme (SetSOOV,SetCR0,$2,$4) } + | ADDZE reg COMMA reg + { `Paddze (DontSetSOOV,DontSetCR0,$2,$4) } + | ADDZEDOT reg COMMA reg + { `Paddze (DontSetSOOV,SetCR0,$2,$4) } + | ADDZEO reg COMMA reg + { `Paddze (SetSOOV,DontSetCR0,$2,$4) } + | ADDZEODOT reg COMMA reg + { `Paddze (SetSOOV,SetCR0,$2,$4) } + | SUBFZE reg COMMA reg + { `Psubfze (DontSetSOOV,DontSetCR0,$2,$4) } + | SUBFZEDOT reg COMMA reg + { `Psubfze (DontSetSOOV,SetCR0,$2,$4) } + | SUBFZEO reg COMMA reg + { `Psubfze (SetSOOV,DontSetCR0,$2,$4) } + | SUBFZEODOT reg COMMA reg + { `Psubfze (SetSOOV,SetCR0,$2,$4) } + | NEG reg COMMA reg + { `Pneg (DontSetSOOV,DontSetCR0,$2,$4) } + | NEGDOT reg COMMA reg + { `Pneg (DontSetSOOV,SetCR0,$2,$4) } + | NEGO reg COMMA reg + { `Pneg (SetSOOV,DontSetCR0,$2,$4) } + | NEGODOT reg COMMA reg + { `Pneg (SetSOOV,SetCR0,$2,$4) } + | MULLI reg COMMA reg COMMA k + { `Pmulli ($2,$4,$6) } + | MULLW reg COMMA reg COMMA reg + { `Pmullw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MULLWDOT reg COMMA reg COMMA reg + { `Pmullw (DontSetSOOV,SetCR0,$2,$4,$6) } + | MULLWO reg COMMA reg COMMA reg + { `Pmullw (SetSOOV,DontSetCR0,$2,$4,$6) } + | MULLWODOT reg COMMA reg COMMA reg + { `Pmullw (SetSOOV,SetCR0,$2,$4,$6) } + | MULHW reg COMMA reg COMMA reg + { `Pmulhw (DontSetCR0,$2,$4,$6) } + | MULHWDOT reg COMMA reg COMMA reg + { `Pmulhw (SetCR0,$2,$4,$6) } + | MULHWU reg COMMA reg COMMA reg + { `Pmulhwu (DontSetCR0,$2,$4,$6) } + | MULHWUDOT reg COMMA reg COMMA reg + { `Pmulhwu (SetCR0,$2,$4,$6) } + | DIVW reg COMMA reg COMMA reg + { `Pdivw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWDOT reg COMMA reg COMMA reg + { `Pdivw (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVWO reg COMMA reg COMMA reg + { `Pdivw (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWODOT reg COMMA reg COMMA reg + { `Pdivw (SetSOOV,SetCR0,$2,$4,$6) } + | DIVWU reg COMMA reg COMMA reg + { `Pdivwu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWUDOT reg COMMA reg COMMA reg + { `Pdivwu (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVWUO reg COMMA reg COMMA reg + { `Pdivwu (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWUODOT reg COMMA reg COMMA reg + { `Pdivwu (SetSOOV,SetCR0,$2,$4,$6) } + | DIVWE reg COMMA reg COMMA reg + { `Pdivwe (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWEDOT reg COMMA reg COMMA reg + { `Pdivwe (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVWEO reg COMMA reg COMMA reg + { `Pdivwe (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWEODOT reg COMMA reg COMMA reg + { `Pdivwe (SetSOOV,SetCR0,$2,$4,$6) } + | DIVWEU reg COMMA reg COMMA reg + { `Pdivweu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWEUDOT reg COMMA reg COMMA reg + { `Pdivweu (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVWEUO reg COMMA reg COMMA reg + { `Pdivweu (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVWEUODOT reg COMMA reg COMMA reg + { `Pdivweu (SetSOOV,SetCR0,$2,$4,$6) } + | MULLD reg COMMA reg COMMA reg + { `Pmulld (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MULLDDOT reg COMMA reg COMMA reg + { `Pmulld (DontSetSOOV,SetCR0,$2,$4,$6) } + | MULLDO reg COMMA reg COMMA reg + { `Pmulld (SetSOOV,DontSetCR0,$2,$4,$6) } + | MULLDODOT reg COMMA reg COMMA reg + { `Pmulld (SetSOOV,SetCR0,$2,$4,$6) } + | MULHD reg COMMA reg COMMA reg + { `Pmulhd (DontSetCR0,$2,$4,$6) } + | MULHDDOT reg COMMA reg COMMA reg + { `Pmulhd (SetCR0,$2,$4,$6) } + | MULHDU reg COMMA reg COMMA reg + { `Pmulhdu (DontSetCR0,$2,$4,$6) } + | MULHDUDOT reg COMMA reg COMMA reg + { `Pmulhdu (SetCR0,$2,$4,$6) } + | DIVD reg COMMA reg COMMA reg + { `Pdivd (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDDOT reg COMMA reg COMMA reg + { `Pdivd (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVDO reg COMMA reg COMMA reg + { `Pdivd (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDODOT reg COMMA reg COMMA reg + { `Pdivd (SetSOOV,SetCR0,$2,$4,$6) } + | DIVDU reg COMMA reg COMMA reg + { `Pdivdu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDUDOT reg COMMA reg COMMA reg + { `Pdivdu (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVDUO reg COMMA reg COMMA reg + { `Pdivdu (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDUODOT reg COMMA reg COMMA reg + { `Pdivdu (SetSOOV,SetCR0,$2,$4,$6) } + | DIVDE reg COMMA reg COMMA reg + { `Pdivde (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDEDOT reg COMMA reg COMMA reg + { `Pdivde (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVDEO reg COMMA reg COMMA reg + { `Pdivde (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDEODOT reg COMMA reg COMMA reg + { `Pdivde (SetSOOV,SetCR0,$2,$4,$6) } + | DIVDEU reg COMMA reg COMMA reg + { `Pdivdeu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDEUDOT reg COMMA reg COMMA reg + { `Pdivdeu (DontSetSOOV,SetCR0,$2,$4,$6) } + | DIVDEUO reg COMMA reg COMMA reg + { `Pdivdeu (SetSOOV,DontSetCR0,$2,$4,$6) } + | DIVDEUODOT reg COMMA reg COMMA reg + { `Pdivdeu (SetSOOV,SetCR0,$2,$4,$6) } + | CMPI crindex COMMA k COMMA reg COMMA k + { `Pcmpi ($2,$4,$6,$8) } + | CMP crindex COMMA k COMMA reg COMMA reg + { `Pcmp ($2,$4,$6,$8) } + | CMPLI crindex COMMA k COMMA reg COMMA k + { `Pcmpli ($2,$4,$6,$8) } + | CMPL crindex COMMA k COMMA reg COMMA reg + { `Pcmpl ($2,$4,$6,$8) } + | ISEL reg COMMA reg COMMA reg COMMA k + { `Pisel ($2,$4,$6,$8) } + | ANDIDOT reg COMMA reg COMMA k + { `Pandi ($2,$4,$6) } + | ANDISDOT reg COMMA reg COMMA k + { `Pandis ($2,$4,$6) } + | ORI reg COMMA reg COMMA k + { `Pori ($2,$4,$6) } + | ORIS reg COMMA reg COMMA k + { `Poris ($2,$4,$6) } + | XORI reg COMMA reg COMMA k + { `Pxori ($2,$4,$6) } + | XORIS reg COMMA reg COMMA k + { `Pxoris ($2,$4,$6) } + | AND reg COMMA reg COMMA reg + { `Pand (DontSetCR0,$2,$4,$6) } + | ANDDOT reg COMMA reg COMMA reg + { `Pand (SetCR0,$2,$4,$6) } + | XOR reg COMMA reg COMMA reg + { `Pxor (DontSetCR0,$2,$4,$6) } + | XORDOT reg COMMA reg COMMA reg + { `Pxor (SetCR0,$2,$4,$6) } + | NAND reg COMMA reg COMMA reg + { `Pnand (DontSetCR0,$2,$4,$6) } + | NANDDOT reg COMMA reg COMMA reg + { `Pnand (SetCR0,$2,$4,$6) } + | OR reg COMMA reg COMMA reg + { `Por (DontSetCR0,$2,$4,$6) } + | ORDOT reg COMMA reg COMMA reg + { `Por (SetCR0,$2,$4,$6) } + | NOR reg COMMA reg COMMA reg + { `Pnor (DontSetCR0,$2,$4,$6) } + | NORDOT reg COMMA reg COMMA reg + { `Pnor (SetCR0,$2,$4,$6) } + | EQV reg COMMA reg COMMA reg + { `Peqv (DontSetCR0,$2,$4,$6) } + | EQVDOT reg COMMA reg COMMA reg + { `Peqv (SetCR0,$2,$4,$6) } + | ANDC reg COMMA reg COMMA reg + { `Pandc (DontSetCR0,$2,$4,$6) } + | ANDCDOT reg COMMA reg COMMA reg + { `Pandc (SetCR0,$2,$4,$6) } + | ORC reg COMMA reg COMMA reg + { `Porc (DontSetCR0,$2,$4,$6) } + | ORCDOT reg COMMA reg COMMA reg + { `Porc (SetCR0,$2,$4,$6) } + | EXTSB reg COMMA reg + { `Pextsb (DontSetCR0,$2,$4) } + | EXTSBDOT reg COMMA reg + { `Pextsb (SetCR0,$2,$4) } + | EXTSH reg COMMA reg + { `Pextsh (DontSetCR0,$2,$4) } + | EXTSHDOT reg COMMA reg + { `Pextsh (SetCR0,$2,$4) } + | CNTLZW reg COMMA reg + { `Pcntlzw (DontSetCR0,$2,$4) } + | CNTLZWDOT reg COMMA reg + { `Pcntlzw (SetCR0,$2,$4) } + | CMPB reg COMMA k COMMA reg + { `Pcmpb ($2,$4,$6) } + | POPCNTB reg COMMA reg + { `Ppopcntb ($2,$4) } + | POPCNTW reg COMMA reg + { `Ppopcntw ($2,$4) } + | PRTYD reg COMMA reg + { `Pprtyd ($2,$4) } + | PRTYW reg COMMA reg + { `Pprtyw ($2,$4) } + | EXTSW reg COMMA reg + { `Pextsw (DontSetCR0,$2,$4) } + | EXTSWDOT reg COMMA reg + { `Pextsw (SetCR0,$2,$4) } + | CNTLZD reg COMMA reg + { `Pcntlzd (DontSetCR0,$2,$4) } + | CNTLZDDOT reg COMMA reg + { `Pcntlzd (SetCR0,$2,$4) } + | POPCNTD reg COMMA reg + { `Ppopcntd ($2,$4) } + | BPERMD reg COMMA reg COMMA reg + { `Pbpermd ($2,$4,$6) } + | RLWINM reg COMMA reg COMMA k COMMA k COMMA k + { `Prlwinm (DontSetCR0,$2,$4,$6,$8,$10) } + | RLWINMDOT reg COMMA reg COMMA k COMMA k COMMA k + { `Prlwinm (SetCR0,$2,$4,$6,$8,$10) } + | RLWNM reg COMMA reg COMMA reg COMMA k COMMA k + { `Prlwnm (DontSetCR0,$2,$4,$6,$8,$10) } + | RLWNMDOT reg COMMA reg COMMA reg COMMA k COMMA k + { `Prlwnm (SetCR0,$2,$4,$6,$8,$10) } + | RLWIMI reg COMMA reg COMMA k COMMA k COMMA k + { `Prlwimi (DontSetCR0,$2,$4,$6,$8,$10) } + | RLWIMIDOT reg COMMA reg COMMA k COMMA k COMMA k + { `Prlwimi (SetCR0,$2,$4,$6,$8,$10) } + | RLDICL reg COMMA reg COMMA k COMMA k + { `Prldicl (DontSetCR0,$2,$4,$6,$8) } + | RLDICLDOT reg COMMA reg COMMA k COMMA k + { `Prldicl (SetCR0,$2,$4,$6,$8) } + | RLDICR reg COMMA reg COMMA k COMMA k + { `Prldicr (DontSetCR0,$2,$4,$6,$8) } + | RLDICRDOT reg COMMA reg COMMA k COMMA k + { `Prldicr (SetCR0,$2,$4,$6,$8) } + | RLDIC reg COMMA reg COMMA k COMMA k + { `Prldic (DontSetCR0,$2,$4,$6,$8) } + | RLDICDOT reg COMMA reg COMMA k COMMA k + { `Prldic (SetCR0,$2,$4,$6,$8) } + | RLDCL reg COMMA reg COMMA reg COMMA k + { `Prldcl (DontSetCR0,$2,$4,$6,$8) } + | RLDCLDOT reg COMMA reg COMMA reg COMMA k + { `Prldcl (SetCR0,$2,$4,$6,$8) } + | RLDCR reg COMMA reg COMMA reg COMMA k + { `Prldcr (DontSetCR0,$2,$4,$6,$8) } + | RLDCRDOT reg COMMA reg COMMA reg COMMA k + { `Prldcr (SetCR0,$2,$4,$6,$8) } + | RLDIMI reg COMMA reg COMMA k COMMA k + { `Prldimi (DontSetCR0,$2,$4,$6,$8) } + | RLDIMIDOT reg COMMA reg COMMA k COMMA k + { `Prldimi (SetCR0,$2,$4,$6,$8) } + | SLW reg COMMA reg COMMA reg + { `Pslw (DontSetCR0,$2,$4,$6) } + | SLWDOT reg COMMA reg COMMA reg + { `Pslw (SetCR0,$2,$4,$6) } + | SRW reg COMMA reg COMMA reg + { `Psrw (DontSetCR0,$2,$4,$6) } + | SRWDOT reg COMMA reg COMMA reg + { `Psrw (SetCR0,$2,$4,$6) } + | SRAWI reg COMMA reg COMMA k + { `Psrawi (DontSetCR0,$2,$4,$6) } + | SRAWIDOT reg COMMA reg COMMA k + { `Psrawi (SetCR0,$2,$4,$6) } + | SRAW reg COMMA reg COMMA reg + { `Psraw (DontSetCR0,$2,$4,$6) } + | SRAWDOT reg COMMA reg COMMA reg + { `Psraw (SetCR0,$2,$4,$6) } + | SLD reg COMMA reg COMMA reg + { `Psld (DontSetCR0,$2,$4,$6) } + | SLDDOT reg COMMA reg COMMA reg + { `Psld (SetCR0,$2,$4,$6) } + | SRD reg COMMA reg COMMA reg + { `Psrd (DontSetCR0,$2,$4,$6) } + | SRDDOT reg COMMA reg COMMA reg + { `Psrd (SetCR0,$2,$4,$6) } + | SRADI reg COMMA reg COMMA k + { `Psradi (DontSetCR0,$2,$4,$6) } + | SRADIDOT reg COMMA reg COMMA k + { `Psradi (SetCR0,$2,$4,$6) } + | SRAD reg COMMA reg COMMA reg + { `Psrad (DontSetCR0,$2,$4,$6) } + | SRADDOT reg COMMA reg COMMA reg + { `Psrad (SetCR0,$2,$4,$6) } + | CDTBCD reg COMMA reg + { `Pcdtbcd ($2,$4) } + | CBCDTD reg COMMA reg + { `Pcbcdtd ($2,$4) } + | ADDG6S reg COMMA reg COMMA reg + { `Paddg6s ($2,$4,$6) } + | MTSPR k COMMA reg + { `Pmtspr ($2,$4) } + | MFSPR reg COMMA k + { `Pmfspr ($2,$4) } + | MTCRF crmask COMMA reg + { `Pmtcrf ($2,$4) } + | MFCR reg + { `Pmfcr ($2) } + | MTOCRF crmask COMMA reg + { `Pmtocrf ($2,$4) } + | MFOCRF reg COMMA crmask + { `Pmfocrf ($2,$4) } + | MCRXR crindex + { `Pmcrxr ($2) } + | DLMZB reg COMMA reg COMMA reg + { `Pdlmzb (DontSetCR0,$2,$4,$6) } + | DLMZBDOT reg COMMA reg COMMA reg + { `Pdlmzb (SetCR0,$2,$4,$6) } + | MACCHW reg COMMA reg COMMA reg + { `Pmacchw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWDOT reg COMMA reg COMMA reg + { `Pmacchw (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACCHWO reg COMMA reg COMMA reg + { `Pmacchw (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWODOT reg COMMA reg COMMA reg + { `Pmacchw (SetSOOV,SetCR0,$2,$4,$6) } + | MACCHWS reg COMMA reg COMMA reg + { `Pmacchws (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWSDOT reg COMMA reg COMMA reg + { `Pmacchws (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACCHWSO reg COMMA reg COMMA reg + { `Pmacchws (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWSODOT reg COMMA reg COMMA reg + { `Pmacchws (SetSOOV,SetCR0,$2,$4,$6) } + | MACCHWU reg COMMA reg COMMA reg + { `Pmacchwu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWUDOT reg COMMA reg COMMA reg + { `Pmacchwu (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACCHWUO reg COMMA reg COMMA reg + { `Pmacchwu (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWUODOT reg COMMA reg COMMA reg + { `Pmacchwu (SetSOOV,SetCR0,$2,$4,$6) } + | MACCHWSU reg COMMA reg COMMA reg + { `Pmacchwsu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWSUDOT reg COMMA reg COMMA reg + { `Pmacchwsu (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACCHWSUO reg COMMA reg COMMA reg + { `Pmacchwsu (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACCHWSUODOT reg COMMA reg COMMA reg + { `Pmacchwsu (SetSOOV,SetCR0,$2,$4,$6) } + | MACHHW reg COMMA reg COMMA reg + { `Pmachhw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWDOT reg COMMA reg COMMA reg + { `Pmachhw (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACHHWO reg COMMA reg COMMA reg + { `Pmachhw (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWODOT reg COMMA reg COMMA reg + { `Pmachhw (SetSOOV,SetCR0,$2,$4,$6) } + | MACHHWS reg COMMA reg COMMA reg + { `Pmachhws (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWSDOT reg COMMA reg COMMA reg + { `Pmachhws (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACHHWSO reg COMMA reg COMMA reg + { `Pmachhws (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWSODOT reg COMMA reg COMMA reg + { `Pmachhws (SetSOOV,SetCR0,$2,$4,$6) } + | MACHHWU reg COMMA reg COMMA reg + { `Pmachhwu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWUDOT reg COMMA reg COMMA reg + { `Pmachhwu (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACHHWUO reg COMMA reg COMMA reg + { `Pmachhwu (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWUODOT reg COMMA reg COMMA reg + { `Pmachhwu (SetSOOV,SetCR0,$2,$4,$6) } + | MACHHWSU reg COMMA reg COMMA reg + { `Pmachhwsu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWSUDOT reg COMMA reg COMMA reg + { `Pmachhwsu (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACHHWSUO reg COMMA reg COMMA reg + { `Pmachhwsu (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACHHWSUODOT reg COMMA reg COMMA reg + { `Pmachhwsu (SetSOOV,SetCR0,$2,$4,$6) } + | MACLHW reg COMMA reg COMMA reg + { `Pmaclhw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWDOT reg COMMA reg COMMA reg + { `Pmaclhw (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACLHWO reg COMMA reg COMMA reg + { `Pmaclhw (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWODOT reg COMMA reg COMMA reg + { `Pmaclhw (SetSOOV,SetCR0,$2,$4,$6) } + | MACLHWS reg COMMA reg COMMA reg + { `Pmaclhws (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWSDOT reg COMMA reg COMMA reg + { `Pmaclhws (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACLHWSO reg COMMA reg COMMA reg + { `Pmaclhws (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWSODOT reg COMMA reg COMMA reg + { `Pmaclhws (SetSOOV,SetCR0,$2,$4,$6) } + | MACLHWU reg COMMA reg COMMA reg + { `Pmaclhwu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWUDOT reg COMMA reg COMMA reg + { `Pmaclhwu (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACLHWUO reg COMMA reg COMMA reg + { `Pmaclhwu (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWUODOT reg COMMA reg COMMA reg + { `Pmaclhwu (SetSOOV,SetCR0,$2,$4,$6) } + | MACLHWSU reg COMMA reg COMMA reg + { `Pmaclhwsu (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWSUDOT reg COMMA reg COMMA reg + { `Pmaclhwsu (DontSetSOOV,SetCR0,$2,$4,$6) } + | MACLHWSUO reg COMMA reg COMMA reg + { `Pmaclhwsu (SetSOOV,DontSetCR0,$2,$4,$6) } + | MACLHWSUODOT reg COMMA reg COMMA reg + { `Pmaclhwsu (SetSOOV,SetCR0,$2,$4,$6) } + | MULCHW reg COMMA reg COMMA reg + { `Pmulchw (DontSetCR0,$2,$4,$6) } + | MULCHWDOT reg COMMA reg COMMA reg + { `Pmulchw (SetCR0,$2,$4,$6) } + | MULCHWU reg COMMA reg COMMA reg + { `Pmulchwu (DontSetCR0,$2,$4,$6) } + | MULCHWUDOT reg COMMA reg COMMA reg + { `Pmulchwu (SetCR0,$2,$4,$6) } + | MULHHW reg COMMA reg COMMA reg + { `Pmulhhw (DontSetCR0,$2,$4,$6) } + | MULHHWDOT reg COMMA reg COMMA reg + { `Pmulhhw (SetCR0,$2,$4,$6) } + | MULHHWU reg COMMA reg COMMA reg + { `Pmulhhwu (DontSetCR0,$2,$4,$6) } + | MULHHWUDOT reg COMMA reg COMMA reg + { `Pmulhhwu (SetCR0,$2,$4,$6) } + | MULLHW reg COMMA reg COMMA reg + { `Pmullhw (DontSetCR0,$2,$4,$6) } + | MULLHWDOT reg COMMA reg COMMA reg + { `Pmullhw (SetCR0,$2,$4,$6) } + | MULLHWU reg COMMA reg COMMA reg + { `Pmullhwu (DontSetCR0,$2,$4,$6) } + | MULLHWUDOT reg COMMA reg COMMA reg + { `Pmullhwu (SetCR0,$2,$4,$6) } + | NMACCHW reg COMMA reg COMMA reg + { `Pnmacchw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | NMACCHWDOT reg COMMA reg COMMA reg + { `Pnmacchw (DontSetSOOV,SetCR0,$2,$4,$6) } + | NMACCHWO reg COMMA reg COMMA reg + { `Pnmacchw (SetSOOV,DontSetCR0,$2,$4,$6) } + | NMACCHWODOT reg COMMA reg COMMA reg + { `Pnmacchw (SetSOOV,SetCR0,$2,$4,$6) } + | NMACCHWS reg COMMA reg COMMA reg + { `Pnmacchws (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | NMACCHWSDOT reg COMMA reg COMMA reg + { `Pnmacchws (DontSetSOOV,SetCR0,$2,$4,$6) } + | NMACCHWSO reg COMMA reg COMMA reg + { `Pnmacchws (SetSOOV,DontSetCR0,$2,$4,$6) } + | NMACCHWSODOT reg COMMA reg COMMA reg + { `Pnmacchws (SetSOOV,SetCR0,$2,$4,$6) } + | NMACHHW reg COMMA reg COMMA reg + { `Pnmachhw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | NMACHHWDOT reg COMMA reg COMMA reg + { `Pnmachhw (DontSetSOOV,SetCR0,$2,$4,$6) } + | NMACHHWO reg COMMA reg COMMA reg + { `Pnmachhw (SetSOOV,DontSetCR0,$2,$4,$6) } + | NMACHHWODOT reg COMMA reg COMMA reg + { `Pnmachhw (SetSOOV,SetCR0,$2,$4,$6) } + | NMACHHWS reg COMMA reg COMMA reg + { `Pnmachhws (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | NMACHHWSDOT reg COMMA reg COMMA reg + { `Pnmachhws (DontSetSOOV,SetCR0,$2,$4,$6) } + | NMACHHWSO reg COMMA reg COMMA reg + { `Pnmachhws (SetSOOV,DontSetCR0,$2,$4,$6) } + | NMACHHWSODOT reg COMMA reg COMMA reg + { `Pnmachhws (SetSOOV,SetCR0,$2,$4,$6) } + | NMACLHW reg COMMA reg COMMA reg + { `Pnmaclhw (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | NMACLHWDOT reg COMMA reg COMMA reg + { `Pnmaclhw (DontSetSOOV,SetCR0,$2,$4,$6) } + | NMACLHWO reg COMMA reg COMMA reg + { `Pnmaclhw (SetSOOV,DontSetCR0,$2,$4,$6) } + | NMACLHWODOT reg COMMA reg COMMA reg + { `Pnmaclhw (SetSOOV,SetCR0,$2,$4,$6) } + | NMACLHWS reg COMMA reg COMMA reg + { `Pnmaclhws (DontSetSOOV,DontSetCR0,$2,$4,$6) } + | NMACLHWSDOT reg COMMA reg COMMA reg + { `Pnmaclhws (DontSetSOOV,SetCR0,$2,$4,$6) } + | NMACLHWSO reg COMMA reg COMMA reg + { `Pnmaclhws (SetSOOV,DontSetCR0,$2,$4,$6) } + | NMACLHWSODOT reg COMMA reg COMMA reg + { `Pnmaclhws (SetSOOV,SetCR0,$2,$4,$6) } + | ICBI reg COMMA reg + { `Picbi ($2,$4) } + | ICBT k COMMA reg COMMA reg + { `Picbt ($2,$4,$6) } + | DCBA reg COMMA reg + { `Pdcba ($2,$4) } + | DCBT reg COMMA reg COMMA k + { `Pdcbt ($2,$4,$6) } + | DCBTST reg COMMA reg COMMA k + { `Pdcbtst ($2,$4,$6) } + | DCBZ reg COMMA reg + { `Pdcbz ($2,$4) } + | DCBST reg COMMA reg + { `Pdcbst ($2,$4) } + | DCBF reg COMMA reg COMMA k + { `Pdcbf ($2,$4,$6) } + | ISYNC + { `Pisync } + | LBARX reg COMMA reg COMMA reg COMMA k + { `Plbarx ($2,$4,$6,$8) } + | LHARX reg COMMA reg COMMA reg COMMA k + { `Plharx ($2,$4,$6,$8) } + | LWARX reg COMMA reg COMMA reg COMMA k + { `Plwarx ($2,$4,$6,$8) } + | STBCXDOT reg COMMA reg COMMA reg + { `Pstbcx ($2,$4,$6) } + | STHCXDOT reg COMMA reg COMMA reg + { `Psthcx ($2,$4,$6) } + | STWCXDOT reg COMMA reg COMMA reg + { `Pstwcx ($2,$4,$6) } + | LDARX reg COMMA reg COMMA reg COMMA k + { `Pldarx ($2,$4,$6,$8) } + | STDCXDOT reg COMMA reg COMMA reg + { `Pstdcx ($2,$4,$6) } + | SYNC k + { `Psync ($2) } + | EIEIO + { `Peieio } + | WAIT k + { `Pwait ($2) } diff --git a/old/power/gen/pretty.gen b/old/power/gen/pretty.gen new file mode 100644 index 00000000..4a7eff69 --- /dev/null +++ b/old/power/gen/pretty.gen @@ -0,0 +1,368 @@ +| `Pb (DontSetAA,DontSetLK,target_addr) -> sprintf "b %d" target_addr +| `Pb (SetAA,DontSetLK,target_addr) -> sprintf "ba %d" target_addr +| `Pb (DontSetAA,SetLK,target_addr) -> sprintf "bl %d" target_addr +| `Pb (SetAA,SetLK,target_addr) -> sprintf "bla %d" target_addr +| `Pbc (DontSetAA,DontSetLK,bO,bI,target_addr) -> sprintf "bc %d,%d,%d" bO bI target_addr +| `Pbc (SetAA,DontSetLK,bO,bI,target_addr) -> sprintf "bca %d,%d,%d" bO bI target_addr +| `Pbc (DontSetAA,SetLK,bO,bI,target_addr) -> sprintf "bcl %d,%d,%d" bO bI target_addr +| `Pbc (SetAA,SetLK,bO,bI,target_addr) -> sprintf "bcla %d,%d,%d" bO bI target_addr +| `Pbclr (DontSetLK,bO,bI,bH) -> sprintf "bclr %d,%d,%d" bO bI bH +| `Pbclr (SetLK,bO,bI,bH) -> sprintf "bclrl %d,%d,%d" bO bI bH +| `Pbcctr (DontSetLK,bO,bI,bH) -> sprintf "bcctr %d,%d,%d" bO bI bH +| `Pbcctr (SetLK,bO,bI,bH) -> sprintf "bcctrl %d,%d,%d" bO bI bH +| `Pcrand (bT,bA,bB) -> sprintf "crand %d,%d,%d" bT bA bB +| `Pcrnand (bT,bA,bB) -> sprintf "crnand %d,%d,%d" bT bA bB +| `Pcror (bT,bA,bB) -> sprintf "cror %d,%d,%d" bT bA bB +| `Pcrxor (bT,bA,bB) -> sprintf "crxor %d,%d,%d" bT bA bB +| `Pcrnor (bT,bA,bB) -> sprintf "crnor %d,%d,%d" bT bA bB +| `Pcreqv (bT,bA,bB) -> sprintf "creqv %d,%d,%d" bT bA bB +| `Pcrandc (bT,bA,bB) -> sprintf "crandc %d,%d,%d" bT bA bB +| `Pcrorc (bT,bA,bB) -> sprintf "crorc %d,%d,%d" bT bA bB +| `Pmcrf (bF,bFA) -> sprintf "mcrf %s,%d" (pp_crf bF) bFA +| `Psc (lEV) -> sprintf "sc %d" lEV +| `Pscv (lEV) -> sprintf "scv %d" lEV +| `Plbz (rT,d,rA) -> sprintf "lbz %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plbzx (rT,rA,rB) -> sprintf "lbzx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plbzu (rT,d,rA) -> sprintf "lbzu %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plbzux (rT,rA,rB) -> sprintf "lbzux %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plhz (rT,d,rA) -> sprintf "lhz %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plhzx (rT,rA,rB) -> sprintf "lhzx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plhzu (rT,d,rA) -> sprintf "lhzu %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plhzux (rT,rA,rB) -> sprintf "lhzux %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plha (rT,d,rA) -> sprintf "lha %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plhax (rT,rA,rB) -> sprintf "lhax %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plhau (rT,d,rA) -> sprintf "lhau %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plhaux (rT,rA,rB) -> sprintf "lhaux %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plwz (rT,d,rA) -> sprintf "lwz %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plwzx (rT,rA,rB) -> sprintf "lwzx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plwzu (rT,d,rA) -> sprintf "lwzu %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Plwzux (rT,rA,rB) -> sprintf "lwzux %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plwa (rT,dS,rA) -> sprintf "lwa %s,%s(%s)" (pp_reg rT) (pp_ds dS) (pp_reg rA) +| `Plwax (rT,rA,rB) -> sprintf "lwax %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Plwaux (rT,rA,rB) -> sprintf "lwaux %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pld (rT,dS,rA) -> sprintf "ld %s,%s(%s)" (pp_reg rT) (pp_ds dS) (pp_reg rA) +| `Pldx (rT,rA,rB) -> sprintf "ldx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pldu (rT,dS,rA) -> sprintf "ldu %s,%s(%s)" (pp_reg rT) (pp_ds dS) (pp_reg rA) +| `Pldux (rT,rA,rB) -> sprintf "ldux %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pstb (rS,d,rA) -> sprintf "stb %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Pstbx (rS,rA,rB) -> sprintf "stbx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pstbu (rS,d,rA) -> sprintf "stbu %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Pstbux (rS,rA,rB) -> sprintf "stbux %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Psth (rS,d,rA) -> sprintf "sth %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Psthx (rS,rA,rB) -> sprintf "sthx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Psthu (rS,d,rA) -> sprintf "sthu %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Psthux (rS,rA,rB) -> sprintf "sthux %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pstw (rS,d,rA) -> sprintf "stw %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Pstwx (rS,rA,rB) -> sprintf "stwx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pstwu (rS,d,rA) -> sprintf "stwu %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Pstwux (rS,rA,rB) -> sprintf "stwux %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pstd (rS,dS,rA) -> sprintf "std %s,%s(%s)" (pp_reg rS) (pp_ds dS) (pp_reg rA) +| `Pstdx (rS,rA,rB) -> sprintf "stdx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pstdu (rS,dS,rA) -> sprintf "stdu %s,%s(%s)" (pp_reg rS) (pp_ds dS) (pp_reg rA) +| `Pstdux (rS,rA,rB) -> sprintf "stdux %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Plq (rTp,dQ,rA,pT) -> sprintf "lq %d,%d(%s),%d" rTp dQ (pp_reg rA) pT +| `Pstq (rSp,dS,rA) -> sprintf "stq %d,%s(%s)" rSp (pp_ds dS) (pp_reg rA) +| `Plhbrx (rT,rA,rB) -> sprintf "lhbrx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psthbrx (rS,rA,rB) -> sprintf "sthbrx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Plwbrx (rT,rA,rB) -> sprintf "lwbrx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pstwbrx (rS,rA,rB) -> sprintf "stwbrx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pldbrx (rT,rA,rB) -> sprintf "ldbrx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pstdbrx (rS,rA,rB) -> sprintf "stdbrx %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Plmw (rT,d,rA) -> sprintf "lmw %s,%d(%s)" (pp_reg rT) d (pp_reg rA) +| `Pstmw (rS,d,rA) -> sprintf "stmw %s,%d(%s)" (pp_reg rS) d (pp_reg rA) +| `Plswi (rT,rA,nB) -> sprintf "lswi %d,%s,%d" rT (pp_reg rA) nB +| `Plswx (rT,rA,rB) -> sprintf "lswx %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pstswi (rS,rA,nB) -> sprintf "stswi %d,%s,%d" rS (pp_reg rA) nB +| `Pstswx (rS,rA,rB) -> sprintf "stswx %d,%s,%s" rS (pp_reg rA) (pp_reg rB) +| `Paddi (rT,rA,sI) -> sprintf "addi %s,%s,%d" (pp_reg rT) (pp_reg rA) sI +| `Paddis (rT,rA,sI) -> sprintf "addis %s,%s,%d" (pp_reg rT) (pp_reg rA) sI +| `Padd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "add %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padd (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "add. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padd (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "addo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padd (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "addo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubf (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "subf %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubf (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "subf. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubf (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "subfo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubf (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "subfo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Paddic (rT,rA,sI) -> sprintf "addic %s,%s,%d" (pp_reg rT) (pp_reg rA) sI +| `Paddicdot (rT,rA,sI) -> sprintf "addic. %s,%s,%d" (pp_reg rT) (pp_reg rA) sI +| `Psubfic (rT,rA,sI) -> sprintf "subfic %s,%s,%d" (pp_reg rT) (pp_reg rA) sI +| `Paddc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "addc %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Paddc (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "addc. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Paddc (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "addco %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Paddc (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "addco. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfc (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "subfc %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfc (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "subfc. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfc (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "subfco %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfc (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "subfco. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "adde %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padde (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "adde. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padde (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "addeo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Padde (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "addeo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "subfe %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfe (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "subfe. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfe (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "subfeo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Psubfe (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "subfeo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Paddme (DontSetSOOV,DontSetCR0,rT,rA) -> sprintf "addme %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddme (DontSetSOOV,SetCR0,rT,rA) -> sprintf "addme. %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddme (SetSOOV,DontSetCR0,rT,rA) -> sprintf "addmeo %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddme (SetSOOV,SetCR0,rT,rA) -> sprintf "addmeo. %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfme (DontSetSOOV,DontSetCR0,rT,rA) -> sprintf "subfme %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfme (DontSetSOOV,SetCR0,rT,rA) -> sprintf "subfme. %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfme (SetSOOV,DontSetCR0,rT,rA) -> sprintf "subfmeo %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfme (SetSOOV,SetCR0,rT,rA) -> sprintf "subfmeo. %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddze (DontSetSOOV,DontSetCR0,rT,rA) -> sprintf "addze %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddze (DontSetSOOV,SetCR0,rT,rA) -> sprintf "addze. %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddze (SetSOOV,DontSetCR0,rT,rA) -> sprintf "addzeo %s,%s" (pp_reg rT) (pp_reg rA) +| `Paddze (SetSOOV,SetCR0,rT,rA) -> sprintf "addzeo. %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfze (DontSetSOOV,DontSetCR0,rT,rA) -> sprintf "subfze %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfze (DontSetSOOV,SetCR0,rT,rA) -> sprintf "subfze. %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfze (SetSOOV,DontSetCR0,rT,rA) -> sprintf "subfzeo %s,%s" (pp_reg rT) (pp_reg rA) +| `Psubfze (SetSOOV,SetCR0,rT,rA) -> sprintf "subfzeo. %s,%s" (pp_reg rT) (pp_reg rA) +| `Pneg (DontSetSOOV,DontSetCR0,rT,rA) -> sprintf "neg %s,%s" (pp_reg rT) (pp_reg rA) +| `Pneg (DontSetSOOV,SetCR0,rT,rA) -> sprintf "neg. %s,%s" (pp_reg rT) (pp_reg rA) +| `Pneg (SetSOOV,DontSetCR0,rT,rA) -> sprintf "nego %s,%s" (pp_reg rT) (pp_reg rA) +| `Pneg (SetSOOV,SetCR0,rT,rA) -> sprintf "nego. %s,%s" (pp_reg rT) (pp_reg rA) +| `Pmulli (rT,rA,sI) -> sprintf "mulli %s,%s,%d" (pp_reg rT) (pp_reg rA) sI +| `Pmullw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "mullw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "mullw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "mullwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "mullwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhw (DontSetCR0,rT,rA,rB) -> sprintf "mulhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhw (SetCR0,rT,rA,rB) -> sprintf "mulhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhwu (DontSetCR0,rT,rA,rB) -> sprintf "mulhwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhwu (SetCR0,rT,rA,rB) -> sprintf "mulhwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divwuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divwuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwe (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divwe %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwe (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divwe. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwe (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divweo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivwe (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divweo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivweu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divweu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivweu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divweu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivweu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divweuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivweu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divweuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulld (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "mulld %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulld (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "mulld. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulld (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "mulldo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulld (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "mulldo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhd (DontSetCR0,rT,rA,rB) -> sprintf "mulhd %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhd (SetCR0,rT,rA,rB) -> sprintf "mulhd. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhdu (DontSetCR0,rT,rA,rB) -> sprintf "mulhdu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhdu (SetCR0,rT,rA,rB) -> sprintf "mulhdu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivd (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divd %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivd (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divd. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivd (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divdo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivd (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divdo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divdu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divdu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divduo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divduo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivde (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divde %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivde (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divde. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivde (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divdeo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivde (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divdeo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdeu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divdeu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdeu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "divdeu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdeu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "divdeuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pdivdeu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "divdeuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pcmpi (bF,l,rA,sI) -> sprintf "cmpi %s,%d,%s,%d" (pp_crf bF) l (pp_reg rA) sI +| `Pcmp (bF,l,rA,rB) -> sprintf "cmp %s,%d,%s,%s" (pp_crf bF) l (pp_reg rA) (pp_reg rB) +| `Pcmpli (bF,l,rA,uI) -> sprintf "cmpli %s,%d,%s,%d" (pp_crf bF) l (pp_reg rA) uI +| `Pcmpl (bF,l,rA,rB) -> sprintf "cmpl %s,%d,%s,%s" (pp_crf bF) l (pp_reg rA) (pp_reg rB) +| `Pisel (rT,rA,rB,bC) -> sprintf "isel %s,%s,%s,%d" (pp_reg rT) (pp_reg rA) (pp_reg rB) bC +| `Pandi (rA,rS,uI) -> sprintf "andi. %s,%s,%d" (pp_reg rA) (pp_reg rS) uI +| `Pandis (rA,rS,uI) -> sprintf "andis. %s,%s,%d" (pp_reg rA) (pp_reg rS) uI +| `Pori (rA,rS,uI) -> sprintf "ori %s,%s,%d" (pp_reg rA) (pp_reg rS) uI +| `Poris (rA,rS,uI) -> sprintf "oris %s,%s,%d" (pp_reg rA) (pp_reg rS) uI +| `Pxori (rA,rS,uI) -> sprintf "xori %s,%s,%d" (pp_reg rA) (pp_reg rS) uI +| `Pxoris (rA,rS,uI) -> sprintf "xoris %s,%s,%d" (pp_reg rA) (pp_reg rS) uI +| `Pand (DontSetCR0,rA,rS,rB) -> sprintf "and %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pand (SetCR0,rA,rS,rB) -> sprintf "and. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pxor (DontSetCR0,rA,rS,rB) -> sprintf "xor %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pxor (SetCR0,rA,rS,rB) -> sprintf "xor. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pnand (DontSetCR0,rA,rS,rB) -> sprintf "nand %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pnand (SetCR0,rA,rS,rB) -> sprintf "nand. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Por (DontSetCR0,rA,rS,rB) -> sprintf "or %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Por (SetCR0,rA,rS,rB) -> sprintf "or. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pnor (DontSetCR0,rA,rS,rB) -> sprintf "nor %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pnor (SetCR0,rA,rS,rB) -> sprintf "nor. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Peqv (DontSetCR0,rA,rS,rB) -> sprintf "eqv %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Peqv (SetCR0,rA,rS,rB) -> sprintf "eqv. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pandc (DontSetCR0,rA,rS,rB) -> sprintf "andc %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pandc (SetCR0,rA,rS,rB) -> sprintf "andc. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Porc (DontSetCR0,rA,rS,rB) -> sprintf "orc %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Porc (SetCR0,rA,rS,rB) -> sprintf "orc. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pextsb (DontSetCR0,rA,rS) -> sprintf "extsb %s,%s" (pp_reg rA) (pp_reg rS) +| `Pextsb (SetCR0,rA,rS) -> sprintf "extsb. %s,%s" (pp_reg rA) (pp_reg rS) +| `Pextsh (DontSetCR0,rA,rS) -> sprintf "extsh %s,%s" (pp_reg rA) (pp_reg rS) +| `Pextsh (SetCR0,rA,rS) -> sprintf "extsh. %s,%s" (pp_reg rA) (pp_reg rS) +| `Pcntlzw (DontSetCR0,rA,rS) -> sprintf "cntlzw %s,%s" (pp_reg rA) (pp_reg rS) +| `Pcntlzw (SetCR0,rA,rS) -> sprintf "cntlzw. %s,%s" (pp_reg rA) (pp_reg rS) +| `Pcmpb (rA,rS,rB) -> sprintf "cmpb %s,%d,%s" (pp_reg rA) rS (pp_reg rB) +| `Ppopcntb (rA,rS) -> sprintf "popcntb %s,%s" (pp_reg rA) (pp_reg rS) +| `Ppopcntw (rA,rS) -> sprintf "popcntw %s,%s" (pp_reg rA) (pp_reg rS) +| `Pprtyd (rA,rS) -> sprintf "prtyd %s,%s" (pp_reg rA) (pp_reg rS) +| `Pprtyw (rA,rS) -> sprintf "prtyw %s,%s" (pp_reg rA) (pp_reg rS) +| `Pextsw (DontSetCR0,rA,rS) -> sprintf "extsw %s,%s" (pp_reg rA) (pp_reg rS) +| `Pextsw (SetCR0,rA,rS) -> sprintf "extsw. %s,%s" (pp_reg rA) (pp_reg rS) +| `Pcntlzd (DontSetCR0,rA,rS) -> sprintf "cntlzd %s,%s" (pp_reg rA) (pp_reg rS) +| `Pcntlzd (SetCR0,rA,rS) -> sprintf "cntlzd. %s,%s" (pp_reg rA) (pp_reg rS) +| `Ppopcntd (rA,rS) -> sprintf "popcntd %s,%s" (pp_reg rA) (pp_reg rS) +| `Pbpermd (rA,rS,rB) -> sprintf "bpermd %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Prlwinm (DontSetCR0,rA,rS,sH,mB,mE) -> sprintf "rlwinm %s,%s,%d,%d,%d" (pp_reg rA) (pp_reg rS) sH mB mE +| `Prlwinm (SetCR0,rA,rS,sH,mB,mE) -> sprintf "rlwinm. %s,%s,%d,%d,%d" (pp_reg rA) (pp_reg rS) sH mB mE +| `Prlwnm (DontSetCR0,rA,rS,rB,mB,mE) -> sprintf "rlwnm %s,%s,%s,%d,%d" (pp_reg rA) (pp_reg rS) (pp_reg rB) mB mE +| `Prlwnm (SetCR0,rA,rS,rB,mB,mE) -> sprintf "rlwnm. %s,%s,%s,%d,%d" (pp_reg rA) (pp_reg rS) (pp_reg rB) mB mE +| `Prlwimi (DontSetCR0,rA,rS,sH,mB,mE) -> sprintf "rlwimi %s,%s,%d,%d,%d" (pp_reg rA) (pp_reg rS) sH mB mE +| `Prlwimi (SetCR0,rA,rS,sH,mB,mE) -> sprintf "rlwimi. %s,%s,%d,%d,%d" (pp_reg rA) (pp_reg rS) sH mB mE +| `Prldicl (DontSetCR0,rA,rS,sH,mB) -> sprintf "rldicl %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mB +| `Prldicl (SetCR0,rA,rS,sH,mB) -> sprintf "rldicl. %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mB +| `Prldicr (DontSetCR0,rA,rS,sH,mE) -> sprintf "rldicr %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mE +| `Prldicr (SetCR0,rA,rS,sH,mE) -> sprintf "rldicr. %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mE +| `Prldic (DontSetCR0,rA,rS,sH,mB) -> sprintf "rldic %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mB +| `Prldic (SetCR0,rA,rS,sH,mB) -> sprintf "rldic. %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mB +| `Prldcl (DontSetCR0,rA,rS,rB,mB) -> sprintf "rldcl %s,%s,%s,%d" (pp_reg rA) (pp_reg rS) (pp_reg rB) mB +| `Prldcl (SetCR0,rA,rS,rB,mB) -> sprintf "rldcl. %s,%s,%s,%d" (pp_reg rA) (pp_reg rS) (pp_reg rB) mB +| `Prldcr (DontSetCR0,rA,rS,rB,mE) -> sprintf "rldcr %s,%s,%s,%d" (pp_reg rA) (pp_reg rS) (pp_reg rB) mE +| `Prldcr (SetCR0,rA,rS,rB,mE) -> sprintf "rldcr. %s,%s,%s,%d" (pp_reg rA) (pp_reg rS) (pp_reg rB) mE +| `Prldimi (DontSetCR0,rA,rS,sH,mB) -> sprintf "rldimi %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mB +| `Prldimi (SetCR0,rA,rS,sH,mB) -> sprintf "rldimi. %s,%s,%d,%d" (pp_reg rA) (pp_reg rS) sH mB +| `Pslw (DontSetCR0,rA,rS,rB) -> sprintf "slw %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pslw (SetCR0,rA,rS,rB) -> sprintf "slw. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psrw (DontSetCR0,rA,rS,rB) -> sprintf "srw %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psrw (SetCR0,rA,rS,rB) -> sprintf "srw. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psrawi (DontSetCR0,rA,rS,sH) -> sprintf "srawi %s,%s,%d" (pp_reg rA) (pp_reg rS) sH +| `Psrawi (SetCR0,rA,rS,sH) -> sprintf "srawi. %s,%s,%d" (pp_reg rA) (pp_reg rS) sH +| `Psraw (DontSetCR0,rA,rS,rB) -> sprintf "sraw %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psraw (SetCR0,rA,rS,rB) -> sprintf "sraw. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psld (DontSetCR0,rA,rS,rB) -> sprintf "sld %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psld (SetCR0,rA,rS,rB) -> sprintf "sld. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psrd (DontSetCR0,rA,rS,rB) -> sprintf "srd %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psrd (SetCR0,rA,rS,rB) -> sprintf "srd. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psradi (DontSetCR0,rA,rS,sH) -> sprintf "sradi %s,%s,%d" (pp_reg rA) (pp_reg rS) sH +| `Psradi (SetCR0,rA,rS,sH) -> sprintf "sradi. %s,%s,%d" (pp_reg rA) (pp_reg rS) sH +| `Psrad (DontSetCR0,rA,rS,rB) -> sprintf "srad %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Psrad (SetCR0,rA,rS,rB) -> sprintf "srad. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pcdtbcd (rA,rS) -> sprintf "cdtbcd %s,%s" (pp_reg rA) (pp_reg rS) +| `Pcbcdtd (rA,rS) -> sprintf "cbcdtd %s,%s" (pp_reg rA) (pp_reg rS) +| `Paddg6s (rT,rA,rB) -> sprintf "addg6s %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmtspr (sPR,rS) -> sprintf "mtspr %d,%s" sPR (pp_reg rS) +| `Pmfspr (rT,sPR) -> sprintf "mfspr %s,%d" (pp_reg rT) sPR +| `Pmtcrf (fXM,rS) -> sprintf "mtcrf %d,%s" fXM (pp_reg rS) +| `Pmfcr (rT) -> sprintf "mfcr %s" (pp_reg rT) +| `Pmtocrf (fXM,rS) -> sprintf "mtocrf %d,%s" fXM (pp_reg rS) +| `Pmfocrf (rT,fXM) -> sprintf "mfocrf %s,%d" (pp_reg rT) fXM +| `Pmcrxr (bF) -> sprintf "mcrxr %s" (pp_crf bF) +| `Pdlmzb (DontSetCR0,rA,rS,rB) -> sprintf "dlmzb %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pdlmzb (SetCR0,rA,rS,rB) -> sprintf "dlmzb. %s,%s,%s" (pp_reg rA) (pp_reg rS) (pp_reg rB) +| `Pmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchws %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchws. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchwso %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchws (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchwso. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchwuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchwuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchwsu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchwsu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "macchwsuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmacchwsu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "macchwsuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhws %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhws. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhwso %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhws (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhwso. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhwuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhwuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhwsu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhwsu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "machhwsuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmachhwsu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "machhwsuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhws %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhws. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhwso %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhwso. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhwuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhwuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwsu (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhwsu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwsu (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhwsu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwsu (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "maclhwsuo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmaclhwsu (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "maclhwsuo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulchw (DontSetCR0,rT,rA,rB) -> sprintf "mulchw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulchw (SetCR0,rT,rA,rB) -> sprintf "mulchw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulchwu (DontSetCR0,rT,rA,rB) -> sprintf "mulchwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulchwu (SetCR0,rT,rA,rB) -> sprintf "mulchwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhhw (DontSetCR0,rT,rA,rB) -> sprintf "mulhhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhhw (SetCR0,rT,rA,rB) -> sprintf "mulhhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhhwu (DontSetCR0,rT,rA,rB) -> sprintf "mulhhwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmulhhwu (SetCR0,rT,rA,rB) -> sprintf "mulhhwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullhw (DontSetCR0,rT,rA,rB) -> sprintf "mullhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullhw (SetCR0,rT,rA,rB) -> sprintf "mullhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullhwu (DontSetCR0,rT,rA,rB) -> sprintf "mullhwu %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pmullhwu (SetCR0,rT,rA,rB) -> sprintf "mullhwu. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmacchw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmacchw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmacchwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmacchwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmacchws %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchws (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmacchws. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchws (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmacchwso %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmacchws (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmacchwso. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmachhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmachhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmachhwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmachhwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmachhws %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhws (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmachhws. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhws (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmachhwso %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmachhws (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmachhwso. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhw (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmaclhw %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhw (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmaclhw. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhw (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmaclhwo %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhw (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmaclhwo. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhws (DontSetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmaclhws %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhws (DontSetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmaclhws. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhws (SetSOOV,DontSetCR0,rT,rA,rB) -> sprintf "nmaclhwso %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Pnmaclhws (SetSOOV,SetCR0,rT,rA,rB) -> sprintf "nmaclhwso. %s,%s,%s" (pp_reg rT) (pp_reg rA) (pp_reg rB) +| `Picbi (rA,rB) -> sprintf "icbi %s,%s" (pp_reg rA) (pp_reg rB) +| `Picbt (cT,rA,rB) -> sprintf "icbt %d,%s,%s" cT (pp_reg rA) (pp_reg rB) +| `Pdcba (rA,rB) -> sprintf "dcba %s,%s" (pp_reg rA) (pp_reg rB) +| `Pdcbt (rA,rB,tH) -> sprintf "dcbt %s,%s,%d" (pp_reg rA) (pp_reg rB) tH +| `Pdcbtst (rA,rB,tH) -> sprintf "dcbtst %s,%s,%d" (pp_reg rA) (pp_reg rB) tH +| `Pdcbz (rA,rB) -> sprintf "dcbz %s,%s" (pp_reg rA) (pp_reg rB) +| `Pdcbst (rA,rB) -> sprintf "dcbst %s,%s" (pp_reg rA) (pp_reg rB) +| `Pdcbf (rA,rB,l) -> sprintf "dcbf %s,%s,%d" (pp_reg rA) (pp_reg rB) l +| `Pisync -> sprintf "isync " +| `Plbarx (rT,rA,rB,eH) -> sprintf "lbarx %s,%s,%s,%d" (pp_reg rT) (pp_reg rA) (pp_reg rB) eH +| `Plharx (rT,rA,rB,eH) -> sprintf "lharx %s,%s,%s,%d" (pp_reg rT) (pp_reg rA) (pp_reg rB) eH +| `Plwarx (rT,rA,rB,eH) -> sprintf "lwarx %s,%s,%s,%d" (pp_reg rT) (pp_reg rA) (pp_reg rB) eH +| `Pstbcx (rS,rA,rB) -> sprintf "stbcx. %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Psthcx (rS,rA,rB) -> sprintf "sthcx. %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pstwcx (rS,rA,rB) -> sprintf "stwcx. %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Pldarx (rT,rA,rB,eH) -> sprintf "ldarx %s,%s,%s,%d" (pp_reg rT) (pp_reg rA) (pp_reg rB) eH +| `Pstdcx (rS,rA,rB) -> sprintf "stdcx. %s,%s,%s" (pp_reg rS) (pp_reg rA) (pp_reg rB) +| `Psync (l) -> sprintf "sync %d" l +| `Peieio -> sprintf "eieio " +| `Pwait (wC) -> sprintf "wait %d" wC diff --git a/old/power/gen/sail_trans_out.gen b/old/power/gen/sail_trans_out.gen new file mode 100644 index 00000000..09d3cdbf --- /dev/null +++ b/old/power/gen/sail_trans_out.gen @@ -0,0 +1,1112 @@ + | ("B", [li; aa; lk], _) -> + `Pb( + (trans_out_aa aa), + (trans_out_lk lk), + (trans_out_int (trans_out_li_setaa_setlk_k3 li aa lk))) + | ("Bc", [bo; bi; bd; aa; lk], _) -> + `Pbc( + (trans_out_aa aa), + (trans_out_lk lk), + (trans_out_int bo), + (trans_out_int bi), + (trans_out_int (trans_out_bd_setaa_setlk_k_k_k5 bo bi bd aa lk))) + | ("Bclr", [bo; bi; bh; lk], _) -> + `Pbclr( + (trans_out_lk lk), + (trans_out_int bo), + (trans_out_int bi), + (trans_out_int bh)) + | ("Bcctr", [bo; bi; bh; lk], _) -> + `Pbcctr( + (trans_out_lk lk), + (trans_out_int bo), + (trans_out_int bi), + (trans_out_int bh)) + | ("Crand", [bt; ba; bb], _) -> + `Pcrand( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Crnand", [bt; ba; bb], _) -> + `Pcrnand( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Cror", [bt; ba; bb], _) -> + `Pcror( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Crxor", [bt; ba; bb], _) -> + `Pcrxor( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Crnor", [bt; ba; bb], _) -> + `Pcrnor( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Creqv", [bt; ba; bb], _) -> + `Pcreqv( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Crandc", [bt; ba; bb], _) -> + `Pcrandc( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Crorc", [bt; ba; bb], _) -> + `Pcrorc( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | ("Mcrf", [bf; bfa], _) -> + `Pmcrf( + (trans_out_int bf), + (trans_out_int bfa)) + | ("Sc", [lev], _) -> + `Psc( + (trans_out_int lev)) + | ("Scv", [lev], _) -> + `Pscv( + (trans_out_int lev)) + | ("Lbz", [rt; ra; d], _) -> + `Plbz( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lbzx", [rt; ra; rb], _) -> + `Plbzx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lbzu", [rt; ra; d], _) -> + `Plbzu( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lbzux", [rt; ra; rb], _) -> + `Plbzux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lhz", [rt; ra; d], _) -> + `Plhz( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lhzx", [rt; ra; rb], _) -> + `Plhzx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lhzu", [rt; ra; d], _) -> + `Plhzu( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lhzux", [rt; ra; rb], _) -> + `Plhzux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lha", [rt; ra; d], _) -> + `Plha( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lhax", [rt; ra; rb], _) -> + `Plhax( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lhau", [rt; ra; d], _) -> + `Plhau( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lhaux", [rt; ra; rb], _) -> + `Plhaux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lwz", [rt; ra; d], _) -> + `Plwz( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lwzx", [rt; ra; rb], _) -> + `Plwzx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lwzu", [rt; ra; d], _) -> + `Plwzu( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lwzux", [rt; ra; rb], _) -> + `Plwzux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lwa", [rt; ra; ds], _) -> + `Plwa( + (trans_out_reg rt), + (trans_out_int ds), + (trans_out_reg ra)) + | ("Lwax", [rt; ra; rb], _) -> + `Plwax( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lwaux", [rt; ra; rb], _) -> + `Plwaux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Ld", [rt; ra; ds], _) -> + `Pld( + (trans_out_reg rt), + (trans_out_int ds), + (trans_out_reg ra)) + | ("Ldx", [rt; ra; rb], _) -> + `Pldx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Ldu", [rt; ra; ds], _) -> + `Pldu( + (trans_out_reg rt), + (trans_out_int ds), + (trans_out_reg ra)) + | ("Ldux", [rt; ra; rb], _) -> + `Pldux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stb", [rs; ra; d], _) -> + `Pstb( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Stbx", [rs; ra; rb], _) -> + `Pstbx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stbu", [rs; ra; d], _) -> + `Pstbu( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Stbux", [rs; ra; rb], _) -> + `Pstbux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Sth", [rs; ra; d], _) -> + `Psth( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Sthx", [rs; ra; rb], _) -> + `Psthx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Sthu", [rs; ra; d], _) -> + `Psthu( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Sthux", [rs; ra; rb], _) -> + `Psthux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stw", [rs; ra; d], _) -> + `Pstw( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Stwx", [rs; ra; rb], _) -> + `Pstwx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stwu", [rs; ra; d], _) -> + `Pstwu( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Stwux", [rs; ra; rb], _) -> + `Pstwux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Std", [rs; ra; ds], _) -> + `Pstd( + (trans_out_reg rs), + (trans_out_int ds), + (trans_out_reg ra)) + | ("Stdx", [rs; ra; rb], _) -> + `Pstdx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stdu", [rs; ra; ds], _) -> + `Pstdu( + (trans_out_reg rs), + (trans_out_int ds), + (trans_out_reg ra)) + | ("Stdux", [rs; ra; rb], _) -> + `Pstdux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lq", [rtp; ra; dq; pt], _) -> + `Plq( + (trans_out_int rtp), + (trans_out_int dq), + (trans_out_reg ra), + (trans_out_int pt)) + | ("Stq", [rsp; ra; ds], _) -> + `Pstq( + (trans_out_int rsp), + (trans_out_int ds), + (trans_out_reg ra)) + | ("Lhbrx", [rt; ra; rb], _) -> + `Plhbrx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Sthbrx", [rs; ra; rb], _) -> + `Psthbrx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lwbrx", [rt; ra; rb], _) -> + `Plwbrx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stwbrx", [rs; ra; rb], _) -> + `Pstwbrx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Ldbrx", [rt; ra; rb], _) -> + `Pldbrx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stdbrx", [rs; ra; rb], _) -> + `Pstdbrx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Lmw", [rt; ra; d], _) -> + `Plmw( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | ("Stmw", [rs; ra; d], _) -> + `Pstmw( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | ("Lswi", [rt; ra; nb], _) -> + `Plswi( + (trans_out_int rt), + (trans_out_reg ra), + (trans_out_int nb)) + | ("Lswx", [rt; ra; rb], _) -> + `Plswx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stswi", [rs; ra; nb], _) -> + `Pstswi( + (trans_out_int rs), + (trans_out_reg ra), + (trans_out_int nb)) + | ("Stswx", [rs; ra; rb], _) -> + `Pstswx( + (trans_out_int rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Addi", [rt; ra; si], _) -> + `Paddi( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | ("Addis", [rt; ra; si], _) -> + `Paddis( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | ("Add", [rt; ra; rb; oe; rc], _) -> + `Padd( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Subf", [rt; ra; rb; oe; rc], _) -> + `Psubf( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Addic", [rt; ra; si], _) -> + `Paddic( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | ("AddicDot", [rt; ra; si], _) -> + `Paddicdot( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | ("Subfic", [rt; ra; si], _) -> + `Psubfic( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | ("Addc", [rt; ra; rb; oe; rc], _) -> + `Paddc( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Subfc", [rt; ra; rb; oe; rc], _) -> + `Psubfc( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Adde", [rt; ra; rb; oe; rc], _) -> + `Padde( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Subfe", [rt; ra; rb; oe; rc], _) -> + `Psubfe( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Addme", [rt; ra; oe; rc], _) -> + `Paddme( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | ("Subfme", [rt; ra; oe; rc], _) -> + `Psubfme( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | ("Addze", [rt; ra; oe; rc], _) -> + `Paddze( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | ("Subfze", [rt; ra; oe; rc], _) -> + `Psubfze( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | ("Neg", [rt; ra; oe; rc], _) -> + `Pneg( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | ("Mulli", [rt; ra; si], _) -> + `Pmulli( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | ("Mullw", [rt; ra; rb; oe; rc], _) -> + `Pmullw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulhw", [rt; ra; rb; rc], _) -> + `Pmulhw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulhwu", [rt; ra; rb; rc], _) -> + `Pmulhwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divw", [rt; ra; rb; oe; rc], _) -> + `Pdivw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divwu", [rt; ra; rb; oe; rc], _) -> + `Pdivwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divwe", [rt; ra; rb; oe; rc], _) -> + `Pdivwe( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divweu", [rt; ra; rb; oe; rc], _) -> + `Pdivweu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulld", [rt; ra; rb; oe; rc], _) -> + `Pmulld( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulhd", [rt; ra; rb; rc], _) -> + `Pmulhd( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulhdu", [rt; ra; rb; rc], _) -> + `Pmulhdu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divd", [rt; ra; rb; oe; rc], _) -> + `Pdivd( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divdu", [rt; ra; rb; oe; rc], _) -> + `Pdivdu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divde", [rt; ra; rb; oe; rc], _) -> + `Pdivde( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Divdeu", [rt; ra; rb; oe; rc], _) -> + `Pdivdeu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Cmpi", [bf; l; ra; si], _) -> + `Pcmpi( + (trans_out_int bf), + (trans_out_int l), + (trans_out_reg ra), + (trans_out_int si)) + | ("Cmp", [bf; l; ra; rb], _) -> + `Pcmp( + (trans_out_int bf), + (trans_out_int l), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Cmpli", [bf; l; ra; ui], _) -> + `Pcmpli( + (trans_out_int bf), + (trans_out_int l), + (trans_out_reg ra), + (trans_out_int ui)) + | ("Cmpl", [bf; l; ra; rb], _) -> + `Pcmpl( + (trans_out_int bf), + (trans_out_int l), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Isel", [rt; ra; rb; bc], _) -> + `Pisel( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int bc)) + | ("Andi", [rs; ra; ui], _) -> + `Pandi( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | ("Andis", [rs; ra; ui], _) -> + `Pandis( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | ("Ori", [rs; ra; ui], _) -> + `Pori( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | ("Oris", [rs; ra; ui], _) -> + `Poris( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | ("Xori", [rs; ra; ui], _) -> + `Pxori( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | ("Xoris", [rs; ra; ui], _) -> + `Pxoris( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | ("And", [rs; ra; rb; rc], _) -> + `Pand( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Xor", [rs; ra; rb; rc], _) -> + `Pxor( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Nand", [rs; ra; rb; rc], _) -> + `Pnand( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Or", [rs; ra; rb; rc], _) -> + `Por( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Nor", [rs; ra; rb; rc], _) -> + `Pnor( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Eqv", [rs; ra; rb; rc], _) -> + `Peqv( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Andc", [rs; ra; rb; rc], _) -> + `Pandc( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Orc", [rs; ra; rb; rc], _) -> + `Porc( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Extsb", [rs; ra; rc], _) -> + `Pextsb( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Extsh", [rs; ra; rc], _) -> + `Pextsh( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Cntlzw", [rs; ra; rc], _) -> + `Pcntlzw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Cmpb", [rs; ra; rb], _) -> + `Pcmpb( + (trans_out_reg ra), + (trans_out_int rs), + (trans_out_reg rb)) + | ("Popcntb", [rs; ra], _) -> + `Ppopcntb( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Popcntw", [rs; ra], _) -> + `Ppopcntw( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Prtyd", [rs; ra], _) -> + `Pprtyd( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Prtyw", [rs; ra], _) -> + `Pprtyw( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Extsw", [rs; ra; rc], _) -> + `Pextsw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Cntlzd", [rs; ra; rc], _) -> + `Pcntlzd( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Popcntd", [rs; ra], _) -> + `Ppopcntd( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Bpermd", [rs; ra; rb], _) -> + `Pbpermd( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Rlwinm", [rs; ra; sh; mb; me; rc], _) -> + `Prlwinm( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb), + (trans_out_int me)) + | ("Rlwnm", [rs; ra; rb; mb; me; rc], _) -> + `Prlwnm( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb), + (trans_out_int mb), + (trans_out_int me)) + | ("Rlwimi", [rs; ra; sh; mb; me; rc], _) -> + `Prlwimi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb), + (trans_out_int me)) + | ("Rldicl", [rs; ra; sh; mb; rc], _) -> + `Prldicl( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb)) + | ("Rldicr", [rs; ra; sh; me; rc], _) -> + `Prldicr( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int me)) + | ("Rldic", [rs; ra; sh; mb; rc], _) -> + `Prldic( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb)) + | ("Rldcl", [rs; ra; rb; mb; rc], _) -> + `Prldcl( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb), + (trans_out_int mb)) + | ("Rldcr", [rs; ra; rb; me; rc], _) -> + `Prldcr( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb), + (trans_out_int me)) + | ("Rldimi", [rs; ra; sh; mb; rc], _) -> + `Prldimi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb)) + | ("Slw", [rs; ra; rb; rc], _) -> + `Pslw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Srw", [rs; ra; rb; rc], _) -> + `Psrw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Srawi", [rs; ra; sh; rc], _) -> + `Psrawi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh)) + | ("Sraw", [rs; ra; rb; rc], _) -> + `Psraw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Sld", [rs; ra; rb; rc], _) -> + `Psld( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Srd", [rs; ra; rb; rc], _) -> + `Psrd( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Sradi", [rs; ra; sh; rc], _) -> + `Psradi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh)) + | ("Srad", [rs; ra; rb; rc], _) -> + `Psrad( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Cdtbcd", [rs; ra], _) -> + `Pcdtbcd( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Cbcdtd", [rs; ra], _) -> + `Pcbcdtd( + (trans_out_reg ra), + (trans_out_reg rs)) + | ("Addg6s", [rt; ra; rb], _) -> + `Paddg6s( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mtspr", [rs; spr], _) -> + `Pmtspr( + (trans_out_int spr), + (trans_out_reg rs)) + | ("Mfspr", [rt; spr], _) -> + `Pmfspr( + (trans_out_reg rt), + (trans_out_int spr)) + | ("Mtcrf", [rs; fxm], _) -> + `Pmtcrf( + (trans_out_int fxm), + (trans_out_reg rs)) + | ("Mfcr", [rt], _) -> + `Pmfcr( + (trans_out_reg rt)) + | ("Mtocrf", [rs; fxm], _) -> + `Pmtocrf( + (trans_out_int fxm), + (trans_out_reg rs)) + | ("Mfocrf", [rt; fxm], _) -> + `Pmfocrf( + (trans_out_reg rt), + (trans_out_int fxm)) + | ("Mcrxr", [bf], _) -> + `Pmcrxr( + (trans_out_int bf)) + | ("Dlmzb", [rs; ra; rb; rc], _) -> + `Pdlmzb( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | ("Macchw", [rt; ra; rb; oe; rc], _) -> + `Pmacchw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Macchws", [rt; ra; rb; oe; rc], _) -> + `Pmacchws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Macchwu", [rt; ra; rb; oe; rc], _) -> + `Pmacchwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Macchwsu", [rt; ra; rb; oe; rc], _) -> + `Pmacchwsu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Machhw", [rt; ra; rb; oe; rc], _) -> + `Pmachhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Machhws", [rt; ra; rb; oe; rc], _) -> + `Pmachhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Machhwu", [rt; ra; rb; oe; rc], _) -> + `Pmachhwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Machhwsu", [rt; ra; rb; oe; rc], _) -> + `Pmachhwsu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Maclhw", [rt; ra; rb; oe; rc], _) -> + `Pmaclhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Maclhws", [rt; ra; rb; oe; rc], _) -> + `Pmaclhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Maclhwu", [rt; ra; rb; oe; rc], _) -> + `Pmaclhwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Maclhwsu", [rt; ra; rb; oe; rc], _) -> + `Pmaclhwsu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulchw", [rt; ra; rb; rc], _) -> + `Pmulchw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulchwu", [rt; ra; rb; rc], _) -> + `Pmulchwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulhhw", [rt; ra; rb; rc], _) -> + `Pmulhhw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mulhhwu", [rt; ra; rb; rc], _) -> + `Pmulhhwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mullhw", [rt; ra; rb; rc], _) -> + `Pmullhw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Mullhwu", [rt; ra; rb; rc], _) -> + `Pmullhwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Nmacchw", [rt; ra; rb; oe; rc], _) -> + `Pnmacchw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Nmacchws", [rt; ra; rb; oe; rc], _) -> + `Pnmacchws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Nmachhw", [rt; ra; rb; oe; rc], _) -> + `Pnmachhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Nmachhws", [rt; ra; rb; oe; rc], _) -> + `Pnmachhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Nmaclhw", [rt; ra; rb; oe; rc], _) -> + `Pnmaclhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Nmaclhws", [rt; ra; rb; oe; rc], _) -> + `Pnmaclhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Icbi", [ra; rb], _) -> + `Picbi( + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Icbt", [ct; ra; rb], _) -> + `Picbt( + (trans_out_int ct), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Dcba", [ra; rb], _) -> + `Pdcba( + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Dcbt", [th; ra; rb], _) -> + `Pdcbt( + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int th)) + | ("Dcbtst", [th; ra; rb], _) -> + `Pdcbtst( + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int th)) + | ("Dcbz", [ra; rb], _) -> + `Pdcbz( + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Dcbst", [ra; rb], _) -> + `Pdcbst( + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Dcbf", [l; ra; rb], _) -> + `Pdcbf( + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int l)) + | ("Isync", [], _) -> + `Pisync + + | ("Lbarx", [rt; ra; rb; eh], _) -> + `Plbarx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int eh)) + | ("Lharx", [rt; ra; rb; eh], _) -> + `Plharx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int eh)) + | ("Lwarx", [rt; ra; rb; eh], _) -> + `Plwarx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int eh)) + | ("Stbcx", [rs; ra; rb], _) -> + `Pstbcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Sthcx", [rs; ra; rb], _) -> + `Psthcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Stwcx", [rs; ra; rb], _) -> + `Pstwcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Ldarx", [rt; ra; rb; eh], _) -> + `Pldarx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int eh)) + | ("Stdcx", [rs; ra; rb], _) -> + `Pstdcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | ("Sync", [l], _) -> + `Psync( + (trans_out_int l)) + | ("Eieio", [], _) -> + `Peieio + + | ("Wait", [wc], _) -> + `Pwait( + (trans_out_int wc)) diff --git a/old/power/gen/sail_trans_out_types.hgen b/old/power/gen/sail_trans_out_types.hgen new file mode 100644 index 00000000..08214129 --- /dev/null +++ b/old/power/gen/sail_trans_out_types.hgen @@ -0,0 +1,146 @@ +let trans_out_int ( _fname, _fsize, fbits ) = + Nat_big_num.to_int (SB.integer_of_bit_list fbits) + +let trans_out_reg flv = + let n = trans_out_int flv in + Ireg (match n with + | 0 -> GPR0 + | 1 -> GPR1 + | 2 -> GPR2 + | 3 -> GPR3 + | 4 -> GPR4 + | 5 -> GPR5 + | 6 -> GPR6 + | 7 -> GPR7 + | 8 -> GPR8 + | 9 -> GPR9 + | 10 -> GPR10 + | 11 -> GPR11 + | 12 -> GPR12 + | 13 -> GPR13 + | 14 -> GPR14 + | 15 -> GPR15 + | 16 -> GPR16 + | 17 -> GPR17 + | 18 -> GPR18 + | 19 -> GPR19 + | 20 -> GPR20 + | 21 -> GPR21 + | 22 -> GPR22 + | 23 -> GPR23 + | 24 -> GPR24 + | 25 -> GPR25 + | 26 -> GPR26 + | 27 -> GPR27 + | 28 -> GPR28 + | 29 -> GPR29 + | 30 -> GPR30 + | 31 -> GPR31 + | _ -> failwith "trans_out_reg given number not 0 to 31") + +let trans_out_soov ifv = + match trans_out_int ifv with + | 1 -> SetSOOV + | 0 -> DontSetSOOV + | _ -> failwith "trans_out_soov given number other than 0 and 1" + +let trans_out_cr0 ifv = + match trans_out_int ifv with + | 1 -> SetCR0 + | 0 -> DontSetCR0 + | _ -> failwith "trans_out_cr0 given number other than 0 and 1" + +let trans_out_aa ifv = + match trans_out_int ifv with + | 1 -> SetAA + | 0 -> DontSetAA + | _ -> failwith "trans_out_aa given number other than 0 and 1" + +let trans_out_lk ifv = + match trans_out_int ifv with + | 1 -> SetLK + | 0 -> DontSetLK + | _ -> failwith "trans_out_lk given number other than 0 and 1" + +(*These probably need to be checked that the shift is the correct thing to do*) +(* translating branch target addresses *) +(* CP: this does not seem to match with how the function is used, trying to fix + this now. *) +(* let trans_out_li_setaa_setlk_k3 setaa setlk li = + match li with + | (n,m,bits) -> + match bits with + | [] | [_] | [_;_] -> (n,m,bits) + | _ -> + (n,m, (let front,rest = List.hd bits, List.tl bits in + let second,rest = List.hd rest, List.tl rest in + rest @ [front;second])) *) +let trans_out_li_setaa_setlk_k3 li setaa setlk = + match li with + | (n,m,bits) -> (n,m, bits @ [Bitc_zero;Bitc_zero]) + +(* CP: this does not seem to match with how the function is used, trying to fix + this now. *) +(* let trans_out_bd_setaa_setlk_k_k_k5 setaa setlk bo bi bd = + match bd with + | (n,m,bits) -> + match bits with + | [] | [_] | [_;_] -> (n,m,bits) + | _ -> + (n,m, (let front,rest = List.hd bits, List.tl bits in + let second,rest = List.hd rest, List.tl rest in + rest @ [front;second])) *) +let trans_out_bd_setaa_setlk_k_k_k5 bo bi bd setaa setlk = + match bd with + | (n,m,bits) -> (n,m, bits @ [Bitc_zero;Bitc_zero]) + +(* translating vector-scalar floating-point ops *) +(* all of these translate a 6-bit value into a 5:1 bit pair, but differ + in number and type of arguments *) +(*this is probably wrong, probably I want to do a transformation on the bits then return, but unclear what translation*) +let trans_out_k xt = xt +let trans_out_xk xt = xt +let trans_out_t_k_k4 xt _ _ _ = trans_out_k xt +let trans_out_tx_k_k4 xt _ _ _ = trans_out_xk xt +let trans_out_t_k_reg_reg4 xt xa _ _ = trans_out_k xt +let trans_out_tx_k_reg_reg4 xt xa _ _ = trans_out_xk xt +let trans_out_s_k_reg_reg4 = trans_out_t_k_reg_reg4 +let trans_out_sx_k_reg_reg4 = trans_out_tx_k_reg_reg4 +let trans_out_t_k_k_k6 x _ _ _ _ _ = trans_out_k x +let trans_out_t_k_k_k5 x _ _ _ _ = trans_out_k x +let trans_out_tx_k_k_k6 x _ _ _ _ _= trans_out_k x +let trans_out_tx_k_k_k5 x _ _ _ _ = trans_out_k x +let trans_out_b_k_k4 = trans_out_t_k_k4 +let trans_out_bx_k_k4 = trans_out_tx_k_k4 +let trans_out_a_k_k_k6 xt xa xb _ _ _ = trans_out_k xa +let trans_out_ax_k_k_k6 xt xa xb _ _ _ = trans_out_xk xa +let trans_out_b_k_k_k6 xt xa xb _ _ _ = trans_out_k xb +let trans_out_b_k_k_k5 xt xa xb _ _ = trans_out_k xb +let trans_out_bx_k_k_k6 xt xa xb _ _ _ = trans_out_xk xb +let trans_out_bx_k_k_k5 xt xa xb _ _ = trans_out_xk xb +let trans_out_a_crindex_k_k5 bf xa xb _ _ = trans_out_k xa +let trans_out_ax_crindex_k_k5 bf xa xb _ _ = trans_out_xk xa +let trans_out_b_crindex_k_k5 bf xa xb _ _ = trans_out_k xb +let trans_out_bx_crindex_k_k5 bf xa xb _ _ = trans_out_xk xb +let trans_out_b_crindex_k3 bf xb _ = trans_out_k xb +let trans_out_bx_crindex_k3 bf xb _ = trans_out_xk xb +let trans_out_t_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_k xt +let trans_out_tx_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_xk xt +let trans_out_a_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_k xa +let trans_out_ax_setcr0_k_k_k7 setcr0 xt xa xb _ _ _= trans_out_xk xa +let trans_out_b_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_k xb +let trans_out_bx_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_xk xb +let trans_out_t_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_k xt +let trans_out_tx_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_xk xt +let trans_out_t_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_k xt +let trans_out_tx_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_xk xt +let trans_out_a_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_k xa +let trans_out_ax_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_xk xa +let trans_out_a_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_k xa +let trans_out_ax_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_xk xa +let trans_out_b_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_k xb +let trans_out_bx_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_xk xb +let trans_out_b_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_k xb +let trans_out_bx_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_xk xb +let trans_out_c_k_k_k_k8 xt xa xb xc _ _ _ _ = trans_out_k xc +let trans_out_cx_k_k_k_k8 xt xa xb xc _ _ _ _ = trans_out_xk xc
\ No newline at end of file diff --git a/old/power/gen/shallow_ast_to_herdtools_ast.gen b/old/power/gen/shallow_ast_to_herdtools_ast.gen new file mode 100644 index 00000000..1ab732f9 --- /dev/null +++ b/old/power/gen/shallow_ast_to_herdtools_ast.gen @@ -0,0 +1,1112 @@ + | B (li, aa, lk) -> + `Pb( + (trans_out_aa aa), + (trans_out_lk lk), + (trans_out_int (trans_out_li_setaa_setlk_k3 li aa lk))) + | Bc (bo, bi, bd, aa, lk) -> + `Pbc( + (trans_out_aa aa), + (trans_out_lk lk), + (trans_out_int bo), + (trans_out_int bi), + (trans_out_int (trans_out_bd_setaa_setlk_k_k_k5 bo bi bd aa lk))) + | Bclr (bo, bi, bh, lk) -> + `Pbclr( + (trans_out_lk lk), + (trans_out_int bo), + (trans_out_int bi), + (trans_out_int bh)) + | Bcctr (bo, bi, bh, lk) -> + `Pbcctr( + (trans_out_lk lk), + (trans_out_int bo), + (trans_out_int bi), + (trans_out_int bh)) + | Crand (bt, ba, bb) -> + `Pcrand( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Crnand (bt, ba, bb) -> + `Pcrnand( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Cror (bt, ba, bb) -> + `Pcror( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Crxor (bt, ba, bb) -> + `Pcrxor( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Crnor (bt, ba, bb) -> + `Pcrnor( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Creqv (bt, ba, bb) -> + `Pcreqv( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Crandc (bt, ba, bb) -> + `Pcrandc( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Crorc (bt, ba, bb) -> + `Pcrorc( + (trans_out_int bt), + (trans_out_int ba), + (trans_out_int bb)) + | Mcrf (bf, bfa) -> + `Pmcrf( + (trans_out_int bf), + (trans_out_int bfa)) + | Sc (lev) -> + `Psc( + (trans_out_int lev)) + | Scv (lev) -> + `Pscv( + (trans_out_int lev)) + | Lbz (rt, ra, d) -> + `Plbz( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lbzx (rt, ra, rb) -> + `Plbzx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lbzu (rt, ra, d) -> + `Plbzu( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lbzux (rt, ra, rb) -> + `Plbzux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lhz (rt, ra, d) -> + `Plhz( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lhzx (rt, ra, rb) -> + `Plhzx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lhzu (rt, ra, d) -> + `Plhzu( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lhzux (rt, ra, rb) -> + `Plhzux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lha (rt, ra, d) -> + `Plha( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lhax (rt, ra, rb) -> + `Plhax( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lhau (rt, ra, d) -> + `Plhau( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lhaux (rt, ra, rb) -> + `Plhaux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lwz (rt, ra, d) -> + `Plwz( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lwzx (rt, ra, rb) -> + `Plwzx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lwzu (rt, ra, d) -> + `Plwzu( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Lwzux (rt, ra, rb) -> + `Plwzux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lwa (rt, ra, ds) -> + `Plwa( + (trans_out_reg rt), + (trans_out_int ds), + (trans_out_reg ra)) + | Lwax (rt, ra, rb) -> + `Plwax( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lwaux (rt, ra, rb) -> + `Plwaux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Ld (rt, ra, ds) -> + `Pld( + (trans_out_reg rt), + (trans_out_int ds), + (trans_out_reg ra)) + | Ldx (rt, ra, rb) -> + `Pldx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Ldu (rt, ra, ds) -> + `Pldu( + (trans_out_reg rt), + (trans_out_int ds), + (trans_out_reg ra)) + | Ldux (rt, ra, rb) -> + `Pldux( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stb (rs, ra, d) -> + `Pstb( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Stbx (rs, ra, rb) -> + `Pstbx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stbu (rs, ra, d) -> + `Pstbu( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Stbux (rs, ra, rb) -> + `Pstbux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Sth (rs, ra, d) -> + `Psth( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Sthx (rs, ra, rb) -> + `Psthx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Sthu (rs, ra, d) -> + `Psthu( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Sthux (rs, ra, rb) -> + `Psthux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stw (rs, ra, d) -> + `Pstw( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Stwx (rs, ra, rb) -> + `Pstwx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stwu (rs, ra, d) -> + `Pstwu( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Stwux (rs, ra, rb) -> + `Pstwux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Std (rs, ra, ds) -> + `Pstd( + (trans_out_reg rs), + (trans_out_int ds), + (trans_out_reg ra)) + | Stdx (rs, ra, rb) -> + `Pstdx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stdu (rs, ra, ds) -> + `Pstdu( + (trans_out_reg rs), + (trans_out_int ds), + (trans_out_reg ra)) + | Stdux (rs, ra, rb) -> + `Pstdux( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lq (rtp, ra, dq, pt) -> + `Plq( + (trans_out_int rtp), + (trans_out_int dq), + (trans_out_reg ra), + (trans_out_int pt)) + | Stq (rsp, ra, ds) -> + `Pstq( + (trans_out_int rsp), + (trans_out_int ds), + (trans_out_reg ra)) + | Lhbrx (rt, ra, rb) -> + `Plhbrx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Sthbrx (rs, ra, rb) -> + `Psthbrx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lwbrx (rt, ra, rb) -> + `Plwbrx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stwbrx (rs, ra, rb) -> + `Pstwbrx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Ldbrx (rt, ra, rb) -> + `Pldbrx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stdbrx (rs, ra, rb) -> + `Pstdbrx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Lmw (rt, ra, d) -> + `Plmw( + (trans_out_reg rt), + (trans_out_int d), + (trans_out_reg ra)) + | Stmw (rs, ra, d) -> + `Pstmw( + (trans_out_reg rs), + (trans_out_int d), + (trans_out_reg ra)) + | Lswi (rt, ra, nb) -> + `Plswi( + (trans_out_int rt), + (trans_out_reg ra), + (trans_out_int nb)) + | Lswx (rt, ra, rb) -> + `Plswx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stswi (rs, ra, nb) -> + `Pstswi( + (trans_out_int rs), + (trans_out_reg ra), + (trans_out_int nb)) + | Stswx (rs, ra, rb) -> + `Pstswx( + (trans_out_int rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Addi (rt, ra, si) -> + `Paddi( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | Addis (rt, ra, si) -> + `Paddis( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | Add (rt, ra, rb, oe, rc) -> + `Padd( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Subf (rt, ra, rb, oe, rc) -> + `Psubf( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Addic (rt, ra, si) -> + `Paddic( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | AddicDot (rt, ra, si) -> + `Paddicdot( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | Subfic (rt, ra, si) -> + `Psubfic( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | Addc (rt, ra, rb, oe, rc) -> + `Paddc( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Subfc (rt, ra, rb, oe, rc) -> + `Psubfc( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Adde (rt, ra, rb, oe, rc) -> + `Padde( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Subfe (rt, ra, rb, oe, rc) -> + `Psubfe( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Addme (rt, ra, oe, rc) -> + `Paddme( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | Subfme (rt, ra, oe, rc) -> + `Psubfme( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | Addze (rt, ra, oe, rc) -> + `Paddze( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | Subfze (rt, ra, oe, rc) -> + `Psubfze( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | Neg (rt, ra, oe, rc) -> + `Pneg( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra)) + | Mulli (rt, ra, si) -> + `Pmulli( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_int si)) + | Mullw (rt, ra, rb, oe, rc) -> + `Pmullw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulhw (rt, ra, rb, rc) -> + `Pmulhw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulhwu (rt, ra, rb, rc) -> + `Pmulhwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divw (rt, ra, rb, oe, rc) -> + `Pdivw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divwu (rt, ra, rb, oe, rc) -> + `Pdivwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divwe (rt, ra, rb, oe, rc) -> + `Pdivwe( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divweu (rt, ra, rb, oe, rc) -> + `Pdivweu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulld (rt, ra, rb, oe, rc) -> + `Pmulld( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulhd (rt, ra, rb, rc) -> + `Pmulhd( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulhdu (rt, ra, rb, rc) -> + `Pmulhdu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divd (rt, ra, rb, oe, rc) -> + `Pdivd( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divdu (rt, ra, rb, oe, rc) -> + `Pdivdu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divde (rt, ra, rb, oe, rc) -> + `Pdivde( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Divdeu (rt, ra, rb, oe, rc) -> + `Pdivdeu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Cmpi (bf, l, ra, si) -> + `Pcmpi( + (trans_out_int bf), + (trans_out_bit l), + (trans_out_reg ra), + (trans_out_int si)) + | Cmp (bf, l, ra, rb) -> + `Pcmp( + (trans_out_int bf), + (trans_out_bit l), + (trans_out_reg ra), + (trans_out_reg rb)) + | Cmpli (bf, l, ra, ui) -> + `Pcmpli( + (trans_out_int bf), + (trans_out_bit l), + (trans_out_reg ra), + (trans_out_int ui)) + | Cmpl (bf, l, ra, rb) -> + `Pcmpl( + (trans_out_int bf), + (trans_out_bit l), + (trans_out_reg ra), + (trans_out_reg rb)) + | Isel (rt, ra, rb, bc) -> + `Pisel( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int bc)) + | Andi (rs, ra, ui) -> + `Pandi( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | Andis (rs, ra, ui) -> + `Pandis( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | Ori (rs, ra, ui) -> + `Pori( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | Oris (rs, ra, ui) -> + `Poris( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | Xori (rs, ra, ui) -> + `Pxori( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | Xoris (rs, ra, ui) -> + `Pxoris( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int ui)) + | And (rs, ra, rb, rc) -> + `Pand( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Xor (rs, ra, rb, rc) -> + `Pxor( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Nand (rs, ra, rb, rc) -> + `Pnand( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Or (rs, ra, rb, rc) -> + `Por( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Nor (rs, ra, rb, rc) -> + `Pnor( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Eqv (rs, ra, rb, rc) -> + `Peqv( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Andc (rs, ra, rb, rc) -> + `Pandc( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Orc (rs, ra, rb, rc) -> + `Porc( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Extsb (rs, ra, rc) -> + `Pextsb( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | Extsh (rs, ra, rc) -> + `Pextsh( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | Cntlzw (rs, ra, rc) -> + `Pcntlzw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | Cmpb (rs, ra, rb) -> + `Pcmpb( + (trans_out_reg ra), + (trans_out_int rs), + (trans_out_reg rb)) + | Popcntb (rs, ra) -> + `Ppopcntb( + (trans_out_reg ra), + (trans_out_reg rs)) + | Popcntw (rs, ra) -> + `Ppopcntw( + (trans_out_reg ra), + (trans_out_reg rs)) + | Prtyd (rs, ra) -> + `Pprtyd( + (trans_out_reg ra), + (trans_out_reg rs)) + | Prtyw (rs, ra) -> + `Pprtyw( + (trans_out_reg ra), + (trans_out_reg rs)) + | Extsw (rs, ra, rc) -> + `Pextsw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | Cntlzd (rs, ra, rc) -> + `Pcntlzd( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs)) + | Popcntd (rs, ra) -> + `Ppopcntd( + (trans_out_reg ra), + (trans_out_reg rs)) + | Bpermd (rs, ra, rb) -> + `Pbpermd( + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Rlwinm (rs, ra, sh, mb, me, rc) -> + `Prlwinm( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb), + (trans_out_int me)) + | Rlwnm (rs, ra, rb, mb, me, rc) -> + `Prlwnm( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb), + (trans_out_int mb), + (trans_out_int me)) + | Rlwimi (rs, ra, sh, mb, me, rc) -> + `Prlwimi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb), + (trans_out_int me)) + | Rldicl (rs, ra, sh, mb, rc) -> + `Prldicl( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb)) + | Rldicr (rs, ra, sh, me, rc) -> + `Prldicr( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int me)) + | Rldic (rs, ra, sh, mb, rc) -> + `Prldic( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb)) + | Rldcl (rs, ra, rb, mb, rc) -> + `Prldcl( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb), + (trans_out_int mb)) + | Rldcr (rs, ra, rb, me, rc) -> + `Prldcr( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb), + (trans_out_int me)) + | Rldimi (rs, ra, sh, mb, rc) -> + `Prldimi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh), + (trans_out_int mb)) + | Slw (rs, ra, rb, rc) -> + `Pslw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Srw (rs, ra, rb, rc) -> + `Psrw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Srawi (rs, ra, sh, rc) -> + `Psrawi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh)) + | Sraw (rs, ra, rb, rc) -> + `Psraw( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Sld (rs, ra, rb, rc) -> + `Psld( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Srd (rs, ra, rb, rc) -> + `Psrd( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Sradi (rs, ra, sh, rc) -> + `Psradi( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_int sh)) + | Srad (rs, ra, rb, rc) -> + `Psrad( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Cdtbcd (rs, ra) -> + `Pcdtbcd( + (trans_out_reg ra), + (trans_out_reg rs)) + | Cbcdtd (rs, ra) -> + `Pcbcdtd( + (trans_out_reg ra), + (trans_out_reg rs)) + | Addg6s (rt, ra, rb) -> + `Paddg6s( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mtspr (rs, spr) -> + `Pmtspr( + (trans_out_int spr), + (trans_out_reg rs)) + | Mfspr (rt, spr) -> + `Pmfspr( + (trans_out_reg rt), + (trans_out_int spr)) + | Mtcrf (rs, fxm) -> + `Pmtcrf( + (trans_out_int fxm), + (trans_out_reg rs)) + | Mfcr (rt) -> + `Pmfcr( + (trans_out_reg rt)) + | Mtocrf (rs, fxm) -> + `Pmtocrf( + (trans_out_int fxm), + (trans_out_reg rs)) + | Mfocrf (rt, fxm) -> + `Pmfocrf( + (trans_out_reg rt), + (trans_out_int fxm)) + | Mcrxr (bf) -> + `Pmcrxr( + (trans_out_int bf)) + | Dlmzb (rs, ra, rb, rc) -> + `Pdlmzb( + (trans_out_cr0 rc), + (trans_out_reg ra), + (trans_out_reg rs), + (trans_out_reg rb)) + | Macchw (rt, ra, rb, oe, rc) -> + `Pmacchw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Macchws (rt, ra, rb, oe, rc) -> + `Pmacchws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Macchwu (rt, ra, rb, oe, rc) -> + `Pmacchwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Macchwsu (rt, ra, rb, oe, rc) -> + `Pmacchwsu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Machhw (rt, ra, rb, oe, rc) -> + `Pmachhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Machhws (rt, ra, rb, oe, rc) -> + `Pmachhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Machhwu (rt, ra, rb, oe, rc) -> + `Pmachhwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Machhwsu (rt, ra, rb, oe, rc) -> + `Pmachhwsu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Maclhw (rt, ra, rb, oe, rc) -> + `Pmaclhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Maclhws (rt, ra, rb, oe, rc) -> + `Pmaclhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Maclhwu (rt, ra, rb, oe, rc) -> + `Pmaclhwu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Maclhwsu (rt, ra, rb, oe, rc) -> + `Pmaclhwsu( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulchw (rt, ra, rb, rc) -> + `Pmulchw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulchwu (rt, ra, rb, rc) -> + `Pmulchwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulhhw (rt, ra, rb, rc) -> + `Pmulhhw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mulhhwu (rt, ra, rb, rc) -> + `Pmulhhwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mullhw (rt, ra, rb, rc) -> + `Pmullhw( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Mullhwu (rt, ra, rb, rc) -> + `Pmullhwu( + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Nmacchw (rt, ra, rb, oe, rc) -> + `Pnmacchw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Nmacchws (rt, ra, rb, oe, rc) -> + `Pnmacchws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Nmachhw (rt, ra, rb, oe, rc) -> + `Pnmachhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Nmachhws (rt, ra, rb, oe, rc) -> + `Pnmachhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Nmaclhw (rt, ra, rb, oe, rc) -> + `Pnmaclhw( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Nmaclhws (rt, ra, rb, oe, rc) -> + `Pnmaclhws( + (trans_out_soov oe), + (trans_out_cr0 rc), + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb)) + | Icbi (ra, rb) -> + `Picbi( + (trans_out_reg ra), + (trans_out_reg rb)) + | Icbt (ct, ra, rb) -> + `Picbt( + (trans_out_int ct), + (trans_out_reg ra), + (trans_out_reg rb)) + | Dcba (ra, rb) -> + `Pdcba( + (trans_out_reg ra), + (trans_out_reg rb)) + | Dcbt (th, ra, rb) -> + `Pdcbt( + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int th)) + | Dcbtst (th, ra, rb) -> + `Pdcbtst( + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int th)) + | Dcbz (ra, rb) -> + `Pdcbz( + (trans_out_reg ra), + (trans_out_reg rb)) + | Dcbst (ra, rb) -> + `Pdcbst( + (trans_out_reg ra), + (trans_out_reg rb)) + | Dcbf (l, ra, rb) -> + `Pdcbf( + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_int l)) + | Isync -> + `Pisync + + | Lbarx (rt, ra, rb, eh) -> + `Plbarx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_bit eh)) + | Lharx (rt, ra, rb, eh) -> + `Plharx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_bit eh)) + | Lwarx (rt, ra, rb, eh) -> + `Plwarx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_bit eh)) + | Stbcx (rs, ra, rb) -> + `Pstbcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Sthcx (rs, ra, rb) -> + `Psthcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Stwcx (rs, ra, rb) -> + `Pstwcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Ldarx (rt, ra, rb, eh) -> + `Pldarx( + (trans_out_reg rt), + (trans_out_reg ra), + (trans_out_reg rb), + (trans_out_bit eh)) + | Stdcx (rs, ra, rb) -> + `Pstdcx( + (trans_out_reg rs), + (trans_out_reg ra), + (trans_out_reg rb)) + | Sync (l) -> + `Psync( + (trans_out_int l)) + | Eieio -> + `Peieio + + | Wait (wc) -> + `Pwait( + (trans_out_int wc)) diff --git a/old/power/gen/shallow_types_to_herdtools_types.hgen b/old/power/gen/shallow_types_to_herdtools_types.hgen new file mode 100644 index 00000000..c08b0131 --- /dev/null +++ b/old/power/gen/shallow_types_to_herdtools_types.hgen @@ -0,0 +1,150 @@ +let trans_out_int fbits = + Nat_big_num.to_int (Sail_values.unsigned fbits) + +let trans_out_bit = function + | Sail_values.B1 -> 1 + | Sail_values.B0 -> 0 + | Sail_values.BU -> failwith "trans_out_bit given Undef bit" + + +let trans_out_reg flv = + let n = trans_out_int flv in + Ireg (match n with + | 0 -> GPR0 + | 1 -> GPR1 + | 2 -> GPR2 + | 3 -> GPR3 + | 4 -> GPR4 + | 5 -> GPR5 + | 6 -> GPR6 + | 7 -> GPR7 + | 8 -> GPR8 + | 9 -> GPR9 + | 10 -> GPR10 + | 11 -> GPR11 + | 12 -> GPR12 + | 13 -> GPR13 + | 14 -> GPR14 + | 15 -> GPR15 + | 16 -> GPR16 + | 17 -> GPR17 + | 18 -> GPR18 + | 19 -> GPR19 + | 20 -> GPR20 + | 21 -> GPR21 + | 22 -> GPR22 + | 23 -> GPR23 + | 24 -> GPR24 + | 25 -> GPR25 + | 26 -> GPR26 + | 27 -> GPR27 + | 28 -> GPR28 + | 29 -> GPR29 + | 30 -> GPR30 + | 31 -> GPR31 + | _ -> failwith "trans_out_reg given number not 0 to 31") + +let trans_out_soov = function + | Sail_values.B1 -> SetSOOV + | Sail_values.B0 -> DontSetSOOV + | _ -> failwith "trans_out_soov given undef bit" + +let trans_out_cr0 = function + | Sail_values.B1 -> SetCR0 + | Sail_values.B0 -> DontSetCR0 + | _ -> failwith "trans_out_cr0 given undef bit" + +let trans_out_aa = function + | Sail_values.B1 -> SetAA + | Sail_values.B0 -> DontSetAA + | _ -> failwith "trans_out_aa given undef bit" + +let trans_out_lk = function + | Sail_values.B1 -> SetLK + | Sail_values.B0 -> DontSetLK + | _ -> failwith "trans_out_lk given undef bit" + +(*These probably need to be checked that the shift is the correct thing to do*) +(* translating branch target addresses *) +(* CP: this seems to assume a different parameter order from how it's used, this + was undetected because the previous field value representation was "untyped", + trying to fix this now. *) +(* let trans_out_li_setaa_setlk_k3 setaa setlk li = + match li with + | (n,m,bits) -> + match bits with + | [] | [_] | [_;_] -> (n,m,bits) + | _ -> + (n,m, (let front,rest = List.hd bits, List.tl bits in + let second,rest = List.hd rest, List.tl rest in + rest @ [front;second])) *) +let trans_out_li_setaa_setlk_k3 li setaa setlk = + match li with + | Sail_values.Vector (bits,start,is_inc) -> + Sail_values.Vector (bits @ [Sail_values.B0;Sail_values.B0],start,is_inc) + +(* CP: same here *) +(* let trans_out_bd_setaa_setlk_k_k_k5 setaa setlk bo bi bd = + match bd with + | (n,m,bits) -> + match bits with + | [] | [_] | [_;_] -> (n,m,bits) + | _ -> + (n,m, (let front,rest = List.hd bits, List.tl bits in + let second,rest = List.hd rest, List.tl rest in + rest @ [front;second])) *) +let trans_out_bd_setaa_setlk_k_k_k5 bo bi bd setaa setlk = + match bd with + | Sail_values.Vector (bits,start,is_inc) -> + Sail_values.Vector (bits @ [Sail_values.B0;Sail_values.B0],start,is_inc) + +(* translating vector-scalar floating-point ops *) +(* all of these translate a 6-bit value into a 5:1 bit pair, but differ + in number and type of arguments *) +(*this is probably wrong, probably I want to do a transformation on the bits then return, but unclear what translation*) +let trans_out_k xt = xt +let trans_out_xk xt = xt +let trans_out_t_k_k4 xt _ _ _ = trans_out_k xt +let trans_out_tx_k_k4 xt _ _ _ = trans_out_xk xt +let trans_out_t_k_reg_reg4 xt xa _ _ = trans_out_k xt +let trans_out_tx_k_reg_reg4 xt xa _ _ = trans_out_xk xt +let trans_out_s_k_reg_reg4 = trans_out_t_k_reg_reg4 +let trans_out_sx_k_reg_reg4 = trans_out_tx_k_reg_reg4 +let trans_out_t_k_k_k6 x _ _ _ _ _ = trans_out_k x +let trans_out_t_k_k_k5 x _ _ _ _ = trans_out_k x +let trans_out_tx_k_k_k6 x _ _ _ _ _= trans_out_k x +let trans_out_tx_k_k_k5 x _ _ _ _ = trans_out_k x +let trans_out_b_k_k4 = trans_out_t_k_k4 +let trans_out_bx_k_k4 = trans_out_tx_k_k4 +let trans_out_a_k_k_k6 xt xa xb _ _ _ = trans_out_k xa +let trans_out_ax_k_k_k6 xt xa xb _ _ _ = trans_out_xk xa +let trans_out_b_k_k_k6 xt xa xb _ _ _ = trans_out_k xb +let trans_out_b_k_k_k5 xt xa xb _ _ = trans_out_k xb +let trans_out_bx_k_k_k6 xt xa xb _ _ _ = trans_out_xk xb +let trans_out_bx_k_k_k5 xt xa xb _ _ = trans_out_xk xb +let trans_out_a_crindex_k_k5 bf xa xb _ _ = trans_out_k xa +let trans_out_ax_crindex_k_k5 bf xa xb _ _ = trans_out_xk xa +let trans_out_b_crindex_k_k5 bf xa xb _ _ = trans_out_k xb +let trans_out_bx_crindex_k_k5 bf xa xb _ _ = trans_out_xk xb +let trans_out_b_crindex_k3 bf xb _ = trans_out_k xb +let trans_out_bx_crindex_k3 bf xb _ = trans_out_xk xb +let trans_out_t_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_k xt +let trans_out_tx_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_xk xt +let trans_out_a_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_k xa +let trans_out_ax_setcr0_k_k_k7 setcr0 xt xa xb _ _ _= trans_out_xk xa +let trans_out_b_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_k xb +let trans_out_bx_setcr0_k_k_k7 setcr0 xt xa xb _ _ _ = trans_out_xk xb +let trans_out_t_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_k xt +let trans_out_tx_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_xk xt +let trans_out_t_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_k xt +let trans_out_tx_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_xk xt +let trans_out_a_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_k xa +let trans_out_ax_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_xk xa +let trans_out_a_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_k xa +let trans_out_ax_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_xk xa +let trans_out_b_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_k xb +let trans_out_bx_k_k_k_k7 xt xa xb dm _ _ _ = trans_out_xk xb +let trans_out_b_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_k xb +let trans_out_bx_k_k_k_k8 xt xa xb dm _ _ _ _ = trans_out_xk xb +let trans_out_c_k_k_k_k8 xt xa xb xc _ _ _ _ = trans_out_k xc +let trans_out_cx_k_k_k_k8 xt xa xb xc _ _ _ _ = trans_out_xk xc
\ No newline at end of file diff --git a/old/power/gen/tokens.gen b/old/power/gen/tokens.gen new file mode 100644 index 00000000..f9022936 --- /dev/null +++ b/old/power/gen/tokens.gen @@ -0,0 +1,368 @@ +%token B +%token BA +%token BL +%token BLA +%token BC +%token BCA +%token BCL +%token BCLA +%token BCLR +%token BCLRL +%token BCCTR +%token BCCTRL +%token CRAND +%token CRNAND +%token CROR +%token CRXOR +%token CRNOR +%token CREQV +%token CRANDC +%token CRORC +%token MCRF +%token SC +%token SCV +%token LBZ +%token LBZX +%token LBZU +%token LBZUX +%token LHZ +%token LHZX +%token LHZU +%token LHZUX +%token LHA +%token LHAX +%token LHAU +%token LHAUX +%token LWZ +%token LWZX +%token LWZU +%token LWZUX +%token LWA +%token LWAX +%token LWAUX +%token LD +%token LDX +%token LDU +%token LDUX +%token STB +%token STBX +%token STBU +%token STBUX +%token STH +%token STHX +%token STHU +%token STHUX +%token STW +%token STWX +%token STWU +%token STWUX +%token STD +%token STDX +%token STDU +%token STDUX +%token LQ +%token STQ +%token LHBRX +%token STHBRX +%token LWBRX +%token STWBRX +%token LDBRX +%token STDBRX +%token LMW +%token STMW +%token LSWI +%token LSWX +%token STSWI +%token STSWX +%token ADDI +%token ADDIS +%token ADD +%token ADDDOT +%token ADDO +%token ADDODOT +%token SUBF +%token SUBFDOT +%token SUBFO +%token SUBFODOT +%token ADDIC +%token ADDICDOT +%token SUBFIC +%token ADDC +%token ADDCDOT +%token ADDCO +%token ADDCODOT +%token SUBFC +%token SUBFCDOT +%token SUBFCO +%token SUBFCODOT +%token ADDE +%token ADDEDOT +%token ADDEO +%token ADDEODOT +%token SUBFE +%token SUBFEDOT +%token SUBFEO +%token SUBFEODOT +%token ADDME +%token ADDMEDOT +%token ADDMEO +%token ADDMEODOT +%token SUBFME +%token SUBFMEDOT +%token SUBFMEO +%token SUBFMEODOT +%token ADDZE +%token ADDZEDOT +%token ADDZEO +%token ADDZEODOT +%token SUBFZE +%token SUBFZEDOT +%token SUBFZEO +%token SUBFZEODOT +%token NEG +%token NEGDOT +%token NEGO +%token NEGODOT +%token MULLI +%token MULLW +%token MULLWDOT +%token MULLWO +%token MULLWODOT +%token MULHW +%token MULHWDOT +%token MULHWU +%token MULHWUDOT +%token DIVW +%token DIVWDOT +%token DIVWO +%token DIVWODOT +%token DIVWU +%token DIVWUDOT +%token DIVWUO +%token DIVWUODOT +%token DIVWE +%token DIVWEDOT +%token DIVWEO +%token DIVWEODOT +%token DIVWEU +%token DIVWEUDOT +%token DIVWEUO +%token DIVWEUODOT +%token MULLD +%token MULLDDOT +%token MULLDO +%token MULLDODOT +%token MULHD +%token MULHDDOT +%token MULHDU +%token MULHDUDOT +%token DIVD +%token DIVDDOT +%token DIVDO +%token DIVDODOT +%token DIVDU +%token DIVDUDOT +%token DIVDUO +%token DIVDUODOT +%token DIVDE +%token DIVDEDOT +%token DIVDEO +%token DIVDEODOT +%token DIVDEU +%token DIVDEUDOT +%token DIVDEUO +%token DIVDEUODOT +%token CMPI +%token CMP +%token CMPLI +%token CMPL +%token ISEL +%token ANDIDOT +%token ANDISDOT +%token ORI +%token ORIS +%token XORI +%token XORIS +%token AND +%token ANDDOT +%token XOR +%token XORDOT +%token NAND +%token NANDDOT +%token OR +%token ORDOT +%token NOR +%token NORDOT +%token EQV +%token EQVDOT +%token ANDC +%token ANDCDOT +%token ORC +%token ORCDOT +%token EXTSB +%token EXTSBDOT +%token EXTSH +%token EXTSHDOT +%token CNTLZW +%token CNTLZWDOT +%token CMPB +%token POPCNTB +%token POPCNTW +%token PRTYD +%token PRTYW +%token EXTSW +%token EXTSWDOT +%token CNTLZD +%token CNTLZDDOT +%token POPCNTD +%token BPERMD +%token RLWINM +%token RLWINMDOT +%token RLWNM +%token RLWNMDOT +%token RLWIMI +%token RLWIMIDOT +%token RLDICL +%token RLDICLDOT +%token RLDICR +%token RLDICRDOT +%token RLDIC +%token RLDICDOT +%token RLDCL +%token RLDCLDOT +%token RLDCR +%token RLDCRDOT +%token RLDIMI +%token RLDIMIDOT +%token SLW +%token SLWDOT +%token SRW +%token SRWDOT +%token SRAWI +%token SRAWIDOT +%token SRAW +%token SRAWDOT +%token SLD +%token SLDDOT +%token SRD +%token SRDDOT +%token SRADI +%token SRADIDOT +%token SRAD +%token SRADDOT +%token CDTBCD +%token CBCDTD +%token ADDG6S +%token MTSPR +%token MFSPR +%token MTCRF +%token MFCR +%token MTOCRF +%token MFOCRF +%token MCRXR +%token DLMZB +%token DLMZBDOT +%token MACCHW +%token MACCHWDOT +%token MACCHWO +%token MACCHWODOT +%token MACCHWS +%token MACCHWSDOT +%token MACCHWSO +%token MACCHWSODOT +%token MACCHWU +%token MACCHWUDOT +%token MACCHWUO +%token MACCHWUODOT +%token MACCHWSU +%token MACCHWSUDOT +%token MACCHWSUO +%token MACCHWSUODOT +%token MACHHW +%token MACHHWDOT +%token MACHHWO +%token MACHHWODOT +%token MACHHWS +%token MACHHWSDOT +%token MACHHWSO +%token MACHHWSODOT +%token MACHHWU +%token MACHHWUDOT +%token MACHHWUO +%token MACHHWUODOT +%token MACHHWSU +%token MACHHWSUDOT +%token MACHHWSUO +%token MACHHWSUODOT +%token MACLHW +%token MACLHWDOT +%token MACLHWO +%token MACLHWODOT +%token MACLHWS +%token MACLHWSDOT +%token MACLHWSO +%token MACLHWSODOT +%token MACLHWU +%token MACLHWUDOT +%token MACLHWUO +%token MACLHWUODOT +%token MACLHWSU +%token MACLHWSUDOT +%token MACLHWSUO +%token MACLHWSUODOT +%token MULCHW +%token MULCHWDOT +%token MULCHWU +%token MULCHWUDOT +%token MULHHW +%token MULHHWDOT +%token MULHHWU +%token MULHHWUDOT +%token MULLHW +%token MULLHWDOT +%token MULLHWU +%token MULLHWUDOT +%token NMACCHW +%token NMACCHWDOT +%token NMACCHWO +%token NMACCHWODOT +%token NMACCHWS +%token NMACCHWSDOT +%token NMACCHWSO +%token NMACCHWSODOT +%token NMACHHW +%token NMACHHWDOT +%token NMACHHWO +%token NMACHHWODOT +%token NMACHHWS +%token NMACHHWSDOT +%token NMACHHWSO +%token NMACHHWSODOT +%token NMACLHW +%token NMACLHWDOT +%token NMACLHWO +%token NMACLHWODOT +%token NMACLHWS +%token NMACLHWSDOT +%token NMACLHWSO +%token NMACLHWSODOT +%token ICBI +%token ICBT +%token DCBA +%token DCBT +%token DCBTST +%token DCBZ +%token DCBST +%token DCBF +%token ISYNC +%token LBARX +%token LHARX +%token LWARX +%token STBCXDOT +%token STHCXDOT +%token STWCXDOT +%token LDARX +%token STDCXDOT +%token SYNC +%token EIEIO +%token WAIT diff --git a/old/power/gen/trans_sail.gen b/old/power/gen/trans_sail.gen new file mode 100644 index 00000000..b6f406f2 --- /dev/null +++ b/old/power/gen/trans_sail.gen @@ -0,0 +1,1516 @@ + | `Pb(setaa0, setlk1, k2) -> + ("B", + [("LI", IInt.Bvector (Some 24), SB.bit_list_of_integer 24 (Nat_big_num.of_int (trans_li_setaa_setlk_k setaa0 setlk1 k2))); + ("AA", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_aa setaa0))); + ("LK", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_lk setlk1)))], + [(* always empty base effects*)] + ) + | `Pbc(setaa0, setlk1, k2, k3, k4) -> + ("Bc", + [("BO", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2)); + ("BI", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k3)); + ("BD", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int (trans_bd_setaa_setlk_k_k_k setaa0 setlk1 k2 k3 k4))); + ("AA", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_aa setaa0))); + ("LK", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_lk setlk1)))], + [(* always empty base effects*)] + ) + | `Pbclr(setlk0, k1, k2, k3) -> + ("Bclr", + [("BO", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BI", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2)); + ("BH", IInt.Bvector (Some 2), SB.bit_list_of_integer 2 (Nat_big_num.of_int k3)); + ("LK", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_lk setlk0)))], + [(* always empty base effects*)] + ) + | `Pbcctr(setlk0, k1, k2, k3) -> + ("Bcctr", + [("BO", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BI", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2)); + ("BH", IInt.Bvector (Some 2), SB.bit_list_of_integer 2 (Nat_big_num.of_int k3)); + ("LK", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_lk setlk0)))], + [(* always empty base effects*)] + ) + | `Pcrand(k0, k1, k2) -> + ("Crand", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcrnand(k0, k1, k2) -> + ("Crnand", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcror(k0, k1, k2) -> + ("Cror", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcrxor(k0, k1, k2) -> + ("Crxor", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcrnor(k0, k1, k2) -> + ("Crnor", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcreqv(k0, k1, k2) -> + ("Creqv", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcrandc(k0, k1, k2) -> + ("Crandc", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pcrorc(k0, k1, k2) -> + ("Crorc", + [("BT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("BA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("BB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pmcrf(crindex0, k1) -> + ("Mcrf", + [("BF", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int crindex0)); + ("BFA", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Psc(k0) -> + ("Sc", + [("LEV", IInt.Bvector (Some 7), SB.bit_list_of_integer 7 (Nat_big_num.of_int k0))], + [(* always empty base effects*)] + ) + | `Pscv(k0) -> + ("Scv", + [("LEV", IInt.Bvector (Some 7), SB.bit_list_of_integer 7 (Nat_big_num.of_int k0))], + [(* always empty base effects*)] + ) + | `Plbz(reg0, k1, reg2) -> + ("Lbz", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plbzx(reg0, reg1, reg2) -> + ("Lbzx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plbzu(reg0, k1, reg2) -> + ("Lbzu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plbzux(reg0, reg1, reg2) -> + ("Lbzux", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plhz(reg0, k1, reg2) -> + ("Lhz", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plhzx(reg0, reg1, reg2) -> + ("Lhzx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plhzu(reg0, k1, reg2) -> + ("Lhzu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plhzux(reg0, reg1, reg2) -> + ("Lhzux", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plha(reg0, k1, reg2) -> + ("Lha", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plhax(reg0, reg1, reg2) -> + ("Lhax", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plhau(reg0, k1, reg2) -> + ("Lhau", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plhaux(reg0, reg1, reg2) -> + ("Lhaux", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plwz(reg0, k1, reg2) -> + ("Lwz", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plwzx(reg0, reg1, reg2) -> + ("Lwzx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plwzu(reg0, k1, reg2) -> + ("Lwzu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plwzux(reg0, reg1, reg2) -> + ("Lwzux", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plwa(reg0, ds1, reg2) -> + ("Lwa", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DS", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int ds1))], + [(* always empty base effects*)] + ) + | `Plwax(reg0, reg1, reg2) -> + ("Lwax", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plwaux(reg0, reg1, reg2) -> + ("Lwaux", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pld(reg0, ds1, reg2) -> + ("Ld", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DS", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int ds1))], + [(* always empty base effects*)] + ) + | `Pldx(reg0, reg1, reg2) -> + ("Ldx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pldu(reg0, ds1, reg2) -> + ("Ldu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DS", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int ds1))], + [(* always empty base effects*)] + ) + | `Pldux(reg0, reg1, reg2) -> + ("Ldux", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstb(reg0, k1, reg2) -> + ("Stb", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Pstbx(reg0, reg1, reg2) -> + ("Stbx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstbu(reg0, k1, reg2) -> + ("Stbu", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Pstbux(reg0, reg1, reg2) -> + ("Stbux", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Psth(reg0, k1, reg2) -> + ("Sth", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Psthx(reg0, reg1, reg2) -> + ("Sthx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Psthu(reg0, k1, reg2) -> + ("Sthu", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Psthux(reg0, reg1, reg2) -> + ("Sthux", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstw(reg0, k1, reg2) -> + ("Stw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Pstwx(reg0, reg1, reg2) -> + ("Stwx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstwu(reg0, k1, reg2) -> + ("Stwu", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Pstwux(reg0, reg1, reg2) -> + ("Stwux", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstd(reg0, ds1, reg2) -> + ("Std", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DS", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int ds1))], + [(* always empty base effects*)] + ) + | `Pstdx(reg0, reg1, reg2) -> + ("Stdx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstdu(reg0, ds1, reg2) -> + ("Stdu", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DS", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int ds1))], + [(* always empty base effects*)] + ) + | `Pstdux(reg0, reg1, reg2) -> + ("Stdux", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plq(k0, k1, reg2, k3) -> + ("Lq", + [("RTp", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DQ", IInt.Bvector (Some 12), SB.bit_list_of_integer 12 (Nat_big_num.of_int k1)); + ("PT", IInt.Bvector (Some 4), SB.bit_list_of_integer 4 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Pstq(k0, ds1, reg2) -> + ("Stq", + [("RSp", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("DS", IInt.Bvector (Some 14), SB.bit_list_of_integer 14 (Nat_big_num.of_int ds1))], + [(* always empty base effects*)] + ) + | `Plhbrx(reg0, reg1, reg2) -> + ("Lhbrx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Psthbrx(reg0, reg1, reg2) -> + ("Sthbrx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plwbrx(reg0, reg1, reg2) -> + ("Lwbrx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstwbrx(reg0, reg1, reg2) -> + ("Stwbrx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pldbrx(reg0, reg1, reg2) -> + ("Ldbrx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstdbrx(reg0, reg1, reg2) -> + ("Stdbrx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Plmw(reg0, k1, reg2) -> + ("Lmw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Pstmw(reg0, k1, reg2) -> + ("Stmw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("D", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Plswi(k0, reg1, k2) -> + ("Lswi", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("NB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Plswx(reg0, reg1, reg2) -> + ("Lswx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstswi(k0, reg1, k2) -> + ("Stswi", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("NB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pstswx(k0, reg1, reg2) -> + ("Stswx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k0)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Paddi(reg0, reg1, k2) -> + ("Addi", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Paddis(reg0, reg1, k2) -> + ("Addis", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Padd(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Add", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Psubf(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Subf", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Paddic(reg0, reg1, k2) -> + ("Addic", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Paddicdot(reg0, reg1, k2) -> + ("AddicDot", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Psubfic(reg0, reg1, k2) -> + ("Subfic", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Paddc(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Addc", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Psubfc(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Subfc", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Padde(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Adde", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Psubfe(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Subfe", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Paddme(setsoov0, setcr01, reg2, reg3) -> + ("Addme", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Psubfme(setsoov0, setcr01, reg2, reg3) -> + ("Subfme", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Paddze(setsoov0, setcr01, reg2, reg3) -> + ("Addze", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Psubfze(setsoov0, setcr01, reg2, reg3) -> + ("Subfze", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pneg(setsoov0, setcr01, reg2, reg3) -> + ("Neg", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmulli(reg0, reg1, k2) -> + ("Mulli", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pmullw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Mullw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmulhw(setcr00, reg1, reg2, reg3) -> + ("Mulhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmulhwu(setcr00, reg1, reg2, reg3) -> + ("Mulhwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pdivw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pdivwu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pdivwe(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divwe", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pdivweu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divweu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmulld(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Mulld", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmulhd(setcr00, reg1, reg2, reg3) -> + ("Mulhd", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmulhdu(setcr00, reg1, reg2, reg3) -> + ("Mulhdu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pdivd(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divd", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pdivdu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divdu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pdivde(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divde", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pdivdeu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Divdeu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pcmpi(crindex0, k1, reg2, k3) -> + ("Cmpi", + [("BF", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int crindex0)); + ("L", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k1)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("SI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Pcmp(crindex0, k1, reg2, reg3) -> + ("Cmp", + [("BF", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int crindex0)); + ("L", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k1)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3)))], + [(* always empty base effects*)] + ) + | `Pcmpli(crindex0, k1, reg2, k3) -> + ("Cmpli", + [("BF", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int crindex0)); + ("L", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k1)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Pcmpl(crindex0, k1, reg2, reg3) -> + ("Cmpl", + [("BF", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int crindex0)); + ("L", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k1)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3)))], + [(* always empty base effects*)] + ) + | `Pisel(reg0, reg1, reg2, k3) -> + ("Isel", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("BC", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Pandi(reg0, reg1, k2) -> + ("Andi", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pandis(reg0, reg1, k2) -> + ("Andis", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pori(reg0, reg1, k2) -> + ("Ori", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Poris(reg0, reg1, k2) -> + ("Oris", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pxori(reg0, reg1, k2) -> + ("Xori", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pxoris(reg0, reg1, k2) -> + ("Xoris", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("UI", IInt.Bvector (Some 16), SB.bit_list_of_integer 16 (Nat_big_num.of_int k2))], + [(* always empty base effects*)] + ) + | `Pand(setcr00, reg1, reg2, reg3) -> + ("And", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pxor(setcr00, reg1, reg2, reg3) -> + ("Xor", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pnand(setcr00, reg1, reg2, reg3) -> + ("Nand", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Por(setcr00, reg1, reg2, reg3) -> + ("Or", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pnor(setcr00, reg1, reg2, reg3) -> + ("Nor", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Peqv(setcr00, reg1, reg2, reg3) -> + ("Eqv", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pandc(setcr00, reg1, reg2, reg3) -> + ("Andc", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Porc(setcr00, reg1, reg2, reg3) -> + ("Orc", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pextsb(setcr00, reg1, reg2) -> + ("Extsb", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pextsh(setcr00, reg1, reg2) -> + ("Extsh", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pcntlzw(setcr00, reg1, reg2) -> + ("Cntlzw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pcmpb(reg0, k1, reg2) -> + ("Cmpb", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k1)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Ppopcntb(reg0, reg1) -> + ("Popcntb", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Ppopcntw(reg0, reg1) -> + ("Popcntw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Pprtyd(reg0, reg1) -> + ("Prtyd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Pprtyw(reg0, reg1) -> + ("Prtyw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Pextsw(setcr00, reg1, reg2) -> + ("Extsw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pcntlzd(setcr00, reg1, reg2) -> + ("Cntlzd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Ppopcntd(reg0, reg1) -> + ("Popcntd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Pbpermd(reg0, reg1, reg2) -> + ("Bpermd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Prlwinm(setcr00, reg1, reg2, k3, k4, k5) -> + ("Rlwinm", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SH", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k3)); + ("MB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k4)); + ("ME", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k5)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prlwnm(setcr00, reg1, reg2, reg3, k4, k5) -> + ("Rlwnm", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("MB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k4)); + ("ME", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k5)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prlwimi(setcr00, reg1, reg2, k3, k4, k5) -> + ("Rlwimi", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SH", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k3)); + ("MB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k4)); + ("ME", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k5)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prldicl(setcr00, reg1, reg2, k3, k4) -> + ("Rldicl", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("sh", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k3)); + ("mb", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k4)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prldicr(setcr00, reg1, reg2, k3, k4) -> + ("Rldicr", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("sh", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k3)); + ("me", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k4)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prldic(setcr00, reg1, reg2, k3, k4) -> + ("Rldic", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("sh", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k3)); + ("mb", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k4)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prldcl(setcr00, reg1, reg2, reg3, k4) -> + ("Rldcl", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("mb", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k4)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prldcr(setcr00, reg1, reg2, reg3, k4) -> + ("Rldcr", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("me", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k4)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Prldimi(setcr00, reg1, reg2, k3, k4) -> + ("Rldimi", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("sh", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k3)); + ("mb", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k4)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pslw(setcr00, reg1, reg2, reg3) -> + ("Slw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psrw(setcr00, reg1, reg2, reg3) -> + ("Srw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psrawi(setcr00, reg1, reg2, k3) -> + ("Srawi", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("SH", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k3)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psraw(setcr00, reg1, reg2, reg3) -> + ("Sraw", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psld(setcr00, reg1, reg2, reg3) -> + ("Sld", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psrd(setcr00, reg1, reg2, reg3) -> + ("Srd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psradi(setcr00, reg1, reg2, k3) -> + ("Sradi", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("sh", IInt.Bvector (Some 6), SB.bit_list_of_integer 6 (Nat_big_num.of_int k3)); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Psrad(setcr00, reg1, reg2, reg3) -> + ("Srad", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pcdtbcd(reg0, reg1) -> + ("Cdtbcd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Pcbcdtd(reg0, reg1) -> + ("Cbcdtd", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Paddg6s(reg0, reg1, reg2) -> + ("Addg6s", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pmtspr(k0, reg1) -> + ("Mtspr", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("spr", IInt.Bvector (Some 10), SB.bit_list_of_integer 10 (Nat_big_num.of_int k0))], + [(* always empty base effects*)] + ) + | `Pmfspr(reg0, k1) -> + ("Mfspr", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("spr", IInt.Bvector (Some 10), SB.bit_list_of_integer 10 (Nat_big_num.of_int k1))], + [(* always empty base effects*)] + ) + | `Pmtcrf(crmask0, reg1) -> + ("Mtcrf", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("FXM", IInt.Bvector (Some 8), SB.bit_list_of_integer 8 (Nat_big_num.of_int crmask0))], + [(* always empty base effects*)] + ) + | `Pmfcr(reg0) -> + ("Mfcr", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0)))], + [(* always empty base effects*)] + ) + | `Pmtocrf(crmask0, reg1) -> + ("Mtocrf", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("FXM", IInt.Bvector (Some 8), SB.bit_list_of_integer 8 (Nat_big_num.of_int crmask0))], + [(* always empty base effects*)] + ) + | `Pmfocrf(reg0, crmask1) -> + ("Mfocrf", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("FXM", IInt.Bvector (Some 8), SB.bit_list_of_integer 8 (Nat_big_num.of_int crmask1))], + [(* always empty base effects*)] + ) + | `Pmcrxr(crindex0) -> + ("Mcrxr", + [("BF", IInt.Bvector (Some 3), SB.bit_list_of_integer 3 (Nat_big_num.of_int crindex0))], + [(* always empty base effects*)] + ) + | `Pdlmzb(setcr00, reg1, reg2, reg3) -> + ("Dlmzb", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmacchw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Macchw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmacchws(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Macchws", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmacchwu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Macchwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmacchwsu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Macchwsu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmachhw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Machhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmachhws(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Machhws", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmachhwu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Machhwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmachhwsu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Machhwsu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmaclhw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Maclhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmaclhws(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Maclhws", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmaclhwu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Maclhwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmaclhwsu(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Maclhwsu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pmulchw(setcr00, reg1, reg2, reg3) -> + ("Mulchw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmulchwu(setcr00, reg1, reg2, reg3) -> + ("Mulchwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmulhhw(setcr00, reg1, reg2, reg3) -> + ("Mulhhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmulhhwu(setcr00, reg1, reg2, reg3) -> + ("Mulhhwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmullhw(setcr00, reg1, reg2, reg3) -> + ("Mullhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pmullhwu(setcr00, reg1, reg2, reg3) -> + ("Mullhwu", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr00)))], + [(* always empty base effects*)] + ) + | `Pnmacchw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Nmacchw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pnmacchws(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Nmacchws", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pnmachhw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Nmachhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pnmachhws(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Nmachhws", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pnmaclhw(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Nmaclhw", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Pnmaclhws(setsoov0, setcr01, reg2, reg3, reg4) -> + ("Nmaclhws", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg3))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg4))); + ("OE", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_soov setsoov0))); + ("Rc", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int (trans_cr0 setcr01)))], + [(* always empty base effects*)] + ) + | `Picbi(reg0, reg1) -> + ("Icbi", + [("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Picbt(k0, reg1, reg2) -> + ("Icbt", + [("CT", IInt.Bvector (Some 4), SB.bit_list_of_integer 4 (Nat_big_num.of_int k0)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pdcba(reg0, reg1) -> + ("Dcba", + [("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Pdcbt(reg0, reg1, k2) -> + ("Dcbt", + [("TH", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Pdcbtst(reg0, reg1, k2) -> + ("Dcbtst", + [("TH", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int k2)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Pdcbz(reg0, reg1) -> + ("Dcbz", + [("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Pdcbst(reg0, reg1) -> + ("Dcbst", + [("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Pdcbf(reg0, reg1, k2) -> + ("Dcbf", + [("L", IInt.Bvector (Some 2), SB.bit_list_of_integer 2 (Nat_big_num.of_int k2)); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1)))], + [(* always empty base effects*)] + ) + | `Pisync -> + ("Isync", + [], + [(* always empty base effects*)] + ) + | `Plbarx(reg0, reg1, reg2, k3) -> + ("Lbarx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("EH", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Plharx(reg0, reg1, reg2, k3) -> + ("Lharx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("EH", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Plwarx(reg0, reg1, reg2, k3) -> + ("Lwarx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("EH", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Pstbcx(reg0, reg1, reg2) -> + ("Stbcx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Psthcx(reg0, reg1, reg2) -> + ("Sthcx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pstwcx(reg0, reg1, reg2) -> + ("Stwcx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Pldarx(reg0, reg1, reg2, k3) -> + ("Ldarx", + [("RT", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2))); + ("EH", IInt.Bit, SB.bit_list_of_integer 1 (Nat_big_num.of_int k3))], + [(* always empty base effects*)] + ) + | `Pstdcx(reg0, reg1, reg2) -> + ("Stdcx", + [("RS", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg0))); + ("RA", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg1))); + ("RB", IInt.Bvector (Some 5), SB.bit_list_of_integer 5 (Nat_big_num.of_int (int_of_reg reg2)))], + [(* always empty base effects*)] + ) + | `Psync(k0) -> + ("Sync", + [("L", IInt.Bvector (Some 2), SB.bit_list_of_integer 2 (Nat_big_num.of_int k0))], + [(* always empty base effects*)] + ) + | `Peieio -> + ("Eieio", + [], + [(* always empty base effects*)] + ) + | `Pwait(k0) -> + ("Wait", + [("WC", IInt.Bvector (Some 2), SB.bit_list_of_integer 2 (Nat_big_num.of_int k0))], + [(* always empty base effects*)] + ) diff --git a/old/power/gen/trans_sail_types.hgen b/old/power/gen/trans_sail_types.hgen new file mode 100644 index 00000000..380fd6e7 --- /dev/null +++ b/old/power/gen/trans_sail_types.hgen @@ -0,0 +1,61 @@ +(* SS: should re-check interpretation of 1 and 0 *) +let trans_soov = function + | SetSOOV -> 1 + | DontSetSOOV -> 0 + +let trans_cr0 = function + | SetCR0 -> 1 + | DontSetCR0 -> 0 + +let trans_aa = function + | SetAA -> 1 + | DontSetAA -> 0 + +let trans_lk = function + | SetLK -> 1 + | DontSetLK -> 0 + + +(* translating branch target addresses *) +let trans_li_setaa_setlk_k setaa setlk li = li asr 2 +let trans_bd_setaa_setlk_k_k_k setaa setlk bo bi bd = bd asr 2 + +(* translating vector-scalar floating-point ops *) +(* all of these translate a 6-bit value into a 5:1 bit pair, but differ + in number and type of arguments *) +let trans_k xt = xt land 0x1F +let trans_xk xt = xt land 0x20 +let trans_t_k_k xt _ = trans_k xt +let trans_tx_k_k xt _ = trans_xk xt +let trans_t_k_reg_reg xt xa _ = trans_k xt +let trans_tx_k_reg_reg xt xa _ = trans_xk xt +let trans_s_k_reg_reg = trans_t_k_reg_reg +let trans_sx_k_reg_reg = trans_tx_k_reg_reg +let trans_t_k_k_k = trans_t_k_reg_reg +let trans_tx_k_k_k = trans_tx_k_reg_reg +let trans_b_k_k = trans_t_k_k +let trans_bx_k_k = trans_tx_k_k +let trans_a_k_k_k xt xa xb = trans_k xa +let trans_ax_k_k_k xt xa xb = trans_xk xa +let trans_b_k_k_k xt xa xb = trans_k xb +let trans_bx_k_k_k xt xa xb = trans_xk xb +let trans_a_crindex_k_k bf xa xb = trans_k xa +let trans_ax_crindex_k_k bf xa xb = trans_xk xa +let trans_b_crindex_k_k bf xa xb = trans_k xb +let trans_bx_crindex_k_k bf xa xb = trans_xk xb +let trans_b_crindex_k bf xb = trans_k xb +let trans_bx_crindex_k bf xb = trans_xk xb +let trans_t_setcr0_k_k_k setcr0 xt xa xb = trans_k xt +let trans_tx_setcr0_k_k_k setcr0 xt xa xb = trans_xk xt +let trans_a_setcr0_k_k_k setcr0 xt xa xb = trans_k xa +let trans_ax_setcr0_k_k_k setcr0 xt xa xb = trans_xk xa +let trans_b_setcr0_k_k_k setcr0 xt xa xb = trans_k xb +let trans_bx_setcr0_k_k_k setcr0 xt xa xb = trans_xk xb +let trans_t_k_k_k_k xt xa xb dm = trans_k xt +let trans_tx_k_k_k_k xt xa xb dm = trans_xk xt +let trans_a_k_k_k_k xt xa xb dm = trans_k xa +let trans_ax_k_k_k_k xt xa xb dm = trans_xk xa +let trans_b_k_k_k_k xt xa xb dm = trans_k xb +let trans_bx_k_k_k_k xt xa xb dm = trans_xk xb +let trans_c_k_k_k_k xt xa xb xc = trans_k xc +let trans_cx_k_k_k_k xt xa xb xc = trans_xk xc
\ No newline at end of file diff --git a/old/power/power.sail b/old/power/power.sail new file mode 100644 index 00000000..6f55a803 --- /dev/null +++ b/old/power/power.sail @@ -0,0 +1,4611 @@ +(*========================================================================*) +(* *) +(* Copyright (c) 2015-2017 Gabriel Kerneis, Susmit Sarkar, Kathyrn Gray *) +(* Copyright (c) 2015-2017 Peter Sewell *) +(* All rights reserved. *) +(* *) +(* This software was developed by the University of Cambridge Computer *) +(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) +(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in *) +(* the documentation and/or other materials provided with the *) +(* distribution. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) +(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) +(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) +(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) +(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) +(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) +(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) +(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) +(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) +(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) +(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) +(* SUCH DAMAGE. *) +(*========================================================================*) + +(* XXX binary coded decimal *) +(*function bit[12] DEC_TO_BCD ( (bit[10]) declet ) = { + (bit[4]) hundreds := 0; + (bit[4]) tens := 0; + (bit[4]) ones := 0; + foreach (i from 0 to 9) { + if hundreds >= 5 then hundreds := hundreds + 3; + if tens >= 5 then tens := tens + 3; + if ones >= 5 then ones := ones + 3; + hundreds := hundreds << 1; + hundreds[3] := tens[0]; + tens := tens << 1; + tens[3] := ones[0]; + ones := ones << 1; + ones[3] := declet[i] }; + hundreds:tens:ones }*) + +function bit[12] DEC_TO_BCD ( (bit[10]) [p,q,r,s,t,u,v,w,x,y]) = { + a := ((~(s) & v & w) | (t & v & w & s) | (v & w & ~(x))); + b := ((p & s & x & ~(t)) | (p & ~(w)) | (p & ~(v))); + c := ((q & s & x & ~(t)) | (q & ~(w)) | (q & ~(v))); + d := r; + + e := ((v & ~(w) & x) | (s & v & w & x) | (~(t) & v & x & w)); + f := ((p & t & v & w & x & ~(s)) | (s & ~(x) & v) | (s & ~(v))); + g := ((q & t & w & v & x & ~(s)) | (t & ~(x) & v) | (t & ~(v))); + h := u; + + i := ((t & v & w & x) | (s & v & w & x) | (v & ~(w) & ~(x))); + j := ((p & ~(s) & ~(t) & w & v) | (s & v & ~(w) & x) | (p & w & ~(x) & v) | (w & ~(v))); + k := ((q & ~(s) & ~(t) & v & w) | (t & v & ~(w) & x) | (q & v & w & ~(x)) | (x & ~(v))); + m := y; + [a,b,c,d,e,f,g,h,i,j,k,m] +} + +(*function bit[10] BCD_TO_DEC ( (bit[12]) bcd ) = + (bit[10]) (([|2** 10|]) (bcd[0..3] * 100)) + ([|2** 7|]) ((([|2** 7|]) (bcd[4..7] * 10)) + bcd[8..11]) +*) + +function bit[10] BCD_TO_DEC ( (bit[12]) [a,b,c,d,e,f,g,h,i,j,k,m] ) = { + p := ((f & a & i & ~(e)) | (j & a & ~(i)) | (b & ~(a))); + q := ((g & a & i & ~(e)) | (k & a & ~(i)) | (c & ~(a))); + r := d; + s := ((j & ~(a) & e & ~(i)) | (f & ~(i) & ~(e)) | (f & ~(a) & ~(e)) | (e & i)); + t := ((k & ~(a) & e & ~(i)) | (g & ~(i) & ~(e)) | (g & ~(a) & ~(e)) | (a & i)); + u := h; + v := (a | e | i); + w := ((~(e) & j & ~(i)) | (e & i) | a); + x := ((~(a) & k & ~(i)) | (a & i) | e); + y := m; + [p,q,r,s,t,u,v,w,x,y] +} + +(* XXX carry out *) +function forall Nat 'a . bit carry_out ( (bit['a]) _,carry ) = carry +(* XXX Storage control *) +function forall Type 'a . 'a real_addr ( x ) = x +(* XXX For stvxl and lvxl - what does that do? *) +function forall Type 'a . unit mark_as_not_likely_to_be_needed_again_anytime_soon ( x ) = () + +(* XXX *) +val extern forall Nat 'k, Nat 'r, + 0 <= 'k, 'k <= 64, 'r + 'k = 64. + (bit[64], [|'k|]) -> [|0:'r|] effect pure countLeadingZeroes + +function forall Nat 'n, Nat 'm . + bit['m] EXTS_EXPLICIT((bit['n]) v, ([:'m:]) m) = + (v[0] ^^ (m - length(v))) : v + +val forall Nat 'n, Nat 'm, 0 <= 'n, 'n <= 'm, 'm <= 63 . + ([|'n|],[|'m|]) -> bit[64] + effect pure + MASK + +function (bit[64]) MASK(start, stop) = { + (bit[64]) mask_temp := 0; + if(start > stop) then { + mask_temp[start .. 63] := bitone ^^ sub(64, start); + mask_temp[0 .. stop] := bitone ^^ (stop + 1); + } else { + mask_temp[start .. stop ] := bitone ^^ (stop - start + 1); + }; + mask_temp; +} + +val forall Nat 'n, 0 <= 'n, 'n <= 63 . + (bit[64], [|'n|]) -> bit[64] effect pure ROTL + +function (bit[64]) ROTL(v, n) = v[n .. 63] : v[0 .. (n - 1)] + +(* Branch facility registers *) + +typedef cr = register bits [ 32 : 63 ] { + 32 .. 35 : CR0; + 32 : LT; 33 : GT; 34 : EQ; 35 : SO; + 36 .. 39 : CR1; + 36 : FX; 37 : FEX; 38 : VX; 39 : OX; + 40 .. 43 : CR2; + 44 .. 47 : CR3; + 48 .. 51 : CR4; + 52 .. 55 : CR5; + 56 .. 59 : CR6; + (* name clashing - do we need hierarchical naming for fields, or do + we just don't care? LT, GT, etc. are not used in the code anyway. + 56 : LT; 57 : GT; 58 : EQ; 59 : SO; + *) + 60 .. 63 : CR7; +} +register (cr) CR + +register (bit[64]) CTR +register (bit[64]) LR + +typedef xer = register bits [ 0 : 63 ] { + 32 : SO; + 33 : OV; + 34 : CA; +} +register (xer) XER + +register alias CA = XER.CA + +(* Fixed-point registers *) + +register (bit[64]) GPR0 +register (bit[64]) GPR1 +register (bit[64]) GPR2 +register (bit[64]) GPR3 +register (bit[64]) GPR4 +register (bit[64]) GPR5 +register (bit[64]) GPR6 +register (bit[64]) GPR7 +register (bit[64]) GPR8 +register (bit[64]) GPR9 +register (bit[64]) GPR10 +register (bit[64]) GPR11 +register (bit[64]) GPR12 +register (bit[64]) GPR13 +register (bit[64]) GPR14 +register (bit[64]) GPR15 +register (bit[64]) GPR16 +register (bit[64]) GPR17 +register (bit[64]) GPR18 +register (bit[64]) GPR19 +register (bit[64]) GPR20 +register (bit[64]) GPR21 +register (bit[64]) GPR22 +register (bit[64]) GPR23 +register (bit[64]) GPR24 +register (bit[64]) GPR25 +register (bit[64]) GPR26 +register (bit[64]) GPR27 +register (bit[64]) GPR28 +register (bit[64]) GPR29 +register (bit[64]) GPR30 +register (bit[64]) GPR31 + +let (vector <0, 32, inc, (register<(bit[64])>) >) GPR = + [ GPR0, GPR1, GPR2, GPR3, GPR4, GPR5, GPR6, GPR7, GPR8, GPR9, GPR10, + GPR11, GPR12, GPR13, GPR14, GPR15, GPR16, GPR17, GPR18, GPR19, GPR20, + GPR21, GPR22, GPR23, GPR24, GPR25, GPR26, GPR27, GPR28, GPR29, GPR30, GPR31 + ] + +register (bit[32:63]) VRSAVE + +register (bit[64]) SPRG3 +register (bit[64]) SPRG4 +register (bit[64]) SPRG5 +register (bit[64]) SPRG6 +register (bit[64]) SPRG7 + +let (vector <0, 1024, inc, (register<(bit[64])>) >) SPR = + [ 1=XER, 8=LR, 9=CTR(*, 256=VRSAVE (*32 bit, so not 64, caught by type checker at last*)*), 259=SPRG3, 260=SPRG4, 261=SPRG5, 262=SPRG6, 263=SPRG7 + ] + +(* XXX DCR is implementation-dependent; also, some DCR are only 32 bits + instead of 64, and mtdcrux/mfdcrux do special tricks in that case, not + shown in pseudo-code. We just define two dummy DCR here, using sparse + vector definition. *) +register (vector <0, 64, inc, bit>) DCR0 +register (vector <0, 64, inc, bit>) DCR1 +let (vector <0, 1024, inc, (register<(vector<0, 64, inc, bit>)>) >) DCR = { + v = undefined; + v[0] = DCR0; + v[1] = DCR1; + v +} + +(* Floating-point registers *) + +register (bit[64]) FPR0 +register (bit[64]) FPR1 +register (bit[64]) FPR2 +register (bit[64]) FPR3 +register (bit[64]) FPR4 +register (bit[64]) FPR5 +register (bit[64]) FPR6 +register (bit[64]) FPR7 +register (bit[64]) FPR8 +register (bit[64]) FPR9 +register (bit[64]) FPR10 +register (bit[64]) FPR11 +register (bit[64]) FPR12 +register (bit[64]) FPR13 +register (bit[64]) FPR14 +register (bit[64]) FPR15 +register (bit[64]) FPR16 +register (bit[64]) FPR17 +register (bit[64]) FPR18 +register (bit[64]) FPR19 +register (bit[64]) FPR20 +register (bit[64]) FPR21 +register (bit[64]) FPR22 +register (bit[64]) FPR23 +register (bit[64]) FPR24 +register (bit[64]) FPR25 +register (bit[64]) FPR26 +register (bit[64]) FPR27 +register (bit[64]) FPR28 +register (bit[64]) FPR29 +register (bit[64]) FPR30 +register (bit[64]) FPR31 + +let (vector <0, 32, inc, (register<(bit[64])>) >) FPR = + [ FPR0, FPR1, FPR2, FPR3, FPR4, FPR5, FPR6, FPR7, FPR8, FPR9, FPR10, + FPR11, FPR12, FPR13, FPR14, FPR15, FPR16, FPR17, FPR18, FPR19, FPR20, + FPR21, FPR22, FPR23, FPR24, FPR25, FPR26, FPR27, FPR28, FPR29, FPR30, FPR31 + ] + +typedef fpscr = register bits [ 0 : 63 ] { + 32 : FX; + 33 : FEX; + 34 : VX; + 35 : OX; + 36 : UX; + 37 : ZX; + 38 : XX; + 39 : VXSNAN; + 40 : VXISI; + 41 : VXIDI; + 42 : VXZDZ; + 43 : VXIMZ; + 44 : VXVC; + 45 : FR; + 46 : FI; + 47 .. 51 : FPRF; + 47 : C; + 48 .. 51 : FPCC; + 48 : FL; 49 : FG; 50 : FE; 51 : FU; + 53 : VXSOFT; + 54 : VXSQRT; + 55 : VXCVI; + 56 : VE; + 57 : OE; + 58 : UE; + 59 : ZE; + 60 : XE; + 61 : NI; + 62 .. 63 : RN; +} +register (fpscr) FPSCR + +(* Pair-wise access to FPR registers *) + +register alias FPRp0 = FPR0 : FPR1 +register alias FPRp2 = FPR2 : FPR3 +register alias FPRp4 = FPR4 : FPR5 +register alias FPRp6 = FPR6 : FPR7 +register alias FPRp8 = FPR8 : FPR9 +register alias FPRp10 = FPR10 : FPR11 +register alias FPRp12 = FPR12 : FPR13 +register alias FPRp14 = FPR14 : FPR15 +register alias FPRp16 = FPR16 : FPR17 +register alias FPRp18 = FPR18 : FPR19 +register alias FPRp20 = FPR20 : FPR21 +register alias FPRp22 = FPR22 : FPR23 +register alias FPRp24 = FPR24 : FPR25 +register alias FPRp26 = FPR26 : FPR27 +register alias FPRp28 = FPR28 : FPR29 +register alias FPRp30 = FPR30 : FPR31 + +let (vector <0, 32, inc, (register<(bit[128])>)>) FPRp = + [ 0 = FPRp0, 2 = FPRp2, 4 = FPRp4, 6 = FPRp6, 8 = FPRp8, 10 = FPRp10, + 12 = FPRp12, 14 = FPRp14, 16 = FPRp16, 18 = FPRp18, 20 = FPRp20, 22 = + FPRp22, 24 = FPRp24, 26 = FPRp26, 28 = FPRp28, 30 = FPRp30 ] + + +val bit[32] -> bit[64] effect pure DOUBLE +val bit[64] -> bit[32] effect { undef } SINGLE + +function bit[64] DOUBLE word = { + (bit[64]) temp := 0; + if word[1..8] > 0 & word[1..8] < 255 + then { + temp[0..1] := word[0..1]; + temp[2] := ~(word[1]); + temp[3] := ~(word[1]); + temp[4] := ~(word[1]); + temp[5..63] := word[2..31] : 0b00000000000000000000000000000; + } else if word[1..8] == 0 & word[9..31] != 0 + then { + sign := word[0]; + exp := 0 - 126; + (bit[53]) frac := 0b0 : word[9..31] : 0b00000000000000000000000000000; + foreach (i from 0 to 52) { + if frac[0] == 0 + then { frac[0..52] := frac[1..52] : 0b0; + exp := exp - 1; } + else () + }; + temp[0] := sign; + temp[1..11] := (bit[1:11]) exp + 1023; + temp[12..63] := frac[1..52]; + } else { + temp[0..1] := word[0..1]; + temp[2] := word[1]; + temp[3] := word[1]; + temp[4] := word[1]; + temp[5..63] := word[2..31] : 0b00000000000000000000000000000; + }; + temp +} + +function bit[32] SINGLE ((bit[64]) frs) = { + (bit[32]) word := 0; + if (frs[1..11] > 896) | (frs[1..63] == 0) + then { word[0..1] := frs[0..1]; + word[2..31] := frs[5..34]; } + else if (874 <= frs[1..11]) & (frs[1..11] <= 896) + then { + sign := frs[0]; + (bit[11]) exp := frs[1..11] - 1023; + (bit[53]) frac := 0b1 : frs[12..63]; + foreach (i from 0 to 53) { + if exp < sub(0, 126) + then { frac[0..52] := 0b0 : frac[0..51]; + exp := exp + 1; } + else ()}; + } else word := undefined; + word +} + +(* Vector registers *) + +register (bit[128]) VR0 +register (bit[128]) VR1 +register (bit[128]) VR2 +register (bit[128]) VR3 +register (bit[128]) VR4 +register (bit[128]) VR5 +register (bit[128]) VR6 +register (bit[128]) VR7 +register (bit[128]) VR8 +register (bit[128]) VR9 +register (bit[128]) VR10 +register (bit[128]) VR11 +register (bit[128]) VR12 +register (bit[128]) VR13 +register (bit[128]) VR14 +register (bit[128]) VR15 +register (bit[128]) VR16 +register (bit[128]) VR17 +register (bit[128]) VR18 +register (bit[128]) VR19 +register (bit[128]) VR20 +register (bit[128]) VR21 +register (bit[128]) VR22 +register (bit[128]) VR23 +register (bit[128]) VR24 +register (bit[128]) VR25 +register (bit[128]) VR26 +register (bit[128]) VR27 +register (bit[128]) VR28 +register (bit[128]) VR29 +register (bit[128]) VR30 +register (bit[128]) VR31 + +let (vector <0, 32, inc, (register<(bit[128])>) >) VR = + [ VR0, VR1, VR2, VR3, VR4, VR5, VR6, VR7, VR8, VR9, VR10, + VR11, VR12, VR13, VR14, VR15, VR16, VR17, VR18, VR19, VR20, + VR21, VR22, VR23, VR24, VR25, VR26, VR27, VR28, VR29, VR30, VR31 + ] + +typedef vscr = register bits [ 96 : 127 ] { + 111 : NJ; + 127 : SAT; +} +register (vscr) VSCR + +(*(* XXX extend with zeroes -- the resulting size in completely unknown and depends of context *) +val extern forall Nat 'n, Nat 'm. (implicit<'m>,bit['n]) -> bit['m] effect pure EXTZ*) + +(* Chop has a very weird definition where the resulting size depends of + context, but in practice it is used with the following definition everywhere, + except in vaddcuw which probably needs to be patched accordingly. *) +val forall Nat 'n, Nat 'm, 'm <= 'n. (bit['n], [:'m:]) -> bit['m] effect pure Chop +function forall Nat 'n, Nat 'm. (bit['m]) Chop(x, y) = x[0..y] + +val forall Nat 'o, Nat 'n, Nat 'm, Nat 'k, 'n <= 0. + (implicit<'k>, [:'o:], [:'n:], [|'m|]) -> bit['k] effect { wreg } Clamp + +function forall Nat 'o,Nat 'n, Nat 'm, Nat 'k, 'n <= 0. (bit['k]) +Clamp(([:'o:]) x, ([:'n:]) y, ([|'m|]) z) = { + ([|'n:'m|]) result := 0; + if (x<y) then { + result := y; + VSCR.SAT := 1; + } else if (x > z) then { + result := z; + VSCR.SAT := 1; + } else { + result := x; + }; + (bit['k]) result; +} + +(* XXX *) +val extern bit[32] -> bit[32] effect pure RoundToSPIntCeil +val extern bit[32] -> bit[32] effect pure RoundToSPIntFloor +val extern bit[32] -> bit[32] effect pure RoundToSPIntNear +val extern bit[32] -> bit[32] effect pure RoundToSPIntTrunc +val extern bit[32] -> bit[32] effect pure RoundToNearSP +val extern bit[32] -> bit[32] effect pure ReciprocalEstimateSP +val extern bit[32] -> bit[32] effect pure ReciprocalSquareRootEstimateSP +val extern bit[32] -> bit[32] effect pure LogBase2EstimateSP +val extern bit[32] -> bit[32] effect pure Power2EstimateSP +val extern (bit[32], bit[5]) -> bit[32] effect pure ConvertSPtoSXWsaturate +val extern (bit[32], bit[5]) -> bit[32] effect pure ConvertSPtoUXWsaturate + + +register (bit[64]) NIA (* next instruction address *) +register (bit[64]) CIA (* current instruction address *) + + +val extern forall Nat 'n. ( bit[64] , [|'n|] , bit[8*'n]) -> unit effect { wmv } MEMw' +val extern forall Nat 'n. ( bit[64] , [|'n|] ) -> (bit[8 * 'n]) effect { rmem } MEMr' +val extern forall Nat 'n. ( bit[64] , [|'n|] ) -> (bit[8 * 'n]) effect { rmem } MEMr_reserve' +val extern forall Nat 'n. ( bit[64] , [|'n|] , bit[8*'n]) -> bool effect { wmv } MEMw_conditional' + +(* announce write address for plain write *) +val extern forall Nat 'N, 'N IN {1,2,4,8,16}. (bit[64] (*address*), [:'N:] (*size*)) -> unit effect {eamem} MEMw_EA + +(* announce write address for write conditional *) +val extern forall Nat 'N, 'N IN {1,2,4,8,16}. (bit[64] (*address*), [:'N:] (*size*)) -> unit effect {eamem} MEMw_EA_cond + +val extern unit -> unit effect { barr } I_Sync +val extern unit -> unit effect { barr } H_Sync (*corresponds to Sync in barrier kinds*) +val extern unit -> unit effect { barr } LW_Sync +val extern unit -> unit effect { barr } EIEIO_Sync + +val extern unit -> unit effect { depend } recalculate_dependency + +val forall Nat 'n, Nat 'm, 'n *8 = 'm. (implicit<'m>,(bit['m])) -> (bit['m]) effect pure byte_reverse +function forall Nat 'n, Nat 'm, 'n*8 = 'm. (bit['m]) effect pure byte_reverse((bit['m]) input) = { + (bit['m]) output := 0; + j := length(input); + foreach (i from 0 to (length(input)) by 8) { + output[i..i+7] := input[j - 7 ..j]; + j := j - 8; }; + output +} + +(* XXX effect for trap? *) +val extern unit -> unit effect {escape} trap + +register (bit[1]) mode64bit +register (bit[1]) bigendianmode + +val forall Nat 'W, 'W IN {8,16,32,64,128}. bit['W] -> bit['W] effect pure reverse_endianness +function rec forall Nat 'W, 'W IN {8, 16, 32, 64, 128}. bit['W] reverse_endianness ((bit['W]) value) = +{ + (nat) width := length(value); + (nat) half := width quot 2; + if width == 8 then value + else reverse_endianness(value[half .. (width - 1)]) : reverse_endianness(value[0 .. (half - 1)]); +} + +function forall Nat 'n. unit effect { wmv } MEMw ((bit[64]) ea, ([|'n|]) size, (bit[8*'n]) value) = +{ + if bigendianmode then + MEMw'(ea, size, reverse_endianness(value)) + else + MEMw'(ea, size, value) +} + +function forall Nat 'n. (bit[8 * 'n]) effect { rmem } MEMr ((bit[64]) ea, ([|'n|]) size) = +{ + if bigendianmode then + reverse_endianness(MEMr'(ea, size)) + else + MEMr'(ea, size) +} + +function forall Nat 'n. (bit[8 * 'n]) effect { rmem } MEMr_reserve ((bit[64]) ea, ([|'n|]) size) = +{ + if bigendianmode then + reverse_endianness(MEMr_reserve'(ea, size)) + else + MEMr_reserve'(ea, size) +} + +function forall Nat 'n. bool effect { wmv } MEMw_conditional ((bit[64]) ea, ([|'n|]) size, (bit[8*'n]) value) = +{ + if bigendianmode then + MEMw_conditional'(ea, size, reverse_endianness(value)) + else + MEMw_conditional'(ea, size, value) +} + + + +val (bit[64],bit) -> unit effect {rreg,wreg} set_overflow_cr0 +function (unit) set_overflow_cr0(target_register,new_xer_so) = { + m:= 0; + (bit[3]) c:= 0; + (bit[64]) zero := 0; + (if mode64bit + then m := 0 + else m := 32); + (if target_register[m..63] <_s zero[m..63] + then c := 0b100 + else if target_register[m..63] >_s zero[m..63] + then c := 0b010 + else c := 0b001); + CR.CR0 := c:[new_xer_so] +} + +function (unit) set_SO_OV(overflow) = { + XER.OV := overflow; + XER.SO := (XER.SO | overflow); +} + +function forall Nat 'n. (bit['n]) zero_or_undef ((bit['n]) x) = { + (bit['n]) out := 0; + foreach (i from 0 to ((length(x)) - 1)) { + out[i] := if x[i] then undefined else 0 + }; + out +} + +scattered function unit execute +scattered typedef ast = const union + +val bit[32] -> option<ast> effect pure decode + +scattered function option<ast> decode + +union ast member (bit[24], bit, bit) B + +function clause decode (0b010010 : (bit[24]) LI : [AA] : [LK] as instr) = Some(B(LI,AA,LK)) + +function clause execute (B (LI, AA, LK)) = + { + if AA then NIA := EXTS(LI : 0b00) else NIA := CIA + EXTS(LI : 0b00); + if LK then LR := CIA + 4 else () + } + +union ast member (bit[5], bit[5], bit[14], bit, bit) Bc + +function clause decode (0b010000 : +(bit[5]) BO : +(bit[5]) BI : +(bit[14]) BD : +[AA] : +[LK] as instr) = + Some(Bc(BO,BI,BD,AA,LK)) + +function clause execute (Bc (BO, BI, BD, AA, LK)) = + { + if mode64bit then M := 0 else M := 32; + (bit[64]) ctr_temp := CTR; + if ~(BO[2]) + then { + ctr_temp := ctr_temp - 1; + CTR := ctr_temp + } + else (); + ctr_ok := (BO[2] | ~(ctr_temp[M .. 63] == 0) ^ BO[3]); + cond_ok := (BO[0] | CR[BI + 32] ^ ~(BO[1])); + if ctr_ok & cond_ok + then if AA then NIA := EXTS(BD : 0b00) else NIA := CIA + EXTS(BD : 0b00) + else (); + if LK then LR := CIA + 4 else () + } + +union ast member (bit[5], bit[5], bit[2], bit) Bclr + +function clause decode (0b010011 : +(bit[5]) BO : +(bit[5]) BI : +(bit[3]) _ : +(bit[2]) BH : +0b0000010000 : +[LK] as instr) = + Some(Bclr(BO,BI,BH,LK)) + +function clause execute (Bclr (BO, BI, BH, LK)) = + { + if mode64bit then M := 0 else M := 32; + (bit[64]) ctr_temp := CTR; + if ~(BO[2]) + then { + ctr_temp := ctr_temp - 1; + CTR := ctr_temp + } + else (); + ctr_ok := (BO[2] | ~(ctr_temp[M .. 63] == 0) ^ BO[3]); + cond_ok := (BO[0] | CR[BI + 32] ^ ~(BO[1])); + if ctr_ok & cond_ok then NIA := LR[0 .. 61] : 0b00 else (); + if LK then LR := CIA + 4 else () + } + +union ast member (bit[5], bit[5], bit[2], bit) Bcctr + +function clause decode (0b010011 : +(bit[5]) BO : +(bit[5]) BI : +(bit[3]) _ : +(bit[2]) BH : +0b1000010000 : +[LK] as instr) = + Some(Bcctr(BO,BI,BH,LK)) + +function clause execute (Bcctr (BO, BI, BH, LK)) = + { + cond_ok := (BO[0] | CR[BI + 32] ^ ~(BO[1])); + if cond_ok then NIA := CTR[0 .. 61] : 0b00 else (); + if LK then LR := CIA + 4 else () + } + +union ast member (bit[5], bit[5], bit[5]) Crand + +function clause decode (0b010011 : +(bit[5]) BT : +(bit[5]) BA : +(bit[5]) BB : +0b0100000001 : +(bit[1]) _ as instr) = + Some(Crand(BT,BA,BB)) + +function clause execute (Crand (BT, BA, BB)) = CR[BT + 32] := (CR[BA + 32] & CR[BB + 32]) + +union ast member (bit[5], bit[5], bit[5]) Crnand + +function clause decode (0b010011 : +(bit[5]) BT : +(bit[5]) BA : +(bit[5]) BB : +0b0011100001 : +(bit[1]) _ as instr) = + Some(Crnand(BT,BA,BB)) + +function clause execute (Crnand (BT, BA, BB)) = CR[BT + 32] := ~(CR[BA + 32] & CR[BB + 32]) + +union ast member (bit[5], bit[5], bit[5]) Cror + +function clause decode (0b010011 : +(bit[5]) BT : +(bit[5]) BA : +(bit[5]) BB : +0b0111000001 : +(bit[1]) _ as instr) = + Some(Cror(BT,BA,BB)) + +function clause execute (Cror (BT, BA, BB)) = CR[BT + 32] := (CR[BA + 32] | CR[BB + 32]) + +union ast member (bit[5], bit[5], bit[5]) Crxor + +function clause decode (0b010011 : +(bit[5]) BT : +(bit[5]) BA : +(bit[5]) BB : +0b0011000001 : +(bit[1]) _ as instr) = + Some(Crxor(BT,BA,BB)) + +function clause execute (Crxor (BT, BA, BB)) = CR[BT + 32] := CR[BA + 32] ^ CR[BB + 32] + +union ast member (bit[5], bit[5], bit[5]) Crnor + +function clause decode (0b010011 : +(bit[5]) BT : +(bit[5]) BA : +(bit[5]) BB : +0b0000100001 : +(bit[1]) _ as instr) = + Some(Crnor(BT,BA,BB)) + +function clause execute (Crnor (BT, BA, BB)) = CR[BT + 32] := ~(CR[BA + 32] | CR[BB + 32]) + +union ast member (bit[5], bit[5], bit[5]) Creqv + +function clause decode (0b010011 : +(bit[5]) BT : +(bit[5]) BA : +(bit[5]) BB : +0b0100100001 : +(bit[1]) _ as instr) = + Some(Creqv(BT,BA,BB)) + +function clause execute (Creqv (BT, BA, BB)) = CR[BT + 32] := CR[BA + 32] ^ ~(CR[BB + 32]) + +union ast member (bit[5], bit[5], bit[5]) Crandc + +function clause decode (0b010011 : +(bit[5]) BT : +(bit[5]) BA : +(bit[5]) BB : +0b0010000001 : +(bit[1]) _ as instr) = + Some(Crandc(BT,BA,BB)) + +function clause execute (Crandc (BT, BA, BB)) = CR[BT + 32] := (CR[BA + 32] & ~(CR[BB + 32])) + +union ast member (bit[5], bit[5], bit[5]) Crorc + +function clause decode (0b010011 : +(bit[5]) BT : +(bit[5]) BA : +(bit[5]) BB : +0b0110100001 : +(bit[1]) _ as instr) = + Some(Crorc(BT,BA,BB)) + +function clause execute (Crorc (BT, BA, BB)) = CR[BT + 32] := (CR[BA + 32] | ~(CR[BB + 32])) + +union ast member (bit[3], bit[3]) Mcrf + +function clause decode (0b010011 : +(bit[3]) BF : +(bit[2]) _ : +(bit[3]) BFA : +(bit[2]) _ : +(bit[5]) _ : +0b0000000000 : +(bit[1]) _ as instr) = + Some(Mcrf(BF,BFA)) + +function clause execute (Mcrf (BF, BFA)) = + CR[4 * BF + 32..4 * BF + 35] := CR[4 * BFA + 32 .. 4 * BFA + 35] + +union ast member (bit[7]) Sc + +function clause decode (0b010001 : +(bit[5]) _ : +(bit[5]) _ : +(bit[4]) _ : +(bit[7]) LEV : +(bit[3]) _ : +0b1 : +(bit[1]) _ as instr) = + Some(Sc(LEV)) + +function clause execute (Sc (LEV)) = () + +union ast member (bit[7]) Scv + +function clause decode (0b010001 : +(bit[5]) _ : +(bit[5]) _ : +(bit[4]) _ : +(bit[7]) LEV : +(bit[3]) _ : +0b0 : +0b1 as instr) = + Some(Scv(LEV)) + +function clause execute (Scv (LEV)) = () + +union ast member (bit[5], bit[5], bit[16]) Lbz + +function clause decode (0b100010 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Lbz(RT,RA,D)) + +function clause execute (Lbz (RT, RA, D)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(D); + GPR[RT] := 0b00000000000000000000000000000000000000000000000000000000 : MEMr(EA,1) + } + +union ast member (bit[5], bit[5], bit[5]) Lbzx + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0001010111 : +(bit[1]) _ as instr) = + Some(Lbzx(RT,RA,RB)) + +function clause execute (Lbzx (RT, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + GPR[RT] := 0b00000000000000000000000000000000000000000000000000000000 : MEMr(EA,1) + } + +union ast member (bit[5], bit[5], bit[16]) Lbzu + +function clause decode (0b100011 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Lbzu(RT,RA,D)) + +function clause execute (Lbzu (RT, RA, D)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + EXTS(D); + GPR[RA] := EA; + GPR[RT] := 0b00000000000000000000000000000000000000000000000000000000 : MEMr(EA,1) + } + +union ast member (bit[5], bit[5], bit[5]) Lbzux + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0001110111 : +(bit[1]) _ as instr) = + Some(Lbzux(RT,RA,RB)) + +function clause execute (Lbzux (RT, RA, RB)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + GPR[RB]; + GPR[RA] := EA; + GPR[RT] := 0b00000000000000000000000000000000000000000000000000000000 : MEMr(EA,1) + } + +union ast member (bit[5], bit[5], bit[16]) Lhz + +function clause decode (0b101000 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Lhz(RT,RA,D)) + +function clause execute (Lhz (RT, RA, D)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(D); + GPR[RT] := 0b000000000000000000000000000000000000000000000000 : MEMr(EA,2) + } + +union ast member (bit[5], bit[5], bit[5]) Lhzx + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0100010111 : +(bit[1]) _ as instr) = + Some(Lhzx(RT,RA,RB)) + +function clause execute (Lhzx (RT, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + GPR[RT] := 0b000000000000000000000000000000000000000000000000 : MEMr(EA,2) + } + +union ast member (bit[5], bit[5], bit[16]) Lhzu + +function clause decode (0b101001 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Lhzu(RT,RA,D)) + +function clause execute (Lhzu (RT, RA, D)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + EXTS(D); + GPR[RA] := EA; + GPR[RT] := 0b000000000000000000000000000000000000000000000000 : MEMr(EA,2) + } + +union ast member (bit[5], bit[5], bit[5]) Lhzux + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0100110111 : +(bit[1]) _ as instr) = + Some(Lhzux(RT,RA,RB)) + +function clause execute (Lhzux (RT, RA, RB)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + GPR[RB]; + GPR[RA] := EA; + GPR[RT] := 0b000000000000000000000000000000000000000000000000 : MEMr(EA,2) + } + +union ast member (bit[5], bit[5], bit[16]) Lha + +function clause decode (0b101010 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Lha(RT,RA,D)) + +function clause execute (Lha (RT, RA, D)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(D); + GPR[RT] := EXTS(MEMr(EA,2)) + } + +union ast member (bit[5], bit[5], bit[5]) Lhax + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0101010111 : +(bit[1]) _ as instr) = + Some(Lhax(RT,RA,RB)) + +function clause execute (Lhax (RT, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + GPR[RT] := EXTS(MEMr(EA,2)) + } + +union ast member (bit[5], bit[5], bit[16]) Lhau + +function clause decode (0b101011 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Lhau(RT,RA,D)) + +function clause execute (Lhau (RT, RA, D)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + EXTS(D); + GPR[RA] := EA; + GPR[RT] := EXTS(MEMr(EA,2)) + } + +union ast member (bit[5], bit[5], bit[5]) Lhaux + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0101110111 : +(bit[1]) _ as instr) = + Some(Lhaux(RT,RA,RB)) + +function clause execute (Lhaux (RT, RA, RB)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + GPR[RB]; + GPR[RA] := EA; + GPR[RT] := EXTS(MEMr(EA,2)) + } + +union ast member (bit[5], bit[5], bit[16]) Lwz + +function clause decode (0b100000 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Lwz(RT,RA,D)) + +function clause execute (Lwz (RT, RA, D)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(D); + GPR[RT] := 0b00000000000000000000000000000000 : MEMr(EA,4) + } + +union ast member (bit[5], bit[5], bit[5]) Lwzx + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0000010111 : +(bit[1]) _ as instr) = + Some(Lwzx(RT,RA,RB)) + +function clause execute (Lwzx (RT, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + GPR[RT] := 0b00000000000000000000000000000000 : MEMr(EA,4) + } + +union ast member (bit[5], bit[5], bit[16]) Lwzu + +function clause decode (0b100001 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Lwzu(RT,RA,D)) + +function clause execute (Lwzu (RT, RA, D)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + EXTS(D); + GPR[RA] := EA; + GPR[RT] := 0b00000000000000000000000000000000 : MEMr(EA,4) + } + +union ast member (bit[5], bit[5], bit[5]) Lwzux + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0000110111 : +(bit[1]) _ as instr) = + Some(Lwzux(RT,RA,RB)) + +function clause execute (Lwzux (RT, RA, RB)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + GPR[RB]; + GPR[RA] := EA; + GPR[RT] := 0b00000000000000000000000000000000 : MEMr(EA,4) + } + +union ast member (bit[5], bit[5], bit[14]) Lwa + +function clause decode (0b111010 : +(bit[5]) RT : +(bit[5]) RA : +(bit[14]) DS : +0b10 as instr) = + Some(Lwa(RT,RA,DS)) + +function clause execute (Lwa (RT, RA, DS)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(DS : 0b00); + GPR[RT] := EXTS(MEMr(EA,4)) + } + +union ast member (bit[5], bit[5], bit[5]) Lwax + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0101010101 : +(bit[1]) _ as instr) = + Some(Lwax(RT,RA,RB)) + +function clause execute (Lwax (RT, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + GPR[RT] := EXTS(MEMr(EA,4)) + } + +union ast member (bit[5], bit[5], bit[5]) Lwaux + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0101110101 : +(bit[1]) _ as instr) = + Some(Lwaux(RT,RA,RB)) + +function clause execute (Lwaux (RT, RA, RB)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + GPR[RB]; + GPR[RA] := EA; + GPR[RT] := EXTS(MEMr(EA,4)) + } + +union ast member (bit[5], bit[5], bit[14]) Ld + +function clause decode (0b111010 : +(bit[5]) RT : +(bit[5]) RA : +(bit[14]) DS : +0b00 as instr) = + Some(Ld(RT,RA,DS)) + +function clause execute (Ld (RT, RA, DS)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(DS : 0b00); + GPR[RT] := MEMr(EA,8) + } + +union ast member (bit[5], bit[5], bit[5]) Ldx + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0000010101 : +(bit[1]) _ as instr) = + Some(Ldx(RT,RA,RB)) + +function clause execute (Ldx (RT, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + GPR[RT] := MEMr(EA,8) + } + +union ast member (bit[5], bit[5], bit[14]) Ldu + +function clause decode (0b111010 : +(bit[5]) RT : +(bit[5]) RA : +(bit[14]) DS : +0b01 as instr) = + Some(Ldu(RT,RA,DS)) + +function clause execute (Ldu (RT, RA, DS)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + EXTS(DS : 0b00); + GPR[RA] := EA; + GPR[RT] := MEMr(EA,8) + } + +union ast member (bit[5], bit[5], bit[5]) Ldux + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0000110101 : +(bit[1]) _ as instr) = + Some(Ldux(RT,RA,RB)) + +function clause execute (Ldux (RT, RA, RB)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + GPR[RB]; + GPR[RA] := EA; + GPR[RT] := MEMr(EA,8) + } + +union ast member (bit[5], bit[5], bit[16]) Stb + +function clause decode (0b100110 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Stb(RS,RA,D)) + +function clause execute (Stb (RS, RA, D)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(D); + MEMw_EA(EA,1); + MEMw(EA,1) := (GPR[RS])[56 .. 63] + } + +union ast member (bit[5], bit[5], bit[5]) Stbx + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0011010111 : +(bit[1]) _ as instr) = + Some(Stbx(RS,RA,RB)) + +function clause execute (Stbx (RS, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + MEMw_EA(EA,1); + MEMw(EA,1) := (GPR[RS])[56 .. 63] + } + +union ast member (bit[5], bit[5], bit[16]) Stbu + +function clause decode (0b100111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Stbu(RS,RA,D)) + +function clause execute (Stbu (RS, RA, D)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + EXTS(D); + MEMw_EA(EA,1); + GPR[RA] := EA; + MEMw(EA,1) := (GPR[RS])[56 .. 63] + } + +union ast member (bit[5], bit[5], bit[5]) Stbux + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0011110111 : +(bit[1]) _ as instr) = + Some(Stbux(RS,RA,RB)) + +function clause execute (Stbux (RS, RA, RB)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + GPR[RB]; + MEMw_EA(EA,1); + GPR[RA] := EA; + MEMw(EA,1) := (GPR[RS])[56 .. 63] + } + +union ast member (bit[5], bit[5], bit[16]) Sth + +function clause decode (0b101100 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Sth(RS,RA,D)) + +function clause execute (Sth (RS, RA, D)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(D); + MEMw_EA(EA,2); + MEMw(EA,2) := (GPR[RS])[48 .. 63] + } + +union ast member (bit[5], bit[5], bit[5]) Sthx + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0110010111 : +(bit[1]) _ as instr) = + Some(Sthx(RS,RA,RB)) + +function clause execute (Sthx (RS, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + MEMw_EA(EA,2); + MEMw(EA,2) := (GPR[RS])[48 .. 63] + } + +union ast member (bit[5], bit[5], bit[16]) Sthu + +function clause decode (0b101101 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Sthu(RS,RA,D)) + +function clause execute (Sthu (RS, RA, D)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + EXTS(D); + MEMw_EA(EA,2); + GPR[RA] := EA; + MEMw(EA,2) := (GPR[RS])[48 .. 63] + } + +union ast member (bit[5], bit[5], bit[5]) Sthux + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0110110111 : +(bit[1]) _ as instr) = + Some(Sthux(RS,RA,RB)) + +function clause execute (Sthux (RS, RA, RB)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + GPR[RB]; + MEMw_EA(EA,2); + GPR[RA] := EA; + MEMw(EA,2) := (GPR[RS])[48 .. 63] + } + +union ast member (bit[5], bit[5], bit[16]) Stw + +function clause decode (0b100100 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Stw(RS,RA,D)) + +function clause execute (Stw (RS, RA, D)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(D); + MEMw_EA(EA,4); + MEMw(EA,4) := (GPR[RS])[32 .. 63] + } + +union ast member (bit[5], bit[5], bit[5]) Stwx + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0010010111 : +(bit[1]) _ as instr) = + Some(Stwx(RS,RA,RB)) + +function clause execute (Stwx (RS, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + MEMw_EA(EA,4); + MEMw(EA,4) := (GPR[RS])[32 .. 63] + } + +union ast member (bit[5], bit[5], bit[16]) Stwu + +function clause decode (0b100101 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Stwu(RS,RA,D)) + +function clause execute (Stwu (RS, RA, D)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + EXTS(D); + MEMw_EA(EA,4); + GPR[RA] := EA; + MEMw(EA,4) := (GPR[RS])[32 .. 63] + } + +union ast member (bit[5], bit[5], bit[5]) Stwux + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0010110111 : +(bit[1]) _ as instr) = + Some(Stwux(RS,RA,RB)) + +function clause execute (Stwux (RS, RA, RB)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + GPR[RB]; + MEMw_EA(EA,4); + GPR[RA] := EA; + MEMw(EA,4) := (GPR[RS])[32 .. 63] + } + +union ast member (bit[5], bit[5], bit[14]) Std + +function clause decode (0b111110 : +(bit[5]) RS : +(bit[5]) RA : +(bit[14]) DS : +0b00 as instr) = + Some(Std(RS,RA,DS)) + +function clause execute (Std (RS, RA, DS)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(DS : 0b00); + MEMw_EA(EA,8); + MEMw(EA,8) := GPR[RS] + } + +union ast member (bit[5], bit[5], bit[5]) Stdx + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0010010101 : +(bit[1]) _ as instr) = + Some(Stdx(RS,RA,RB)) + +function clause execute (Stdx (RS, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + MEMw_EA(EA,8); + MEMw(EA,8) := GPR[RS] + } + +union ast member (bit[5], bit[5], bit[14]) Stdu + +function clause decode (0b111110 : +(bit[5]) RS : +(bit[5]) RA : +(bit[14]) DS : +0b01 as instr) = + Some(Stdu(RS,RA,DS)) + +function clause execute (Stdu (RS, RA, DS)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + EXTS(DS : 0b00); + MEMw_EA(EA,8); + GPR[RA] := EA; + MEMw(EA,8) := GPR[RS] + } + +union ast member (bit[5], bit[5], bit[5]) Stdux + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0010110101 : +(bit[1]) _ as instr) = + Some(Stdux(RS,RA,RB)) + +function clause execute (Stdux (RS, RA, RB)) = + { + (bit[64]) EA := 0; + EA := GPR[RA] + GPR[RB]; + MEMw_EA(EA,8); + GPR[RA] := EA; + MEMw(EA,8) := GPR[RS] + } + +union ast member (bit[5], bit[5], bit[12], bit[4]) Lq + +function clause decode (0b111000 : +(bit[5]) RTp : +(bit[5]) RA : +(bit[12]) DQ : +(bit[4]) PT as instr) = + Some(Lq(RTp,RA,DQ,PT)) + +function clause execute (Lq (RTp, RA, DQ, PT)) = + { + (bit[64]) EA := 0; + (bit[64]) b := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(DQ : 0b0000); + (bit[128]) mem := MEMr(EA,16); + if bigendianmode + then { + GPR[RTp] := mem[0 .. 63]; + GPR[RTp + 1] := mem[64 .. 127] + } + else { + (bit[128]) bytereverse := byte_reverse(mem); + GPR[RTp] := bytereverse[0 .. 63]; + GPR[RTp + 1] := bytereverse[64 .. 127] + } + } + +union ast member (bit[5], bit[5], bit[14]) Stq + +function clause decode (0b111110 : +(bit[5]) RSp : +(bit[5]) RA : +(bit[14]) DS : +0b10 as instr) = + Some(Stq(RSp,RA,DS)) + +function clause execute (Stq (RSp, RA, DS)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(DS : 0b00); + MEMw_EA(EA,16); + (bit[128]) mem := 0; + mem[0..63] := GPR[RSp]; + mem[64..127] := GPR[RSp + 1]; + if ~(bigendianmode) then mem := byte_reverse(mem) else (); + MEMw(EA,16) := mem + } + +union ast member (bit[5], bit[5], bit[5]) Lhbrx + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b1100010110 : +(bit[1]) _ as instr) = + Some(Lhbrx(RT,RA,RB)) + +function clause execute (Lhbrx (RT, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + load_data := MEMr(EA,2); + GPR[RT] := + 0b000000000000000000000000000000000000000000000000 : load_data[8 .. 15] : load_data[0 .. 7] + } + +union ast member (bit[5], bit[5], bit[5]) Sthbrx + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b1110010110 : +(bit[1]) _ as instr) = + Some(Sthbrx(RS,RA,RB)) + +function clause execute (Sthbrx (RS, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + MEMw_EA(EA,2); + MEMw(EA,2) := (GPR[RS])[56 .. 63] : (GPR[RS])[48 .. 55] + } + +union ast member (bit[5], bit[5], bit[5]) Lwbrx + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b1000010110 : +(bit[1]) _ as instr) = + Some(Lwbrx(RT,RA,RB)) + +function clause execute (Lwbrx (RT, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + load_data := MEMr(EA,4); + GPR[RT] := + 0b00000000000000000000000000000000 : + load_data[24 .. 31] : load_data[16 .. 23] : load_data[8 .. 15] : load_data[0 .. 7] + } + +union ast member (bit[5], bit[5], bit[5]) Stwbrx + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b1010010110 : +(bit[1]) _ as instr) = + Some(Stwbrx(RS,RA,RB)) + +function clause execute (Stwbrx (RS, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + MEMw_EA(EA,4); + MEMw(EA,4) := + (GPR[RS])[56 .. 63] : (GPR[RS])[48 .. 55] : (GPR[RS])[40 .. 47] : (GPR[RS])[32 .. 39] + } + +union ast member (bit[5], bit[5], bit[5]) Ldbrx + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b1000010100 : +(bit[1]) _ as instr) = + Some(Ldbrx(RT,RA,RB)) + +function clause execute (Ldbrx (RT, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + load_data := MEMr(EA,8); + GPR[RT] := + load_data[56 .. 63] : + load_data[48 .. 55] : + load_data[40 .. 47] : + load_data[32 .. 39] : + load_data[24 .. 31] : load_data[16 .. 23] : load_data[8 .. 15] : load_data[0 .. 7] + } + +union ast member (bit[5], bit[5], bit[5]) Stdbrx + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b1010010100 : +(bit[1]) _ as instr) = + Some(Stdbrx(RS,RA,RB)) + +function clause execute (Stdbrx (RS, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + MEMw_EA(EA,8); + MEMw(EA,8) := + (GPR[RS])[56 .. 63] : + (GPR[RS])[48 .. 55] : + (GPR[RS])[40 .. 47] : + (GPR[RS])[32 .. 39] : + (GPR[RS])[24 .. 31] : (GPR[RS])[16 .. 23] : (GPR[RS])[8 .. 15] : (GPR[RS])[0 .. 7] + } + +union ast member (bit[5], bit[5], bit[16]) Lmw + +function clause decode (0b101110 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Lmw(RT,RA,D)) + +function clause execute (Lmw (RT, RA, D)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(D); + size := ([|32|])(sub(32, RT)) * 4; + buffer := MEMr(EA,size); + i := 0; + foreach (r from RT to 31 by 1 in inc) + { + GPR[r] := 0b00000000000000000000000000000000 : buffer[i .. i + 31]; + i := i + 32 + } + } + +union ast member (bit[5], bit[5], bit[16]) Stmw + +function clause decode (0b101111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) D as instr) = + Some(Stmw(RS,RA,D)) + +function clause execute (Stmw (RS, RA, D)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + EXTS(D); + size := ([|32|]) (sub(32, RS)) * 4; + MEMw_EA(EA,size); + (bit[994]) buffer := zeros(994); + i := 0; + foreach (r from RS to 31 by 1 in inc) + { + buffer[i..i + 31] := (GPR[r])[32 .. 63]; + i := i + 32 + }; + MEMw(EA,size) := buffer[0 .. size * 8 - 1] + } + +union ast member (bit[5], bit[5], bit[5]) Lswi + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) NB : +0b1001010101 : +(bit[1]) _ as instr) = + Some(Lswi(RT,RA,NB)) + +function clause execute (Lswi (RT, RA, NB)) = + { + (bit[64]) EA := 0; + if RA == 0 then EA := 0 else EA := GPR[RA]; + ([|31|]) r := 0; + r := RT - 1; + ([|32|]) size := if NB == 0 then 32 else NB; + (bit[256]) membuffer := MEMr(EA,size); + j := 0; + i := 32; + foreach (n from (if NB == 0 then 32 else NB) to 1 by 1 in dec) + { + if i == 32 + then { + r := ([|31|]) (r + 1) mod 32; + GPR[r] := 0 + } + else (); + (GPR[r])[i..i + 7] := membuffer[j .. j + 7]; + j := j + 8; + i := i + 8; + if i == 64 then i := 32 else (); + EA := EA + 1 + } + } + +union ast member (bit[5], bit[5], bit[5]) Lswx + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b1000010101 : +(bit[1]) _ as instr) = + Some(Lswx(RT,RA,RB)) + +function clause execute (Lswx (RT, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + ([|31|]) r := 0; + EA := b + GPR[RB]; + r := RT - 1; + i := 32; + ([|128|]) n_top := XER[57 .. 63]; + recalculate_dependency(()); + if n_top == 0 + then GPR[RT] := undefined + else { + (bit[512]) membuffer := MEMr(EA,n_top); + j := 0; + n_r := n_top quot 4; + n_mod := n_top mod 4; + n_r := if n_mod == 0 then n_r else n_r + 1; + foreach (n from n_r to 1 by 1 in dec) + { + r := ([|32|]) (r + 1) mod 32; + (bit[64]) temp := 0; + if n == 1 + then switch n_mod { + case 0 -> temp[32..63] := membuffer[j .. j + 31] + case 1 -> temp[32..39] := membuffer[j .. j + 7] + case 2 -> temp[32..47] := membuffer[j .. j + 15] + case 3 -> temp[32..55] := membuffer[j .. j + 23] + } + else temp[32..63] := membuffer[j .. j + 31]; + j := j + 32; + GPR[r] := temp + } + } + } + +union ast member (bit[5], bit[5], bit[5]) Stswi + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) NB : +0b1011010101 : +(bit[1]) _ as instr) = + Some(Stswi(RS,RA,NB)) + +function clause execute (Stswi (RS, RA, NB)) = + { + (bit[64]) EA := 0; + if RA == 0 then EA := 0 else EA := GPR[RA]; + ([|31|]) r := 0; + r := RS - 1; + ([|32|]) size := if NB == 0 then 32 else NB; + MEMw_EA(EA,size); + (bit[256]) membuffer := zeros(255); + j := 0; + i := 32; + foreach (n from (if NB == 0 then 32 else NB) to 1 by 1 in dec) + { + if i == 32 then r := ([|32|]) (r + 1) mod 32 else (); + membuffer[j..j + 7] := (GPR[r])[i .. i + 7]; + j := j + 8; + i := i + 8; + if i == 64 then i := 32 else () + }; + MEMw(EA,size) := membuffer[0 .. size * 8 - 1] + } + +union ast member (bit[5], bit[5], bit[5]) Stswx + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b1010010101 : +(bit[1]) _ as instr) = + Some(Stswx(RS,RA,RB)) + +function clause execute (Stswx (RS, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + ([|31|]) r := 0; + EA := b + GPR[RB]; + r := RS - 1; + i := 32; + ([|128|]) n_top := XER[57 .. 63]; + recalculate_dependency(()); + MEMw_EA(EA,n_top); + (bit[512]) membuffer := zeros(512); + j := 0; + foreach (n from n_top to 1 by 1 in dec) + { + if i == 32 then r := ([|32|]) (r + 1) mod 32 else (); + membuffer[j..j + 7] := (GPR[r])[i .. i + 7]; + i := i + 8; + j := j + 8; + if i == 64 then i := 32 else () + }; + if ~(n_top == 0) then MEMw(EA,n_top) := membuffer[0 .. n_top * 8 - 1] else () + } + +union ast member (bit[5], bit[5], bit[16]) Addi + +function clause decode (0b001110 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) SI as instr) = + Some(Addi(RT,RA,SI)) + +function clause execute (Addi (RT, RA, SI)) = + if RA == 0 then GPR[RT] := EXTS(SI) else GPR[RT] := GPR[RA] + EXTS(SI) + +union ast member (bit[5], bit[5], bit[16]) Addis + +function clause decode (0b001111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) SI as instr) = + Some(Addis(RT,RA,SI)) + +function clause execute (Addis (RT, RA, SI)) = + if RA == 0 + then GPR[RT] := EXTS(SI : 0b0000000000000000) + else GPR[RT] := GPR[RA] + EXTS(SI : 0b0000000000000000) + +union ast member (bit[5], bit[5], bit[5], bit, bit) Add + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b100001010 : +[Rc] as instr) = + Some(Add(RT,RA,RB,OE,Rc)) + +function clause execute (Add (RT, RA, RB, OE, Rc)) = + let (temp, overflow, _) = (GPR[RA] +_s GPR[RB]) in + { + GPR[RT] := temp; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + set_overflow_cr0(temp,xer_so) + } + else (); + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Subf + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b000101000 : +[Rc] as instr) = + Some(Subf(RT,RA,RB,OE,Rc)) + +function clause execute (Subf (RT, RA, RB, OE, Rc)) = + let (t1, o1, _) = (~(GPR[RA]) +_s GPR[RB]) in + let (t2, o2, _) = (t1 +_s (bit) 1) in + { + (bit[64]) temp := t2; + overflow := (o1 | o2); + GPR[RT] := temp; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + set_overflow_cr0(temp,xer_so) + } + else (); + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit[16]) Addic + +function clause decode (0b001100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) SI as instr) = + Some(Addic(RT,RA,SI)) + +function clause execute (Addic (RT, RA, SI)) = + let (temp, _, carry) = (GPR[RA] +_s EXTS(SI)) in + { + GPR[RT] := temp; + CA := carry + } + +union ast member (bit[5], bit[5], bit[16]) AddicDot + +function clause decode (0b001101 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) SI as instr) = + Some(AddicDot(RT,RA,SI)) + +function clause execute (AddicDot (RT, RA, SI)) = + let (temp, overflow, carry) = (GPR[RA] +_s EXTS(SI)) in + { + GPR[RT] := temp; + CA := carry; + set_overflow_cr0(temp,overflow | XER.SO) + } + +union ast member (bit[5], bit[5], bit[16]) Subfic + +function clause decode (0b001000 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) SI as instr) = + Some(Subfic(RT,RA,SI)) + +function clause execute (Subfic (RT, RA, SI)) = + let (t1, o1, c1) = (~(GPR[RA]) +_s EXTS(SI)) in + let (t2, o2, c2) = (t1 +_s (bit) 1) in + { + (bit[64]) temp := t2; + GPR[RT] := temp; + CA := (c1 | c2) + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Addc + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b000001010 : +[Rc] as instr) = + Some(Addc(RT,RA,RB,OE,Rc)) + +function clause execute (Addc (RT, RA, RB, OE, Rc)) = + let (temp, overflow, carry) = (GPR[RA] +_s GPR[RB]) in + { + GPR[RT] := temp; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + set_overflow_cr0(temp,xer_so) + } + else (); + CA := carry; + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Subfc + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b000001000 : +[Rc] as instr) = + Some(Subfc(RT,RA,RB,OE,Rc)) + +function clause execute (Subfc (RT, RA, RB, OE, Rc)) = + let (t1, o1, c1) = (~(GPR[RA]) +_s GPR[RB]) in + let (t2, o2, c2) = (t1 +_s (bit) 1) in + { + (bit[64]) temp := t2; + overflow := (o1 | o2); + carry := (c1 | c2); + GPR[RT] := temp; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + set_overflow_cr0(temp,xer_so) + } + else (); + CA := carry; + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Adde + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b010001010 : +[Rc] as instr) = + Some(Adde(RT,RA,RB,OE,Rc)) + +function clause execute (Adde (RT, RA, RB, OE, Rc)) = + let (t1, o1, c1) = (GPR[RA] +_s GPR[RB]) in + let (t2, o2, c2) = (t1 +_s (bit) CA) in + { + (bit[64]) temp := t2; + overflow := (o1 | o2); + carry := (c1 | c2); + GPR[RT] := temp; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + set_overflow_cr0(temp,xer_so) + } + else (); + CA := carry; + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Subfe + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b010001000 : +[Rc] as instr) = + Some(Subfe(RT,RA,RB,OE,Rc)) + +function clause execute (Subfe (RT, RA, RB, OE, Rc)) = + let (t1, o1, c1) = (~(GPR[RA]) +_s GPR[RB]) in + let (t2, o2, c2) = (t1 +_s (bit) CA) in + { + (bit[64]) temp := t2; + overflow := (o1 | o2); + carry := (c1 | c2); + GPR[RT] := temp; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + set_overflow_cr0(temp,xer_so) + } + else (); + CA := carry; + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit, bit) Addme + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) _ : +[OE] : +0b011101010 : +[Rc] as instr) = + Some(Addme(RT,RA,OE,Rc)) + +function clause execute (Addme (RT, RA, OE, Rc)) = + let (t1, o1, c1) = (GPR[RA] +_s CA) in + let (t2, o2, c2) = (t1 +_s 0b1111111111111111111111111111111111111111111111111111111111111111) in + { + (bit[64]) temp := t2; + overflow := (o1 | o2); + carry := (c1 | c2); + GPR[RT] := temp; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + set_overflow_cr0(temp,xer_so) + } + else (); + CA := carry; + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit, bit) Subfme + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) _ : +[OE] : +0b011101000 : +[Rc] as instr) = + Some(Subfme(RT,RA,OE,Rc)) + +function clause execute (Subfme (RT, RA, OE, Rc)) = + let (t1, o1, c1) = (~(GPR[RA]) +_s CA) in + let (t2, o2, c2) = (t1 +_s 0b1111111111111111111111111111111111111111111111111111111111111111) in + { + (bit[64]) temp := t2; + overflow := (o1 | o2); + carry := (c1 | c2); + GPR[RT] := temp; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + set_overflow_cr0(temp,xer_so) + } + else (); + CA := carry; + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit, bit) Addze + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) _ : +[OE] : +0b011001010 : +[Rc] as instr) = + Some(Addze(RT,RA,OE,Rc)) + +function clause execute (Addze (RT, RA, OE, Rc)) = + let (temp, overflow, carry) = (GPR[RA] +_s CA) in + { + GPR[RT] := temp; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + set_overflow_cr0(temp,xer_so) + } + else (); + CA := carry; + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit, bit) Subfze + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) _ : +[OE] : +0b011001000 : +[Rc] as instr) = + Some(Subfze(RT,RA,OE,Rc)) + +function clause execute (Subfze (RT, RA, OE, Rc)) = + let (temp, overflow, carry) = (~(GPR[RA]) +_s CA) in + { + GPR[RT] := temp; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + set_overflow_cr0(temp,xer_so) + } + else (); + CA := carry; + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit, bit) Neg + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) _ : +[OE] : +0b001101000 : +[Rc] as instr) = + Some(Neg(RT,RA,OE,Rc)) + +function clause execute (Neg (RT, RA, OE, Rc)) = + let (temp, overflow, _) = (~(GPR[RA]) +_s (bit) 1) in + { + GPR[RT] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else (); + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit[16]) Mulli + +function clause decode (0b000111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[16]) SI as instr) = + Some(Mulli(RT,RA,SI)) + +function clause execute (Mulli (RT, RA, SI)) = + { + (bit[128]) prod := GPR[RA] *_s EXTS(SI); + GPR[RT] := prod[64 .. 127] + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Mullw + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b011101011 : +[Rc] as instr) = + Some(Mullw(RT,RA,RB,OE,Rc)) + +function clause execute (Mullw (RT, RA, RB, OE, Rc)) = + let (prod, overflow, _) = ((GPR[RA])[32 .. 63] *_s (GPR[RB])[32 .. 63]) in + { + GPR[RT] := prod; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + set_overflow_cr0(prod,xer_so) + } + else (); + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Mulhw + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +(bit[1]) _ : +0b001001011 : +[Rc] as instr) = + Some(Mulhw(RT,RA,RB,Rc)) + +function clause execute (Mulhw (RT, RA, RB, Rc)) = + { + (bit[64]) prod := 0; + (bit) overflow := 0; + let (p, o, _) = ((GPR[RA])[32 .. 63] *_s (GPR[RB])[32 .. 63]) in + { + prod := p; + overflow := o + }; + (GPR[RT])[32..63] := prod[0 .. 31]; + (GPR[RT])[0..31] := undefined; + if Rc + then { + (bit) xer_so := XER.SO; + if mode64bit + then CR.CR0 := [undefined,undefined,undefined,xer_so] + else set_overflow_cr0(prod,xer_so) + } + else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Mulhwu + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +(bit[1]) _ : +0b000001011 : +[Rc] as instr) = + Some(Mulhwu(RT,RA,RB,Rc)) + +function clause execute (Mulhwu (RT, RA, RB, Rc)) = + { + (bit[64]) prod := (GPR[RA])[32 .. 63] * (GPR[RB])[32 .. 63]; + (GPR[RT])[32..63] := prod[0 .. 31]; + (GPR[RT])[0..31] := undefined; + if Rc + then { + (bit) xer_so := XER.SO; + if mode64bit + then CR.CR0 := [undefined,undefined,undefined,xer_so] + else set_overflow_cr0(prod,xer_so) + } + else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Divw + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b111101011 : +[Rc] as instr) = + Some(Divw(RT,RA,RB,OE,Rc)) + +function clause execute (Divw (RT, RA, RB, OE, Rc)) = + { + (bit[32]) dividend := (GPR[RA])[32 .. 63]; + (bit[32]) divisor := (GPR[RB])[32 .. 63]; + (bit[64]) divided := 0b0000000000000000000000000000000000000000000000000000000000000000; + (bit) overflow := 0; + let (d, o, _) = (dividend quot_s divisor) in + { + divided[32..63] := d; + overflow := o + }; + (GPR[RT])[32..63] := divided[32 .. 63]; + (GPR[RT])[0..31] := undefined; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + if mode64bit | overflow + then CR.CR0 := [undefined,undefined,undefined,xer_so] + else set_overflow_cr0(divided,xer_so) + } + else (); + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Divwu + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b111001011 : +[Rc] as instr) = + Some(Divwu(RT,RA,RB,OE,Rc)) + +function clause execute (Divwu (RT, RA, RB, OE, Rc)) = + { + (bit[32]) dividend := (GPR[RA])[32 .. 63]; + (bit[32]) divisor := (GPR[RB])[32 .. 63]; + (bit[64]) divided := 0b0000000000000000000000000000000000000000000000000000000000000000; + (bit) overflow := 0; + let (d, o, _) = (dividend quot divisor) in + { + divided[32..63] := d; + overflow := o + }; + (GPR[RT])[32..63] := divided[32 .. 63]; + (GPR[RT])[0..31] := undefined; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + if mode64bit | overflow + then CR.CR0 := [undefined,undefined,undefined,xer_so] + else set_overflow_cr0(divided,xer_so) + } + else (); + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Divwe + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b110101011 : +[Rc] as instr) = + Some(Divwe(RT,RA,RB,OE,Rc)) + +function clause execute (Divwe (RT, RA, RB, OE, Rc)) = + { + (bit[64]) dividend := (GPR[RA])[32 .. 63] : 0b00000000000000000000000000000000; + (bit[32]) divisor := (GPR[RB])[32 .. 63]; + (bit[64]) divided := 0b0000000000000000000000000000000000000000000000000000000000000000; + (bit) overflow := 0; + let (d, o, _) = (dividend quot_s divisor) in + { + divided[32..63] := d[32 .. 63]; + overflow := o + }; + (GPR[RT])[32..63] := divided[32 .. 63]; + (GPR[RT])[0..31] := undefined; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + if mode64bit | overflow + then CR.CR0 := [undefined,undefined,undefined,xer_so] + else set_overflow_cr0(divided,xer_so) + } + else (); + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Divweu + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b110001011 : +[Rc] as instr) = + Some(Divweu(RT,RA,RB,OE,Rc)) + +function clause execute (Divweu (RT, RA, RB, OE, Rc)) = + { + (bit[64]) dividend := (GPR[RA])[32 .. 63] : 0b00000000000000000000000000000000; + (bit[32]) divisor := (GPR[RB])[32 .. 63]; + (bit[64]) divided := 0b0000000000000000000000000000000000000000000000000000000000000000; + (bit) overflow := 0; + let (d, o, _) = (dividend quot divisor) in + { + divided[32..63] := d[32 .. 63]; + overflow := o + }; + (GPR[RT])[32..63] := divided[32 .. 63]; + (GPR[RT])[0..31] := undefined; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + if mode64bit | overflow + then CR.CR0 := [undefined,undefined,undefined,xer_so] + else set_overflow_cr0(divided,xer_so) + } + else (); + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Mulld + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b011101001 : +[Rc] as instr) = + Some(Mulld(RT,RA,RB,OE,Rc)) + +function clause execute (Mulld (RT, RA, RB, OE, Rc)) = + { + (bit[128]) prod := 0; + (bit) overflow := 0; + let (p, o, _) = (GPR[RA] *_s GPR[RB]) in + { + prod := p; + overflow := o + }; + GPR[RT] := prod[64 .. 127]; + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + set_overflow_cr0(prod[64 .. 127],xer_so) + } + else (); + if OE then set_SO_OV(overflow) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Mulhd + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +(bit[1]) _ : +0b001001001 : +[Rc] as instr) = + Some(Mulhd(RT,RA,RB,Rc)) + +function clause execute (Mulhd (RT, RA, RB, Rc)) = + { + (bit[128]) prod := GPR[RA] *_s GPR[RB]; + GPR[RT] := prod[0 .. 63]; + if Rc then set_overflow_cr0(prod[0 .. 63],XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Mulhdu + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +(bit[1]) _ : +0b000001001 : +[Rc] as instr) = + Some(Mulhdu(RT,RA,RB,Rc)) + +function clause execute (Mulhdu (RT, RA, RB, Rc)) = + { + (bit[128]) prod := GPR[RA] * GPR[RB]; + GPR[RT] := prod[0 .. 63]; + if Rc then set_overflow_cr0(prod[0 .. 63],XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Divd + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b111101001 : +[Rc] as instr) = + Some(Divd(RT,RA,RB,OE,Rc)) + +function clause execute (Divd (RT, RA, RB, OE, Rc)) = + { + (bit[64]) dividend := GPR[RA]; + (bit[64]) divisor := GPR[RB]; + (bit[64]) divided := 0b0000000000000000000000000000000000000000000000000000000000000000; + (bit) overflow := 0; + let (d, o, _) = (dividend quot_s divisor) in + { + divided := d; + overflow := o + }; + GPR[RT] := divided; + if OE then set_SO_OV(overflow) else (); + if Rc then set_overflow_cr0(divided,overflow | XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Divdu + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b111001001 : +[Rc] as instr) = + Some(Divdu(RT,RA,RB,OE,Rc)) + +function clause execute (Divdu (RT, RA, RB, OE, Rc)) = + { + (bit[64]) dividend := GPR[RA]; + (bit[64]) divisor := GPR[RB]; + (bit[64]) divided := 0b0000000000000000000000000000000000000000000000000000000000000000; + (bit) overflow := 0; + let (d, o, _) = (dividend quot divisor) in + { + divided := d; + overflow := o + }; + GPR[RT] := divided; + if OE then set_SO_OV(overflow) else (); + if Rc then set_overflow_cr0(divided,overflow | XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Divde + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b110101001 : +[Rc] as instr) = + Some(Divde(RT,RA,RB,OE,Rc)) + +function clause execute (Divde (RT, RA, RB, OE, Rc)) = + { + (bit[128]) dividend := + GPR[RA] : 0b0000000000000000000000000000000000000000000000000000000000000000; + (bit[64]) divisor := GPR[RB]; + (bit[128]) divided := 0; + (bit) overflow := 0; + let (d, o, _) = (dividend quot_s divisor) in + { + divided := d; + overflow := o + }; + GPR[RT] := divided[64 .. 127]; + if OE then set_SO_OV(overflow) else (); + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + if overflow + then CR.CR0 := [undefined,undefined,undefined,xer_so] + else set_overflow_cr0(divided[64 .. 127],xer_so) + } + else () + } + +union ast member (bit[5], bit[5], bit[5], bit, bit) Divdeu + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b110001001 : +[Rc] as instr) = + Some(Divdeu(RT,RA,RB,OE,Rc)) + +function clause execute (Divdeu (RT, RA, RB, OE, Rc)) = + { + (bit[128]) dividend := + GPR[RA] : 0b0000000000000000000000000000000000000000000000000000000000000000; + (bit[64]) divisor := GPR[RB]; + (bit[128]) divided := 0; + (bit) overflow := 0; + let (d, o, _) = (dividend quot divisor) in + { + divided := d; + overflow := o + }; + GPR[RT] := divided[64 .. 127]; + if OE then set_SO_OV(overflow) else (); + if Rc + then { + (bit) xer_so := XER.SO; + if OE & overflow then xer_so := overflow else (); + if overflow + then CR.CR0 := [undefined,undefined,undefined,xer_so] + else set_overflow_cr0(divided[64 .. 127],xer_so) + } + else () + } + +union ast member (bit[3], bit, bit[5], bit[16]) Cmpi + +function clause decode (0b001011 : +(bit[3]) BF : +(bit[1]) _ : +[L] : +(bit[5]) RA : +(bit[16]) SI as instr) = + Some(Cmpi(BF,L,RA,SI)) + +function clause execute (Cmpi (BF, L, RA, SI)) = + { + (bit[64]) a := 0; + if L == 0 then a := EXTS((GPR[RA])[32 .. 63]) else a := GPR[RA]; + if a < EXTS(SI) then c := 0b100 else if a > EXTS(SI) then c := 0b010 else c := 0b001; + CR[4 * BF + 32..4 * BF + 35] := c : [XER.SO] + } + +union ast member (bit[3], bit, bit[5], bit[5]) Cmp + +function clause decode (0b011111 : +(bit[3]) BF : +(bit[1]) _ : +[L] : +(bit[5]) RA : +(bit[5]) RB : +0b0000000000 : +(bit[1]) _ as instr) = + Some(Cmp(BF,L,RA,RB)) + +function clause execute (Cmp (BF, L, RA, RB)) = + { + (bit[64]) a := 0; + (bit[64]) b := 0; + if L == 0 + then { + a := EXTS((GPR[RA])[32 .. 63]); + b := EXTS((GPR[RB])[32 .. 63]) + } + else { + a := GPR[RA]; + b := GPR[RB] + }; + if a < b then c := 0b100 else if a > b then c := 0b010 else c := 0b001; + CR[4 * BF + 32..4 * BF + 35] := c : [XER.SO] + } + +union ast member (bit[3], bit, bit[5], bit[16]) Cmpli + +function clause decode (0b001010 : +(bit[3]) BF : +(bit[1]) _ : +[L] : +(bit[5]) RA : +(bit[16]) UI as instr) = + Some(Cmpli(BF,L,RA,UI)) + +function clause execute (Cmpli (BF, L, RA, UI)) = + { + (bit[64]) a := 0; + (bit[3]) c := 0; + if L == 0 then a := 0b00000000000000000000000000000000 : (GPR[RA])[32 .. 63] else a := GPR[RA]; + if a <_u 0b000000000000000000000000000000000000000000000000 : UI + then c := 0b100 + else if a >_u 0b000000000000000000000000000000000000000000000000 : UI + then c := 0b010 + else c := 0b001; + CR[4 * BF + 32..4 * BF + 35] := c : [XER.SO] + } + +union ast member (bit[3], bit, bit[5], bit[5]) Cmpl + +function clause decode (0b011111 : +(bit[3]) BF : +(bit[1]) _ : +[L] : +(bit[5]) RA : +(bit[5]) RB : +0b0000100000 : +(bit[1]) _ as instr) = + Some(Cmpl(BF,L,RA,RB)) + +function clause execute (Cmpl (BF, L, RA, RB)) = + { + (bit[64]) a := 0; + (bit[64]) b := 0; + (bit[3]) c := 0; + if L == 0 + then { + a := 0b00000000000000000000000000000000 : (GPR[RA])[32 .. 63]; + b := 0b00000000000000000000000000000000 : (GPR[RB])[32 .. 63] + } + else { + a := GPR[RA]; + b := GPR[RB] + }; + if a <_u b then c := 0b100 else if a >_u b then c := 0b010 else c := 0b001; + CR[4 * BF + 32..4 * BF + 35] := c : [XER.SO] + } + +union ast member (bit[5], bit[5], bit[5], bit[5]) Isel + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +(bit[5]) BC : +0b01111 : +(bit[1]) _ as instr) = + Some(Isel(RT,RA,RB,BC)) + +function clause execute (Isel (RT, RA, RB, BC)) = + { + (bit[64]) a := 0; + if RA == 0 then a := 0 else a := GPR[RA]; + if CR[BC + 32] == 1 + then { + GPR[RT] := a; + discard := GPR[RB] + } + else GPR[RT] := GPR[RB] + } + +union ast member (bit[5], bit[5], bit[16]) Andi + +function clause decode (0b011100 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) UI as instr) = + Some(Andi(RS,RA,UI)) + +function clause execute (Andi (RS, RA, UI)) = + { + (bit[64]) temp := (GPR[RS] & 0b000000000000000000000000000000000000000000000000 : UI); + GPR[RA] := temp; + set_overflow_cr0(temp,XER.SO) + } + +union ast member (bit[5], bit[5], bit[16]) Andis + +function clause decode (0b011101 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) UI as instr) = + Some(Andis(RS,RA,UI)) + +function clause execute (Andis (RS, RA, UI)) = + { + (bit[64]) temp := (GPR[RS] & 0b00000000000000000000000000000000 : UI : 0b0000000000000000); + GPR[RA] := temp; + set_overflow_cr0(temp,XER.SO) + } + +union ast member (bit[5], bit[5], bit[16]) Ori + +function clause decode (0b011000 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) UI as instr) = + Some(Ori(RS,RA,UI)) + +function clause execute (Ori (RS, RA, UI)) = + GPR[RA] := (GPR[RS] | 0b000000000000000000000000000000000000000000000000 : UI) + +union ast member (bit[5], bit[5], bit[16]) Oris + +function clause decode (0b011001 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) UI as instr) = + Some(Oris(RS,RA,UI)) + +function clause execute (Oris (RS, RA, UI)) = + GPR[RA] := (GPR[RS] | 0b00000000000000000000000000000000 : UI : 0b0000000000000000) + +union ast member (bit[5], bit[5], bit[16]) Xori + +function clause decode (0b011010 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) UI as instr) = + Some(Xori(RS,RA,UI)) + +function clause execute (Xori (RS, RA, UI)) = + GPR[RA] := GPR[RS] ^ 0b000000000000000000000000000000000000000000000000 : UI + +union ast member (bit[5], bit[5], bit[16]) Xoris + +function clause decode (0b011011 : +(bit[5]) RS : +(bit[5]) RA : +(bit[16]) UI as instr) = + Some(Xoris(RS,RA,UI)) + +function clause execute (Xoris (RS, RA, UI)) = + GPR[RA] := GPR[RS] ^ 0b00000000000000000000000000000000 : UI : 0b0000000000000000 + +union ast member (bit[5], bit[5], bit[5], bit) And + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0000011100 : +[Rc] as instr) = + Some(And(RS,RA,RB,Rc)) + +function clause execute (And (RS, RA, RB, Rc)) = + { + (bit[64]) temp := (GPR[RS] & GPR[RB]); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Xor + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0100111100 : +[Rc] as instr) = + Some(Xor(RS,RA,RB,Rc)) + +function clause execute (Xor (RS, RA, RB, Rc)) = + { + (bit[64]) temp := 0; + if RS == RB + then { + temp := GPR[RS]; + temp := 0; + GPR[RA] := 0 + } + else { + temp := GPR[RS] ^ GPR[RB]; + GPR[RA] := temp + }; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Nand + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0111011100 : +[Rc] as instr) = + Some(Nand(RS,RA,RB,Rc)) + +function clause execute (Nand (RS, RA, RB, Rc)) = + { + (bit[64]) temp := ~(GPR[RS] & GPR[RB]); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Or + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0110111100 : +[Rc] as instr) = + Some(Or(RS,RA,RB,Rc)) + +function clause execute (Or (RS, RA, RB, Rc)) = + { + (bit[64]) temp := (GPR[RS] | GPR[RB]); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Nor + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0001111100 : +[Rc] as instr) = + Some(Nor(RS,RA,RB,Rc)) + +function clause execute (Nor (RS, RA, RB, Rc)) = + { + (bit[64]) temp := ~(GPR[RS] | GPR[RB]); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Eqv + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0100011100 : +[Rc] as instr) = + Some(Eqv(RS,RA,RB,Rc)) + +function clause execute (Eqv (RS, RA, RB, Rc)) = + { + (bit[64]) temp := GPR[RS] ^ ~(GPR[RB]); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Andc + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0000111100 : +[Rc] as instr) = + Some(Andc(RS,RA,RB,Rc)) + +function clause execute (Andc (RS, RA, RB, Rc)) = + { + (bit[64]) temp := (GPR[RS] & ~(GPR[RB])); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Orc + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0110011100 : +[Rc] as instr) = + Some(Orc(RS,RA,RB,Rc)) + +function clause execute (Orc (RS, RA, RB, Rc)) = + { + (bit[64]) temp := (GPR[RS] | ~(GPR[RB])); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit) Extsb + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b1110111010 : +[Rc] as instr) = + Some(Extsb(RS,RA,Rc)) + +function clause execute (Extsb (RS, RA, Rc)) = + { + (bit[64]) temp := 0; + s := (GPR[RS])[56]; + temp[56..63] := (GPR[RS])[56 .. 63]; + (GPR[RA])[56..63] := temp[56 .. 63]; + temp[0..55] := s ^^ 56; + (GPR[RA])[0..55] := temp[0 .. 55]; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit) Extsh + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b1110011010 : +[Rc] as instr) = + Some(Extsh(RS,RA,Rc)) + +function clause execute (Extsh (RS, RA, Rc)) = + { + (bit[64]) temp := 0; + s := (GPR[RS])[48]; + temp[48..63] := (GPR[RS])[48 .. 63]; + (GPR[RA])[48..63] := temp[48 .. 63]; + temp[0..47] := s ^^ 48; + (GPR[RA])[0..47] := temp[0 .. 47]; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit) Cntlzw + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b0000011010 : +[Rc] as instr) = + Some(Cntlzw(RS,RA,Rc)) + +function clause execute (Cntlzw (RS, RA, Rc)) = + { + temp := (bit[64]) (countLeadingZeroes(GPR[RS],32)); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5]) Cmpb + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0111111100 : +(bit[1]) _ as instr) = + Some(Cmpb(RS,RA,RB)) + +function clause execute (Cmpb (RS, RA, RB)) = + foreach (n from 0 to 7 by 1 in inc) + if (GPR[RS])[8 * n .. 8 * n + 7] == (GPR[RB])[8 * n .. 8 * n + 7] + then (GPR[RA])[8 * n..8 * n + 7] := 0b11111111 + else (GPR[RA])[8 * n..8 * n + 7] := (bit[8]) 0 + +union ast member (bit[5], bit[5]) Popcntb + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b0001111010 : +(bit[1]) _ as instr) = + Some(Popcntb(RS,RA)) + +function clause execute (Popcntb (RS, RA)) = + foreach (i from 0 to 7 by 1 in inc) + { + ([|64|]) n := 0; + foreach (j from 0 to 7 by 1 in inc) if (GPR[RS])[i * 8 + j] == 1 then n := n + 1 else (); + (GPR[RA])[i * 8..i * 8 + 7] := (bit[8]) n + } + +union ast member (bit[5], bit[5]) Popcntw + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b0101111010 : +(bit[1]) _ as instr) = + Some(Popcntw(RS,RA)) + +function clause execute (Popcntw (RS, RA)) = + foreach (i from 0 to 1 by 1 in inc) + { + ([|64|]) n := 0; + foreach (j from 0 to 31 by 1 in inc) if (GPR[RS])[i * 32 + j] == 1 then n := n + 1 else (); + (GPR[RA])[i * 32..i * 32 + 31] := (bit[32]) n + } + +union ast member (bit[5], bit[5]) Prtyd + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b0010111010 : +(bit[1]) _ as instr) = + Some(Prtyd(RS,RA)) + +function clause execute (Prtyd (RS, RA)) = + { + s := 0; + foreach (i from 0 to 7 by 1 in inc) s := s ^ (GPR[RS])[i * 8 + 7]; + GPR[RA] := 0b000000000000000000000000000000000000000000000000000000000000000 : [s] + } + +union ast member (bit[5], bit[5]) Prtyw + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b0010011010 : +(bit[1]) _ as instr) = + Some(Prtyw(RS,RA)) + +function clause execute (Prtyw (RS, RA)) = + { + s := 0; + t := 0; + foreach (i from 0 to 3 by 1 in inc) s := s ^ (GPR[RS])[i * 8 + 7]; + foreach (i from 4 to 7 by 1 in inc) t := t ^ (GPR[RS])[i * 8 + 7]; + (GPR[RA])[0..31] := 0b0000000000000000000000000000000 : [s]; + (GPR[RA])[32..63] := 0b0000000000000000000000000000000 : [t] + } + +union ast member (bit[5], bit[5], bit) Extsw + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b1111011010 : +[Rc] as instr) = + Some(Extsw(RS,RA,Rc)) + +function clause execute (Extsw (RS, RA, Rc)) = + { + s := (GPR[RS])[32]; + (bit[64]) temp := 0; + temp[32..63] := (GPR[RS])[32 .. 63]; + temp[0..31] := s ^^ 32; + if Rc then set_overflow_cr0(temp,XER.SO) else (); + GPR[RA] := temp + } + +union ast member (bit[5], bit[5], bit) Cntlzd + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b0000111010 : +[Rc] as instr) = + Some(Cntlzd(RS,RA,Rc)) + +function clause execute (Cntlzd (RS, RA, Rc)) = + { + temp := (bit[64]) (countLeadingZeroes(GPR[RS],0)); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5]) Popcntd + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b0111111010 : +(bit[1]) _ as instr) = + Some(Popcntd(RS,RA)) + +function clause execute (Popcntd (RS, RA)) = + { + ([|64|]) n := 0; + foreach (i from 0 to 63 by 1 in inc) if (GPR[RS])[i] == 1 then n := n + 1 else (); + GPR[RA] := (bit[64]) n + } + +union ast member (bit[5], bit[5], bit[5]) Bpermd + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0011111100 : +(bit[1]) _ as instr) = + Some(Bpermd(RS,RA,RB)) + +function clause execute (Bpermd (RS, RA, RB)) = + { + (bit[8]) perm := 0; + foreach (i from 0 to 7 by 1 in inc) + { + index := (GPR[RS])[8 * i .. 8 * i + 7]; + if index <_u (bit[8]) 64 + then perm[i] := (GPR[RB])[index] + else { + perm[i] := 0; + discard := GPR[RB] + } + }; + GPR[RA] := 0b00000000000000000000000000000000000000000000000000000000 : perm[0 .. 7] + } + +union ast member (bit[5], bit[5], bit[5], bit[5], bit[5], bit) Rlwinm + +function clause decode (0b010101 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) SH : +(bit[5]) MB : +(bit[5]) ME : +[Rc] as instr) = + Some(Rlwinm(RS,RA,SH,MB,ME,Rc)) + +function clause execute (Rlwinm (RS, RA, SH, MB, ME, Rc)) = + { + n := SH; + r := ROTL((GPR[RS])[32 .. 63] : (GPR[RS])[32 .. 63],n); + m := MASK(MB + 32,ME + 32); + (bit[64]) temp := (r & m); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit[5], bit[5], bit) Rlwnm + +function clause decode (0b010111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +(bit[5]) MB : +(bit[5]) ME : +[Rc] as instr) = + Some(Rlwnm(RS,RA,RB,MB,ME,Rc)) + +function clause execute (Rlwnm (RS, RA, RB, MB, ME, Rc)) = + { + n := (GPR[RB])[59 .. 63]; + r := ROTL((GPR[RS])[32 .. 63] : (GPR[RS])[32 .. 63],n); + m := MASK(MB + 32,ME + 32); + (bit[64]) temp := (r & m); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit[5], bit[5], bit) Rlwimi + +function clause decode (0b010100 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) SH : +(bit[5]) MB : +(bit[5]) ME : +[Rc] as instr) = + Some(Rlwimi(RS,RA,SH,MB,ME,Rc)) + +function clause execute (Rlwimi (RS, RA, SH, MB, ME, Rc)) = + { + n := SH; + r := ROTL((GPR[RS])[32 .. 63] : (GPR[RS])[32 .. 63],n); + m := MASK(MB + 32,ME + 32); + (bit[64]) temp := (r & m | GPR[RA] & ~(m)); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[6], bit[6], bit) Rldicl + +function clause decode (0b011110 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +(bit[6]) mb : +0b000 : +(bit[1]) _ : +[Rc] as instr) = + Some(Rldicl(RS,RA,instr[16 .. 20] : instr[30 .. 30],mb,Rc)) + +function clause execute (Rldicl (RS, RA, sh, mb, Rc)) = + { + n := [sh[5]] : sh[0 .. 4]; + r := ROTL(GPR[RS],n); + b := [mb[5]] : mb[0 .. 4]; + m := MASK(b,63); + (bit[64]) temp := (r & m); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[6], bit[6], bit) Rldicr + +function clause decode (0b011110 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +(bit[6]) me : +0b001 : +(bit[1]) _ : +[Rc] as instr) = + Some(Rldicr(RS,RA,instr[16 .. 20] : instr[30 .. 30],me,Rc)) + +function clause execute (Rldicr (RS, RA, sh, me, Rc)) = + { + n := [sh[5]] : sh[0 .. 4]; + r := ROTL(GPR[RS],n); + e := [me[5]] : me[0 .. 4]; + m := MASK(0,e); + (bit[64]) temp := (r & m); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[6], bit[6], bit) Rldic + +function clause decode (0b011110 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +(bit[6]) mb : +0b010 : +(bit[1]) _ : +[Rc] as instr) = + Some(Rldic(RS,RA,instr[16 .. 20] : instr[30 .. 30],mb,Rc)) + +function clause execute (Rldic (RS, RA, sh, mb, Rc)) = + { + n := [sh[5]] : sh[0 .. 4]; + r := ROTL(GPR[RS],n); + b := [mb[5]] : mb[0 .. 4]; + m := MASK(b,(bit[6]) (~(n))); + (bit[64]) temp := (r & m); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit[6], bit) Rldcl + +function clause decode (0b011110 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +(bit[6]) mb : +0b1000 : +[Rc] as instr) = + Some(Rldcl(RS,RA,RB,mb,Rc)) + +function clause execute (Rldcl (RS, RA, RB, mb, Rc)) = + { + n := (GPR[RB])[58 .. 63]; + r := ROTL(GPR[RS],n); + b := [mb[5]] : mb[0 .. 4]; + m := MASK(b,63); + (bit[64]) temp := (r & m); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit[6], bit) Rldcr + +function clause decode (0b011110 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +(bit[6]) me : +0b1001 : +[Rc] as instr) = + Some(Rldcr(RS,RA,RB,me,Rc)) + +function clause execute (Rldcr (RS, RA, RB, me, Rc)) = + { + n := (GPR[RB])[58 .. 63]; + r := ROTL(GPR[RS],n); + e := [me[5]] : me[0 .. 4]; + m := MASK(0,e); + (bit[64]) temp := (r & m); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[6], bit[6], bit) Rldimi + +function clause decode (0b011110 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +(bit[6]) mb : +0b011 : +(bit[1]) _ : +[Rc] as instr) = + Some(Rldimi(RS,RA,instr[16 .. 20] : instr[30 .. 30],mb,Rc)) + +function clause execute (Rldimi (RS, RA, sh, mb, Rc)) = + { + n := [sh[5]] : sh[0 .. 4]; + r := ROTL(GPR[RS],n); + b := [mb[5]] : mb[0 .. 4]; + m := MASK(b,(bit[6]) (~(n))); + (bit[64]) temp := (r & m | GPR[RA] & ~(m)); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Slw + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0000011000 : +[Rc] as instr) = + Some(Slw(RS,RA,RB,Rc)) + +function clause execute (Slw (RS, RA, RB, Rc)) = + { + n := (GPR[RB])[59 .. 63]; + r := ROTL((GPR[RS])[32 .. 63] : (GPR[RS])[32 .. 63],n); + if (GPR[RB])[58] == 0 + then m := MASK(32,63 - n) + else m := 0b0000000000000000000000000000000000000000000000000000000000000000; + (bit[64]) temp := (r & m); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Srw + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b1000011000 : +[Rc] as instr) = + Some(Srw(RS,RA,RB,Rc)) + +function clause execute (Srw (RS, RA, RB, Rc)) = + { + n := (GPR[RB])[59 .. 63]; + r := ROTL((GPR[RS])[32 .. 63] : (GPR[RS])[32 .. 63],64 - n); + if (GPR[RB])[58] == 0 + then m := MASK(n + 32,63) + else m := 0b0000000000000000000000000000000000000000000000000000000000000000; + (bit[64]) temp := (r & m); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Srawi + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) SH : +0b1100111000 : +[Rc] as instr) = + Some(Srawi(RS,RA,SH,Rc)) + +function clause execute (Srawi (RS, RA, SH, Rc)) = + { + n := SH; + r := ROTL((GPR[RS])[32 .. 63] : (GPR[RS])[32 .. 63],64 - n); + m := MASK(n + 32,63); + s := (GPR[RS])[32]; + (bit[64]) temp := (r & m | s ^^ 64 & ~(m)); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else (); + XER.CA := if n >_u (bit[5]) 0 then s & ~((r & ~(m)) == 0) else 0 + } + +union ast member (bit[5], bit[5], bit[5], bit) Sraw + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b1100011000 : +[Rc] as instr) = + Some(Sraw(RS,RA,RB,Rc)) + +function clause execute (Sraw (RS, RA, RB, Rc)) = + { + n := (GPR[RB])[59 .. 63]; + r := ROTL((GPR[RS])[32 .. 63] : (GPR[RS])[32 .. 63],64 - n); + if (GPR[RB])[58] == 0 + then m := MASK(n + 32,63) + else m := 0b0000000000000000000000000000000000000000000000000000000000000000; + s := (GPR[RS])[32]; + (bit[64]) temp := (r & m | s ^^ 64 & ~(m)); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else (); + XER.CA := if n >_u (bit[5]) 0 then s & ~((r & ~(m)) == 0) else 0 + } + +union ast member (bit[5], bit[5], bit[5], bit) Sld + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0000011011 : +[Rc] as instr) = + Some(Sld(RS,RA,RB,Rc)) + +function clause execute (Sld (RS, RA, RB, Rc)) = + { + n := (GPR[RB])[58 .. 63]; + r := ROTL(GPR[RS],n); + if (GPR[RB])[57] == 0 + then m := MASK(0,63 - n) + else m := 0b0000000000000000000000000000000000000000000000000000000000000000; + (bit[64]) temp := (r & m); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[5], bit) Srd + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b1000011011 : +[Rc] as instr) = + Some(Srd(RS,RA,RB,Rc)) + +function clause execute (Srd (RS, RA, RB, Rc)) = + { + n := (GPR[RB])[58 .. 63]; + r := ROTL(GPR[RS],64 - n); + if (GPR[RB])[57] == 0 + then m := MASK(n,63) + else m := 0b0000000000000000000000000000000000000000000000000000000000000000; + (bit[64]) temp := (r & m); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else () + } + +union ast member (bit[5], bit[5], bit[6], bit) Sradi + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b110011101 : +(bit[1]) _ : +[Rc] as instr) = + Some(Sradi(RS,RA,instr[16 .. 20] : instr[30 .. 30],Rc)) + +function clause execute (Sradi (RS, RA, sh, Rc)) = + { + n := [sh[5]] : sh[0 .. 4]; + r := ROTL(GPR[RS],64 - n); + m := MASK(n,63); + s := (GPR[RS])[0]; + (bit[64]) temp := (r & m | s ^^ 64 & ~(m)); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else (); + XER.CA := if n >_u (bit[6]) 0 then s & ~((r & ~(m)) == 0) else 0 + } + +union ast member (bit[5], bit[5], bit[5], bit) Srad + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b1100011010 : +[Rc] as instr) = + Some(Srad(RS,RA,RB,Rc)) + +function clause execute (Srad (RS, RA, RB, Rc)) = + { + n := (GPR[RB])[58 .. 63]; + r := ROTL(GPR[RS],64 - n); + if (GPR[RB])[57] == 0 + then m := MASK(n,63) + else m := 0b0000000000000000000000000000000000000000000000000000000000000000; + s := (GPR[RS])[0]; + (bit[64]) temp := (r & m | s ^^ 64 & ~(m)); + GPR[RA] := temp; + if Rc then set_overflow_cr0(temp,XER.SO) else (); + XER.CA := if n >_u (bit[6]) 0 then s & ~((r & ~(m)) == 0) else 0 + } + +union ast member (bit[5], bit[5]) Cdtbcd + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b0100011010 : +(bit[1]) _ as instr) = + Some(Cdtbcd(RS,RA)) + +function clause execute (Cdtbcd (RS, RA)) = + foreach (i from 0 to 1 by 1 in inc) + { + n := i * 32; + (GPR[RA])[n + 0..n + 7] := (bit[8]) 0; + (GPR[RA])[n + 8..n + 19] := DEC_TO_BCD((GPR[RS])[n + 12 .. n + 21]); + (GPR[RA])[n + 20..n + 31] := DEC_TO_BCD((GPR[RS])[n + 22 .. n + 31]) + } + +union ast member (bit[5], bit[5]) Cbcdtd + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) _ : +0b0100111010 : +(bit[1]) _ as instr) = + Some(Cbcdtd(RS,RA)) + +function clause execute (Cbcdtd (RS, RA)) = + foreach (i from 0 to 1 by 1 in inc) + { + n := i * 32; + (GPR[RA])[n + 0..n + 11] := (bit[12]) 0; + (GPR[RA])[n + 12..n + 21] := BCD_TO_DEC((GPR[RS])[n + 8 .. n + 19]); + (GPR[RA])[n + 22..n + 31] := BCD_TO_DEC((GPR[RS])[n + 20 .. n + 31]) + } + +union ast member (bit[5], bit[5], bit[5]) Addg6s + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +(bit[1]) _ : +0b001001010 : +(bit[1]) _ as instr) = + Some(Addg6s(RT,RA,RB)) + +function clause execute (Addg6s (RT, RA, RB)) = + { + (bit[16]) dc := 0; + foreach (i from 0 to 15 by 1 in inc) + let (v, _, co) = ((GPR[RA])[4 * i .. 63] + (GPR[RB])[4 * i .. 63]) in dc[i] := carry_out(v,co); + c := + (dc[0] ^^ 4) : + (dc[1] ^^ 4) : + (dc[2] ^^ 4) : + (dc[3] ^^ 4) : + (dc[4] ^^ 4) : + (dc[5] ^^ 4) : + (dc[6] ^^ 4) : + (dc[7] ^^ 4) : + (dc[8] ^^ 4) : + (dc[9] ^^ 4) : + (dc[10] ^^ 4) : + (dc[11] ^^ 4) : + (dc[12] ^^ 4) : (dc[13] ^^ 4) : (dc[14] ^^ 4) : (dc[15] ^^ 4); + GPR[RT] := (~(c) & 0b0110011001100110011001100110011001100110011001100110011001100110) + } + +union ast member (bit[5], bit[10]) Mtspr + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[10]) spr : +0b0111010011 : +(bit[1]) _ as instr) = + Some(Mtspr(RS,spr)) + +function clause execute (Mtspr (RS, spr)) = + { + n := spr[5 .. 9] : spr[0 .. 4]; + if n == 13 + then trap(()) + else if n == 1 + then { + (bit[64]) reg := GPR[RS]; + (bit[32]) front := zero_or_undef(reg[0 .. 31]); + (bit) xer_so := reg[32]; + (bit) xer_ov := reg[33]; + (bit) xer_ca := reg[34]; + (bit[22]) mid := zero_or_undef(reg[35 .. 56]); + (bit[7]) bot := reg[57 .. 63]; + XER := front : [xer_so] : [xer_ov] : [xer_ca] : mid : bot + } + else if length(SPR[n]) == 64 + then SPR[n] := GPR[RS] + else if n == 152 then CTRL := (GPR[RS])[32 .. 63] else () + } + +union ast member (bit[5], bit[10]) Mfspr + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[10]) spr : +0b0101010011 : +(bit[1]) _ as instr) = + Some(Mfspr(RT,spr)) + +function clause execute (Mfspr (RT, spr)) = + { + n := spr[5 .. 9] : spr[0 .. 4]; + if length(SPR[n]) == 64 + then GPR[RT] := SPR[n] + else GPR[RT] := 0b00000000000000000000000000000000 : SPR[n] + } + +union ast member (bit[5], bit[8]) Mtcrf + +function clause decode (0b011111 : +(bit[5]) RS : +0b0 : +(bit[8]) FXM : +(bit[1]) _ : +0b0010010000 : +(bit[1]) _ as instr) = + Some(Mtcrf(RS,FXM)) + +function clause execute (Mtcrf (RS, FXM)) = + { + mask := + (FXM[0] ^^ 4) : + (FXM[1] ^^ 4) : + (FXM[2] ^^ 4) : + (FXM[3] ^^ 4) : (FXM[4] ^^ 4) : (FXM[5] ^^ 4) : (FXM[6] ^^ 4) : (FXM[7] ^^ 4); + CR := ((bit[32]) ((GPR[RS])[32 .. 63] & mask) | (bit[32]) (CR & ~((bit[32]) mask))) + } + +union ast member (bit[5]) Mfcr + +function clause decode (0b011111 : +(bit[5]) RT : +0b0 : +(bit[9]) _ : +0b0000010011 : +(bit[1]) _ as instr) = + Some(Mfcr(RT)) + +function clause execute (Mfcr (RT)) = GPR[RT] := 0b00000000000000000000000000000000 : CR + +union ast member (bit[5], bit[8]) Mtocrf + +function clause decode (0b011111 : +(bit[5]) RS : +0b1 : +(bit[8]) FXM : +(bit[1]) _ : +0b0010010000 : +(bit[1]) _ as instr) = + Some(Mtocrf(RS,FXM)) + +function clause execute (Mtocrf (RS, FXM)) = + { + ([|7|]) n := 0; + count := 0; + foreach (i from 0 to 7 by 1 in inc) + if FXM[i] == 1 + then { + n := i; + count := count + 1 + } + else (); + if count == 1 + then CR[4 * n + 32..4 * n + 35] := (GPR[RS])[4 * n + 32 .. 4 * n + 35] + else CR := undefined + } + +union ast member (bit[5], bit[8]) Mfocrf + +function clause decode (0b011111 : +(bit[5]) RT : +0b1 : +(bit[8]) FXM : +(bit[1]) _ : +0b0000010011 : +(bit[1]) _ as instr) = + Some(Mfocrf(RT,FXM)) + +function clause execute (Mfocrf (RT, FXM)) = + { + ([|7|]) n := 0; + count := 0; + foreach (i from 0 to 7 by 1 in inc) + if FXM[i] == 1 + then { + n := i; + count := count + 1 + } + else (); + if count == 1 + then { + (bit[64]) temp := undefined; + temp[4 * n + 32..4 * n + 35] := CR[4 * n + 32 .. 4 * n + 35]; + GPR[RT] := temp + } + else GPR[RT] := undefined + } + +union ast member (bit[3]) Mcrxr + +function clause decode (0b011111 : +(bit[3]) BF : +(bit[2]) _ : +(bit[5]) _ : +(bit[5]) _ : +0b1000000000 : +(bit[1]) _ as instr) = + Some(Mcrxr(BF)) + +function clause execute (Mcrxr (BF)) = + { + CR[4 * BF + 32..4 * BF + 35] := XER[32 .. 35]; + XER[32..35] := 0b0000 + } + +union ast member (bit[5], bit[5], bit[5], bit) Dlmzb + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0001001110 : +[Rc] as instr) = + Some(Dlmzb(RS,RA,RB,Rc)) + +function clause execute (Dlmzb (RS, RA, RB, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Macchw + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b010101100 : +[Rc] as instr) = + Some(Macchw(RT,RA,RB,OE,Rc)) + +function clause execute (Macchw (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Macchws + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b011101100 : +[Rc] as instr) = + Some(Macchws(RT,RA,RB,OE,Rc)) + +function clause execute (Macchws (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Macchwu + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b010001100 : +[Rc] as instr) = + Some(Macchwu(RT,RA,RB,OE,Rc)) + +function clause execute (Macchwu (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Macchwsu + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b011001100 : +[Rc] as instr) = + Some(Macchwsu(RT,RA,RB,OE,Rc)) + +function clause execute (Macchwsu (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Machhw + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b000101100 : +[Rc] as instr) = + Some(Machhw(RT,RA,RB,OE,Rc)) + +function clause execute (Machhw (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Machhws + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b001101100 : +[Rc] as instr) = + Some(Machhws(RT,RA,RB,OE,Rc)) + +function clause execute (Machhws (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Machhwu + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b000001100 : +[Rc] as instr) = + Some(Machhwu(RT,RA,RB,OE,Rc)) + +function clause execute (Machhwu (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Machhwsu + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b001001100 : +[Rc] as instr) = + Some(Machhwsu(RT,RA,RB,OE,Rc)) + +function clause execute (Machhwsu (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Maclhw + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b110101100 : +[Rc] as instr) = + Some(Maclhw(RT,RA,RB,OE,Rc)) + +function clause execute (Maclhw (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Maclhws + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b111101100 : +[Rc] as instr) = + Some(Maclhws(RT,RA,RB,OE,Rc)) + +function clause execute (Maclhws (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Maclhwu + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b110001100 : +[Rc] as instr) = + Some(Maclhwu(RT,RA,RB,OE,Rc)) + +function clause execute (Maclhwu (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Maclhwsu + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b111001100 : +[Rc] as instr) = + Some(Maclhwsu(RT,RA,RB,OE,Rc)) + +function clause execute (Maclhwsu (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit) Mulchw + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0010101000 : +[Rc] as instr) = + Some(Mulchw(RT,RA,RB,Rc)) + +function clause execute (Mulchw (RT, RA, RB, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit) Mulchwu + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0010001000 : +[Rc] as instr) = + Some(Mulchwu(RT,RA,RB,Rc)) + +function clause execute (Mulchwu (RT, RA, RB, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit) Mulhhw + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0000101000 : +[Rc] as instr) = + Some(Mulhhw(RT,RA,RB,Rc)) + +function clause execute (Mulhhw (RT, RA, RB, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit) Mulhhwu + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0000001000 : +[Rc] as instr) = + Some(Mulhhwu(RT,RA,RB,Rc)) + +function clause execute (Mulhhwu (RT, RA, RB, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit) Mullhw + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0110101000 : +[Rc] as instr) = + Some(Mullhw(RT,RA,RB,Rc)) + +function clause execute (Mullhw (RT, RA, RB, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit) Mullhwu + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0110001000 : +[Rc] as instr) = + Some(Mullhwu(RT,RA,RB,Rc)) + +function clause execute (Mullhwu (RT, RA, RB, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Nmacchw + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b010101110 : +[Rc] as instr) = + Some(Nmacchw(RT,RA,RB,OE,Rc)) + +function clause execute (Nmacchw (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Nmacchws + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b011101110 : +[Rc] as instr) = + Some(Nmacchws(RT,RA,RB,OE,Rc)) + +function clause execute (Nmacchws (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Nmachhw + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b000101110 : +[Rc] as instr) = + Some(Nmachhw(RT,RA,RB,OE,Rc)) + +function clause execute (Nmachhw (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Nmachhws + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b001101110 : +[Rc] as instr) = + Some(Nmachhws(RT,RA,RB,OE,Rc)) + +function clause execute (Nmachhws (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Nmaclhw + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b110101110 : +[Rc] as instr) = + Some(Nmaclhw(RT,RA,RB,OE,Rc)) + +function clause execute (Nmaclhw (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5], bit[5], bit, bit) Nmaclhws + +function clause decode (0b000100 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +[OE] : +0b111101110 : +[Rc] as instr) = + Some(Nmaclhws(RT,RA,RB,OE,Rc)) + +function clause execute (Nmaclhws (RT, RA, RB, OE, Rc)) = () + +union ast member (bit[5], bit[5]) Icbi + +function clause decode (0b011111 : +(bit[5]) _ : +(bit[5]) RA : +(bit[5]) RB : +0b1111010110 : +(bit[1]) _ as instr) = + Some(Icbi(RA,RB)) + +function clause execute (Icbi (RA, RB)) = () + +union ast member (bit[4], bit[5], bit[5]) Icbt + +function clause decode (0b011111 : +(bit[1]) _ : +(bit[4]) CT : +(bit[5]) RA : +(bit[5]) RB : +0b0000010110 : +(bit[1]) _ as instr) = + Some(Icbt(CT,RA,RB)) + +function clause execute (Icbt (CT, RA, RB)) = () + +union ast member (bit[5], bit[5]) Dcba + +function clause decode (0b011111 : +(bit[5]) _ : +(bit[5]) RA : +(bit[5]) RB : +0b1011110110 : +(bit[1]) _ as instr) = + Some(Dcba(RA,RB)) + +function clause execute (Dcba (RA, RB)) = () + +union ast member (bit[5], bit[5], bit[5]) Dcbt + +function clause decode (0b011111 : +(bit[5]) TH : +(bit[5]) RA : +(bit[5]) RB : +0b0100010110 : +(bit[1]) _ as instr) = + Some(Dcbt(TH,RA,RB)) + +function clause execute (Dcbt (TH, RA, RB)) = () + +union ast member (bit[5], bit[5], bit[5]) Dcbtst + +function clause decode (0b011111 : +(bit[5]) TH : +(bit[5]) RA : +(bit[5]) RB : +0b0011110110 : +(bit[1]) _ as instr) = + Some(Dcbtst(TH,RA,RB)) + +function clause execute (Dcbtst (TH, RA, RB)) = () + +union ast member (bit[5], bit[5]) Dcbz + +function clause decode (0b011111 : +(bit[5]) _ : +(bit[5]) RA : +(bit[5]) RB : +0b1111110110 : +(bit[1]) _ as instr) = + Some(Dcbz(RA,RB)) + +function clause execute (Dcbz (RA, RB)) = () + +union ast member (bit[5], bit[5]) Dcbst + +function clause decode (0b011111 : +(bit[5]) _ : +(bit[5]) RA : +(bit[5]) RB : +0b0000110110 : +(bit[1]) _ as instr) = + Some(Dcbst(RA,RB)) + +function clause execute (Dcbst (RA, RB)) = () + +union ast member (bit[2], bit[5], bit[5]) Dcbf + +function clause decode (0b011111 : +(bit[3]) _ : +(bit[2]) L : +(bit[5]) RA : +(bit[5]) RB : +0b0001010110 : +(bit[1]) _ as instr) = + Some(Dcbf(L,RA,RB)) + +function clause execute (Dcbf (L, RA, RB)) = () + +union ast member Isync + +function clause decode (0b010011 : +(bit[5]) _ : +(bit[5]) _ : +(bit[5]) _ : +0b0010010110 : +(bit[1]) _ as instr) = + Some(Isync()) + +function clause execute Isync = I_Sync(()) + +union ast member (bit[5], bit[5], bit[5], bit) Lbarx + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0000110100 : +[EH] as instr) = + Some(Lbarx(RT,RA,RB,EH)) + +function clause execute (Lbarx (RT, RA, RB, EH)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + GPR[RT] := 0b00000000000000000000000000000000000000000000000000000000 : MEMr_reserve(EA,1) + } + +union ast member (bit[5], bit[5], bit[5], bit) Lharx + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0001110100 : +[EH] as instr) = + Some(Lharx(RT,RA,RB,EH)) + +function clause execute (Lharx (RT, RA, RB, EH)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + GPR[RT] := 0b000000000000000000000000000000000000000000000000 : MEMr_reserve(EA,2) + } + +union ast member (bit[5], bit[5], bit[5], bit) Lwarx + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0000010100 : +[EH] as instr) = + Some(Lwarx(RT,RA,RB,EH)) + +function clause execute (Lwarx (RT, RA, RB, EH)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + GPR[RT] := 0b00000000000000000000000000000000 : MEMr_reserve(EA,4) + } + +union ast member (bit[5], bit[5], bit[5]) Stbcx + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b1010110110 : +0b1 as instr) = + Some(Stbcx(RS,RA,RB)) + +function clause execute (Stbcx (RS, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + MEMw_EA_cond(EA,1); + status := MEMw_conditional(EA,1,(GPR[RS])[56 .. 63]); + CR0 := 0b00 : [status] : [XER.SO] + } + +union ast member (bit[5], bit[5], bit[5]) Sthcx + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b1011010110 : +0b1 as instr) = + Some(Sthcx(RS,RA,RB)) + +function clause execute (Sthcx (RS, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + MEMw_EA_cond(EA,2); + status := MEMw_conditional(EA,2,(GPR[RS])[48 .. 63]); + CR0 := 0b00 : [status] : [XER.SO] + } + +union ast member (bit[5], bit[5], bit[5]) Stwcx + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0010010110 : +0b1 as instr) = + Some(Stwcx(RS,RA,RB)) + +function clause execute (Stwcx (RS, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + MEMw_EA_cond(EA,4); + status := MEMw_conditional(EA,4,(GPR[RS])[32 .. 63]); + CR0 := 0b00 : [status] : [XER.SO] + } + +union ast member (bit[5], bit[5], bit[5], bit) Ldarx + +function clause decode (0b011111 : +(bit[5]) RT : +(bit[5]) RA : +(bit[5]) RB : +0b0001010100 : +[EH] as instr) = + Some(Ldarx(RT,RA,RB,EH)) + +function clause execute (Ldarx (RT, RA, RB, EH)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + GPR[RT] := MEMr_reserve(EA,8) + } + +union ast member (bit[5], bit[5], bit[5]) Stdcx + +function clause decode (0b011111 : +(bit[5]) RS : +(bit[5]) RA : +(bit[5]) RB : +0b0011010110 : +0b1 as instr) = + Some(Stdcx(RS,RA,RB)) + +function clause execute (Stdcx (RS, RA, RB)) = + { + (bit[64]) b := 0; + (bit[64]) EA := 0; + if RA == 0 then b := 0 else b := GPR[RA]; + EA := b + GPR[RB]; + MEMw_EA_cond(EA,8); + status := MEMw_conditional(EA,8,GPR[RS]); + CR0 := 0b00 : [status] : [XER.SO] + } + +union ast member (bit[2]) Sync + +function clause decode (0b011111 : +(bit[3]) _ : +(bit[2]) L : +(bit[5]) _ : +(bit[5]) _ : +0b1001010110 : +(bit[1]) _ as instr) = + Some(Sync(L)) + +function clause execute (Sync (L)) = + switch L { case 0b00 -> { H_Sync(()) } case 0b01 -> { LW_Sync(()) } } + +union ast member Eieio + +function clause decode (0b011111 : +(bit[5]) _ : +(bit[5]) _ : +(bit[5]) _ : +0b1101010110 : +(bit[1]) _ as instr) = + Some(Eieio()) + +function clause execute Eieio = EIEIO_Sync(()) + +union ast member (bit[2]) Wait + +function clause decode (0b011111 : +(bit[3]) _ : +(bit[2]) WC : +(bit[5]) _ : +(bit[5]) _ : +0b0000111110 : +(bit[1]) _ as instr) = + Some(Wait(WC)) + +function clause execute (Wait (WC)) = () + + +typedef decode_failure = enumerate { no_matching_pattern; unsupported_instruction; illegal_instruction } + +function clause decode _ = None + +end decode +end execute +end ast + +val ast -> option<ast> effect pure supported_instructions +function option<ast> supported_instructions ((ast) instr) = { + switch instr { + (* case (Mbar(_)) -> None *) + case (Sync(0b10)) -> None + case (Sync(0b11)) -> None + case _ -> Some(instr) + } +} + +val ast -> bit effect pure illegal_instructions_pred +function bit illegal_instructions_pred ((ast) instr) = { + switch instr { + case (Bcctr(BO,BI,BH,LK)) -> ~(BO[2]) + case (Lbzu(RT,RA,D)) -> (RA == 0) | (RA == RT) + case (Lbzux(RT,RA,_)) ->(RA == 0) | (RA == RT) + case (Lhzu(RT,RA,D)) -> (RA == 0) | (RA == RT) + case (Lhzux(RT,RA,RB)) -> (RA == 0) | (RA == RT) + case (Lhau(RT,RA,D)) -> (RA == 0) | (RA == RT) + case (Lhaux(RT,RA,RB)) -> (RA == 0) | (RA == RT) + case (Lwzu(RA,RT,D)) -> (RA == 0) | (RA == RT) + case (Lwzux(RT,RA,RB)) -> (RA == 0) | (RA == RT) + case (Lwaux(RA,RT,RB)) -> (RA == 0) | (RA == RT) + case (Ldu(RT,RA,DS)) -> (RA == 0) | (RA == RT) + case (Ldux(RT,RA,RB)) -> (RA == 0) | (RA == RT) + case (Stbu(RS,RA,D)) -> (RA == 0) + case (Stbux(RS,RA,RB)) -> (RA == 0) + case (Sthu(RS,RA,RB)) -> (RA == 0) + case (Sthux(RS,RA,RB)) -> (RA == 0) + case (Stwu(RS,RA,D)) -> (RA == 0) + case (Stwux(RS,RA,RB)) -> (RA == 0) + case (Stdu(RS,RA,DS)) -> (RA == 0) + case (Stdux(RS,RA,RB)) -> (RA == 0) + case (Lmw(RT,RA,D)) -> (RA == 0) | ((RT <= RA) & (RA <= 31)) + case (Lswi(RT,RA,NB)) -> + let (([|32|]) n) = (if ~(NB == 0) then NB else 32) in + let ceil = + (if (n mod 4) == 0 + then n quot 4 else (n quot 4) + 1) in + (RT <= RA) & (RA <= ((bit[5]) (((bit[5]) (RT + ceil)) - 1))) + (* Can't read XER at the time meant, so will need to rethink *) + (* case (Lswx(RT,RA,RB)) -> + let (([|32|]) n) = (XER[57..63]) in + let ceil = + (if (n mod 4 == 0) + then n quot 4 else (n quot 4) + 1) in + let ((bit[5]) upper_bound) = (RT + ceil) in + (RT <= RA & RA <= upper_bound) | + (RT <= RB & RB <= upper_bound) | + (RT == RA) | (RT == RB)*) +(*Floating point instructions*) +(* case (Lfsu(FRT,RA,D)) -> (RA == 0) + case (Lfsux(FRT,RA,RB)) -> (RA == 0) + case (Lfdu(FRT,RA,D)) -> (RA == 0) + case (Lfdux(FRT,RA,RB)) -> (RA == 0) + case (Stfsu(FRS,RA,D)) -> (RA == 0) + case (Stfsux(FRS,RA,RB)) -> (RA == 0) + case (Stfdu(FRS,D,RA)) -> (RA == 0) + case (Stfdux(FRS,RA,RB)) -> (RA == 0) + case (Lfdp(FRTp,RA,DS)) -> (FRTp mod 2 == 1) + case (Stfdp(FRSp,RA,DS)) -> (FRSp mod 2 == 1) + case (Lfdpx(FRTp,RA,RB)) -> (FRTp mod 2 == 1) + case (Stfdpx(FRSp,RA,RB)) -> (FRSp mod 2 == 1)*) + case (Lq(RTp,RA,DQ,Pt)) -> ((RTp mod 2 ==1) | RTp == RA) + case (Stq(RSp,RA,RS)) -> (RSp mod 2 == 1) + case (Mtspr(RS, spr)) -> + ~ ((spr == 1) | (spr == 8) | (spr == 9) | (spr == 256) | + (spr == 512) | (spr == 896) | (spr == 898)) +(*One of these causes a stack overflow error, don't want to debug why now*) + (*case (Mfspr(RT, spr)) -> + ~ ((spr == 1) | (spr == 8) | (spr == 9) | (spr == 136) | + (spr == 256) | (spr == 259) | (spr == 260) | (spr == 261) | + (spr == 262) | (spr == 263) | (spr == 268) | (spr == 268) | + (spr == 269) | (spr == 512) | (spr == 526) | (spr == 526) | + (spr == 527) | (spr == 896) | (spr == 898)) + case (Se_illegal) -> true + case (E_lhau(RT,RA,D8)) -> (RA == 0 | RA == RT) + case (E_Lhzu(RT,RA,D8)) -> (RA == 0 | RA == RT) + case (E_lwzu(RT,RA,D8)) -> (RA == 0 | RA == RT) + case (E_stbu(RS,RA,D8)) -> (RA == 0) + case (E_sthu(RS,RA,D8)) -> (RA == 0) + case (E_stwu(RS,RA,D8)) -> (RA == 0) + case (E_lmw(RT,RA,D8)) -> (RT <= RA & RA <= 31)*) + case _ -> false + } +} + +val ast -> option<ast> effect pure illegal_instructions +function option<ast> illegal_instructions instr = + if (illegal_instructions_pred (instr)) + then None else Some(instr) + +(* old fetch-decode-execute *) +(*function unit fde () = { + NIA := CIA + 4; + instr := decode(MEMr(CIA, 4)); + instr := supported_instructions(instr); + execute(instr); + CIA := NIA; +}*) diff --git a/old/power/power_extras.lem b/old/power/power_extras.lem new file mode 100644 index 00000000..b126aced --- /dev/null +++ b/old/power/power_extras.lem @@ -0,0 +1,96 @@ +open import Pervasives_extra +open import Interp_ast +open import Interp_interface +open import Sail_impl_base +open import Interp_inter_imp +import Set_extra + +let rec countLeadingZeros_helper bits = + match bits with + | (Interp_ast.V_lit (L_aux L_zero _))::bits -> + let (n,loc) = match countLeadingZeros_helper bits with + | (Interp_ast.V_lit (L_aux (L_num n) loc)) -> (n,loc) + | _ -> failwith "countLeadingZeros_helper: unexpected value" end in + Interp_ast.V_lit (L_aux (L_num (n+1)) loc) + | _ -> Interp_ast.V_lit (L_aux (L_num 0) Interp_ast.Unknown) +end +let rec countLeadingZeros e = + match e with + | Interp_ast.V_tuple v -> + match v with + | [Interp_ast.V_track v r;Interp_ast.V_track v2 r2] -> + Interp.taint (countLeadingZeros (Interp_ast.V_tuple [v;v2])) (r union r2) + | [Interp_ast.V_track v r;v2] -> Interp.taint (countLeadingZeros (Interp_ast.V_tuple [v;v2])) r + | [v;Interp_ast.V_track v2 r2] -> Interp.taint (countLeadingZeros (Interp_ast.V_tuple [v;v2])) r2 + | [Interp_ast.V_unknown;_] -> Interp_ast.V_unknown + | [_;Interp_ast.V_unknown] -> Interp_ast.V_unknown + | [Interp_ast.V_vector _ _ bits;Interp_ast.V_lit (L_aux (L_num n) _)] -> + countLeadingZeros_helper (snd (List.splitAt (natFromInteger n) bits)) + | _ -> failwith "countLeadingZeros: unexpected value" + end + | _ -> failwith "countLeadingZeros: unexpected value" +end + +(*Power specific external functions*) +let power_externs = [ + ("countLeadingZeroes", countLeadingZeros); +] + +(*All external functions*) +(*let external_functions = Interp_lib.function_map ++ power_externs*) + +(*List of memory functions; needs to be expanded with all of the memory functions needed for PPCMem. + Should probably be expanded into a parameter to mode as with above + *) + +let memory_parameter_transformer mode v = + match v with + | Interp_ast.V_tuple [location;length] -> + let (v,loc_regs) = extern_with_track mode extern_vector_value location in + + match length with + | Interp_ast.V_lit (L_aux (L_num len) _) -> + (v,(natFromInteger len),loc_regs) + | Interp_ast.V_track (Interp_ast.V_lit (L_aux (L_num len) _)) size_regs -> + match loc_regs with + | Nothing -> (v,(natFromInteger len),Just (List.map (fun r -> extern_reg r Nothing) (Set_extra.toList size_regs))) + | Just loc_regs -> + (v,(natFromInteger len),Just (loc_regs++(List.map (fun r -> extern_reg r Nothing) (Set_extra.toList size_regs)))) + end + | _ -> failwith "memory_parameter_transformer: unexpected value" + end + | _ -> failwith "memory_parameter_transformer: unexpected value" + end + +let power_read_memory_functions : memory_reads = + [ ("MEMr'", (MR Read_plain memory_parameter_transformer)); + ("MEMr_reserve'", (MR Read_reserve memory_parameter_transformer)); + ] +let power_memory_writes : memory_writes = [] + (* [ ("MEMw", (MW Write_plain memory_parameter_transformer Nothing)); + ("MEMw_conditional", (MW Write_conditional memory_parameter_transformer + (Just (fun (IState interp_state c) success -> + let v = Interp.V_lit (L_aux (if success then L_one else L_zero) Unknown) in + IState (Interp.add_answer_to_stack interp_state v) c)) + )); + ] *) + +let power_memory_eas : memory_write_eas = + [ ("MEMw_EA", (MEA Write_plain memory_parameter_transformer)); + ("MEMw_EA_cond", (MEA Write_conditional memory_parameter_transformer)) + ] + +let power_memory_vals : memory_write_vals = + [ ("MEMw'", (MV (fun mode v -> Nothing) Nothing)); + ("MEMw_conditional'", (MV (fun mode v -> Nothing) + (Just (fun (IState interp_state c) success -> + let v = Interp_ast.V_lit (L_aux (if success then L_one else L_zero) Unknown) in + IState (Interp.add_answer_to_stack interp_state v) c)))); + ] + +let power_barrier_functions = [ + ("I_Sync", Barrier_Isync); + ("H_Sync", Barrier_Sync); + ("LW_Sync", Barrier_LwSync); + ("EIEIO_Sync", Barrier_Eieio); +] diff --git a/old/power/power_extras_embed.lem b/old/power/power_extras_embed.lem new file mode 100644 index 00000000..c83a87a7 --- /dev/null +++ b/old/power/power_extras_embed.lem @@ -0,0 +1,50 @@ +open import Pervasives +open import Sail_impl_base +open import Sail_values +open import Prompt + +val MEMr' : (vector bitU * integer) -> M (vector bitU) +val MEMr_reserve' : (vector bitU * integer) -> M (vector bitU) + +let MEMr' (addr,size) = read_mem true Read_plain addr size +let MEMr_reserve' (addr,size) = read_mem true Read_reserve addr size + + +val MEMw_EA : (vector bitU * integer) -> M unit +val MEMr_EA_cond : (vector bitU * integer) -> M unit + +let MEMw_EA (addr,size) = write_mem_ea Write_plain addr size +let MEMw_EA_cond (addr,size) = write_mem_ea Write_conditional addr size + + +val MEMw' : (vector bitU * integer * vector bitU) -> M unit +val MEMw_conditional' : (vector bitU * integer * vector bitU) -> M bitU + +let MEMw' (_,_,value) = write_mem_val value >>= fun _ -> return () +let MEMw_conditional' (_,_,value) = write_mem_val value >>= fun b -> return (bool_to_bitU b) + + +val I_Sync : unit -> M unit +val H_Sync : unit -> M unit +val LW_Sync : unit -> M unit +val EIEIO_Sync : unit -> M unit + +let I_Sync () = barrier Barrier_Isync +let H_Sync () = barrier Barrier_Sync +let LW_Sync () = barrier Barrier_LwSync +let EIEIO_Sync () = barrier Barrier_Eieio + +let recalculate_dependency () = footprint + +let trap () = exit "error" +(* this needs to change, but for that we'd have to make the type checker know about trap + * as an effect *) + +val countLeadingZeroes : vector bitU * integer -> integer +let countLeadingZeroes (Vector bits _ _ ,n) = + let (_,bits) = List.splitAt (natFromInteger n) bits in + integerFromNat (List.length (takeWhile ((=) B0) bits)) + + +let duplicate (bit,length) = + Vector (List.replicate (natFromInteger length) bit) 0 true diff --git a/old/power/power_extras_embed_sequential.lem b/old/power/power_extras_embed_sequential.lem new file mode 100644 index 00000000..4ec33151 --- /dev/null +++ b/old/power/power_extras_embed_sequential.lem @@ -0,0 +1,50 @@ +open import Pervasives +open import Sail_impl_base +open import Sail_values +open import State + +val MEMr' : (vector bitU * integer) -> M (vector bitU) +val MEMr_reserve' : (vector bitU * integer) -> M (vector bitU) + +let MEMr' (addr,size) = read_mem true Read_plain addr size +let MEMr_reserve' (addr,size) = read_mem true Read_reserve addr size + + +val MEMw_EA : (vector bitU * integer) -> M unit +val MEMr_EA_cond : (vector bitU * integer) -> M unit + +let MEMw_EA (addr,size) = write_mem_ea Write_plain addr size +let MEMw_EA_cond (addr,size) = write_mem_ea Write_conditional addr size + + +val MEMw' : (vector bitU * integer * vector bitU) -> M unit +val MEMw_conditional' : (vector bitU * integer * vector bitU) -> M bitU + +let MEMw' (_,_,value) = write_mem_val value >>= fun _ -> return () +let MEMw_conditional' (_,_,value) = write_mem_val value >>= fun b -> return (bool_to_bitU b) + + +val I_Sync : unit -> M unit +val H_Sync : unit -> M unit +val LW_Sync : unit -> M unit +val EIEIO_Sync : unit -> M unit + +let I_Sync () = barrier Barrier_Isync +let H_Sync () = barrier Barrier_Sync +let LW_Sync () = barrier Barrier_LwSync +let EIEIO_Sync () = barrier Barrier_Eieio + +let recalculate_dependency () = footprint + +let trap () = exit "error" +(* this needs to change, but for that we'd have to make the type checker know about trap + * as an effect *) + +val countLeadingZeroes : vector bitU * integer -> integer +let countLeadingZeroes (Vector bits _ _ ,n) = + let (_,bits) = List.splitAt (natFromInteger n) bits in + integerFromNat (List.length (takeWhile ((=) B0) bits)) + + +let duplicate (bit,length) = + Vector (List.replicate (natFromInteger length) bit) 0 true diff --git a/old/power/power_regfp.sail b/old/power/power_regfp.sail new file mode 100644 index 00000000..1f421186 --- /dev/null +++ b/old/power/power_regfp.sail @@ -0,0 +1,1483 @@ +(*========================================================================*) +(* *) +(* Copyright (c) 2015-2017 Gabriel Kerneis, Susmit Sarkar, Kathyrn Gray *) +(* Copyright (c) 2015-2017 Peter Sewell *) +(* All rights reserved. *) +(* *) +(* This software was developed by the University of Cambridge Computer *) +(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) +(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in *) +(* the documentation and/or other materials provided with the *) +(* distribution. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) +(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) +(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) +(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) +(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) +(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) +(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) +(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) +(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) +(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) +(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) +(* SUCH DAMAGE. *) +(*========================================================================*) + +let (vector <0, 32, inc, string >) GPRs = + [ "GPR0", "GPR1", "GPR2", "GPR3", "GPR4", "GPR5", "GPR6", "GPR7", "GPR8", "GPR9", "GPR10", + "GPR11", "GPR12", "GPR13", "GPR14", "GPR15", "GPR16", "GPR17", "GPR18", "GPR19", "GPR20", + "GPR21", "GPR22", "GPR23", "GPR24", "GPR25", "GPR26", "GPR27", "GPR28", "GPR29", "GPR30", "GPR31" + ] + +let (vector <0, 1024, inc, string >) SPRs = + [ 1="XER", 8="LR", 9="CTR"(*, 256=VRSAVE (*32 bit, so not 64, caught by type checker at last*)*), 259="SPRG3", 260="SPRG4", 261="SPRG5", 262="SPRG6", 263="SPRG7" + ] + +let (vector <0, 1024, inc, string >) DCRs = + [ 0="DCR0", 1="DCR1" ; default=undefined] + +function nat length_spr i = switch i { + case 1 -> 64 + case 8 -> 64 + case 9 -> 64 + case 259 -> 64 + case 260 -> 64 + case 261 -> 64 + case 262 -> 64 + case 263 -> 64 +} + +let CIA_fp = RFull("CIA") +let NIA_fp = RFull("NIA") +let mode64bit_fp = RFull("mode64bit") +let bigendianmode_fp = RFull("bigendianmode") + +val ast -> (regfps,regfps,regfps,niafps,diafp,instruction_kind) effect {rreg} initial_analysis +function (regfps,regfps,regfps,niafps,diafp,instruction_kind) initial_analysis (instr) = { + iR := [|| ||]; + oR := [|| ||]; + aR := [|| ||]; + ik := IK_simple; + Nias := [|| NIAFP_successor ||]; + Dia := DIAFP_none; + switch instr { + case (B (LI, AA, LK)) -> { + oR := NIA_fp :: oR; + if AA then iR := CIA_fp :: iR; + if LK then oR := RFull("LR") :: oR; + (bit[64]) nia' := if AA then EXTS(LI : 0b00) else CIA + EXTS(LI : 0b00); + Nias := [|| NIAFP_concrete_address(nia') ||]; + ik := IK_branch + } + case (Bc (BO, BI, BD, AA, LK)) -> { + iR := mode64bit_fp :: iR; + iR := RFull("CTR") :: iR; + if ~(BO[2]) then oR := RFull("CTR") :: oR; + iR := RSliceBit("CR",BI + 32) :: iR; + (* TODO: actually whether CIA is read and NIA written depends on runtime data *) + (* if ctr_ok .. *) + oR := NIA_fp :: oR; + if AA then iR := CIA_fp :: iR; + Nias := [|| NIAFP_successor, NIAFP_concrete_address(if AA then EXTS(BD : 0b00) else CIA + EXTS(BD : 0b00)) ||]; + if LK then {oR := RFull("LR") :: oR; iR := CIA_fp :: iR}; + ik := IK_branch + } + case (Bclr (BO, BI, BH, LK)) -> { + iR := mode64bit_fp :: iR; + iR := RFull("CTR") :: iR; + if ~(BO[2]) then oR := RFull("CTR") :: oR; + iR := RSliceBit("CR",BI + 32) :: iR; + (* TODO: actually whether LR is read, NIA written depends on runtime data *) + (* if ctr_ok .. *) iR := RSlice("LR",0,61) :: iR; + oR := NIA_fp :: oR; + Nias := [|| NIAFP_successor, NIAFP_indirect_address ||]; + if LK then {oR := RFull("LR") :: oR; iR := CIA_fp :: iR;}; + ik := IK_branch; + } + case (Bcctr (BO, BI, BH, LK)) -> { + iR := RSliceBit("CR",BI + 32) :: iR; + (* TODO: actually whether CTR is read and NIA written depends on runtime data *) + (* if cond_ok *) iR := RSlice("CTR",0,61) :: iR; + oR := NIA_fp :: oR; + Nias := [|| NIAFP_successor, NIAFP_indirect_address ||]; + if LK then {oR := RFull("LR") :: oR; iR := CIA_fp :: iR;}; + ik := IK_branch; + } + case (Crand (BT, BA, BB)) -> { + iR := RSliceBit("CR",BA + 32) :: RSliceBit("CR",BB + 32) :: iR; + oR := RSliceBit("CR",BT + 32) :: oR; + } + case (Crnand (BT, BA, BB)) -> { + iR := RSliceBit("CR",BA + 32) :: RSliceBit("CR",BB + 32) :: iR; + oR := RSliceBit("CR",BT + 32) :: oR; + } + case (Cror (BT, BA, BB)) -> { + iR := RSliceBit("CR",BA + 32) :: RSliceBit("CR",BB + 32) :: iR; + oR := RSliceBit("CR",BT + 32) :: oR; + } + case (Crxor (BT, BA, BB)) -> { + iR := RSliceBit("CR",BA + 32) :: RSliceBit("CR",BB + 32) :: iR; + oR := RSliceBit("CR",BT + 32) :: oR; + } + case (Crnor (BT, BA, BB)) -> { + iR := RSliceBit("CR",BA + 32) :: RSliceBit("CR",BB + 32) :: iR; + oR := RSliceBit("CR",BT + 32) :: oR; + } + case (Creqv (BT, BA, BB)) -> { + iR := RSliceBit("CR",BA + 32) :: RSliceBit("CR",BB + 32) :: iR; + oR := RSliceBit("CR",BT + 32) :: oR; + } + case (Crandc (BT, BA, BB)) -> { + iR := RSliceBit("CR",BA + 32) :: RSliceBit("CR",BB + 32) :: iR; + oR := RSliceBit("CR",BT + 32) :: oR; + } + case (Crorc (BT, BA, BB)) -> { + iR := RSliceBit("CR",BA + 32) :: RSliceBit("CR",BB + 32) :: iR; + oR := RSliceBit("CR",BT + 32) :: oR; + } + case (Mcrf (BF, BFA)) -> { + iR := RSlice("CR",4 * BFA + 32,4 * BFA + 35) :: iR; + oR := RSlice("CR",4 * BF + 32,4 * BF + 35) :: oR; + } + case (Sc (LEV)) -> { + (* fake test end instruction *) + (); + } + case (Scv (LEV)) -> () + case (Lbz (RT, RA, D)) -> { + if RA == 0 then () else iR := (RFull(GPRs[RA])) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lbzx (RT, RA, RB)) -> { + if RA == 0 then () else iR := (RFull(GPRs[RA])) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lbzu (RT, RA, D)) -> { + iR := RFull(GPRs[RA]) :: iR; + aR := iR; + oR := RFull(GPRs[RA]) :: RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lbzux (RT, RA, RB)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RA]) :: RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lhz (RT, RA, D)) -> { + if RA == 0 then () else iR := (RFull(GPRs[RA])) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lhzx (RT, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lhzu (RT, RA, D)) -> { + iR := RFull(GPRs[RA]) :: iR; + aR := iR; + oR := RFull(GPRs[RA]) :: RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lhzux (RT, RA, RB)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RA]) :: RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lha (RT, RA, D)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lhax (RT, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lhau (RT, RA, D)) -> { + iR := RFull(GPRs[RA]) :: iR; + aR := iR; + oR := RFull(GPRs[RA]) :: RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lhaux (RT, RA, RB)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RA]) :: RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lwz (RT, RA, D)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lwzx (RT, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lwzu (RT, RA, D)) -> { + iR := RFull(GPRs[RA]) :: iR; + aR := iR; + oR := RFull(GPRs[RA]) :: RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lwzux (RT, RA, RB)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RA]) :: RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lwa (RT, RA, DS)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lwax (RT, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Lwaux (RT, RA, RB)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RA]) :: RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Ld (RT, RA, DS)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Ldx (RT, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Ldu (RT, RA, DS)) -> { + iR := RFull(GPRs[RA]) :: iR; + aR := iR; + oR := RFull(GPRs[RA]) :: RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Ldux (RT, RA, RB)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RA]) :: RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Stb (RS, RA, D)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + iR := RSlice(GPRs[RS],56,63) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Stbx (RS, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + iR := RSlice(GPRs[RS],56,63) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Stbu (RS, RA, D)) -> { + iR := RFull(GPRs[RA]) :: iR; + aR := iR; + iR := RSlice(GPRs[RS],56,63) :: iR; + oR := RFull(GPRs[RA]) :: oR; + ik := IK_mem_write(Write_plain); + } + case (Stbux (RS, RA, RB)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + aR := iR; + iR := RSlice(GPRs[RS],56,63) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Sth (RS, RA, D)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + iR := RSlice(GPRs[RS],48,63) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Sthx (RS, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + iR := RFull(GPRs[RB]) :: RSlice(GPRs[RS],48,63) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Sthu (RS, RA, D)) -> { + iR := RFull(GPRs[RA]) :: iR; + aR := iR; + oR := RFull(GPRs[RA]) :: oR; + iR := RSlice(GPRs[RS],48,63) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Sthux (RS, RA, RB)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + aR := iR; + iR := RSlice(GPRs[RS],48,63) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Stw (RS, RA, D)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + iR := RSlice(GPRs[RS],32,63) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Stwx (RS, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + iR := RSlice(GPRs[RS],32,63) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Stwu (RS, RA, D)) -> { + iR := RFull(GPRs[RA]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + aR := iR; + iR := RSlice(GPRs[RS],32,63) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Stwux (RS, RA, RB)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + aR := iR; + iR := RSlice(GPRs[RS],32,63) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Std (RS, RA, DS)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + iR := RFull(GPRs[RS]) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Stdx (RS, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + iR := RFull(GPRs[RS]) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Stdu (RS, RA, DS)) -> { + iR := RFull(GPRs[RA]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + aR := iR; + iR := RFull(GPRs[RS]) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Stdux (RS, RA, RB)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + aR := iR; + iR := RFull(GPRs[RS]) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Lq (RTp, RA, DQ, PT)) -> { + iR := bigendianmode_fp :: iR; + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + oR := RFull(GPRs[RTp]) :: RFull(GPRs[RTp + 1]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Stq (RSp, RA, DS)) -> { + iR := bigendianmode_fp :: iR; + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + iR := RFull(GPRs[RSp]) :: RFull(GPRs[RSp + 1]) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Lhbrx (RT, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Sthbrx (RS, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + iR := RSlice(GPRs[RS],56,63) :: RSlice(GPRs[RS],48,55) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Lwbrx (RT, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Stwbrx (RS, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + iR := RSlice(GPRs[RS],56,63) :: RSlice(GPRs[RS],48,55) :: RSlice(GPRs[RS],40,47) :: RSlice(GPRs[RS],32,39) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Ldbrx (RT, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_plain); + } + case (Stdbrx (RS, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + iR := RSlice(GPRs[RS],56,63) :: RSlice(GPRs[RS],48,55) :: RSlice(GPRs[RS],40,47) :: RSlice(GPRs[RS],32,39) :: RSlice(GPRs[RS],24,31) :: RSlice(GPRs[RS],16,23) :: RSlice(GPRs[RS],8,15) :: RSlice(GPRs[RS],0,7) :: iR; + ik := IK_mem_write(Write_plain); + } + case (Lmw (RT, RA, D)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + i := 0; + aR := iR; + foreach (r from RT to 31 by 1 in inc) { + oR := RFull(GPRs[r]) :: oR; + i := i + 32 + }; + ik := IK_mem_read(Read_plain); + } + case (Stmw (RS, RA, D)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + i := 0; + foreach (r from RS to 31 by 1 in inc) { + iR := RSlice(GPRs[r],32,63) :: iR; + i := i + 32 + }; + ik := IK_mem_write(Write_plain); + } + case (Lswi (RT, RA, NB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + ([|31|]) r := 0; + r := RT - 1; + j := 0; + i := 32; + foreach (n from (if NB == 0 then 32 else NB) to 1 by 1 in dec) { + if i == 32 then { + r := ([|31|]) (r + 1) mod 32; + oR := RFull(GPRs[r]) :: oR; + }; + oR := RSlice(GPRs[r],i,i + 7) :: oR; + j := j + 8; + i := i + 8; + if i == 64 then i := 32; + }; + ik := IK_mem_read(Read_plain); + } + case (Lswx (RT, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: RSlice("XER",57,63) :: iR; + aR := iR; + (* as long as XER[57 .. 63] is unknown all registers could be written to *) + foreach (r from 0 to 31 by 1 in inc) {oR := RFull(GPRs[r]) :: oR}; + ik := IK_mem_read(Read_plain); + } + case (Stswi (RS, RA, NB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + aR := iR; + ([|31|]) r := 0; + r := RS - 1; + j := 0; + i := 32; + foreach (n from (if NB == 0 then 32 else NB) to 1 by 1 in dec) { + if i == 32 then r := ([|32|]) (r + 1) mod 32; + iR := RSlice(GPRs[r],i,i + 7) :: iR; + j := j + 8; + i := i + 8; + if i == 64 then i := 32 + }; + ik := IK_mem_write(Write_plain); + } + case (Stswx (RS, RA, RB)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + ([|31|]) r := 0; + iR := RFull(GPRs[RB]) :: RSlice("XER",57,63) :: iR; + aR := iR; + r := RS - 1; + i := 32; + ([|128|]) n_top := 0b1111111; (* maximal XER[57 .. 63]; *) + j := 0; + foreach (n from n_top to 1 by 1 in dec) { + if i == 32 then r := ([|32|]) (r + 1) mod 32; + iR := RSlice(GPRs[r],i,i + 7) :: iR; + i := i + 8; + j := j + 8; + if i == 64 then i := 32 + }; + ik := IK_mem_write(Write_plain); + } + case (Addi (RT, RA, SI)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + } + case (Addis (RT, RA, SI)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + } + case (Add (RT, RA, RB, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Subf (RT, RA, RB, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Addic (RT, RA, SI)) -> { + iR := RFull(GPRs[RA]) :: iR; + oR := RFull(GPRs[RT]) :: RField("XER","CA") :: oR; + } + case (AddicDot (RT, RA, SI)) -> { + iR := RFull(GPRs[RA]) :: iR; + oR := RFull(GPRs[RT]) :: RField("XER","CA") :: oR; + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + case (Subfic (RT, RA, SI)) -> { + iR := RFull(GPRs[RA]) :: iR; + oR := RFull(GPRs[RT]) :: RField("XER","CA") :: oR; + } + case (Addc (RT, RA, RB, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RField("XER","CA") :: oR; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Subfc (RT, RA, RB, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RField("XER","CA") :: oR; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Adde (RT, RA, RB, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + iR := RField("XER","CA") :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RField("XER","CA") :: oR; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Subfe (RT, RA, RB, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + iR := RField("XER","CA") :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RField("XER","CA") :: oR; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Addme (RT, RA, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RField("XER","CA") :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RField("XER","CA") :: oR; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Subfme (RT, RA, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RField("XER","CA") :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RField("XER","CA") :: oR; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Addze (RT, RA, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RField("XER","CA") :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RField("XER","CA") :: oR; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Subfze (RT, RA, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RField("XER","CA") :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RField("XER","CA") :: oR; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Neg (RT, RA, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Mulli (RT, RA, SI)) -> { + iR := RFull(GPRs[RA]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + } + case (Mullw (RT, RA, RB, OE, Rc)) -> { + iR := RSlice(GPRs[RA],32,63) :: RSlice(GPRs[RB],32,63) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Mulhw (RT, RA, RB, Rc)) -> { + iR := RSlice(GPRs[RA],32,63) :: RSlice(GPRs[RB],32,63) :: iR; + oR := RSlice(GPRs[RT],32,63) :: RSlice(GPRs[RT],0,31) :: oR; + if Rc then { + iR := mode64bit_fp :: iR; + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Mulhwu (RT, RA, RB, Rc)) -> { + iR := RSlice(GPRs[RA],32,63) :: RSlice(GPRs[RB],32,63) :: iR; + oR := RSlice(GPRs[RT],32,63) :: RSlice(GPRs[RT],0,31) :: oR; + if Rc then { + iR := mode64bit_fp :: iR; + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Divw (RT, RA, RB, OE, Rc)) -> { + iR := RSlice(GPRs[RA],32,63) :: RSlice(GPRs[RB],32,63) :: iR; + oR := RSlice(GPRs[RT],32,63) :: RSlice(GPRs[RT],0,31) :: oR; + if Rc then { + iR := mode64bit_fp :: iR; + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Divwu (RT, RA, RB, OE, Rc)) -> { + iR := RSlice(GPRs[RA],32,63) :: RSlice(GPRs[RB],32,63) :: iR; + oR := RSlice(GPRs[RT],32,63) :: RSlice(GPRs[RT],0,31) :: oR; + if Rc then { + iR := mode64bit_fp :: iR; + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Divwe (RT, RA, RB, OE, Rc)) -> { + iR := RSlice(GPRs[RA],32,63) :: RSlice(GPRs[RB],32,63) :: iR; + oR := RSlice(GPRs[RT],32,63) :: RSlice(GPRs[RT],0,31) :: oR; + if Rc then { + iR := mode64bit_fp :: iR; + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Divweu (RT, RA, RB, OE, Rc)) -> { + iR := RSlice(GPRs[RA],32,63) :: RSlice(GPRs[RB],32,63) :: iR; + oR := RSlice(GPRs[RT],32,63) :: RSlice(GPRs[RT],0,31) :: oR; + if Rc then { + iR := mode64bit_fp :: iR; + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Mulld (RT, RA, RB, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Mulhd (RT, RA, RB, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Mulhdu (RT, RA, RB, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Divd (RT, RA, RB, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Divdu (RT, RA, RB, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Divde (RT, RA, RB, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Divdeu (RT, RA, RB, OE, Rc)) -> { + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + if OE then { + iR := RField("XER","SO") :: iR; (* set_SO_OV *) + oR := RField("XER","OV") :: RField("XER","SO") :: oR; (* set_SO_OV *) + } + } + case (Cmpi (BF, L, RA, SI)) -> { + iR := (if L == 0 then RSlice(GPRs[RA],32,63) else RFull(GPRs[RA])) :: iR; + iR := RField("XER","SO") :: iR; + oR := RSlice("CR",4 * BF + 32,4 * BF + 35) :: oR; + } + case (Cmp (BF, L, RA, RB)) -> { + if L == 0 then + iR := RSlice(GPRs[RA],32,63) :: RSlice(GPRs[RB],32,63) :: iR + else iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + iR := RField("XER","SO") :: iR; + oR := RSlice("CR",4 * BF,4 * BF + 35) :: oR; + } + case (Cmpli (BF, L, RA, UI)) -> { + iR := (if L == 0 then RSlice(GPRs[RA],32,63) else RFull(GPRs[RA])) :: iR; + iR := RField("XER","SO") :: iR; + oR := RSlice("CR",4 * BF + 32,4 * BF + 35) :: oR; + } + case (Cmpl (BF, L, RA, RB)) -> { + if L == 0 then + iR := RSlice(GPRs[RA],32,63) :: RSlice(GPRs[RB],32,63) :: iR + else + iR := RFull(GPRs[RA]) :: RFull(GPRs[RB]) :: iR; + iR := RField("XER","SO") :: iR; + oR := RSlice("CR",4 * BF + 32,4 * BF + 35) :: oR; + } +(* case (Twi (TO, RA, SI)) -> { + iR := RSlice(GPRs[RA],32,63) :: iR; + } + case (Tw (TO, RA, RB)) -> { + iR := RSlice(GPRs[RA],32,63) :: RSlice(GPRs[RB],32,63) :: iR; + } + case (Tdi (TO, RA, SI)) -> () + case (Td (TO, RA, RB)) -> () *) + case (Isel (RT, RA, RB, BC)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RSliceBit("CR",BC + 32) :: iR; + iR := RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + } + case (Andi (RS, RA, UI)) -> { + iR := RFull(GPRs[RS]) :: RField("XER","SO") :: iR; + oR := RFull(GPRs[RA]) :: oR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + case (Andis (RS, RA, UI)) -> { + iR := RFull(GPRs[RS]) :: RField("XER","SO") :: iR; + oR := RFull(GPRs[RA]) :: oR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + case (Ori (RS, RA, UI)) -> { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + } + case (Oris (RS, RA, UI)) -> { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + } + case (Xori (RS, RA, UI)) -> { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + } + case (Xoris (RS, RA, UI)) -> { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + } + case (And (RS, RA, RB, Rc)) -> { + iR := RFull(GPRs[RS]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + } + case (Xor (RS, RA, RB, Rc)) -> { + if RS == RB then { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + } + else { + iR := RFull(GPRs[RS]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + }; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + } + case (Nand (RS, RA, RB, Rc)) -> { + iR := RFull(GPRs[RS]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + } + case (Or (RS, RA, RB, Rc)) -> { + iR := RFull(GPRs[RS]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + } + case (Nor (RS, RA, RB, Rc)) -> { + iR := RFull(GPRs[RS]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + } + case (Eqv (RS, RA, RB, Rc)) -> { + iR := RFull(GPRs[RS]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + } + case (Andc (RS, RA, RB, Rc)) -> { + iR := RFull(GPRs[RS]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + } + case (Orc (RS, RA, RB, Rc)) -> { + iR := RFull(GPRs[RS]) :: RFull(GPRs[RB]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + } + case (Extsb (RS, RA, Rc)) -> { + iR := RSliceBit(GPRs[RS],56) :: iR; + iR := RSlice(GPRs[RS],56,63) :: iR; + oR := RSlice(GPRs[RA],56,63) :: oR; + oR := RSlice(GPRs[RA],0,55) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + } + case (Extsh (RS, RA, Rc)) -> { + iR := RSliceBit(GPRs[RS],48) :: iR; + iR := RSlice(GPRs[RS],48,63) :: iR; + oR := RSlice(GPRs[RA],48,63) :: oR; + oR := RSlice(GPRs[RA],0,47) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + } + case (Cntlzw (RS, RA, Rc)) -> { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + } + } + case (Cmpb (RS, RA, RB)) -> { + foreach (n from 0 to 7 by 1 in inc) { + iR := RSlice(GPRs[RS],8 * n,8 * n + 7) :: RSlice(GPRs[RB],8 * n,8 * n + 7) :: iR; + oR := RSlice(GPRs[RA],8 * n,8 * n + 7) :: oR; + } + } + case (Popcntb (RS, RA)) -> { + foreach (i from 0 to 7 by 1 in inc) { + foreach (j from 0 to 7 by 1 in inc) iR := RSliceBit(GPRs[RS],i * 8 + j) :: iR; + oR := RSlice(GPRs[RA],i * 8,i * 8 + 7) :: oR; + } + } + case (Popcntw (RS, RA)) -> { + foreach (i from 0 to 1 by 1 in inc) { + foreach (j from 0 to 31 by 1 in inc) iR := RSliceBit(GPRs[RS],i * 32 + j) :: iR; + oR := RSlice(GPRs[RA],i * 32,i * 32 + 31) :: oR; + } + } + case (Prtyd (RS, RA)) -> { + foreach (i from 0 to 7 by 1 in inc) iR := RSliceBit(GPRs[RS],i * 8 + 7) :: iR; + oR := RFull(GPRs[RA]) :: oR; + } + case (Prtyw (RS, RA)) -> { + foreach (i from 0 to 3 by 1 in inc) iR := RSliceBit(GPRs[RS],i * 8 + 7) :: iR; + foreach (i from 4 to 7 by 1 in inc) iR := RSliceBit(GPRs[RS],i * 8 + 7) :: iR; + oR := RSlice(GPRs[RA],0,31) :: oR; + oR := RSlice(GPRs[RA],32,63) :: oR; + } + case (Extsw (RS, RA, Rc)) -> { + iR := RSliceBit(GPRs[RS],32) :: iR; + iR := RSlice(GPRs[RS],32,63) :: iR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RFull(GPRs[RA]) :: oR; + } + case (Cntlzd (RS, RA, Rc)) -> { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Popcntd (RS, RA)) -> { + foreach (i from 0 to 63 by 1 in inc) iR := RSliceBit(GPRs[RS],i) :: iR; + oR := RFull(GPRs[RA]) :: oR; + } + (* TODO: here the footprint depends on dynamic data *) + case (Bpermd (RS, RA, RB)) -> { + foreach (i from 0 to 7 by 1 in inc) { + iR := RSlice(GPRs[RS],8 * i,8 * i + 7) :: iR; + iR := RFull(GPRs[RB]) :: iR; (* this is actually only a single bit, *) + (* which one it is depends on the read before *) + oR := RFull(GPRs[RA]) :: oR; + } + } + case (Rlwinm (RS, RA, SH, MB, ME, Rc)) -> { + iR := RSlice(GPRs[RS],32,63) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Rlwnm (RS, RA, RB, MB, ME, Rc)) -> { + iR := RSlice(GPRs[RB],59,63) :: RSlice(GPRs[RS],32,63) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Rlwimi (RS, RA, SH, MB, ME, Rc)) -> { + iR := RSlice(GPRs[RS],32,63) :: iR; + iR := RFull(GPRs[RA]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Rldicl (RS, RA, sh, mb, Rc)) -> { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Rldicr (RS, RA, sh, me, Rc)) -> { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Rldic (RS, RA, sh, mb, Rc)) -> { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Rldcl (RS, RA, RB, mb, Rc)) -> { + iR := RSlice(GPRs[RB],58,63) :: iR; + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Rldcr (RS, RA, RB, me, Rc)) -> { + iR := RSlice(GPRs[RB],58,63) :: iR; + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Rldimi (RS, RA, sh, mb, Rc)) -> { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Slw (RS, RA, RB, Rc)) -> { + iR := RSlice(GPRs[RB],59,63) :: iR; + iR := RSlice(GPRs[RS],32,63) :: iR; + iR := RSliceBit(GPRs[RB],58) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Srw (RS, RA, RB, Rc)) -> { + iR := RSlice(GPRs[RB],59,63) :: iR; + iR := RSlice(GPRs[RS],32,63) :: iR; + iR := RSliceBit(GPRs[RB],58) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Srawi (RS, RA, SH, Rc)) -> { + iR := RSlice(GPRs[RS],32,63) :: iR; + iR := RSliceBit(GPRs[RS],32) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RField("XER","CA") :: oR; + } + case (Sraw (RS, RA, RB, Rc)) -> { + iR := RSlice(GPRs[RB],59,63) :: iR; + iR := RSlice(GPRs[RS],32,63) :: RSliceBit(GPRs[RB],58) :: RSliceBit(GPRs[RS],32) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RField("XER","CA") :: oR; + } + case (Sld (RS, RA, RB, Rc)) -> { + iR := RSlice(GPRs[RB],58,63) :: RFull(GPRs[RS]) :: iR; + iR := RSliceBit(GPRs[RB],57) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Srd (RS, RA, RB, Rc)) -> { + iR := RSlice(GPRs[RB],58,63) :: RFull(GPRs[RS]) :: iR; + iR := RSliceBit(GPRs[RB],57) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + } + case (Sradi (RS, RA, sh, Rc)) -> { + iR := RFull(GPRs[RS]) :: iR; + iR := RSliceBit(GPRs[RS],0) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RField("XER","CA") :: oR; + } + case (Srad (RS, RA, RB, Rc)) -> { + iR := RSlice(GPRs[RB],58,63) :: RFull(GPRs[RS]) :: RSliceBit(GPRs[RB],57) :: RSliceBit(GPRs[RS],0) :: iR; + oR := RFull(GPRs[RA]) :: oR; + if Rc then { + iR := RField("XER","SO") :: iR; + oR := RField("CR","CR0") :: oR; (* set_overflow_cr0 *) + }; + oR := RField("XER","CA") :: oR; + } + case (Cdtbcd (RS, RA)) -> { + foreach (i from 0 to 1 by 1 in inc) { + n := i * 32; + iR := RSlice(GPRs[RS],n + 12,n + 31) :: iR; + oR := RSlice(GPRs[RA],n + 0,n + 31) :: oR; + } + } + case (Cbcdtd (RS, RA)) -> { + foreach (i from 0 to 1 by 1 in inc) { + n := i * 32; + iR := RSlice(GPRs[RS],n + 8,n + 31) :: iR; + oR := RSlice(GPRs[RA],n + 0,n + 31) :: oR; + } + } + case (Addg6s (RT, RA, RB)) -> { + foreach (i from 0 to 15 by 1 in inc) { + iR := RSlice(GPRs[RA],4 * i,63) :: iR; + iR := RSlice(GPRs[RB],4 * i,63) :: iR; + }; + oR := RFull(GPRs[RT]) :: oR; + } + case (Mtspr (RS, spr)) -> { + n := spr[5 .. 9] : spr[0 .. 4]; + if n == 1 then { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull("XER") :: oR; + } + else { + (* the below is debatable: to determine the length of that register, does it + * really need to read the content? *) + iR := RFull(SPRs[n]) ::iR; + if length_spr(n) == 64 then { + iR := RFull(GPRs[RS]) :: iR; + oR := RFull(SPRs[n]) :: oR; + } + else if n == 152 then { + iR := RSlice(GPRs[RS],32,63) :: iR; + oR := RFull("CTRL") :: oR; + } + else (); + } + } + case (Mfspr (RT, spr)) -> { + n := spr[5 .. 9] : spr[0 .. 4]; + iR := RFull(SPRs[n]) :: iR; + oR := RFull(GPRs[RT]) :: oR; + } + case (Mtcrf (RS, FXM)) -> { + iR := RFull("CR") :: RSlice(GPRs[RS],32,63) :: iR; + oR := RFull("CR") :: oR; + } + case (Mfcr (RT)) -> { + iR := RFull("CR") :: iR; + oR := RFull(GPRs[RT]) :: oR; + } + case (Mtocrf (RS, FXM)) -> { + ([|7|]) n := 0; + count := 0; + foreach (i from 0 to 7 by 1 in inc) + if FXM[i] == 1 + then { + n := i; + count := count + 1 + } + else (); + if count == 1 + then { + oR := RSlice("CR",4 * n + 32,4 * n + 35) :: oR; + iR := RSlice(GPRs[RS],4 * n + 32,4 * n + 35) :: iR; + } + else oR := RFull("CR") :: oR; + } + case (Mfocrf (RT, FXM)) -> { + ([|7|]) n := 0; + count := 0; + foreach (i from 0 to 7 by 1 in inc) + if FXM[i] == 1 + then { + n := i; + count := count + 1 + } + else (); + if count == 1 + then { + iR := RSlice("CR",4 * n + 32,4 * n + 35) :: iR; + oR := RFull(GPRs[RT]) :: oR; + } + else oR := RFull(GPRs[RT]) :: oR; + } + case (Mcrxr (BF)) -> { + iR := RSlice("XER",32,35) :: iR; + oR := RSlice("CR",4 * BF + 32,4 * BF + 35) :: RSlice("XER",32,35) :: oR; + } + case (Dlmzb (RS, RA, RB, Rc)) -> () + case (Macchws (RT, RA, RB, OE, Rc)) -> () + case (Macchwu (RT, RA, RB, OE, Rc)) -> () + case (Macchwsu (RT, RA, RB, OE, Rc)) -> () + case (Machhws (RT, RA, RB, OE, Rc)) -> () + case (Machhwu (RT, RA, RB, OE, Rc)) -> () + case (Machhwsu (RT, RA, RB, OE, Rc)) -> () + case (Maclhw (RT, RA, RB, OE, Rc)) -> () + case (Maclhws (RT, RA, RB, OE, Rc)) -> () + case (Maclhwu (RT, RA, RB, OE, Rc)) -> () + case (Maclhwsu (RT, RA, RB, OE, Rc)) -> () + case (Mulchw (RT, RA, RB, Rc)) -> () + case (Mulchwu (RT, RA, RB, Rc)) -> () + case (Mulhhw (RT, RA, RB, Rc)) -> () + case (Mulhhwu (RT, RA, RB, Rc)) -> () + case (Mullhw (RT, RA, RB, Rc)) -> () + case (Mullhwu (RT, RA, RB, Rc)) -> () + case (Nmacchw (RT, RA, RB, OE, Rc)) -> () + case (Nmacchws (RT, RA, RB, OE, Rc)) -> () + case (Nmachhw (RT, RA, RB, OE, Rc)) -> () + case (Nmachhws (RT, RA, RB, OE, Rc)) -> () + case (Nmaclhw (RT, RA, RB, OE, Rc)) -> () + case (Nmaclhws (RT, RA, RB, OE, Rc)) -> () + case (Icbi (RA, RB)) -> () + case (Icbt (CT, RA, RB)) -> () + case (Dcba (RA, RB)) -> () + case (Dcbt (TH, RA, RB)) -> () + case (Dcbtst (TH, RA, RB)) -> () + case (Dcbz (RA, RB)) -> () + case (Dcbst (RA, RB)) -> () + case (Dcbf (L, RA, RB)) -> () + case Isync -> { + ik := IK_barrier(Barrier_Isync); + } + case (Lbarx (RT, RA, RB, EH)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_reserve); + } + case (Lharx (RT, RA, RB, EH)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_reserve); + } + case (Lwarx (RT, RA, RB, EH)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_reserve); + } + case (Stbcx (RS, RA, RB)) -> { + ik := IK_mem_write(Write_conditional); + } + case (Sthcx (RS, RA, RB)) -> { + ik := IK_mem_write(Write_conditional); + } + case (Stwcx (RS, RA, RB)) -> { + ik := IK_mem_write(Write_conditional); + } + case (Ldarx (RT, RA, RB, EH)) -> { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + iR := RFull(GPRs[RB]) :: iR; + aR := iR; + oR := RFull(GPRs[RT]) :: oR; + ik := IK_mem_read(Read_reserve); + } + case (Stdcx (RS, RA, RB)) -> { + ik := IK_mem_write(Write_conditional); + } + case (Sync (L)) -> { + ik := switch L { + case 0b00 -> { IK_barrier(Barrier_Sync) } + case 0b01 -> { IK_barrier(Barrier_LwSync) } + } + } + case Eieio -> { + ik := IK_barrier(Barrier_Eieio) + } + case (Wait (WC)) -> () + }; + (iR,oR,aR,Nias,Dia,ik) +} + +val ast -> (regfps,regfps,regfps,niafps,diafp,instruction_kind) effect {rreg} recalculate_lswx_reg_footprint +(* run when footprint transition is taken, supplying n_top = XER[57 .. 63] as a parameter *) +function (regfps,regfps,regfps,niafps,diafp,instruction_kind) recalculate_lswx_reg_footprint instr = { + (regfps) iR := [|| ||]; + (regfps) oR := [|| ||]; + Nias := [|| NIAFP_successor ||]; + Dia := DIAFP_none; + ik := IK_mem_read(Read_plain); + let (RT,RA,RB) = switch instr {case (Lswx (RT, RA, RB)) -> (RT,RA,RB)} in { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + ([|31|]) r := 0; + iR := RFull(GPRs[RB]) :: RSlice("XER",57,63) :: iR; + aR := iR; + r := RT - 1; + i := 32; + ([|128|]) n_top := XER[57 .. 63]; + if n_top == 0 then + oR := RFull(GPRs[RT]) :: oR + else { + j := 0; + n_r := n_top quot 4; + n_mod := n_top mod 4; + n_r := if n_mod == 0 then n_r else n_r + 1; + foreach (n from n_r to 1 by 1 in dec) { + r := ([|32|]) (r + 1) mod 32; + j := j + 32; + oR := RFull(GPRs[r]) :: oR + } + }; + (iR,oR,aR,Nias,Dia,ik)} +} + +val ast -> (regfps,regfps,regfps,niafps,diafp,instruction_kind) effect {rreg} recalculate_stswx_reg_footprint +(* run when footprint transition is taken, supplying n_top = XER[57 .. 63] as a parameter *) +function (regfps,regfps,regfps,niafps,diafp,instruction_kind) recalculate_stswx_reg_footprint instr = { + (regfps) iR := [|| ||]; + (regfps) oR := [|| ||]; + Nias := [|| NIAFP_successor ||]; + Dia := DIAFP_none; + ik := IK_mem_write(Write_plain); + let (RS,RA,RB) = switch instr {case (Stswx (RS, RA, RB)) -> (RS,RA,RB)} in { + if RA == 0 then () else iR := RFull(GPRs[RA]) :: iR; + ([|31|]) r := 0; + iR := RFull(GPRs[RB]) :: RSlice("XER",57,63) :: iR; + aR := iR; + r := RS - 1; + i := 32; + ([|128|]) n_top := XER[57 .. 63]; + j := 0; + foreach (n from n_top to 1 by 1 in dec) { + if i == 32 then r := ([|32|]) (r + 1) mod 32; + iR := RSlice(GPRs[r],i,i + 7) :: iR; + i := i + 8; + j := j + 8; + if i == 64 then i := 32 + }; + ik := IK_mem_write(Write_plain); + (iR,oR,aR,Nias,Dia,ik)} +} diff --git a/old/x86/Makefile b/old/x86/Makefile new file mode 100644 index 00000000..0c6e830e --- /dev/null +++ b/old/x86/Makefile @@ -0,0 +1,20 @@ +SAIL=../src/sail.native +LEM:=../../lem/lem + +SOURCES=../lib/regfp.sail x64.sail + +all: x86.lem x86.ml x86_embed.lem + +x86.lem: + $(SAIL) -lem_ast -o x86 $(SOURCES) + +x86.ml: x86.lem ../src/lem_interp/interp_ast.lem + $(LEM) -ocaml -lib ../src/lem_interp/ $< + +x86_embed.lem: $(SOURCES) +# also generates x86_embed_sequential.lem, x86_embed_types.lem, x86_toFromInterp.lem + $(SAIL) -lem -lem_lib X86_extras_embed -o x86 $(SOURCES) + +clean: + rm -f x86.lem x86.ml + rm -f x86_embed*.lem x86_toFromInterp.lem diff --git a/old/x86/gen/ast.hgen b/old/x86/gen/ast.hgen new file mode 100644 index 00000000..83488eda --- /dev/null +++ b/old/x86/gen/ast.hgen @@ -0,0 +1,26 @@ +| `X86BINOP of bool * x86Binop * x86Size * x86Dest_src +| `X86BITOP of bool * x86Bitop * x86Size * x86Bit_offset +| `X86CALL of x86Imm_rm +| `X86CLC +| `X86CMC +| `X86CMPXCHG of bool * x86Size * x86Rm * reg +| `X86DIV of x86Size * x86Rm +| `X86JCC of x86Cond * bit64 +| `X86JMP of x86Rm +| `X86LEA of x86Size * x86Dest_src +| `X86LEAVE +| `X86LOOP of x86Cond * bit64 +| `X86MFENCE +| `X86MONOP of bool * x86Monop * x86Size * x86Rm +| `X86MOV of x86Cond * x86Size * x86Dest_src +| `X86MOVSX of x86Size * x86Dest_src * x86Size +| `X86MOVZX of x86Size * x86Dest_src * x86Size +| `X86MUL of x86Size * x86Rm +| `X86NOP +| `X86POP of x86Rm +| `X86PUSH of x86Imm_rm +| `X86RET of bit64 +| `X86SET of x86Cond * bool * x86Rm +| `X86STC +| `X86XADD of bool * x86Size * x86Rm * reg +| `X86XCHG of bool * x86Size * x86Rm * reg diff --git a/old/x86/gen/fold.hgen b/old/x86/gen/fold.hgen new file mode 100644 index 00000000..df546a13 --- /dev/null +++ b/old/x86/gen/fold.hgen @@ -0,0 +1,26 @@ +| `X86BINOP (_, _, _, ds) -> fold_dest_src ds c +| `X86BITOP (_, _, _, bo) -> fold_bit_offset bo c +| `X86CALL irm -> fold_imm_rm irm c +| `X86CLC -> c +| `X86CMC -> c +| `X86CMPXCHG (_, _, rm, r) -> fold_rm rm (fold_reg r c) +| `X86DIV (_, rm) -> fold_rm rm c +| `X86JCC _ -> c +| `X86JMP rm -> fold_rm rm c +| `X86LEA (_, ds) -> fold_dest_src ds c +| `X86LEAVE -> c +| `X86LOOP _ -> c +| `X86MFENCE -> c +| `X86MONOP (_, _, _, rm) -> fold_rm rm c +| `X86MOV (_, _, ds) -> fold_dest_src ds c +| `X86MOVSX (_, ds, _) -> fold_dest_src ds c +| `X86MOVZX (_, ds, _) -> fold_dest_src ds c +| `X86MUL (_, rm) -> fold_rm rm c +| `X86NOP -> c +| `X86POP rm -> fold_rm rm c +| `X86PUSH irm -> fold_imm_rm irm c +| `X86RET _ -> c +| `X86SET (_, _, rm) -> fold_rm rm c +| `X86STC -> c +| `X86XADD (_, _, rm, r) -> fold_rm rm (fold_reg r c) +| `X86XCHG (_, _, rm, r) -> fold_rm rm (fold_reg r c) diff --git a/old/x86/gen/herdtools_ast_to_shallow_ast.hgen b/old/x86/gen/herdtools_ast_to_shallow_ast.hgen new file mode 100644 index 00000000..c709ee6c --- /dev/null +++ b/old/x86/gen/herdtools_ast_to_shallow_ast.hgen @@ -0,0 +1,28 @@ +| `X86BINOP(locked, binop, sz, dest_src) -> Binop (translate_bool locked, translate_binop binop, translate_size sz, translate_dest_src dest_src) +| `X86BITOP(locked, op, sz, bo) -> Bitop (translate_bool locked, translate_bitop op, translate_size sz, translate_bitoffset bo) +| `X86CALL (imm_rm) -> CALL (translate_imm_rm imm_rm) +| `X86CLC -> CLC +| `X86CMC -> CMC +| `X86CMPXCHG (locked, sz, rm , reg) -> CMPXCHG (translate_bool locked, translate_size sz, translate_rm rm, translate_reg reg) +| `X86DIV (sz, rm) -> X86_DIV (translate_size sz, translate_rm rm) +| `X86StopFetching -> HLT +| `X86JCC (cond, imm64) -> Jcc (translate_cond cond, translate_imm64 imm64) +| `X86JMP (rm) -> JMP (translate_rm rm) +| `X86LEA (sz, dest_src) -> LEA (translate_size sz, translate_dest_src dest_src) +| `X86LEAVE -> LEAVE +| `X86LOOP (cond, imm64) -> LOOP (translate_cond cond, translate_imm64 imm64) +| `X86MFENCE -> MFENCE +| `X86MONOP (locked, monop, sz, rm) -> Monop (translate_bool locked, translate_monop monop, translate_size sz, translate_rm rm) +| `X86MOV (cond, sz, dest_src) -> MOV (translate_cond cond, translate_size sz, translate_dest_src dest_src) +| `X86MOVSX (sz1, dest_src, sz2) -> MOVSX (translate_size sz1, translate_dest_src dest_src, translate_size sz2) +| `X86MOVZX (sz1, dest_src, sz2) -> MOVZX (translate_size sz1, translate_dest_src dest_src, translate_size sz2) +| `X86MUL (sz, rm) -> X86_MUL (translate_size sz, translate_rm rm) +| `X86NOP -> NOP (Nat_big_num.of_int 0) +| `X86POP (rm) -> POP (translate_rm rm) +| `X86PUSH (imm_rm) -> PUSH (translate_imm_rm imm_rm) +| `X86RET (imm64) -> RET (translate_imm64 imm64) +| `X86SET (cond, b, rm) -> SET (translate_cond cond, translate_bool b, translate_rm rm) +| `X86STC -> STC +| `X86XADD (locked, sz, rm, reg) -> XADD (translate_bool locked, translate_size sz, translate_rm rm, translate_reg reg) +| `X86XCHG (locked, sz, rm, reg) -> XCHG (translate_bool locked, translate_size sz, translate_rm rm, translate_reg reg) + diff --git a/old/x86/gen/herdtools_types_to_shallow_types.hgen b/old/x86/gen/herdtools_types_to_shallow_types.hgen new file mode 100644 index 00000000..44e16991 --- /dev/null +++ b/old/x86/gen/herdtools_types_to_shallow_types.hgen @@ -0,0 +1,93 @@ +let is_inc = false + +let translate_bool = function + | true -> Sail_values.B1 + | false -> Sail_values.B0 + +let translate_binop = function + | X86ADD -> X86_Add + | X86OR -> X86_Or + | X86ADC -> X86_Adc + | X86SBB -> X86_Sbb + | X86AND -> X86_And + | X86SUB -> X86_Sub + | X86XOR -> X86_Xor + | X86CMP -> X86_Cmp + | X86ROL -> X86_Rol + | X86ROR -> X86_Ror + | X86RCL -> X86_Rcl + | X86RCR -> X86_Rcr + | X86SHL -> X86_Shl + | X86SHR -> X86_Shr + | X86TEST -> X86_Test + | X86SAR -> X86_Sar + +let translate_bitop = function + | X86Btc -> Btc + | X86Bts -> Bts + | X86Btr -> Btr + +let translate_size = function + | X86S8(high) -> Sz8 (translate_bool high) + | X86S16 -> Sz16 + | X86S32 -> Sz32 + | X86S64 -> Sz64 + +let translate_reg r = Nat_big_num.of_int (reg_to_int r) + +let translate_scale s = + Sail_values.to_vec0 is_inc (Nat_big_num.of_int 2, Nat_big_num.of_int s) + +let translate_imm64 i = Sail_values.to_vec0 is_inc (Nat_big_num.of_int 64, i) + +let translate_msi = function + | Some (scale, reg) -> Some (translate_scale scale, translate_reg reg) + | None -> None + +let translate_base = function + | X86HGenBase.NoBase -> X86_embed_types.NoBase + | X86HGenBase.RegBase(r) -> X86_embed_types.RegBase (translate_reg r) + | X86HGenBase.RipBase -> X86_embed_types.RipBase + +let translate_rm = function + | X86HGenBase.Reg (r) -> X86_embed_types.X86_Reg (translate_reg r) + | X86HGenBase.Mem (m_si, base, imm) -> X86_embed_types.Mem (translate_msi m_si, translate_base base, translate_imm64 imm) + | X86HGenBase.Sym (s) -> X86_embed_types.Mem (None, X86_embed_types.NoBase, translate_imm64 Nat_big_num.zero) + +let translate_dest_src = function + | X86HGenBase.R_rm (reg, rm) -> X86_embed_types.R_rm (translate_reg reg, translate_rm rm) + | X86HGenBase.Rm_i (rm, imm64) -> X86_embed_types.Rm_i (translate_rm rm, translate_imm64 imm64) + | X86HGenBase.Rm_r (rm, reg) -> X86_embed_types.Rm_r (translate_rm rm, translate_reg reg) + +let translate_imm_rm = function + | X86HGenBase.Imm (imm) -> X86_embed_types.Imm (translate_imm64 imm) + | X86HGenBase.Rm (rm) -> X86_embed_types.Rm (translate_rm rm) + +let translate_bitoffset = function + | X86HGenBase.Bit_rm_imm (rm, imm) -> Bit_rm_imm (translate_rm rm, translate_imm64 (Nat_big_num.of_int imm)) + | X86HGenBase.Bit_rm_r (rm, r) -> Bit_rm_r (translate_rm rm, translate_reg r) + +let translate_cond = function + | X86O -> X86_O + | X86NO -> X86_NO + | X86B -> X86_B + | X86NB -> X86_NB + | X86E -> X86_E + | X86NE -> X86_NE + | X86NA -> X86_NA + | X86A -> X86_A + | X86S -> X86_S + | X86NS -> X86_NS + | X86P -> X86_P + | X86NP -> X86_NP + | X86L -> X86_L + | X86NL -> X86_NL + | X86NG -> X86_NG + | X86G -> X86_G + | X86ALWAYS -> X86_ALWAYS + +let translate_monop = function + | X86DEC -> X86_Dec + | X86INC -> X86_Inc + | X86NOT -> X86_Not + | X86NEG -> X86_Neg diff --git a/old/x86/gen/lexer.hgen b/old/x86/gen/lexer.hgen new file mode 100644 index 00000000..56944e6d --- /dev/null +++ b/old/x86/gen/lexer.hgen @@ -0,0 +1,399 @@ +"addb" , BINOP { txt = "ADDB"; op = X86ADD; sz = X86BYTE }; +"orb" , BINOP { txt = "ORB"; op = X86OR; sz = X86BYTE }; +"adcb" , BINOP { txt = "ADCB"; op = X86ADC; sz = X86BYTE }; +"sbbb" , BINOP { txt = "SBBB"; op = X86SBB; sz = X86BYTE }; +"andb" , BINOP { txt = "ANDB"; op = X86AND; sz = X86BYTE }; +"subb" , BINOP { txt = "SUBB"; op = X86SUB; sz = X86BYTE }; +"xorb" , BINOP { txt = "XORB"; op = X86XOR; sz = X86BYTE }; +"cmpb" , BINOP { txt = "CMPB"; op = X86CMP; sz = X86BYTE }; +"rolb" , BINOP { txt = "ROLB"; op = X86ROL; sz = X86BYTE }; +"rorb" , BINOP { txt = "RORB"; op = X86ROR; sz = X86BYTE }; +"shlb" , BINOP { txt = "SHLB"; op = X86SHL; sz = X86BYTE }; +"shrb" , BINOP { txt = "SHRB"; op = X86SHR; sz = X86BYTE }; +"testb" , BINOP { txt = "TESTB"; op = X86TEST; sz = X86BYTE }; +"sarb" , BINOP { txt = "SARB"; op = X86SAR; sz = X86BYTE }; +"addw" , BINOP { txt = "ADDW"; op = X86ADD; sz = X86WORD }; +"orw" , BINOP { txt = "ORW"; op = X86OR; sz = X86WORD }; +"adcw" , BINOP { txt = "ADCW"; op = X86ADC; sz = X86WORD }; +"sbbw" , BINOP { txt = "SBBW"; op = X86SBB; sz = X86WORD }; +"andw" , BINOP { txt = "ANDW"; op = X86AND; sz = X86WORD }; +"subw" , BINOP { txt = "SUBW"; op = X86SUB; sz = X86WORD }; +"xorw" , BINOP { txt = "XORW"; op = X86XOR; sz = X86WORD }; +"cmpw" , BINOP { txt = "CMPW"; op = X86CMP; sz = X86WORD }; +"rolw" , BINOP { txt = "ROLW"; op = X86ROL; sz = X86WORD }; +"rorw" , BINOP { txt = "RORW"; op = X86ROR; sz = X86WORD }; +"shlw" , BINOP { txt = "SHLW"; op = X86SHL; sz = X86WORD }; +"shrw" , BINOP { txt = "SHRW"; op = X86SHR; sz = X86WORD }; +"testw" , BINOP { txt = "TESTW"; op = X86TEST; sz = X86WORD }; +"sarw" , BINOP { txt = "SARW"; op = X86SAR; sz = X86WORD }; +"addl" , BINOP { txt = "ADDL"; op = X86ADD; sz = X86LONG }; +"orl" , BINOP { txt = "ORL"; op = X86OR; sz = X86LONG }; +"adcl" , BINOP { txt = "ADCL"; op = X86ADC; sz = X86LONG }; +"sbbl" , BINOP { txt = "SBBL"; op = X86SBB; sz = X86LONG }; +"andl" , BINOP { txt = "ANDL"; op = X86AND; sz = X86LONG }; +"subl" , BINOP { txt = "SUBL"; op = X86SUB; sz = X86LONG }; +"xorl" , BINOP { txt = "XORL"; op = X86XOR; sz = X86LONG }; +"cmpl" , BINOP { txt = "CMPL"; op = X86CMP; sz = X86LONG }; +"roll" , BINOP { txt = "ROLL"; op = X86ROL; sz = X86LONG }; +"rorl" , BINOP { txt = "RORL"; op = X86ROR; sz = X86LONG }; +"shll" , BINOP { txt = "SHLL"; op = X86SHL; sz = X86LONG }; +"shrl" , BINOP { txt = "SHRL"; op = X86SHR; sz = X86LONG }; +"testl" , BINOP { txt = "TESTL"; op = X86TEST; sz = X86LONG }; +"sarl" , BINOP { txt = "SARL"; op = X86SAR; sz = X86LONG }; +"addq" , BINOP { txt = "ADDQ"; op = X86ADD; sz = X86QUAD }; +"orq" , BINOP { txt = "ORQ"; op = X86OR; sz = X86QUAD }; +"adcq" , BINOP { txt = "ADCQ"; op = X86ADC; sz = X86QUAD }; +"sbbq" , BINOP { txt = "SBBQ"; op = X86SBB; sz = X86QUAD }; +"andq" , BINOP { txt = "ANDQ"; op = X86AND; sz = X86QUAD }; +"subq" , BINOP { txt = "SUBQ"; op = X86SUB; sz = X86QUAD }; +"xorq" , BINOP { txt = "XORQ"; op = X86XOR; sz = X86QUAD }; +"cmpq" , BINOP { txt = "CMPQ"; op = X86CMP; sz = X86QUAD }; +"rolq" , BINOP { txt = "ROLQ"; op = X86ROL; sz = X86QUAD }; +"rorq" , BINOP { txt = "RORQ"; op = X86ROR; sz = X86QUAD }; +"shlq" , BINOP { txt = "SHLQ"; op = X86SHL; sz = X86QUAD }; +"shrq" , BINOP { txt = "SHRQ"; op = X86SHR; sz = X86QUAD }; +"testq" , BINOP { txt = "TESTQ"; op = X86TEST; sz = X86QUAD }; +"sarq" , BINOP { txt = "SARQ"; op = X86SAR; sz = X86QUAD }; +"add" , BINOP { txt = "ADDQ"; op = X86ADD; sz = X86NONE }; +"or" , BINOP { txt = "OR"; op = X86OR; sz = X86NONE }; +"adc" , BINOP { txt = "ADC"; op = X86ADC; sz = X86NONE }; +"sbb" , BINOP { txt = "SBB"; op = X86SBB; sz = X86NONE }; +"and" , BINOP { txt = "AND"; op = X86AND; sz = X86NONE }; +"sub" , BINOP { txt = "SUB"; op = X86SUB; sz = X86NONE }; +"xor" , BINOP { txt = "XOR"; op = X86XOR; sz = X86NONE }; +"cmp" , BINOP { txt = "CMP"; op = X86CMP; sz = X86NONE }; +"rol" , BINOP { txt = "ROL"; op = X86ROL; sz = X86NONE }; +"ror" , BINOP { txt = "ROR"; op = X86ROR; sz = X86NONE }; +"shl" , BINOP { txt = "SHL"; op = X86SHL; sz = X86NONE }; +"shr" , BINOP { txt = "SHR"; op = X86SHR; sz = X86NONE }; +"test" , BINOP { txt = "TEST"; op = X86TEST; sz = X86NONE }; +"sar" , BINOP { txt = "SAR"; op = X86SAR; sz = X86NONE }; +"btcw" , BITOP { txt = "BTSW"; op = X86Btc; sz = X86WORD }; +"btsw" , BITOP { txt = "BTCW"; op = X86Bts; sz = X86WORD }; +"btrw" , BITOP { txt = "BTRW"; op = X86Btr; sz = X86WORD }; +"btcl" , BITOP { txt = "BTSL"; op = X86Btc; sz = X86LONG }; +"btsl" , BITOP { txt = "BTCL"; op = X86Bts; sz = X86LONG }; +"btrl" , BITOP { txt = "BTRL"; op = X86Btr; sz = X86LONG }; +"btcq" , BITOP { txt = "BTSQ"; op = X86Btc; sz = X86QUAD }; +"btsq" , BITOP { txt = "BTCQ"; op = X86Bts; sz = X86QUAD }; +"btrq" , BITOP { txt = "BTRQ"; op = X86Btr; sz = X86QUAD }; +"btc" , BITOP { txt = "BTS"; op = X86Btc; sz = X86NONE }; +"bts" , BITOP { txt = "BTC"; op = X86Bts; sz = X86NONE }; +"btr" , BITOP { txt = "BTR"; op = X86Btr; sz = X86NONE }; +"call" , CALL { txt = "CALL" }; +"clc" , CLC { txt = "CLC" }; +"cmc" , CMC { txt = "CMC" }; +"cmpxchgb" , CMPXCHG { txt = "CMPXCHGB"; sz = X86BYTE }; +"cmpxchgw" , CMPXCHG { txt = "CMPXCHGW"; sz = X86WORD }; +"cmpxchgl" , CMPXCHG { txt = "CMPXCHGL"; sz = X86LONG }; +"cmpxchgq" , CMPXCHG { txt = "CMPXCHGQ"; sz = X86QUAD }; +"cmpxchg" , CMPXCHG { txt = "CMPXCHG"; sz = X86NONE }; +"divb" , DIV { txt = "DIVB"; sz = X86BYTE }; +"divw" , DIV { txt = "DIVW"; sz = X86WORD }; +"divl" , DIV { txt = "DIVL"; sz = X86LONG }; +"divq" , DIV { txt = "DIVQ"; sz = X86QUAD }; +"div" , DIV { txt = "DIV"; sz = X86NONE }; +"jo" , JCC { txt = "JO"; cond = X86O }; +"jb" , JCC { txt = "JB"; cond = X86B }; +"jc" , JCC { txt = "JC"; cond = X86B }; +"jnae" , JCC { txt = "JNAE"; cond = X86B }; +"je" , JCC { txt = "JE"; cond = X86E }; +"jz" , JCC { txt = "JZ"; cond = X86E }; +"ja" , JCC { txt = "JA"; cond = X86A }; +"jnbe" , JCC { txt = "JNBE"; cond = X86A }; +"js" , JCC { txt = "JS"; cond = X86S }; +"jp" , JCC { txt = "JP"; cond = X86P }; +"jpe" , JCC { txt = "JPE"; cond = X86P }; +"jl" , JCC { txt = "JL"; cond = X86L }; +"jnge" , JCC { txt = "JNGE"; cond = X86L }; +"jg" , JCC { txt = "JG"; cond = X86G }; +"jnle" , JCC { txt = "JNLE"; cond = X86G }; +"jno" , JCC { txt = "JNO"; cond = X86NO }; +"jnb" , JCC { txt = "JNB"; cond = X86NB }; +"jnc" , JCC { txt = "JNC"; cond = X86NB }; +"jae" , JCC { txt = "JAE"; cond = X86NB }; +"jne" , JCC { txt = "JNE"; cond = X86NE }; +"jnz" , JCC { txt = "JNZ"; cond = X86NE }; +"jna" , JCC { txt = "JNA"; cond = X86NA }; +"jbe" , JCC { txt = "JBE"; cond = X86NA }; +"jns" , JCC { txt = "JNS"; cond = X86NS }; +"jnp" , JCC { txt = "JNP"; cond = X86NP }; +"jpo" , JCC { txt = "JPO"; cond = X86NP }; +"jnl" , JCC { txt = "JNL"; cond = X86NL }; +"jge" , JCC { txt = "JGE"; cond = X86NL }; +"jng" , JCC { txt = "JNG"; cond = X86NG }; +"jle" , JCC { txt = "JLE"; cond = X86NG }; +"jmp" , JMP { txt = "JMP" }; +"leaw" , LEA { txt = "LEAW"; sz = X86BYTE }; +"leal" , LEA { txt = "LEAL"; sz = X86LONG }; +"leaq" , LEA { txt = "LEAQ"; sz = X86QUAD }; +"lea" , LEA { txt = "LEA"; sz = X86NONE }; +"leave" , LEAVE { txt = "LEAVE" }; +"loopo" , LOOP { txt = "LOOPO"; cond = X86O }; +"loopb" , LOOP { txt = "LOOPB"; cond = X86B }; +"loopc" , LOOP { txt = "LOOPC"; cond = X86B }; +"loopnae" , LOOP { txt = "LOOPNAE"; cond = X86B }; +"loope" , LOOP { txt = "LOOPE"; cond = X86E }; +"loopz" , LOOP { txt = "LOOPZ"; cond = X86E }; +"loopa" , LOOP { txt = "LOOPA"; cond = X86A }; +"loopnbe" , LOOP { txt = "LOOPNBE"; cond = X86A }; +"loops" , LOOP { txt = "LOOPS"; cond = X86S }; +"loopp" , LOOP { txt = "LOOPP"; cond = X86P }; +"looppe" , LOOP { txt = "LOOPPE"; cond = X86P }; +"loopl" , LOOP { txt = "LOOPL"; cond = X86L }; +"loopnge" , LOOP { txt = "LOOPNGE"; cond = X86L }; +"loopg" , LOOP { txt = "LOOPG"; cond = X86G }; +"loopnle" , LOOP { txt = "LOOPNLE"; cond = X86G }; +"loopno" , LOOP { txt = "LOOPNO"; cond = X86NO }; +"loopnb" , LOOP { txt = "LOOPNB"; cond = X86NB }; +"loopnc" , LOOP { txt = "LOOPNC"; cond = X86NB }; +"loopae" , LOOP { txt = "LOOPAE"; cond = X86NB }; +"loopne" , LOOP { txt = "LOOPNE"; cond = X86NE }; +"loopnz" , LOOP { txt = "LOOPNZ"; cond = X86NE }; +"loopna" , LOOP { txt = "LOOPNA"; cond = X86NA }; +"loopbe" , LOOP { txt = "LOOPBE"; cond = X86NA }; +"loopns" , LOOP { txt = "LOOPNS"; cond = X86NS }; +"loopnp" , LOOP { txt = "LOOPNP"; cond = X86NP }; +"looppo" , LOOP { txt = "LOOPPO"; cond = X86NP }; +"loopnl" , LOOP { txt = "LOOPNL"; cond = X86NL }; +"loopge" , LOOP { txt = "LOOPGE"; cond = X86NL }; +"loopng" , LOOP { txt = "LOOPNG"; cond = X86NG }; +"loople" , LOOP { txt = "LOOPLE"; cond = X86NG }; +"mfence" , MFENCE { txt = "MFENCE" }; +"decb" , MONOP { txt = "DECB"; op = X86DEC; sz = X86BYTE }; +"incb" , MONOP { txt = "INCB"; op = X86INC; sz = X86BYTE }; +"notb" , MONOP { txt = "NOTB"; op = X86NOT; sz = X86BYTE }; +"negb" , MONOP { txt = "NEGB"; op = X86NEG; sz = X86BYTE }; +"decw" , MONOP { txt = "DECW"; op = X86DEC; sz = X86WORD }; +"incw" , MONOP { txt = "INCW"; op = X86INC; sz = X86WORD }; +"notw" , MONOP { txt = "NOTW"; op = X86NOT; sz = X86WORD }; +"negw" , MONOP { txt = "NEGW"; op = X86NEG; sz = X86WORD }; +"decl" , MONOP { txt = "DECL"; op = X86DEC; sz = X86LONG }; +"incl" , MONOP { txt = "INCL"; op = X86INC; sz = X86LONG }; +"notl" , MONOP { txt = "NOTL"; op = X86NOT; sz = X86LONG }; +"negl" , MONOP { txt = "NEGL"; op = X86NEG; sz = X86LONG }; +"decq" , MONOP { txt = "DECQ"; op = X86DEC; sz = X86QUAD }; +"incq" , MONOP { txt = "INCQ"; op = X86INC; sz = X86QUAD }; +"notq" , MONOP { txt = "NOTQ"; op = X86NOT; sz = X86QUAD }; +"negq" , MONOP { txt = "NEGQ"; op = X86NEG; sz = X86QUAD }; +"dec" , MONOP { txt = "DEC"; op = X86DEC; sz = X86NONE }; +"inc" , MONOP { txt = "INC"; op = X86INC; sz = X86NONE }; +"not" , MONOP { txt = "NOT"; op = X86NOT; sz = X86NONE }; +"neg" , MONOP { txt = "NEG"; op = X86NEG; sz = X86NONE }; +"cmovow" , CMOV { txt = "CMOVOW"; cond = X86O; sz = X86WORD }; +"cmovbw" , CMOV { txt = "CMOVBW"; cond = X86B; sz = X86WORD }; +"cmovcw" , CMOV { txt = "CMOVCW"; cond = X86B; sz = X86WORD }; +"cmovnaew" , CMOV { txt = "CMOVNAEW"; cond = X86B; sz = X86WORD }; +"cmovew" , CMOV { txt = "CMOVEW"; cond = X86E; sz = X86WORD }; +"cmovzw" , CMOV { txt = "CMOVZW"; cond = X86E; sz = X86WORD }; +"cmovaw" , CMOV { txt = "CMOVAW"; cond = X86A; sz = X86WORD }; +"cmovnbew" , CMOV { txt = "CMOVNBEW"; cond = X86A; sz = X86WORD }; +"cmovsw" , CMOV { txt = "CMOVSW"; cond = X86S; sz = X86WORD }; +"cmovpw" , CMOV { txt = "CMOVPW"; cond = X86P; sz = X86WORD }; +"cmovpew" , CMOV { txt = "CMOVPEW"; cond = X86P; sz = X86WORD }; +"cmovlw" , CMOV { txt = "CMOVLW"; cond = X86L; sz = X86WORD }; +"cmovngew" , CMOV { txt = "CMOVNGEW"; cond = X86L; sz = X86WORD }; +"cmovgw" , CMOV { txt = "CMOVGW"; cond = X86G; sz = X86WORD }; +"cmovnlew" , CMOV { txt = "CMOVNLEW"; cond = X86G; sz = X86WORD }; +"cmovnow" , CMOV { txt = "CMOVNOW"; cond = X86NO; sz = X86WORD }; +"cmovnbw" , CMOV { txt = "CMOVNBW"; cond = X86NB; sz = X86WORD }; +"cmovncw" , CMOV { txt = "CMOVNCW"; cond = X86NB; sz = X86WORD }; +"cmovaew" , CMOV { txt = "CMOVAEW"; cond = X86NB; sz = X86WORD }; +"cmovnew" , CMOV { txt = "CMOVNEW"; cond = X86NE; sz = X86WORD }; +"cmovnzw" , CMOV { txt = "CMOVNZW"; cond = X86NE; sz = X86WORD }; +"cmovnaw" , CMOV { txt = "CMOVNAW"; cond = X86NA; sz = X86WORD }; +"cmovbew" , CMOV { txt = "CMOVBEW"; cond = X86NA; sz = X86WORD }; +"cmovnsw" , CMOV { txt = "CMOVNSW"; cond = X86NS; sz = X86WORD }; +"cmovnpw" , CMOV { txt = "CMOVNPW"; cond = X86NP; sz = X86WORD }; +"cmovpow" , CMOV { txt = "CMOVPOW"; cond = X86NP; sz = X86WORD }; +"cmovnlw" , CMOV { txt = "CMOVNLW"; cond = X86NL; sz = X86WORD }; +"cmovgew" , CMOV { txt = "CMOVGEW"; cond = X86NL; sz = X86WORD }; +"cmovngw" , CMOV { txt = "CMOVNGW"; cond = X86NG; sz = X86WORD }; +"cmovlew" , CMOV { txt = "CMOVLEW"; cond = X86NG; sz = X86WORD }; +"cmovol" , CMOV { txt = "CMOVOL"; cond = X86O; sz = X86LONG }; +"cmovbl" , CMOV { txt = "CMOVBL"; cond = X86B; sz = X86LONG }; +"cmovcl" , CMOV { txt = "CMOVCL"; cond = X86B; sz = X86LONG }; +"cmovnael" , CMOV { txt = "CMOVNAEL"; cond = X86B; sz = X86LONG }; +"cmovel" , CMOV { txt = "CMOVEL"; cond = X86E; sz = X86LONG }; +"cmovzl" , CMOV { txt = "CMOVZL"; cond = X86E; sz = X86LONG }; +"cmoval" , CMOV { txt = "CMOVAL"; cond = X86A; sz = X86LONG }; +"cmovnbel" , CMOV { txt = "CMOVNBEL"; cond = X86A; sz = X86LONG }; +"cmovsl" , CMOV { txt = "CMOVSL"; cond = X86S; sz = X86LONG }; +"cmovpl" , CMOV { txt = "CMOVPL"; cond = X86P; sz = X86LONG }; +"cmovpel" , CMOV { txt = "CMOVPEL"; cond = X86P; sz = X86LONG }; +"cmovll" , CMOV { txt = "CMOVLL"; cond = X86L; sz = X86LONG }; +"cmovngel" , CMOV { txt = "CMOVNGEL"; cond = X86L; sz = X86LONG }; +"cmovgl" , CMOV { txt = "CMOVGL"; cond = X86G; sz = X86LONG }; +"cmovnlel" , CMOV { txt = "CMOVNLEL"; cond = X86G; sz = X86LONG }; +"cmovnol" , CMOV { txt = "CMOVNOL"; cond = X86NO; sz = X86LONG }; +"cmovnbl" , CMOV { txt = "CMOVNBL"; cond = X86NB; sz = X86LONG }; +"cmovncl" , CMOV { txt = "CMOVNCL"; cond = X86NB; sz = X86LONG }; +"cmovael" , CMOV { txt = "CMOVAEL"; cond = X86NB; sz = X86LONG }; +"cmovnel" , CMOV { txt = "CMOVNEL"; cond = X86NE; sz = X86LONG }; +"cmovnzl" , CMOV { txt = "CMOVNZL"; cond = X86NE; sz = X86LONG }; +"cmovnal" , CMOV { txt = "CMOVNAL"; cond = X86NA; sz = X86LONG }; +"cmovbel" , CMOV { txt = "CMOVBEL"; cond = X86NA; sz = X86LONG }; +"cmovnsl" , CMOV { txt = "CMOVNSL"; cond = X86NS; sz = X86LONG }; +"cmovnpl" , CMOV { txt = "CMOVNPL"; cond = X86NP; sz = X86LONG }; +"cmovpol" , CMOV { txt = "CMOVPOL"; cond = X86NP; sz = X86LONG }; +"cmovnll" , CMOV { txt = "CMOVNLL"; cond = X86NL; sz = X86LONG }; +"cmovgel" , CMOV { txt = "CMOVGEL"; cond = X86NL; sz = X86LONG }; +"cmovngl" , CMOV { txt = "CMOVNGL"; cond = X86NG; sz = X86LONG }; +"cmovlel" , CMOV { txt = "CMOVLEL"; cond = X86NG; sz = X86LONG }; +"cmovoq" , CMOV { txt = "CMOVOQ"; cond = X86O; sz = X86QUAD }; +"cmovbq" , CMOV { txt = "CMOVBQ"; cond = X86B; sz = X86QUAD }; +"cmovcq" , CMOV { txt = "CMOVCQ"; cond = X86B; sz = X86QUAD }; +"cmovnaeq" , CMOV { txt = "CMOVNAEQ"; cond = X86B; sz = X86QUAD }; +"cmoveq" , CMOV { txt = "CMOVEQ"; cond = X86E; sz = X86QUAD }; +"cmovzq" , CMOV { txt = "CMOVZQ"; cond = X86E; sz = X86QUAD }; +"cmovaq" , CMOV { txt = "CMOVAQ"; cond = X86A; sz = X86QUAD }; +"cmovnbeq" , CMOV { txt = "CMOVNBEQ"; cond = X86A; sz = X86QUAD }; +"cmovsq" , CMOV { txt = "CMOVSQ"; cond = X86S; sz = X86QUAD }; +"cmovpq" , CMOV { txt = "CMOVPQ"; cond = X86P; sz = X86QUAD }; +"cmovpeq" , CMOV { txt = "CMOVPEQ"; cond = X86P; sz = X86QUAD }; +"cmovlq" , CMOV { txt = "CMOVLQ"; cond = X86L; sz = X86QUAD }; +"cmovngeq" , CMOV { txt = "CMOVNGEQ"; cond = X86L; sz = X86QUAD }; +"cmovgq" , CMOV { txt = "CMOVGQ"; cond = X86G; sz = X86QUAD }; +"cmovnleq" , CMOV { txt = "CMOVNLEQ"; cond = X86G; sz = X86QUAD }; +"cmovnoq" , CMOV { txt = "CMOVNOQ"; cond = X86NO; sz = X86QUAD }; +"cmovnbq" , CMOV { txt = "CMOVNBQ"; cond = X86NB; sz = X86QUAD }; +"cmovncq" , CMOV { txt = "CMOVNCQ"; cond = X86NB; sz = X86QUAD }; +"cmovaeq" , CMOV { txt = "CMOVAEQ"; cond = X86NB; sz = X86QUAD }; +"cmovneq" , CMOV { txt = "CMOVNEQ"; cond = X86NE; sz = X86QUAD }; +"cmovnzq" , CMOV { txt = "CMOVNZQ"; cond = X86NE; sz = X86QUAD }; +"cmovnaq" , CMOV { txt = "CMOVNAQ"; cond = X86NA; sz = X86QUAD }; +"cmovbeq" , CMOV { txt = "CMOVBEQ"; cond = X86NA; sz = X86QUAD }; +"cmovnsq" , CMOV { txt = "CMOVNSQ"; cond = X86NS; sz = X86QUAD }; +"cmovnpq" , CMOV { txt = "CMOVNPQ"; cond = X86NP; sz = X86QUAD }; +"cmovpoq" , CMOV { txt = "CMOVPOQ"; cond = X86NP; sz = X86QUAD }; +"cmovnlq" , CMOV { txt = "CMOVNLQ"; cond = X86NL; sz = X86QUAD }; +"cmovgeq" , CMOV { txt = "CMOVGEQ"; cond = X86NL; sz = X86QUAD }; +"cmovngq" , CMOV { txt = "CMOVNGQ"; cond = X86NG; sz = X86QUAD }; +"cmovleq" , CMOV { txt = "CMOVLEQ"; cond = X86NG; sz = X86QUAD }; +"cmovo" , CMOV { txt = "CMOVO"; cond = X86O; sz = X86NONE }; +"cmovb" , CMOV { txt = "CMOVB"; cond = X86B; sz = X86NONE }; +"cmovc" , CMOV { txt = "CMOVC"; cond = X86B; sz = X86NONE }; +"cmovnae" , CMOV { txt = "CMOVNAE"; cond = X86B; sz = X86NONE }; +"cmove" , CMOV { txt = "CMOVE"; cond = X86E; sz = X86NONE }; +"cmovz" , CMOV { txt = "CMOVZ"; cond = X86E; sz = X86NONE }; +"cmova" , CMOV { txt = "CMOVA"; cond = X86A; sz = X86NONE }; +"cmovnbe" , CMOV { txt = "CMOVNBE"; cond = X86A; sz = X86NONE }; +"cmovs" , CMOV { txt = "CMOVS"; cond = X86S; sz = X86NONE }; +"cmovp" , CMOV { txt = "CMOVP"; cond = X86P; sz = X86NONE }; +"cmovpe" , CMOV { txt = "CMOVPE"; cond = X86P; sz = X86NONE }; +"cmovl" , CMOV { txt = "CMOVL"; cond = X86L; sz = X86NONE }; +"cmovnge" , CMOV { txt = "CMOVNGE"; cond = X86L; sz = X86NONE }; +"cmovg" , CMOV { txt = "CMOVG"; cond = X86G; sz = X86NONE }; +"cmovnle" , CMOV { txt = "CMOVNLE"; cond = X86G; sz = X86NONE }; +"cmovno" , CMOV { txt = "CMOVNO"; cond = X86NO; sz = X86NONE }; +"cmovnb" , CMOV { txt = "CMOVNB"; cond = X86NB; sz = X86NONE }; +"cmovnc" , CMOV { txt = "CMOVNC"; cond = X86NB; sz = X86NONE }; +"cmovae" , CMOV { txt = "CMOVAE"; cond = X86NB; sz = X86NONE }; +"cmovne" , CMOV { txt = "CMOVNE"; cond = X86NE; sz = X86NONE }; +"cmovnz" , CMOV { txt = "CMOVNZ"; cond = X86NE; sz = X86NONE }; +"cmovna" , CMOV { txt = "CMOVNA"; cond = X86NA; sz = X86NONE }; +"cmovbe" , CMOV { txt = "CMOVBE"; cond = X86NA; sz = X86NONE }; +"cmovns" , CMOV { txt = "CMOVNS"; cond = X86NS; sz = X86NONE }; +"cmovnp" , CMOV { txt = "CMOVNP"; cond = X86NP; sz = X86NONE }; +"cmovpo" , CMOV { txt = "CMOVPO"; cond = X86NP; sz = X86NONE }; +"cmovnl" , CMOV { txt = "CMOVNL"; cond = X86NL; sz = X86NONE }; +"cmovge" , CMOV { txt = "CMOVGE"; cond = X86NL; sz = X86NONE }; +"cmovng" , CMOV { txt = "CMOVNG"; cond = X86NG; sz = X86NONE }; +"cmovle" , CMOV { txt = "CMOVLE"; cond = X86NG; sz = X86NONE }; +"movb" , MOV { txt = "MOVB"; sz = X86BYTE }; +"movw" , MOV { txt = "MOVW"; sz = X86WORD }; +"movl" , MOV { txt = "MOVL"; sz = X86LONG }; +"movq" , MOV { txt = "MOVQ"; sz = X86QUAD }; +"mov" , MOV { txt = "MOV"; sz = X86NONE }; +"movabs" , MOV { txt = "MOVABS"; sz = X86QUAD }; +"movsbw" , MOVSX { txt = "MOVSBW"; sz1 = X86BYTE; sz2 = X86WORD }; +"movsbl" , MOVSX { txt = "MOVSBL"; sz1 = X86BYTE; sz2 = X86LONG }; +"movsbq" , MOVSX { txt = "MOVSBQ"; sz1 = X86BYTE; sz2 = X86QUAD }; +"movswl" , MOVSX { txt = "MOVSWL"; sz1 = X86WORD; sz2 = X86LONG }; +"movswq" , MOVSX { txt = "MOVSWQ"; sz1 = X86WORD; sz2 = X86QUAD }; +"movslq" , MOVSX { txt = "MOVSWQ"; sz1 = X86LONG; sz2 = X86QUAD }; +"movzbw" , MOVZX { txt = "MOVZBW"; sz1 = X86BYTE; sz2 = X86WORD }; +"movzbl" , MOVZX { txt = "MOVZBL"; sz1 = X86BYTE; sz2 = X86LONG }; +"movzbq" , MOVZX { txt = "MOVZBQ"; sz1 = X86BYTE; sz2 = X86QUAD }; +"movzwl" , MOVZX { txt = "MOVZWL"; sz1 = X86WORD; sz2 = X86LONG }; +"movzwq" , MOVZX { txt = "MOVZWQ"; sz1 = X86WORD; sz2 = X86QUAD }; +"mulb" , MUL { txt = "MULB"; sz = X86BYTE }; +"mulw" , MUL { txt = "MULW"; sz = X86WORD }; +"mull" , MUL { txt = "MULL"; sz = X86LONG }; +"mulq" , MUL { txt = "MULQ"; sz = X86QUAD }; +"mul" , MUL { txt = "MUL"; sz = X86NONE }; +"nop" , NOP { txt = "NOP" }; +"pop" , POP { txt = "POP" }; +"push" , PUSH { txt = "PUSH" }; +"ret" , PUSH { txt = "RET" }; +"setob" , SET { txt = "SETOB"; cond = X86O }; +"setbb" , SET { txt = "SETBB"; cond = X86B }; +"setcb" , SET { txt = "SETCB"; cond = X86B }; +"setnaeb" , SET { txt = "SETNAEB"; cond = X86B }; +"seteb" , SET { txt = "SETEB"; cond = X86E }; +"setzb" , SET { txt = "SETZB"; cond = X86E }; +"setab" , SET { txt = "SETAB"; cond = X86A }; +"setnbeb" , SET { txt = "SETNBEB"; cond = X86A }; +"setsb" , SET { txt = "SETSB"; cond = X86S }; +"setpb" , SET { txt = "SETPB"; cond = X86P }; +"setpeb" , SET { txt = "SETPEB"; cond = X86P }; +"setlb" , SET { txt = "SETLB"; cond = X86L }; +"setngeb" , SET { txt = "SETNGEB"; cond = X86L }; +"setgb" , SET { txt = "SETGB"; cond = X86G }; +"setnleb" , SET { txt = "SETNLEB"; cond = X86G }; +"setnob" , SET { txt = "SETNOB"; cond = X86NO }; +"setnbb" , SET { txt = "SETNBB"; cond = X86NB }; +"setncb" , SET { txt = "SETNCB"; cond = X86NB }; +"setaeb" , SET { txt = "SETAEB"; cond = X86NB }; +"setneb" , SET { txt = "SETNEB"; cond = X86NE }; +"setnzb" , SET { txt = "SETNZB"; cond = X86NE }; +"setnab" , SET { txt = "SETNAB"; cond = X86NA }; +"setbeb" , SET { txt = "SETBEB"; cond = X86NA }; +"setnsb" , SET { txt = "SETNSB"; cond = X86NS }; +"setnpb" , SET { txt = "SETNPB"; cond = X86NP }; +"setpob" , SET { txt = "SETPOB"; cond = X86NP }; +"setnlb" , SET { txt = "SETNLB"; cond = X86NL }; +"setgeb" , SET { txt = "SETGEB"; cond = X86NL }; +"setngb" , SET { txt = "SETNGB"; cond = X86NG }; +"setleb" , SET { txt = "SETLEB"; cond = X86NG }; +"seto" , SET { txt = "SETO"; cond = X86O }; +"setb" , SET { txt = "SETB"; cond = X86B }; +"setc" , SET { txt = "SETC"; cond = X86B }; +"setnae" , SET { txt = "SETNAE"; cond = X86B }; +"sete" , SET { txt = "SETE"; cond = X86E }; +"setz" , SET { txt = "SETZ"; cond = X86E }; +"seta" , SET { txt = "SETA"; cond = X86A }; +"setnbe" , SET { txt = "SETNBE"; cond = X86A }; +"sets" , SET { txt = "SETS"; cond = X86S }; +"setp" , SET { txt = "SETP"; cond = X86P }; +"setpe" , SET { txt = "SETPE"; cond = X86P }; +"setl" , SET { txt = "SETL"; cond = X86L }; +"setnge" , SET { txt = "SETNGE"; cond = X86L }; +"setg" , SET { txt = "SETG"; cond = X86G }; +"setnle" , SET { txt = "SETNLE"; cond = X86G }; +"setno" , SET { txt = "SETNO"; cond = X86NO }; +"setnb" , SET { txt = "SETNB"; cond = X86NB }; +"setnc" , SET { txt = "SETNC"; cond = X86NB }; +"setae" , SET { txt = "SETAE"; cond = X86NB }; +"setne" , SET { txt = "SETNE"; cond = X86NE }; +"setnz" , SET { txt = "SETNZ"; cond = X86NE }; +"setna" , SET { txt = "SETNA"; cond = X86NA }; +"setbe" , SET { txt = "SETBE"; cond = X86NA }; +"setns" , SET { txt = "SETNS"; cond = X86NS }; +"setnp" , SET { txt = "SETNP"; cond = X86NP }; +"setpo" , SET { txt = "SETPO"; cond = X86NP }; +"setnl" , SET { txt = "SETNL"; cond = X86NL }; +"setge" , SET { txt = "SETGE"; cond = X86NL }; +"setng" , SET { txt = "SETNG"; cond = X86NG }; +"setle" , SET { txt = "SETLE"; cond = X86NG }; +"stc" , STC { txt = "STC" }; +"xaddb" , XADD { txt = "XADDB"; sz = X86BYTE }; +"xaddw" , XADD { txt = "XADDW"; sz = X86WORD }; +"xaddl" , XADD { txt = "XADDL"; sz = X86LONG }; +"xaddq" , XADD { txt = "XADDQ"; sz = X86QUAD }; +"xadd" , XADD { txt = "XADD"; sz = X86NONE }; +"xchgb" , XCHG { txt = "XCHGB"; sz = X86BYTE }; +"xchgw" , XCHG { txt = "XCHGW"; sz = X86WORD }; +"xchgl" , XCHG { txt = "XCHGL"; sz = X86LONG }; +"xchgq" , XCHG { txt = "XCHGQ"; sz = X86QUAD }; +"xchg" , XCHG { txt = "XCHG"; sz = X86NONE }; diff --git a/old/x86/gen/lexer_intel.hgen b/old/x86/gen/lexer_intel.hgen new file mode 100644 index 00000000..e1854a14 --- /dev/null +++ b/old/x86/gen/lexer_intel.hgen @@ -0,0 +1,161 @@ +"add" , BINOP { txt = "ADDQ"; op = X86ADD; sz = X86NONE }; +"or" , BINOP { txt = "OR"; op = X86OR; sz = X86NONE }; +"adc" , BINOP { txt = "ADC"; op = X86ADC; sz = X86NONE }; +"sbb" , BINOP { txt = "SBB"; op = X86SBB; sz = X86NONE }; +"and" , BINOP { txt = "AND"; op = X86AND; sz = X86NONE }; +"sub" , BINOP { txt = "SUB"; op = X86SUB; sz = X86NONE }; +"xor" , BINOP { txt = "XOR"; op = X86XOR; sz = X86NONE }; +"cmp" , BINOP { txt = "CMP"; op = X86CMP; sz = X86NONE }; +"rol" , BINOP { txt = "ROL"; op = X86ROL; sz = X86NONE }; +"ror" , BINOP { txt = "ROR"; op = X86ROR; sz = X86NONE }; +"shl" , BINOP { txt = "SHL"; op = X86SHL; sz = X86NONE }; +"shr" , BINOP { txt = "SHR"; op = X86SHR; sz = X86NONE }; +"test" , BINOP { txt = "TEST"; op = X86TEST; sz = X86NONE }; +"sar" , BINOP { txt = "SAR"; op = X86SAR; sz = X86NONE }; +"btc" , BITOP { txt = "BTS"; op = X86Btc; sz = X86NONE }; +"bts" , BITOP { txt = "BTC"; op = X86Bts; sz = X86NONE }; +"btr" , BITOP { txt = "BTR"; op = X86Btr; sz = X86NONE }; +"call" , CALL { txt = "CALL" }; +"clc" , CLC { txt = "CLC" }; +"cmc" , CMC { txt = "CMC" }; +"cmpxchg" , CMPXCHG { txt = "CMPXCHG"; sz = X86NONE }; +"div" , DIV { txt = "DIV"; sz = X86NONE }; +"jo" , JCC { txt = "JO"; cond = X86O }; +"jb" , JCC { txt = "JB"; cond = X86B }; +"jc" , JCC { txt = "JC"; cond = X86B }; +"jnae" , JCC { txt = "JNAE"; cond = X86B }; +"je" , JCC { txt = "JE"; cond = X86E }; +"jz" , JCC { txt = "JZ"; cond = X86E }; +"ja" , JCC { txt = "JA"; cond = X86A }; +"jnbe" , JCC { txt = "JNBE"; cond = X86A }; +"js" , JCC { txt = "JS"; cond = X86S }; +"jp" , JCC { txt = "JP"; cond = X86P }; +"jpe" , JCC { txt = "JPE"; cond = X86P }; +"jl" , JCC { txt = "JL"; cond = X86L }; +"jnge" , JCC { txt = "JNGE"; cond = X86L }; +"jg" , JCC { txt = "JG"; cond = X86G }; +"jnle" , JCC { txt = "JNLE"; cond = X86G }; +"jno" , JCC { txt = "JNO"; cond = X86NO }; +"jnb" , JCC { txt = "JNB"; cond = X86NB }; +"jnc" , JCC { txt = "JNC"; cond = X86NB }; +"jae" , JCC { txt = "JAE"; cond = X86NB }; +"jne" , JCC { txt = "JNE"; cond = X86NE }; +"jnz" , JCC { txt = "JNZ"; cond = X86NE }; +"jna" , JCC { txt = "JNA"; cond = X86NA }; +"jbe" , JCC { txt = "JBE"; cond = X86NA }; +"jns" , JCC { txt = "JNS"; cond = X86NS }; +"jnp" , JCC { txt = "JNP"; cond = X86NP }; +"jpo" , JCC { txt = "JPO"; cond = X86NP }; +"jnl" , JCC { txt = "JNL"; cond = X86NL }; +"jge" , JCC { txt = "JGE"; cond = X86NL }; +"jng" , JCC { txt = "JNG"; cond = X86NG }; +"jle" , JCC { txt = "JLE"; cond = X86NG }; +"jmp" , JMP { txt = "JMP" }; +"lea" , LEA { txt = "LEA"; sz = X86NONE }; +"leave" , LEAVE { txt = "LEAVE" }; +"loopo" , LOOP { txt = "LOOPO"; cond = X86O }; +"loopb" , LOOP { txt = "LOOPB"; cond = X86B }; +"loopc" , LOOP { txt = "LOOPC"; cond = X86B }; +"loopnae" , LOOP { txt = "LOOPNAE"; cond = X86B }; +"loope" , LOOP { txt = "LOOPE"; cond = X86E }; +"loopz" , LOOP { txt = "LOOPZ"; cond = X86E }; +"loopa" , LOOP { txt = "LOOPA"; cond = X86A }; +"loopnbe" , LOOP { txt = "LOOPNBE"; cond = X86A }; +"loops" , LOOP { txt = "LOOPS"; cond = X86S }; +"loopp" , LOOP { txt = "LOOPP"; cond = X86P }; +"looppe" , LOOP { txt = "LOOPPE"; cond = X86P }; +"loopl" , LOOP { txt = "LOOPL"; cond = X86L }; +"loopnge" , LOOP { txt = "LOOPNGE"; cond = X86L }; +"loopg" , LOOP { txt = "LOOPG"; cond = X86G }; +"loopnle" , LOOP { txt = "LOOPNLE"; cond = X86G }; +"loopno" , LOOP { txt = "LOOPNO"; cond = X86NO }; +"loopnb" , LOOP { txt = "LOOPNB"; cond = X86NB }; +"loopnc" , LOOP { txt = "LOOPNC"; cond = X86NB }; +"loopae" , LOOP { txt = "LOOPAE"; cond = X86NB }; +"loopne" , LOOP { txt = "LOOPNE"; cond = X86NE }; +"loopnz" , LOOP { txt = "LOOPNZ"; cond = X86NE }; +"loopna" , LOOP { txt = "LOOPNA"; cond = X86NA }; +"loopbe" , LOOP { txt = "LOOPBE"; cond = X86NA }; +"loopns" , LOOP { txt = "LOOPNS"; cond = X86NS }; +"loopnp" , LOOP { txt = "LOOPNP"; cond = X86NP }; +"looppo" , LOOP { txt = "LOOPPO"; cond = X86NP }; +"loopnl" , LOOP { txt = "LOOPNL"; cond = X86NL }; +"loopge" , LOOP { txt = "LOOPGE"; cond = X86NL }; +"loopng" , LOOP { txt = "LOOPNG"; cond = X86NG }; +"loople" , LOOP { txt = "LOOPLE"; cond = X86NG }; +"mfence" , MFENCE { txt = "MFENCE" }; +"dec" , MONOP { txt = "DEC"; op = X86DEC; sz = X86NONE }; +"inc" , MONOP { txt = "INC"; op = X86INC; sz = X86NONE }; +"not" , MONOP { txt = "NOT"; op = X86NOT; sz = X86NONE }; +"neg" , MONOP { txt = "NEG"; op = X86NEG; sz = X86NONE }; +"cmovo" , CMOV { txt = "CMOVO"; cond = X86O; sz = X86NONE }; +"cmovb" , CMOV { txt = "CMOVB"; cond = X86B; sz = X86NONE }; +"cmovc" , CMOV { txt = "CMOVC"; cond = X86B; sz = X86NONE }; +"cmovnae" , CMOV { txt = "CMOVNAE"; cond = X86B; sz = X86NONE }; +"cmove" , CMOV { txt = "CMOVE"; cond = X86E; sz = X86NONE }; +"cmovz" , CMOV { txt = "CMOVZ"; cond = X86E; sz = X86NONE }; +"cmova" , CMOV { txt = "CMOVA"; cond = X86A; sz = X86NONE }; +"cmovnbe" , CMOV { txt = "CMOVNBE"; cond = X86A; sz = X86NONE }; +"cmovs" , CMOV { txt = "CMOVS"; cond = X86S; sz = X86NONE }; +"cmovp" , CMOV { txt = "CMOVP"; cond = X86P; sz = X86NONE }; +"cmovpe" , CMOV { txt = "CMOVPE"; cond = X86P; sz = X86NONE }; +"cmovl" , CMOV { txt = "CMOVL"; cond = X86L; sz = X86NONE }; +"cmovnge" , CMOV { txt = "CMOVNGE"; cond = X86L; sz = X86NONE }; +"cmovg" , CMOV { txt = "CMOVG"; cond = X86G; sz = X86NONE }; +"cmovnle" , CMOV { txt = "CMOVNLE"; cond = X86G; sz = X86NONE }; +"cmovno" , CMOV { txt = "CMOVNO"; cond = X86NO; sz = X86NONE }; +"cmovnb" , CMOV { txt = "CMOVNB"; cond = X86NB; sz = X86NONE }; +"cmovnc" , CMOV { txt = "CMOVNC"; cond = X86NB; sz = X86NONE }; +"cmovae" , CMOV { txt = "CMOVAE"; cond = X86NB; sz = X86NONE }; +"cmovne" , CMOV { txt = "CMOVNE"; cond = X86NE; sz = X86NONE }; +"cmovnz" , CMOV { txt = "CMOVNZ"; cond = X86NE; sz = X86NONE }; +"cmovna" , CMOV { txt = "CMOVNA"; cond = X86NA; sz = X86NONE }; +"cmovbe" , CMOV { txt = "CMOVBE"; cond = X86NA; sz = X86NONE }; +"cmovns" , CMOV { txt = "CMOVNS"; cond = X86NS; sz = X86NONE }; +"cmovnp" , CMOV { txt = "CMOVNP"; cond = X86NP; sz = X86NONE }; +"cmovpo" , CMOV { txt = "CMOVPO"; cond = X86NP; sz = X86NONE }; +"cmovnl" , CMOV { txt = "CMOVNL"; cond = X86NL; sz = X86NONE }; +"cmovge" , CMOV { txt = "CMOVGE"; cond = X86NL; sz = X86NONE }; +"cmovng" , CMOV { txt = "CMOVNG"; cond = X86NG; sz = X86NONE }; +"cmovle" , CMOV { txt = "CMOVLE"; cond = X86NG; sz = X86NONE }; +"mov" , MOV { txt = "MOV"; sz = X86NONE }; +"movsx" , MOVSX { txt = "MOVSBW"; sz1 = X86NONE; sz2 = X86NONE }; +"movzx" , MOVZX { txt = "MOVZBW"; sz1 = X86NONE; sz2 = X86NONE }; +"mul" , MUL { txt = "MUL"; sz = X86NONE }; +"nop" , NOP { txt = "NOP" }; +"pop" , POP { txt = "POP" }; +"push" , PUSH { txt = "PUSH" }; +"ret" , PUSH { txt = "RET" }; +"seto" , SET { txt = "SETO"; cond = X86O }; +"setb" , SET { txt = "SETB"; cond = X86B }; +"setc" , SET { txt = "SETC"; cond = X86B }; +"setnae" , SET { txt = "SETNAE"; cond = X86B }; +"sete" , SET { txt = "SETE"; cond = X86E }; +"setz" , SET { txt = "SETZ"; cond = X86E }; +"seta" , SET { txt = "SETA"; cond = X86A }; +"setnbe" , SET { txt = "SETNBE"; cond = X86A }; +"sets" , SET { txt = "SETS"; cond = X86S }; +"setp" , SET { txt = "SETP"; cond = X86P }; +"setpe" , SET { txt = "SETPE"; cond = X86P }; +"setl" , SET { txt = "SETL"; cond = X86L }; +"setnge" , SET { txt = "SETNGE"; cond = X86L }; +"setg" , SET { txt = "SETG"; cond = X86G }; +"setnle" , SET { txt = "SETNLE"; cond = X86G }; +"setno" , SET { txt = "SETNO"; cond = X86NO }; +"setnb" , SET { txt = "SETNB"; cond = X86NB }; +"setnc" , SET { txt = "SETNC"; cond = X86NB }; +"setae" , SET { txt = "SETAE"; cond = X86NB }; +"setne" , SET { txt = "SETNE"; cond = X86NE }; +"setnz" , SET { txt = "SETNZ"; cond = X86NE }; +"setna" , SET { txt = "SETNA"; cond = X86NA }; +"setbe" , SET { txt = "SETBE"; cond = X86NA }; +"setns" , SET { txt = "SETNS"; cond = X86NS }; +"setnp" , SET { txt = "SETNP"; cond = X86NP }; +"setpo" , SET { txt = "SETPO"; cond = X86NP }; +"setnl" , SET { txt = "SETNL"; cond = X86NL }; +"setge" , SET { txt = "SETGE"; cond = X86NL }; +"setng" , SET { txt = "SETNG"; cond = X86NG }; +"setle" , SET { txt = "SETLE"; cond = X86NG }; +"stc" , STC { txt = "STC" }; +"xadd" , XADD { txt = "XADD"; sz = X86NONE }; +"xchg" , XCHG { txt = "XCHG"; sz = X86NONE }; diff --git a/old/x86/gen/map.hgen b/old/x86/gen/map.hgen new file mode 100644 index 00000000..843e8832 --- /dev/null +++ b/old/x86/gen/map.hgen @@ -0,0 +1,26 @@ +| `X86BINOP (locked, bop, sz, ds) -> `X86BINOP (locked, bop, sz, map_dest_src ds) +| `X86BITOP (locked, bop, sz, bo) -> `X86BITOP (locked, bop, sz, map_bit_offset bo) +| `X86CALL irm -> `X86CALL (map_imm_rm irm) +| `X86CLC -> `X86CLC +| `X86CMC -> `X86CMC +| `X86CMPXCHG (locked, sz, rm, r) -> `X86CMPXCHG (locked, sz, map_rm rm, map_reg r) +| `X86DIV (sz, rm) -> `X86DIV (sz, map_rm rm) +| `X86JCC x -> `X86JCC x +| `X86JMP rm -> `X86JMP (map_rm rm) +| `X86LEA (sz, ds) -> `X86LEA (sz, map_dest_src ds) +| `X86LEAVE -> `X86LEAVE +| `X86LOOP x -> `X86LOOP x +| `X86MFENCE -> `X86MFENCE +| `X86MONOP (locked, mop, sz, rm) -> `X86MONOP (locked, mop, sz, map_rm rm) +| `X86MOV (cnd, sz, ds) -> `X86MOV (cnd, sz, map_dest_src ds) +| `X86MOVSX (sz1, ds, sz2) -> `X86MOVSX (sz1, map_dest_src ds, sz2) +| `X86MOVZX (sz1, ds, sz2) -> `X86MOVZX (sz1, map_dest_src ds, sz2) +| `X86MUL (sz, rm) -> `X86MUL (sz, map_rm rm) +| `X86NOP -> `X86NOP +| `X86POP rm -> `X86POP (map_rm rm) +| `X86PUSH irm -> `X86PUSH (map_imm_rm irm) +| `X86RET i -> `X86RET i +| `X86SET (cnd, b, rm) -> `X86SET (cnd, b, map_rm rm) +| `X86STC -> `X86STC +| `X86XADD (locked, sz, rm, r) -> `X86XADD (locked, sz, map_rm rm, map_reg r) +| `X86XCHG (locked, sz, rm, r) -> `X86XCHG (locked, sz, map_rm rm, map_reg r) diff --git a/old/x86/gen/parser.hgen b/old/x86/gen/parser.hgen new file mode 100644 index 00000000..b3c9dc72 --- /dev/null +++ b/old/x86/gen/parser.hgen @@ -0,0 +1,600 @@ +| BINOP imm COMMA addr + { `X86BINOP (false, $1.op, suffix_size $1.sz, Rm_i ($4, bit64_of_int $2)) } +| LOCK BINOP imm COMMA addr + { check_binop_lockable $2.op + ; `X86BINOP (true, $2.op, suffix_size $2.sz, Rm_i ($5, bit64_of_int $3)) } +| BINOP imm COMMA breg + { check_size ($1.sz, X86BYTE) + ; `X86BINOP (false, $1.op, X86S8 ($4.high), Rm_i (Reg (IReg ($4.reg)), bit64_of_int $2)) + } +| BINOP breg COMMA breg + { check_size ($1.sz, X86BYTE) + ; check_byte_regs ($2, $4) + ; `X86BINOP (false, $1.op, X86S8 ($4.high), Rm_r (Reg (IReg ($4.reg)), IReg ($2.reg))) + } +| BINOP addr COMMA breg + { check_size ($1.sz, X86BYTE) + ; `X86BINOP (false, $1.op, X86S8 ($4.high), R_rm (IReg ($4.reg), $2)) + } +| BINOP breg COMMA addr + { check_size ($1.sz, X86BYTE) + ; `X86BINOP (false, $1.op, X86S8 ($2.high), Rm_r ($4, IReg ($2.reg))) + } +| LOCK BINOP breg COMMA addr + { check_binop_lockable $2.op + ; check_size ($2.sz, X86BYTE) + ; `X86BINOP (true, $2.op, X86S8 ($3.high), Rm_r ($5, IReg ($3.reg))) + } +| BINOP imm COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86BINOP (false, $1.op, X86S16, Rm_i (Reg $4, bit64_of_int $2)) + } +| BINOP wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86BINOP (false, $1.op, X86S16, Rm_r (Reg $4, $2)) + } +| BINOP addr COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86BINOP (false, $1.op, X86S16, R_rm ($4, $2)) + } +| BINOP wreg COMMA addr + { check_size ($1.sz, X86WORD) + ; `X86BINOP (false, $1.op, X86S16, Rm_r ($4, $2)) + } +| LOCK BINOP wreg COMMA addr + { check_binop_lockable $2.op + ; check_size ($2.sz, X86WORD) + ; `X86BINOP (true, $2.op, X86S16, Rm_r ($5, $3)) + } +| BINOP imm COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86BINOP (false, $1.op, X86S32, Rm_i (Reg $4, bit64_of_int $2)) + } +| BINOP lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86BINOP (false, $1.op, X86S32, Rm_r (Reg $4, $2)) + } +| BINOP addr COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86BINOP (false, $1.op, X86S32, R_rm ($4, $2)) + } +| BINOP lreg COMMA addr + { check_size ($1.sz, X86LONG) + ; `X86BINOP (false, $1.op, X86S32, Rm_r ($4, $2)) + } +| LOCK BINOP lreg COMMA addr + { check_binop_lockable $2.op + ; check_size ($2.sz, X86LONG) + ; `X86BINOP (true, $2.op, X86S32, Rm_r ($5, $3)) + } +| BINOP imm COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86BINOP (false, $1.op, X86S64, Rm_i (Reg $4, bit64_of_int $2)) + } +| BINOP qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86BINOP (false, $1.op, X86S64, Rm_r (Reg $4, $2)) + } +| BINOP addr COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86BINOP (false, $1.op, X86S64, R_rm ($4, $2)) + } +| BINOP qreg COMMA addr + { check_size ($1.sz, X86QUAD) + ; `X86BINOP (false, $1.op, X86S64, Rm_r ($4, $2)) + } +| LOCK BINOP qreg COMMA addr + { check_binop_lockable $2.op + ; check_size ($2.sz, X86QUAD) + ; `X86BINOP (true, $2.op, X86S64, Rm_r ($5, $3)) + } +| BITOP imm COMMA addr + { `X86BITOP (false, $1.op, suffix_size $1.sz, Bit_rm_imm ($4, $2)) + } +| LOCK BITOP imm COMMA addr + { `X86BITOP (true, $2.op, suffix_size $2.sz, Bit_rm_imm ($5, $3)) + } +| BITOP imm COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86BITOP (false, $1.op, X86S16, Bit_rm_imm (Reg $4, $2)) + } +| LOCK BITOP imm COMMA wreg + { check_size ($2.sz, X86WORD) + ; `X86BITOP (true, $2.op, X86S16, Bit_rm_imm (Reg $5, $3)) + } +| BITOP wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86BITOP (true, $1.op, X86S16, Bit_rm_r (Reg $4, $2)) + } +| LOCK BITOP wreg COMMA wreg + { check_size ($2.sz, X86WORD) + ; `X86BITOP (false, $2.op, X86S16, Bit_rm_r (Reg $5, $3)) + } +| BITOP wreg COMMA addr + { check_size ($1.sz, X86WORD) + ; `X86BITOP (false, $1.op, X86S16, Bit_rm_r ($4, $2)) + } +| LOCK BITOP wreg COMMA addr + { check_size ($2.sz, X86WORD) + ; `X86BITOP (true, $2.op, X86S16, Bit_rm_r ($5, $3)) + } +| BITOP imm COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86BITOP (false, $1.op, X86S32, Bit_rm_imm (Reg $4, $2)) + } +| LOCK BITOP imm COMMA lreg + { check_size ($2.sz, X86LONG) + ; `X86BITOP (true, $2.op, X86S32, Bit_rm_imm (Reg $5, $3)) + } +| BITOP lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86BITOP (false, $1.op, X86S32, Bit_rm_r (Reg $4, $2)) + } +| LOCK BITOP lreg COMMA lreg + { check_size ($2.sz, X86LONG) + ; `X86BITOP (true, $2.op, X86S32, Bit_rm_r (Reg $5, $3)) + } +| BITOP lreg COMMA addr + { check_size ($1.sz, X86LONG) + ; `X86BITOP (false, $1.op, X86S32, Bit_rm_r ($4, $2)) + } +| LOCK BITOP lreg COMMA addr + { check_size ($2.sz, X86LONG) + ; `X86BITOP (true, $2.op, X86S32, Bit_rm_r ($5, $3)) + } +| BITOP imm COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86BITOP (false, $1.op, X86S64, Bit_rm_imm (Reg $4, $2)) + } +| LOCK BITOP imm COMMA qreg + { check_size ($2.sz, X86QUAD) + ; `X86BITOP (true, $2.op, X86S64, Bit_rm_imm (Reg $5, $3)) + } +| BITOP qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86BITOP (false, $1.op, X86S64, Bit_rm_r (Reg $4, $2)) + } +| LOCK BITOP qreg COMMA qreg + { check_size ($2.sz, X86QUAD) + ; `X86BITOP (true, $2.op, X86S64, Bit_rm_r (Reg $5, $3)) + } +| BITOP qreg COMMA addr + { check_size ($1.sz, X86QUAD) + ; `X86BITOP (false, $1.op, X86S64, Bit_rm_r ($4, $2)) + } +| LOCK BITOP qreg COMMA addr + { check_size ($2.sz, X86QUAD) + ; `X86BITOP (true, $2.op, X86S64, Bit_rm_r ($5, $3)) + } +| CALL big_imm + { `X86CALL (Imm $2) } +| CALL addr + { `X86CALL (Rm $2) } +| CALL qreg + { `X86CALL (Rm (Reg $2)) } +| CLC + { `X86CLC } +| CMC + { `X86CMC } +| CMOV addr COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86MOV ($1.cond, X86S16, R_rm ($4, $2)) + } +| CMOV addr COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86MOV ($1.cond, X86S32, R_rm ($4, $2)) + } +| CMOV addr COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86MOV ($1.cond, X86S64, R_rm ($4, $2)) + } +| CMOV wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86MOV ($1.cond, X86S16, R_rm ($4, Reg $2)) + } +| CMOV lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86MOV ($1.cond, X86S32, R_rm ($4, Reg $2)) + } +| CMOV qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86MOV ($1.cond, X86S64, R_rm ($4, Reg $2)) + } +| CMPXCHG breg COMMA breg + { check_size ($1.sz, X86BYTE) + ; check_byte_regs ($2, $4) + ; `X86CMPXCHG (false, X86S8 ($2.high), Reg (IReg ($4.reg)), IReg ($2.reg)) + } +| CMPXCHG breg COMMA addr + { check_size ($1.sz, X86BYTE) + ; `X86CMPXCHG (false, X86S8 ($2.high), $4, IReg ($2.reg)) + } +| LOCK CMPXCHG breg COMMA addr + { check_size ($2.sz, X86BYTE) + ; `X86CMPXCHG (true, X86S8 ($3.high), $5, IReg ($3.reg)) + } +| CMPXCHG wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86CMPXCHG (false, X86S16, Reg $4, $2) + } +| CMPXCHG wreg COMMA addr + { check_size ($1.sz, X86WORD) + ; `X86CMPXCHG (false, X86S16, $4, $2) + } +| LOCK CMPXCHG wreg COMMA addr + { check_size ($2.sz, X86WORD) + ; `X86CMPXCHG (true, X86S16, $5, $3) + } +| CMPXCHG lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86CMPXCHG (false, X86S32, Reg $4, $2) + } +| CMPXCHG lreg COMMA addr + { check_size ($1.sz, X86LONG) + ; `X86CMPXCHG (false, X86S32, $4, $2) + } +| LOCK CMPXCHG lreg COMMA addr + { check_size ($2.sz, X86LONG) + ; `X86CMPXCHG (true, X86S32, $5, $3) + } +| CMPXCHG qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86CMPXCHG (false, X86S64, Reg $4, $2) + } +| CMPXCHG qreg COMMA addr + { check_size ($1.sz, X86QUAD) + ; `X86CMPXCHG (false, X86S64, $4, $2) + } +| LOCK CMPXCHG qreg COMMA addr + { check_size ($2.sz, X86QUAD) + ; `X86CMPXCHG (true, X86S64, $5, $3) + } +| DIV addr + { `X86DIV (suffix_size $1.sz, $2) } +| DIV breg + { check_size ($1.sz, X86BYTE) + ; `X86DIV (X86S8 ($2.high), Reg (IReg ($2.reg))) + } +| DIV wreg + { check_size ($1.sz, X86WORD) + ; `X86DIV (X86S16, Reg $2) + } +| DIV lreg + { check_size ($1.sz, X86LONG) + ; `X86DIV (X86S32, Reg $2) + } +| DIV qreg + { check_size ($1.sz, X86QUAD) + ; `X86DIV (X86S64, Reg $2) + } +| JCC big_num + { `X86JCC ($1.cond, $2) } +| JMP big_num + { `X86JCC (X86ALWAYS, $2) } +| JMP addr + { `X86JMP $2 } +| JMP qreg + { `X86JMP (Reg $2) } +| LEA addr COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86LEA (X86S16, R_rm ($4, $2)) + } +| LEA addr COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86LEA (X86S32, R_rm ($4, $2)) + } +| LEA addr COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86LEA (X86S64, R_rm ($4, $2)) + } +| LEAVE + { `X86LEAVE } +| LOOP big_num + { `X86LOOP ($1.cond, $2) } +| MFENCE + { `X86MFENCE } +| MONOP addr + { `X86MONOP (false, $1.op, suffix_size $1.sz, $2) } +| LOCK MONOP addr + { `X86MONOP (true, $2.op, suffix_size $2.sz, $3) } +| MONOP breg + { check_size ($1.sz, X86BYTE) + ; `X86MONOP (false, $1.op, X86S8 ($2.high), Reg (IReg $2.reg)) + } +| MONOP wreg + { check_size ($1.sz, X86WORD) + ; `X86MONOP (false, $1.op, X86S16, Reg $2) + } +| MONOP lreg + { check_size ($1.sz, X86LONG) + ; `X86MONOP (false, $1.op, X86S32, Reg $2) + } +| MONOP qreg + { check_size ($1.sz, X86QUAD) + ; `X86MONOP (false, $1.op, X86S64, Reg $2) + } +| MOV big_imm COMMA addr + { `X86MOV (X86ALWAYS, suffix_size $1.sz, Rm_i ($4, $2)) } +| MOV imm COMMA breg + { check_size ($1.sz, X86BYTE) + ; `X86MOV (X86ALWAYS, X86S8 ($4.high), Rm_i (Reg (IReg $4.reg), bit64_of_int $2)) + } +| MOV breg COMMA breg + { check_size ($1.sz, X86BYTE) + ; check_byte_regs ($2, $4) + ; `X86MOV (X86ALWAYS, X86S8 ($4.high), Rm_r (Reg (IReg $4.reg), (IReg $2.reg))) + } +| MOV addr COMMA breg + { check_size ($1.sz, X86BYTE) + ; `X86MOV (X86ALWAYS, X86S8 ($4.high), R_rm (IReg $4.reg, $2)) + } +| MOV breg COMMA addr + { check_size ($1.sz, X86BYTE) + ; `X86MOV (X86ALWAYS, X86S8 ($2.high), Rm_r ($4, IReg $2.reg)) + } +| MOV imm COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86MOV (X86ALWAYS, X86S16, Rm_i (Reg $4, bit64_of_int $2)) + } +| MOV wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86MOV (X86ALWAYS, X86S16, Rm_r (Reg $4, $2)) + } +| MOV addr COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86MOV (X86ALWAYS, X86S16, R_rm ($4, $2)) + } +| MOV wreg COMMA addr + { check_size ($1.sz, X86WORD) + ; `X86MOV (X86ALWAYS, X86S16, Rm_r ($4, $2)) + } +| MOV imm COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86MOV (X86ALWAYS, X86S32, Rm_i (Reg $4, bit64_of_int $2)) + } +| MOV lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86MOV (X86ALWAYS, X86S32, Rm_r (Reg $4, $2)) + } +| MOV addr COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86MOV (X86ALWAYS, X86S32, R_rm ($4, $2)) + } +| MOV lreg COMMA addr + { check_size ($1.sz, X86LONG) + ; `X86MOV (X86ALWAYS, X86S32, Rm_r ($4, $2)) + } +| MOV big_imm COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86MOV (X86ALWAYS, X86S64, Rm_i (Reg $4, $2)) + } +| MOV qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; if $1.txt = "MOVABS" then failwith "movabs expects and immediate" else () + ; `X86MOV (X86ALWAYS, X86S64, Rm_r (Reg $4, $2)) + } +| MOV addr COMMA qreg + { check_size ($1.sz, X86QUAD) + ; if $1.txt = "MOVABS" then failwith "movabs expects and immediate" else () + ; `X86MOV (X86ALWAYS, X86S64, R_rm ($4, $2)) + } +| MOV qreg COMMA addr + { check_size ($1.sz, X86QUAD) + ; if $1.txt = "MOVABS" then failwith "movabs expects and immediate" else () + ; `X86MOV (X86ALWAYS, X86S64, Rm_r ($4, $2)) + } +| MOVSX breg COMMA wreg + { check_size ($1.sz1, X86BYTE) + ; check_size ($1.sz2, X86WORD) + ; `X86MOVSX (X86S16, R_rm ($4, Reg (IReg $2.reg)), X86S8 $2.high) + } +| MOVSX breg COMMA lreg + { check_size ($1.sz1, X86BYTE) + ; check_size ($1.sz2, X86LONG) + ; `X86MOVSX (X86S32, R_rm ($4, Reg (IReg $2.reg)), X86S8 $2.high) + } +| MOVSX breg COMMA qreg + { check_size ($1.sz1, X86BYTE) + ; check_size ($1.sz2, X86QUAD) + ; `X86MOVSX (X86S64, R_rm ($4, Reg (IReg $2.reg)), X86S8 $2.high) + } +| MOVSX wreg COMMA lreg + { check_size ($1.sz1, X86WORD) + ; check_size ($1.sz2, X86LONG) + ; `X86MOVSX (X86S32, R_rm ($4, Reg $2), X86S16) + } +| MOVSX wreg COMMA qreg + { check_size ($1.sz1, X86WORD) + ; check_size ($1.sz2, X86QUAD) + ; `X86MOVSX (X86S64, R_rm ($4, Reg $2), X86S16) + } +| MOVSX lreg COMMA qreg + { check_size ($1.sz1, X86LONG) + ; check_size ($1.sz2, X86QUAD) + ; `X86MOVSX (X86S64, R_rm ($4, Reg $2), X86S32) + } +| MOVSX addr COMMA wreg + { check_size ($1.sz2, X86WORD) + ; `X86MOVSX (X86S16, R_rm ($4, $2), suffix_size $1.sz1) + } +| MOVSX addr COMMA lreg + { check_size ($1.sz2, X86LONG) + ; `X86MOVSX (X86S32, R_rm ($4, $2), suffix_size $1.sz1) + } +| MOVSX addr COMMA qreg + { check_size ($1.sz2, X86QUAD) + ; `X86MOVSX (X86S64, R_rm ($4, $2), suffix_size $1.sz1) + } +| MOVZX breg COMMA wreg + { check_size ($1.sz1, X86BYTE) + ; check_size ($1.sz2, X86WORD) + ; `X86MOVZX (X86S16, R_rm ($4, Reg (IReg $2.reg)), X86S8 $2.high) + } +| MOVZX breg COMMA lreg + { check_size ($1.sz1, X86BYTE) + ; check_size ($1.sz2, X86LONG) + ; `X86MOVZX (X86S32, R_rm ($4, Reg (IReg $2.reg)), X86S8 $2.high) + } +| MOVZX breg COMMA qreg + { check_size ($1.sz1, X86BYTE) + ; check_size ($1.sz2, X86QUAD) + ; `X86MOVZX (X86S64, R_rm ($4, Reg (IReg $2.reg)), X86S8 $2.high) + } +| MOVZX wreg COMMA lreg + { check_size ($1.sz1, X86WORD) + ; check_size ($1.sz2, X86LONG) + ; `X86MOVZX (X86S32, R_rm ($4, Reg $2), X86S16) + } +| MOVZX wreg COMMA qreg + { check_size ($1.sz1, X86WORD) + ; check_size ($1.sz2, X86QUAD) + ; `X86MOVZX (X86S64, R_rm ($4, Reg $2), X86S16) + } +| MOVZX addr COMMA wreg + { check_size ($1.sz2, X86WORD) + ; `X86MOVZX (X86S16, R_rm ($4, $2), suffix_size $1.sz1) + } +| MOVZX addr COMMA lreg + { check_size ($1.sz2, X86LONG) + ; `X86MOVZX (X86S32, R_rm ($4, $2), suffix_size $1.sz1) + } +| MOVZX addr COMMA qreg + { check_size ($1.sz2, X86QUAD) + ; `X86MOVZX (X86S64, R_rm ($4, $2), suffix_size $1.sz1) + } +| MUL addr + { `X86MUL (suffix_size $1.sz, $2) } +| MUL breg + { check_size ($1.sz, X86BYTE) + ; `X86MUL (X86S8 ($2.high), Reg (IReg $2.reg)) + } +| MUL wreg + { check_size ($1.sz, X86WORD) + ; `X86MUL (X86S16, Reg $2) + } +| MUL lreg + { check_size ($1.sz, X86LONG) + ; `X86MUL (X86S32, Reg $2) + } +| MUL qreg + { check_size ($1.sz, X86QUAD) + ; `X86MUL (X86S64, Reg $2) + } +| NOP + { `X86NOP } +| POP qreg + { `X86POP (Reg $2) } +| POP addr + { `X86POP $2 } +| PUSH big_imm + { `X86PUSH (Imm $2) } +| PUSH addr + { `X86PUSH (Rm $2) } +| PUSH qreg + { `X86PUSH (Rm (Reg $2)) } +| RET big_imm + { `X86RET $2 } +| SET breg + { `X86SET ($1.cond, $2.high, Reg (IReg $2.reg)) } +| SET addr + { `X86SET ($1.cond, false, $2) } +| STC + { `X86STC } +| XADD breg COMMA breg + { check_size ($1.sz, X86BYTE) + ; check_byte_regs ($2, $4) + ; `X86XADD (false, X86S8 ($2.high), Reg (IReg $4.reg), (IReg $2.reg)) + } +| XADD breg COMMA addr + { check_size ($1.sz, X86BYTE) + ; `X86XADD (false, X86S8 ($2.high), $4, (IReg $2.reg)) + } +| LOCK XADD breg COMMA addr + { check_size ($2.sz, X86BYTE) + ; `X86XADD (true, X86S8 ($3.high), $5, (IReg $3.reg)) + } +| XADD wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86XADD (false, X86S16, Reg $4, $2) + } +| XADD wreg COMMA addr + { check_size ($1.sz, X86WORD) + ; `X86XADD (false, X86S16, $4, $2) + } +| LOCK XADD wreg COMMA addr + { check_size ($2.sz, X86WORD) + ; `X86XADD (true, X86S16, $5, $3) + } +| XADD lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86XADD (false, X86S32, Reg $4, $2) + } +| XADD lreg COMMA addr + { check_size ($1.sz, X86LONG) + ; `X86XADD (false, X86S32, $4, $2) + } +| LOCK XADD lreg COMMA addr + { check_size ($2.sz, X86LONG) + ; `X86XADD (true, X86S32, $5, $3) + } +| XADD qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86XADD (false, X86S64, Reg $4, $2) + } +| XADD qreg COMMA addr + { check_size ($1.sz, X86QUAD) + ; `X86XADD (false, X86S64, $4, $2) + } +| LOCK XADD qreg COMMA addr + { check_size ($2.sz, X86QUAD) + ; `X86XADD (true, X86S64, $5, $3) + } +| XCHG breg COMMA breg + { check_size ($1.sz, X86BYTE) + ; check_byte_regs ($2, $4) + ; `X86XCHG (false, X86S8 ($2.high), Reg (IReg $4.reg), IReg $2.reg) + } +| XCHG breg COMMA addr + { check_size ($1.sz, X86BYTE) + ; `X86XCHG (false, X86S8 ($2.high), $4, (IReg $2.reg)) + } +| LOCK XCHG breg COMMA addr + { check_size ($2.sz, X86BYTE) + ; `X86XCHG (true, X86S8 ($3.high), $5, (IReg $3.reg)) + } +| XCHG wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86XCHG (false, X86S16, Reg $4, $2) + } +| XCHG wreg COMMA addr + { check_size ($1.sz, X86WORD) + ; `X86XCHG (false, X86S16, $4, $2) + } +| LOCK XCHG wreg COMMA addr + { check_size ($2.sz, X86WORD) + ; `X86XCHG (true, X86S16, $5, $3) + } +| XCHG lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86XCHG (false, X86S32, Reg $4, $2) + } +| XCHG lreg COMMA addr + { check_size ($1.sz, X86LONG) + ; `X86XCHG (false, X86S32, $4, $2) + } +| LOCK XCHG lreg COMMA addr + { check_size ($2.sz, X86LONG) + ; `X86XCHG (true, X86S32, $5, $3) + } +| XCHG qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86XCHG (false, X86S64, Reg $4, $2) + } +| XCHG qreg COMMA addr + { check_size ($1.sz, X86QUAD) + ; `X86XCHG (false, X86S64, $4, $2) + } +| LOCK XCHG qreg COMMA addr + { check_size ($2.sz, X86QUAD) + ; `X86XCHG (true, X86S64, $5, $3) + } diff --git a/old/x86/gen/parser_intel.hgen b/old/x86/gen/parser_intel.hgen new file mode 100644 index 00000000..72fa0ede --- /dev/null +++ b/old/x86/gen/parser_intel.hgen @@ -0,0 +1,601 @@ +| BINOP addr COMMA imm + { `X86BINOP (false, $1.op, suffix_size $1.sz, Rm_i ($2, bit64_of_int $4)) + (* XXX size is ambigious -- should require anotation *) } +| LOCK BINOP addr COMMA imm + { check_binop_lockable $2.op + ; `X86BINOP (true, $2.op, suffix_size $2.sz, Rm_i ($3, bit64_of_int $5)) } +| BINOP breg COMMA imm + { check_size ($1.sz, X86BYTE) + ; `X86BINOP (false, $1.op, X86S8 ($2.high), Rm_i (Reg (IReg ($2.reg)), bit64_of_int $4)) + } +| BINOP breg COMMA breg + { check_size ($1.sz, X86BYTE) + ; check_byte_regs ($2, $4) + ; `X86BINOP (false, $1.op, X86S8 ($2.high), Rm_r (Reg (IReg ($2.reg)), IReg ($4.reg))) + } +| BINOP addr COMMA breg + { check_size ($1.sz, X86BYTE) + ; `X86BINOP (false, $1.op, X86S8 ($4.high), Rm_r ($2, IReg ($4.reg))) + } +| LOCK BINOP addr COMMA breg + { check_binop_lockable $2.op; + check_size ($2.sz, X86BYTE) + ; `X86BINOP (true, $2.op, X86S8 ($5.high), Rm_r ($3, IReg ($5.reg))) + } +| BINOP breg COMMA addr + { check_size ($1.sz, X86BYTE) + ; `X86BINOP (false, $1.op, X86S8 ($2.high), R_rm (IReg ($2.reg), $4)) + } +| BINOP wreg COMMA imm + { check_size ($1.sz, X86WORD) + ; `X86BINOP (false, $1.op, X86S16, Rm_i (Reg $2, bit64_of_int $4)) + } +| BINOP wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86BINOP (false, $1.op, X86S16, Rm_r (Reg $2, $4)) + } +| BINOP addr COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86BINOP (false, $1.op, X86S16, Rm_r ($2, $4)) + } +| LOCK BINOP addr COMMA wreg + { check_binop_lockable $2.op; + check_size ($2.sz, X86WORD) + ; `X86BINOP (true, $2.op, X86S16, Rm_r ($3, $5)) + } +| BINOP wreg COMMA addr + { check_size ($1.sz, X86WORD) + ; `X86BINOP (false, $1.op, X86S16, R_rm ($2, $4)) + } +| BINOP lreg COMMA imm + { check_size ($1.sz, X86LONG) + ; `X86BINOP (false, $1.op, X86S32, Rm_i (Reg $2, bit64_of_int $4)) + } +| BINOP lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86BINOP (false, $1.op, X86S32, Rm_r (Reg $2, $4)) + } +| BINOP addr COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86BINOP (false, $1.op, X86S32, Rm_r ($2, $4)) + } +| LOCK BINOP addr COMMA lreg + { check_binop_lockable $2.op; + check_size ($2.sz, X86LONG) + ; `X86BINOP (true, $2.op, X86S32, Rm_r ($3, $5)) + } +| BINOP lreg COMMA addr + { check_size ($1.sz, X86LONG) + ; `X86BINOP (false, $1.op, X86S32, R_rm ($2, $4)) + } +| BINOP qreg COMMA imm + { check_size ($1.sz, X86QUAD) + ; `X86BINOP (false, $1.op, X86S64, Rm_i (Reg $2, bit64_of_int $4)) + } +| BINOP qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86BINOP (false, $1.op, X86S64, Rm_r (Reg $2, $4)) + } +| BINOP addr COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86BINOP (false, $1.op, X86S64, Rm_r ($2, $4)) + } +| LOCK BINOP addr COMMA qreg + { check_binop_lockable $2.op; + check_size ($2.sz, X86QUAD) + ; `X86BINOP (true, $2.op, X86S64, Rm_r ($3, $5)) + } +| BINOP qreg COMMA addr + { check_size ($1.sz, X86QUAD) + ; `X86BINOP (false, $1.op, X86S64, R_rm ($2, $4)) + } +| BITOP addr COMMA imm + { `X86BITOP (false, $1.op, suffix_size $1.sz, Bit_rm_imm ($2, $4)) + } +| LOCK BITOP addr COMMA imm + { `X86BITOP (true, $2.op, suffix_size $2.sz, Bit_rm_imm ($3, $5)) + } +| BITOP wreg COMMA imm + { check_size ($1.sz, X86WORD) + ; `X86BITOP (false, $1.op, X86S16, Bit_rm_imm (Reg $2, $4)) + } +| LOCK BITOP wreg COMMA imm + { check_size ($2.sz, X86WORD) + ; `X86BITOP (true, $2.op, X86S16, Bit_rm_imm (Reg $3, $5)) + } +| BITOP wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86BITOP (true, $1.op, X86S16, Bit_rm_r (Reg $2, $4)) + } +| LOCK BITOP wreg COMMA wreg + { check_size ($2.sz, X86WORD) + ; `X86BITOP (false, $2.op, X86S16, Bit_rm_r (Reg $3, $5)) + } +| BITOP addr COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86BITOP (false, $1.op, X86S16, Bit_rm_r ($2, $4)) + } +| LOCK BITOP addr COMMA wreg + { check_size ($2.sz, X86WORD) + ; `X86BITOP (true, $2.op, X86S16, Bit_rm_r ($3, $5)) + } +| BITOP lreg COMMA imm + { check_size ($1.sz, X86LONG) + ; `X86BITOP (false, $1.op, X86S32, Bit_rm_imm (Reg $2, $4)) + } +| LOCK BITOP lreg COMMA imm + { check_size ($2.sz, X86LONG) + ; `X86BITOP (true, $2.op, X86S32, Bit_rm_imm (Reg $3, $5)) + } +| BITOP lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86BITOP (false, $1.op, X86S32, Bit_rm_r (Reg $2, $4)) + } +| LOCK BITOP lreg COMMA lreg + { check_size ($2.sz, X86LONG) + ; `X86BITOP (true, $2.op, X86S32, Bit_rm_r (Reg $3, $5)) + } +| BITOP addr COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86BITOP (false, $1.op, X86S32, Bit_rm_r ($2, $4)) + } +| LOCK BITOP addr COMMA lreg + { check_size ($2.sz, X86LONG) + ; `X86BITOP (true, $2.op, X86S32, Bit_rm_r ($3, $5)) + } +| BITOP qreg COMMA imm + { check_size ($1.sz, X86QUAD) + ; `X86BITOP (false, $1.op, X86S64, Bit_rm_imm (Reg $2, $4)) + } +| LOCK BITOP qreg COMMA imm + { check_size ($2.sz, X86QUAD) + ; `X86BITOP (true, $2.op, X86S64, Bit_rm_imm (Reg $3, $5)) + } +| BITOP qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86BITOP (false, $1.op, X86S64, Bit_rm_r (Reg $2, $4)) + } +| LOCK BITOP qreg COMMA qreg + { check_size ($2.sz, X86QUAD) + ; `X86BITOP (true, $2.op, X86S64, Bit_rm_r (Reg $3, $5)) + } +| BITOP addr COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86BITOP (false, $1.op, X86S64, Bit_rm_r ($2, $4)) + } +| LOCK BITOP addr COMMA qreg + { check_size ($2.sz, X86QUAD) + ; `X86BITOP (true, $2.op, X86S64, Bit_rm_r ($3, $5)) + } +| CALL big_imm + { `X86CALL (Imm $2) } +| CALL addr + { `X86CALL (Rm $2) } +| CALL qreg + { `X86CALL (Rm (Reg $2)) } +| CLC + { `X86CLC } +| CMC + { `X86CMC } +| CMOV wreg COMMA addr + { check_size ($1.sz, X86WORD) + ; `X86MOV ($1.cond, X86S16, R_rm ($2, $4)) + } +| CMOV lreg COMMA addr + { check_size ($1.sz, X86LONG) + ; `X86MOV ($1.cond, X86S32, R_rm ($2, $4)) + } +| CMOV qreg COMMA addr + { check_size ($1.sz, X86QUAD) + ; `X86MOV ($1.cond, X86S64, R_rm ($2, $4)) + } +| CMOV wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86MOV ($1.cond, X86S16, R_rm ($2, Reg $4)) + } +| CMOV lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86MOV ($1.cond, X86S32, R_rm ($2, Reg $4)) + } +| CMOV qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86MOV ($1.cond, X86S64, R_rm ($2, Reg $4)) + } +| CMPXCHG breg COMMA breg + { check_size ($1.sz, X86BYTE) + ; check_byte_regs ($2, $4) + ; `X86CMPXCHG (false, X86S8 ($2.high), Reg (IReg ($2.reg)), IReg ($4.reg)) + } +| CMPXCHG addr COMMA breg + { check_size ($1.sz, X86BYTE) + ; `X86CMPXCHG (false, X86S8 ($4.high), $2, IReg ($4.reg)) + } +| LOCK CMPXCHG addr COMMA breg + { check_size ($2.sz, X86BYTE) + ; `X86CMPXCHG (true, X86S8 ($5.high), $3, IReg ($5.reg)) + } +| CMPXCHG wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86CMPXCHG (false, X86S16, Reg $2, $4) + } +| CMPXCHG addr COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86CMPXCHG (false, X86S16, $2, $4) + } +| LOCK CMPXCHG addr COMMA wreg + { check_size ($2.sz, X86WORD) + ; `X86CMPXCHG (true, X86S16, $3, $5) + } +| CMPXCHG lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86CMPXCHG (false, X86S32, Reg $2, $4) + } +| CMPXCHG addr COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86CMPXCHG (false, X86S32, $2, $4) + } +| LOCK CMPXCHG addr COMMA lreg + { check_size ($2.sz, X86LONG) + ; `X86CMPXCHG (true, X86S32, $3, $5) + } +| CMPXCHG qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86CMPXCHG (false, X86S64, Reg $2, $4) + } +| CMPXCHG addr COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86CMPXCHG (false, X86S64, $2, $4) + } +| LOCK CMPXCHG addr COMMA qreg + { check_size ($2.sz, X86QUAD) + ; `X86CMPXCHG (true, X86S64, $3, $5) + } +| DIV addr + { `X86DIV (suffix_size $1.sz, $2) } +| DIV breg + { check_size ($1.sz, X86BYTE) + ; `X86DIV (X86S8 ($2.high), Reg (IReg ($2.reg))) + } +| DIV wreg + { check_size ($1.sz, X86WORD) + ; `X86DIV (X86S16, Reg $2) + } +| DIV lreg + { check_size ($1.sz, X86LONG) + ; `X86DIV (X86S32, Reg $2) + } +| DIV qreg + { check_size ($1.sz, X86QUAD) + ; `X86DIV (X86S64, Reg $2) + } +| JCC big_num + { `X86JCC ($1.cond, $2) } +| JMP big_num + { `X86JCC (X86ALWAYS, $2) } +| JMP addr + { `X86JMP $2 } +| JMP qreg + { `X86JMP (Reg $2) } +| LEA wreg COMMA addr + { check_size ($1.sz, X86WORD) + ; `X86LEA (X86S16, R_rm ($2, $4)) + } +| LEA lreg COMMA addr + { check_size ($1.sz, X86LONG) + ; `X86LEA (X86S32, R_rm ($2, $4)) + } +| LEA qreg COMMA addr + { check_size ($1.sz, X86QUAD) + ; `X86LEA (X86S64, R_rm ($2, $4)) + } +| LEAVE + { `X86LEAVE } +| LOOP big_num + { `X86LOOP ($1.cond, $2) } +| MFENCE + { `X86MFENCE } +| MONOP addr + { `X86MONOP (false, $1.op, suffix_size $1.sz, $2) } +| LOCK MONOP addr + { `X86MONOP (true, $2.op, suffix_size $2.sz, $3) } +| MONOP breg + { check_size ($1.sz, X86BYTE) + ; `X86MONOP (false, $1.op, X86S8 ($2.high), Reg (IReg $2.reg)) + } +| MONOP wreg + { check_size ($1.sz, X86WORD) + ; `X86MONOP (false, $1.op, X86S16, Reg $2) + } +| MONOP lreg + { check_size ($1.sz, X86LONG) + ; `X86MONOP (false, $1.op, X86S32, Reg $2) + } +| MONOP qreg + { check_size ($1.sz, X86QUAD) + ; `X86MONOP (false, $1.op, X86S64, Reg $2) + } +| MOV addr COMMA big_imm + { `X86MOV (X86ALWAYS, suffix_size $1.sz, Rm_i ($2, $4)) } +| MOV breg COMMA imm + { check_size ($1.sz, X86BYTE) + ; `X86MOV (X86ALWAYS, X86S8 ($2.high), Rm_i (Reg (IReg $2.reg), bit64_of_int $4)) + } +| MOV breg COMMA breg + { check_size ($1.sz, X86BYTE) + ; check_byte_regs ($2, $4) + ; `X86MOV (X86ALWAYS, X86S8 ($2.high), Rm_r (Reg (IReg $2.reg), (IReg $4.reg))) + } +| MOV addr COMMA breg + { check_size ($1.sz, X86BYTE) + ; `X86MOV (X86ALWAYS, X86S8 ($4.high), Rm_r ($2, IReg $4.reg)) + } +| MOV breg COMMA addr + { check_size ($1.sz, X86BYTE) + ; `X86MOV (X86ALWAYS, X86S8 ($2.high), R_rm (IReg $2.reg, $4)) + } +| MOV wreg COMMA imm + { check_size ($1.sz, X86WORD) + ; `X86MOV (X86ALWAYS, X86S16, Rm_i (Reg $2, bit64_of_int $4)) + } +| MOV wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86MOV (X86ALWAYS, X86S16, Rm_r (Reg $2, $4)) + } +| MOV addr COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86MOV (X86ALWAYS, X86S16, Rm_r ($2, $4)) + } +| MOV wreg COMMA addr + { check_size ($1.sz, X86WORD) + ; `X86MOV (X86ALWAYS, X86S16, R_rm ($2, $4)) + } +| MOV lreg COMMA imm + { check_size ($1.sz, X86LONG) + ; `X86MOV (X86ALWAYS, X86S32, Rm_i (Reg $2, bit64_of_int $4)) + } +| MOV lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86MOV (X86ALWAYS, X86S32, Rm_r (Reg $2, $4)) + } +| MOV addr COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86MOV (X86ALWAYS, X86S32, Rm_r ($2, $4)) + } +| MOV lreg COMMA addr + { check_size ($1.sz, X86LONG) + ; `X86MOV (X86ALWAYS, X86S32, R_rm ($2, $4)) + } +| MOV qreg COMMA big_imm + { check_size ($1.sz, X86QUAD) + ; `X86MOV (X86ALWAYS, X86S64, Rm_i (Reg $2, $4)) + } +| MOV qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; if $1.txt = "MOVABS" then failwith "movabs expects an immediate" else () + ; `X86MOV (X86ALWAYS, X86S64, Rm_r (Reg $2, $4)) + } +| MOV addr COMMA qreg + { check_size ($1.sz, X86QUAD) + ; if $1.txt = "MOVABS" then failwith "movabs expects an immediate" else () + ; `X86MOV (X86ALWAYS, X86S64, Rm_r ($2, $4)) + } +| MOV qreg COMMA addr + { check_size ($1.sz, X86QUAD) + ; if $1.txt = "MOVABS" then failwith "movabs expects an immediate" else () + ; `X86MOV (X86ALWAYS, X86S64, R_rm ($2, $4)) + } +| MOVSX wreg COMMA breg + { check_size ($1.sz1, X86BYTE) + ; check_size ($1.sz2, X86WORD) + ; `X86MOVSX (X86S16, R_rm ($2, Reg (IReg $4.reg)), X86S8 $4.high) + } +| MOVSX lreg COMMA breg + { check_size ($1.sz1, X86BYTE) + ; check_size ($1.sz2, X86LONG) + ; `X86MOVSX (X86S32, R_rm ($2, Reg (IReg $4.reg)), X86S8 $4.high) + } +| MOVSX qreg COMMA breg + { check_size ($1.sz1, X86BYTE) + ; check_size ($1.sz2, X86QUAD) + ; `X86MOVSX (X86S64, R_rm ($2, Reg (IReg $4.reg)), X86S8 $4.high) + } +| MOVSX lreg COMMA wreg + { check_size ($1.sz1, X86WORD) + ; check_size ($1.sz2, X86LONG) + ; `X86MOVSX (X86S32, R_rm ($2, Reg $4), X86S16) + } +| MOVSX qreg COMMA wreg + { check_size ($1.sz1, X86WORD) + ; check_size ($1.sz2, X86QUAD) + ; `X86MOVSX (X86S64, R_rm ($2, Reg $4), X86S16) + } +| MOVSX qreg COMMA lreg + { check_size ($1.sz1, X86LONG) + ; check_size ($1.sz2, X86QUAD) + ; `X86MOVSX (X86S64, R_rm ($2, Reg $4), X86S32) + } +| MOVSX wreg COMMA addr + { check_size ($1.sz2, X86WORD) + ; `X86MOVSX (X86S16, R_rm ($2, $4), suffix_size $1.sz1) (* XXX size *) + } +| MOVSX lreg COMMA addr + { check_size ($1.sz2, X86LONG) + ; `X86MOVSX (X86S32, R_rm ($2, $4), suffix_size $1.sz1) + } +| MOVSX qreg COMMA addr + { check_size ($1.sz2, X86QUAD) + ; `X86MOVSX (X86S64, R_rm ($2, $4), suffix_size $1.sz1) + } +| MOVZX wreg COMMA breg + { check_size ($1.sz1, X86BYTE) + ; check_size ($1.sz2, X86WORD) + ; `X86MOVZX (X86S16, R_rm ($2, Reg (IReg $4.reg)), X86S8 $4.high) + } +| MOVZX lreg COMMA breg + { check_size ($1.sz1, X86BYTE) + ; check_size ($1.sz2, X86LONG) + ; `X86MOVZX (X86S32, R_rm ($2, Reg (IReg $4.reg)), X86S8 $4.high) + } +| MOVZX qreg COMMA breg + { check_size ($1.sz1, X86BYTE) + ; check_size ($1.sz2, X86QUAD) + ; `X86MOVZX (X86S64, R_rm ($2, Reg (IReg $4.reg)), X86S8 $4.high) + } +| MOVZX lreg COMMA wreg + { check_size ($1.sz1, X86WORD) + ; check_size ($1.sz2, X86LONG) + ; `X86MOVZX (X86S32, R_rm ($2, Reg $4), X86S16) + } +| MOVZX qreg COMMA wreg + { check_size ($1.sz1, X86WORD) + ; check_size ($1.sz2, X86QUAD) + ; `X86MOVZX (X86S64, R_rm ($2, Reg $4), X86S16) + } +| MOVZX wreg COMMA addr + { check_size ($1.sz2, X86WORD) + ; `X86MOVZX (X86S16, R_rm ($2, $4), suffix_size $1.sz1) (* XXX size *) + } +| MOVZX lreg COMMA addr + { check_size ($1.sz2, X86LONG) + ; `X86MOVZX (X86S32, R_rm ($2, $4), suffix_size $1.sz1) + } +| MOVZX qreg COMMA addr + { check_size ($1.sz2, X86QUAD) + ; `X86MOVZX (X86S64, R_rm ($2, $4), suffix_size $1.sz1) + } +| MUL addr + { `X86MUL (suffix_size $1.sz, $2) } +| MUL breg + { check_size ($1.sz, X86BYTE) + ; `X86MUL (X86S8 ($2.high), Reg (IReg $2.reg)) + } +| MUL wreg + { check_size ($1.sz, X86WORD) + ; `X86MUL (X86S16, Reg $2) + } +| MUL lreg + { check_size ($1.sz, X86LONG) + ; `X86MUL (X86S32, Reg $2) + } +| MUL qreg + { check_size ($1.sz, X86QUAD) + ; `X86MUL (X86S64, Reg $2) + } +| NOP + { `X86NOP } +| POP qreg + { `X86POP (Reg $2) } +| POP addr + { `X86POP $2 } +| PUSH big_imm + { `X86PUSH (Imm $2) } +| PUSH addr + { `X86PUSH (Rm $2) } +| PUSH qreg + { `X86PUSH (Rm (Reg $2)) } +| RET big_imm + { `X86RET $2 } +| SET breg + { `X86SET ($1.cond, $2.high, Reg (IReg $2.reg)) } +| SET addr + { `X86SET ($1.cond, false, $2) } +| STC + { `X86STC } +| XADD breg COMMA breg + { check_size ($1.sz, X86BYTE) + ; check_byte_regs ($2, $4) + ; `X86XADD (false, X86S8 ($2.high), Reg (IReg $2.reg), (IReg $4.reg)) + } +| XADD addr COMMA breg + { check_size ($1.sz, X86BYTE) + ; `X86XADD (false, X86S8 ($4.high), $2, (IReg $4.reg)) + } +| LOCK XADD addr COMMA breg + { check_size ($2.sz, X86BYTE) + ; `X86XADD (true, X86S8 ($5.high), $3, (IReg $5.reg)) + } +| XADD wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86XADD (false, X86S16, Reg $2, $4) + } +| XADD addr COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86XADD (false, X86S16, $2, $4) + } +| LOCK XADD addr COMMA wreg + { check_size ($2.sz, X86WORD) + ; `X86XADD (true, X86S16, $3, $5) + } +| XADD lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86XADD (false, X86S32, Reg $2, $4) + } +| XADD addr COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86XADD (false, X86S32, $2, $4) + } +| LOCK XADD addr COMMA lreg + { check_size ($2.sz, X86LONG) + ; `X86XADD (true, X86S32, $3, $5) + } +| XADD qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86XADD (false, X86S64, Reg $2, $4) + } +| XADD addr COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86XADD (false, X86S64, $2, $4) + } +| LOCK XADD addr COMMA qreg + { check_size ($2.sz, X86QUAD) + ; `X86XADD (true, X86S64, $3, $5) + } +| XCHG breg COMMA breg + { check_size ($1.sz, X86BYTE) + ; check_byte_regs ($2, $4) + ; `X86XCHG (false, X86S8 ($2.high), Reg (IReg $2.reg), IReg $4.reg) + } +| XCHG addr COMMA breg + { check_size ($1.sz, X86BYTE) + ; `X86XCHG (false, X86S8 ($4.high), $2, (IReg $4.reg)) + } +| LOCK XCHG addr COMMA breg + { check_size ($2.sz, X86BYTE) + ; `X86XCHG (true, X86S8 ($5.high), $3, (IReg $5.reg)) + } +| XCHG wreg COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86XCHG (false, X86S16, Reg $2, $4) + } +| XCHG addr COMMA wreg + { check_size ($1.sz, X86WORD) + ; `X86XCHG (false, X86S16, $2, $4) + } +| LOCK XCHG addr COMMA wreg + { check_size ($2.sz, X86WORD) + ; `X86XCHG (true, X86S16, $3, $5) + } +| XCHG lreg COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86XCHG (false, X86S32, Reg $2, $4) + } +| XCHG addr COMMA lreg + { check_size ($1.sz, X86LONG) + ; `X86XCHG (false, X86S32, $2, $4) + } +| LOCK XCHG addr COMMA lreg + { check_size ($2.sz, X86LONG) + ; `X86XCHG (true, X86S32, $3, $5) + } +| XCHG qreg COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86XCHG (false, X86S64, Reg $2, $4) + } +| XCHG addr COMMA qreg + { check_size ($1.sz, X86QUAD) + ; `X86XCHG (false, X86S64, $2, $4) + } +| LOCK XCHG addr COMMA qreg + { check_size ($2.sz, X86QUAD) + ; `X86XCHG (true, X86S64, $3, $5) + } diff --git a/old/x86/gen/pretty.hgen b/old/x86/gen/pretty.hgen new file mode 100644 index 00000000..fc0c59d4 --- /dev/null +++ b/old/x86/gen/pretty.hgen @@ -0,0 +1,50 @@ +| `X86BINOP (locked, bop, sz, dst_src) -> + pp_locked locked ^ pp_x86Binop bop ^ pp_x86Size sz ^ " " ^ pp_x86Dest_src (sz, dst_src) +| `X86BITOP (locked, bop, sz, bo) -> + pp_locked locked ^ pp_x86Bitop bop ^ pp_x86Size sz ^ " " ^ pp_x86Bit_offset (sz, bo) +| `X86CALL (Imm i) -> "call " ^ " $" ^ bit64_to_string i +| `X86CALL (Rm rm) -> "call " ^ pp_x86Rm (X86S64, rm) +| `X86CLC -> "clc" +| `X86CMC -> "cmc" +| `X86CMPXCHG (locked, sz, rm, r) -> + sprintf "%scmpxchg%s %s, %s" + (pp_locked locked) (pp_x86Size sz) (pp_size_reg sz r) (pp_x86Rm (sz, rm)) +| `X86DIV (sz, rm) -> "div" ^ pp_x86Size sz ^ " " ^ pp_x86Rm (sz, rm) +| `X86JCC (X86ALWAYS, i) -> "jmp " ^ bit64_to_string i +| `X86JCC (cnd, i) -> "j" ^ pp_x86Cond cnd ^ " " ^ bit64_to_string i +| `X86JMP (rm) -> "jmp " ^ pp_x86Rm(X86S64, rm) +| `X86LEA (sz, dst_src) -> + "lea" ^ (pp_x86Size sz) ^ " " ^ pp_x86Dest_src (sz, dst_src) +| `X86LEAVE -> "leave" +| `X86LOOP (cnd, i) -> "loop" ^ pp_x86Cond cnd ^ " " ^ bit64_to_string i +| `X86MFENCE -> "mfence" +| `X86MONOP (locked, mop, sz, rm) -> + pp_x86Monop mop ^ pp_x86Size sz ^ " " ^ pp_x86Rm (sz, rm) +| `X86MOV (X86ALWAYS, sz, dst_src) -> + "mov" ^ pp_x86Size sz ^ " " ^ pp_x86Dest_src (sz, dst_src) +| `X86MOV (cnd, sz, dst_src) -> + "cmov" ^ pp_x86Cond cnd ^ pp_x86Size sz ^ " " ^ pp_x86Dest_src (sz, dst_src) +| `X86MOVSX (sz1, R_rm (r, rm), sz2) -> + "movs" ^ pp_x86Size sz1 ^ pp_x86Size sz2 ^ " " ^ pp_x86Rm (sz1, rm) ^ + ", " ^ pp_size_reg sz2 r +| `X86MOVSX (sz1, _, sz2) -> failwith "bad movsx instruction" +| `X86MOVZX (sz1, R_rm (r, rm), sz2) -> + "movz" ^ pp_x86Size sz1 ^ pp_x86Size sz2 ^ " " ^ pp_x86Rm (sz1, rm) ^ + ", " ^ pp_size_reg sz2 r +| `X86MOVZX (sz1, _, sz2) -> failwith "bad movzx instruction" +| `X86MUL (sz, rm) -> "mul" ^ pp_x86Size sz ^ " " ^ pp_x86Rm (sz, rm) +| `X86NOP -> "nop" +| `X86POP rm -> "pop " ^ (pp_x86Rm (X86S64, rm)) +| `X86PUSH (Imm i) -> "push $" ^ bit64_to_string i +| `X86PUSH (Rm rm) -> "push " ^ pp_x86Rm (X86S64, rm) +| `X86RET i -> "ret " ^ bit64_to_string i +| `X86SET (cnd, b, rm) -> "set" ^ pp_x86Cond cnd ^ " " ^ pp_x86Rm (X86S8 b, rm) +| `X86STC -> "stc" +| `X86XADD (locked, sz, rm, r) -> + sprintf "%s xadd%s %s, %s" + (pp_locked locked) (pp_x86Size sz) (pp_size_reg sz r) (pp_x86Rm (sz, rm)) +| `X86XCHG (locked, sz, rm, r) -> + sprintf "%sxchg%s %s, %s" + (pp_locked locked) (pp_x86Size sz) (pp_size_reg sz r) (pp_x86Rm (sz, rm)) +| `X86ThreadStart -> "start" +| `X86StopFetching -> "hlt" diff --git a/old/x86/gen/sail_trans_out.hgen b/old/x86/gen/sail_trans_out.hgen new file mode 100644 index 00000000..948db8fa --- /dev/null +++ b/old/x86/gen/sail_trans_out.hgen @@ -0,0 +1 @@ +(* *) diff --git a/old/x86/gen/shallow_ast_to_herdtools_ast.hgen b/old/x86/gen/shallow_ast_to_herdtools_ast.hgen new file mode 100644 index 00000000..ed5d6680 --- /dev/null +++ b/old/x86/gen/shallow_ast_to_herdtools_ast.hgen @@ -0,0 +1,27 @@ +| Binop (locked, binop, sz, dest_src) -> `X86BINOP (translate_out_bool locked, translate_out_binop binop, translate_out_size sz, translate_out_dest_src dest_src) +| Bitop (locked, bitop, sz, bo) -> `X86BITOP (translate_out_bool locked, translate_out_bitop bitop, translate_out_size sz, translate_out_bitoffset bo) +| CALL (imm_rm) -> `X86CALL (translate_out_imm_rm imm_rm) +| CLC -> `X86CLC +| CMC -> `X86CMC +| CMPXCHG (locked, sz, rm , reg) -> `X86CMPXCHG (translate_out_bool locked, translate_out_size sz, translate_out_rm rm, translate_out_reg reg) +| X86_DIV (sz, rm) -> `X86DIV (translate_out_size sz, translate_out_rm rm) +| HLT -> `X86StopFetching +| Jcc (cond, imm64) -> `X86JCC (translate_out_cond cond, translate_out_imm64 imm64) +| JMP (rm) -> `X86JMP (translate_out_rm rm) +| LEA (sz, dest_src) -> `X86LEA (translate_out_size sz, translate_out_dest_src dest_src) +| LEAVE -> `X86LEAVE +| LOOP (cond, imm64) -> `X86LOOP (translate_out_cond cond, translate_out_imm64 imm64) +| MFENCE -> `X86MFENCE +| Monop (locked, monop, sz, rm) -> `X86MONOP (translate_out_bool locked, translate_out_monop monop, translate_out_size sz, translate_out_rm rm) +| MOV (cond, sz, dest_src) -> `X86MOV (translate_out_cond cond, translate_out_size sz, translate_out_dest_src dest_src) +| MOVSX (sz1, dest_src, sz2) -> `X86MOVSX (translate_out_size sz1, translate_out_dest_src dest_src, translate_out_size sz2) +| MOVZX (sz1, dest_src, sz2) -> `X86MOVZX (translate_out_size sz1, translate_out_dest_src dest_src, translate_out_size sz2) +| X86_MUL (sz, rm) -> `X86MUL (translate_out_size sz, translate_out_rm rm) +| NOP (_) -> `X86NOP +| POP (rm) -> `X86POP (translate_out_rm rm) +| PUSH (imm_rm) -> `X86PUSH (translate_out_imm_rm imm_rm) +| RET (imm64) -> `X86RET (translate_out_imm64 imm64) +| SET (cond, b, rm) -> `X86SET (translate_out_cond cond, translate_out_bool b, translate_out_rm rm) +| STC -> `X86STC +| XADD (locked, sz, rm, reg) -> `X86XADD (translate_out_bool locked, translate_out_size sz, translate_out_rm rm, translate_out_reg reg) +| XCHG (locked, sz, rm, reg) -> `X86XCHG (translate_out_bool locked, translate_out_size sz, translate_out_rm rm, translate_out_reg reg) diff --git a/old/x86/gen/shallow_types_to_herdtools_types.hgen b/old/x86/gen/shallow_types_to_herdtools_types.hgen new file mode 100644 index 00000000..ba4eccaa --- /dev/null +++ b/old/x86/gen/shallow_types_to_herdtools_types.hgen @@ -0,0 +1,97 @@ +let is_inc = false + +let translate_out_bool = function + | Sail_values.B1 -> true + | Sail_values.B0 -> false + | _ -> failwith "translate_out_bool Undef" + +let translate_out_binop = function + | X86_Add -> X86ADD + | X86_Or -> X86OR + | X86_Adc -> X86ADC + | X86_Sbb -> X86SBB + | X86_And -> X86AND + | X86_Sub -> X86SUB + | X86_Xor -> X86XOR + | X86_Cmp -> X86CMP + | X86_Rol -> X86ROL + | X86_Ror -> X86ROR + | X86_Rcl -> X86RCL + | X86_Rcr -> X86RCR + | X86_Shl -> X86SHL + | X86_Shr -> X86SHR + | X86_Test -> X86TEST + | X86_Sar -> X86SAR + +let translate_out_bitop = function + | Btc -> X86Btc + | Bts -> X86Bts + | Btr -> X86Btr + +let translate_out_size = function + | Sz8 (high) -> X86S8 (translate_out_bool high) + | Sz16 -> X86S16 + | Sz32 -> X86S32 + | Sz64 -> X86S64 + +let translate_out_big_bit = Sail_values.unsigned + +let translate_out_int inst = (Nat_big_num.to_int (translate_out_big_bit inst)) + +let translate_out_reg r = IReg (int_to_ireg (Nat_big_num.to_int r)) + +let translate_out_scale = translate_out_int + +let translate_out_imm64 i = translate_out_big_bit i + +let translate_out_msi = function + | Some (scale, reg) -> Some (translate_out_scale scale, translate_out_reg reg) + | None -> None + +let translate_out_base = function + | X86_embed_types.NoBase -> X86HGenBase.NoBase + | X86_embed_types.RegBase(r) -> X86HGenBase.RegBase (translate_out_reg r) + | X86_embed_types.RipBase -> X86HGenBase.RipBase + +let translate_out_rm = function + | X86_embed_types.X86_Reg (r) -> X86HGenBase.Reg (translate_out_reg r) + | X86_embed_types.Mem (m_si, base, imm) -> X86HGenBase.Mem (translate_out_msi m_si, translate_out_base base, translate_out_imm64 imm) + +let translate_out_dest_src = function + | X86_embed_types.R_rm (reg, rm) -> X86HGenBase.R_rm (translate_out_reg reg, translate_out_rm rm) + | X86_embed_types.Rm_i (rm, imm64) -> X86HGenBase.Rm_i (translate_out_rm rm, translate_out_imm64 imm64) + | X86_embed_types.Rm_r (rm, reg) -> X86HGenBase.Rm_r (translate_out_rm rm, translate_out_reg reg) + +let translate_out_imm_rm = function + | X86_embed_types.Imm (imm) -> X86HGenBase.Imm (translate_out_imm64 imm) + | X86_embed_types.Rm (rm) -> X86HGenBase.Rm (translate_out_rm rm) + +let translate_out_bitoffset = function + | Bit_rm_imm (rm, imm) -> X86HGenBase.Bit_rm_imm (translate_out_rm rm, Nat_big_num.to_int (translate_out_imm64 imm)) + | Bit_rm_r (rm, r) -> X86HGenBase.Bit_rm_r (translate_out_rm rm, translate_out_reg r) + +let translate_out_cond = function + | X86_O -> X86O + | X86_NO -> X86NO + | X86_B -> X86B + | X86_NB -> X86NB + | X86_E -> X86E + | X86_NE -> X86NE + | X86_NA -> X86NA + | X86_A -> X86A + | X86_S -> X86S + | X86_NS -> X86NS + | X86_P -> X86P + | X86_NP -> X86NP + | X86_L -> X86L + | X86_NL -> X86NL + | X86_NG -> X86NG + | X86_G -> X86G + | X86_ALWAYS -> X86ALWAYS + +let translate_out_monop = function + | X86_Dec -> X86DEC + | X86_Inc -> X86INC + | X86_Not -> X86NOT + | X86_Neg -> X86NEG + diff --git a/old/x86/gen/token_types.hgen b/old/x86/gen/token_types.hgen new file mode 100644 index 00000000..9485e544 --- /dev/null +++ b/old/x86/gen/token_types.hgen @@ -0,0 +1,29 @@ +type token_BINOP = { txt : string; op : x86Binop; sz : x86Suffix } +type token_BITOP = { txt : string; op : x86Bitop; sz : x86Suffix } +type token_CALL = { txt : string } +type token_CLC = { txt : string } +type token_CMC = { txt : string } +type token_CMOV = { txt : string; cond : x86Cond; sz : x86Suffix } +type token_CMPXCHG = { txt : string; sz : x86Suffix } +type token_DIV = { txt : string; sz : x86Suffix } +type token_JCC = { txt : string; cond : x86Cond } +type token_JMP = { txt : string } +type token_LEA = { txt : string; sz : x86Suffix } +type token_LEAVE = { txt : string } +type token_LOOP = { txt : string; cond : x86Cond } +type token_MFENCE = { txt : string; } +type token_MONOP = { txt : string; op : x86Monop; sz : x86Suffix } +type token_MOV = { txt : string; sz : x86Suffix } +type token_MOVABS = { txt : string } +type token_MOVSX = { txt : string; sz1 : x86Suffix; sz2 : x86Suffix } +type token_MOVZX = { txt : string; sz1 : x86Suffix; sz2 : x86Suffix } +type token_MUL = { txt : string; sz : x86Suffix } +type token_NOP = { txt : string } +type token_POP = { txt : string } +type token_PUSH = { txt : string } +type token_RET = { txt : string } +type token_SET = { txt : string; cond : x86Cond } +type token_STC = { txt : string } +type token_XADD = { txt : string; sz : x86Suffix } +type token_XCHG = { txt : string; sz : x86Suffix } + diff --git a/old/x86/gen/tokens.hgen b/old/x86/gen/tokens.hgen new file mode 100644 index 00000000..7aa5256f --- /dev/null +++ b/old/x86/gen/tokens.hgen @@ -0,0 +1,28 @@ +%token <X86HGenBase.token_BINOP> BINOP +%token <X86HGenBase.token_BITOP> BITOP +%token <X86HGenBase.token_CALL> CALL +%token <X86HGenBase.token_CLC> CLC +%token <X86HGenBase.token_CMC> CMC +%token <X86HGenBase.token_CMPXCHG> CMPXCHG +%token <X86HGenBase.token_DIV> DIV +%token <X86HGenBase.token_JCC> JCC +%token <X86HGenBase.token_JMP> JMP +%token <X86HGenBase.token_LEA> LEA +%token <X86HGenBase.token_LEAVE> LEAVE +%token <X86HGenBase.token_LOOP> LOOP +%token <X86HGenBase.token_MFENCE> MFENCE +%token <X86HGenBase.token_MONOP> MONOP +%token <X86HGenBase.token_CMOV> CMOV +%token <X86HGenBase.token_MOV> MOV +%token <X86HGenBase.token_MOVABS> MOVABS +%token <X86HGenBase.token_MOVSX> MOVSX +%token <X86HGenBase.token_MOVZX> MOVZX +%token <X86HGenBase.token_MUL> MUL +%token <X86HGenBase.token_NOP> NOP +%token <X86HGenBase.token_POP> POP +%token <X86HGenBase.token_PUSH> PUSH +%token <X86HGenBase.token_RET> RET +%token <X86HGenBase.token_SET> SET +%token <X86HGenBase.token_STC> STC +%token <X86HGenBase.token_XADD> XADD +%token <X86HGenBase.token_XCHG> XCHG diff --git a/old/x86/gen/trans_sail.hgen b/old/x86/gen/trans_sail.hgen new file mode 100644 index 00000000..0fdfc803 --- /dev/null +++ b/old/x86/gen/trans_sail.hgen @@ -0,0 +1,28 @@ +(*| `X86BINOP(binop, sz, dest_src) -> ("Binop", [translate_binop binop; translate_size sz; translate_dest_src dest_src], []) +| `X86CALL (imm_rm) -> ("CALL", [translate_imm_rm imm_rm], []) +| `X86CLC -> ("CLC", [], []) +| `X86CMC -> ("CMC", [], []) +| `X86CMPXCHG (sz, rm , reg) -> ("CMPXCHG", [translate_size sz; translate_rm rm; translate_reg reg], []) +| `X86DIV (sz, rm) -> ("DIV", [translate_size sz; translate_rm rm], []) +| `X86StopFetching -> ("HLT", [], []) +| `X86JCC (cond, imm64) -> ("Jcc", [translate_cond cond; translate_imm64 imm64], []) +| `X86JMP (rm) -> ("JMP", [translate_rm rm], []) +| `X86LEA (sz, dest_src) -> ("LEA", [translate_size sz; translate_dest_src dest_src], []) +| `X86LEAVE -> ("LEAVE", [], []) +| `X86LOOP (cond, imm64) -> ("LOOP", [translate_cond cond; translate_imm64 imm64], []) +| `X86MFENCE -> ("MFENCE", [], []) +| `X86MONOP (monop, sz, rm) -> ("Monop", [translate_monop monop; translate_size sz; translate_rm rm], []) +| `X86MOV (cond, sz, dest_src) -> ("MOV", [translate_cond cond; translate_size sz; translate_dest_src dest_src], []) +| `X86MOVSX (sz1, dest_src, sz2) -> ("MOVSX", [translate_size sz1; translate_dest_src dest_src; translate_size sz2], []) +| `X86MOVZX (sz1, dest_src, sz2) -> ("MOVZX", [translate_size sz1; translate_dest_src dest_src; translate_size sz2], []) +| `X86MUL (sz, rm) -> ("MUL", [translate_size sz; translate_rm rm], []) +| `X86NOP -> ("NOP", [Nat_big_num.of_int 0], []) +| `X86POP (rm) -> ("POP", [translate_rm rm], []) +| `X86PUSH (imm_rm) -> ("PUSH", [translate_imm_rm imm_rm], []) +| `X86RET (imm64) -> ("RET", [translate_imm64 imm64], []) +| `X86SET (cond, b, rm) -> ("SET", [translate_cond cond; translate_bool b; translate_rm rm], []) +| `X86STC -> ("STC", [], []) +| `X86XADD (sz, rm, reg) -> ("XADD", [translate_size sz; translate_rm rm; translate_reg reg], []) +| `X86XCHG (sz, rm, reg) -> ("XCHG", [translate_size sz; translate_rm rm; translate_reg reg], []) + +*)
\ No newline at end of file diff --git a/old/x86/gen/types.hgen b/old/x86/gen/types.hgen new file mode 100644 index 00000000..117f0f4d --- /dev/null +++ b/old/x86/gen/types.hgen @@ -0,0 +1,134 @@ +type bit2 = int +type bit64 = Nat_big_num.num +let bit64_of_int = Nat_big_num.of_int +let bit64_to_int = Nat_big_num.to_int +let bit64_to_string = Nat_big_num.to_string +let eq_bit64 = Nat_big_num.equal + +type x86Binop = +| X86ADD +| X86OR +| X86ADC +| X86SBB +| X86AND +| X86SUB +| X86XOR +| X86CMP +| X86ROL +| X86ROR +| X86RCL +| X86RCR +| X86SHL +| X86SHR +| X86TEST +| X86SAR + +let pp_x86Binop = function +| X86ADD -> "add" +| X86OR -> "or" +| X86ADC -> "adc" +| X86SBB -> "sbb" +| X86AND -> "and" +| X86SUB -> "sub" +| X86XOR -> "xor" +| X86CMP -> "cmp" +| X86ROL -> "rol" +| X86ROR -> "ror" +| X86RCL -> "rcl" +| X86RCR -> "rcr" +| X86SHL -> "shl" +| X86SHR -> "shr" +| X86TEST -> "test" +| X86SAR -> "sar" + +type x86Bitop = X86Bts | X86Btc | X86Btr + +let pp_x86Bitop = function +| X86Bts -> "bts" +| X86Btc -> "btc" +| X86Btr -> "btr" + +type x86Monop = +| X86DEC +| X86INC +| X86NOT +| X86NEG + +let pp_x86Monop = function +| X86DEC -> "dec" +| X86INC -> "inc" +| X86NOT -> "not" +| X86NEG -> "neg" + +type x86Cond = +| X86O +| X86NO +| X86B +| X86NB +| X86E +| X86NE +| X86NA +| X86A +| X86S +| X86NS +| X86P +| X86NP +| X86L +| X86NL +| X86NG +| X86G +| X86ALWAYS + +let pp_x86Cond = function +| X86O -> "o" +| X86NO -> "no" +| X86B -> "b" +| X86NB -> "nb" +| X86E -> "e" +| X86NE -> "ne" +| X86NA -> "na" +| X86A -> "a" +| X86S -> "s" +| X86NS -> "ns" +| X86P -> "p" +| X86NP -> "np" +| X86L -> "l" +| X86NL -> "nl" +| X86NG -> "ng" +| X86G -> "g" +| X86ALWAYS -> "" + +type x86Suffix = +| X86BYTE +| X86WORD +| X86LONG +| X86QUAD +| X86NONE + +let pp_x86Suffix = function +| X86BYTE -> "byte" +| X86WORD -> "word" +| X86LONG -> "long" +| X86QUAD -> "quad" +| X86NONE -> "" + +type x86Size = +| X86S8 of bool +| X86S16 +| X86S32 +| X86S64 + +let pp_x86Size = function +| X86S8(_) -> "b" +| X86S16 -> "w" +| X86S32 -> "l" +| X86S64 -> "q" + +let pp_locked l = if l then "lock " else "" + +let suffix_size = function +| X86BYTE -> X86S8 false +| X86WORD -> X86S16 +| X86LONG -> X86S32 +| X86QUAD -> X86S64 +| X86NONE -> X86S64 diff --git a/old/x86/gen/types_sail_trans_out.hgen b/old/x86/gen/types_sail_trans_out.hgen new file mode 100644 index 00000000..948db8fa --- /dev/null +++ b/old/x86/gen/types_sail_trans_out.hgen @@ -0,0 +1 @@ +(* *) diff --git a/old/x86/gen/types_trans_sail.hgen b/old/x86/gen/types_trans_sail.hgen new file mode 100644 index 00000000..f088db39 --- /dev/null +++ b/old/x86/gen/types_trans_sail.hgen @@ -0,0 +1,61 @@ +(*let translate_enum enum_values name value = + let rec bit_count n = + if n = 0 then 0 + else 1 + (bit_count (n lsr 1)) in + let rec find_index element = function + | h::tail -> if h = element then 0 else 1 + (find_index element tail) + | _ -> failwith "translate_enum could not find value" + in + let size = bit_count (List.length enum_values) in + let index = find_index value enum_values in + (name, Range0 (Some size), IInt.bit_list_of_integer size (Nat_big_num.of_int index)) + +let translate_binop = translate_enum [X86ADD ; X86OR ; X86ADC ; X86SBB ; X86AND ; X86SUB ; X86XOR ; X86CMP ; X86ROL ; X86ROR ; X86RCL ; X86RCR ; X86SHL ; X86SHR ; X86TEST; X86SAR] + +let translate_cond = translate_enum [X86O ; X86NO ; X86B ; X86NB ; X86E ; X86NE ; X86NA ; X86A ; X86S ; X86NS ; X86P ; X86NP ; X86L ; X86NL ; X86NG ; X86G ; X86ALWAYS ] + +let translate_monop = translate_enum [X86DEC; X86INC; X86NOT; X86NEG] + +let translate_bool value = + ("bool", Bit, [if value then Bitc_one else Bitc_zero]) + +let translate_size = function + | X86S8(high) -> ("Sz8", [translate_bool high], []) + | X86S16 -> ("Sz16", [], []) + | X86S32 -> ("Sz32", [], []) + | X86S64 -> ("Sz64", [], []) + +let translate_bits bits value = + ("bits", Bvector (Some bits), IInt.bit_list_of_integer bits (Nat_big_num.of_int value)) + +let translate_bits_big bits value = + ("bits", Bvector (Some bits), IInt.bit_list_of_integer bits value) + +let translate_reg r = translate_bits 4 (reg_to_int r) + +let translate_scale s = translate_bits 2 s + +let translate_imm64 i = translate_bits_big 64 i + +let translate_msi = function + | Some (scale, reg) -> ("Some", [translate_scale scale; translate_reg reg], []) + | None -> ("None", [], []) + +let translate_base = function + | X86HGenBase.NoBase -> ("NoBase", [], []) + | X86HGenBase.RegBase(r) -> ("RegBase", [translate_reg r], []) + | X86HGenBase.RipBase -> ("RipBase", [], []) + +let translate_rm = function + | X86HGenBase.Reg (r) -> ("Reg", [translate_reg r], []) + | X86HGenBase.Mem (m_si, base, imm) -> ("Mem", [translate_msi m_si; translate_base base; translate_imm64 imm], []) + +let translate_dest_src = function + | X86HGenBase.R_rm (reg, rm) -> ("R_rm", [translate_reg reg; translate_rm rm], []) + | X86HGenBase.Rm_i (rm, imm64) -> ("Rm_i", [translate_rm rm; translate_imm64 imm64], []) + | X86HGenBase.Rm_r (rm, reg) -> ("Rm_r", [translate_rm rm; translate_reg reg], []) + +let translate_imm_rm = function + | X86HGenBase.Imm (imm) -> ("Imm", [translate_imm64 imm], []) + | X86HGenBase.Rm (rm) -> ("Rm", [translate_rm rm], []) + *) diff --git a/old/x86/x64.sail b/old/x86/x64.sail new file mode 100644 index 00000000..3549b123 --- /dev/null +++ b/old/x86/x64.sail @@ -0,0 +1,1610 @@ +(*========================================================================*) +(* *) +(* This software was developed by the University of Cambridge Computer *) +(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) +(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in *) +(* the documentation and/or other materials provided with the *) +(* distribution. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) +(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) +(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) +(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) +(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) +(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) +(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) +(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) +(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) +(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) +(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) +(* SUCH DAMAGE. *) +(*========================================================================*) + +default Order dec + +val extern forall Type 'a. ('a, list<'a>) -> bool effect pure ismember +val extern forall Type 'a. list<'a> -> nat effect pure listlength + +function (bit[8 ]) ASR8 ((bit[8 ]) v, ([|8 |]) shift) = let v2 = ((bit[16 ]) (EXTS(v))) in (bit[8 ]) (mask(v2 >> shift)) +function (bit[16]) ASR16 ((bit[16]) v, ([|16|]) shift) = let v2 = ((bit[32 ]) (EXTS(v))) in (bit[16]) (mask(v2 >> shift)) +function (bit[32]) ASR32 ((bit[32]) v, ([|32|]) shift) = let v2 = ((bit[64 ]) (EXTS(v))) in (bit[32]) (mask(v2 >> shift)) +function (bit[64]) ASR64 ((bit[64]) v, ([|64|]) shift) = let v2 = ((bit[128]) (EXTS(v))) in (bit[64]) (mask(v2 >> shift)) + +function (bit[8 ]) ROR8 ((bit[8 ]) v, ([|8 |]) shift) = let v2 = ((bit[16 ]) (v:v)) in (bit[8 ]) (mask(v2 >> shift)) +function (bit[16]) ROR16 ((bit[16]) v, ([|16|]) shift) = let v2 = ((bit[32 ]) (v:v)) in (bit[16]) (mask(v2 >> shift)) +function (bit[32]) ROR32 ((bit[32]) v, ([|32|]) shift) = let v2 = ((bit[64 ]) (v:v)) in (bit[32]) (mask(v2 >> shift)) +function (bit[64]) ROR64 ((bit[64]) v, ([|64|]) shift) = let v2 = ((bit[128]) (v:v)) in (bit[64]) (mask(v2 >> shift)) + +function (bit[8 ]) ROL8 ((bit[8 ]) v, ([|8 |]) shift) = let v2 = ((bit[16 ]) (v:v)) in (bit[8 ]) (mask(v2 << shift)) +function (bit[16]) ROL16 ((bit[16]) v, ([|16|]) shift) = let v2 = ((bit[32 ]) (v:v)) in (bit[16]) (mask(v2 << shift)) +function (bit[32]) ROL32 ((bit[32]) v, ([|32|]) shift) = let v2 = ((bit[64 ]) (v:v)) in (bit[32]) (mask(v2 << shift)) +function (bit[64]) ROL64 ((bit[64]) v, ([|64|]) shift) = let v2 = ((bit[128]) (v:v)) in (bit[64]) (mask(v2 << shift)) + +(*val cast bool -> bit effect pure cast_bool_bit +val cast bit -> int effect pure cast_bit_int *) +function forall Nat 'n, Nat 'm, Nat 'o, 'n <= 0, 'm <= 'o. ([|0:'o|]) negative_to_zero (([|'n:'m|]) x) = + if x < 0 then 0 else x + +typedef byte = bit[8] +typedef qword = bit[64] +typedef regn = [|15|] +typedef byte_stream = list<byte> +typedef ostream = option<byte_stream> + +(* -------------------------------------------------------------------------- + Registers + -------------------------------------------------------------------------- *) + +(* Program Counter *) + +register qword RIP + +(* General purpose registers *) + +register qword RAX (* 0 *) +register qword RCX (* 1 *) +register qword RDX (* 2 *) +register qword RBX (* 3 *) +register qword RSP (* 4 *) +register qword RBP (* 5 *) +register qword RSI (* 6 *) +register qword RDI (* 7 *) +register qword R8 +register qword R9 +register qword R10 +register qword R11 +register qword R12 +register qword R13 +register qword R14 +register qword R15 + +let (vector<0,16,inc,(register<qword>)>) REG = + [RAX,RCX,RDX,RBX,RSP,RBP,RSI,RDI,R8,R9,R10,R11,R12,R13,R14,R15] + +(* Flags *) + +register bit[1] CF +register bit[1] PF +register bit[1] AF +register bit[1] ZF +register bit[1] SF +register bit[1] OF + +(* -------------------------------------------------------------------------- + Memory + -------------------------------------------------------------------------- *) + +val extern forall Nat 'n. (qword, [|'n|]) -> (bit[8 * 'n]) effect { rmem } rMEM +val extern forall Nat 'n. (qword, [|'n|]) -> (bit[8 * 'n]) effect { rmem } rMEM_locked +function forall Nat 'n. (bit[8 * 'n]) effect { rmem } rMEMl ((bool) locked, (qword) addr, ([|'n|]) size) = + if locked then rMEM_locked(addr, size) else rMEM(addr, size) + +val extern forall Nat 'n. ( bit[64] , [|'n|]) -> unit effect { eamem } MEMea +val extern forall Nat 'n. ( bit[64] , [|'n|]) -> unit effect { eamem } MEMea_locked +val extern forall Nat 'n. ( bit[64] , [|'n|] , bit[8*'n]) -> unit effect { wmv } MEMval +val extern unit -> unit effect { barr } X86_MFENCE + +function forall Nat 'n. unit effect {eamem, wmv} wMEM ((bool) locked, (qword) addr, ([|'n|]) len, (bit[8 * 'n]) data) = { + if locked then MEMea_locked(addr, len) else MEMea(addr, len); + MEMval(addr, len, data); +} + +(* -------------------------------------------------------------------------- + Helper functions + -------------------------------------------------------------------------- *) + +(* Instruction addressing modes *) + +typedef wsize = const union { + bool Sz8; + unit Sz16; + unit Sz32; + unit Sz64; +} + +function ([|8:64|]) size_to_int((wsize) s) = + switch(s) { + case (Sz8(_)) -> 8 + case Sz16 -> 16 + case Sz32 -> 32 + case Sz64 -> 64 + } + +typedef base = const union { + unit NoBase; + unit RipBase; + regn RegBase; +} + +typedef scale_index = (bit[2],regn) + +typedef rm = const union { + regn X86_Reg; + (option<scale_index>,base,qword) Mem; +} + +typedef dest_src = const union { + (rm,qword) Rm_i; + (rm,regn) Rm_r; + (regn,rm) R_rm; +} + +typedef imm_rm = const union { + rm Rm; + qword Imm; +} + +typedef bit_offset = const union { + (rm, qword) Bit_rm_imm; + (rm, regn) Bit_rm_r; +} + +typedef monop_name = enumerate { X86_Dec; X86_Inc; X86_Not; X86_Neg } + +typedef binop_name = enumerate { + X86_Add; X86_Or; X86_Adc; X86_Sbb; X86_And; X86_Sub; X86_Xor; X86_Cmp; + X86_Rol; X86_Ror; X86_Rcl; X86_Rcr; X86_Shl; X86_Shr; X86_Test; X86_Sar; +} + +typedef bitop_name = enumerate { Bts; Btc; Btr } + +function binop_name opc_to_binop_name ((bit[4]) opc) = + switch opc + { + case 0x0 -> X86_Add + case 0x1 -> X86_Or + case 0x2 -> X86_Adc + case 0x3 -> X86_Sbb + case 0x4 -> X86_And + case 0x5 -> X86_Sub + case 0x6 -> X86_Xor + case 0x7 -> X86_Cmp + case 0x8 -> X86_Rol + case 0x9 -> X86_Ror + case 0xa -> X86_Rcl + case 0xb -> X86_Rcr + case 0xc -> X86_Shl + case 0xd -> X86_Shr + case 0xe -> X86_Test + case 0xf -> X86_Sar + } + +typedef cond = enumerate { + X86_O; X86_NO; X86_B; X86_NB; X86_E; X86_NE; X86_NA; X86_A; X86_S; + X86_NS; X86_P; X86_NP; X86_L; X86_NL; X86_NG; X86_G; X86_ALWAYS; +} + +function cond bv_to_cond ((bit[4]) v) = + switch v + { + case 0x0 -> X86_O + case 0x1 -> X86_NO + case 0x2 -> X86_B + case 0x3 -> X86_NB + case 0x4 -> X86_E + case 0x5 -> X86_NE + case 0x6 -> X86_NA + case 0x7 -> X86_A + case 0x8 -> X86_S + case 0x9 -> X86_NS + case 0xa -> X86_P + case 0xb -> X86_NP + case 0xc -> X86_L + case 0xd -> X86_NL + case 0xe -> X86_NG + case 0xf -> X86_G + } + +(* Effective addresses *) + +typedef ea = const union { + (wsize,qword) Ea_i; + (wsize,regn) Ea_r; + (wsize,qword) Ea_m; +} + +function qword ea_index ((option<scale_index>) index) = + switch (index) { + case None -> 0x0000000000000000 + case (Some(scale, idx)) -> + let x = (qword) (0x0000000000000001 << scale) in + let y = (qword) (REG[idx]) in + let z = (bit[128]) (x * y) in + z[63 .. 0] + } + +function qword ea_base ((base) b) = + switch b { + case NoBase -> 0x0000000000000000 + case RipBase -> RIP + case (RegBase(b)) -> REG[b] + } + +function ea ea_rm ((wsize) sz, (rm) r) = + switch r { + case (X86_Reg(n)) -> Ea_r (sz, n) + case (Mem(idx, b, d)) -> Ea_m (sz, ea_index(idx) + (qword) (ea_base(b) + d)) + } + +function ea ea_dest ((wsize) sz, (dest_src) ds) = + switch ds { + case (Rm_i (v, _)) -> ea_rm (sz, v) + case (Rm_r (v, _)) -> ea_rm (sz, v) + case (R_rm (v, _)) -> Ea_r (sz, v) + } + +function ea ea_src ((wsize) sz, (dest_src) ds) = + switch ds { + case (Rm_i (_, v)) -> Ea_i (sz, v) + case (Rm_r (_, v)) -> Ea_r (sz, v) + case (R_rm (_, v)) -> ea_rm (sz, v) + } + +function ea ea_imm_rm ((imm_rm) i_rm) = + switch i_rm { + case (Rm (v)) -> ea_rm (Sz64, v) + case (Imm (v)) -> Ea_i (Sz64, v) + } + +function qword restrict_size ((wsize) sz, (qword) imm) = + switch sz { + case (Sz8(_)) -> imm & 0x00000000000000FF + case Sz16 -> imm & 0x000000000000FFFF + case Sz32 -> imm & 0x00000000FFFFFFFF + case Sz64 -> imm + } + +function regn sub4 ((regn) r) = negative_to_zero (r - 4) + +function qword effect { rreg, rmem } EA ((bool) locked, (ea) e) = + switch e { + case (Ea_i(sz,i)) -> restrict_size(sz,i) + case (Ea_r((Sz8(have_rex)),r)) -> + if have_rex | r < 4 (* RSP *) | r > 7 (* RDI *) then + REG[r] + else + (REG[sub4 (r)] >> 8) & 0x00000000000000FF + case (Ea_r(sz,r)) -> restrict_size(sz, REG[r]) + case (Ea_m((Sz8(_)),a)) -> EXTZ (rMEMl(locked, a, 1)) + case (Ea_m(Sz16,a)) -> EXTZ (rMEMl(locked, a, 2)) + case (Ea_m(Sz32,a)) -> EXTZ (rMEMl(locked, a, 4)) + case (Ea_m(Sz64,a)) -> rMEMl(locked, a, 8) + } + +function unit effect { wmem, wreg, escape } wEA ((bool) locked, (ea) e, (qword) w) = + switch e { + case (Ea_i(_,_)) -> exit () + case (Ea_r((Sz8(have_rex)),r)) -> + if have_rex | r < 4 (* RSP *) | r > 7 (* RDI *) then + (REG[r])[7 .. 0] := w[7 .. 0] + else + (REG[sub4(r)])[15 .. 8] := (vector<15,8,dec,bit>) (w[7 .. 0]) + case (Ea_r(Sz16,r)) ->(REG[r])[15 .. 0] := w[15 .. 0] + case (Ea_r(Sz32,r)) -> REG[r] := (qword) (EXTZ (w[31 .. 0])) + case (Ea_r(Sz64,r)) -> REG[r] := w + case (Ea_m((Sz8(_)),a)) -> wMEM(locked, a, 1, w[7 .. 0]) + case (Ea_m(Sz16,a)) -> wMEM(locked, a, 2, w[15 .. 0]) + case (Ea_m(Sz32,a)) -> wMEM(locked, a, 4, w[31 .. 0]) + case (Ea_m(Sz64,a)) -> wMEM(locked, a, 8, w) + } + +function (ea, qword, qword) read_dest_src_ea ((bool) locked, (wsize) sz, (dest_src) ds) = + let e = ea_dest (sz, ds) in + (e, EA(locked, e), EA(locked, ea_src(sz, ds))) + +function qword call_dest_from_ea ((ea) e) = + switch e { + case (Ea_i(_, i)) -> RIP + i + case (Ea_r(_, r)) -> REG[r] + case (Ea_m(_, a)) -> rMEM(a, 8) + } + +function qword get_ea_address ((ea) e) = + switch e { + case (Ea_i(_, i)) -> 0x0000000000000000 + case (Ea_r(_, r)) -> 0x0000000000000000 + case (Ea_m(_, a)) -> a + } + +function unit jump_to_ea ((ea) e) = RIP := call_dest_from_ea(e) + +function (ea, nat) bit_offset_ea ((wsize) sz, (bit_offset) bo) = + let s = size_to_int (sz) in + switch bo { + case (Bit_rm_imm (r_m, imm)) -> + let base_ea = ea_rm (sz, r_m) in + switch (base_ea) { + case (Ea_r(_, r)) -> (Ea_r(sz, r), imm mod s) + case (Ea_m(_, a)) -> (Ea_m(sz, a), imm mod s) + } + case (Bit_rm_r (r_m, r)) -> + let base_ea = ea_rm (sz, r_m) in + let offset = REG[r] in + switch (base_ea) { + case (Ea_r(_, r)) -> (Ea_r(sz, r), offset mod s) + case (Ea_m(_, a)) -> (Ea_m(Sz64, a + (offset div 8)), offset mod 64) + } + } + +(* EFLAG updates *) + +function bit byte_parity ((byte) b) = +{ + (int) acc := 0; + foreach (i from 0 to 7) acc := acc + (int) (b[i]); + (bit) (acc mod 2 == 0) +} + +function [|64|] size_width ((wsize) sz) = + switch sz { + case (Sz8(_)) -> 8 + case Sz16 -> 16 + case Sz32 -> 32 + case Sz64 -> 64 + } + +function [|63|] size_width_sub1 ((wsize) sz) = + switch sz { + case (Sz8(_)) -> 7 + case Sz16 -> 15 + case Sz32 -> 31 + case Sz64 -> 63 + } + +(* XXXXX +function bit word_size_msb ((wsize) sz, (qword) w) = w[size_width(sz) - 1] +*) + +function bit word_size_msb ((wsize) sz, (qword) w) = w[size_width_sub1(sz)] + +function unit write_PF ((qword) w) = PF := byte_parity (w[7 .. 0]) + +function unit write_SF ((wsize) sz, (qword) w) = SF := word_size_msb (sz, w) + +function unit write_ZF ((wsize) sz, (qword) w) = + ZF := (bit) + (switch sz { + case (Sz8(_)) -> w[7 .. 0] == 0x00 + case Sz16 -> w[15 .. 0] == 0x0000 + case Sz32 -> w[31 .. 0] == 0x00000000 + case Sz64 -> w == 0x0000000000000000 + }) + +function unit write_arith_eflags_except_CF_OF ((wsize) sz, (qword) w) = +{ + AF := undefined; + write_PF(w); + write_SF(sz, w); + write_ZF(sz, w); +} + +function unit write_arith_eflags ((wsize) sz, (qword) w, (bit) c, (bit) x) = +{ + CF := c; + OF := x; + write_arith_eflags_except_CF_OF (sz, w) +} + +function unit write_logical_eflags ((wsize) sz, (qword) w) = + write_arith_eflags (sz, w, bitzero, bitzero) + +function unit erase_eflags () = +{ + AF := undefined; + CF := undefined; + OF := undefined; + PF := undefined; + SF := undefined; + ZF := undefined; +} + +function nat value_width ((wsize) sz) = 2 ** size_width(sz) + +function bit word_signed_overflow_add ((wsize) sz, (qword) a, (qword) b) = + (bit) (word_size_msb (sz, a) == word_size_msb (sz, b) & + word_size_msb (sz, a + b) != word_size_msb (sz, a)) + +function bit word_signed_overflow_sub ((wsize) sz, (qword) a, (qword) b) = + (bit) (word_size_msb (sz, a) != word_size_msb (sz, b) & + word_size_msb (sz, a - b) != word_size_msb (sz, a)) + +function (qword, bit, bit) add_with_carry_out ((wsize) sz, (qword) a, (qword) b) = + (a + b, (bit) ((int) (value_width (sz)) <= unsigned(a) + unsigned(b)), + word_signed_overflow_add (sz, a, b)) + +function (qword, bit, bit) sub_with_borrow ((wsize) sz, (qword) a, (qword) b) = + (a - b, (bit) (a < b), word_signed_overflow_sub (sz, a, b)) + +function unit write_arith_result ((bool) locked, (wsize) sz, (qword) w, (bit) c, (bit) x, (ea) e) = +{ + write_arith_eflags (sz, w, c, x); + wEA (locked, e) := w; +} + +function unit write_arith_result_no_CF_OF ((bool) locked, (wsize) sz, (qword) w, (ea) e) = +{ + write_arith_eflags_except_CF_OF (sz, w); + wEA (locked, e) := w; +} + +function unit write_logical_result ((bool) locked, (wsize) sz, (qword) w, (ea) e) = +{ + write_arith_eflags_except_CF_OF (sz, w); + wEA (locked, e) := w; +} + +function unit write_result_erase_eflags ((bool) locked, (qword) w, (ea) e) = +{ + erase_eflags (); + wEA (locked, e) := w; +} + +function qword effect { escape } sign_extension ((qword) w, (wsize) size1, (wsize) size2) = +{ + (qword) x := w; + switch (size1, size2) { + case ((Sz8(_)), Sz16) -> x[15 .. 0] := (bit[16]) (EXTS (w[7 .. 0])) + case ((Sz8(_)), Sz32) -> x[31 .. 0] := (bit[32]) (EXTS (w[7 .. 0])) + case ((Sz8(_)), Sz64) -> x := (qword) (EXTS (w[7 .. 0])) + case (Sz16, Sz32) -> x[31 .. 0] := (bit[32]) (EXTS (w[15 .. 0])) + case (Sz16, Sz64) -> x := (qword) (EXTS (w[15 .. 0])) + case (Sz32, Sz64) -> x := (qword) (EXTS (w[31 .. 0])) + case _ -> undefined + }; + x; +} + +function [|64|] mask_shift ((wsize) sz, (qword) w) = + if sz == Sz64 then w[5 .. 0] else w[4 .. 0] + +function qword rol ((wsize) sz, (qword) a, (qword) b) = + switch sz { + case (Sz8(_)) -> EXTZ (ROL8 (a[7 .. 0], b[2 .. 0])) + case Sz16 -> EXTZ (ROL16 (a[15 .. 0], b[3 .. 0])) + case Sz32 -> EXTZ (ROL32 (a[31 .. 0], b[4 .. 0])) + case Sz64 -> ROL64 (a, b[5 .. 0]) + } + +function qword ror ((wsize) sz, (qword) a, (qword) b) = + switch sz { + case (Sz8(_)) -> EXTZ (ROR8 (a[7 .. 0], b[2 .. 0])) + case Sz16 -> EXTZ (ROR16 (a[15 .. 0], b[3 .. 0])) + case Sz32 -> EXTZ (ROR32 (a[31 .. 0], b[4 .. 0])) + case Sz64 -> ROR64 (a, b[5 .. 0]) + } + +function qword sar ((wsize) sz, (qword) a, (qword) b) = + switch sz { + case (Sz8(_)) -> EXTZ (ASR8 (a[7 .. 0], b[2 .. 0])) + case Sz16 -> EXTZ (ASR16 (a[15 .. 0], b[3 .. 0])) + case Sz32 -> EXTZ (ASR32 (a[31 .. 0], b[4 .. 0])) + case Sz64 -> ASR64 (a, b[5 .. 0]) + } + +function unit write_binop ((bool) locked, (wsize) sz, (binop_name) bop, (qword) a, (qword) b, (ea) e) = + switch bop { + case X86_Add -> let (w,c,x) = add_with_carry_out (sz, a, b) in + write_arith_result (locked, sz, w, c, x, e) + case X86_Sub -> let (w,c,x) = sub_with_borrow (sz, a, b) in + write_arith_result (locked, sz, w, c, x, e) + case X86_Cmp -> let (w,c,x) = sub_with_borrow (sz, a, b) in + write_arith_eflags (sz, w, c, x) + case X86_Test -> write_logical_eflags (sz, a & b) + case X86_And -> write_logical_result (locked, sz, a & b, e) (* XXX rmn30 wrong flags? *) + case X86_Xor -> write_logical_result (locked, sz, a ^ b, e) + case X86_Or -> write_logical_result (locked, sz, a | b, e) + case X86_Rol -> write_result_erase_eflags (locked, rol (sz, a, b), e) + case X86_Ror -> write_result_erase_eflags (locked, ror (sz, a, b), e) + case X86_Sar -> write_result_erase_eflags (locked, sar (sz, a, b), e) + case X86_Shl -> write_result_erase_eflags (locked, a << mask_shift (sz, b), e) + case X86_Shr -> write_result_erase_eflags (locked, a >> mask_shift (sz, b), e) + case X86_Adc -> + { + let carry = (bit) CF in + let (qword) result = a + (qword) (b + carry) in + { + CF := (bit) ((int) (value_width (sz)) <= unsigned(a) + unsigned(b)); + OF := undefined; + write_arith_result_no_CF_OF (locked, sz, result, e); + } + } + case X86_Sbb -> + { + let carry = (bit) CF in + let (qword) result = a - (qword) (b + carry) in + { + CF := (bit) (unsigned(a) < unsigned(b) + (int) carry); + OF := undefined; + write_arith_result_no_CF_OF (locked, sz, result, e); + } + } + case _ -> exit () + } + +function unit write_monop ((bool) locked, (wsize) sz, (monop_name) mop, (qword) a, (ea) e) = + switch mop { + case X86_Not -> wEA(locked, e) := ~(a) + case X86_Dec -> write_arith_result_no_CF_OF (locked, sz, a - 1, e) + case X86_Inc -> write_arith_result_no_CF_OF (locked, sz, a + 1, e)(* XXX rmn30 should set OF *) + case X86_Neg -> { write_arith_result_no_CF_OF (locked, sz, 0 - a, e); + CF := undefined; + } + } + +function bool read_cond ((cond) c) = + switch c { + case X86_A -> ~(CF) & ~(ZF) + case X86_NB -> ~(CF) + case X86_B -> CF + case X86_NA -> CF | (bit) ZF + case X86_E -> ZF + case X86_G -> ~(ZF) & (SF == OF) + case X86_NL -> SF == OF + case X86_L -> SF != OF + case X86_NG -> ZF | SF != OF + case X86_NE -> ~(ZF) + case X86_NO -> ~(OF) + case X86_NP -> ~(PF) + case X86_NS -> ~(SF) + case X86_O -> OF + case X86_P -> PF + case X86_S -> SF + case X86_ALWAYS -> true + } + +function qword pop_aux () = + let top = rMEM(RSP, 8) in + { + RSP := RSP + 8; + top; + } + +function unit push_aux ((qword) w) = +{ + RSP := RSP - 8; + wMEM(false, RSP, 8) := w; +} + +function unit pop ((rm) r) = wEA (false, ea_rm (Sz64,r)) := pop_aux() +function unit pop_rip () = RIP := pop_aux() +function unit push ((imm_rm) i) = push_aux (EA (false, ea_imm_rm (i))) +function unit push_rip () = push_aux (RIP) + +function unit drop ((qword) i) = if i[7 ..0] != 0 then () else RSP := RSP + i + +(* -------------------------------------------------------------------------- + Instructions + -------------------------------------------------------------------------- *) + +scattered function unit execute +scattered typedef ast = const union + +val ast -> unit effect {escape, rmem, rreg, undef, eamem, wmv, wreg, barr} execute + +(* ========================================================================== + Binop + ========================================================================== *) + +union ast member (bool,binop_name,wsize,dest_src) Binop + +function clause execute (Binop (locked,bop,sz,ds)) = + let (e, val_dst, val_src) = read_dest_src_ea (locked, sz, ds) in + write_binop (locked, sz, bop, val_dst, val_src, e) + +(* ========================================================================== + Bitop + ========================================================================== *) + +union ast member (bool,bitop_name,wsize,bit_offset) Bitop + +function clause execute (Bitop (locked,bop,sz,boffset)) = + let (base_ea, offset) = bit_offset_ea (sz, boffset) in { + word := EA(locked, base_ea); + bitval := word[offset]; + word[offset] := switch(bop) { + case Bts -> bitone + case Btc -> (~ (bitval)) + case Btr -> bitzero + }; + CF := bitval; + wEA(locked, base_ea) := word; + } + +(* ========================================================================== + CALL + ========================================================================== *) + +union ast member imm_rm CALL + +function clause execute (CALL (i)) = +{ + push_rip(); + jump_to_ea (ea_imm_rm (i)) +} + +(* ========================================================================== + CLC + ========================================================================== *) + +union ast member unit CLC + +function clause execute CLC = CF := false + +(* ========================================================================== + CMC + ========================================================================== *) + +union ast member unit CMC + +function clause execute CMC = CF := ~(CF) + +(* ========================================================================== + CMPXCHG + ========================================================================== *) + +union ast member (bool, wsize,rm,regn) CMPXCHG + +function clause execute (CMPXCHG (locked, sz,r,n)) = + let src = Ea_r(sz, n) in + let acc = Ea_r(sz, 0) in (* RAX *) + let dst = ea_rm(sz, r) in + let val_dst = EA(locked, dst) in + let val_acc = EA(false, acc) in + { + write_binop (locked, sz, X86_Cmp, val_acc, val_dst, src); + if val_acc == val_dst then + wEA(locked, dst) := EA (false, src) + else { + wEA(false, acc) := val_dst; + (* write back the original value in dst so that we always + perform locked write after locked read *) + wEA(locked, dst) := val_dst; + } + } + +(* ========================================================================== + DIV + ========================================================================== *) + +union ast member (wsize,rm) X86_DIV + +function clause execute (X86_DIV (sz,r)) = + let w = (int) (value_width(sz)) in + let eax = Ea_r(sz, 0) in (* RAX *) + let edx = Ea_r(sz, 2) in (* RDX *) + let n = unsigned(EA(false, edx)) * w + unsigned(EA(false, eax)) in + let d = unsigned(EA(false, ea_rm(sz, r))) in + let q = n quot d in + let m = n mod d in + if d == 0 | w < q then exit () + else + { + wEA(false, eax) := (qword) q; + wEA(false, edx) := (qword) m; + erase_eflags(); + } + +(* ========================================================================== + HLT -- halt instruction used to end test in RMEM + ========================================================================== *) + +union ast member unit HLT + +function clause execute (HLT) = () + + +(* ========================================================================== + Jcc + ========================================================================== *) + +union ast member (cond,qword) Jcc + +function clause execute (Jcc (c,i)) = + if read_cond (c) then RIP := RIP + i else () + +(* ========================================================================== + JMP + ========================================================================== *) + +union ast member rm JMP + +function clause execute (JMP (r)) = RIP := EA (false, ea_rm (Sz64, r)) + +(* ========================================================================== + LEA + ========================================================================== *) + +union ast member (wsize,dest_src) LEA + +function clause execute (LEA (sz,ds)) = + let src = ea_src (sz, ds) in + let dst = ea_dest (sz, ds) in + wEA(false, dst) := get_ea_address (src) + +(* ========================================================================== + LEAVE + ========================================================================== *) + +union ast member unit LEAVE + +function clause execute LEAVE = +{ + RSP := RBP; + pop (X86_Reg (5)); (* RBP *) +} + +(* ========================================================================== + LOOP + ========================================================================== *) + +union ast member (cond,qword) LOOP + +function clause execute (LOOP (c,i)) = +{ + RCX := RCX - 1; + if RCX != 0 & read_cond (c) then RIP := RIP + i else (); +} + +(* ========================================================================== + MFENCE + ========================================================================== *) + +union ast member unit MFENCE + +function clause execute (MFENCE) = + X86_MFENCE () + +(* ========================================================================== + Monop + ========================================================================== *) + +union ast member (bool,monop_name,wsize,rm) Monop + +function clause execute (Monop (locked,mop,sz,r)) = + let e = ea_rm (sz, r) in write_monop (locked, sz, mop, EA(locked, e), e) + +(* ========================================================================== + MOV + ========================================================================== *) + +union ast member (cond,wsize,dest_src) MOV + +function clause execute (MOV (c,sz,ds)) = + if read_cond (c) then + let src = ea_src (sz, ds) in + let dst = ea_dest (sz, ds) in + wEA(false, dst) := EA(false, src) + else () + +(* ========================================================================== + MOVSX + ========================================================================== *) + +union ast member (wsize,dest_src,wsize) MOVSX + +function clause execute (MOVSX (sz1,ds,sz2)) = + let src = ea_src (sz1, ds) in + let dst = ea_dest (sz2, ds) in + wEA(false, dst) := sign_extension (EA(false, src), sz1, sz2) + +(* ========================================================================== + MOVZX + ========================================================================== *) + +union ast member (wsize,dest_src,wsize) MOVZX + +function clause execute (MOVZX (sz1,ds,sz2)) = + let src = ea_src (sz1, ds) in + let dst = ea_dest (sz2, ds) in + wEA(false, dst) := EA(false, src) + +(* ========================================================================== + MUL + ========================================================================== *) + +union ast member (wsize,rm) X86_MUL + +function clause execute (X86_MUL (sz,r)) = + let eax = Ea_r (sz, 0) in (* RAX *) + let val_eax = EA(false, eax) in + let val_src = EA(false, ea_rm (sz, r)) in + switch sz { + case (Sz8(_)) -> wEA(false, Ea_r(Sz16,0)) := (val_eax * val_src)[63 .. 0] + case _ -> + let m = val_eax * val_src in + let edx = Ea_r (sz, 2) in (* RDX *) + { + wEA(false, eax) := m[63 .. 0]; + wEA(false, edx) := (m >> size_width(sz))[63 .. 0] + } + } + +(* ========================================================================== + NOP + ========================================================================== *) + +union ast member nat NOP + +function clause execute (NOP (_)) = () + +(* ========================================================================== + POP + ========================================================================== *) + +union ast member rm POP + +function clause execute (POP (r)) = pop(r) + +(* ========================================================================== + PUSH + ========================================================================== *) + +union ast member imm_rm PUSH + +function clause execute (PUSH (i)) = push(i) + +(* ========================================================================== + RET + ========================================================================== *) + +union ast member qword RET + +function clause execute (RET (i)) = +{ + pop_rip(); + drop(i); +} + +(* ========================================================================== + SET + ========================================================================== *) + +union ast member (cond,bool,rm) SET + +function clause execute (SET (c,b,r)) = + wEA(false, ea_rm(Sz8(b),r)) := if read_cond (c) then 1 else 0 + +(* ========================================================================== + STC + ========================================================================== *) + +union ast member unit STC + +function clause execute STC = CF := true + +(* ========================================================================== + XADD + ========================================================================== *) + +union ast member (bool, wsize,rm,regn) XADD + +function clause execute (XADD (locked,sz,r,n)) = + let src = Ea_r (sz, n) in + let dst = ea_rm (sz, r) in + let val_src = EA(false, src) in + let val_dst = EA(locked, dst) in + { + wEA(false, src) := val_dst; + write_binop (locked, sz, X86_Add, val_src, val_dst, dst); + } + +(* ========================================================================== + XCHG + ========================================================================== *) + +union ast member (bool,wsize,rm,regn) XCHG + +function clause execute (XCHG (locked,sz,r,n)) = + let src = Ea_r (sz, n) in + let dst = ea_rm (sz, r) in + let val_src = EA(false, src) in + let val_dst = EA(locked, dst) in + { + wEA(false, src) := val_dst; + wEA(locked, dst) := val_src; + } + +end ast +end execute + +(* -------------------------------------------------------------------------- + Decoding + -------------------------------------------------------------------------- *) +(* +function (qword,ostream) oimmediate8 ((ostream) strm) = + switch strm { + case (Some (b :: t)) -> ((qword) (EXTS(b)), Some (t)) + case _ -> ((qword) undefined, (ostream) None) + } + +function (qword,ostream) immediate8 ((byte_stream) strm) = + oimmediate8 (Some (strm)) + +function (qword,ostream) immediate16 ((byte_stream) strm) = + switch strm { + case b1 :: b2 :: t -> ((qword) (EXTS(b2 : b1)), Some (t)) + case _ -> ((qword) undefined, (ostream) None) + } + +function (qword,ostream) immediate32 ((byte_stream) strm) = + switch strm { + case b1 :: b2 :: b3 :: b4 :: t -> + ((qword) (EXTS(b4 : b3 : b2 : b1)), Some (t)) + case _ -> ((qword) undefined, (ostream) None) + } + +function (qword,ostream) immediate64 ((byte_stream) strm) = + switch strm { + case b1 :: b2 :: b3 :: b4 :: b5 :: b6 :: b7 :: b8 :: t -> + ((qword) (EXTS(b8 : b7 : b6 : b5 : b4 : b3 : b2 : b1)), Some (t)) + case _ -> ((qword) undefined, (ostream) None) + } + +function (qword, ostream) immediate ((wsize) sz, (byte_stream) strm) = + switch sz { + case (Sz8 (_)) -> immediate8 (strm) + case Sz16 -> immediate16 (strm) + case _ -> immediate32 (strm) + } + +function (qword, ostream) oimmediate ((wsize) sz, (ostream) strm) = + switch strm { + case (Some (s)) -> immediate (sz, s) + case None -> ((qword) undefined, (ostream) None) + } + +function (qword, ostream) full_immediate ((wsize) sz, (byte_stream) strm) = + if sz == Sz64 then immediate64 (strm) else immediate (sz, strm) + +(* - Parse ModR/M and SIB bytes --------------------------------------------- *) + +typedef REX = register bits [3 : 0] { + 3 : W; + 2 : R; + 1 : X; + 0 : B +} + +function regn rex_reg ((bit[1]) b, (bit[3]) r) = unsigned(b : r) + +function (qword, ostream) read_displacement ((bit[2]) Mod, (byte_stream) strm) = + if Mod == 0b01 + then immediate8 (strm) + else if Mod == 0b10 + then immediate32 (strm) + else (0x0000000000000000, (Some (strm))) + +function (qword, ostream) + read_sib_displacement ((bit[2]) Mod, (byte_stream) strm) = + if Mod == 0b01 then immediate8 (strm) else immediate32 (strm) + +function (rm, ostream) + read_SIB ((REX) rex, (bit[2]) Mod, (byte_stream) strm) = + switch strm { + case ((bit[2]) SS : (bit[3]) Index : (bit[3]) Base) :: strm1 -> + (let bbase = rex_reg (rex.B, Base) in + let index = rex_reg (rex.X, Index) in + let scaled_index = if index == 4 (* RSP *) then + (option<scale_index>) None + else let x = (scale_index) (SS, index) in + Some (x) in + (if bbase == 5 (* RBP *) + then let (displacement, strm2) = + read_sib_displacement (Mod, strm1) in + let bbase = if Mod == 0b00 then NoBase else RegBase (bbase) + in + (Mem (scaled_index, bbase, displacement), strm2) + else let (displacement, strm2) = read_displacement (Mod, strm1) in + (Mem (scaled_index, RegBase (bbase), displacement), strm2))) + case _ -> ((rm) undefined, (ostream) None) + } + +function (regn, rm, ostream) read_ModRM ((REX) rex, (byte_stream) strm) = + switch strm { + case (0b00 : (bit[3]) RegOpc : 0b101) :: strm1 -> + let (displacement, strm2) = immediate32 (strm1) in + (rex_reg (rex.R, RegOpc), Mem (None, RipBase, displacement), strm2) + case (0b11 : (bit[3]) REG : (bit[3]) RM) :: strm1 -> + (rex_reg (rex.R, REG), Reg (rex_reg (rex.B, RM)), Some (strm1)) + case ((bit[2]) Mod : (bit[3]) RegOpc : 0b100) :: strm1 -> + let (sib, strm2) = read_SIB (rex, Mod, strm1) in + (rex_reg (rex.R, RegOpc), sib, strm2) + case ((bit[2]) Mod : (bit[3]) RegOpc : (bit[3]) RM) :: strm1 -> + let (displacement, strm2) = read_displacement (Mod, strm1) in + (rex_reg (rex.R, RegOpc), + Mem (None, RegBase (rex_reg (rex.B, RM)), displacement), + strm2) + case _ -> ((regn) undefined, (rm) undefined, (ostream) None) + } + +function (bit[3], rm, ostream) + read_opcode_ModRM ((REX) rex, (byte_stream) strm) = + let (opcode, r, strm1) = read_ModRM (rex, strm) in + ((bit[3]) (cast_int_vec((int) opcode mod 8)), r, strm1) + +(* - Prefixes --------------------------------------------------------------- *) + +typedef prefix = [|5|] + +function prefix prefix_group ((byte) b) = + switch b { + case 0xf0 -> 1 + case 0xf2 -> 1 + case 0xf3 -> 1 + case 0x26 -> 2 + case 0x2e -> 2 + case 0x36 -> 2 + case 0x3e -> 2 + case 0x64 -> 2 + case 0x65 -> 2 + case 0x66 -> 3 + case 0x67 -> 4 + case _ -> if b[7 .. 4] == 0b0100 then 5 else 0 + } + +typedef atuple = (byte_stream, bool, REX, byte_stream) + +val (list<prefix>, byte_stream, byte_stream) -> option<atuple> effect {undef} read_prefix + +function rec option<atuple> read_prefix + ((list<prefix>) s, (byte_stream) p, (byte_stream) strm) = + switch strm { + case h :: strm1 -> + let group = prefix_group (h) in + if group == 0 then + let x = (p, false, (REX) 0b0000, strm) in Some (x) + else if group == 5 then + let x = (p, true, (REX) (h[3 .. 0]), strm1) in Some (x) + else if ismember (group, s) then + None + else + read_prefix (group :: s, h :: p, strm1) + case _ -> let x = (p, false, (REX) undefined, strm) in Some (x) + } + +function option<atuple> read_prefixes ((byte_stream) strm) = + read_prefix ([||||], [||||], strm) + +function wsize op_size ((bool) have_rex, (bit[1]) w, (bit[1]) v, (bool) override) = + if v == 1 then + Sz8 (have_rex) + else if w == 1 then + Sz64 + else if override then + Sz16 + else + Sz32 + +function bool is_mem ((rm) r) = + switch r {case (Mem (_, _, _)) -> true case _ -> false} + +(* - Decoder ---------------------------------------------------------------- *) + +function (ast, ostream) decode_aux + ((byte_stream) strm, (bool) have_rex, (REX) rex, (bool) op_size_override) = + switch strm + { + case (0b00 : (bit[3]) opc : 0b0 : (bit[1]) x : (bit[1]) v) :: strm2 -> + let (reg, r, strm3) = read_ModRM (rex, strm2) in + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let binop = opc_to_binop_name (EXTZ (opc)) in + let src_dst = if x == 0 then Rm_r (r, reg) else R_rm (reg, r) in + (Binop (binop, sz, src_dst), strm3) + case (0b00 : (bit[3]) opc : 0b10 : (bit[1]) v) :: strm2 -> + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let binop = opc_to_binop_name (EXTZ (opc)) in + let (imm, strm3) = immediate (sz, strm2) in + (Binop (binop, sz, Rm_i (Reg (0), imm)), strm3) + case (0x5 : (bit[1]) b : (bit[3]) r) :: strm2 -> + let reg = Reg (([|15|]) (rex.B : r)) in + (if b == 0b0 then PUSH (Rm (reg)) else POP (reg), Some (strm2)) + case 0x63 :: strm2 -> + let (reg, r, strm3) = read_ModRM (rex, strm2) in + (MOVSX (Sz32, R_rm (reg, r), Sz64), strm3) + case (0x6 : 0b10 : (bit[1]) b : 0b0) :: strm2 -> + let (imm, strm3) = if b == 1 then immediate8 (strm2) + else immediate32 (strm2) in + (PUSH (Imm (imm)), strm3) + case (0x7 : (bit[4]) c) :: strm2 -> + let (imm, strm3) = immediate8 (strm2) in + (Jcc (bv_to_cond (c), imm), strm3) + case (0x8 : 0b000 : (bit[1]) v) :: strm2 -> + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let (opc, r, strm3) = read_opcode_ModRM (rex, strm2) in + let (imm, strm4) = oimmediate (sz, strm3) in + let binop = opc_to_binop_name (EXTZ (opc)) in + (Binop (binop, sz, Rm_i (r, imm)), strm4) + case 0x83 :: strm2 -> + let sz = op_size (have_rex, rex.W, 1, op_size_override) in + let (opc, r, strm3) = read_opcode_ModRM (rex, strm2) in + let (imm, strm4) = oimmediate (sz, strm3) in + let binop = opc_to_binop_name (EXTZ (opc)) in + (Binop (binop, sz, Rm_i (r, imm)), strm4) + case (0x8 : 0b010 : (bit[1]) v) :: strm2 -> + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let (reg, r, strm3) = read_ModRM (rex, strm2) in + (Binop (Test, sz, Rm_r (r, reg)), strm3) + case (0x8 : 0b011 : (bit[1]) v) :: strm2 -> + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let (reg, r, strm3) = read_ModRM (rex, strm2) in + (XCHG (sz, r, reg), strm3) + case (0x8 : 0b10 : (bit[1]) x : (bit[1]) v) :: strm2 -> + let (reg, r, strm3) = read_ModRM (rex, strm2) in + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let src_dst = if x == 0 then Rm_r (r, reg) else R_rm (reg, r) in + (MOV (ALWAYS, sz, src_dst), strm3) + case 0x8d :: strm2 -> + let sz = op_size (true, rex.W, 1, op_size_override) in + let (reg, r, strm3) = read_ModRM (rex, strm2) in + if is_mem (r) then (LEA (sz, R_rm (reg, r)), strm3) else exit () + case 0x8f :: strm2 -> + let (opc, r, strm3) = read_opcode_ModRM (rex, strm2) in + if opc == 0 then (POP (r), strm3) else exit () + case (0x9 : 0b0 : (bit[3]) r) :: strm2 -> + let sz = op_size (true, rex.W, 1, op_size_override) in + let reg = rex_reg (rex.B, r) in + if reg == 0 then + (NOP (listlength (strm)), Some (strm2)) + else + (XCHG (sz, Reg (0), reg), Some (strm2)) + case (0xa : 0b100 : (bit[1]) v) :: strm2 -> + let sz = op_size (true, rex.W, v, op_size_override) in + let (imm, strm3) = immediate (sz, strm2) in + (Binop (Test, sz, Rm_i (Reg (0), imm)), strm3) + case (0xb : (bit[1]) v : (bit[3]) r) :: strm2 -> + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let (imm, strm3) = full_immediate (sz, strm2) in + let reg = rex_reg (rex.B, r) in + (MOV (ALWAYS, sz, Rm_i (Reg (reg), imm)), strm3) + case (0xc : 0b000 : (bit[1]) v) :: strm2 -> + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let (opc, r, strm3) = read_opcode_ModRM (rex, strm2) in + let (imm, strm4) = oimmediate8 (strm3) in + let binop = opc_to_binop_name (0b1 : opc) in + if opc == 0b110 then exit () + else (Binop (binop, sz, Rm_i (r, imm)), strm4) + case (0xc : 0b001 : (bit[1]) v) :: strm2 -> + if v == 0 then + let (imm, strm3) = immediate16 (strm2) in (RET (imm), strm3) + else + (RET (0), Some (strm2)) + case (0xc : 0b011 : (bit[1]) v) :: strm2 -> + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let (opc, r, strm3) = read_opcode_ModRM (rex, strm2) in + let (imm, strm4) = oimmediate (sz, strm3) in + if opc == 0 then (MOV (ALWAYS, sz, Rm_i (r, imm)), strm4) + else exit () + case 0xc9 :: strm2 -> + (LEAVE, Some (strm2)) + case (0xd : 0b00 : (bit[1]) b : (bit[1]) v) :: strm2 -> + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let (opc, r, strm3) = read_opcode_ModRM (rex, strm2) in + let shift = if b == 0 then Rm_i (r, 1) else Rm_r (r, 1) in + let binop = opc_to_binop_name (0b1 : opc) in + if opc == 0b110 then exit () + else (Binop (binop, sz, shift), strm3) + case (0xe : 0b000 : (bit[1]) b) :: strm2 -> + let (imm, strm3) = immediate8 (strm2) in + let cnd = if b == 0 then NE else E in + (LOOP (cnd, imm), strm3) + case 0xe2 :: strm2 -> + let (imm, strm3) = immediate8 (strm2) in + (LOOP (ALWAYS, imm), strm3) + case 0xe8 :: strm2 -> + let (imm, strm3) = immediate32 (strm2) in + (CALL (Imm (imm)), strm3) + case (0xe : 0b10 : (bit[1]) b : 0b1) :: strm2 -> + let (imm, strm3) = if b == 0 then immediate32 (strm2) + else immediate8 (strm2) in + (Jcc (ALWAYS, imm), strm3) + case 0xf5 :: strm2 -> (CMC, Some (strm2)) + case 0xf8 :: strm2 -> (CLC, Some (strm2)) + case 0xf9 :: strm2 -> (STC, Some (strm2)) + case (0xf : 0b011 : (bit[1]) v) :: strm2 -> + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let (opc, r, strm3) = read_opcode_ModRM (rex, strm2) in + switch opc { + case 0b000 -> let (imm, strm4) = oimmediate (sz, strm3) in + (Binop (Test, sz, Rm_i (r, imm)), strm4) + case 0b010 -> (Monop (Not, sz, r), strm3) + case 0b011 -> (Monop (Neg, sz, r), strm3) + case 0b100 -> (MUL (sz, r), strm3) + case 0b110 -> (DIV (sz, r), strm3) + case _ -> exit () + } + case 0xfe :: strm2 -> + let (opc, r, strm3) = read_opcode_ModRM (rex, strm2) in + switch opc { + case 0b000 -> (Monop (Inc, Sz8 (have_rex), r), strm3) + case 0b001 -> (Monop (Dec, Sz8 (have_rex), r), strm3) + case _ -> exit () + } + case 0xff :: strm2 -> + let sz = op_size (have_rex, rex.W, 1, op_size_override) in + let (opc, r, strm3) = read_opcode_ModRM (rex, strm2) in + switch opc { + case 0b000 -> (Monop (Inc, sz, r), strm3) + case 0b001 -> (Monop (Dec, sz, r), strm3) + case 0b010 -> (CALL (Rm (r)), strm3) + case 0b100 -> (JMP (r), strm3) + case 0b110 -> (PUSH (Rm (r)), strm3) + case _ -> exit () + } + case 0x0f :: opc :: strm2 -> + switch opc { + case 0x1f -> + let (opc, r, strm3) = read_opcode_ModRM (rex, strm2) in + (NOP (listlength (strm)), strm3) + case (0x4 : (bit[4]) c) -> + let sz = op_size (true, rex.W, 1, op_size_override) in + let (reg, r, strm3) = read_ModRM (rex, strm2) in + (MOV (bv_to_cond (c), sz, R_rm (reg, r)), strm3) + case (0x8 : (bit[4]) c) -> + let (imm, strm3) = immediate32 (strm2) in + (Jcc (bv_to_cond (c), imm), strm3) + case (0x9 : (bit[4]) c) -> + let (reg, r, strm3) = read_ModRM (rex, strm2) in + (SET (bv_to_cond (c), have_rex, r), strm3) + case (0xb : 0b000 : (bit[1]) v) -> + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let (reg, r, strm3) = read_ModRM (rex, strm2) in + (CMPXCHG (sz, r, reg), strm3) + case (0xc : 0b000 : (bit[1]) v) -> + let sz = op_size (have_rex, rex.W, v, op_size_override) in + let (reg, r, strm3) = read_ModRM (rex, strm2) in + (XADD (sz, r, reg), strm3) + case (0xb : (bit[1]) s : 0b11 : (bit[1]) v) -> + let sz2 = op_size (have_rex, rex.W, 1, op_size_override) in + let sz = if v == 1 then Sz16 else Sz8 (have_rex) in + let (reg, r, strm3) = read_ModRM (rex, strm2) in + if s == 1 then + (MOVSX (sz, R_rm (reg, r), sz2), strm3) + else + (MOVZX (sz, R_rm (reg, r), sz2), strm3) + case _ -> exit () + } + case _ -> exit () + } + +function (byte_stream, ast, nat) decode ((byte_stream) strm) = + switch read_prefixes (strm) + { + case None -> exit () + case (Some (prefixes, have_rex, rex, strm1)) -> + let op_size_override = ismember (0x66, prefixes) in + if rex.W == 1 & op_size_override | ismember (0x67, prefixes) then + exit () + else + switch decode_aux (strm1, have_rex, rex, op_size_override) { + case (instr, (Some (strm2))) -> (prefixes, instr, listlength (strm2)) + case _ -> exit () + } + } + *) + +let (vector <0, 16, inc, string >) GPRstr = + ["RAX","RCX","RDX","RBX","RSP","RBP","RSI","RDI","R8","R9","R10","R11","R12","R13","R14","R15"] + +function (regfps) regfp_base ((base) b) = + switch b { + case NoBase -> [|| ||] + case RipBase -> [|| RFull("RIP") ||] + case (RegBase(b)) -> [|| RFull(GPRstr[b]) ||] + } + +function (regfps) regfp_idx ((option<scale_index>) idx) = + switch idx { + case (None) -> [|| ||] + case (Some(scale, idx)) -> [|| RFull(GPRstr[idx]) ||] + } + +function (bool, regfps, regfps) regfp_rm ((rm) r) = + switch r { + case (X86_Reg(n)) -> + (false, [|| RFull(GPRstr[n]) ||], [|| ||]) + case (Mem(idx, b, d)) -> { + (true, [|| ||], append(regfp_idx(idx), regfp_base(b))) + } + } + +function (instruction_kind, regfps, regfps, regfps) regfp_dest_src ((dest_src) ds) = + switch ds { + case (Rm_i (r_m, i)) -> + let (m,rd,ars) = regfp_rm(r_m) in + (if m then IK_mem_write(Write_plain) else IK_simple, ars, rd, ars) + case (Rm_r (r_m, r)) -> + let (m,rd,ars) = regfp_rm(r_m) in + (if m then IK_mem_write(Write_plain) else IK_simple, RFull(GPRstr[r]) :: ars, rd, ars) + case (R_rm (r, r_m)) -> + let (m,rs,ars) = regfp_rm(r_m) in + (if m then IK_mem_read(Read_plain) else IK_simple, append(rs, ars), [|| RFull(GPRstr[r]) ||], ars) + } + +(* as above but where destination is also a source operand *) +function (instruction_kind, regfps, regfps, regfps) regfp_dest_src_rmw (locked, (dest_src) ds) = + let rk = if locked then Read_X86_locked else Read_plain in + let wk = if locked then Write_X86_locked else Write_plain in + switch ds { + case (Rm_i (r_m, i)) -> + let (m,rds, ars) = regfp_rm(r_m) in + (if m then IK_mem_rmw(rk, wk) else IK_simple, append(rds, ars), rds, ars) + case (Rm_r (r_m, r)) -> + let (m,rds, ars) = regfp_rm(r_m) in + (if m then IK_mem_rmw(rk, wk) else IK_simple, RFull(GPRstr[r]) :: append(rds, ars), rds, ars) + case (R_rm (r, r_m)) -> + let rds = [|| RFull(GPRstr[r]) ||] in + let (m,rs,ars) = regfp_rm(r_m) in + (if m then IK_mem_read(Read_plain) else IK_simple, append(rds, ars), rds, ars) + } + +function (bool, regfps, regfps) regfp_imm_rm ((imm_rm) i_rm) = + switch i_rm { + case (Rm (v)) -> regfp_rm (v) + case (Imm (v)) -> (false, [|| ||], [|| ||]) + } + +let all_flags_but_cf_of = [|| RFull("AF"), RFull("PF"), RFull("SF"), RFull("ZF") ||] +let all_flags = append([|| RFull("CF"), RFull("OF") ||], all_flags_but_cf_of) + +function (regfps) regfp_binop_flags ((binop_name) op) = + switch (op) { + case X86_Add -> all_flags + case X86_Sub -> all_flags + case X86_Cmp -> all_flags + case X86_Test -> all_flags_but_cf_of + case X86_And -> all_flags_but_cf_of + case X86_Xor -> all_flags_but_cf_of + case X86_Or -> all_flags_but_cf_of + case X86_Rol -> all_flags + case X86_Ror -> all_flags + case X86_Sar -> all_flags + case X86_Shl -> all_flags + case X86_Shr -> all_flags + case X86_Adc -> all_flags + case X86_Sbb -> all_flags + } +function (regfps) regfp_cond ((cond) c) = + switch c { + case X86_A -> [|| RFull("CF"), RFull("ZF") ||] + case X86_NB -> [|| RFull("CF") ||] + case X86_B -> [|| RFull("CF") ||] + case X86_NA -> [|| RFull("CF"), RFull("ZF") ||] + case X86_E -> [|| RFull("ZF") ||] + case X86_G -> [|| RFull("ZF"), RFull("SF"), RFull("OF") ||] + case X86_NL -> [|| RFull("SF"), RFull("OF") ||] + case X86_L -> [|| RFull("SF"), RFull("OF") ||] + case X86_NG -> [|| RFull("ZF"), RFull("SF"), RFull("OF") ||] + case X86_NE -> [|| RFull("ZF") ||] + case X86_NO -> [|| RFull("OF") ||] + case X86_NP -> [|| RFull("PF") ||] + case X86_NS -> [|| RFull("SF") ||] + case X86_O -> [|| RFull("OF") ||] + case X86_P -> [|| RFull("PF") ||] + case X86_S -> [|| RFull("SF") ||] + case X86_ALWAYS -> [|| ||] + } + +function (regfps,regfps,regfps,niafps,diafp,instruction_kind) initial_analysis (instr) = { + iR := [|| ||]; + oR := [|| ||]; + aR := [|| ||]; + ik := IK_simple; + Nias := [|| NIAFP_successor ||]; + Dia := DIAFP_none; + switch instr { + case(Binop (locked, binop, sz, ds)) -> { + let flags = regfp_binop_flags (binop) in + let (ik', iRs, oRs, aRs) = regfp_dest_src_rmw(locked, ds) in { + ik := ik'; + iR := append(iRs, iR); + oR := append(flags, append(oRs, oR)); + aR := append(aRs, aR); + } + } + case(Bitop (locked, bitop, sz, bitoff)) -> { + let rk = if locked then Read_X86_locked else Read_plain in + let wk = if locked then Write_X86_locked else Write_plain in + let (ik', iRs, oRs, aRs) = switch(bitoff) { + case (Bit_rm_imm (r_m, imm)) -> + let (m, rs, ars) = regfp_rm(r_m) in + (if m then IK_mem_rmw(rk, wk) else IK_simple, + append(rs, ars), rs, ars) + case (Bit_rm_r (r_m, r)) -> + let rfp = RFull(GPRstr[r]) in + let (m, rs, ars) = regfp_rm(r_m) in + (if m then IK_mem_rmw(rk, wk) else IK_simple, + rfp::append(rs, ars), rs, + if m then (rfp::ars) else ars) (* in memory case r is a third input to address! *) + } in { + ik := ik'; + iR := append(iRs, iR); + oR := RFull("CF")::append(oRs, oR); + aR := append(aRs, aR); + } + } + case(CALL (irm) ) -> + let (m, rs, ars) = regfp_imm_rm (irm) in { + ik := if m then IK_mem_rmw(Read_plain, Write_plain) else IK_mem_write(Write_plain); + iR := RFull("RIP") :: RFull("RSP") :: rs; + oR := RFull("RSP") :: oR; + aR := ars; + Nias := switch irm { + case (Rm (v)) -> NIAFP_indirect_address + case (Imm (v)) -> NIAFP_concrete_address(RIP + v) + } :: Nias; + } + case(CLC ) -> oR := RFull("CF") :: oR + case(CMC ) -> { + iR := RFull("CF") :: iR; + oR := RFull("CF") :: oR; + } + case(CMPXCHG (locked, sz, r_m, reg) ) -> + let rk = if locked then Read_X86_locked else Read_plain in + let wk = if locked then Write_X86_locked else Write_plain in + let (m, rs, aRs) = regfp_rm (r_m) in { + ik := if m then IK_mem_rmw (rk, wk) else IK_simple; + iR := RFull("RAX") :: RFull(GPRstr[reg]) :: append(rs, aRs); + oR := RFull("RAX") :: append(regfp_binop_flags(X86_Cmp), rs); + aR := aRs; + } + case(X86_DIV (sz, r_m) ) -> + let (m, rs, ars) = regfp_rm (r_m) in { + ik := if m then IK_mem_read (Read_plain) else IK_simple; + iR := RFull("RAX") :: RFull("RDX") :: append(rs, ars); + oR := RFull("RAX") :: RFull("RDX") :: append(oR, all_flags); + aR := ars; + } + case(HLT ) -> () + case(Jcc (c, imm64) ) -> + let flags = regfp_cond(c) in { + ik := IK_branch; + iR := RFull("RIP") :: flags; + Nias := NIAFP_concrete_address(RIP + imm64) :: Nias; + } + case(JMP (r_m) ) -> + let (m, rs, ars) = regfp_rm (r_m) in { + ik := if m then IK_mem_read(Read_plain) else IK_simple; + iR := RFull("RIP")::append(rs, ars); + aR := ars; + Nias := NIAFP_indirect_address :: Nias; + } + case(LEA (sz, ds) ) -> + let (_, irs, ors, ars) = regfp_dest_src (ds) in { + iR := irs; + oR := ors; + aR := ars; + } + case(LEAVE ) -> { + ik := IK_mem_read(Read_plain); + iR := RFull("RBP") :: iR; + oR := RFull("RBP") :: RFull("RSP") :: oR; + aR := RFull("RBP") :: aR; + } + case(LOOP (c, imm64) ) -> + let flags = regfp_cond(c) in { + ik := IK_branch; + iR := RFull("RCX") :: flags; + oR := RFull("RCX") :: oR; + Nias := NIAFP_concrete_address(RIP + imm64) :: Nias; + } + case(MFENCE ) -> + ik := IK_barrier (Barrier_x86_MFENCE) + case(Monop (locked, monop, sz, r_m) ) -> + let rk = if locked then Read_X86_locked else Read_plain in + let wk = if locked then Write_X86_locked else Write_plain in + let (m, rds, ars) = regfp_rm(r_m) in { + ik := if m then IK_mem_rmw(rk, wk) else IK_simple; + iR := append(rds, ars); + oR := append(all_flags_but_cf_of, rds); (* XXX fix flags *) + aR := ars; + } + case(MOV (c, sz, ds) ) -> + let (ik', irs, ors, ars) = regfp_dest_src (ds) in + let flags = regfp_cond(c) in + { + ik := ik'; + iR := append(irs, flags); + oR := ors; + aR := ars; + } + case(MOVSX (sz1, ds, sz2) ) -> + let (ik', irs, ors, ars) = regfp_dest_src (ds) in { + ik := ik'; + iR := irs; + oR := ors; + aR := ars; + } + case(MOVZX (sz1, ds, sz2) ) -> + let (ik', irs, ors, ars) = regfp_dest_src (ds) in { + ik := ik'; + iR := irs; + oR := ors; + aR := ars; + } + case(X86_MUL (sz, r_m) ) -> + let (m, rs, ars) = regfp_rm (r_m) in { + ik := if m then IK_mem_read (Read_plain) else IK_simple; + iR := RFull("RAX") :: append(rs, ars); + oR := RFull("RAX") :: RFull("RDX") :: append(oR, all_flags); + aR := ars; + } + case(NOP (_) ) -> () + case(POP (r_m) ) -> + let (m, rd, ars) = regfp_rm (r_m) in { + ik := if m then IK_mem_rmw(Read_plain, Write_plain) else IK_mem_write(Write_plain); + iR := RFull("RSP") :: ars; + oR := RFull("RSP") :: rd; + aR := RFull("RSP") :: ars; + } + case(PUSH (irm) ) -> + let (m, rs, ars) = regfp_imm_rm (irm) in { + ik := if m then IK_mem_rmw(Read_plain, Write_plain) else IK_mem_write(Write_plain); + iR := RFull("RSP") :: append(rs, ars); + oR := RFull("RSP") :: oR; + aR := RFull("RSP") :: ars; + } + case(RET (imm64) ) -> { + ik := IK_mem_read(Read_plain); + iR := RFull("RSP") :: iR; + oR := RFull("RSP") :: oR; + aR := RFull("RSP") :: aR; + Nias := NIAFP_indirect_address :: Nias; + } + case(SET (c, b, r_m) ) -> + let flags = regfp_cond(c) in + let (m, rs, ars) = regfp_rm(r_m) in { + ik := if m then IK_mem_write(Write_plain) else IK_simple; + iR := append(flags, ars); + oR := rs; + aR := ars; + } + case(STC ) -> oR := [|| RFull("CF") ||] + case(XADD (locked, sz, r_m, reg) ) -> + let rk = if locked then Read_X86_locked else Read_plain in + let wk = if locked then Write_X86_locked else Write_plain in + let (m, rs, ars) = regfp_rm(r_m) in { + ik := if m then IK_mem_rmw(rk, wk) else IK_simple; + iR := RFull(GPRstr[reg]) :: append(rs, ars); + oR := RFull(GPRstr[reg]) :: append(rs, all_flags); + aR := ars; + } + case(XCHG (locked, sz, r_m, reg) ) -> + let rk = if locked then Read_X86_locked else Read_plain in + let wk = if locked then Write_X86_locked else Write_plain in + let (m, rs, ars) = regfp_rm(r_m) in { + ik := if m then IK_mem_rmw(rk, wk) else IK_simple; + iR := RFull(GPRstr[reg]) :: append(rs, ars); + oR := RFull(GPRstr[reg]) :: rs; + aR := ars; + } + }; + (iR,oR,aR,Nias,Dia,ik) +} diff --git a/old/x86/x86_extras.lem b/old/x86/x86_extras.lem new file mode 100644 index 00000000..d6498d87 --- /dev/null +++ b/old/x86/x86_extras.lem @@ -0,0 +1,53 @@ +open import Pervasives +open import Interp_ast +open import Interp_interface +open import Sail_impl_base +open import Interp_inter_imp +import Set_extra + +let memory_parameter_transformer mode v = + match v with + | Interp_ast.V_tuple [location;length] -> + let (v,loc_regs) = extern_with_track mode extern_vector_value location in + + match length with + | Interp_ast.V_lit (L_aux (L_num len) _) -> + (v,(natFromInteger len),loc_regs) + | Interp_ast.V_track (Interp_ast.V_lit (L_aux (L_num len) _)) size_regs -> + match loc_regs with + | Nothing -> (v,(natFromInteger len),Just (List.map (fun r -> extern_reg r Nothing) (Set_extra.toList size_regs))) + | Just loc_regs -> (v,(natFromInteger len),Just (loc_regs++(List.map (fun r -> extern_reg r Nothing) (Set_extra.toList size_regs)))) + end + | _ -> Assert_extra.failwith "expected 'V_lit (L_aux (L_num _) _)' or 'V_track (V_lit (L_aux (L_num len) _)) _'" + end + | _ -> Assert_extra.failwith ("memory_parameter_transformer: expected 'V_tuple [_;_]' given " ^ (Interp.string_of_value v)) + end + +let memory_parameter_transformer_option_address _mode v = + match v with + | Interp_ast.V_tuple [location;_] -> + Just (extern_vector_value location) + | _ -> Assert_extra.failwith ("memory_parameter_transformer_option_address: expected 'V_tuple [_;_]' given " ^ (Interp.string_of_value v)) + end + +let x86_read_memory_functions : memory_reads = + [ ("rMEM", (MR Read_plain memory_parameter_transformer)); + ("rMEM_locked", (MR Read_X86_locked memory_parameter_transformer)); + ] + +let x86_memory_writes : memory_writes = + [] + +let x86_memory_eas : memory_write_eas = + [ ("MEMea", (MEA Write_plain memory_parameter_transformer)); + ("MEMea_locked", (MEA Write_X86_locked memory_parameter_transformer)); + ] + +let x86_memory_vals : memory_write_vals = + [ ("MEMval", (MV memory_parameter_transformer_option_address Nothing)); + ] + +let x86_barrier_functions = + [ + ("X86_MFENCE", Barrier_x86_MFENCE); + ] diff --git a/old/x86/x86_extras_embed.lem b/old/x86/x86_extras_embed.lem new file mode 100644 index 00000000..f5130995 --- /dev/null +++ b/old/x86/x86_extras_embed.lem @@ -0,0 +1,24 @@ +open import Pervasives +open import Pervasives_extra +open import Sail_impl_base +open import Sail_values +open import Prompt + +val rMEM : (vector bitU * integer) -> M (vector bitU) +val rMEM_locked : (vector bitU * integer) -> M (vector bitU) + +let rMEM (addr,size) = read_mem false Read_plain addr size +let rMEM_locked (addr,size) = read_mem false Read_X86_locked addr size + +val MEMea : (vector bitU * integer) -> M unit +val MEMea_locked : (vector bitU * integer) -> M unit + +let MEMea (addr,size) = write_mem_ea Write_plain addr size +let MEMea_locked (addr,size) = write_mem_ea Write_X86_locked addr size + +val MEMval : (vector bitU * integer * vector bitU) -> M unit +val MEMval_conditional : (vector bitU * integer * vector bitU) -> M bitU + +let MEMval (_,_,v) = write_mem_val v >>= fun _ -> return () + +let X86_MFENCE () = barrier Barrier_x86_MFENCE diff --git a/old/x86/x86_extras_embed_sequential.lem b/old/x86/x86_extras_embed_sequential.lem new file mode 100644 index 00000000..2703b6c4 --- /dev/null +++ b/old/x86/x86_extras_embed_sequential.lem @@ -0,0 +1,24 @@ +open import Pervasives +open import Pervasives_extra +open import Sail_impl_base +open import Sail_values +open import State + +val rMEM : (vector bitU * integer) -> M (vector bitU) +val rMEM_locked : (vector bitU * integer) -> M (vector bitU) + +let rMEM (addr,size) = read_mem false Read_plain addr size +let rMEM_locked (addr,size) = read_mem false Read_X86_locked addr size + +val MEMea : (vector bitU * integer) -> M unit +val MEMea_locked : (vector bitU * integer) -> M unit + +let MEMea (addr,size) = write_mem_ea Write_plain addr size +let MEMea_locked (addr,size) = write_mem_ea Write_X86_locked addr size + +val MEMval : (vector bitU * integer * vector bitU) -> M unit +val MEMval_conditional : (vector bitU * integer * vector bitU) -> M bitU + +let MEMval (_,_,v) = write_mem_val v >>= fun _ -> return () + +let X86_MFENCE () = barrier Barrier_x86_MFENCE |