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-rw-r--r--mips/mips_wrappers.sail4
1 files changed, 2 insertions, 2 deletions
diff --git a/mips/mips_wrappers.sail b/mips/mips_wrappers.sail
index b70853f0..b46e35be 100644
--- a/mips/mips_wrappers.sail
+++ b/mips/mips_wrappers.sail
@@ -54,12 +54,12 @@ function bool effect {wmem} MEMw_conditional_wrapper(addr, size, data) =
function bit[64] addrWrapper((bit[64]) addr, (MemAccessType) accessType, (WordType) width) =
addr
-function (bit[64]) TranslateAddress ((bit[64]) vAddr, (MemAccessType) accessType) = {
+function (bit[64]) TranslatePC ((bit[64]) vAddr) = {
incrementCP0Count();
if (vAddr[1..0] != 0b00) then (* bad PC alignment *)
(SignalExceptionBadAddr(AdEL, vAddr))
else
- TLBTranslate(vAddr, accessType)
+ TLBTranslate(vAddr, Instruction)
}
let have_cp2 = false