diff options
Diffstat (limited to 'mips')
| -rw-r--r-- | mips/mips_insts.sail | 4 | ||||
| -rw-r--r-- | mips/mips_prelude.sail | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/mips/mips_insts.sail b/mips/mips_insts.sail index a3781426..db494224 100644 --- a/mips/mips_insts.sail +++ b/mips/mips_insts.sail @@ -1455,7 +1455,7 @@ function clause execute (MFC0(rt, rd, sel, double)) = { @ 0b000 /* AR */ @ 0b001 /* MT standard TLB */ @ 0b0000 /* zero */ - @ 0b000), + @ CP0ConfigK0), (0b10000,0b001) => zero_extend( /* 16, sel 1: Config1 */ 0b1 /* M */ @ TLBIndexMax /* MMU size-1 */ @@ -1556,7 +1556,7 @@ function clause execute (MTC0(rt, rd, sel, double)) = { CP0Cause->IP() = ((ip[7..2]) @ (reg_val[9..8])); }, (0b01110,0b000) => CP0EPC = reg_val, /* 14, EPC */ - (0b10000,0b000) => (), /* XXX ignore K0 cache config 16: Config0 */ + (0b10000,0b000) => CP0ConfigK0 = reg_val[2..0], /* K0 cache config 16: Config0 */ (0b10100,0b000) => TLBXContext->XPTEBase() = reg_val[63..33], (0b11110,0b000) => CP0ErrorEPC = reg_val, /* 30, ErrorEPC */ _ => (SignalException(ResI)) diff --git a/mips/mips_prelude.sail b/mips/mips_prelude.sail index c151f38b..b5931a45 100644 --- a/mips/mips_prelude.sail +++ b/mips/mips_prelude.sail @@ -267,6 +267,7 @@ register CP0BadVAddr : bits(64) register CP0Count : bits(32) register CP0HWREna : bits(32) register CP0UserLocal : bits(64) +register CP0ConfigK0 : bits(3) bitfield StatusReg : bits(32) = { CU : 31.. 28, /* co-processor enable bits */ |