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-rw-r--r--mips/mips_tlb.sail2
1 files changed, 1 insertions, 1 deletions
diff --git a/mips/mips_tlb.sail b/mips/mips_tlb.sail
index 2e40deed..d72e0e75 100644
--- a/mips/mips_tlb.sail
+++ b/mips/mips_tlb.sail
@@ -108,7 +108,7 @@ function (bit[64], bool) TLBTranslateC ((bit[64]) vAddr, (MemAccessType) accessT
case 0b01 -> (Supervisor, None) (* xsseg - supervisor mapped *)
case 0b00 -> (User, None) (* xuseg - user mapped *)
} in
- if (((nat)currentAccessLevel) < ((nat)requiredLevel)) then
+ if ((int_of_accessLevel(currentAccessLevel)) < (int_of_accessLevel(requiredLevel))) then
(SignalExceptionBadAddr(if (accessType == StoreData) then AdES else AdEL, vAddr))
else
let (pa, c) = switch(addr) {