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Diffstat (limited to 'arm/armv8_A32_sys_regs.sail')
| -rw-r--r-- | arm/armv8_A32_sys_regs.sail | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/arm/armv8_A32_sys_regs.sail b/arm/armv8_A32_sys_regs.sail new file mode 100644 index 00000000..8b4a8e00 --- /dev/null +++ b/arm/armv8_A32_sys_regs.sail @@ -0,0 +1,61 @@ +(*========================================================================*) +(* *) +(* Copyright (c) 2015-2016 Shaked Flur *) +(* Copyright (c) 2015-2016 Kathyrn Gray *) +(* All rights reserved. *) +(* *) +(* This software was developed by the University of Cambridge Computer *) +(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) +(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in *) +(* the documentation and/or other materials provided with the *) +(* distribution. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) +(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) +(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) +(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) +(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) +(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) +(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) +(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) +(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) +(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) +(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) +(* SUCH DAMAGE. *) +(*========================================================================*) + +(*************************************************************************) +(* General system control registers *) + +register (SCRType) SCR (* Secure Configuration Register *) + +(*************************************************************************) +(* Debug registers *) + +typedef DBGOSDLR_type = register bits [31:0] +{ + (*31..1 : RES0;*) + 0 : DLK; +} +register (DBGOSDLR_type) DBGOSDLR (* Debug OS Double Lock Register *) + +register (DBGPRCR_type) DBGPRCR (* Debug Power Control Register *) + + +(*************************************************************************) +(* Performance Monitors registers *) + +(*************************************************************************) +(* Generic Timer registers *) + +(*************************************************************************) +(* Generic Interrupt Controller CPU interface registers *) + |