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Diffstat (limited to 'aarch64')
-rw-r--r--aarch64/elfmain.sail2
-rwxr-xr-xaarch64/prelude.sail2
2 files changed, 2 insertions, 2 deletions
diff --git a/aarch64/elfmain.sail b/aarch64/elfmain.sail
index 44b6c14a..24579b79 100644
--- a/aarch64/elfmain.sail
+++ b/aarch64/elfmain.sail
@@ -13,8 +13,6 @@ let CNT_IRQ = [0x0000_000d, 0x0000_000a, 0x0000_03ff, 0x000
// SGI Interrupts are 0-15, PPI interrupts are 16-31, so SPI interrupts have an offset of 32.
let SPI_OFFSET = 32
-val get_cycle_count = { c: "get_cycle_count" } : unit -> int effect {undef, wreg, rreg, rmem, wmem}
-
// Advance CPU by one cycle
val Step_CPU : unit -> unit effect {escape, undef, wreg, rreg, rmem, wmem}
diff --git a/aarch64/prelude.sail b/aarch64/prelude.sail
index 73a084c4..6ce47ae3 100755
--- a/aarch64/prelude.sail
+++ b/aarch64/prelude.sail
@@ -358,3 +358,5 @@ val __Sleeping = {ocaml: "sleeping", lem: "sleeping", smt: "sleeping", interpret
val __GetVerbosity = {c: "sail_get_verbosity"}: unit -> bits(64) effect {rreg, undef}
+val get_cycle_count = { c: "get_cycle_count" } : unit -> int effect {undef, wreg, rreg, rmem, wmem}
+