diff options
Diffstat (limited to 'aarch64/no_vector')
| -rw-r--r-- | aarch64/no_vector/spec.sail | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/aarch64/no_vector/spec.sail b/aarch64/no_vector/spec.sail index d8a05777..ccf8aba1 100644 --- a/aarch64/no_vector/spec.sail +++ b/aarch64/no_vector/spec.sail @@ -6984,7 +6984,7 @@ function __TakeColdReset () = { val AArch64_TakeException : (bits(2), ExceptionRecord, bits(64), int) -> unit effect {escape, rreg, undef, wreg} function AArch64_TakeException (target_el, exception, preferred_exception_return, vect_offset__arg) = { - vect_offset = vect_offset__arg; + vect_offset : int = vect_offset__arg; SynchronizeContext(); assert((HaveEL(target_el) & ~(ELUsingAArch32(target_el))) & UInt(target_el) >= UInt(PSTATE.EL), "((HaveEL(target_el) && !(ELUsingAArch32(target_el))) && (UInt(target_el) >= UInt((PSTATE).EL)))"); from_32 : bool = UsingAArch32(); @@ -8507,7 +8507,7 @@ val aarch64_memory_vector_single_nowb : forall ('esize : Int) ('selem : Int). function aarch64_memory_vector_single_nowb (datasize, esize, index, m, memop, n, replicate, selem, t__arg, wback) = { assert(constraint('selem >= 1 & 'esize >= 0)); - t = t__arg; + t : int = t__arg; CheckFPAdvSIMDEnabled64(); address : bits(64) = undefined; offs : bits(64) = undefined; |