diff options
240 files changed, 38422 insertions, 2472 deletions
@@ -3,6 +3,8 @@ *.byte src/_build/ src/sail.docdir +_sbuild/ +test/typecheck/rtpass*/ language/*.pdf language/*.uo language/*.ui diff --git a/aarch64/README b/aarch64/README index 452aff0f..947db614 100644 --- a/aarch64/README +++ b/aarch64/README @@ -1,4 +1,14 @@ This folder contains an automatically generated ARM v8.3 architecture specification. This specification is based on ARM's publically realeased machine-readable XML specification available at -https://github.com/meriac/archex +https://github.com/meriac/archex. See that github repository for +licensing information. + +Generated parts of the specification are contained within the +following subdirectories: + +no_vector/ - a version of the specification without vector +instructions + +duopod/ - a minimal slice of the specification with only add-sub +immediate and some memory instructions
\ No newline at end of file diff --git a/aarch64/aarch64_extras_embed_sequential.lem b/aarch64/aarch64_extras_embed_sequential.lem index a9e2e9e3..4f9e0fe3 100644 --- a/aarch64/aarch64_extras_embed_sequential.lem +++ b/aarch64/aarch64_extras_embed_sequential.lem @@ -1,10 +1,9 @@ open import Pervasives_extra open import Sail_impl_base open import Sail_values -open import Sail_operators +open import Sail_operators_bitlists open import State - type ty2048 instance (Size ty2048) let size = 2048 end declare isabelle target_rep type ty2048 = `2048` @@ -20,12 +19,16 @@ val putchar : integer -> unit let putchar _ = () declare ocaml target_rep function putchar i = (`print_char` (`char_of_int` (`Nat_big_num.to_int` i))) -let inline uint = unsigned -let inline sint = signed +val uint : list bitU -> integer +let uint = unsigned +val sint : list bitU -> integer +let sint = signed +val slice : list bitU -> integer -> integer -> list bitU let slice v lo len = subrange_vec_dec v (lo + len - 1) lo +val set_slice : integer -> integer -> list bitU -> integer -> list bitU -> list bitU let set_slice (out_len:ii) (slice_len:ii) out (n:ii) v = update_subrange_vec_dec out (n + slice_len - 1) n v @@ -35,8 +38,10 @@ let get_slice_int_bl len n lo = let bits = bits_of_int (hi + 1) n in get_bits false bits hi lo +val get_slice_int : integer -> integer -> integer -> list bitU let get_slice_int len n lo = of_bits (get_slice_int_bl len n lo) +val set_slice_int : integer -> integer -> integer -> list bitU -> integer let set_slice_int len n lo v = let hi = lo + len - 1 in let bits = bitlist_of_int n in @@ -48,7 +53,9 @@ let ext_slice signed v i j = let len = length v in let bits = get_bits false (bits_of v) i j in of_bits (if signed then exts_bits len bits else extz_bits len bits) +val exts_slice : list bitU -> integer -> integer -> list bitU let exts_slice v i j = ext_slice true v i j +val extz_slice : list bitU -> integer -> integer -> list bitU let extz_slice v i j = ext_slice false v i j val shr_int : ii -> ii -> ii @@ -90,6 +97,7 @@ let hexstring_to_bits s = | _ -> failwith "hexstring_to_bits called with unexpected string" end +val hex_slice : string -> integer -> integer -> list bitU let hex_slice v len lo = let hi = len + lo - 1 in let bits = extz_bits (len + lo) (hexstring_to_bits v) in @@ -101,7 +109,9 @@ let undefined_string () = "" let undefined_unit () = () let undefined_int () = (0:ii) let undefined_bool () = false +val undefined_vector : forall 'a. integer -> 'a -> list 'a let undefined_vector len u = repeat [u] len +val undefined_bitvector : integer -> list bitU let undefined_bitvector len = duplicate B0 len let undefined_bits len = undefined_bitvector len let undefined_bit () = B0 diff --git a/aarch64/duopod/decode.sail b/aarch64/duopod/decode.sail new file mode 100644 index 00000000..a9c4b058 --- /dev/null +++ b/aarch64/duopod/decode.sail @@ -0,0 +1,50 @@ +function clause decode _ : bits(2) @ 0b111001 @ _ : bits(24) as op_code = { + size : bits(2) = op_code[31 .. 30]; + V : bits(1) = [op_code[26]]; + opc : bits(2) = op_code[23 .. 22]; + imm12 : bits(12) = op_code[21 .. 10]; + Rn : bits(5) = op_code[9 .. 5]; + Rt : bits(5) = op_code[4 .. 0]; + memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode(size, V, opc, imm12, Rn, Rt) +} + +function clause decode _ : bits(2) @ 0b111000 @ _ : bits(2) @ 0b0 @ _ : bits(9) @ 0b01 @ _ : bits(10) as op_code = { + size : bits(2) = op_code[31 .. 30]; + V : bits(1) = [op_code[26]]; + opc : bits(2) = op_code[23 .. 22]; + imm9 : bits(9) = op_code[20 .. 12]; + Rn : bits(5) = op_code[9 .. 5]; + Rt : bits(5) = op_code[4 .. 0]; + memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode(size, V, opc, imm9, Rn, Rt) +} + +function clause decode _ : bits(2) @ 0b111000 @ _ : bits(2) @ 0b0 @ _ : bits(9) @ 0b11 @ _ : bits(10) as op_code = { + size : bits(2) = op_code[31 .. 30]; + V : bits(1) = [op_code[26]]; + opc : bits(2) = op_code[23 .. 22]; + imm9 : bits(9) = op_code[20 .. 12]; + Rn : bits(5) = op_code[9 .. 5]; + Rt : bits(5) = op_code[4 .. 0]; + memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode(size, V, opc, imm9, Rn, Rt) +} + +function clause decode _ : bits(2) @ 0b111001 @ _ : bits(24) as op_code = { + size : bits(2) = op_code[31 .. 30]; + V : bits(1) = [op_code[26]]; + opc : bits(2) = op_code[23 .. 22]; + imm12 : bits(12) = op_code[21 .. 10]; + Rn : bits(5) = op_code[9 .. 5]; + Rt : bits(5) = op_code[4 .. 0]; + memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode(size, V, opc, imm12, Rn, Rt) +} + +function clause decode _ : bits(3) @ 0b10001 @ _ : bits(24) as op_code = { + sf : bits(1) = [op_code[31]]; + op : bits(1) = [op_code[30]]; + S : bits(1) = [op_code[29]]; + shift : bits(2) = op_code[23 .. 22]; + imm12 : bits(12) = op_code[21 .. 10]; + Rn : bits(5) = op_code[9 .. 5]; + Rd : bits(5) = op_code[4 .. 0]; + integer_arithmetic_addsub_immediate_decode(sf, op, S, shift, imm12, Rn, Rd) +} diff --git a/aarch64/duopod/spec.sail b/aarch64/duopod/spec.sail new file mode 100644 index 00000000..f477a997 --- /dev/null +++ b/aarch64/duopod/spec.sail @@ -0,0 +1,4314 @@ +enum boolean = {FALSE, TRUE} + +enum signal = {LOW, HIGH} + +enum __RetCode = { + __RC_OK, + __RC_UNDEFINED, + __RC_UNPREDICTABLE, + __RC_SEE, + __RC_IMPLEMENTATION_DEFINED, + __RC_SUBARCHITECTURE_DEFINED, + __RC_EXCEPTION_TAKEN, + __RC_ASSERT_FAILED, + __RC_UNMATCHED_CASE +} + +type CPACRType = bits(32) + +type CNTKCTLType = bits(32) + +type ESRType = bits(32) + +type FPCRType = bits(32) + +type MAIRType = bits(64) + +type SCRType = bits(32) + +type SCTLRType = bits(32) + +enum FPConvOp = { + FPConvOp_CVT_FtoI, + FPConvOp_CVT_ItoF, + FPConvOp_MOV_FtoI, + FPConvOp_MOV_ItoF, + FPConvOp_CVT_FtoI_JS +} + +enum Exception = { + Exception_Uncategorized, + Exception_WFxTrap, + Exception_CP15RTTrap, + Exception_CP15RRTTrap, + Exception_CP14RTTrap, + Exception_CP14DTTrap, + Exception_AdvSIMDFPAccessTrap, + Exception_FPIDTrap, + Exception_PACTrap, + Exception_CP14RRTTrap, + Exception_IllegalState, + Exception_SupervisorCall, + Exception_HypervisorCall, + Exception_MonitorCall, + Exception_SystemRegisterTrap, + Exception_ERetTrap, + Exception_InstructionAbort, + Exception_PCAlignment, + Exception_DataAbort, + Exception_SPAlignment, + Exception_FPTrappedException, + Exception_SError, + Exception_Breakpoint, + Exception_SoftwareStep, + Exception_Watchpoint, + Exception_SoftwareBreakpoint, + Exception_VectorCatch, + Exception_IRQ, + Exception_FIQ +} + +enum ArchVersion = {ARMv8p0, ARMv8p1, ARMv8p2, ARMv8p3} + +enum Unpredictable = { + Unpredictable_WBOVERLAPLD, + Unpredictable_WBOVERLAPST, + Unpredictable_LDPOVERLAP, + Unpredictable_BASEOVERLAP, + Unpredictable_DATAOVERLAP, + Unpredictable_DEVPAGE2, + Unpredictable_INSTRDEVICE, + Unpredictable_RESCPACR, + Unpredictable_RESMAIR, + Unpredictable_RESTEXCB, + Unpredictable_RESPRRR, + Unpredictable_RESDACR, + Unpredictable_RESVTCRS, + Unpredictable_RESTnSZ, + Unpredictable_OORTnSZ, + Unpredictable_LARGEIPA, + Unpredictable_ESRCONDPASS, + Unpredictable_ILZEROIT, + Unpredictable_ILZEROT, + Unpredictable_BPVECTORCATCHPRI, + Unpredictable_VCMATCHHALF, + Unpredictable_VCMATCHDAPA, + Unpredictable_WPMASKANDBAS, + Unpredictable_WPBASCONTIGUOUS, + Unpredictable_RESWPMASK, + Unpredictable_WPMASKEDBITS, + Unpredictable_RESBPWPCTRL, + Unpredictable_BPNOTIMPL, + Unpredictable_RESBPTYPE, + Unpredictable_BPNOTCTXCMP, + Unpredictable_BPMATCHHALF, + Unpredictable_BPMISMATCHHALF, + Unpredictable_RESTARTALIGNPC, + Unpredictable_RESTARTZEROUPPERPC, + Unpredictable_ZEROUPPER, + Unpredictable_ERETZEROUPPERPC, + Unpredictable_A32FORCEALIGNPC, + Unpredictable_SMD, + Unpredictable_AFUPDATE, + Unpredictable_IESBinDebug, + Unpredictable_ZEROPMSEVFR, + Unpredictable_NOOPTYPES, + Unpredictable_ZEROMINLATENCY, + Unpredictable_CLEARERRITEZERO, + Unpredictable_TBD +} + +enum Constraint = { + Constraint_NONE, + Constraint_UNKNOWN, + Constraint_UNDEF, + Constraint_UNDEFEL0, + Constraint_NOP, + Constraint_TRUE, + Constraint_FALSE, + Constraint_DISABLED, + Constraint_UNCOND, + Constraint_COND, + Constraint_ADDITIONAL_DECODE, + Constraint_WBSUPPRESS, + Constraint_FAULT, + Constraint_FORCE, + Constraint_FORCENOSLCHECK +} + +enum InstrSet = {InstrSet_A64, InstrSet_A32, InstrSet_T32} + +struct ProcState = { + N : bits(1), + Z : bits(1), + C : bits(1), + V : bits(1), + D : bits(1), + A : bits(1), + I : bits(1), + F : bits(1), + PAN : bits(1), + UAO : bits(1), + SS : bits(1), + IL : bits(1), + EL : bits(2), + nRW : bits(1), + SP : bits(1), + Q : bits(1), + GE : bits(4), + IT : bits(8), + J : bits(1), + T : bits(1), + E : bits(1), + M : bits(5) +} + +enum BranchType = { + BranchType_CALL, + BranchType_ERET, + BranchType_DBGEXIT, + BranchType_RET, + BranchType_JMP, + BranchType_EXCEPTION, + BranchType_UNKNOWN +} + +struct ExceptionRecord = { + typ : Exception, + syndrome : bits(25), + vaddress : bits(64), + ipavalid : bool, + ipaddress : bits(52) +} + +enum Fault = { + Fault_None, + Fault_AccessFlag, + Fault_Alignment, + Fault_Background, + Fault_Domain, + Fault_Permission, + Fault_Translation, + Fault_AddressSize, + Fault_SyncExternal, + Fault_SyncExternalOnWalk, + Fault_SyncParity, + Fault_SyncParityOnWalk, + Fault_AsyncParity, + Fault_AsyncExternal, + Fault_Debug, + Fault_TLBConflict, + Fault_Lockdown, + Fault_Exclusive, + Fault_ICacheMaint +} + +enum AccType = { + AccType_NORMAL, + AccType_VEC, + AccType_STREAM, + AccType_VECSTREAM, + AccType_ATOMIC, + AccType_ATOMICRW, + AccType_ORDERED, + AccType_ORDEREDRW, + AccType_LIMITEDORDERED, + AccType_UNPRIV, + AccType_IFETCH, + AccType_PTW, + AccType_DC, + AccType_IC, + AccType_DCZVA, + AccType_AT +} + +struct FaultRecord = { + typ : Fault, + acctype : AccType, + ipaddress : bits(52), + s2fs1walk : bool, + write : bool, + level : int, + extflag : bits(1), + secondstage : bool, + domain : bits(4), + errortype : bits(2), + debugmoe : bits(4) +} + +enum MBReqDomain = { + MBReqDomain_Nonshareable, + MBReqDomain_InnerShareable, + MBReqDomain_OuterShareable, + MBReqDomain_FullSystem +} + +enum MBReqTypes = {MBReqTypes_Reads, MBReqTypes_Writes, MBReqTypes_All} + +enum MemType = {MemType_Normal, MemType_Device} + +enum DeviceType = { + DeviceType_GRE, + DeviceType_nGRE, + DeviceType_nGnRE, + DeviceType_nGnRnE +} + +struct MemAttrHints = {attrs : bits(2), hints : bits(2), transient : bool} + +struct MemoryAttributes = { + typ : MemType, + device : DeviceType, + inner : MemAttrHints, + outer : MemAttrHints, + shareable : bool, + outershareable : bool +} + +struct FullAddress = {physicaladdress : bits(52), NS : bits(1)} + +struct AddressDescriptor = { + fault : FaultRecord, + memattrs : MemoryAttributes, + paddress : FullAddress, + vaddress : bits(64) +} + +struct DescriptorUpdate = {AF : bool, AP : bool, descaddr : AddressDescriptor} + +enum MemAtomicOp = { + MemAtomicOp_ADD, + MemAtomicOp_BIC, + MemAtomicOp_EOR, + MemAtomicOp_ORR, + MemAtomicOp_SMAX, + MemAtomicOp_SMIN, + MemAtomicOp_UMAX, + MemAtomicOp_UMIN, + MemAtomicOp_SWP +} + +enum FPType = { + FPType_Nonzero, + FPType_Zero, + FPType_Infinity, + FPType_QNaN, + FPType_SNaN +} + +enum FPExc = { + FPExc_InvalidOp, + FPExc_DivideByZero, + FPExc_Overflow, + FPExc_Underflow, + FPExc_Inexact, + FPExc_InputDenorm +} + +enum FPRounding = { + FPRounding_TIEEVEN, + FPRounding_POSINF, + FPRounding_NEGINF, + FPRounding_ZERO, + FPRounding_TIEAWAY, + FPRounding_ODD +} + +enum SysRegAccess = { + SysRegAccess_OK, + SysRegAccess_UNDEFINED, + SysRegAccess_TrapToEL1, + SysRegAccess_TrapToEL2, + SysRegAccess_TrapToEL3 +} + +enum SRType = {SRType_LSL, SRType_LSR, SRType_ASR, SRType_ROR, SRType_RRX} + +enum ShiftType = {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR} + +enum PrefetchHint = {Prefetch_READ, Prefetch_WRITE, Prefetch_EXEC} + +enum InterruptID = { + InterruptID_PMUIRQ, + InterruptID_COMMIRQ, + InterruptID_CTIIRQ, + InterruptID_COMMRX, + InterruptID_COMMTX +} + +enum CrossTriggerOut = { + CrossTriggerOut_DebugRequest, + CrossTriggerOut_RestartRequest, + CrossTriggerOut_IRQ, + CrossTriggerOut_RSVD3, + CrossTriggerOut_TraceExtIn0, + CrossTriggerOut_TraceExtIn1, + CrossTriggerOut_TraceExtIn2, + CrossTriggerOut_TraceExtIn3 +} + +enum CrossTriggerIn = { + CrossTriggerIn_CrossHalt, + CrossTriggerIn_PMUOverflow, + CrossTriggerIn_RSVD2, + CrossTriggerIn_RSVD3, + CrossTriggerIn_TraceExtOut0, + CrossTriggerIn_TraceExtOut1, + CrossTriggerIn_TraceExtOut2, + CrossTriggerIn_TraceExtOut3 +} + +enum MemBarrierOp = {MemBarrierOp_DSB, MemBarrierOp_DMB, MemBarrierOp_ISB} + +struct AccessDescriptor = { + acctype : AccType, + page_table_walk : bool, + secondstage : bool, + s2fs1walk : bool, + level : int +} + +struct Permissions = {ap : bits(3), xn : bits(1), xxn : bits(1), pxn : bits(1)} + +struct TLBRecord = { + perms : Permissions, + nG : bits(1), + domain : bits(4), + contiguous : bool, + level : int, + blocksize : int, + descupdate : DescriptorUpdate, + CnP : bits(1), + addrdesc : AddressDescriptor +} + +enum ImmediateOp = { + ImmediateOp_MOVI, + ImmediateOp_MVNI, + ImmediateOp_ORR, + ImmediateOp_BIC +} + +enum MoveWideOp = {MoveWideOp_N, MoveWideOp_Z, MoveWideOp_K} + +enum SystemAccessType = { + SystemAccessType_RT, + SystemAccessType_RRT, + SystemAccessType_DT +} + +enum VBitOp = {VBitOp_VBIF, VBitOp_VBIT, VBitOp_VBSL, VBitOp_VEOR} + +enum TimeStamp = {TimeStamp_None, TimeStamp_Virtual, TimeStamp_Physical} + +enum PrivilegeLevel = {PL3, PL2, PL1, PL0} + +struct AArch32_SErrorSyndrome = {AET : bits(2), ExT : bits(1)} + +enum SystemOp = {Sys_AT, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS} + +struct PCSample = { + valid_name : bool, + pc : bits(64), + el : bits(2), + rw : bits(1), + ns : bits(1), + contextidr : bits(32), + contextidr_el2 : bits(32), + vmid : bits(16) +} + +enum ReduceOp = { + ReduceOp_FMINNUM, + ReduceOp_FMAXNUM, + ReduceOp_FMIN, + ReduceOp_FMAX, + ReduceOp_FADD, + ReduceOp_ADD +} + +enum LogicalOp = {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR} + +enum ExtendType = { + ExtendType_SXTB, + ExtendType_SXTH, + ExtendType_SXTW, + ExtendType_SXTX, + ExtendType_UXTB, + ExtendType_UXTH, + ExtendType_UXTW, + ExtendType_UXTX +} + +enum SystemHintOp = { + SystemHintOp_NOP, + SystemHintOp_YIELD, + SystemHintOp_WFE, + SystemHintOp_WFI, + SystemHintOp_SEV, + SystemHintOp_SEVL, + SystemHintOp_ESB, + SystemHintOp_PSB +} + +enum MemOp = {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH} + +enum OpType = { + OpType_Load, + OpType_Store, + OpType_LoadAtomic, + OpType_Branch, + OpType_Other +} + +enum FPUnaryOp = {FPUnaryOp_ABS, FPUnaryOp_MOV, FPUnaryOp_NEG, FPUnaryOp_SQRT} + +enum CompareOp = { + CompareOp_GT, + CompareOp_GE, + CompareOp_EQ, + CompareOp_LE, + CompareOp_LT +} + +enum PSTATEField = { + PSTATEField_DAIFSet, + PSTATEField_DAIFClr, + PSTATEField_PAN, + PSTATEField_UAO, + PSTATEField_SP +} + +enum FPMaxMinOp = { + FPMaxMinOp_MAX, + FPMaxMinOp_MIN, + FPMaxMinOp_MAXNUM, + FPMaxMinOp_MINNUM +} + +enum CountOp = {CountOp_CLZ, CountOp_CLS, CountOp_CNT} + +enum VFPNegMul = {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL} + +enum VBitOps = {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL} + +enum VCGEtype = {VCGEtype_signed, VCGEtype_unsigned, VCGEtype_fp} + +enum VCGTtype = {VCGTtype_signed, VCGTtype_unsigned, VCGTtype_fp} + +enum __InstrEnc = {__A64, __A32, __T16, __T32} + +val AArch64_SecondStageTranslate : (AddressDescriptor, bits(64), AccType, bool, bool, bool, int, bool) -> AddressDescriptor effect {rreg, escape, rmem, undef, wmem} + +val AArch64_CheckAndUpdateDescriptor : (DescriptorUpdate, FaultRecord, bool, bits(64), AccType, bool, bool, bool) -> FaultRecord effect {escape, rreg, rmem, wmem, undef} + +register __unconditional : bool + +val __UNKNOWN_integer : unit -> int + +function __UNKNOWN_integer () = return(0) + +register __ThisInstrEnc : __InstrEnc + +register __ThisInstr : bits(32) + +register __Memory : bits(52) + +register __BranchTaken : bool + +register _R : vector(31, dec, bits(64)) + +register _PC : bits(64) + +register VTTBR_EL2 : bits(64) + +register VTCR_EL2 : bits(32) + +register VBAR_EL3 : bits(64) + +register VBAR_EL2 : bits(64) + +register VBAR_EL1 : bits(64) + +register VBAR : bits(32) + +val ThisInstrAddr : forall ('N : Int), 'N >= 0. unit -> bits('N) effect {rreg} + +function ThisInstrAddr () = return(slice(_PC, 0, 'N)) + +val ThisInstr : unit -> bits(32) effect {rreg} + +function ThisInstr () = return(__ThisInstr) + +register TTBR1_EL2 : bits(64) + +register TTBR1_EL1 : bits(64) + +register TTBR0_EL3 : bits(64) + +register TTBR0_EL2 : bits(64) + +register TTBR0_EL1 : bits(64) + +register TCR_EL3 : bits(32) + +register TCR_EL2 : bits(64) + +register TCR_EL1 : bits(64) + +val SynchronizeContext : unit -> unit + +function SynchronizeContext () = () + +register SP_mon : bits(32) + +register SP_EL3 : bits(64) + +register SP_EL2 : bits(64) + +register SP_EL1 : bits(64) + +register SP_EL0 : bits(64) + +register SPSR_und : bits(32) + +register SPSR_svc : bits(32) + +register SPSR_mon : bits(32) + +register SPSR_irq : bits(32) + +register SPSR_hyp : bits(32) + +register SPSR_fiq : bits(32) + +register SPSR_abt : bits(32) + +register SPSR_EL3 : bits(32) + +register SPSR_EL2 : bits(32) + +register SPSR_EL1 : bits(32) + +register SPIDEN : signal + +register SCTLR_EL3 : bits(32) + +register SCTLR_EL2 : bits(32) + +register SCTLR_EL1 : bits(32) + +register SCTLR : bits(32) + +register SCR_EL3 : bits(32) + +register SCR : bits(32) + +val ProcessorID : unit -> int + +function ProcessorID () = return(0) + +val __UNKNOWN_PrefetchHint : unit -> PrefetchHint + +function __UNKNOWN_PrefetchHint () = return(Prefetch_READ) + +register PSTATE : ProcState + +register OSLSR_EL1 : bits(32) + +register OSDLR_EL1 : bits(32) + +val __UNKNOWN_MemType : unit -> MemType + +function __UNKNOWN_MemType () = return(MemType_Normal) + +val __UNKNOWN_MemOp : unit -> MemOp + +function __UNKNOWN_MemOp () = return(MemOp_LOAD) + +let MemHint_RWA : vector(2, dec, bit) = 0b11 + +let MemHint_RA : vector(2, dec, bit) = 0b10 + +let MemHint_No : vector(2, dec, bit) = 0b00 + +let MemAttr_WT : vector(2, dec, bit) = 0b10 + +let MemAttr_WB : vector(2, dec, bit) = 0b11 + +let MemAttr_NC : vector(2, dec, bit) = 0b00 + +register MDSCR_EL1 : bits(32) + +register MDCR_EL3 : bits(32) + +register MDCR_EL2 : bits(32) + +register MAIR_EL3 : bits(64) + +register MAIR_EL2 : bits(64) + +register MAIR_EL1 : bits(64) + +let M32_User : vector(5, dec, bit) = 0b10000 + +let M32_Undef : vector(5, dec, bit) = 0b11011 + +let M32_System : vector(5, dec, bit) = 0b11111 + +let M32_Svc : vector(5, dec, bit) = 0b10011 + +let M32_Monitor : vector(5, dec, bit) = 0b10110 + +let M32_IRQ : vector(5, dec, bit) = 0b10010 + +let M32_Hyp : vector(5, dec, bit) = 0b11010 + +let M32_FIQ : vector(5, dec, bit) = 0b10001 + +let M32_Abort : vector(5, dec, bit) = 0b10111 + +register LR_mon : bits(32) + +val __UNKNOWN_InstrSet : unit -> InstrSet + +function __UNKNOWN_InstrSet () = return(InstrSet_A64) + +register ID_AA64DFR0_EL1 : bits(64) + +val Hint_Prefetch : (bits(64), PrefetchHint, int, bool) -> unit + +function Hint_Prefetch (address, hint, 'target, stream) = () + +val Hint_Branch : BranchType -> unit + +function Hint_Branch hint = () + +val HaveAnyAArch32 : unit -> bool + +function HaveAnyAArch32 () = return(false) + +register HVBAR : bits(32) + +register HSR : bits(32) + +register HSCTLR : bits(32) + +register HPFAR_EL2 : bits(64) + +register HPFAR : bits(32) + +register HIFAR : bits(32) + +register HDFAR : bits(32) + +register HCR_EL2 : bits(64) + +register HCR2 : bits(32) + +register HCR : bits(32) + +val __UNKNOWN_Fault : unit -> Fault + +function __UNKNOWN_Fault () = return(Fault_None) + +register FPEXC : bits(32) + +register FAR_EL3 : bits(64) + +register FAR_EL2 : bits(64) + +register FAR_EL1 : bits(64) + +val __UNKNOWN_boolean : unit -> bool + +function __UNKNOWN_boolean () = return(false) + +val Unreachable : unit -> unit effect {escape} + +function Unreachable () = assert(false, "FALSE") + +val RBankSelect : (bits(5), int, int, int, int, int, int, int) -> int effect {escape, undef} + +function RBankSelect (mode, 'usr, 'fiq, 'irq, 'svc, 'abt, 'und, 'hyp) = { + result : int = undefined; + match mode { + ? if ? == M32_User => result = usr, + ? if ? == M32_FIQ => result = fiq, + ? if ? == M32_IRQ => result = irq, + ? if ? == M32_Svc => result = svc, + ? if ? == M32_Abort => result = abt, + ? if ? == M32_Hyp => result = hyp, + ? if ? == M32_Undef => result = und, + ? if ? == M32_System => result = usr, + _ => Unreachable() + }; + return(result) +} + +val TakeUnmaskedPhysicalSErrorInterrupts : bool -> unit effect {escape} + +function TakeUnmaskedPhysicalSErrorInterrupts iesb_req = assert(false, "FALSE") + +val StopInstructionPrefetchAndEnableITR : unit -> unit effect {escape} + +function StopInstructionPrefetchAndEnableITR () = assert(false, "FALSE") + +val __UNKNOWN_Exception : unit -> Exception + +function __UNKNOWN_Exception () = return(Exception_Uncategorized) + +val ErrorSynchronizationBarrier : (MBReqDomain, MBReqTypes) -> unit + +function ErrorSynchronizationBarrier (domain, types) = () + +val EndOfInstruction : unit -> unit + +function EndOfInstruction () = () + +register ESR_EL3 : bits(32) + +register ESR_EL2 : bits(32) + +register ESR_EL1 : bits(32) + +register ELR_hyp : bits(32) + +register ELR_EL3 : bits(64) + +register ELR_EL2 : bits(64) + +register ELR_EL1 : bits(64) + +let EL3 : vector(2, dec, bit) = 0b11 + +let EL2 : vector(2, dec, bit) = 0b10 + +let EL1 : vector(2, dec, bit) = 0b01 + +let EL0 : vector(2, dec, bit) = 0b00 + +register EDSCR : bits(32) + +val __UNKNOWN_DeviceType : unit -> DeviceType + +function __UNKNOWN_DeviceType () = return(DeviceType_GRE) + +let DebugHalt_Watchpoint : vector(6, dec, bit) = 0b101011 + +let DebugHalt_Breakpoint : vector(6, dec, bit) = 0b000111 + +let DebugException_VectorCatch : vector(4, dec, bit) = 0x5 + +register DSPSR_EL0 : bits(32) + +register DSPSR : bits(32) + +register DLR_EL0 : bits(64) + +register DLR : bits(32) + +register DBGWVR_EL1 : vector(16, dec, bits(64)) + +register DBGWCR_EL1 : vector(16, dec, bits(32)) + +register DBGPRCR_EL1 : bits(32) + +register DBGPRCR : bits(32) + +register DBGOSDLR : bits(32) + +register DBGEN : signal + +register DBGBVR_EL1 : vector(16, dec, bits(64)) + +register DBGBCR_EL1 : vector(16, dec, bits(32)) + +val __UNKNOWN_Constraint : unit -> Constraint + +function __UNKNOWN_Constraint () = return(Constraint_NONE) + +val ConstrainUnpredictable : Unpredictable -> Constraint + +function ConstrainUnpredictable which = match which { + Unpredictable_WBOVERLAPLD => return(Constraint_WBSUPPRESS), + Unpredictable_WBOVERLAPST => return(Constraint_NONE), + Unpredictable_LDPOVERLAP => return(Constraint_UNDEF), + Unpredictable_BASEOVERLAP => return(Constraint_NONE), + Unpredictable_DATAOVERLAP => return(Constraint_NONE), + Unpredictable_DEVPAGE2 => return(Constraint_FAULT), + Unpredictable_INSTRDEVICE => return(Constraint_NONE), + Unpredictable_RESCPACR => return(Constraint_UNKNOWN), + Unpredictable_RESMAIR => return(Constraint_UNKNOWN), + Unpredictable_RESTEXCB => return(Constraint_UNKNOWN), + Unpredictable_RESDACR => return(Constraint_UNKNOWN), + Unpredictable_RESPRRR => return(Constraint_UNKNOWN), + Unpredictable_RESVTCRS => return(Constraint_UNKNOWN), + Unpredictable_RESTnSZ => return(Constraint_FORCE), + Unpredictable_OORTnSZ => return(Constraint_FORCE), + Unpredictable_LARGEIPA => return(Constraint_FORCE), + Unpredictable_ESRCONDPASS => return(Constraint_FALSE), + Unpredictable_ILZEROIT => return(Constraint_FALSE), + Unpredictable_ILZEROT => return(Constraint_FALSE), + Unpredictable_BPVECTORCATCHPRI => return(Constraint_TRUE), + Unpredictable_VCMATCHHALF => return(Constraint_FALSE), + Unpredictable_VCMATCHDAPA => return(Constraint_FALSE), + Unpredictable_WPMASKANDBAS => return(Constraint_FALSE), + Unpredictable_WPBASCONTIGUOUS => return(Constraint_FALSE), + Unpredictable_RESWPMASK => return(Constraint_DISABLED), + Unpredictable_WPMASKEDBITS => return(Constraint_FALSE), + Unpredictable_RESBPWPCTRL => return(Constraint_DISABLED), + Unpredictable_BPNOTIMPL => return(Constraint_DISABLED), + Unpredictable_RESBPTYPE => return(Constraint_DISABLED), + Unpredictable_BPNOTCTXCMP => return(Constraint_DISABLED), + Unpredictable_BPMATCHHALF => return(Constraint_FALSE), + Unpredictable_BPMISMATCHHALF => return(Constraint_FALSE), + Unpredictable_RESTARTALIGNPC => return(Constraint_FALSE), + Unpredictable_RESTARTZEROUPPERPC => return(Constraint_TRUE), + Unpredictable_ZEROUPPER => return(Constraint_TRUE), + Unpredictable_ERETZEROUPPERPC => return(Constraint_TRUE), + Unpredictable_A32FORCEALIGNPC => return(Constraint_FALSE), + Unpredictable_SMD => return(Constraint_UNDEF), + Unpredictable_AFUPDATE => return(Constraint_TRUE), + Unpredictable_IESBinDebug => return(Constraint_TRUE), + Unpredictable_CLEARERRITEZERO => return(Constraint_FALSE) +} + +val ClearExclusiveByAddress : (FullAddress, int, int) -> unit + +function ClearExclusiveByAddress (paddress, 'processorid, 'size) = () + +val CTI_SignalEvent : CrossTriggerIn -> unit effect {escape} + +function CTI_SignalEvent id = assert(false, "FALSE") + +register CONTEXTIDR_EL2 : bits(32) + +register CONTEXTIDR_EL1 : bits(32) + +val __UNKNOWN_AccType : unit -> AccType + +function __UNKNOWN_AccType () = return(AccType_NORMAL) + +val CreateAccessDescriptorPTW : (AccType, bool, bool, int) -> AccessDescriptor effect {undef} + +function CreateAccessDescriptorPTW (acctype, secondstage, s2fs1walk, 'level) = { + accdesc : AccessDescriptor = undefined; + accdesc.acctype = acctype; + accdesc.page_table_walk = true; + accdesc.secondstage = s2fs1walk; + accdesc.secondstage = secondstage; + accdesc.level = level; + return(accdesc) +} + +val CreateAccessDescriptor : AccType -> AccessDescriptor effect {undef} + +function CreateAccessDescriptor acctype = { + accdesc : AccessDescriptor = undefined; + accdesc.acctype = acctype; + accdesc.page_table_walk = false; + return(accdesc) +} + +val AArch64_CreateFaultRecord : (Fault, bits(52), int, AccType, bool, bits(1), bits(2), bool, bool) -> FaultRecord effect {undef} + +function AArch64_CreateFaultRecord (typ, ipaddress, 'level, acctype, write, extflag, errortype, secondstage, s2fs1walk) = { + fault : FaultRecord = undefined; + fault.typ = typ; + fault.domain = undefined; + fault.debugmoe = undefined; + fault.errortype = errortype; + fault.ipaddress = ipaddress; + fault.level = level; + fault.acctype = acctype; + fault.write = write; + fault.extflag = extflag; + fault.secondstage = secondstage; + fault.s2fs1walk = s2fs1walk; + return(fault) +} + +val AArch64_TranslationFault : (bits(52), int, AccType, bool, bool, bool) -> FaultRecord effect {undef} + +function AArch64_TranslationFault (ipaddress, 'level, acctype, iswrite, secondstage, s2fs1walk) = { + extflag : bits(1) = undefined; + errortype : bits(2) = undefined; + return(AArch64_CreateFaultRecord(Fault_Translation, ipaddress, level, acctype, iswrite, extflag, errortype, secondstage, s2fs1walk)) +} + +val AArch64_PermissionFault : (bits(52), int, AccType, bool, bool, bool) -> FaultRecord effect {undef} + +function AArch64_PermissionFault (ipaddress, 'level, acctype, iswrite, secondstage, s2fs1walk) = { + extflag : bits(1) = undefined; + errortype : bits(2) = undefined; + return(AArch64_CreateFaultRecord(Fault_Permission, ipaddress, level, acctype, iswrite, extflag, errortype, secondstage, s2fs1walk)) +} + +val AArch64_NoFault : unit -> FaultRecord effect {undef} + +function AArch64_NoFault () = { + ipaddress : bits(52) = undefined; + level : int = undefined; + acctype : AccType = AccType_NORMAL; + iswrite : bool = undefined; + extflag : bits(1) = undefined; + errortype : bits(2) = undefined; + secondstage : bool = false; + s2fs1walk : bool = false; + return(AArch64_CreateFaultRecord(Fault_None, ipaddress, level, acctype, iswrite, extflag, errortype, secondstage, s2fs1walk)) +} + +val AArch64_DebugFault : (AccType, bool) -> FaultRecord effect {undef} + +function AArch64_DebugFault (acctype, iswrite) = { + ipaddress : bits(52) = undefined; + errortype : bits(2) = undefined; + level : int = undefined; + extflag : bits(1) = undefined; + secondstage : bool = false; + s2fs1walk : bool = false; + return(AArch64_CreateFaultRecord(Fault_Debug, ipaddress, level, acctype, iswrite, extflag, errortype, secondstage, s2fs1walk)) +} + +val AArch64_AlignmentFault : (AccType, bool, bool) -> FaultRecord effect {undef} + +function AArch64_AlignmentFault (acctype, iswrite, secondstage) = { + ipaddress : bits(52) = undefined; + level : int = undefined; + extflag : bits(1) = undefined; + errortype : bits(2) = undefined; + s2fs1walk : bool = undefined; + return(AArch64_CreateFaultRecord(Fault_Alignment, ipaddress, level, acctype, iswrite, extflag, errortype, secondstage, s2fs1walk)) +} + +val AArch64_AddressSizeFault : (bits(52), int, AccType, bool, bool, bool) -> FaultRecord effect {undef} + +function AArch64_AddressSizeFault (ipaddress, 'level, acctype, iswrite, secondstage, s2fs1walk) = { + extflag : bits(1) = undefined; + errortype : bits(2) = undefined; + return(AArch64_CreateFaultRecord(Fault_AddressSize, ipaddress, level, acctype, iswrite, extflag, errortype, secondstage, s2fs1walk)) +} + +val AArch64_AccessFlagFault : (bits(52), int, AccType, bool, bool, bool) -> FaultRecord effect {undef} + +function AArch64_AccessFlagFault (ipaddress, 'level, acctype, iswrite, secondstage, s2fs1walk) = { + extflag : bits(1) = undefined; + errortype : bits(2) = undefined; + return(AArch64_CreateFaultRecord(Fault_AccessFlag, ipaddress, level, acctype, iswrite, extflag, errortype, secondstage, s2fs1walk)) +} + +val aget_SP : forall ('width : Int), 'width >= 0. + unit -> bits('width) effect {escape, rreg} + +function aget_SP () = { + assert('width == 8 | 'width == 16 | 'width == 32 | 'width == 64, "((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))"); + if PSTATE.SP == 0b0 then return(slice(SP_EL0, 0, 'width)) else match PSTATE.EL { + ? if ? == EL0 => return(slice(SP_EL0, 0, 'width)), + ? if ? == EL1 => return(slice(SP_EL1, 0, 'width)), + ? if ? == EL2 => return(slice(SP_EL2, 0, 'width)), + ? if ? == EL3 => return(slice(SP_EL3, 0, 'width)) + } +} + +val __IMPDEF_integer : string -> int + +function __IMPDEF_integer x = { + if x == "Maximum Physical Address Size" then return(52) else if x == "Maximum Virtual Address Size" then return(56) else (); + return(0) +} + +val PAMax : unit -> int + +function PAMax () = return(__IMPDEF_integer("Maximum Physical Address Size")) + +val __IMPDEF_boolean : string -> bool + +function __IMPDEF_boolean x = { + if x == "Condition valid for trapped T32" then return(true) else if x == "Has Dot Product extension" then return(true) else if x == "Has RAS extension" then return(true) else if x == "Has SHA512 and SHA3 Crypto instructions" then return(true) else if x == "Has SM3 and SM4 Crypto instructions" then return(true) else if x == "Has basic Crypto instructions" then return(true) else if x == "Have CRC extension" then return(true) else if x == "Report I-cache maintenance fault in IFSR" then return(true) else if x == "Reserved Control Space EL0 Trapped" then return(true) else if x == "Translation fault on misprogrammed contiguous bit" then return(true) else if x == "UNDEF unallocated CP15 access at NS EL0" then return(true) else if x == "UNDEF unallocated CP15 access at NS EL0" then return(true) else (); + return(false) +} + +val ThisInstrLength : unit -> int effect {rreg} + +function ThisInstrLength () = return(if __ThisInstrEnc == __T16 then 16 else 32) + +val MemAttrDefaults : MemoryAttributes -> MemoryAttributes effect {undef} + +function MemAttrDefaults memattrs__arg = { + memattrs = memattrs__arg; + if memattrs.typ == MemType_Device then { + memattrs.inner = undefined; + memattrs.outer = undefined; + memattrs.shareable = true; + memattrs.outershareable = true + } else { + memattrs.device = undefined; + if memattrs.inner.attrs == MemAttr_NC & memattrs.outer.attrs == MemAttr_NC then { + memattrs.shareable = true; + memattrs.outershareable = true + } else () + }; + return(memattrs) +} + +val HaveEL : bits(2) -> bool + +function HaveEL el = { + if el == EL1 | el == EL0 then return(true) else (); + return(true) +} + +val HighestEL : unit -> bits(2) + +function HighestEL () = if HaveEL(EL3) then return(EL3) else if HaveEL(EL2) then return(EL2) else return(EL1) + +val Have16bitVMID : unit -> bool + +function Have16bitVMID () = return(HaveEL(EL2)) + +val HasArchVersion : ArchVersion -> bool + +function HasArchVersion version = return(version == ARMv8p0 | version == ARMv8p1 | version == ARMv8p2 | version == ARMv8p3) + +val HaveVirtHostExt : unit -> bool + +function HaveVirtHostExt () = return(HasArchVersion(ARMv8p1)) + +val HaveUAOExt : unit -> bool + +function HaveUAOExt () = return(HasArchVersion(ARMv8p2)) + +val HaveTrapLoadStoreMultipleDeviceExt : unit -> bool + +function HaveTrapLoadStoreMultipleDeviceExt () = return(HasArchVersion(ARMv8p2)) + +val HaveRASExt : unit -> bool + +function HaveRASExt () = return(HasArchVersion(ARMv8p2) | __IMPDEF_boolean("Has RAS extension")) + +val HavePrivATExt : unit -> bool + +function HavePrivATExt () = return(HasArchVersion(ARMv8p2)) + +val HavePANExt : unit -> bool + +function HavePANExt () = return(HasArchVersion(ARMv8p1)) + +val HavePACExt : unit -> bool + +function HavePACExt () = return(HasArchVersion(ARMv8p3)) + +val HaveNVExt : unit -> bool + +function HaveNVExt () = return(HasArchVersion(ARMv8p3)) + +val HaveExtendedExecuteNeverExt : unit -> bool + +function HaveExtendedExecuteNeverExt () = return(HasArchVersion(ARMv8p2)) + +val HaveDirtyBitModifierExt : unit -> bool + +function HaveDirtyBitModifierExt () = return(HasArchVersion(ARMv8p1)) + +val HaveCommonNotPrivateTransExt : unit -> bool + +function HaveCommonNotPrivateTransExt () = return(HasArchVersion(ARMv8p2)) + +val HaveAccessFlagUpdateExt : unit -> bool + +function HaveAccessFlagUpdateExt () = return(HasArchVersion(ARMv8p1)) + +val Have52BitVAExt : unit -> bool + +function Have52BitVAExt () = return(HasArchVersion(ARMv8p2)) + +val Have52BitPAExt : unit -> bool + +function Have52BitPAExt () = return(HasArchVersion(ARMv8p2)) + +val AArch64_HaveHPDExt : unit -> bool + +function AArch64_HaveHPDExt () = return(HasArchVersion(ARMv8p1)) + +val ExternalInvasiveDebugEnabled : unit -> bool effect {rreg} + +function ExternalInvasiveDebugEnabled () = return(DBGEN == HIGH) + +val ConstrainUnpredictableInteger : (int, int, Unpredictable) -> (Constraint, int) effect {undef} + +function ConstrainUnpredictableInteger (low, high, which) = { + c : Constraint = ConstrainUnpredictable(which); + if c == Constraint_UNKNOWN then return((c, low)) else return((c, undefined : int)) +} + +val ConstrainUnpredictableBool : Unpredictable -> bool effect {escape} + +function ConstrainUnpredictableBool which = { + c : Constraint = ConstrainUnpredictable(which); + assert(c == Constraint_TRUE | c == Constraint_FALSE, "((c == Constraint_TRUE) || (c == Constraint_FALSE))"); + return(c == Constraint_TRUE) +} + +val CombineS1S2Device : (DeviceType, DeviceType) -> DeviceType effect {undef} + +function CombineS1S2Device (s1device, s2device) = { + result : DeviceType = undefined; + if s2device == DeviceType_nGnRnE | s1device == DeviceType_nGnRnE then result = DeviceType_nGnRnE else if s2device == DeviceType_nGnRE | s1device == DeviceType_nGnRE then result = DeviceType_nGnRE else if s2device == DeviceType_nGRE | s1device == DeviceType_nGRE then result = DeviceType_nGRE else result = DeviceType_GRE; + return(result) +} + +val CombineS1S2AttrHints : (MemAttrHints, MemAttrHints) -> MemAttrHints effect {undef} + +function CombineS1S2AttrHints (s1desc, s2desc) = { + result : MemAttrHints = undefined; + if s2desc.attrs == 0b01 | s1desc.attrs == 0b01 then result.attrs = undefined else if s2desc.attrs == MemAttr_NC | s1desc.attrs == MemAttr_NC then result.attrs = MemAttr_NC else if s2desc.attrs == MemAttr_WT | s1desc.attrs == MemAttr_WT then result.attrs = MemAttr_WT else result.attrs = MemAttr_WB; + result.hints = s1desc.hints; + result.transient = s1desc.transient; + return(result) +} + +val AArch64_InstructionDevice : (AddressDescriptor, bits(64), bits(52), int, AccType, bool, bool, bool) -> AddressDescriptor effect {escape, undef} + +function AArch64_InstructionDevice (addrdesc__arg, vaddress, ipaddress, 'level, acctype, iswrite, secondstage, s2fs1walk) = { + addrdesc = addrdesc__arg; + c : Constraint = ConstrainUnpredictable(Unpredictable_INSTRDEVICE); + assert(c == Constraint_NONE | c == Constraint_FAULT, "((c == Constraint_NONE) || (c == Constraint_FAULT))"); + if c == Constraint_FAULT then addrdesc.fault = AArch64_PermissionFault(ipaddress, level, acctype, iswrite, secondstage, s2fs1walk) else { + __tmp_12 : MemoryAttributes = addrdesc.memattrs; + __tmp_12.typ = MemType_Normal; + addrdesc.memattrs = __tmp_12; + __tmp_13 : MemAttrHints = addrdesc.memattrs.inner; + __tmp_13.attrs = MemAttr_NC; + __tmp_14 : MemoryAttributes = addrdesc.memattrs; + __tmp_14.inner = __tmp_13; + addrdesc.memattrs = __tmp_14; + __tmp_15 : MemAttrHints = addrdesc.memattrs.inner; + __tmp_15.hints = MemHint_No; + __tmp_16 : MemoryAttributes = addrdesc.memattrs; + __tmp_16.inner = __tmp_15; + addrdesc.memattrs = __tmp_16; + __tmp_17 : MemoryAttributes = addrdesc.memattrs; + __tmp_17.outer = addrdesc.memattrs.inner; + addrdesc.memattrs = __tmp_17; + addrdesc.memattrs = MemAttrDefaults(addrdesc.memattrs) + }; + return(addrdesc) +} + +val LookUpRIndex : (int, bits(5)) -> int effect {escape, undef} + +function LookUpRIndex ('n, mode) = { + assert(n >= 0 & n <= 14, "((n >= 0) && (n <= 14))"); + result : int = undefined; + match n { + 8 => result = RBankSelect(mode, 8, 24, 8, 8, 8, 8, 8), + 9 => result = RBankSelect(mode, 9, 25, 9, 9, 9, 9, 9), + 10 => result = RBankSelect(mode, 10, 26, 10, 10, 10, 10, 10), + 11 => result = RBankSelect(mode, 11, 27, 11, 11, 11, 11, 11), + 12 => result = RBankSelect(mode, 12, 28, 12, 12, 12, 12, 12), + 13 => result = RBankSelect(mode, 13, 29, 17, 19, 21, 23, 15), + 14 => result = RBankSelect(mode, 14, 30, 16, 18, 20, 22, 14), + _ => result = n + }; + return(result) +} + +val AArch32_ExceptionClass : Exception -> (int, bits(1)) effect {escape, rreg, undef} + +function AArch32_ExceptionClass typ = { + il : bits(1) = if ThisInstrLength() == 32 then 0b1 else 0b0; + ec : int = undefined; + match typ { + Exception_Uncategorized => { + ec = 0; + il = 0b1 + }, + Exception_WFxTrap => ec = 1, + Exception_CP15RTTrap => ec = 3, + Exception_CP15RRTTrap => ec = 4, + Exception_CP14RTTrap => ec = 5, + Exception_CP14DTTrap => ec = 6, + Exception_AdvSIMDFPAccessTrap => ec = 7, + Exception_FPIDTrap => ec = 8, + Exception_CP14RRTTrap => ec = 12, + Exception_IllegalState => { + ec = 14; + il = 0b1 + }, + Exception_SupervisorCall => ec = 17, + Exception_HypervisorCall => ec = 18, + Exception_MonitorCall => ec = 19, + Exception_InstructionAbort => { + ec = 32; + il = 0b1 + }, + Exception_PCAlignment => { + ec = 34; + il = 0b1 + }, + Exception_DataAbort => ec = 36, + Exception_FPTrappedException => ec = 40, + _ => Unreachable() + }; + if (ec == 32 | ec == 36) & PSTATE.EL == EL2 then ec = ec + 1 else (); + return((ec, il)) +} + +val EncodeLDFSC : (Fault, int) -> bits(6) effect {escape, undef} + +function EncodeLDFSC (typ, 'level) = { + result : bits(6) = undefined; + match typ { + Fault_AddressSize => { + result = 0x0 @ __GetSlice_int(2, level, 0); + assert(level == 0 | level == 1 | level == 2 | level == 3, "((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))") + }, + Fault_AccessFlag => { + result = 0x2 @ __GetSlice_int(2, level, 0); + assert(level == 1 | level == 2 | level == 3, "((level == 1) || ((level == 2) || (level == 3)))") + }, + Fault_Permission => { + result = 0x3 @ __GetSlice_int(2, level, 0); + assert(level == 1 | level == 2 | level == 3, "((level == 1) || ((level == 2) || (level == 3)))") + }, + Fault_Translation => { + result = 0x1 @ __GetSlice_int(2, level, 0); + assert(level == 0 | level == 1 | level == 2 | level == 3, "((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))") + }, + Fault_SyncExternal => result = 0b010000, + Fault_SyncExternalOnWalk => { + result = 0x5 @ __GetSlice_int(2, level, 0); + assert(level == 0 | level == 1 | level == 2 | level == 3, "((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))") + }, + Fault_SyncParity => result = 0b011000, + Fault_SyncParityOnWalk => { + result = 0x7 @ __GetSlice_int(2, level, 0); + assert(level == 0 | level == 1 | level == 2 | level == 3, "((level == 0) || ((level == 1) || ((level == 2) || (level == 3))))") + }, + Fault_AsyncParity => result = 0b011001, + Fault_AsyncExternal => result = 0b010001, + Fault_Alignment => result = 0b100001, + Fault_Debug => result = 0b100010, + Fault_TLBConflict => result = 0b110000, + Fault_Lockdown => result = 0b110100, + Fault_Exclusive => result = 0b110101, + _ => Unreachable() + }; + return(result) +} + +val BigEndianReverse : forall ('width : Int), 'width >= 0 & 'width >= 0. + bits('width) -> bits('width) effect {escape} + +function BigEndianReverse value_name = { + assert('width == 8 | 'width == 16 | 'width == 32 | 'width == 64 | 'width == 128); + let 'half = 'width / 2; + assert(constraint('half * 2 = 'width)); + if 'width == 8 then return(value_name) else (); + return(BigEndianReverse(slice(value_name, 0, half)) @ BigEndianReverse(slice(value_name, half, 'width - half))) +} + +val AArch32_ReportHypEntry : ExceptionRecord -> unit effect {escape, rreg, undef, wreg} + +function AArch32_ReportHypEntry exception = { + typ : Exception = exception.typ; + il : bits(1) = undefined; + ec : int = undefined; + (ec, il) = AArch32_ExceptionClass(typ); + iss : bits(25) = exception.syndrome; + if (ec == 36 | ec == 37) & [iss[24]] == 0b0 then il = 0b1 else (); + HSR = (__GetSlice_int(6, ec, 0) @ il) @ iss; + if typ == Exception_InstructionAbort | typ == Exception_PCAlignment then { + HIFAR = slice(exception.vaddress, 0, 32); + HDFAR = undefined + } else if typ == Exception_DataAbort then { + HIFAR = undefined; + HDFAR = slice(exception.vaddress, 0, 32) + } else (); + if exception.ipavalid then HPFAR = __SetSlice_bits(32, 28, HPFAR, 4, slice(exception.ipaddress, 12, 28)) else HPFAR = __SetSlice_bits(32, 28, HPFAR, 4, undefined); + () +} + +val Replicate : forall ('M : Int) ('N : Int), 'M >= 0 & 'N >= 0. + bits('M) -> bits('N) effect {escape} + +function Replicate x = { + assert('N % 'M == 0, "((N MOD M) == 0)"); + let 'p = ex_int('N / 'M); + assert(constraint('N = 'p * 'M)); + return(replicate_bits(x, p)) +} + +val Zeros__0 : forall ('N : Int), 'N >= 0. atom('N) -> bits('N) + +val Zeros__1 : forall ('N : Int), 'N >= 0. unit -> bits('N) + +overload Zeros = {Zeros__0, Zeros__1} + +function Zeros__0 N = return(replicate_bits(0b0, 'N)) + +function Zeros__1 () = return(Zeros('N)) + +val ZeroExtend__0 : forall ('M : Int) ('N : Int), 'M >= 0 & 'N >= 0. + (bits('M), atom('N)) -> bits('N) effect {escape} + +val ZeroExtend__1 : forall ('M : Int) ('N : Int), 'M >= 0 & 'N >= 0. + bits('M) -> bits('N) effect {escape} + +overload ZeroExtend = {ZeroExtend__0, ZeroExtend__1} + +function ZeroExtend__0 (x, N) = { + assert('N >= 'M); + return(Zeros('N - 'M) @ x) +} + +function ZeroExtend__1 x = return(ZeroExtend(x, 'N)) + +val aset_SP : forall ('width : Int), 'width >= 0. + bits('width) -> unit effect {escape, rreg, wreg} + +function aset_SP value_name = { + assert('width == 32 | 'width == 64, "((width == 32) || (width == 64))"); + if PSTATE.SP == 0b0 then SP_EL0 = ZeroExtend(value_name) else match PSTATE.EL { + ? if ? == EL0 => SP_EL0 = ZeroExtend(value_name), + ? if ? == EL1 => SP_EL1 = ZeroExtend(value_name), + ? if ? == EL2 => SP_EL2 = ZeroExtend(value_name), + ? if ? == EL3 => SP_EL3 = ZeroExtend(value_name) + }; + () +} + +val LSL_C : forall ('N : Int), 'N >= 0 & 'N >= 0 & 1 >= 0. + (bits('N), int) -> (bits('N), bits(1)) effect {escape} + +function LSL_C (x, 'shift) = { + assert(shift > 0, "(shift > 0)"); + extended_x : bits('shift + 'N) = x @ Zeros(shift); + result : bits('N) = slice(extended_x, 0, 'N); + carry_out : bits(1) = [extended_x['N]]; + return((result, carry_out)) +} + +val LSL : forall ('N : Int), 'N >= 0 & 'N >= 0. + (bits('N), int) -> bits('N) effect {escape, undef} + +function LSL (x, 'shift) = { + assert(shift >= 0, "(shift >= 0)"); + __anon1 : bits(1) = undefined; + result : bits('N) = undefined; + if shift == 0 then result = x else (result, __anon1) = LSL_C(x, shift); + return(result) +} + +val LSInstructionSyndrome : unit -> bits(11) effect {escape} + +function LSInstructionSyndrome () = { + assert(false, "FALSE"); + return(Zeros(11)) +} + +val IsZero : forall ('N : Int), 'N >= 0. bits('N) -> bool + +function IsZero x = return(x == Zeros('N)) + +val AddWithCarry : forall ('N : Int), 'N >= 0 & 'N >= 0 & 1 >= 0 & 'N >= 0 & 4 >= 0. + (bits('N), bits('N), bits(1)) -> (bits('N), bits(4)) + +function AddWithCarry (x, y, carry_in) = { + unsigned_sum : int = UInt(x) + UInt(y) + UInt(carry_in); + signed_sum : int = SInt(x) + SInt(y) + UInt(carry_in); + result : bits('N) = __GetSlice_int('N, unsigned_sum, 0); + n : bits(1) = [result['N - 1]]; + z : bits(1) = if IsZero(result) then 0b1 else 0b0; + c : bits(1) = if UInt(result) == unsigned_sum then 0b0 else 0b1; + v : bits(1) = if SInt(result) == signed_sum then 0b0 else 0b1; + return((result, ((n @ z) @ c) @ v)) +} + +val GetPSRFromPSTATE : unit -> bits(32) effect {rreg, escape} + +function GetPSRFromPSTATE () = { + spsr : bits(32) = Zeros(); + spsr[31 .. 31] = PSTATE.N; + spsr[30 .. 30] = PSTATE.Z; + spsr[29 .. 29] = PSTATE.C; + spsr[28 .. 28] = PSTATE.V; + spsr[21 .. 21] = PSTATE.SS; + spsr[20 .. 20] = PSTATE.IL; + if PSTATE.nRW == 0b1 then { + spsr[27 .. 27] = PSTATE.Q; + spsr[26 .. 25] = PSTATE.IT[1 .. 0]; + spsr[19 .. 16] = PSTATE.GE; + spsr[15 .. 10] = PSTATE.IT[7 .. 2]; + spsr[9 .. 9] = PSTATE.E; + spsr[8 .. 8] = PSTATE.A; + spsr[7 .. 7] = PSTATE.I; + spsr[6 .. 6] = PSTATE.F; + spsr[5 .. 5] = PSTATE.T; + assert([PSTATE.M[4]] == PSTATE.nRW, "(((PSTATE).M)<4> == (PSTATE).nRW)"); + spsr[4 .. 0] = PSTATE.M + } else { + spsr[9 .. 9] = PSTATE.D; + spsr[8 .. 8] = PSTATE.A; + spsr[7 .. 7] = PSTATE.I; + spsr[6 .. 6] = PSTATE.F; + spsr[4 .. 4] = PSTATE.nRW; + spsr[3 .. 2] = PSTATE.EL; + spsr[0 .. 0] = PSTATE.SP + }; + return(spsr) +} + +val ExceptionSyndrome : Exception -> ExceptionRecord effect {undef} + +function ExceptionSyndrome typ = { + r : ExceptionRecord = undefined; + r.typ = typ; + r.syndrome = Zeros(); + r.vaddress = Zeros(); + r.ipavalid = false; + r.ipaddress = Zeros(); + return(r) +} + +val ConstrainUnpredictableBits : forall ('width : Int), 'width >= 0. + Unpredictable -> (Constraint, bits('width)) effect {undef} + +function ConstrainUnpredictableBits which = { + c : Constraint = ConstrainUnpredictable(which); + if c == Constraint_UNKNOWN then return((c, Zeros('width))) else return((c, undefined : bits('width))) +} + +val SignExtend__0 : forall ('M : Int) ('N : Int), 'M >= 0 & 'N >= 0. + (bits('M), atom('N)) -> bits('N) effect {escape} + +val SignExtend__1 : forall ('M : Int) ('N : Int), 'M >= 0 & 'N >= 0. + bits('M) -> bits('N) effect {escape} + +overload SignExtend = {SignExtend__0, SignExtend__1} + +function SignExtend__0 (x, N) = { + assert('N >= 'M); + return(replicate_bits([x['M - 1]], 'N - 'M) @ x) +} + +function SignExtend__1 x = return(SignExtend(x, 'N)) + +val Ones__0 : forall ('N : Int), 'N >= 0. atom('N) -> bits('N) + +val Ones__1 : forall ('N : Int), 'N >= 0. unit -> bits('N) + +overload Ones = {Ones__0, Ones__1} + +function Ones__0 N = return(replicate_bits(0b1, 'N)) + +function Ones__1 () = return(Ones('N)) + +val IsOnes : forall ('N : Int), 'N >= 0. bits('N) -> bool + +function IsOnes x = return(x == Ones('N)) + +val ExcVectorBase : unit -> bits(32) effect {rreg} + +function ExcVectorBase () = if [SCTLR[13]] == 0b1 then return(Ones(16) @ Zeros(16)) else return(slice(VBAR, 5, 27) @ Zeros(5)) + +val Align__0 : (int, int) -> int + +val Align__1 : forall ('N : Int), 'N >= 0 & 'N >= 0. (bits('N), int) -> bits('N) + +overload Align = {Align__0, Align__1} + +function Align__0 ('x, 'y) = return(y * (x / y)) + +function Align__1 (x, 'y) = return(__GetSlice_int('N, Align(UInt(x), y), 0)) + +val aset__Mem : forall ('size : Int), 8 * 'size >= 0. + (AddressDescriptor, atom('size), AccessDescriptor, bits(8 * 'size)) -> unit effect {escape, rreg} + +function aset__Mem (desc, size, accdesc, value_name) = { + assert('size == 1 | 'size == 2 | 'size == 4 | 'size == 8 | 'size == 16, "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))"); + address : bits(52) = desc.paddress.physicaladdress; + assert(address == Align(address, 'size), "(address == Align(address, size))"); + if address == hex_slice("0x13000000", 52, 0) then if UInt(value_name) == 4 then { + print("Program exited by writing ^D to TUBE\n"); + exit(()) + } else putchar(UInt(slice(value_name, 0, 8))) else __WriteRAM(52, 'size, __Memory, address, value_name); + () +} + +val aget__Mem : forall ('size : Int), 8 * 'size >= 0. + (AddressDescriptor, atom('size), AccessDescriptor) -> bits(8 * 'size) effect {escape, rreg} + +function aget__Mem (desc, size, accdesc) = { + assert('size == 1 | 'size == 2 | 'size == 4 | 'size == 8 | 'size == 16, "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))"); + address : bits(52) = desc.paddress.physicaladdress; + assert(address == Align(address, 'size), "(address == Align(address, size))"); + return(__ReadRAM(52, 'size, __Memory, address)) +} + +val aset_X : forall ('width : Int), 'width >= 0. + (int, bits('width)) -> unit effect {wreg, escape} + +function aset_X (n, value_name) = { + assert(n >= 0 & n <= 31, "((n >= 0) && (n <= 31))"); + assert('width == 32 | 'width == 64, "((width == 32) || (width == 64))"); + if n != 31 then _R[n] = ZeroExtend(value_name, 64) + else (); + () +} + +val aset_ELR__0 : (bits(2), bits(64)) -> unit effect {wreg, escape} + +val aset_ELR__1 : bits(64) -> unit effect {wreg, rreg, escape} + +overload aset_ELR = {aset_ELR__0, aset_ELR__1} + +function aset_ELR__0 (el, value_name) = { + r : bits(64) = value_name; + match el { + ? if ? == EL1 => ELR_EL1 = r, + ? if ? == EL2 => ELR_EL2 = r, + ? if ? == EL3 => ELR_EL3 = r, + _ => Unreachable() + }; + () +} + +function aset_ELR__1 value_name = { + assert(PSTATE.EL != EL0); + aset_ELR(PSTATE.EL, value_name); + () +} + +val aget_X : forall ('width : Int), 'width >= 0. + int -> bits('width) effect {escape, rreg} + +function aget_X 'n = { + assert(n >= 0 & n <= 31, "((n >= 0) && (n <= 31))"); + assert('width == 8 | 'width == 16 | 'width == 32 | 'width == 64, "((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))"); + if n != 31 then return(slice(_R[n], 0, 'width)) else return(Zeros('width)) +} + +val Prefetch : (bits(64), bits(5)) -> unit effect {undef} + +function Prefetch (address, prfop) = { + hint : PrefetchHint = undefined; + target : int = undefined; + stream : bool = undefined; + match slice(prfop, 3, 2) { + 0b00 => hint = Prefetch_READ, + 0b01 => hint = Prefetch_EXEC, + 0b10 => hint = Prefetch_WRITE, + 0b11 => () + }; + target = UInt(slice(prfop, 1, 2)); + stream = [prfop[0]] != 0b0; + Hint_Prefetch(address, hint, target, stream); + () +} + +val IsSecondStage : FaultRecord -> bool effect {escape} + +function IsSecondStage fault = { + assert(fault.typ != Fault_None, "((fault).type != Fault_None)"); + return(fault.secondstage) +} + +val IsFault : AddressDescriptor -> bool + +function IsFault addrdesc = return(addrdesc.fault.typ != Fault_None) + +val CombineS1S2Desc : (AddressDescriptor, AddressDescriptor) -> AddressDescriptor effect {undef} + +function CombineS1S2Desc (s1desc, s2desc) = { + result : AddressDescriptor = undefined; + result.paddress = s2desc.paddress; + if IsFault(s1desc) | IsFault(s2desc) then result = if IsFault(s1desc) then s1desc else s2desc else if s2desc.memattrs.typ == MemType_Device | s1desc.memattrs.typ == MemType_Device then { + __tmp_61 : MemoryAttributes = result.memattrs; + __tmp_61.typ = MemType_Device; + result.memattrs = __tmp_61; + if s1desc.memattrs.typ == MemType_Normal then { + __tmp_62 : MemoryAttributes = result.memattrs; + __tmp_62.device = s2desc.memattrs.device; + result.memattrs = __tmp_62 + } else if s2desc.memattrs.typ == MemType_Normal then { + __tmp_63 : MemoryAttributes = result.memattrs; + __tmp_63.device = s1desc.memattrs.device; + result.memattrs = __tmp_63 + } else { + __tmp_64 : MemoryAttributes = result.memattrs; + __tmp_64.device = CombineS1S2Device(s1desc.memattrs.device, s2desc.memattrs.device); + result.memattrs = __tmp_64 + } + } else { + __tmp_65 : MemoryAttributes = result.memattrs; + __tmp_65.typ = MemType_Normal; + result.memattrs = __tmp_65; + __tmp_66 : MemoryAttributes = result.memattrs; + __tmp_66.device = undefined; + result.memattrs = __tmp_66; + __tmp_67 : MemoryAttributes = result.memattrs; + __tmp_67.inner = CombineS1S2AttrHints(s1desc.memattrs.inner, s2desc.memattrs.inner); + result.memattrs = __tmp_67; + __tmp_68 : MemoryAttributes = result.memattrs; + __tmp_68.outer = CombineS1S2AttrHints(s1desc.memattrs.outer, s2desc.memattrs.outer); + result.memattrs = __tmp_68; + __tmp_69 : MemoryAttributes = result.memattrs; + __tmp_69.shareable = s1desc.memattrs.shareable | s2desc.memattrs.shareable; + result.memattrs = __tmp_69; + __tmp_70 : MemoryAttributes = result.memattrs; + __tmp_70.outershareable = s1desc.memattrs.outershareable | s2desc.memattrs.outershareable; + result.memattrs = __tmp_70 + }; + result.memattrs = MemAttrDefaults(result.memattrs); + return(result) +} + +val IsExternalSyncAbort__0 : Fault -> bool effect {escape} + +val IsExternalSyncAbort__1 : FaultRecord -> bool effect {escape} + +overload IsExternalSyncAbort = {IsExternalSyncAbort__0, IsExternalSyncAbort__1} + +function IsExternalSyncAbort__0 typ = { + assert(typ != Fault_None); + return(typ == Fault_SyncExternal | typ == Fault_SyncParity | typ == Fault_SyncExternalOnWalk | typ == Fault_SyncParityOnWalk) +} + +function IsExternalSyncAbort__1 fault = return(IsExternalSyncAbort(fault.typ)) + +val IsExternalAbort__0 : Fault -> bool effect {escape} + +val IsExternalAbort__1 : FaultRecord -> bool effect {escape} + +overload IsExternalAbort = {IsExternalAbort__0, IsExternalAbort__1} + +function IsExternalAbort__0 typ = { + assert(typ != Fault_None); + return(typ == Fault_SyncExternal | typ == Fault_SyncParity | typ == Fault_SyncExternalOnWalk | typ == Fault_SyncParityOnWalk | typ == Fault_AsyncExternal | typ == Fault_AsyncParity) +} + +function IsExternalAbort__1 fault = return(IsExternalAbort(fault.typ)) + +val IsDebugException : FaultRecord -> bool effect {escape} + +function IsDebugException fault = { + assert(fault.typ != Fault_None, "((fault).type != Fault_None)"); + return(fault.typ == Fault_Debug) +} + +val IPAValid : FaultRecord -> bool effect {escape} + +function IPAValid fault = { + assert(fault.typ != Fault_None, "((fault).type != Fault_None)"); + if fault.s2fs1walk then return(fault.typ == Fault_AccessFlag | fault.typ == Fault_Permission | fault.typ == Fault_Translation | fault.typ == Fault_AddressSize) else if fault.secondstage then return(fault.typ == Fault_AccessFlag | fault.typ == Fault_Translation | fault.typ == Fault_AddressSize) else return(false) +} + +val aarch64_integer_arithmetic_addsub_immediate : forall ('datasize : Int). + (int, atom('datasize), bits('datasize), int, bool, bool) -> unit effect {escape, rreg, undef, wreg} + +function aarch64_integer_arithmetic_addsub_immediate ('d, datasize, imm, 'n, setflags, sub_op) = let 'dbytes = ex_int(datasize / 8) in { + assert(constraint('datasize in {8, 16, 32, 64, 128}), "datasize constraint"); + assert(constraint(8 * 'dbytes = 'datasize), "dbytes constraint"); + result : bits('datasize) = undefined; + operand1 : bits('datasize) = if n == 31 then aget_SP() else aget_X(n); + operand2 : bits('datasize) = imm; + nzcv : bits(4) = undefined; + carry_in : bits(1) = undefined; + if sub_op then { + operand2 = ~(operand2); + carry_in = 0b1 + } else carry_in = 0b0; + (result, nzcv) = AddWithCarry(operand1, operand2, carry_in); + if setflags then (PSTATE.N, PSTATE.Z, PSTATE.C, PSTATE.V) = nzcv else (); + if d == 31 & ~(setflags) then aset_SP(result) else aset_X(d, result) +} + +val HighestELUsingAArch32 : unit -> bool + +function HighestELUsingAArch32 () = { + if ~(HaveAnyAArch32()) then return(false) else (); + return(false) +} + +val aget_SCR_GEN : unit -> bits(32) effect {escape, rreg, undef} + +function aget_SCR_GEN () = { + assert(HaveEL(EL3), "HaveEL(EL3)"); + r : bits(32) = undefined; + if HighestELUsingAArch32() then r = SCR else r = SCR_EL3; + return(r) +} + +val IsSecureBelowEL3 : unit -> bool effect {escape, rreg, undef} + +function IsSecureBelowEL3 () = if HaveEL(EL3) then return([aget_SCR_GEN()[0]] == 0b0) else if HaveEL(EL2) then return(false) else return(false) + +val UsingAArch32 : unit -> bool effect {escape, rreg} + +function UsingAArch32 () = { + aarch32 : bool = PSTATE.nRW == 0b1; + if ~(HaveAnyAArch32()) then assert(~(aarch32), "!(aarch32)") else (); + if HighestELUsingAArch32() then assert(aarch32, "aarch32") else (); + return(aarch32) +} + +val aset_SPSR : bits(32) -> unit effect {escape, rreg, wreg} + +function aset_SPSR value_name = { + if UsingAArch32() then match PSTATE.M { + ? if ? == M32_FIQ => SPSR_fiq = value_name, + ? if ? == M32_IRQ => SPSR_irq = value_name, + ? if ? == M32_Svc => SPSR_svc = value_name, + ? if ? == M32_Monitor => SPSR_mon = value_name, + ? if ? == M32_Abort => SPSR_abt = value_name, + ? if ? == M32_Hyp => SPSR_hyp = value_name, + ? if ? == M32_Undef => SPSR_und = value_name, + _ => Unreachable() + } else match PSTATE.EL { + ? if ? == EL1 => SPSR_EL1 = value_name, + ? if ? == EL2 => SPSR_EL2 = value_name, + ? if ? == EL3 => SPSR_EL3 = value_name, + _ => Unreachable() + }; + () +} + +val IsSecure : unit -> bool effect {escape, rreg, undef} + +function IsSecure () = { + if (HaveEL(EL3) & ~(UsingAArch32())) & PSTATE.EL == EL3 then return(true) else if (HaveEL(EL3) & UsingAArch32()) & PSTATE.M == M32_Monitor then return(true) else (); + return(IsSecureBelowEL3()) +} + +val CurrentInstrSet : unit -> InstrSet effect {escape, rreg, undef} + +function CurrentInstrSet () = { + result : InstrSet = undefined; + if UsingAArch32() then result = if PSTATE.T == 0b0 then InstrSet_A32 else InstrSet_T32 else result = InstrSet_A64; + return(result) +} + +val AArch32_ExecutingLSMInstr : unit -> bool effect {escape, rreg, undef} + +function AArch32_ExecutingLSMInstr () = { + instr : bits(32) = ThisInstr(); + instr_set : InstrSet = CurrentInstrSet(); + assert(instr_set == InstrSet_A32 | instr_set == InstrSet_T32, "((instr_set == InstrSet_A32) || (instr_set == InstrSet_T32))"); + if instr_set == InstrSet_A32 then return(slice(instr, 28, 4) != 0xF & slice(instr, 25, 3) == 0b100) else if ThisInstrLength() == 16 then return(slice(instr, 12, 4) == 0xC) else return(slice(instr, 25, 7) == 0b1110100 & [instr[22]] == 0b0) +} + +val AArch32_ExecutingCP10or11Instr : unit -> bool effect {escape, rreg, undef} + +function AArch32_ExecutingCP10or11Instr () = { + instr : bits(32) = ThisInstr(); + instr_set : InstrSet = CurrentInstrSet(); + assert(instr_set == InstrSet_A32 | instr_set == InstrSet_T32, "((instr_set == InstrSet_A32) || (instr_set == InstrSet_T32))"); + if instr_set == InstrSet_A32 then return((slice(instr, 24, 4) == 0xE | slice(instr, 25, 3) == 0b110) & (slice(instr, 8, 4) & 0xE) == 0xA) else return(((slice(instr, 28, 4) & 0xE) == 0xE & (slice(instr, 24, 4) == 0xE | slice(instr, 25, 3) == 0b110)) & (slice(instr, 8, 4) & 0xE) == 0xA) +} + +val HaveAArch32EL : bits(2) -> bool + +function HaveAArch32EL el = { + if ~(HaveEL(el)) then return(false) else if ~(HaveAnyAArch32()) then return(false) else if HighestELUsingAArch32() then return(true) else if el == HighestEL() then return(false) else if el == EL0 then return(true) else (); + return(true) +} + +val Halted : unit -> bool effect {rreg} + +function Halted () = return(~(slice(EDSCR, 0, 6) == 0b000001 | slice(EDSCR, 0, 6) == 0b000010)) + +val ExternalSecureInvasiveDebugEnabled : unit -> bool effect {escape, rreg, undef} + +function ExternalSecureInvasiveDebugEnabled () = { + if ~(HaveEL(EL3)) & ~(IsSecure()) then return(false) else (); + return(ExternalInvasiveDebugEnabled() & SPIDEN == HIGH) +} + +val ELStateUsingAArch32K : (bits(2), bool) -> (bool, bool) effect {rreg, undef} + +function ELStateUsingAArch32K (el, secure) = { + aarch32 : bool = undefined; + known : bool = true; + aarch32_at_el1 : bool = undefined; + aarch32_below_el3 : bool = undefined; + if ~(HaveAArch32EL(el)) then aarch32 = false else if HighestELUsingAArch32() then aarch32 = true else { + aarch32_below_el3 = HaveEL(EL3) & [SCR_EL3[10]] == 0b0; + aarch32_at_el1 = aarch32_below_el3 | ((HaveEL(EL2) & ~(secure)) & [HCR_EL2[31]] == 0b0) & ~(([HCR_EL2[34]] == 0b1 & [HCR_EL2[27]] == 0b1) & HaveVirtHostExt()); + if el == EL0 & ~(aarch32_at_el1) then if PSTATE.EL == EL0 then aarch32 = PSTATE.nRW == 0b1 else known = false else aarch32 = aarch32_below_el3 & el != EL3 | aarch32_at_el1 & (el == EL1 | el == EL0) + }; + if ~(known) then aarch32 = undefined else (); + return((known, aarch32)) +} + +val ELStateUsingAArch32 : (bits(2), bool) -> bool effect {escape, rreg, undef} + +function ELStateUsingAArch32 (el, secure) = { + aarch32 : bool = undefined; + known : bool = undefined; + (known, aarch32) = ELStateUsingAArch32K(el, secure); + assert(known, "known"); + return(aarch32) +} + +val ELUsingAArch32 : bits(2) -> bool effect {escape, rreg, undef} + +function ELUsingAArch32 el = return(ELStateUsingAArch32(el, IsSecureBelowEL3())) + +val UpdateEDSCRFields : unit -> unit effect {escape, rreg, undef, wreg} + +function UpdateEDSCRFields () = { + if ~(Halted()) then { + EDSCR = __SetSlice_bits(32, 2, EDSCR, 8, 0b00); + EDSCR = __SetSlice_bits(32, 1, EDSCR, 18, undefined); + EDSCR = __SetSlice_bits(32, 4, EDSCR, 10, 0xF) + } else { + EDSCR = __SetSlice_bits(32, 2, EDSCR, 8, PSTATE.EL); + EDSCR = __SetSlice_bits(32, 1, EDSCR, 18, if IsSecure() then 0b0 else 0b1); + RW : bits(4) = undefined; + RW : bits(4) = __SetSlice_bits(4, 1, RW, 1, if ELUsingAArch32(EL1) then 0b0 else 0b1); + if PSTATE.EL != EL0 then RW = __SetSlice_bits(4, 1, RW, 0, [RW[1]]) else RW = __SetSlice_bits(4, 1, RW, 0, if UsingAArch32() then 0b0 else 0b1); + if ~(HaveEL(EL2)) | HaveEL(EL3) & [aget_SCR_GEN()[0]] == 0b0 then RW = __SetSlice_bits(4, 1, RW, 2, [RW[1]]) else RW = __SetSlice_bits(4, 1, RW, 2, if ELUsingAArch32(EL2) then 0b0 else 0b1); + if ~(HaveEL(EL3)) then RW = __SetSlice_bits(4, 1, RW, 3, [RW[2]]) else RW = __SetSlice_bits(4, 1, RW, 3, if ELUsingAArch32(EL3) then 0b0 else 0b1); + if [RW[3]] == 0b0 then RW = __SetSlice_bits(4, 3, RW, 0, undefined) else if [RW[2]] == 0b0 then RW = __SetSlice_bits(4, 2, RW, 0, undefined) else if [RW[1]] == 0b0 then RW = __SetSlice_bits(4, 1, RW, 0, undefined) else (); + EDSCR = __SetSlice_bits(32, 4, EDSCR, 10, RW) + }; + () +} + +val Halt : bits(6) -> unit effect {wreg, undef, rreg, escape} + +function Halt reason = { + CTI_SignalEvent(CrossTriggerIn_CrossHalt); + if UsingAArch32() then { + DLR = ThisInstrAddr(); + DSPSR = GetPSRFromPSTATE(); + DSPSR[21 .. 21] = PSTATE.SS + } else { + DLR_EL0 = ThisInstrAddr(); + DSPSR_EL0 = GetPSRFromPSTATE(); + DSPSR_EL0[21 .. 21] = PSTATE.SS + }; + EDSCR[24 .. 24] = 0b1; + EDSCR[28 .. 28] = 0b0; + if IsSecure() then EDSCR[16 .. 16] = 0b0 + else if HaveEL(EL3) then + EDSCR[16 .. 16] = if ExternalSecureInvasiveDebugEnabled() then 0b0 else 0b1 + else assert([EDSCR[16]] == 0b1, "((EDSCR).SDD == '1')"); + EDSCR[20 .. 20] = 0b0; + if UsingAArch32() then { + (PSTATE.SS, PSTATE.A, PSTATE.I, PSTATE.F) = undefined : bits(4); + PSTATE.IT = 0x00; + PSTATE.T = 0b1 + } else + (PSTATE.SS, PSTATE.D, PSTATE.A, PSTATE.I, PSTATE.F) = undefined : bits(5); + PSTATE.IL = 0b0; + StopInstructionPrefetchAndEnableITR(); + EDSCR[5 .. 0] = reason; + UpdateEDSCRFields(); + () +} + +val S2CacheDisabled : AccType -> bool effect {escape, rreg, undef} + +function S2CacheDisabled acctype = { + disable : bits(1) = undefined; + if ELUsingAArch32(EL2) then disable = if acctype == AccType_IFETCH then [HCR2[1]] else [HCR2[0]] else disable = if acctype == AccType_IFETCH then [HCR_EL2[33]] else [HCR_EL2[32]]; + return(disable == 0b1) +} + +val S2ConvertAttrsHints : (bits(2), AccType) -> MemAttrHints effect {escape, rreg, undef} + +function S2ConvertAttrsHints (attr, acctype) = { + assert(~(IsZero(attr)), "!(IsZero(attr))"); + result : MemAttrHints = undefined; + if S2CacheDisabled(acctype) then { + result.attrs = MemAttr_NC; + result.hints = MemHint_No + } else match attr { + 0b01 => { + result.attrs = MemAttr_NC; + result.hints = MemHint_No + }, + 0b10 => { + result.attrs = MemAttr_WT; + result.hints = MemHint_RWA + }, + 0b11 => { + result.attrs = MemAttr_WB; + result.hints = MemHint_RWA + } + }; + result.transient = false; + return(result) +} + +val S2AttrDecode : (bits(2), bits(4), AccType) -> MemoryAttributes effect {escape, rreg, undef} + +function S2AttrDecode (SH, attr, acctype) = { + memattrs : MemoryAttributes = undefined; + if slice(attr, 2, 2) == 0b00 then { + memattrs.typ = MemType_Device; + match slice(attr, 0, 2) { + 0b00 => memattrs.device = DeviceType_nGnRnE, + 0b01 => memattrs.device = DeviceType_nGnRE, + 0b10 => memattrs.device = DeviceType_nGRE, + 0b11 => memattrs.device = DeviceType_GRE + } + } else if slice(attr, 0, 2) != 0b00 then { + memattrs.typ = MemType_Normal; + memattrs.outer = S2ConvertAttrsHints(slice(attr, 2, 2), acctype); + memattrs.inner = S2ConvertAttrsHints(slice(attr, 0, 2), acctype); + memattrs.shareable = [SH[1]] == 0b1; + memattrs.outershareable = SH == 0b10 + } else memattrs = undefined; + return(MemAttrDefaults(memattrs)) +} + +val ELIsInHost : bits(2) -> bool effect {escape, rreg, undef} + +function ELIsInHost el = return((((~(IsSecureBelowEL3()) & HaveVirtHostExt()) & ~(ELUsingAArch32(EL2))) & [HCR_EL2[34]] == 0b1) & (el == EL2 | el == EL0 & [HCR_EL2[27]] == 0b1)) + +val S1TranslationRegime__0 : bits(2) -> bits(2) effect {rreg, undef, escape} + +val S1TranslationRegime__1 : unit -> bits(2) effect {rreg, undef, escape} + +overload S1TranslationRegime = {S1TranslationRegime__0, S1TranslationRegime__1} + +function S1TranslationRegime__0 el = if el != EL0 then return(el) else if (HaveEL(EL3) & ELUsingAArch32(EL3)) & [SCR[0]] == 0b0 then return(EL3) else if HaveVirtHostExt() & ELIsInHost(el) then return(EL2) else return(EL1) + +function S1TranslationRegime__1 () = return(S1TranslationRegime(PSTATE.EL)) + +val aset_FAR__0 : (bits(2), bits(64)) -> unit effect {wreg, escape} + +val aset_FAR__1 : bits(64) -> unit effect {wreg, undef, rreg, escape} + +overload aset_FAR = {aset_FAR__0, aset_FAR__1} + +function aset_FAR__0 (regime, value_name) = { + r : bits(64) = value_name; + match regime { + ? if ? == EL1 => FAR_EL1 = r, + ? if ? == EL2 => FAR_EL2 = r, + ? if ? == EL3 => FAR_EL3 = r, + _ => Unreachable() + }; + () +} + +function aset_FAR__1 value_name = { + aset_FAR(S1TranslationRegime(), value_name); + () +} + +val aset_ESR__0 : (bits(2), bits(32)) -> unit effect {wreg, escape} + +val aset_ESR__1 : bits(32) -> unit effect {wreg, rreg, undef, escape} + +overload aset_ESR = {aset_ESR__0, aset_ESR__1} + +function aset_ESR__0 (regime, value_name) = { + r : bits(32) = value_name; + match regime { + ? if ? == EL1 => ESR_EL1 = r, + ? if ? == EL2 => ESR_EL2 = r, + ? if ? == EL3 => ESR_EL3 = r, + _ => Unreachable() + }; + () +} + +function aset_ESR__1 value_name = aset_ESR(S1TranslationRegime(), value_name) + +val aget_VBAR__0 : bits(2) -> bits(64) effect {rreg, undef, escape} + +val aget_VBAR__1 : unit -> bits(64) effect {rreg, undef, escape} + +overload aget_VBAR = {aget_VBAR__0, aget_VBAR__1} + +function aget_VBAR__0 regime = { + r : bits(64) = undefined; + match regime { + ? if ? == EL1 => r = VBAR_EL1, + ? if ? == EL2 => r = VBAR_EL2, + ? if ? == EL3 => r = VBAR_EL3, + _ => Unreachable() + }; + return(r) +} + +function aget_VBAR__1 () = return(aget_VBAR(S1TranslationRegime())) + +val aget_SCTLR__0 : bits(2) -> bits(32) effect {rreg, undef, escape} + +val aget_SCTLR__1 : unit -> bits(32) effect {rreg, undef, escape} + +overload aget_SCTLR = {aget_SCTLR__0, aget_SCTLR__1} + +function aget_SCTLR__0 regime = { + r : bits(32) = undefined; + match regime { + ? if ? == EL1 => r = SCTLR_EL1, + ? if ? == EL2 => r = SCTLR_EL2, + ? if ? == EL3 => r = SCTLR_EL3, + _ => Unreachable() + }; + return(r) +} + +function aget_SCTLR__1 () = return(aget_SCTLR(S1TranslationRegime())) + +val BigEndian : unit -> bool effect {escape, rreg, undef} + +function BigEndian () = { + bigend : bool = undefined; + if UsingAArch32() then bigend = PSTATE.E != 0b0 else if PSTATE.EL == EL0 then bigend = [aget_SCTLR()[24]] != 0b0 else bigend = [aget_SCTLR()[25]] != 0b0; + return(bigend) +} + +val aget_MAIR__0 : bits(2) -> bits(64) effect {rreg, undef, escape} + +val aget_MAIR__1 : unit -> bits(64) effect {rreg, undef, escape} + +overload aget_MAIR = {aget_MAIR__0, aget_MAIR__1} + +function aget_MAIR__0 regime = { + r : bits(64) = undefined; + match regime { + ? if ? == EL1 => r = MAIR_EL1, + ? if ? == EL2 => r = MAIR_EL2, + ? if ? == EL3 => r = MAIR_EL3, + _ => Unreachable() + }; + return(r) +} + +function aget_MAIR__1 () = return(aget_MAIR(S1TranslationRegime())) + +val S1CacheDisabled : AccType -> bool effect {escape, rreg, undef} + +function S1CacheDisabled acctype = { + enable : bits(1) = undefined; + if ELUsingAArch32(S1TranslationRegime()) then if PSTATE.EL == EL2 then enable = if acctype == AccType_IFETCH then [HSCTLR[12]] else [HSCTLR[2]] else enable = if acctype == AccType_IFETCH then [SCTLR[12]] else [SCTLR[2]] else enable = if acctype == AccType_IFETCH then [aget_SCTLR()[12]] else [aget_SCTLR()[2]]; + return(enable == 0b0) +} + +val ShortConvertAttrsHints : (bits(2), AccType, bool) -> MemAttrHints effect {escape, rreg, undef} + +function ShortConvertAttrsHints (RGN, acctype, secondstage) = { + result : MemAttrHints = undefined; + if ~(secondstage) & S1CacheDisabled(acctype) | secondstage & S2CacheDisabled(acctype) then { + result.attrs = MemAttr_NC; + result.hints = MemHint_No + } else match RGN { + 0b00 => { + result.attrs = MemAttr_NC; + result.hints = MemHint_No + }, + 0b01 => { + result.attrs = MemAttr_WB; + result.hints = MemHint_RWA + }, + 0b10 => { + result.attrs = MemAttr_WT; + result.hints = MemHint_RA + }, + 0b11 => { + result.attrs = MemAttr_WB; + result.hints = MemHint_RA + } + }; + result.transient = false; + return(result) +} + +val WalkAttrDecode : (bits(2), bits(2), bits(2), bool) -> MemoryAttributes effect {escape, rreg, undef} + +function WalkAttrDecode (SH, ORGN, IRGN, secondstage) = { + memattrs : MemoryAttributes = undefined; + acctype : AccType = AccType_NORMAL; + memattrs.typ = MemType_Normal; + memattrs.inner = ShortConvertAttrsHints(IRGN, acctype, secondstage); + memattrs.outer = ShortConvertAttrsHints(ORGN, acctype, secondstage); + memattrs.shareable = [SH[1]] == 0b1; + memattrs.outershareable = SH == 0b10; + return(MemAttrDefaults(memattrs)) +} + +val LongConvertAttrsHints : (bits(4), AccType) -> MemAttrHints effect {escape, rreg, undef} + +function LongConvertAttrsHints (attrfield, acctype) = { + assert(~(IsZero(attrfield)), "!(IsZero(attrfield))"); + result : MemAttrHints = undefined; + if S1CacheDisabled(acctype) then { + result.attrs = MemAttr_NC; + result.hints = MemHint_No + } else if slice(attrfield, 2, 2) == 0b00 then { + result.attrs = MemAttr_WT; + result.hints = slice(attrfield, 0, 2); + result.transient = true + } else if slice(attrfield, 0, 4) == 0x4 then { + result.attrs = MemAttr_NC; + result.hints = MemHint_No; + result.transient = false + } else if slice(attrfield, 2, 2) == 0b01 then { + result.attrs = slice(attrfield, 0, 2); + result.hints = MemAttr_WB; + result.transient = true + } else { + result.attrs = slice(attrfield, 2, 2); + result.hints = slice(attrfield, 0, 2); + result.transient = false + }; + return(result) +} + +val AArch64_S1AttrDecode : (bits(2), bits(3), AccType) -> MemoryAttributes effect {rreg, undef, escape} + +function AArch64_S1AttrDecode (SH, attr, acctype) = let 'uattr = ex_nat(UInt(attr)) in { + memattrs : MemoryAttributes = undefined; + mair : bits(64) = aget_MAIR(); + index : atom(8 * 'uattr) = 8 * uattr; + attrfield : bits(8) = mair[7 + index .. index]; + __anon1 : Constraint = undefined; + if attrfield[7 .. 4] != 0x0 & attrfield[3 .. 0] == 0x0 | attrfield[7 .. 4] == 0x0 & (attrfield[3 .. 0] & 0x3) != 0x0 then + (__anon1, attrfield) = ConstrainUnpredictableBits(Unpredictable_RESMAIR) : (Constraint, bits(8)) + else (); + if attrfield[7 .. 4] == 0x0 then { + memattrs.typ = MemType_Device; + match attrfield[3 .. 0] { + 0x0 => memattrs.device = DeviceType_nGnRnE, + 0x4 => memattrs.device = DeviceType_nGnRE, + 0x8 => memattrs.device = DeviceType_nGRE, + 0xC => memattrs.device = DeviceType_GRE, + _ => Unreachable() + } + } else if attrfield[3 .. 0] != 0x0 then { + memattrs.typ = MemType_Normal; + memattrs.outer = LongConvertAttrsHints(attrfield[7 .. 4], acctype); + memattrs.inner = LongConvertAttrsHints(attrfield[3 .. 0], acctype); + memattrs.shareable = [SH[1]] == 0b1; + memattrs.outershareable = SH == 0b10 + } else Unreachable(); + return(MemAttrDefaults(memattrs)) +} + +val IsInHost : unit -> bool effect {escape, rreg, undef} + +function IsInHost () = return(ELIsInHost(PSTATE.EL)) + +val HasS2Translation : unit -> bool effect {escape, rreg, undef} + +function HasS2Translation () = return(((HaveEL(EL2) & ~(IsSecure())) & ~(IsInHost())) & (PSTATE.EL == EL0 | PSTATE.EL == EL1)) + +val AArch64_SecondStageWalk : (AddressDescriptor, bits(64), AccType, bool, int, bool) -> AddressDescriptor effect {escape, rmem, rreg, undef, wmem} + +function AArch64_SecondStageWalk (S1, vaddress, acctype, iswrite, 'size, hwupdatewalk) = { + assert(HasS2Translation(), "HasS2Translation()"); + s2fs1walk : bool = true; + wasaligned : bool = true; + return(AArch64_SecondStageTranslate(S1, vaddress, acctype, iswrite, wasaligned, s2fs1walk, size, hwupdatewalk)) +} + +val DoubleLockStatus : unit -> bool effect {escape, rreg, undef} + +function DoubleLockStatus () = if ELUsingAArch32(EL1) then return(([DBGOSDLR[0]] == 0b1 & [DBGPRCR[0]] == 0b0) & ~(Halted())) else return(([OSDLR_EL1[0]] == 0b1 & [DBGPRCR_EL1[0]] == 0b0) & ~(Halted())) + +val HaltingAllowed : unit -> bool effect {escape, rreg, undef} + +function HaltingAllowed () = if Halted() | DoubleLockStatus() then return(false) else if IsSecure() then return(ExternalSecureInvasiveDebugEnabled()) else return(ExternalInvasiveDebugEnabled()) + +val HaltOnBreakpointOrWatchpoint : unit -> bool effect {escape, rreg, undef} + +function HaltOnBreakpointOrWatchpoint () = return((HaltingAllowed() & [EDSCR[14]] == 0b1) & [OSLSR_EL1[1]] == 0b0) + +val BadMode : bits(5) -> bool effect {undef} + +function BadMode mode = { + valid_name : bool = undefined; + match mode { + ? if ? == M32_Monitor => valid_name = HaveAArch32EL(EL3), + ? if ? == M32_Hyp => valid_name = HaveAArch32EL(EL2), + ? if ? == M32_FIQ => valid_name = HaveAArch32EL(EL1), + ? if ? == M32_IRQ => valid_name = HaveAArch32EL(EL1), + ? if ? == M32_Svc => valid_name = HaveAArch32EL(EL1), + ? if ? == M32_Abort => valid_name = HaveAArch32EL(EL1), + ? if ? == M32_Undef => valid_name = HaveAArch32EL(EL1), + ? if ? == M32_System => valid_name = HaveAArch32EL(EL1), + ? if ? == M32_User => valid_name = HaveAArch32EL(EL0), + _ => valid_name = false + }; + return(~(valid_name)) +} + +val aset_Rmode : (int, bits(5), bits(32)) -> unit effect {wreg, rreg, undef, escape} + +function aset_Rmode (n, mode, value_name) = { + assert(n >= 0 & n <= 14, "((n >= 0) && (n <= 14))"); + if ~(IsSecure()) then assert(mode != M32_Monitor, "(mode != M32_Monitor)") else (); + assert(~(BadMode(mode)), "!(BadMode(mode))"); + if mode == M32_Monitor then + if n == 13 then SP_mon = value_name + else if n == 14 then LR_mon = value_name + else { + __tmp_1 : bits(64) = _R[n]; + __tmp_1[31 .. 0] = value_name; + _R[n] = __tmp_1 + } + else if ~(HighestELUsingAArch32()) & ConstrainUnpredictableBool(Unpredictable_ZEROUPPER) then + _R[LookUpRIndex(n, mode)] = ZeroExtend(value_name, 64) + else { + __tmp_2 : bits(64) = _R[LookUpRIndex(n, mode)]; + __tmp_2[31 .. 0] = value_name; + _R[LookUpRIndex(n, mode)] = __tmp_2 + }; + () +} + +val aset_R : (int, bits(32)) -> unit effect {escape, rreg, undef, wreg} + +function aset_R ('n, value_name) = { + aset_Rmode(n, PSTATE.M, value_name); + () +} + +val ELFromM32 : bits(5) -> (bool, bits(2)) effect {escape, rreg, undef} + +function ELFromM32 mode = { + el : bits(2) = undefined; + valid_name : bool = ~(BadMode(mode)); + match mode { + ? if ? == M32_Monitor => el = EL3, + ? if ? == M32_Hyp => { + el = EL2; + valid_name = valid_name & (~(HaveEL(EL3)) | [aget_SCR_GEN()[0]] == 0b1) + }, + ? if ? == M32_FIQ => el = if (HaveEL(EL3) & HighestELUsingAArch32()) & [SCR[0]] == 0b0 then EL3 else EL1, + ? if ? == M32_IRQ => el = if (HaveEL(EL3) & HighestELUsingAArch32()) & [SCR[0]] == 0b0 then EL3 else EL1, + ? if ? == M32_Svc => el = if (HaveEL(EL3) & HighestELUsingAArch32()) & [SCR[0]] == 0b0 then EL3 else EL1, + ? if ? == M32_Abort => el = if (HaveEL(EL3) & HighestELUsingAArch32()) & [SCR[0]] == 0b0 then EL3 else EL1, + ? if ? == M32_Undef => el = if (HaveEL(EL3) & HighestELUsingAArch32()) & [SCR[0]] == 0b0 then EL3 else EL1, + ? if ? == M32_System => el = if (HaveEL(EL3) & HighestELUsingAArch32()) & [SCR[0]] == 0b0 then EL3 else EL1, + ? if ? == M32_User => el = EL0, + _ => valid_name = false + }; + if ~(valid_name) then el = undefined else (); + return((valid_name, el)) +} + +val AArch32_WriteMode : bits(5) -> unit effect {escape, rreg, undef, wreg} + +function AArch32_WriteMode mode = { + el : bits(2) = undefined; + valid_name : bool = undefined; + (valid_name, el) = ELFromM32(mode); + assert(valid_name, "valid"); + PSTATE.M = mode; + PSTATE.EL = el; + PSTATE.nRW = 0b1; + PSTATE.SP = if mode == M32_User | mode == M32_System then 0b0 else 0b1; + () +} + +val AddrTop : (bits(64), bool, bits(2)) -> int effect {escape, rreg, undef} + +function AddrTop (address, IsInstr, el) = { + assert(HaveEL(el), "HaveEL(el)"); + regime : bits(2) = S1TranslationRegime(el); + tbid : bits(1) = undefined; + tbi : bits(1) = undefined; + if ELUsingAArch32(regime) then return(31) else match regime { + ? if ? == EL1 => { + tbi = if [address[55]] == 0b1 then [TCR_EL1[38]] else [TCR_EL1[37]]; + if HavePACExt() then tbid = if [address[55]] == 0b1 then [TCR_EL1[52]] else [TCR_EL1[51]] else () + }, + ? if ? == EL2 => if HaveVirtHostExt() & ELIsInHost(el) then { + tbi = if [address[55]] == 0b1 then [TCR_EL2[38]] else [TCR_EL2[37]]; + if HavePACExt() then tbid = if [address[55]] == 0b1 then [TCR_EL2[52]] else [TCR_EL2[51]] else () + } else { + tbi = [TCR_EL2[20]]; + if HavePACExt() then tbid = [TCR_EL2[29]] else () + }, + ? if ? == EL3 => { + tbi = [TCR_EL3[20]]; + if HavePACExt() then tbid = [TCR_EL3[29]] else () + } + }; + return(if tbi == 0b1 & ((~(HavePACExt()) | tbid == 0b0) | ~(IsInstr)) then 55 else 63) +} + +val AArch64_WatchpointByteMatch : (int, bits(64)) -> bool effect {rreg, undef, escape} + +function AArch64_WatchpointByteMatch (n, vaddress) = let 'top : {'n, true. atom('n)} = AddrTop(vaddress, false, PSTATE.EL) in { + bottom : int = if [DBGWVR_EL1[n][2]] == 0b1 then 2 else 3; + byte_select_match : bool = [DBGWCR_EL1[n][12 .. 5][UInt(vaddress[bottom - 1 .. 0])]] != 0b0; + mask : int = UInt(DBGWCR_EL1[n][28 .. 24]); + MSB : bits(8) = undefined; + LSB : bits(8) = undefined; + if mask > 0 & ~(IsOnes(DBGWCR_EL1[n][12 .. 5])) then + byte_select_match = ConstrainUnpredictableBool(Unpredictable_WPMASKANDBAS) + else { + LSB = DBGWCR_EL1[n][12 .. 5] & ~(DBGWCR_EL1[n][12 .. 5] - 1); + MSB = DBGWCR_EL1[n][12 .. 5] + LSB; + if ~(IsZero(MSB & MSB - 1)) then { + byte_select_match = ConstrainUnpredictableBool(Unpredictable_WPBASCONTIGUOUS); + bottom = 3 + } else () + }; + c : Constraint = undefined; + if mask > 0 & mask <= 2 then { + (c, mask) = ConstrainUnpredictableInteger(3, 31, Unpredictable_RESWPMASK); + assert(c == Constraint_DISABLED | c == Constraint_NONE | c == Constraint_UNKNOWN, "((c == Constraint_DISABLED) || ((c == Constraint_NONE) || (c == Constraint_UNKNOWN)))"); + match c { + Constraint_DISABLED => return(false), + Constraint_NONE => mask = 0 + } + } else (); + WVR_match : bool = undefined; + let 'mask2 : {'n, true. atom('n)} = ex_int(mask); + let 'bottom2 : {'n, true. atom('n)} = ex_int(bottom); + if mask > bottom then { + assert(constraint('mask2 >= 'bottom2 + 1)); + WVR_match = vaddress[top - mask2 + 1 - 1 + mask2 .. mask2] == DBGWVR_EL1[n][top - mask2 + 1 - 1 + mask2 .. mask2]; + if WVR_match & ~(IsZero(DBGWVR_EL1[n][mask2 - bottom2 - 1 + bottom2 .. bottom2])) then + WVR_match = ConstrainUnpredictableBool(Unpredictable_WPMASKEDBITS) + else () + } else + WVR_match = vaddress[top - bottom2 + 1 - 1 + bottom2 .. bottom2] == DBGWVR_EL1[n][top - bottom2 + 1 - 1 + bottom2 .. bottom2]; + return(WVR_match & byte_select_match) +} + +val IsZero_slice : forall 'n, 'n >= 0. + (bits('n), int, int) -> bool effect {escape} + +function IsZero_slice (xs, i, 'l) = { + assert(constraint('l >= 0)); + IsZero(slice(xs, i, l)) +} + +val IsOnes_slice : forall 'n, 'n >= 0. + (bits('n), int, int) -> bool effect {escape} + +function IsOnes_slice (xs, i, 'l) = { + assert(constraint('l >= 0)); + IsOnes(slice(xs, i, l)) +} + +val ZeroExtend_slice_append : forall 'n 'm 'o, 'n >= 0 & 'm >= 0 & 'o >= 0. + (bits('n), int, int, bits('m)) -> bits('o) effect {escape} + +function ZeroExtend_slice_append (xs, i, 'l, ys) = { + assert(constraint('l >= 0)); + ZeroExtend(slice(xs, i, l) @ ys) +} + +val AArch64_TranslationTableWalk : (bits(52), bits(64), AccType, bool, bool, bool, int) -> TLBRecord effect {escape, rreg, rmem, wmem, undef} + +function AArch64_TranslationTableWalk (ipaddress, vaddress, acctype, iswrite, secondstage, s2fs1walk, 'size) = { + if ~(secondstage) then assert(~(ELUsingAArch32(S1TranslationRegime()))) else assert(((HaveEL(EL2) & ~(IsSecure())) & ~(ELUsingAArch32(EL2))) & HasS2Translation()); + result : TLBRecord = undefined; + descaddr : AddressDescriptor = undefined; + baseregister : bits(64) = undefined; + inputaddr : bits(64) = undefined; + __tmp_18 : MemoryAttributes = descaddr.memattrs; + __tmp_18.typ = MemType_Normal; + descaddr.memattrs = __tmp_18; + startsizecheck : int = undefined; + inputsizecheck : int = undefined; + startlevel : int = undefined; + level : int = undefined; + stride : int = undefined; + firstblocklevel : int = undefined; + grainsize : int = undefined; + hierattrsdisabled : bool = undefined; + update_AP : bool = undefined; + update_AF : bool = undefined; + singlepriv : bool = undefined; + lookupsecure : bool = undefined; + reversedescriptors : bool = undefined; + disabled : bool = undefined; + basefound : bool = undefined; + ps : bits(3) = undefined; + inputsize_min : int = undefined; + c : Constraint = undefined; + inputsize_max : int = undefined; + inputsize : int = undefined; + midgrain : bool = undefined; + largegrain : bool = undefined; + top : int = undefined; + if ~(secondstage) then { + inputaddr = ZeroExtend(vaddress); + top = AddrTop(inputaddr, acctype == AccType_IFETCH, PSTATE.EL); + if PSTATE.EL == EL3 then { + largegrain = slice(TCR_EL3, 14, 2) == 0b01; + midgrain = slice(TCR_EL3, 14, 2) == 0b10; + inputsize = 64 - UInt(slice(TCR_EL3, 0, 6)); + inputsize_max = if Have52BitVAExt() & largegrain then 52 else 48; + if inputsize > inputsize_max then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_max + else () + } else (); + inputsize_min = 64 - 39; + if inputsize < inputsize_min then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_min + else () + } else (); + ps = slice(TCR_EL3, 16, 3); + basefound = (inputsize >= inputsize_min & inputsize <= inputsize_max) & IsZero_slice(inputaddr, inputsize, top - inputsize + 1); + disabled = false; + baseregister = TTBR0_EL3; + descaddr.memattrs = WalkAttrDecode(slice(TCR_EL3, 12, 2), slice(TCR_EL3, 10, 2), slice(TCR_EL3, 8, 2), secondstage); + reversedescriptors = [SCTLR_EL3[25]] == 0b1; + lookupsecure = true; + singlepriv = true; + update_AF = HaveAccessFlagUpdateExt() & [TCR_EL3[21]] == 0b1; + update_AP = (HaveDirtyBitModifierExt() & update_AF) & [TCR_EL3[22]] == 0b1; + hierattrsdisabled = AArch64_HaveHPDExt() & [TCR_EL3[24]] == 0b1 + } else if IsInHost() then { + if [inputaddr[top]] == 0b0 then { + largegrain = slice(TCR_EL2, 14, 2) == 0b01; + midgrain = slice(TCR_EL2, 14, 2) == 0b10; + inputsize = 64 - UInt(slice(TCR_EL2, 0, 6)); + inputsize_max = if Have52BitVAExt() & largegrain then 52 else 48; + if inputsize > inputsize_max then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_max + else () + } else (); + inputsize_min = 64 - 39; + if inputsize < inputsize_min then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_min + else () + } else (); + basefound = (inputsize >= inputsize_min & inputsize <= inputsize_max) & IsZero_slice(inputaddr, inputsize, top - inputsize + 1); + disabled = [TCR_EL2[7]] == 0b1; + baseregister = TTBR0_EL2; + descaddr.memattrs = WalkAttrDecode(slice(TCR_EL2, 12, 2), slice(TCR_EL2, 10, 2), slice(TCR_EL2, 8, 2), secondstage); + hierattrsdisabled = AArch64_HaveHPDExt() & [TCR_EL2[41]] == 0b1 + } else { + inputsize = 64 - UInt(slice(TCR_EL2, 16, 6)); + largegrain = slice(TCR_EL2, 30, 2) == 0b11; + midgrain = slice(TCR_EL2, 30, 2) == 0b01; + inputsize_max = if Have52BitVAExt() & largegrain then 52 else 48; + if inputsize > inputsize_max then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_max + else () + } else (); + inputsize_min = 64 - 39; + if inputsize < inputsize_min then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_min + else () + } else (); + basefound = (inputsize >= inputsize_min & inputsize <= inputsize_max) & IsOnes_slice(inputaddr, inputsize, top - inputsize + 1); + disabled = [TCR_EL2[23]] == 0b1; + baseregister = TTBR1_EL2; + descaddr.memattrs = WalkAttrDecode(slice(TCR_EL2, 28, 2), slice(TCR_EL2, 26, 2), slice(TCR_EL2, 24, 2), secondstage); + hierattrsdisabled = AArch64_HaveHPDExt() & [TCR_EL2[42]] == 0b1 + }; + ps = slice(TCR_EL2, 32, 3); + reversedescriptors = [SCTLR_EL2[25]] == 0b1; + lookupsecure = false; + singlepriv = false; + update_AF = HaveAccessFlagUpdateExt() & [TCR_EL2[39]] == 0b1; + update_AP = (HaveDirtyBitModifierExt() & update_AF) & [TCR_EL2[40]] == 0b1 + } else if PSTATE.EL == EL2 then { + inputsize = 64 - UInt(slice(TCR_EL2, 0, 6)); + largegrain = slice(TCR_EL2, 14, 2) == 0b01; + midgrain = slice(TCR_EL2, 14, 2) == 0b10; + inputsize_max = if Have52BitVAExt() & largegrain then 52 else 48; + if inputsize > inputsize_max then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_max + else () + } else (); + inputsize_min = 64 - 39; + if inputsize < inputsize_min then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_min + else () + } else (); + ps = slice(TCR_EL2, 16, 3); + basefound = (inputsize >= inputsize_min & inputsize <= inputsize_max) & IsZero_slice(inputaddr, inputsize, top - inputsize + 1); + disabled = false; + baseregister = TTBR0_EL2; + descaddr.memattrs = WalkAttrDecode(slice(TCR_EL2, 12, 2), slice(TCR_EL2, 10, 2), slice(TCR_EL2, 8, 2), secondstage); + reversedescriptors = [SCTLR_EL2[25]] == 0b1; + lookupsecure = false; + singlepriv = true; + update_AF = HaveAccessFlagUpdateExt() & [TCR_EL2[39]] == 0b1; + update_AP = (HaveDirtyBitModifierExt() & update_AF) & [TCR_EL2[40]] == 0b1; + hierattrsdisabled = AArch64_HaveHPDExt() & [TCR_EL2[24]] == 0b1 + } else { + if [inputaddr[top]] == 0b0 then { + inputsize = 64 - UInt(slice(TCR_EL1, 0, 6)); + largegrain = slice(TCR_EL1, 14, 2) == 0b01; + midgrain = slice(TCR_EL1, 14, 2) == 0b10; + inputsize_max = if Have52BitVAExt() & largegrain then 52 else 48; + if inputsize > inputsize_max then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_max + else () + } else (); + inputsize_min = 64 - 39; + if inputsize < inputsize_min then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_min + else () + } else (); + basefound = (inputsize >= inputsize_min & inputsize <= inputsize_max) & IsZero_slice(inputaddr, inputsize, top - inputsize + 1); + disabled = [TCR_EL1[7]] == 0b1; + baseregister = TTBR0_EL1; + descaddr.memattrs = WalkAttrDecode(slice(TCR_EL1, 12, 2), slice(TCR_EL1, 10, 2), slice(TCR_EL1, 8, 2), secondstage); + hierattrsdisabled = AArch64_HaveHPDExt() & [TCR_EL1[41]] == 0b1 + } else { + inputsize = 64 - UInt(slice(TCR_EL1, 16, 6)); + largegrain = slice(TCR_EL1, 30, 2) == 0b11; + midgrain = slice(TCR_EL1, 30, 2) == 0b01; + inputsize_max = if Have52BitVAExt() & largegrain then 52 else 48; + if inputsize > inputsize_max then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_max + else () + } else (); + inputsize_min = 64 - 39; + if inputsize < inputsize_min then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_min + else () + } else (); + basefound = (inputsize >= inputsize_min & inputsize <= inputsize_max) & IsOnes_slice(inputaddr, inputsize, top - inputsize + 1); + disabled = [TCR_EL1[23]] == 0b1; + baseregister = TTBR1_EL1; + descaddr.memattrs = WalkAttrDecode(slice(TCR_EL1, 28, 2), slice(TCR_EL1, 26, 2), slice(TCR_EL1, 24, 2), secondstage); + hierattrsdisabled = AArch64_HaveHPDExt() & [TCR_EL1[42]] == 0b1 + }; + ps = slice(TCR_EL1, 32, 3); + reversedescriptors = [SCTLR_EL1[25]] == 0b1; + lookupsecure = IsSecure(); + singlepriv = false; + update_AF = HaveAccessFlagUpdateExt() & [TCR_EL1[39]] == 0b1; + update_AP = (HaveDirtyBitModifierExt() & update_AF) & [TCR_EL1[40]] == 0b1 + }; + if largegrain then { + grainsize = 16; + firstblocklevel = if Have52BitPAExt() then 1 else 2 + } else if midgrain then { + grainsize = 14; + firstblocklevel = 2 + } else { + grainsize = 12; + firstblocklevel = 1 + }; + stride = grainsize - 3; + level = 4 - RoundUp(Real(inputsize - grainsize) / Real(stride)) + } else { + inputaddr = ZeroExtend(ipaddress); + inputsize = 64 - UInt(slice(VTCR_EL2, 0, 6)); + largegrain = slice(VTCR_EL2, 14, 2) == 0b01; + midgrain = slice(VTCR_EL2, 14, 2) == 0b10; + inputsize_max = if Have52BitVAExt() & largegrain then 52 else 48; + if inputsize > inputsize_max then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_max + else () + } else (); + inputsize_min = 64 - 39; + if inputsize < inputsize_min then { + c = ConstrainUnpredictable(Unpredictable_RESTnSZ); + assert(c == Constraint_FORCE | c == Constraint_FAULT); + if c == Constraint_FORCE then inputsize = inputsize_min + else () + } else (); + ps = slice(VTCR_EL2, 16, 3); + basefound = (inputsize >= inputsize_min & inputsize <= inputsize_max) & IsZero_slice(inputaddr, inputsize, negate(inputsize) + 64); + disabled = false; + baseregister = VTTBR_EL2; + descaddr.memattrs = WalkAttrDecode(slice(VTCR_EL2, 8, 2), slice(VTCR_EL2, 10, 2), slice(VTCR_EL2, 12, 2), secondstage); + reversedescriptors = [SCTLR_EL2[25]] == 0b1; + lookupsecure = false; + singlepriv = true; + update_AF = HaveAccessFlagUpdateExt() & [VTCR_EL2[21]] == 0b1; + update_AP = (HaveDirtyBitModifierExt() & update_AF) & [VTCR_EL2[22]] == 0b1; + startlevel = UInt(slice(VTCR_EL2, 6, 2)); + if largegrain then { + grainsize = 16; + level = 3 - startlevel; + firstblocklevel = if Have52BitPAExt() then 1 else 2 + } else if midgrain then { + grainsize = 14; + level = 3 - startlevel; + firstblocklevel = 2 + } else { + grainsize = 12; + level = 2 - startlevel; + firstblocklevel = 1 + }; + stride = grainsize - 3; + if largegrain then + if level == 0 | level == 1 & PAMax() <= 42 then basefound = false + else () + else if midgrain then + if level == 0 | level == 1 & PAMax() <= 40 then basefound = false + else () + else if level < 0 | level == 0 & PAMax() <= 42 then basefound = false + else (); + inputsizecheck = inputsize; + if inputsize > PAMax() & (~(ELUsingAArch32(EL1)) | inputsize > 40) then match ConstrainUnpredictable(Unpredictable_LARGEIPA) { + Constraint_FORCE => { + inputsize = PAMax(); + inputsizecheck = PAMax() + }, + Constraint_FORCENOSLCHECK => inputsize = PAMax(), + Constraint_FAULT => basefound = false, + _ => Unreachable() + } else (); + startsizecheck = inputsizecheck - ((3 - level) * stride + grainsize); + if startsizecheck < 1 | startsizecheck > stride + 4 then basefound = false + else () + }; + if ~(basefound) | disabled then { + level = 0; + __tmp_19 : AddressDescriptor = result.addrdesc; + __tmp_19.fault = AArch64_TranslationFault(ipaddress, level, acctype, iswrite, secondstage, s2fs1walk); + result.addrdesc = __tmp_19; + return(result) + } else (); + outputsize : int = undefined; + match ps { + 0b000 => outputsize = 32, + 0b001 => outputsize = 36, + 0b010 => outputsize = 40, + 0b011 => outputsize = 42, + 0b100 => outputsize = 44, + 0b101 => outputsize = 48, + 0b110 => outputsize = if Have52BitPAExt() & largegrain then 52 else 48, + _ => outputsize = 48 + }; + if outputsize > PAMax() then outputsize = PAMax() + else (); + if outputsize < 48 & ~(IsZero_slice(baseregister, outputsize, negate(outputsize) + 48)) then { + level = 0; + __tmp_20 : AddressDescriptor = result.addrdesc; + __tmp_20.fault = AArch64_AddressSizeFault(ipaddress, level, acctype, iswrite, secondstage, s2fs1walk); + result.addrdesc = __tmp_20; + return(result) + } else (); + let 'baselowerbound = (3 + inputsize - ((3 - level) * stride + grainsize)) : int; + assert(constraint(0 <= 'baselowerbound & 'baselowerbound <= 48)); + baseaddress : bits(52) = undefined; + if outputsize == 52 then let 'z = (if baselowerbound < 6 then 6 else baselowerbound) : int in { + assert(constraint(0 <= 'z & 'z <= 48)); + baseaddress = (slice(baseregister, 2, 4) @ slice(baseregister, z, negate(z) + 48)) @ Zeros(z) + } else + baseaddress = ZeroExtend(slice(baseregister, baselowerbound, negate(baselowerbound) + 48) @ Zeros(baselowerbound)); + ns_table : bits(1) = if lookupsecure then 0b0 else 0b1; + ap_table : bits(2) = 0b00; + xn_table : bits(1) = 0b0; + pxn_table : bits(1) = 0b0; + addrselecttop : int = inputsize - 1; + apply_nvnv1_effect : bool = ((HaveNVExt() & HaveEL(EL2)) & [HCR_EL2[42]] == 0b1) & [HCR_EL2[43]] == 0b1; + blocktranslate : bool = undefined; + desc : bits(64) = undefined; + accdesc : AccessDescriptor = undefined; + hwupdatewalk : bool = undefined; + descaddr2 : AddressDescriptor = undefined; + addrselectbottom : int = undefined; + repeat { + addrselectbottom = (3 - level) * stride + grainsize; + index : bits(52) = ZeroExtend_slice_append(inputaddr, addrselectbottom, addrselecttop - addrselectbottom + 1, 0b000); + __tmp_21 : FullAddress = descaddr.paddress; + __tmp_21.physicaladdress = baseaddress | index; + descaddr.paddress = __tmp_21; + __tmp_22 : FullAddress = descaddr.paddress; + __tmp_22.NS = ns_table; + descaddr.paddress = __tmp_22; + if secondstage | ~(HasS2Translation()) then descaddr2 = descaddr + else { + hwupdatewalk = false; + descaddr2 = AArch64_SecondStageWalk(descaddr, vaddress, acctype, iswrite, 8, hwupdatewalk); + if IsFault(descaddr2) then { + __tmp_23 : AddressDescriptor = result.addrdesc; + __tmp_23.fault = descaddr2.fault; + result.addrdesc = __tmp_23; + return(result) + } else () + }; + descaddr2.vaddress = ZeroExtend(vaddress); + accdesc = CreateAccessDescriptorPTW(acctype, secondstage, s2fs1walk, level); + desc = aget__Mem(descaddr2, 8, accdesc); + if reversedescriptors then desc = BigEndianReverse(desc) + else (); + if [desc[0]] == 0b0 | slice(desc, 0, 2) == 0b01 & level == 3 then { + __tmp_24 : AddressDescriptor = result.addrdesc; + __tmp_24.fault = AArch64_TranslationFault(ipaddress, level, acctype, iswrite, secondstage, s2fs1walk); + result.addrdesc = __tmp_24; + return(result) + } else (); + if slice(desc, 0, 2) == 0b01 | level == 3 then blocktranslate = true + else { + if (outputsize < 52 & largegrain) & ~(IsZero(slice(desc, 12, 4))) | outputsize < 48 & ~(IsZero_slice(desc, outputsize, negate(outputsize) + 48)) then { + __tmp_25 : AddressDescriptor = result.addrdesc; + __tmp_25.fault = AArch64_AddressSizeFault(ipaddress, level, acctype, iswrite, secondstage, s2fs1walk); + result.addrdesc = __tmp_25; + return(result) + } else (); + let 'gsz = grainsize; + assert(constraint(0 <= 'gsz & 'gsz <= 48)); + if outputsize == 52 then + baseaddress = (slice(desc, 12, 4) @ slice(desc, gsz, negate(gsz) + 48)) @ Zeros(gsz) + else + baseaddress = ZeroExtend(slice(desc, gsz, negate(gsz) + 48) @ Zeros(gsz)); + if ~(secondstage) then ns_table = ns_table | [desc[63]] + else (); + if ~(secondstage) & ~(hierattrsdisabled) then { + ap_table = __SetSlice_bits(2, 1, ap_table, 1, [ap_table[1]] | [desc[62]]); + if apply_nvnv1_effect then pxn_table = pxn_table | [desc[60]] + else xn_table = xn_table | [desc[60]]; + if ~(singlepriv) then + if ~(apply_nvnv1_effect) then { + pxn_table = pxn_table | [desc[59]]; + ap_table = __SetSlice_bits(2, 1, ap_table, 0, [ap_table[0]] | [desc[61]]) + } else () + else () + } else (); + level = level + 1; + addrselecttop = addrselectbottom - 1; + blocktranslate = false + } + } until blocktranslate; + if level < firstblocklevel then { + __tmp_26 : AddressDescriptor = result.addrdesc; + __tmp_26.fault = AArch64_TranslationFault(ipaddress, level, acctype, iswrite, secondstage, s2fs1walk); + result.addrdesc = __tmp_26; + return(result) + } else (); + contiguousbitcheck : bool = undefined; + if largegrain then contiguousbitcheck = level == 2 & inputsize < 34 + else if midgrain then contiguousbitcheck = level == 2 & inputsize < 30 + else contiguousbitcheck = level == 1 & inputsize < 34; + if contiguousbitcheck & [desc[52]] == 0b1 then + if undefined then { + __tmp_27 : AddressDescriptor = result.addrdesc; + __tmp_27.fault = AArch64_TranslationFault(ipaddress, level, acctype, iswrite, secondstage, s2fs1walk); + result.addrdesc = __tmp_27; + return(result) + } else () + else (); + if (outputsize < 52 & largegrain) & ~(IsZero(slice(desc, 12, 4))) | outputsize < 48 & ~(IsZero_slice(desc, outputsize, negate(outputsize) + 48)) then { + __tmp_28 : AddressDescriptor = result.addrdesc; + __tmp_28.fault = AArch64_AddressSizeFault(ipaddress, level, acctype, iswrite, secondstage, s2fs1walk); + result.addrdesc = __tmp_28; + return(result) + } else (); + outputaddress : bits(52) = undefined; + let 'asb = addrselectbottom; + assert(constraint(0 <= 'asb & 'asb <= 48)); + if outputsize == 52 then + outputaddress = (slice(desc, 12, 4) @ slice(desc, asb, negate(asb) + 48)) @ slice(inputaddr, 0, asb) + else + outputaddress = ZeroExtend(slice(desc, asb, negate(asb) + 48) @ slice(inputaddr, 0, asb)); + if [desc[10]] == 0b0 then + if ~(update_AF) then { + __tmp_29 : AddressDescriptor = result.addrdesc; + __tmp_29.fault = AArch64_AccessFlagFault(ipaddress, level, acctype, iswrite, secondstage, s2fs1walk); + result.addrdesc = __tmp_29; + return(result) + } else { + __tmp_30 : DescriptorUpdate = result.descupdate; + __tmp_30.AF = true; + result.descupdate = __tmp_30 + } + else (); + if update_AP & [desc[51]] == 0b1 then + if ~(secondstage) & [desc[7]] == 0b1 then { + desc = __SetSlice_bits(64, 1, desc, 7, 0b0); + __tmp_31 : DescriptorUpdate = result.descupdate; + __tmp_31.AP = true; + result.descupdate = __tmp_31 + } else if secondstage & [desc[7]] == 0b0 then { + desc = __SetSlice_bits(64, 1, desc, 7, 0b1); + __tmp_32 : DescriptorUpdate = result.descupdate; + __tmp_32.AP = true; + result.descupdate = __tmp_32 + } else () + else (); + __tmp_33 : DescriptorUpdate = result.descupdate; + __tmp_33.descaddr = descaddr; + result.descupdate = __tmp_33; + xn : bits(1) = undefined; + pxn : bits(1) = undefined; + if apply_nvnv1_effect then { + pxn = [desc[54]]; + xn = 0b0 + } else { + xn = [desc[54]]; + pxn = [desc[53]] + }; + contiguousbit : bits(1) = [desc[52]]; + nG : bits(1) = [desc[11]]; + sh : bits(2) = slice(desc, 8, 2); + ap : bits(3) = undefined; + if apply_nvnv1_effect then ap = [desc[7]] @ 0b01 + else ap = slice(desc, 6, 2) @ 0b1; + memattr : bits(4) = slice(desc, 2, 4); + result.domain = undefined; + result.level = level; + result.blocksize = 2 ^ ((3 - level) * stride + grainsize); + if ~(secondstage) then { + __tmp_34 : Permissions = result.perms; + __tmp_34.xn = xn | xn_table; + result.perms = __tmp_34; + __tmp_35 : bits(3) = result.perms.ap; + __tmp_35 = __SetSlice_bits(3, 1, __tmp_35, 2, [ap[2]] | [ap_table[1]]); + __tmp_36 : Permissions = result.perms; + __tmp_36.ap = __tmp_35; + result.perms = __tmp_36; + if ~(singlepriv) then { + __tmp_37 : bits(3) = result.perms.ap; + __tmp_37 = __SetSlice_bits(3, 1, __tmp_37, 1, [ap[1]] & ~([ap_table[0]])); + __tmp_38 : Permissions = result.perms; + __tmp_38.ap = __tmp_37; + result.perms = __tmp_38; + __tmp_39 : Permissions = result.perms; + __tmp_39.pxn = pxn | pxn_table; + result.perms = __tmp_39; + if IsSecure() then result.nG = nG | ns_table + else result.nG = nG + } else { + __tmp_40 : bits(3) = result.perms.ap; + __tmp_40 = __SetSlice_bits(3, 1, __tmp_40, 1, 0b1); + __tmp_41 : Permissions = result.perms; + __tmp_41.ap = __tmp_40; + result.perms = __tmp_41; + __tmp_42 : Permissions = result.perms; + __tmp_42.pxn = 0b0; + result.perms = __tmp_42; + result.nG = 0b0 + }; + __tmp_43 : bits(3) = result.perms.ap; + __tmp_43 = __SetSlice_bits(3, 1, __tmp_43, 0, 0b1); + __tmp_44 : Permissions = result.perms; + __tmp_44.ap = __tmp_43; + result.perms = __tmp_44; + __tmp_45 : AddressDescriptor = result.addrdesc; + __tmp_45.memattrs = AArch64_S1AttrDecode(sh, slice(memattr, 0, 3), acctype); + result.addrdesc = __tmp_45; + __tmp_46 : FullAddress = result.addrdesc.paddress; + __tmp_46.NS = [memattr[3]] | ns_table; + __tmp_47 : AddressDescriptor = result.addrdesc; + __tmp_47.paddress = __tmp_46; + result.addrdesc = __tmp_47 + } else { + __tmp_48 : bits(3) = result.perms.ap; + __tmp_48 = __SetSlice_bits(3, 2, __tmp_48, 1, slice(ap, 1, 2)); + __tmp_49 : Permissions = result.perms; + __tmp_49.ap = __tmp_48; + result.perms = __tmp_49; + __tmp_50 : bits(3) = result.perms.ap; + __tmp_50 = __SetSlice_bits(3, 1, __tmp_50, 0, 0b1); + __tmp_51 : Permissions = result.perms; + __tmp_51.ap = __tmp_50; + result.perms = __tmp_51; + __tmp_52 : Permissions = result.perms; + __tmp_52.xn = xn; + result.perms = __tmp_52; + if HaveExtendedExecuteNeverExt() then { + __tmp_53 : Permissions = result.perms; + __tmp_53.xxn = [desc[53]]; + result.perms = __tmp_53 + } else (); + __tmp_54 : Permissions = result.perms; + __tmp_54.pxn = 0b0; + result.perms = __tmp_54; + result.nG = 0b0; + __tmp_55 : AddressDescriptor = result.addrdesc; + __tmp_55.memattrs = S2AttrDecode(sh, memattr, acctype); + result.addrdesc = __tmp_55; + __tmp_56 : FullAddress = result.addrdesc.paddress; + __tmp_56.NS = 0b1; + __tmp_57 : AddressDescriptor = result.addrdesc; + __tmp_57.paddress = __tmp_56; + result.addrdesc = __tmp_57 + }; + __tmp_58 : FullAddress = result.addrdesc.paddress; + __tmp_58.physicaladdress = outputaddress; + __tmp_59 : AddressDescriptor = result.addrdesc; + __tmp_59.paddress = __tmp_58; + result.addrdesc = __tmp_59; + __tmp_60 : AddressDescriptor = result.addrdesc; + __tmp_60.fault = AArch64_NoFault(); + result.addrdesc = __tmp_60; + result.contiguous = contiguousbit == 0b1; + if HaveCommonNotPrivateTransExt() then result.CnP = [baseregister[0]] + else (); + return(result) +} + +val IsZero_slice2 : forall 'n, 'n >= 0. + (bits('n), int, int) -> bool effect {escape} + +function IsZero_slice2 (xs, i, 'l) = { + assert(constraint('l >= 0)); + IsZero(slice(xs, i, l)) +} + +val AArch64_TranslateAddressS1Off : (bits(64), AccType, bool) -> TLBRecord effect {rreg, undef, escape} + +function AArch64_TranslateAddressS1Off (vaddress, acctype, iswrite) = { + assert(~(ELUsingAArch32(S1TranslationRegime()))); + result : TLBRecord = undefined; + Top : int = AddrTop(vaddress, false, PSTATE.EL); + s2fs1walk : bool = undefined; + secondstage : bool = undefined; + ipaddress : bits(52) = undefined; + level : int = undefined; + if ~(IsZero_slice2(vaddress, PAMax(), Top + 1 - PAMax())) then { + level = 0; + ipaddress = undefined; + secondstage = false; + s2fs1walk = false; + __tmp_198 : AddressDescriptor = result.addrdesc; + __tmp_198.fault = AArch64_AddressSizeFault(ipaddress, level, acctype, iswrite, secondstage, s2fs1walk); + result.addrdesc = __tmp_198; + return(result) + } else (); + default_cacheable : bool = HasS2Translation() & [HCR_EL2[12]] == 0b1; + cacheable : bool = undefined; + if default_cacheable then { + __tmp_199 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_199.typ = MemType_Normal; + __tmp_200 : AddressDescriptor = result.addrdesc; + __tmp_200.memattrs = __tmp_199; + result.addrdesc = __tmp_200; + __tmp_201 : MemAttrHints = result.addrdesc.memattrs.inner; + __tmp_201.attrs = MemAttr_WB; + __tmp_202 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_202.inner = __tmp_201; + __tmp_203 : AddressDescriptor = result.addrdesc; + __tmp_203.memattrs = __tmp_202; + result.addrdesc = __tmp_203; + __tmp_204 : MemAttrHints = result.addrdesc.memattrs.inner; + __tmp_204.hints = MemHint_RWA; + __tmp_205 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_205.inner = __tmp_204; + __tmp_206 : AddressDescriptor = result.addrdesc; + __tmp_206.memattrs = __tmp_205; + result.addrdesc = __tmp_206; + __tmp_207 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_207.shareable = false; + __tmp_208 : AddressDescriptor = result.addrdesc; + __tmp_208.memattrs = __tmp_207; + result.addrdesc = __tmp_208; + __tmp_209 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_209.outershareable = false; + __tmp_210 : AddressDescriptor = result.addrdesc; + __tmp_210.memattrs = __tmp_209; + result.addrdesc = __tmp_210 + } else if acctype != AccType_IFETCH then { + __tmp_211 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_211.typ = MemType_Device; + __tmp_212 : AddressDescriptor = result.addrdesc; + __tmp_212.memattrs = __tmp_211; + result.addrdesc = __tmp_212; + __tmp_213 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_213.device = DeviceType_nGnRnE; + __tmp_214 : AddressDescriptor = result.addrdesc; + __tmp_214.memattrs = __tmp_213; + result.addrdesc = __tmp_214; + __tmp_215 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_215.inner = undefined; + __tmp_216 : AddressDescriptor = result.addrdesc; + __tmp_216.memattrs = __tmp_215; + result.addrdesc = __tmp_216 + } else { + cacheable = [aget_SCTLR()[12]] == 0b1; + __tmp_217 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_217.typ = MemType_Normal; + __tmp_218 : AddressDescriptor = result.addrdesc; + __tmp_218.memattrs = __tmp_217; + result.addrdesc = __tmp_218; + if cacheable then { + __tmp_219 : MemAttrHints = result.addrdesc.memattrs.inner; + __tmp_219.attrs = MemAttr_WT; + __tmp_220 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_220.inner = __tmp_219; + __tmp_221 : AddressDescriptor = result.addrdesc; + __tmp_221.memattrs = __tmp_220; + result.addrdesc = __tmp_221; + __tmp_222 : MemAttrHints = result.addrdesc.memattrs.inner; + __tmp_222.hints = MemHint_RA; + __tmp_223 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_223.inner = __tmp_222; + __tmp_224 : AddressDescriptor = result.addrdesc; + __tmp_224.memattrs = __tmp_223; + result.addrdesc = __tmp_224 + } else { + __tmp_225 : MemAttrHints = result.addrdesc.memattrs.inner; + __tmp_225.attrs = MemAttr_NC; + __tmp_226 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_226.inner = __tmp_225; + __tmp_227 : AddressDescriptor = result.addrdesc; + __tmp_227.memattrs = __tmp_226; + result.addrdesc = __tmp_227; + __tmp_228 : MemAttrHints = result.addrdesc.memattrs.inner; + __tmp_228.hints = MemHint_No; + __tmp_229 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_229.inner = __tmp_228; + __tmp_230 : AddressDescriptor = result.addrdesc; + __tmp_230.memattrs = __tmp_229; + result.addrdesc = __tmp_230 + }; + __tmp_231 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_231.shareable = true; + __tmp_232 : AddressDescriptor = result.addrdesc; + __tmp_232.memattrs = __tmp_231; + result.addrdesc = __tmp_232; + __tmp_233 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_233.outershareable = true; + __tmp_234 : AddressDescriptor = result.addrdesc; + __tmp_234.memattrs = __tmp_233; + result.addrdesc = __tmp_234 + }; + __tmp_235 : MemoryAttributes = result.addrdesc.memattrs; + __tmp_235.outer = result.addrdesc.memattrs.inner; + __tmp_236 : AddressDescriptor = result.addrdesc; + __tmp_236.memattrs = __tmp_235; + result.addrdesc = __tmp_236; + __tmp_237 : AddressDescriptor = result.addrdesc; + __tmp_237.memattrs = MemAttrDefaults(result.addrdesc.memattrs); + result.addrdesc = __tmp_237; + __tmp_238 : Permissions = result.perms; + __tmp_238.ap = undefined; + result.perms = __tmp_238; + __tmp_239 : Permissions = result.perms; + __tmp_239.xn = 0b0; + result.perms = __tmp_239; + __tmp_240 : Permissions = result.perms; + __tmp_240.pxn = 0b0; + result.perms = __tmp_240; + result.nG = undefined; + result.contiguous = undefined; + result.domain = undefined; + result.level = undefined; + result.blocksize = undefined; + __tmp_241 : FullAddress = result.addrdesc.paddress; + __tmp_241.physicaladdress = slice(vaddress, 0, 52); + __tmp_242 : AddressDescriptor = result.addrdesc; + __tmp_242.paddress = __tmp_241; + result.addrdesc = __tmp_242; + __tmp_243 : FullAddress = result.addrdesc.paddress; + __tmp_243.NS = if IsSecure() then 0b0 else 0b1; + __tmp_244 : AddressDescriptor = result.addrdesc; + __tmp_244.paddress = __tmp_243; + result.addrdesc = __tmp_244; + __tmp_245 : AddressDescriptor = result.addrdesc; + __tmp_245.fault = AArch64_NoFault(); + result.addrdesc = __tmp_245; + return(result) +} + +val AArch64_MaybeZeroRegisterUppers : unit -> unit effect {wreg, undef, rreg, escape} + +function AArch64_MaybeZeroRegisterUppers () = { + assert(UsingAArch32(), "UsingAArch32()"); + include_R15_name : bool = undefined; + last : range(14, 30) = undefined; + first : atom(0) = 0; + if PSTATE.EL == EL0 & ~(ELUsingAArch32(EL1)) then { + first = 0; + last = 14; + include_R15_name = false + } else if (((PSTATE.EL == EL0 | PSTATE.EL == EL1) & HaveEL(EL2)) & ~(IsSecure())) & ~(ELUsingAArch32(EL2)) then { + first = 0; + last = 30; + include_R15_name = false + } else { + first = 0; + last = 30; + include_R15_name = true + }; + foreach (n from first to last by 1 in inc) + if (n : int != 15 : int | include_R15_name) & ConstrainUnpredictableBool(Unpredictable_ZEROUPPER) then { + __tmp_3 : bits(64) = _R[n]; + __tmp_3[63 .. 32] = Zeros(32); + _R[n] = __tmp_3 + } else (); + () +} + +val AArch64_GenerateDebugExceptionsFrom : (bits(2), bool, bits(1)) -> bool effect {escape, rreg, undef} + +function AArch64_GenerateDebugExceptionsFrom (from, secure, mask) = { + if ([OSLSR_EL1[1]] == 0b1 | DoubleLockStatus()) | Halted() then return(false) else (); + route_to_el2 : bool = (HaveEL(EL2) & ~(secure)) & ([HCR_EL2[27]] == 0b1 | [MDCR_EL2[8]] == 0b1); + target : bits(2) = if route_to_el2 then EL2 else EL1; + enabled : bool = (~(HaveEL(EL3)) | ~(secure)) | [MDCR_EL3[16]] == 0b0; + if from == target then enabled = (enabled & [MDSCR_EL1[13]] == 0b1) & mask == 0b0 else enabled = enabled & UInt(target) > UInt(from); + return(enabled) +} + +val AArch64_GenerateDebugExceptions : unit -> bool effect {escape, rreg, undef} + +function AArch64_GenerateDebugExceptions () = return(AArch64_GenerateDebugExceptionsFrom(PSTATE.EL, IsSecure(), PSTATE.D)) + +val AArch64_FaultSyndrome : (bool, FaultRecord) -> bits(25) effect {escape, undef} + +function AArch64_FaultSyndrome (d_side, fault) = { + assert(fault.typ != Fault_None, "((fault).type != Fault_None)"); + iss : bits(25) = Zeros(); + if HaveRASExt() & IsExternalSyncAbort(fault) then iss = __SetSlice_bits(25, 2, iss, 11, fault.errortype) else (); + if d_side then { + if IsSecondStage(fault) & ~(fault.s2fs1walk) then iss = __SetSlice_bits(25, 11, iss, 14, LSInstructionSyndrome()) else (); + if fault.acctype == AccType_DC | fault.acctype == AccType_IC | fault.acctype == AccType_AT then { + iss = __SetSlice_bits(25, 1, iss, 8, 0b1); + iss = __SetSlice_bits(25, 1, iss, 6, 0b1) + } else iss = __SetSlice_bits(25, 1, iss, 6, if fault.write then 0b1 else 0b0) + } else (); + if IsExternalAbort(fault) then iss = __SetSlice_bits(25, 1, iss, 9, fault.extflag) else (); + iss = __SetSlice_bits(25, 1, iss, 7, if fault.s2fs1walk then 0b1 else 0b0); + iss = __SetSlice_bits(25, 6, iss, 0, EncodeLDFSC(fault.typ, fault.level)); + return(iss) +} + +val AArch64_AbortSyndrome : (Exception, FaultRecord, bits(64)) -> ExceptionRecord effect {escape, undef} + +function AArch64_AbortSyndrome (typ, fault, vaddress) = { + exception : ExceptionRecord = ExceptionSyndrome(typ); + d_side : bool = typ == Exception_DataAbort | typ == Exception_Watchpoint; + exception.syndrome = AArch64_FaultSyndrome(d_side, fault); + exception.vaddress = ZeroExtend(vaddress); + if IPAValid(fault) then { + exception.ipavalid = true; + exception.ipaddress = fault.ipaddress + } else exception.ipavalid = false; + return(exception) +} + +val AArch64_ExecutingATS1xPInstr : unit -> bool effect {rreg, undef} + +function AArch64_ExecutingATS1xPInstr () = { + if ~(HavePrivATExt()) then return(false) else (); + instr : bits(32) = ThisInstr(); + op2 : bits(3) = undefined; + CRm : bits(4) = undefined; + CRn : bits(4) = undefined; + op1 : bits(3) = undefined; + if slice(instr, 22, 10) == 0b1101010100 then { + op1 = slice(instr, 16, 3); + CRn = slice(instr, 12, 4); + CRm = slice(instr, 8, 4); + op2 = slice(instr, 5, 3); + return(((op1 == 0b000 & CRn == 0x7) & CRm == 0x9) & (op2 == 0b000 | op2 == 0b001)) + } else return(false) +} + +val AArch64_ExceptionClass : (Exception, bits(2)) -> (int, bits(1)) effect {escape, rreg, undef} + +function AArch64_ExceptionClass (typ, target_el) = { + il : bits(1) = if ThisInstrLength() == 32 then 0b1 else 0b0; + from_32 : bool = UsingAArch32(); + assert(from_32 | il == 0b1, "(from_32 || (il == '1'))"); + ec : int = undefined; + match typ { + Exception_Uncategorized => { + ec = 0; + il = 0b1 + }, + Exception_WFxTrap => ec = 1, + Exception_CP15RTTrap => { + ec = 3; + assert(from_32, "from_32") + }, + Exception_CP15RRTTrap => { + ec = 4; + assert(from_32, "from_32") + }, + Exception_CP14RTTrap => { + ec = 5; + assert(from_32, "from_32") + }, + Exception_CP14DTTrap => { + ec = 6; + assert(from_32, "from_32") + }, + Exception_AdvSIMDFPAccessTrap => ec = 7, + Exception_FPIDTrap => ec = 8, + Exception_CP14RRTTrap => { + ec = 12; + assert(from_32, "from_32") + }, + Exception_IllegalState => { + ec = 14; + il = 0b1 + }, + Exception_SupervisorCall => ec = 17, + Exception_HypervisorCall => ec = 18, + Exception_MonitorCall => ec = 19, + Exception_SystemRegisterTrap => { + ec = 24; + assert(~(from_32), "!(from_32)") + }, + Exception_InstructionAbort => { + ec = 32; + il = 0b1 + }, + Exception_PCAlignment => { + ec = 34; + il = 0b1 + }, + Exception_DataAbort => ec = 36, + Exception_SPAlignment => { + ec = 38; + il = 0b1; + assert(~(from_32), "!(from_32)") + }, + Exception_FPTrappedException => ec = 40, + Exception_SError => { + ec = 47; + il = 0b1 + }, + Exception_Breakpoint => { + ec = 48; + il = 0b1 + }, + Exception_SoftwareStep => { + ec = 50; + il = 0b1 + }, + Exception_Watchpoint => { + ec = 52; + il = 0b1 + }, + Exception_SoftwareBreakpoint => ec = 56, + Exception_VectorCatch => { + ec = 58; + il = 0b1; + assert(from_32, "from_32") + }, + _ => Unreachable() + }; + if (ec == 32 | ec == 36 | ec == 48 | ec == 50 | ec == 52) & target_el == PSTATE.EL then ec = ec + 1 else (); + if (ec == 17 | ec == 18 | ec == 19 | ec == 40 | ec == 56) & ~(from_32) then ec = ec + 4 else (); + return((ec, il)) +} + +val AArch64_ReportException : (ExceptionRecord, bits(2)) -> unit effect {escape, rreg, undef, wreg} + +function AArch64_ReportException (exception, target_el) = { + typ : Exception = exception.typ; + il : bits(1) = undefined; + ec : int = undefined; + (ec, il) = AArch64_ExceptionClass(typ, target_el); + iss : bits(25) = exception.syndrome; + if (ec == 36 | ec == 37) & [iss[24]] == 0b0 then il = 0b1 else (); + aset_ESR(target_el, (__GetSlice_int(6, ec, 0) @ il) @ iss); + if typ == Exception_InstructionAbort | typ == Exception_PCAlignment | typ == Exception_DataAbort | typ == Exception_Watchpoint then aset_FAR(target_el, exception.vaddress) else aset_FAR(target_el, undefined); + if target_el == EL2 then if exception.ipavalid then HPFAR_EL2 = __SetSlice_bits(64, 40, HPFAR_EL2, 4, slice(exception.ipaddress, 12, 40)) else HPFAR_EL2 = __SetSlice_bits(64, 40, HPFAR_EL2, 4, undefined) else (); + () +} + +val AArch64_CheckS2Permission : (Permissions, bits(64), bits(52), int, AccType, bool, bool, bool) -> FaultRecord effect {escape, rreg, undef} + +function AArch64_CheckS2Permission (perms, vaddress, ipaddress, 'level, acctype, iswrite, s2fs1walk, hwupdatewalk) = { + assert(((HaveEL(EL2) & ~(IsSecure())) & ~(ELUsingAArch32(EL2))) & HasS2Translation(), "(((HaveEL(EL2) && !(IsSecure())) && !(ELUsingAArch32(EL2))) && HasS2Translation())"); + r : bool = [perms.ap[1]] == 0b1; + w : bool = [perms.ap[2]] == 0b1; + xn : bool = undefined; + if HaveExtendedExecuteNeverExt() then match perms.xn @ perms.xxn { + 0b00 => xn = false, + 0b01 => xn = PSTATE.EL == EL1, + 0b10 => xn = true, + 0b11 => xn = PSTATE.EL == EL0 + } else xn = perms.xn == 0b1; + failedread : bool = undefined; + fail : bool = undefined; + if acctype == AccType_IFETCH & ~(s2fs1walk) then { + fail = xn; + failedread = true + } else if (acctype == AccType_ATOMICRW | acctype == AccType_ORDEREDRW) & ~(s2fs1walk) then { + fail = ~(r) | ~(w); + failedread = ~(r) + } else if iswrite & ~(s2fs1walk) then { + fail = ~(w); + failedread = false + } else if hwupdatewalk then { + fail = ~(w); + failedread = ~(iswrite) + } else { + fail = ~(r); + failedread = ~(iswrite) + }; + secondstage : bool = undefined; + domain : bits(4) = undefined; + if fail then { + domain = undefined; + secondstage = true; + return(AArch64_PermissionFault(ipaddress, level, acctype, ~(failedread), secondstage, s2fs1walk)) + } else return(AArch64_NoFault()) +} + +function AArch64_SecondStageTranslate (S1, vaddress, acctype, iswrite, wasaligned, s2fs1walk, 'size, hwupdatewalk) = { + assert(HasS2Translation(), "HasS2Translation()"); + s2_enabled : bool = [HCR_EL2[0]] == 0b1 | [HCR_EL2[12]] == 0b1; + secondstage : bool = true; + result : AddressDescriptor = undefined; + S2 : TLBRecord = undefined; + ipaddress : bits(52) = undefined; + if s2_enabled then { + ipaddress = slice(S1.paddress.physicaladdress, 0, 52); + S2 = AArch64_TranslationTableWalk(ipaddress, vaddress, acctype, iswrite, secondstage, s2fs1walk, size); + if ((~(wasaligned) & acctype != AccType_IFETCH | acctype == AccType_DCZVA) & S2.addrdesc.memattrs.typ == MemType_Device) & ~(IsFault(S2.addrdesc)) then { + __tmp_71 : AddressDescriptor = S2.addrdesc; + __tmp_71.fault = AArch64_AlignmentFault(acctype, iswrite, secondstage); + S2.addrdesc = __tmp_71 + } else (); + if ~(IsFault(S2.addrdesc)) then { + __tmp_72 : AddressDescriptor = S2.addrdesc; + __tmp_72.fault = AArch64_CheckS2Permission(S2.perms, vaddress, ipaddress, S2.level, acctype, iswrite, s2fs1walk, hwupdatewalk); + S2.addrdesc = __tmp_72 + } else (); + if ((~(s2fs1walk) & ~(IsFault(S2.addrdesc))) & S2.addrdesc.memattrs.typ == MemType_Device) & acctype == AccType_IFETCH then S2.addrdesc = AArch64_InstructionDevice(S2.addrdesc, vaddress, ipaddress, S2.level, acctype, iswrite, secondstage, s2fs1walk) else (); + if ((s2fs1walk & ~(IsFault(S2.addrdesc))) & [HCR_EL2[2]] == 0b1) & S2.addrdesc.memattrs.typ == MemType_Device then { + __tmp_73 : AddressDescriptor = S2.addrdesc; + __tmp_73.fault = AArch64_PermissionFault(ipaddress, S2.level, acctype, iswrite, secondstage, s2fs1walk); + S2.addrdesc = __tmp_73 + } else (); + __tmp_74 : AddressDescriptor = S2.addrdesc; + __tmp_74.fault = AArch64_CheckAndUpdateDescriptor(S2.descupdate, S2.addrdesc.fault, secondstage, vaddress, acctype, iswrite, s2fs1walk, hwupdatewalk); + S2.addrdesc = __tmp_74; + result = CombineS1S2Desc(S1, S2.addrdesc) + } else result = S1; + return(result) +} + +function AArch64_CheckAndUpdateDescriptor (result, fault, secondstage, vaddress, acctype, iswrite, s2fs1walk, hwupdatewalk__arg) = { + hwupdatewalk = hwupdatewalk__arg; + hw_update_AF : bool = undefined; + if result.AF then if fault.typ == Fault_None then hw_update_AF = true else if ConstrainUnpredictable(Unpredictable_AFUPDATE) == Constraint_TRUE then hw_update_AF = true else hw_update_AF = false else (); + hw_update_AP : bool = undefined; + write_perm_req : bool = undefined; + if result.AP & fault.typ == Fault_None then { + write_perm_req = (iswrite | acctype == AccType_ATOMICRW | acctype == AccType_ORDEREDRW) & ~(s2fs1walk); + hw_update_AP = write_perm_req & ~(acctype == AccType_AT | acctype == AccType_DC) | hwupdatewalk + } else hw_update_AP = false; + desc : bits(64) = undefined; + accdesc : AccessDescriptor = undefined; + descaddr2 : AddressDescriptor = undefined; + if hw_update_AF | hw_update_AP then { + if secondstage | ~(HasS2Translation()) then descaddr2 = result.descaddr else { + hwupdatewalk = true; + descaddr2 = AArch64_SecondStageWalk(result.descaddr, vaddress, acctype, iswrite, 8, hwupdatewalk); + if IsFault(descaddr2) then return(descaddr2.fault) else () + }; + accdesc = CreateAccessDescriptor(AccType_ATOMICRW); + desc = aget__Mem(descaddr2, 8, accdesc); + if hw_update_AF then desc = __SetSlice_bits(64, 1, desc, 10, 0b1) else (); + if hw_update_AP then desc = __SetSlice_bits(64, 1, desc, 7, if secondstage then 0b1 else 0b0) else (); + aset__Mem(descaddr2, 8, accdesc, desc) + } else (); + return(fault) +} + +val AArch64_BreakpointValueMatch : (int, bits(64), bool) -> bool + +function AArch64_BreakpointValueMatch (n__arg, vaddress, linked_to) = false + +val AArch64_StateMatch : (bits(2), bits(1), bits(2), bool, bits(4), bool, bool) -> bool effect {rreg, undef, escape} + +function AArch64_StateMatch (SSC__arg, HMC__arg, PxC__arg, linked__arg, LBN, isbreakpnt, ispriv) = { + HMC = HMC__arg; + PxC = PxC__arg; + SSC = SSC__arg; + linked = linked__arg; + c : Constraint = undefined; + if (((((((HMC @ SSC) @ PxC) & 0b11100) == 0b01100 | (((HMC @ SSC) @ PxC) & 0b11101) == 0b10000 | (((HMC @ SSC) @ PxC) & 0b11101) == 0b10100 | ((HMC @ SSC) @ PxC) == 0b11010 | ((HMC @ SSC) @ PxC) == 0b11101 | (((HMC @ SSC) @ PxC) & 0b11110) == 0b11110) | (HMC == 0b0 & PxC == 0b00) & (~(isbreakpnt) | ~(HaveAArch32EL(EL1)))) | (SSC == 0b01 | SSC == 0b10) & ~(HaveEL(EL3))) | (((HMC @ SSC) != 0b000 & (HMC @ SSC) != 0b111) & ~(HaveEL(EL3))) & ~(HaveEL(EL2))) | ((HMC @ SSC) @ PxC) == 0b11100 & ~(HaveEL(EL2)) then { + __tmp_5 : bits(5) = undefined; + (c, __tmp_5) = ConstrainUnpredictableBits(Unpredictable_RESBPWPCTRL) : (Constraint, bits(5)); + __tmp_6 : bits(5) = __tmp_5; + HMC = [__tmp_6[4]]; + __tmp_7 : bits(4) = slice(__tmp_6, 0, 4); + SSC = slice(__tmp_7, 2, 2); + PxC = slice(__tmp_7, 0, 2); + assert(c == Constraint_DISABLED | c == Constraint_UNKNOWN, "((c == Constraint_DISABLED) || (c == Constraint_UNKNOWN))"); + if c == Constraint_DISABLED then return(false) else () + } else (); + EL3_match : bool = (HaveEL(EL3) & HMC == 0b1) & [SSC[0]] == 0b0; + EL2_match : bool = HaveEL(EL2) & HMC == 0b1; + EL1_match : bool = [PxC[0]] == 0b1; + EL0_match : bool = [PxC[1]] == 0b1; + priv_match : bool = undefined; + if ~(ispriv) & ~(isbreakpnt) then priv_match = EL0_match + else match PSTATE.EL { + EL3 => priv_match = EL3_match, + EL2 => priv_match = EL2_match, + EL1 => priv_match = EL1_match, + EL0 => priv_match = EL0_match + }; + security_state_match : bool = undefined; + match SSC { + 0b00 => security_state_match = true, + 0b01 => security_state_match = ~(IsSecure()), + 0b10 => security_state_match = IsSecure(), + 0b11 => security_state_match = true + }; + last_ctx_cmp : int = undefined; + first_ctx_cmp : int = undefined; + lbn : int = undefined; + if linked then { + lbn = UInt(LBN); + first_ctx_cmp = UInt(slice(ID_AA64DFR0_EL1, 12, 4)) - UInt(slice(ID_AA64DFR0_EL1, 28, 4)); + last_ctx_cmp = UInt(slice(ID_AA64DFR0_EL1, 12, 4)); + if lbn < first_ctx_cmp | lbn > last_ctx_cmp then { + (c, lbn) = ConstrainUnpredictableInteger(first_ctx_cmp, last_ctx_cmp, Unpredictable_BPNOTCTXCMP); + assert(c == Constraint_DISABLED | c == Constraint_NONE | c == Constraint_UNKNOWN, "((c == Constraint_DISABLED) || ((c == Constraint_NONE) || (c == Constraint_UNKNOWN)))"); + match c { + Constraint_DISABLED => return(false), + Constraint_NONE => linked = false + } + } else () + } else (); + linked_match : bool = undefined; + linked_to : bool = undefined; + vaddress : bits(64) = undefined; + if linked then { + vaddress = undefined; + linked_to = true; + linked_match = AArch64_BreakpointValueMatch(lbn, vaddress, linked_to) + } else (); + return((priv_match & security_state_match) & (~(linked) | linked_match)) +} + +val AArch64_WatchpointMatch : (int, bits(64), int, bool, bool) -> bool + +function AArch64_WatchpointMatch (n, vaddress, size, ispriv, iswrite) = false + +val AArch64_BreakpointMatch : (int, bits(64), int) -> bool effect {escape, rreg, undef} + +function AArch64_BreakpointMatch ('n, vaddress, 'size) = { + assert(~(ELUsingAArch32(S1TranslationRegime())), "!(ELUsingAArch32(S1TranslationRegime()))"); + assert(n <= UInt(slice(ID_AA64DFR0_EL1, 12, 4)), "(n <= UInt((ID_AA64DFR0_EL1).BRPs))"); + enabled : bool = [DBGBCR_EL1[n][0]] == 0b1; + ispriv : bool = PSTATE.EL != EL0; + linked : bool = (slice(DBGBCR_EL1[n], 20, 4) & 0xB) == 0x1; + isbreakpnt : bool = true; + linked_to : bool = false; + state_match : bool = AArch64_StateMatch(slice(DBGBCR_EL1[n], 14, 2), [DBGBCR_EL1[n][13]], slice(DBGBCR_EL1[n], 1, 2), linked, slice(DBGBCR_EL1[n], 16, 4), isbreakpnt, ispriv); + value_match_name : bool = AArch64_BreakpointValueMatch(n, vaddress, linked_to); + match_i : bool = undefined; + if HaveAnyAArch32() & size == 4 then { + match_i = AArch64_BreakpointValueMatch(n, vaddress + 2, linked_to); + if ~(value_match_name) & match_i then value_match_name = ConstrainUnpredictableBool(Unpredictable_BPMATCHHALF) else () + } else (); + if [vaddress[1]] == 0b1 & slice(DBGBCR_EL1[n], 5, 4) == 0xF then if value_match_name then value_match_name = ConstrainUnpredictableBool(Unpredictable_BPMATCHHALF) else () else (); + val_match : bool = (value_match_name & state_match) & enabled; + return(val_match) +} + +val AArch64_CheckBreakpoint : (bits(64), int) -> FaultRecord effect {wreg, rreg, undef, escape} + +function AArch64_CheckBreakpoint (vaddress, size) = { + assert(~(ELUsingAArch32(S1TranslationRegime())), "!(ELUsingAArch32(S1TranslationRegime()))"); + assert(UsingAArch32() & (size == 2 | size == 4) | size == 4, "((UsingAArch32() && ((size == 2) || (size == 4))) || (size == 4))"); + val_match : bool = false; + match_i : bool = undefined; + foreach (i from 0 to UInt(slice(ID_AA64DFR0_EL1, 12, 4)) by 1 in inc) { + match_i = AArch64_BreakpointMatch(i, vaddress, size); + val_match = val_match | match_i + }; + iswrite : bool = undefined; + acctype : AccType = undefined; + reason : bits(6) = undefined; + if val_match & HaltOnBreakpointOrWatchpoint() then { + reason = DebugHalt_Breakpoint; + Halt(reason); + undefined : FaultRecord + } else if (val_match & [MDSCR_EL1[15]] == 0b1) & AArch64_GenerateDebugExceptions() then { + acctype = AccType_IFETCH; + iswrite = false; + return(AArch64_DebugFault(acctype, iswrite)) + } else return(AArch64_NoFault()) +} + +val AArch64_BranchAddr : bits(64) -> bits(64) effect {rreg, undef, escape} + +function AArch64_BranchAddr vaddress = { + assert(~(UsingAArch32()), "!(UsingAArch32())"); + msbit : nat = coerce_int_nat(AddrTop(vaddress, true, PSTATE.EL)); + if msbit == 63 then return(vaddress) else if ((PSTATE.EL == EL0 | PSTATE.EL == EL1) | IsInHost()) & [vaddress[msbit]] == 0b1 then return(SignExtend(slice(vaddress, 0, msbit + 1))) else return(ZeroExtend(slice(vaddress, 0, msbit + 1))) +} + +val BranchTo : forall ('N : Int), 'N >= 0. + (bits('N), BranchType) -> unit effect {escape, rreg, undef, wreg} + +function BranchTo (target, branch_type) = { + __BranchTaken = true; + Hint_Branch(branch_type); + if 'N == 32 then { + assert(UsingAArch32(), "UsingAArch32()"); + _PC = ZeroExtend(target) + } else { + assert('N == 64 & ~(UsingAArch32()), "((N == 64) && !(UsingAArch32()))"); + _PC = AArch64_BranchAddr(slice(target, 0, 64)) + }; + () +} + +val AArch64_TakeException : (bits(2), ExceptionRecord, bits(64), int) -> unit effect {escape, rreg, undef, wreg} + +function AArch64_TakeException (target_el, exception, preferred_exception_return, vect_offset__arg) = { + vect_offset = vect_offset__arg; + SynchronizeContext(); + assert((HaveEL(target_el) & ~(ELUsingAArch32(target_el))) & UInt(target_el) >= UInt(PSTATE.EL), "((HaveEL(target_el) && !(ELUsingAArch32(target_el))) && (UInt(target_el) >= UInt((PSTATE).EL)))"); + from_32 : bool = UsingAArch32(); + if from_32 then AArch64_MaybeZeroRegisterUppers() else (); + if UInt(target_el) > UInt(PSTATE.EL) then { + lower_32 : bool = undefined; + if target_el == EL3 then if ~(IsSecure()) & HaveEL(EL2) then lower_32 = ELUsingAArch32(EL2) else lower_32 = ELUsingAArch32(EL1) else if (IsInHost() & PSTATE.EL == EL0) & target_el == EL2 then lower_32 = ELUsingAArch32(EL0) else lower_32 = ELUsingAArch32(target_el - 1); + vect_offset = vect_offset + (if lower_32 then 1536 else 1024) + } else if PSTATE.SP == 0b1 then vect_offset = vect_offset + 512 else (); + spsr : bits(32) = GetPSRFromPSTATE(); + if HaveUAOExt() then PSTATE.UAO = 0b0 else (); + if ~(exception.typ == Exception_IRQ | exception.typ == Exception_FIQ) then AArch64_ReportException(exception, target_el) else (); + PSTATE.EL = target_el; + PSTATE.nRW = 0b0; + PSTATE.SP = 0b1; + aset_SPSR(spsr); + aset_ELR(preferred_exception_return); + PSTATE.SS = 0b0; + (PSTATE.D, PSTATE.A, PSTATE.I, PSTATE.F) = 0xF; + PSTATE.IL = 0b0; + if from_32 then { + PSTATE.IT = 0x00; + PSTATE.T = 0b0 + } else (); + if (HavePANExt() & (PSTATE.EL == EL1 | PSTATE.EL == EL2 & ELIsInHost(EL0))) & [aget_SCTLR()[23]] == 0b0 then PSTATE.PAN = 0b1 else (); + BranchTo(slice(aget_VBAR(), 11, 53) @ __GetSlice_int(11, vect_offset, 0), BranchType_EXCEPTION); + iesb_req : bool = undefined; + if HaveRASExt() & [aget_SCTLR()[21]] == 0b1 then { + ErrorSynchronizationBarrier(MBReqDomain_FullSystem, MBReqTypes_All); + iesb_req = true; + TakeUnmaskedPhysicalSErrorInterrupts(iesb_req) + } else (); + EndOfInstruction() +} + +val AArch64_WatchpointException : (bits(64), FaultRecord) -> unit effect {escape, rreg, undef, wreg} + +function AArch64_WatchpointException (vaddress, fault) = { + assert(PSTATE.EL != EL3, "((PSTATE).EL != EL3)"); + route_to_el2 : bool = ((HaveEL(EL2) & ~(IsSecure())) & (PSTATE.EL == EL0 | PSTATE.EL == EL1)) & ([HCR_EL2[27]] == 0b1 | [MDCR_EL2[8]] == 0b1); + preferred_exception_return : bits(64) = ThisInstrAddr(); + vect_offset : int = 0; + exception : ExceptionRecord = AArch64_AbortSyndrome(Exception_Watchpoint, fault, vaddress); + if PSTATE.EL == EL2 | route_to_el2 then AArch64_TakeException(EL2, exception, preferred_exception_return, vect_offset) else AArch64_TakeException(EL1, exception, preferred_exception_return, vect_offset) +} + +val AArch64_VectorCatchException : FaultRecord -> unit effect {escape, rreg, undef, wreg} + +function AArch64_VectorCatchException fault = { + assert(PSTATE.EL != EL2, "((PSTATE).EL != EL2)"); + assert((HaveEL(EL2) & ~(IsSecure())) & ([HCR_EL2[27]] == 0b1 | [MDCR_EL2[8]] == 0b1), "((HaveEL(EL2) && !(IsSecure())) && (((HCR_EL2).TGE == '1') || ((MDCR_EL2).TDE == '1')))"); + preferred_exception_return : bits(64) = ThisInstrAddr(); + vect_offset : int = 0; + vaddress : bits(64) = undefined; + exception : ExceptionRecord = AArch64_AbortSyndrome(Exception_VectorCatch, fault, vaddress); + AArch64_TakeException(EL2, exception, preferred_exception_return, vect_offset) +} + +val AArch64_UndefinedFault : unit -> unit effect {escape, rreg, undef, wreg} + +function AArch64_UndefinedFault () = { + route_to_el2 : bool = ((HaveEL(EL2) & ~(IsSecure())) & PSTATE.EL == EL0) & [HCR_EL2[27]] == 0b1; + preferred_exception_return : bits(64) = ThisInstrAddr(); + vect_offset : int = 0; + exception : ExceptionRecord = ExceptionSyndrome(Exception_Uncategorized); + if UInt(PSTATE.EL) > UInt(EL1) then AArch64_TakeException(PSTATE.EL, exception, preferred_exception_return, vect_offset) else if route_to_el2 then AArch64_TakeException(EL2, exception, preferred_exception_return, vect_offset) else AArch64_TakeException(EL1, exception, preferred_exception_return, vect_offset) +} + +val AArch64_SPAlignmentFault : unit -> unit effect {escape, rreg, undef, wreg} + +function AArch64_SPAlignmentFault () = { + preferred_exception_return : bits(64) = ThisInstrAddr(); + vect_offset : int = 0; + exception : ExceptionRecord = ExceptionSyndrome(Exception_SPAlignment); + if UInt(PSTATE.EL) > UInt(EL1) then AArch64_TakeException(PSTATE.EL, exception, preferred_exception_return, vect_offset) else if (HaveEL(EL2) & ~(IsSecure())) & [HCR_EL2[27]] == 0b1 then AArch64_TakeException(EL2, exception, preferred_exception_return, vect_offset) else AArch64_TakeException(EL1, exception, preferred_exception_return, vect_offset) +} + +val CheckSPAlignment : unit -> unit effect {escape, rreg, undef, wreg} + +function CheckSPAlignment () = { + sp : bits(64) = aget_SP(); + stack_align_check : bool = undefined; + if PSTATE.EL == EL0 then stack_align_check = [aget_SCTLR()[4]] != 0b0 else stack_align_check = [aget_SCTLR()[3]] != 0b0; + if stack_align_check & sp != Align(sp, 16) then AArch64_SPAlignmentFault() else (); + () +} + +val AArch64_InstructionAbort : (bits(64), FaultRecord) -> unit effect {escape, rreg, undef, wreg} + +function AArch64_InstructionAbort (vaddress, fault) = { + route_to_el3 : bool = (HaveEL(EL3) & [SCR_EL3[3]] == 0b1) & IsExternalAbort(fault); + route_to_el2 : bool = ((HaveEL(EL2) & ~(IsSecure())) & (PSTATE.EL == EL0 | PSTATE.EL == EL1)) & (([HCR_EL2[27]] == 0b1 | IsSecondStage(fault)) | (HaveRASExt() & [HCR_EL2[37]] == 0b1) & IsExternalAbort(fault)); + preferred_exception_return : bits(64) = ThisInstrAddr(); + vect_offset : int = 0; + exception : ExceptionRecord = AArch64_AbortSyndrome(Exception_InstructionAbort, fault, vaddress); + if PSTATE.EL == EL3 | route_to_el3 then AArch64_TakeException(EL3, exception, preferred_exception_return, vect_offset) else if PSTATE.EL == EL2 | route_to_el2 then AArch64_TakeException(EL2, exception, preferred_exception_return, vect_offset) else AArch64_TakeException(EL1, exception, preferred_exception_return, vect_offset) +} + +val AArch64_DataAbort : (bits(64), FaultRecord) -> unit effect {escape, rreg, undef, wreg} + +function AArch64_DataAbort (vaddress, fault) = { + route_to_el3 : bool = (HaveEL(EL3) & [SCR_EL3[3]] == 0b1) & IsExternalAbort(fault); + route_to_el2 : bool = ((HaveEL(EL2) & ~(IsSecure())) & (PSTATE.EL == EL0 | PSTATE.EL == EL1)) & (([HCR_EL2[27]] == 0b1 | IsSecondStage(fault)) | (HaveRASExt() & [HCR_EL2[37]] == 0b1) & IsExternalAbort(fault)); + preferred_exception_return : bits(64) = ThisInstrAddr(); + vect_offset : int = 0; + exception : ExceptionRecord = AArch64_AbortSyndrome(Exception_DataAbort, fault, vaddress); + if PSTATE.EL == EL3 | route_to_el3 then AArch64_TakeException(EL3, exception, preferred_exception_return, vect_offset) else if PSTATE.EL == EL2 | route_to_el2 then AArch64_TakeException(EL2, exception, preferred_exception_return, vect_offset) else AArch64_TakeException(EL1, exception, preferred_exception_return, vect_offset) +} + +val AArch64_BreakpointException : FaultRecord -> unit effect {escape, rreg, undef, wreg} + +function AArch64_BreakpointException fault = { + assert(PSTATE.EL != EL3, "((PSTATE).EL != EL3)"); + route_to_el2 : bool = ((HaveEL(EL2) & ~(IsSecure())) & (PSTATE.EL == EL0 | PSTATE.EL == EL1)) & ([HCR_EL2[27]] == 0b1 | [MDCR_EL2[8]] == 0b1); + preferred_exception_return : bits(64) = ThisInstrAddr(); + vect_offset : int = 0; + vaddress : bits(64) = undefined; + exception : ExceptionRecord = AArch64_AbortSyndrome(Exception_Breakpoint, fault, vaddress); + if PSTATE.EL == EL2 | route_to_el2 then AArch64_TakeException(EL2, exception, preferred_exception_return, vect_offset) else AArch64_TakeException(EL1, exception, preferred_exception_return, vect_offset) +} + +val AArch64_Abort : (bits(64), FaultRecord) -> unit effect {escape, rreg, undef, wreg} + +function AArch64_Abort (vaddress, fault) = if IsDebugException(fault) then if fault.acctype == AccType_IFETCH then if UsingAArch32() & fault.debugmoe == DebugException_VectorCatch then AArch64_VectorCatchException(fault) else AArch64_BreakpointException(fault) else AArch64_WatchpointException(vaddress, fault) else if fault.acctype == AccType_IFETCH then AArch64_InstructionAbort(vaddress, fault) else AArch64_DataAbort(vaddress, fault) + +val AArch64_CheckAlignment : (bits(64), int, AccType, bool) -> bool effect {escape, rreg, undef, wreg} + +function AArch64_CheckAlignment (address, 'alignment, acctype, iswrite) = { + aligned : bool = address == Align(address, alignment); + atomic : bool = acctype == AccType_ATOMIC | acctype == AccType_ATOMICRW; + ordered : bool = acctype == AccType_ORDERED | acctype == AccType_ORDEREDRW | acctype == AccType_LIMITEDORDERED; + vector_name : bool = acctype == AccType_VEC; + check : bool = (atomic | ordered) | [aget_SCTLR()[1]] == 0b1; + secondstage : bool = undefined; + if check & ~(aligned) then { + secondstage = false; + AArch64_Abort(address, AArch64_AlignmentFault(acctype, iswrite, secondstage)) + } else (); + return(aligned) +} + +val AArch32_EnterMode : (bits(5), bits(32), int, int) -> unit effect {escape, rreg, undef, wreg} + +function AArch32_EnterMode (target_mode, preferred_exception_return, 'lr_offset, 'vect_offset) = { + SynchronizeContext(); + assert(ELUsingAArch32(EL1) & PSTATE.EL != EL2, "(ELUsingAArch32(EL1) && ((PSTATE).EL != EL2))"); + spsr : bits(32) = GetPSRFromPSTATE(); + if PSTATE.M == M32_Monitor then SCR = __SetSlice_bits(32, 1, SCR, 0, 0b0) else (); + AArch32_WriteMode(target_mode); + aset_SPSR(spsr); + aset_R(14, preferred_exception_return + lr_offset); + PSTATE.T = [SCTLR[30]]; + PSTATE.SS = 0b0; + if target_mode == M32_FIQ then (PSTATE.A, PSTATE.I, PSTATE.F) = 0b111 else if target_mode == M32_Abort | target_mode == M32_IRQ then (PSTATE.A, PSTATE.I) = 0b11 else PSTATE.I = 0b1; + PSTATE.E = [SCTLR[25]]; + PSTATE.IL = 0b0; + PSTATE.IT = 0x00; + if HavePANExt() & [SCTLR[23]] == 0b0 then PSTATE.PAN = 0b1 else (); + BranchTo(slice(ExcVectorBase(), 5, 27) @ __GetSlice_int(5, vect_offset, 0), BranchType_UNKNOWN); + EndOfInstruction() +} + +val AArch64_AccessIsPrivileged : AccType -> bool effect {escape, rreg, undef} + +function AArch64_AccessIsPrivileged acctype = { + ispriv : bool = undefined; + if PSTATE.EL == EL0 then ispriv = false else if PSTATE.EL == EL3 then ispriv = true else if PSTATE.EL == EL2 & (~(IsInHost()) | [HCR_EL2[27]] == 0b0) then ispriv = true else if HaveUAOExt() & PSTATE.UAO == 0b1 then ispriv = true else ispriv = acctype != AccType_UNPRIV; + return(ispriv) +} + +val AArch64_CheckWatchpoint : (bits(64), AccType, bool, int) -> FaultRecord effect {wreg, rreg, undef, escape} + +function AArch64_CheckWatchpoint (vaddress, acctype, iswrite, size) = { + assert(~(ELUsingAArch32(S1TranslationRegime())), "!(ELUsingAArch32(S1TranslationRegime()))"); + val_match : bool = false; + ispriv : bool = AArch64_AccessIsPrivileged(acctype); + foreach (i from 0 to UInt(slice(ID_AA64DFR0_EL1, 20, 4)) by 1 in inc) + val_match = val_match | AArch64_WatchpointMatch(i, vaddress, size, ispriv, iswrite); + reason : bits(6) = undefined; + if val_match & HaltOnBreakpointOrWatchpoint() then { + reason = DebugHalt_Watchpoint; + Halt(reason); + undefined + } else if (val_match & [MDSCR_EL1[15]] == 0b1) & AArch64_GenerateDebugExceptions() then return(AArch64_DebugFault(acctype, iswrite)) else return(AArch64_NoFault()) +} + +val AArch64_CheckDebug : (bits(64), AccType, bool, int) -> FaultRecord effect {escape, rreg, undef, wreg} + +function AArch64_CheckDebug (vaddress, acctype, iswrite, 'size) = { + fault : FaultRecord = AArch64_NoFault(); + d_side : bool = acctype != AccType_IFETCH; + generate_exception : bool = AArch64_GenerateDebugExceptions() & [MDSCR_EL1[15]] == 0b1; + halt : bool = HaltOnBreakpointOrWatchpoint(); + if generate_exception | halt then if d_side then fault = AArch64_CheckWatchpoint(vaddress, acctype, iswrite, size) else fault = AArch64_CheckBreakpoint(vaddress, size) else (); + return(fault) +} + +val AArch64_CheckPermission : (Permissions, bits(64), int, bits(1), AccType, bool) -> FaultRecord effect {rreg, undef, escape} + +function AArch64_CheckPermission (perms, vaddress, level, NS, acctype, iswrite) = { + assert(~(ELUsingAArch32(S1TranslationRegime())), "!(ELUsingAArch32(S1TranslationRegime()))"); + wxn : bool = [aget_SCTLR()[19]] == 0b1; + xn : bool = undefined; + w : bool = undefined; + r : bool = undefined; + priv_xn : bool = undefined; + user_xn : bool = undefined; + pan : bits(1) = undefined; + ispriv : bool = undefined; + user_w : bool = undefined; + user_r : bool = undefined; + priv_w : bool = undefined; + priv_r : bool = undefined; + if (PSTATE.EL == EL0 | PSTATE.EL == EL1) | IsInHost() then { + priv_r = true; + priv_w = [perms.ap[2]] == 0b0; + user_r = [perms.ap[1]] == 0b1; + user_w = slice(perms.ap, 1, 2) == 0b01; + ispriv = AArch64_AccessIsPrivileged(acctype); + pan = if HavePANExt() then PSTATE.PAN else 0b0; + if ((((HaveNVExt() & HaveEL(EL2)) & [HCR_EL2[42]] == 0b1) & [HCR_EL2[43]] == 0b1) & ~(IsSecure())) & PSTATE.EL == EL1 then + pan = 0b0 + else (); + if ((pan == 0b1 & user_r) & ispriv) & ~(acctype == AccType_DC | acctype == AccType_AT | acctype == AccType_IFETCH) | acctype == AccType_AT & AArch64_ExecutingATS1xPInstr() then { + priv_r = false; + priv_w = false + } else (); + user_xn = perms.xn == 0b1 | user_w & wxn; + priv_xn = (perms.pxn == 0b1 | priv_w & wxn) | user_w; + if ispriv then (r, w, xn) = (priv_r, priv_w, priv_xn) + else (r, w, xn) = (user_r, user_w, user_xn) + } else { + r = true; + w = [perms.ap[2]] == 0b0; + xn = perms.xn == 0b1 | w & wxn + }; + if ((HaveEL(EL3) & IsSecure()) & NS == 0b1) & [SCR_EL3[9]] == 0b1 then + xn = true + else (); + failedread : bool = undefined; + fail : bool = undefined; + if acctype == AccType_IFETCH then { + fail = xn; + failedread = true + } else if acctype == AccType_ATOMICRW | acctype == AccType_ORDEREDRW then { + fail = ~(r) | ~(w); + failedread = ~(r) + } else if iswrite then { + fail = ~(w); + failedread = false + } else { + fail = ~(r); + failedread = true + }; + ipaddress : bits(52) = undefined; + s2fs1walk : bool = undefined; + secondstage : bool = undefined; + if fail then { + secondstage = false; + s2fs1walk = false; + ipaddress = undefined; + return(AArch64_PermissionFault(ipaddress, level, acctype, ~(failedread), secondstage, s2fs1walk)) + } else return(AArch64_NoFault()) +} + +val AArch64_FirstStageTranslate : (bits(64), AccType, bool, bool, int) -> AddressDescriptor effect {escape, rmem, rreg, undef, wmem} + +function AArch64_FirstStageTranslate (vaddress, acctype, iswrite, wasaligned, 'size) = { + s1_enabled : bool = undefined; + if HasS2Translation() then s1_enabled = ([HCR_EL2[27]] == 0b0 & [HCR_EL2[12]] == 0b0) & [SCTLR_EL1[0]] == 0b1 else s1_enabled = [aget_SCTLR()[0]] == 0b1; + ipaddress : bits(52) = undefined; + secondstage : bool = false; + s2fs1walk : bool = false; + nTLSMD : bits(1) = undefined; + permissioncheck : bool = undefined; + S1 : TLBRecord = undefined; + if s1_enabled then { + S1 = AArch64_TranslationTableWalk(ipaddress, vaddress, acctype, iswrite, secondstage, s2fs1walk, size); + permissioncheck = true + } else { + S1 = AArch64_TranslateAddressS1Off(vaddress, acctype, iswrite); + permissioncheck = false; + if (UsingAArch32() & HaveTrapLoadStoreMultipleDeviceExt()) & AArch32_ExecutingLSMInstr() then if S1.addrdesc.memattrs.typ == MemType_Device & S1.addrdesc.memattrs.device != DeviceType_GRE then { + nTLSMD = if S1TranslationRegime() == EL2 then [SCTLR_EL2[28]] else [SCTLR_EL1[28]]; + if nTLSMD == 0b0 then { + __tmp_246 : AddressDescriptor = S1.addrdesc; + __tmp_246.fault = AArch64_AlignmentFault(acctype, iswrite, secondstage); + S1.addrdesc = __tmp_246 + } else () + } else () else () + }; + if ((~(wasaligned) & acctype != AccType_IFETCH | acctype == AccType_DCZVA) & S1.addrdesc.memattrs.typ == MemType_Device) & ~(IsFault(S1.addrdesc)) then { + __tmp_247 : AddressDescriptor = S1.addrdesc; + __tmp_247.fault = AArch64_AlignmentFault(acctype, iswrite, secondstage); + S1.addrdesc = __tmp_247 + } else (); + if ~(IsFault(S1.addrdesc)) & permissioncheck then { + __tmp_248 : AddressDescriptor = S1.addrdesc; + __tmp_248.fault = AArch64_CheckPermission(S1.perms, vaddress, S1.level, S1.addrdesc.paddress.NS, acctype, iswrite); + S1.addrdesc = __tmp_248 + } else (); + if (~(IsFault(S1.addrdesc)) & S1.addrdesc.memattrs.typ == MemType_Device) & acctype == AccType_IFETCH then S1.addrdesc = AArch64_InstructionDevice(S1.addrdesc, vaddress, ipaddress, S1.level, acctype, iswrite, secondstage, s2fs1walk) else (); + hwupdatewalk : bool = false; + s2fs1walk = false; + __tmp_249 : AddressDescriptor = S1.addrdesc; + __tmp_249.fault = AArch64_CheckAndUpdateDescriptor(S1.descupdate, S1.addrdesc.fault, secondstage, vaddress, acctype, iswrite, s2fs1walk, hwupdatewalk); + S1.addrdesc = __tmp_249; + return(S1.addrdesc) +} + +val AArch64_FullTranslate : (bits(64), AccType, bool, bool, int) -> AddressDescriptor effect {escape, rmem, rreg, undef, wmem} + +function AArch64_FullTranslate (vaddress, acctype, iswrite, wasaligned, 'size) = { + S1 : AddressDescriptor = AArch64_FirstStageTranslate(vaddress, acctype, iswrite, wasaligned, size); + result : AddressDescriptor = undefined; + hwupdatewalk : bool = undefined; + s2fs1walk : bool = undefined; + if ~(IsFault(S1)) & HasS2Translation() then { + s2fs1walk = false; + hwupdatewalk = false; + result = AArch64_SecondStageTranslate(S1, vaddress, acctype, iswrite, wasaligned, s2fs1walk, size, hwupdatewalk) + } else result = S1; + return(result) +} + +val AArch64_TranslateAddress : (bits(64), AccType, bool, bool, int) -> AddressDescriptor effect {escape, rmem, rreg, undef, wmem, wreg} + +function AArch64_TranslateAddress (vaddress, acctype, iswrite, wasaligned, 'size) = { + result : AddressDescriptor = AArch64_FullTranslate(vaddress, acctype, iswrite, wasaligned, size); + if ~(acctype == AccType_PTW | acctype == AccType_IC | acctype == AccType_AT) & ~(IsFault(result)) then result.fault = AArch64_CheckDebug(vaddress, acctype, iswrite, size) else (); + result.vaddress = ZeroExtend(vaddress); + return(result) +} + +val AArch64_aset_MemSingle : forall ('size : Int), 64 >= 0 & 8 * 'size >= 0. + (bits(64), atom('size), AccType, bool, bits(8 * 'size)) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} + +function AArch64_aset_MemSingle (address, size, acctype, wasaligned, value_name) = { + assert('size == 1 | 'size == 2 | 'size == 4 | 'size == 8 | 'size == 16, "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))"); + assert(address == Align(address, 'size), "(address == Align(address, size))"); + memaddrdesc : AddressDescriptor = undefined; + iswrite : bool = true; + memaddrdesc = AArch64_TranslateAddress(address, acctype, iswrite, wasaligned, 'size); + if IsFault(memaddrdesc) then AArch64_Abort(address, memaddrdesc.fault) else (); + if memaddrdesc.memattrs.shareable then ClearExclusiveByAddress(memaddrdesc.paddress, ProcessorID(), 'size) else (); + accdesc : AccessDescriptor = CreateAccessDescriptor(acctype); + aset__Mem(memaddrdesc, 'size, accdesc, value_name); + () +} + +val aset_Mem : forall ('size : Int), 64 >= 0 & 8 * 'size >= 0. + (bits(64), atom('size), AccType, bits(8 * 'size)) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} + +function aset_Mem (address, size, acctype, value_name__arg) = { + value_name = value_name__arg; + i : int = undefined; + iswrite : bool = true; + if BigEndian() then value_name = BigEndianReverse(value_name) else (); + aligned : bool = AArch64_CheckAlignment(address, 'size, acctype, iswrite); + atomic : bool = undefined; + if 'size != 16 | ~(acctype == AccType_VEC | acctype == AccType_VECSTREAM) then atomic = aligned else atomic = address == Align(address, 8); + c : Constraint = undefined; + if ~(atomic) then { + assert('size > 1, "(size > 1)"); + AArch64_aset_MemSingle(address, 1, acctype, aligned, slice(value_name, 0, 8)); + if ~(aligned) then { + c = ConstrainUnpredictable(Unpredictable_DEVPAGE2); + assert(c == Constraint_FAULT | c == Constraint_NONE, "((c == Constraint_FAULT) || (c == Constraint_NONE))"); + if c == Constraint_NONE then aligned = true else () + } else (); + foreach (i from 1 to ('size - 1) by 1 in inc) + AArch64_aset_MemSingle(address + i, 1, acctype, aligned, slice(value_name, 8 * i, 8)) + } else if 'size == 16 & (acctype == AccType_VEC | acctype == AccType_VECSTREAM) then { + AArch64_aset_MemSingle(address, 8, acctype, aligned, slice(value_name, 0, 64)); + AArch64_aset_MemSingle(address + 8, 8, acctype, aligned, slice(value_name, 64, 64)) + } else AArch64_aset_MemSingle(address, 'size, acctype, aligned, value_name); + () +} + +val AArch64_aget_MemSingle : forall ('size : Int), 64 >= 0 & 8 * 'size >= 0. + (bits(64), atom('size), AccType, bool) -> bits(8 * 'size) effect {escape, rmem, rreg, undef, wmem, wreg} + +function AArch64_aget_MemSingle (address, size, acctype, wasaligned) = { + assert('size == 1 | 'size == 2 | 'size == 4 | 'size == 8 | 'size == 16, "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))"); + assert(address == Align(address, 'size), "(address == Align(address, size))"); + memaddrdesc : AddressDescriptor = undefined; + value_name : bits(8 * 'size) = undefined; + iswrite : bool = false; + memaddrdesc = AArch64_TranslateAddress(address, acctype, iswrite, wasaligned, 'size); + if IsFault(memaddrdesc) then AArch64_Abort(address, memaddrdesc.fault) else (); + accdesc : AccessDescriptor = CreateAccessDescriptor(acctype); + value_name = aget__Mem(memaddrdesc, 'size, accdesc); + return(value_name) +} + +val aget_Mem : forall ('size : Int), 64 >= 0 & 8 * 'size >= 0. + (bits(64), atom('size), AccType) -> bits(8 * 'size) effect {escape, rmem, rreg, undef, wmem, wreg} + +function aget_Mem (address, size, acctype) = { + assert('size == 1 | 'size == 2 | 'size == 4 | 'size == 8 | 'size == 16, "((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))"); + value_name : bits(8 * 'size) = undefined; + i : int = undefined; + iswrite : bool = false; + aligned : bool = AArch64_CheckAlignment(address, 'size, acctype, iswrite); + atomic : bool = undefined; + if 'size != 16 | ~(acctype == AccType_VEC | acctype == AccType_VECSTREAM) then atomic = aligned else atomic = address == Align(address, 8); + c : Constraint = undefined; + if ~(atomic) then { + assert('size > 1, "(size > 1)"); + value_name = __SetSlice_bits(8 * 'size, 8, value_name, 0, AArch64_aget_MemSingle(address, 1, acctype, aligned)); + if ~(aligned) then { + c = ConstrainUnpredictable(Unpredictable_DEVPAGE2); + assert(c == Constraint_FAULT | c == Constraint_NONE, "((c == Constraint_FAULT) || (c == Constraint_NONE))"); + if c == Constraint_NONE then aligned = true else () + } else (); + foreach (i from 1 to ('size - 1) by 1 in inc) + value_name = __SetSlice_bits(8 * 'size, 8, value_name, 8 * i, AArch64_aget_MemSingle(address + i, 1, acctype, aligned)) + } else if 'size == 16 & (acctype == AccType_VEC | acctype == AccType_VECSTREAM) then { + value_name = __SetSlice_bits(8 * 'size, 64, value_name, 0, AArch64_aget_MemSingle(address, 8, acctype, aligned)); + value_name = __SetSlice_bits(8 * 'size, 64, value_name, 64, AArch64_aget_MemSingle(address + 8, 8, acctype, aligned)) + } else value_name = AArch64_aget_MemSingle(address, 'size, acctype, aligned); + if BigEndian() then value_name = BigEndianReverse(value_name) else (); + return(value_name) +} + +val AArch32_GeneralExceptionsToAArch64 : unit -> bool effect {escape, rreg, undef} + +function AArch32_GeneralExceptionsToAArch64 () = return(PSTATE.EL == EL0 & ~(ELUsingAArch32(EL1)) | ((HaveEL(EL2) & ~(IsSecure())) & ~(ELUsingAArch32(EL2))) & [HCR_EL2[27]] == 0b1) + +val AArch32_EnterHypMode : (ExceptionRecord, bits(32), int) -> unit effect {escape, rreg, undef, wreg} + +function AArch32_EnterHypMode (exception, preferred_exception_return, 'vect_offset) = { + SynchronizeContext(); + assert((HaveEL(EL2) & ~(IsSecure())) & ELUsingAArch32(EL2), "((HaveEL(EL2) && !(IsSecure())) && ELUsingAArch32(EL2))"); + spsr : bits(32) = GetPSRFromPSTATE(); + if ~(exception.typ == Exception_IRQ | exception.typ == Exception_FIQ) then AArch32_ReportHypEntry(exception) else (); + AArch32_WriteMode(M32_Hyp); + aset_SPSR(spsr); + ELR_hyp = preferred_exception_return; + PSTATE.T = [HSCTLR[30]]; + PSTATE.SS = 0b0; + if ~(HaveEL(EL3)) | [aget_SCR_GEN()[3]] == 0b0 then PSTATE.A = 0b1 else (); + if ~(HaveEL(EL3)) | [aget_SCR_GEN()[1]] == 0b0 then PSTATE.I = 0b1 else (); + if ~(HaveEL(EL3)) | [aget_SCR_GEN()[2]] == 0b0 then PSTATE.F = 0b1 else (); + PSTATE.E = [HSCTLR[25]]; + PSTATE.IL = 0b0; + PSTATE.IT = 0x00; + BranchTo(slice(HVBAR, 5, 27) @ __GetSlice_int(5, vect_offset, 0), BranchType_UNKNOWN); + EndOfInstruction() +} + +val AArch32_TakeUndefInstrException__0 : unit -> unit effect {escape, undef, wreg, rreg} + +val AArch32_TakeUndefInstrException__1 : ExceptionRecord -> unit effect {escape, rreg, undef, wreg} + +overload AArch32_TakeUndefInstrException = { + AArch32_TakeUndefInstrException__0, + AArch32_TakeUndefInstrException__1 +} + +function AArch32_TakeUndefInstrException__0 () = { + exception : ExceptionRecord = ExceptionSyndrome(Exception_Uncategorized); + AArch32_TakeUndefInstrException(exception) +} + +function AArch32_TakeUndefInstrException__1 exception = { + route_to_hyp : bool = ((HaveEL(EL2) & ~(IsSecure())) & PSTATE.EL == EL0) & [HCR[27]] == 0b1; + preferred_exception_return : bits(32) = ThisInstrAddr(); + vect_offset : int = 4; + lr_offset : int = if CurrentInstrSet() == InstrSet_A32 then 4 else 2; + if PSTATE.EL == EL2 then AArch32_EnterHypMode(exception, preferred_exception_return, vect_offset) else if route_to_hyp then AArch32_EnterHypMode(exception, preferred_exception_return, 20) else AArch32_EnterMode(M32_Undef, preferred_exception_return, lr_offset, vect_offset) +} + +val UnallocatedEncoding : unit -> unit effect {escape, rreg, undef, wreg} + +function UnallocatedEncoding () = { + if UsingAArch32() & AArch32_ExecutingCP10or11Instr() then FPEXC = __SetSlice_bits(32, 1, FPEXC, 29, 0b0) else (); + if UsingAArch32() & ~(AArch32_GeneralExceptionsToAArch64()) then AArch32_TakeUndefInstrException() else AArch64_UndefinedFault() +} + +val aarch64_memory_single_general_immediate_unsigned : forall ('datasize : Int) ('regsize : Int). + (AccType, atom('datasize), MemOp, int, bits(64), bool, atom('regsize), bool, int, bool) -> unit effect {escape, undef, rreg, wreg, wmem, rmem} + +function aarch64_memory_single_general_immediate_unsigned (acctype, datasize, memop, n, offset, postindex, regsize, signed, t, wback__arg) = { + assert(constraint('regsize >= 0), "destsize constraint"); + let 'dbytes = ex_int(datasize / 8); + assert(constraint('datasize in {8, 16, 32, 64, 128}), "datasize constraint"); + assert(constraint(8 * 'dbytes = 'datasize), "dbytes constraint"); + wback = wback__arg; + address : bits(64) = undefined; + data : bits('datasize) = undefined; + wb_unknown : bool = false; + rt_unknown : bool = false; + c : Constraint = undefined; + if ((memop == MemOp_LOAD & wback) & n == t) & n != 31 then { + c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); + assert(c == Constraint_WBSUPPRESS | c == Constraint_UNKNOWN | c == Constraint_UNDEF | c == Constraint_NOP, "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))"); + match c { + Constraint_WBSUPPRESS => wback = false, + Constraint_UNKNOWN => wb_unknown = true, + Constraint_UNDEF => UnallocatedEncoding(), + Constraint_NOP => EndOfInstruction() + } + } else (); + if ((memop == MemOp_STORE & wback) & n == t) & n != 31 then { + c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); + assert(c == Constraint_NONE | c == Constraint_UNKNOWN | c == Constraint_UNDEF | c == Constraint_NOP, "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))"); + match c { + Constraint_NONE => rt_unknown = false, + Constraint_UNKNOWN => rt_unknown = true, + Constraint_UNDEF => UnallocatedEncoding(), + Constraint_NOP => EndOfInstruction() + } + } else (); + if n == 31 then { + if memop != MemOp_PREFETCH then CheckSPAlignment() else (); + address = aget_SP() + } else address = aget_X(n); + if ~(postindex) then address = address + offset + else (); + match memop { + MemOp_STORE => { + if rt_unknown then data = undefined + else data = aget_X(t); + aset_Mem(address, dbytes, acctype, data) + }, + MemOp_LOAD => { + data = aget_Mem(address, dbytes, acctype); + if signed then aset_X(t, SignExtend(data, regsize)) else aset_X(t, ZeroExtend(data, regsize)) + }, + MemOp_PREFETCH => Prefetch(address, __GetSlice_int(5, t, 0)) + }; + if wback then { + if wb_unknown then address = undefined + else if postindex then address = address + offset + else (); + if n == 31 then aset_SP(address) else aset_X(n, address) + } else () +} + +val aarch64_memory_single_general_immediate_signed_postidx : forall ('datasize : Int) ('regsize : Int). + (AccType, atom('datasize), MemOp, int, bits(64), bool, atom('regsize), bool, int, bool) -> unit effect {escape, undef, rreg, wreg, wmem, rmem} + +function aarch64_memory_single_general_immediate_signed_postidx (acctype, datasize, memop, n, offset, postindex, regsize, signed, t, wback__arg) = { + assert(constraint('regsize >= 0), "destsize constraint"); + let 'dbytes = ex_int(datasize / 8); + assert(constraint('datasize in {8, 16, 32, 64, 128}), "datasize constraint"); + assert(constraint(8 * 'dbytes = 'datasize), "dbytes constraint"); + wback = wback__arg; + address : bits(64) = undefined; + data : bits('datasize) = undefined; + wb_unknown : bool = false; + rt_unknown : bool = false; + c : Constraint = undefined; + if ((memop == MemOp_LOAD & wback) & n == t) & n != 31 then { + c = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); + assert(c == Constraint_WBSUPPRESS | c == Constraint_UNKNOWN | c == Constraint_UNDEF | c == Constraint_NOP, "((c == Constraint_WBSUPPRESS) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))"); + match c { + Constraint_WBSUPPRESS => wback = false, + Constraint_UNKNOWN => wb_unknown = true, + Constraint_UNDEF => UnallocatedEncoding(), + Constraint_NOP => EndOfInstruction() + } + } else (); + if ((memop == MemOp_STORE & wback) & n == t) & n != 31 then { + c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); + assert(c == Constraint_NONE | c == Constraint_UNKNOWN | c == Constraint_UNDEF | c == Constraint_NOP, "((c == Constraint_NONE) || ((c == Constraint_UNKNOWN) || ((c == Constraint_UNDEF) || (c == Constraint_NOP))))"); + match c { + Constraint_NONE => rt_unknown = false, + Constraint_UNKNOWN => rt_unknown = true, + Constraint_UNDEF => UnallocatedEncoding(), + Constraint_NOP => EndOfInstruction() + } + } else (); + if n == 31 then { + if memop != MemOp_PREFETCH then CheckSPAlignment() else (); + address = aget_SP() + } else address = aget_X(n); + if ~(postindex) then address = address + offset + else (); + match memop { + MemOp_STORE => { + if rt_unknown then data = undefined + else data = aget_X(t); + aset_Mem(address, dbytes, acctype, data) + }, + MemOp_LOAD => { + data = aget_Mem(address, dbytes, acctype); + if signed then aset_X(t, SignExtend(data, regsize)) else aset_X(t, ZeroExtend(data, regsize)) + }, + MemOp_PREFETCH => Prefetch(address, __GetSlice_int(5, t, 0)) + }; + if wback then { + if wb_unknown then address = undefined + else if postindex then address = address + offset + else (); + if n == 31 then aset_SP(address) else aset_X(n, address) + } else () +} + +val memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode : (bits(2), bits(1), bits(2), bits(12), bits(5), bits(5)) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} + +function memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_unsigned__decode (size, V, opc, imm12, Rn, Rt) = { + __unconditional = true; + wback : bool = false; + postindex : bool = false; + scale : int = UInt(size); + offset : bits(64) = LSL(ZeroExtend(imm12, 64), scale); + n : int = UInt(Rn); + t : int = UInt(Rt); + acctype : AccType = AccType_NORMAL; + memop : MemOp = undefined; + signed : bool = undefined; + regsize : int = undefined; + if [opc[1]] == 0b0 then { + memop = if [opc[0]] == 0b1 then MemOp_LOAD else MemOp_STORE; + regsize = if size == 0b11 then 64 else 32; + signed = false + } else if size == 0b11 then { + memop = MemOp_PREFETCH; + if [opc[0]] == 0b1 then UnallocatedEncoding() else () + } else { + memop = MemOp_LOAD; + if size == 0b10 & [opc[0]] == 0b1 then UnallocatedEncoding() else (); + regsize = if [opc[0]] == 0b1 then 32 else 64; + signed = true + }; + datasize : int = shl_int(8, scale); + aarch64_memory_single_general_immediate_unsigned(acctype, datasize, memop, n, offset, postindex, regsize, signed, t, wback) +} + +val memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode : (bits(2), bits(1), bits(2), bits(12), bits(5), bits(5)) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} + +function memory_single_general_immediate_unsigned_aarch64_memory_single_general_immediate_signed_postidx__decode (size, V, opc, imm12, Rn, Rt) = { + __unconditional = true; + wback : bool = false; + postindex : bool = false; + scale : int = UInt(size); + offset : bits(64) = LSL(ZeroExtend(imm12, 64), scale); + n : int = UInt(Rn); + t : int = UInt(Rt); + acctype : AccType = AccType_NORMAL; + memop : MemOp = undefined; + signed : bool = undefined; + regsize : int = undefined; + if [opc[1]] == 0b0 then { + memop = if [opc[0]] == 0b1 then MemOp_LOAD else MemOp_STORE; + regsize = if size == 0b11 then 64 else 32; + signed = false + } else if size == 0b11 then UnallocatedEncoding() else { + memop = MemOp_LOAD; + if size == 0b10 & [opc[0]] == 0b1 then UnallocatedEncoding() else (); + regsize = if [opc[0]] == 0b1 then 32 else 64; + signed = true + }; + datasize : int = shl_int(8, scale); + aarch64_memory_single_general_immediate_signed_postidx(acctype, datasize, memop, n, offset, postindex, regsize, signed, t, wback) +} + +val memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode : (bits(2), bits(1), bits(2), bits(9), bits(5), bits(5)) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} + +function memory_single_general_immediate_signed_preidx_aarch64_memory_single_general_immediate_signed_postidx__decode (size, V, opc, imm9, Rn, Rt) = { + __unconditional = true; + wback : bool = true; + postindex : bool = false; + scale : int = UInt(size); + offset : bits(64) = SignExtend(imm9, 64); + n : int = UInt(Rn); + t : int = UInt(Rt); + acctype : AccType = AccType_NORMAL; + memop : MemOp = undefined; + signed : bool = undefined; + regsize : int = undefined; + if [opc[1]] == 0b0 then { + memop = if [opc[0]] == 0b1 then MemOp_LOAD else MemOp_STORE; + regsize = if size == 0b11 then 64 else 32; + signed = false + } else if size == 0b11 then UnallocatedEncoding() else { + memop = MemOp_LOAD; + if size == 0b10 & [opc[0]] == 0b1 then UnallocatedEncoding() else (); + regsize = if [opc[0]] == 0b1 then 32 else 64; + signed = true + }; + datasize : int = shl_int(8, scale); + aarch64_memory_single_general_immediate_signed_postidx(acctype, datasize, memop, n, offset, postindex, regsize, signed, t, wback) +} + +val memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode : (bits(2), bits(1), bits(2), bits(9), bits(5), bits(5)) -> unit effect {escape, rmem, rreg, undef, wmem, wreg} + +function memory_single_general_immediate_signed_postidx_aarch64_memory_single_general_immediate_signed_postidx__decode (size, V, opc, imm9, Rn, Rt) = { + __unconditional = true; + wback : bool = true; + postindex : bool = true; + scale : int = UInt(size); + offset : bits(64) = SignExtend(imm9, 64); + n : int = UInt(Rn); + t : int = UInt(Rt); + acctype : AccType = AccType_NORMAL; + memop : MemOp = undefined; + signed : bool = undefined; + regsize : int = undefined; + if [opc[1]] == 0b0 then { + memop = if [opc[0]] == 0b1 then MemOp_LOAD else MemOp_STORE; + regsize = if size == 0b11 then 64 else 32; + signed = false + } else if size == 0b11 then UnallocatedEncoding() else { + memop = MemOp_LOAD; + if size == 0b10 & [opc[0]] == 0b1 then UnallocatedEncoding() else (); + regsize = if [opc[0]] == 0b1 then 32 else 64; + signed = true + }; + datasize : int = shl_int(8, scale); + aarch64_memory_single_general_immediate_signed_postidx(acctype, datasize, memop, n, offset, postindex, regsize, signed, t, wback) +} + +val ReservedValue : unit -> unit effect {escape, rreg, undef, wreg} + +function ReservedValue () = if UsingAArch32() & ~(AArch32_GeneralExceptionsToAArch64()) then AArch32_TakeUndefInstrException() else AArch64_UndefinedFault() + +val integer_arithmetic_addsub_immediate_decode : (bits(1), bits(1), bits(1), bits(2), bits(12), bits(5), bits(5)) -> unit effect {escape, undef, rreg, wreg} + +function integer_arithmetic_addsub_immediate_decode (sf, op, S, shift, imm12, Rn, Rd) = { + __unconditional = true; + d : int = UInt(Rd); + n : int = UInt(Rn); + let 'datasize : {|64, 32|} = if sf == 0b1 then 64 else 32; + sub_op : bool = op == 0b1; + setflags : bool = S == 0b1; + imm : bits('datasize) = undefined; + match shift { + 0b00 => imm = ZeroExtend(imm12, datasize), + 0b01 => imm = ZeroExtend(imm12 @ Zeros(12), datasize), + [bitone] @ _ : bits(1) => ReservedValue() + }; + aarch64_integer_arithmetic_addsub_immediate(d, datasize, imm, n, setflags, sub_op) +} diff --git a/aarch64/prelude.sail b/aarch64/prelude.sail index ab916e27..46d12375 100644 --- a/aarch64/prelude.sail +++ b/aarch64/prelude.sail @@ -5,10 +5,6 @@ $include <flow.sail> type bits ('n : Int) = vector('n, dec, bit) -infix 4 == - -val eq_int = {ocaml: "eq_int", lem: "eq"} : (int, int) -> bool - val eq_vec = {ocaml: "eq_list", lem: "eq_vec"} : forall 'n. (bits('n), bits('n)) -> bool val eq_string = {ocaml: "eq_string", lem: "eq"} : (string, string) -> bool @@ -27,7 +23,7 @@ val list_length = {ocaml: "length", lem: "length_list"} : forall ('a : Type). li overload length = {bitvector_length, vector_length, list_length} -overload operator == = {eq_atom, eq_int, eq_vec, eq_string, eq_real, eq_anything} +overload operator == = {eq_vec, eq_string, eq_real, eq_anything} val vector_subrange_A = {ocaml: "subrange", lem: "subrange_vec_dec"} : forall ('n : Int) ('m : Int) ('o : Int), 'o <= 'm <= 'n. (bits('n), atom('m), atom('o)) -> bits('m - ('o - 1)) @@ -91,17 +87,17 @@ function neq_anything (x, y) = not_bool(x == y) overload operator != = {neq_atom, neq_int, neq_vec, neq_anything} -val builtin_and_vec = {ocaml: "and_vec", lem: "Sail_operators.and_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) +val builtin_and_vec = {ocaml: "and_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) -val and_vec : forall 'n. (bits('n), bits('n)) -> bits('n) +val and_vec = {lem: "and_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) function and_vec (xs, ys) = builtin_and_vec(xs, ys) overload operator & = {and_bool, and_vec} -val builtin_or_vec = {ocaml: "or_vec", lem: "Sail_operators.or_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) +val builtin_or_vec = {ocaml: "or_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) -val or_vec : forall 'n. (bits('n), bits('n)) -> bits('n) +val or_vec = {lem: "or_vec"}: forall 'n. (bits('n), bits('n)) -> bits('n) function or_vec (xs, ys) = builtin_or_vec(xs, ys) @@ -208,26 +204,18 @@ overload operator * = {mult_range, mult_int, mult_real} val Sqrt = {ocaml: "sqrt_real", lem: "realSqrt"} : real -> real -val gteq_int = "gteq" : (int, int) -> bool - val gteq_real = {ocaml: "gteq_real", lem: "gteq"} : (real, real) -> bool overload operator >= = {gteq_atom, gteq_int, gteq_real} -val lteq_int = "lteq" : (int, int) -> bool - val lteq_real = {ocaml: "lteq_real", lem: "lteq"} : (real, real) -> bool overload operator <= = {lteq_atom, lteq_int, lteq_real} -val gt_int = "gt" : (int, int) -> bool - val gt_real = {ocaml: "gt_real", lem: "gt"} : (real, real) -> bool overload operator > = {gt_atom, gt_int, gt_real} -val lt_int = "lt" : (int, int) -> bool - val lt_real = {ocaml: "lt_real", lem: "lt"} : (real, real) -> bool overload operator < = {lt_atom, lt_int, lt_real} @@ -248,14 +236,10 @@ val quotient_real = {ocaml: "quotient_real", lem: "realDiv"} : (real, real) -> r val quotient = {ocaml: "quotient", lem: "integerDiv"} : (int, int) -> int -infixl 7 / - overload operator / = {quotient_nat, quotient, quotient_real} val modulus = {ocaml: "modulus", lem: "hardware_mod"} : (int, int) -> int -infixl 7 % - overload operator % = {modulus} val Real = {ocaml: "to_real", lem: "realFromInteger"} : int -> real diff --git a/lib/flow.sail b/lib/flow.sail index cb7b1b99..52c98753 100644 --- a/lib/flow.sail +++ b/lib/flow.sail @@ -5,7 +5,7 @@ val not_bool = "not" : bool -> bool val and_bool = "and_bool" : (bool, bool) -> bool val or_bool = "or_bool" : (bool, bool) -> bool -val eq_atom = {ocaml: "eq_int", lem: "eq"} : forall 'n 'm. (atom('n), atom('m)) -> bool +val eq_atom = {ocaml: "eq_int", lem: "eq", c: "eq_int"} : forall 'n 'm. (atom('n), atom('m)) -> bool val neq_atom = {lem: "neq"} : forall 'n 'm. (atom('n), atom('m)) -> bool @@ -25,6 +25,16 @@ val lteq_atom_range = "lteq" : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> boo val gt_atom_range = "gt" : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> bool val gteq_atom_range = "gteq" : forall 'n 'm 'o. (atom('n), range('m, 'o)) -> bool +val eq_range = {ocaml: "eq_int", lem: "eq"} : forall 'n 'm 'o 'p. (range('n, 'm), range('o, 'p)) -> bool +val eq_int = {ocaml: "eq_int", lem: "eq"} : (int, int) -> bool + +val lteq_int = "lteq" : (int, int) -> bool +val gteq_int = "gteq" : (int, int) -> bool +val lt_int = "lt" : (int, int) -> bool +val gt_int = "lt" : (int, int) -> bool + +overload operator == = {eq_atom, eq_range, eq_int} + $ifdef TEST val __flow_test : forall 'n 'm. (atom('n), atom('m)) -> unit diff --git a/lib/isabelle/Makefile b/lib/isabelle/Makefile index 5ff58069..84af5d75 100644 --- a/lib/isabelle/Makefile +++ b/lib/isabelle/Makefile @@ -1,10 +1,13 @@ -THYS = Sail_impl_base.thy Sail_values.thy Sail_operators.thy State.thy Prompt.thy +THYS = Sail_impl_base.thy Sail_values.thy Sail_operators.thy \ + Sail_operators_mwords.thy Sail_operators_bitlists.thy \ + State_monad.thy State.thy Prompt_monad.thy Prompt.thy +EXTRA_THYS = State_monad_extras.thy Prompt_monad_extras.thy .PHONY: all heap-img clean all: heap-img -heap-img: $(THYS) +heap-img: $(THYS) $(EXTRA_THYS) ROOT @echo '*** To build a heap image with the Sail library, please' @echo '*** add the ROOT file in this directory to your ROOTS file' @echo '*** (e.g. $$HOME/.isabelle/Isabelle<version>/ROOTS)' @@ -20,13 +23,22 @@ Sail_values.thy: ../../src/gen_lib/sail_values.lem Sail_impl_base.thy Sail_operators.thy: ../../src/gen_lib/sail_operators.lem Sail_values.thy lem -isa -outdir . -lib ../../src/lem_interp -lib ../../src/gen_lib $< -Sail_operators_mwords.thy: ../../src/gen_lib/sail_operators_mwords.lem Sail_values.thy +Sail_operators_mwords.thy: ../../src/gen_lib/sail_operators_mwords.lem Sail_operators.thy lem -isa -outdir . -lib ../../src/lem_interp -lib ../../src/gen_lib $< -State.thy: ../../src/gen_lib/state.lem Sail_values.thy +Sail_operators_bitlists.thy: ../../src/gen_lib/sail_operators_bitlists.lem Sail_operators.thy lem -isa -outdir . -lib ../../src/lem_interp -lib ../../src/gen_lib $< -Prompt.thy: ../../src/gen_lib/prompt.lem Sail_values.thy +State_monad.thy: ../../src/gen_lib/state_monad.lem Sail_values.thy + lem -isa -outdir . -lib ../../src/lem_interp -lib ../../src/gen_lib $< + +State.thy: ../../src/gen_lib/state.lem State_monad.thy State_monad_extras.thy + lem -isa -outdir . -lib ../../src/lem_interp -lib ../../src/gen_lib $< + +Prompt_monad.thy: ../../src/gen_lib/prompt_monad.lem Sail_values.thy + lem -isa -outdir . -lib ../../src/lem_interp -lib ../../src/gen_lib $< + +Prompt.thy: ../../src/gen_lib/prompt.lem Prompt_monad.thy Prompt_monad_extras.thy lem -isa -outdir . -lib ../../src/lem_interp -lib ../../src/gen_lib $< clean: diff --git a/lib/isabelle/Prompt_monad_extras.thy b/lib/isabelle/Prompt_monad_extras.thy new file mode 100644 index 00000000..0c319f97 --- /dev/null +++ b/lib/isabelle/Prompt_monad_extras.thy @@ -0,0 +1,214 @@ +theory Prompt_monad_extras + imports Prompt_monad +begin + +lemma All_bind_dom: "bind_dom (oc, f)" + by (induction oc) (auto intro: bind.domintros; blast intro: bind.domintros)+ + +termination bind using All_bind_dom by auto + +lemma bind_induct[case_names Done Read_mem Read_reg Write_memv Excl_res Write_ea Barrier Footprint Write_reg Escape Fail Error Exception Internal]: + fixes m :: "('a, 'e) outcome" and f :: "'a \<Rightarrow> ('b, 'e) outcome" + assumes "\<And>a f. P (Done a) f" + and "\<And>rk addr sz k f. (\<And>v m' opt. (m', opt) = k v \<Longrightarrow> P m' f) \<Longrightarrow> P (Read_mem (rk, addr, sz) k) f" + and "\<And>reg k f. (\<And>v m' opt. (m', opt) = k v \<Longrightarrow> P m' f) \<Longrightarrow> P (Read_reg reg k) f" + and "\<And>val k f. (\<And>v m' opt. (m', opt) = k v \<Longrightarrow> P m' f) \<Longrightarrow> P (Write_memv val k) f" + and "\<And>k f. (\<And>v m' opt. (m', opt) = k v \<Longrightarrow> P m' f) \<Longrightarrow> P (Excl_res k) f" + and "\<And>wk addr sz m opt f. P m f \<Longrightarrow> P (Write_ea (wk, addr, sz) (m, opt)) f" + and "\<And>bk m opt f. P m f \<Longrightarrow> P (Barrier bk (m, opt)) f" + and "\<And>m opt f. P m f \<Longrightarrow> P (Footprint (m, opt)) f" + and "\<And>reg val m opt f. P m f \<Longrightarrow> P (Write_reg (reg, val) (m, opt)) f" + and "\<And>descr f. P (Escape descr) f" + and "\<And>descr f. P (Fail descr) f" and "\<And>descr f. P (Error descr) f" and "\<And>e f. P (Exception e) f" + and "\<And>i m opt f. P m f \<Longrightarrow> P (Internal i (m, opt)) f" + shows "P m f" + by (rule bind.induct[split_format (complete), OF assms]; blast) + +datatype event = + (* Request to read memory *) + Read_mem read_kind address_lifted nat memory_value + (* Write is imminent, at address lifted, of size nat *) + | Write_ea write_kind address_lifted nat + (* Request the result of store-exclusive *) + | Excl_res bool + (* Request to write memory at last signalled address. Memory value should be 8 + times the size given in ea signal *) + | Write_memv memory_value bool + (* Request a memory barrier *) + | Barrier " barrier_kind " + (* Tell the system to dynamically recalculate dependency footprint *) + | Footprint + (* Request to read register *) + | Read_reg reg_name register_value + (* Request to write register *) + | Write_reg reg_name register_value + | Internal " ( string option * (unit \<Rightarrow> string)option) " + +inductive_set T :: "(('a, 'e)outcome \<times> event \<times> ('a, 'e)outcome) set" where + Read_mem: "\<exists>opt. k v = (m, opt) \<Longrightarrow> ((outcome.Read_mem (rk, addr, sz) k), Read_mem rk addr sz v, m) \<in> T" +| Write_ea: "\<exists>opt. k = (m, opt) \<Longrightarrow> ((outcome.Write_ea (rk, addr, sz) k), Write_ea rk addr sz, m) \<in> T" +| Excl_res: "\<exists>opt. k r = (m, opt) \<Longrightarrow> ((outcome.Excl_res k), Excl_res r, m) \<in> T" +| Write_memv: "\<exists>opt. k r = (m, opt) \<Longrightarrow> ((outcome.Write_memv v k), Write_memv v r, m) \<in> T" +| Barrier: "\<exists>opt. k = (m, opt) \<Longrightarrow> ((outcome.Barrier bk k), Barrier bk, m) \<in> T" +| Footprint: "\<exists>opt. k = (m, opt) \<Longrightarrow> ((outcome.Footprint k), Footprint, m) \<in> T" +| Read_reg: "\<exists>opt. k v = (m, opt) \<Longrightarrow> ((outcome.Read_reg r k), Read_reg r v, m) \<in> T" +| Write_reg: "\<exists>opt. k = (m, opt) \<Longrightarrow> ((outcome.Write_reg (r, v) k), Write_reg r v, m) \<in> T" +| Internal: "\<exists>opt. k = (m, opt) \<Longrightarrow> ((outcome.Internal descr k), Internal descr, m) \<in> T" + +inductive_set Traces :: "(('a, 'r)outcome \<times> event list \<times> ('a, 'r)outcome) set" where + Nil: "(s, [], s) \<in> Traces" +| Step: "\<lbrakk>(s, e, s'') \<in> T; (s'', t, s') \<in> Traces\<rbrakk> \<Longrightarrow> (s, e # t, s') \<in> Traces" + +declare Traces.intros[intro] +declare T.intros[intro] + +declare prod.splits[split] +(* lemma fst_case_bind[simp]: "fst (case k of (o1, x) \<Rightarrow> (bind o1 f, x)) = bind (fst k) f" + by (cases k) auto *) + +lemmas Traces_ConsI = T.intros[THEN Step, rotated] + +inductive_cases Traces_NilE[elim]: "(s, [], s') \<in> Traces" +inductive_cases Traces_ConsE[elim]: "(s, e # t, s') \<in> Traces" + +abbreviation Run :: "('a, 'r)outcome \<Rightarrow> event list \<Rightarrow> 'a \<Rightarrow> bool" + where "Run s t a \<equiv> (s, t, Done a) \<in> Traces" + +lemma Run_appendI: + assumes "(s, t1, s') \<in> Traces" + and "Run s' t2 a" + shows "Run s (t1 @ t2) a" +proof (use assms in \<open>induction t1 arbitrary: s\<close>) + case (Cons e t1) + then show ?case by (elim Traces_ConsE) auto +qed auto + +lemma bind_DoneE: + assumes "bind m f = outcome.Done a" + obtains a' where "m = outcome.Done a'" and "f a' = outcome.Done a" + using assms by (auto elim: bind.elims) + +lemma bind_T_cases: + assumes "(bind m f, e, s') \<in> T" + obtains (Done) a where "m = Done a" + | (Bind) m' where "s' = bind m' f" and "(m, e, m') \<in> T" +proof cases + assume D: "\<forall>a. m \<noteq> Done a" + show thesis using assms proof cases + case (Read_mem k v rk addr sz) + then obtain k' where "m = outcome.Read_mem (rk, addr, sz) k'" using D by (cases m) auto + then show ?thesis using Read_mem by (intro Bind[of "fst (k' v)"]) auto + next + case (Write_ea k rk addr sz) + then obtain k' where "m = outcome.Write_ea (rk, addr, sz) k'" using D by (cases m) auto + then show ?thesis using Write_ea by (intro Bind[of "fst k'"]) auto + next + case (Excl_res k r) + then obtain k' where "m = outcome.Excl_res k'" using D by (cases m) auto + then show ?thesis using Excl_res by (intro Bind[of "fst (k' r)"]) auto + next + case (Write_memv k r v) + then obtain k' where "m = outcome.Write_memv v k'" using D by (cases m) auto + then show ?thesis using Write_memv by (intro Bind[of "fst (k' r)"]) auto + next + case (Barrier k bk) + then obtain k' where "m = outcome.Barrier bk k'" using D by (cases m) auto + then show ?thesis using Barrier by (intro Bind[of "fst k'"]) auto + next + case (Footprint k) + then obtain k' where "m = outcome.Footprint k'" using D by (cases m) auto + then show ?thesis using Footprint by (intro Bind[of "fst k'"]) auto + next + case (Read_reg k v r) + then obtain k' where "m = outcome.Read_reg r k'" using D by (cases m) auto + then show ?thesis using Read_reg by (intro Bind[of "fst (k' v)"]) (auto split: prod.splits) + next + case (Write_reg k r v) + then obtain k' where "m = outcome.Write_reg (r, v) k'" using D by (cases m) auto + then show ?thesis using Write_reg by (intro Bind[of "fst k'"]) auto + next + case (Internal k descr) + then obtain k' where "m = outcome.Internal descr k'" using D by (cases m) auto + then show ?thesis using Internal by (intro Bind[of "fst k'"]) auto + qed +qed auto + +lemma Run_bindE: + fixes m :: "('b, 'r) outcome" and a :: 'a + assumes "Run (bind m f) t a" + obtains tm am tf where "t = tm @ tf" and "Run m tm am" and "Run (f am) tf a" +proof (use assms in \<open>induction "bind m f" t "Done a :: ('a,'r) outcome" arbitrary: m rule: Traces.induct\<close>) + case Nil + obtain am where "m = Done am" and "f am = Done a" using Nil(1) by (elim bind_DoneE) + then show ?case by (intro Nil(2)) auto +next + case (Step e s'' t m) + show thesis using Step(1) + proof (cases rule: bind_T_cases) + case (Done am) + then show ?thesis using Step(1,2) by (intro Step(4)[of "[]" "e # t" am]) auto + next + case (Bind m') + show ?thesis proof (rule Step(3)[OF Bind(1)]) + fix tm tf am + assume "t = tm @ tf" and "Run m' tm am" and "Run (f am) tf a" + then show thesis using Bind by (intro Step(4)[of "e # tm" tf am]) auto + qed + qed +qed + +lemma Run_DoneE: + assumes "Run (Done a) t a'" + obtains "t = []" and "a' = a" + using assms by (auto elim: Traces.cases T.cases) + +lemma Run_Done_iff_Nil[simp]: "Run (Done a) t a' \<longleftrightarrow> t = [] \<and> a' = a" + by (auto elim: Run_DoneE) + +lemma Run_BarrierE[elim!]: + assumes "Run (outcome.Barrier bk k) t a" + obtains t' where "t = Barrier bk # t'" and "Run (fst k) t' a" + using assms by cases (auto elim: T.cases) + +lemma bind_cong[fundef_cong]: + assumes m: "m1 = m2" + and f: "\<And>t a. Run m2 t a \<Longrightarrow> f1 a = f2 a" + shows "bind m1 f1 = bind m2 f2" +proof (unfold m, use f in \<open>induction m2 f1 arbitrary: f2 rule: bind_induct\<close>) + case (Read_mem rk addr sz k f) + have "bind m' f = bind m' f2" if k: "k v = (m', opt)" for v m' opt + using k by (auto intro!: Read_mem.IH[of _ opt v] Read_mem.prems) + then show ?case by auto +next + case (Read_reg reg k f) + have "bind m' f = bind m' f2" if k: "k v = (m', opt)" for v m' opt + using k by (auto intro!: Read_reg.IH[of _ opt v] Read_reg.prems) + then show ?case by auto +next + case (Write_memv val k f) + have "bind m' f = bind m' f2" if k: "k v = (m', opt)" for v m' opt + using k by (auto intro!: Write_memv.IH[of _ opt v] Write_memv.prems) + then show ?case by auto +next + case (Excl_res k f) + have "bind m' f = bind m' f2" if k: "k v = (m', opt)" for v m' opt + using k by (auto intro!: Excl_res.IH[of _ opt v] Excl_res.prems) + then show ?case by auto +next + case (Write_ea wk addr sz m opt f) + show ?case by (auto intro!: Write_ea) +next + case (Barrier bk m opt f) + show ?case by (auto intro!: Barrier) +next + case (Footprint m opt f) + show ?case by (auto intro!: Footprint) +next + case (Write_reg reg val m opt f) + show ?case by (auto intro!: Write_reg) +next + case (Internal i m opt f) + show ?case by (auto intro!: Internal) +qed auto + +end diff --git a/lib/isabelle/ROOT b/lib/isabelle/ROOT index 2062b64b..c798447e 100644 --- a/lib/isabelle/ROOT +++ b/lib/isabelle/ROOT @@ -4,7 +4,8 @@ session "Sail" = "LEM" + Sail_values State Prompt - Sail_operators + Sail_operators_mwords + Sail_operators_bitlists (*session "Sail" = "Sail_Base" + options [document = false] diff --git a/lib/isabelle/State_monad_extras.thy b/lib/isabelle/State_monad_extras.thy new file mode 100644 index 00000000..c9522f58 --- /dev/null +++ b/lib/isabelle/State_monad_extras.thy @@ -0,0 +1,25 @@ +theory State_monad_extras + imports State_monad +begin + +lemma bind_ext_cong[fundef_cong]: + assumes m: "m1 s = m2 s" + and f: "\<And>a s'. (Value a, s') \<in> set (m2 s) \<Longrightarrow> f1 a s' = f2 a s'" + shows "(bind m1 f1) s = (bind m2 f2) s" +proof - + have "List.concat (map (\<lambda>x. case x of (Value a, s') \<Rightarrow> f1 a s' | (Exception0 e, s') \<Rightarrow> [(Exception0 e, s')]) (m2 s)) = + List.concat (map (\<lambda>x. case x of (Value a, s') \<Rightarrow> f2 a s' | (Exception0 e, s') \<Rightarrow> [(Exception0 e, s')]) (m2 s))" + using f by (intro arg_cong[where f = List.concat]) (auto intro: map_ext split: result.splits) + then show ?thesis using m by (auto simp: bind_def) +qed + +lemma bind_cong[fundef_cong]: + assumes m: "m1 = m2" + and f: "\<And>s a s'. (Value a, s') \<in> set (m2 s) \<Longrightarrow> f1 a s' = f2 a s'" + shows "bind m1 f1 = bind m2 f2" + using assms by (blast intro: bind_ext_cong) + +lemma bind_return[simp]: "bind (return x) m = m x" + by (auto simp add: bind_def return_def) + +end diff --git a/lib/mono_rewrites.sail b/lib/mono_rewrites.sail index 650fdf53..1af9b17f 100644 --- a/lib/mono_rewrites.sail +++ b/lib/mono_rewrites.sail @@ -16,6 +16,9 @@ val shiftright = "shiftr" : forall 'n ('ord : Order). overload operator >> = {shiftright} +val arith_shiftright = "arith_shiftr" : forall 'n ('ord : Order). + (vector('n, 'ord, bit), int) -> vector('n, 'ord, bit) effect pure + val "extz_vec" : forall 'n 'm. (atom('m),vector('n, dec, bit)) -> vector('m, dec, bit) effect pure val extzv : forall 'n 'm. vector('n, dec, bit) -> vector('m, dec, bit) effect pure function extzv(v) = extz_vec(sizeof('m),v) diff --git a/riscv/Makefile b/riscv/Makefile index 7f52dde7..aeba80ef 100644 --- a/riscv/Makefile +++ b/riscv/Makefile @@ -11,6 +11,19 @@ check: $(SAIL_SRCS) main.sail riscv: $(SAIL_SRCS) main.sail $(SAIL_DIR)/sail -ocaml -o riscv $^ +riscv_duopod_ocaml: prelude.sail riscv_duopod.sail + $(SAIL_DIR)/sail -ocaml -o $@ $^ + +riscv_duopod_embed_sequential.lem: prelude.sail riscv_duopod.sail + $(SAIL_DIR)/sail -lem -lem_sequential -lem_mwords -lem_lib Riscv_extras_embed -o riscv_duopod $^ +Riscv_duopod_embed_sequential.thy: riscv_duopod_embed_sequential.lem riscv_extras_embed_sequential.lem + lem -isa -outdir . -lib ../src/lem_interp -lib ../src/gen_lib \ + riscv_extras_embed_sequential.lem \ + riscv_duopod_embed_types_sequential.lem \ + riscv_duopod_embed_sequential.lem + +riscv_duopod: riscv_duopod_ocaml Riscv_duopod_embed_sequential.thy + Riscv_embed_sequential.thy: riscv_embed_sequential.lem riscv_extras_embed_sequential.lem lem -isa -outdir . -lib ../src/lem_interp -lib ../src/gen_lib \ riscv_extras_embed_sequential.lem \ @@ -25,3 +38,4 @@ clean: -rm -f riscv_embed_sequential.lem riscv_embed_types_sequential.lem -rm -f Riscv_embed_sequential.thy Riscv_embed_types_sequential.thy \ Riscv_extras_embed_sequential.thy + -rm -f Riscv_duopod_embed_sequential.thy Riscv_duopod_embed_types_sequential.thy riscv_duopod_embed_sequential.lem riscv_duopod_embed_types_sequential.lem diff --git a/riscv/main.sail b/riscv/main.sail index cc6bb90c..4209b7d1 100644 --- a/riscv/main.sail +++ b/riscv/main.sail @@ -6,12 +6,29 @@ function fetch_and_execute () = let tohost = __GetSlice_int(64, elf_tohost(), 0) in while true do { print_bits("PC: ", PC); + + /* for now, always fetch a 32-bit value. this would need to + change with privileged mode, since we could cross a page + boundary with PC only 16-bit aligned in C mode. */ let instr = __RISCV_read(PC, 4); - nextPC = PC + 4; - let instr_ast = decode(instr); - match instr_ast { - Some(ast) => execute(ast), - None => {print("Decode failed"); exit (())} + + let (instr_ast, instr_sz) : (option(ast), int)= + match (instr[1 .. 0]) { + 0b11 => (decode(instr), 4), + _ => (decodeCompressed(instr[15 .. 0]), 2) + }; + /* check whether a compressed instruction is legal. */ + if (misa.C() == 0b0 & (instr_sz == 2)) then { + let t : sync_exception = + struct { trap = Illegal_Instr, + excinfo = Some (EXTZ(instr)) } in + nextPC = handle_exception_ctl(cur_privilege, CTL_TRAP(t), PC) + } else { + nextPC = PC + instr_sz; + match instr_ast { + Some(ast) => execute(ast), + None => {print("Decode failed"); exit (())} + } }; let tohost_val = __RISCV_read(tohost, 4); if unsigned(tohost_val) != 0 then { diff --git a/riscv/prelude.sail b/riscv/prelude.sail index dacde107..a0d3d3a1 100644 --- a/riscv/prelude.sail +++ b/riscv/prelude.sail @@ -2,7 +2,6 @@ default Order dec type bits ('n : Int) = vector('n, dec, bit) union option ('a : Type) = {None, Some : 'a} -infix 4 == val eq_atom = {ocaml: "eq_int", lem: "eq"} : forall 'n 'm. (atom('n), atom('m)) -> bool val lteq_atom = "lteq" : forall 'n 'm. (atom('n), atom('m)) -> bool @@ -91,9 +90,9 @@ overload operator != = {neq_atom, neq_int, neq_vec, neq_anything} val and_bool = "and_bool" : (bool, bool) -> bool -val builtin_and_vec = {ocaml: "and_vec", lem: "Sail_operators.and_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) +val builtin_and_vec = {ocaml: "and_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) -val and_vec : forall 'n. (bits('n), bits('n)) -> bits('n) +val and_vec = {lem: "and_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) function and_vec (xs, ys) = builtin_and_vec(xs, ys) @@ -101,9 +100,9 @@ overload operator & = {and_bool, and_vec} val or_bool = "or_bool" : (bool, bool) -> bool -val builtin_or_vec = {ocaml: "or_vec", lem: "Sail_operators.or_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) +val builtin_or_vec = {ocaml: "or_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) -val or_vec : forall 'n. (bits('n), bits('n)) -> bits('n) +val or_vec = {lem: "or_vec"} : forall 'n. (bits('n), bits('n)) -> bits('n) function or_vec (xs, ys) = builtin_or_vec(xs, ys) @@ -152,6 +151,8 @@ val putchar = "putchar" : forall ('a : Type). 'a -> unit val concat_str = {ocaml: "concat_str", lem: "stringAppend"} : (string, string) -> string +val string_of_int = "string_of_int" : int -> string + val DecStr : int -> string val HexStr : int -> string @@ -160,7 +161,7 @@ val BitStr = "string_of_bits" : forall 'n. bits('n) -> string val xor_vec = "xor_vec" : forall 'n. (bits('n), bits('n)) -> bits('n) -val int_power = {lem: "pow"} : (int, int) -> int +val int_power = {ocaml: "int_power", lem: "pow"} : (int, int) -> int val real_power = {ocaml: "real_power", lem: "realPowInteger"} : (real, int) -> real @@ -251,13 +252,12 @@ val quotient_real = {ocaml: "quotient_real", lem: "realDiv"} : (real, real) -> r val quotient = {ocaml: "quotient", lem: "integerDiv"} : (int, int) -> int -infixl 7 / - overload operator / = {quotient_nat, quotient, quotient_real} -val modulus = {ocaml: "modulus", lem: "hardware_mod"} : (int, int) -> int +val quot_round_zero = {ocaml: "quot_round_zero", lem: "hardware_quot"} : (int, int) -> int +val rem_round_zero = {ocaml: "rem_round_zero", lem: "hardware_mod"} : (int, int) -> int -infixl 7 % +val modulus = {ocaml: "modulus", lem: "hardware_mod"} : (int, int) -> int overload operator % = {modulus} @@ -376,6 +376,9 @@ val vector64 : int -> bits(64) function vector64 n = __raw_GetSlice_int(64, n, 0) +val to_bits : forall 'l.(atom('l), int) -> bits('l) +function to_bits (l, n) = __raw_GetSlice_int(l, n, 0) + function break () : unit -> unit = () val vector_update_subrange_dec = {ocaml: "update_subrange", lem: "update_subrange_vec_dec"} : forall 'n 'm 'o. diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 9ec5734e..37244735 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -3,6 +3,10 @@ scattered union ast val decode : bits(32) -> option(ast) effect pure scattered function decode +val decodeCompressed : bits(16) -> option(ast) effect pure +scattered function decodeCompressed + + val execute : ast -> unit effect {escape, wreg, rreg, wmv, eamem, rmem, barr, exmem} scattered function execute @@ -29,7 +33,7 @@ function clause decode imm : bits(20) @ rd : regbits @ 0b1101111 = Some (RISCV_J function clause execute (RISCV_JAL(imm, rd)) = { let pc : bits(64) = PC; - wGPR(rd, pc + 4); + wGPR(rd, nextPC); /* compatible with JAL and C.JAL */ let offset : bits(64) = EXTS(imm); nextPC = pc + offset; } @@ -155,9 +159,9 @@ function clause decode imm : bits(12) @ rs1 : regbits @ 0b101 @ rd : regbits @ 0 function clause decode imm : bits(12) @ rs1 : regbits @ 0b110 @ rd : regbits @ 0b0000011 = Some(LOAD(imm, rs1, rd, true, WORD, false, false)) -function clause execute(LOAD(imm, rs1, rd, unsigned, width, aq, rl)) = +function clause execute(LOAD(imm, rs1, rd, is_unsigned, width, aq, rl)) = let addr : bits(64) = rGPR(rs1) + EXTS(imm) in - let result : bits(64) = if unsigned then + let result : bits(64) = if is_unsigned then match width { BYTE => EXTZ(mem_read(addr, 1, aq, rl, false)), HALF => EXTZ(mem_read(addr, 2, aq, rl, false)), @@ -248,6 +252,93 @@ function clause execute (RTYPEW(rs2, rs1, rd, op)) = wGPR(rd, EXTS(result)) /* ****************************************************************** */ + +union clause ast = MUL : (regbits, regbits, regbits, bool, bool, bool) + +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b000 @ rd : regbits @ 0b0110011 = Some(MUL(rs2, rs1, rd, false, true, true)) /* MUL */ +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b001 @ rd : regbits @ 0b0110011 = Some(MUL(rs2, rs1, rd, true, true, true)) /* MULH */ +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b010 @ rd : regbits @ 0b0110011 = Some(MUL(rs2, rs1, rd, true, true, false)) /* MULHSU */ +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b011 @ rd : regbits @ 0b0110011 = Some(MUL(rs2, rs1, rd, true, false, false)) /* MULHU */ +function clause execute (MUL(rs2, rs1, rd, high, signed1, signed2)) = + let rs1_val = rGPR(rs1) in + let rs2_val = rGPR(rs2) in + let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val) in + let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val) in + let result128 = to_bits(128, rs1_int * rs2_int) in + let result = if high then result128[127..64] else result128[63..0] in + wGPR(rd, result) + +/* ****************************************************************** */ + +union clause ast = DIV : (regbits, regbits, regbits, bool) +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b100 @ rd : regbits @ 0b0110011 = Some(DIV(rs2, rs1, rd, true)) /* DIV */ +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b101 @ rd : regbits @ 0b0110011 = Some(DIV(rs2, rs1, rd, false)) /* DIVU */ +function clause execute (DIV(rs2, rs1, rd, s)) = + let rs1_val = rGPR(rs1) in + let rs2_val = rGPR(rs2) in + let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val) in + let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val) in + let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int) in + let q': int = if s & q > (2 ^ 63 - 1) then (0 - 2^63) else q in /* check for signed overflow */ + wGPR(rd, to_bits(64, q')) + +/* ****************************************************************** */ + +union clause ast = REM : (regbits, regbits, regbits, bool) +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b110 @ rd : regbits @ 0b0110011 = Some(REM(rs2, rs1, rd, true)) /* REM */ +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b111 @ rd : regbits @ 0b0110011 = Some(REM(rs2, rs1, rd, false)) /* REMU */ +function clause execute (REM(rs2, rs1, rd, s)) = + let rs1_val = rGPR(rs1) in + let rs2_val = rGPR(rs2) in + let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val) in + let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val) in + let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int) in + /* signed overflow case returns zero naturally as required due to -1 divisor */ + wGPR(rd, to_bits(64, r)) + +/* ****************************************************************** */ + +union clause ast = MULW : (regbits, regbits, regbits) +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b000 @ rd : regbits @ 0b0111011 = Some(MULW(rs2, rs1, rd)) /* MULW */ +function clause execute (MULW(rs2, rs1, rd)) = + let rs1_val = rGPR(rs1)[31..0] in + let rs2_val = rGPR(rs2)[31..0] in + let rs1_int : int = signed(rs1_val) in + let rs2_int : int = signed(rs2_val) in + let result32 = to_bits(64, rs1_int * rs2_int)[31..0] in /* XXX surprising behaviour of to_bits requires exapnsion to 64 bits followed by truncation... */ + let result64 : regval = EXTS(result32) in + wGPR(rd, result64) + +/* ****************************************************************** */ + +union clause ast = DIVW : (regbits, regbits, regbits, bool) +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b100 @ rd : regbits @ 0b0111011 = Some(DIVW(rs2, rs1, rd, true)) /* DIVW */ +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b101 @ rd : regbits @ 0b0111011 = Some(DIVW(rs2, rs1, rd, false)) /* DIVUW */ +function clause execute (DIVW(rs2, rs1, rd, s)) = + let rs1_val = rGPR(rs1)[31..0] in + let rs2_val = rGPR(rs2)[31..0] in + let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val) in + let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val) in + let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int) in + let q': int = if s & q > (2 ^ 31 - 1) then (0 - 2^31) else q in /* check for signed overflow */ + wGPR(rd, EXTS(to_bits(32, q'))) + +/* ****************************************************************** */ + +union clause ast = REMW : (regbits, regbits, regbits, bool) +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b110 @ rd : regbits @ 0b0111011 = Some(REMW(rs2, rs1, rd, true)) /* REMW */ +function clause decode 0b0000001 @ rs2 : regbits @ rs1 : regbits @ 0b111 @ rd : regbits @ 0b0111011 = Some(REMW(rs2, rs1, rd, false)) /* REMUW */ +function clause execute (REMW(rs2, rs1, rd, s)) = + let rs1_val = rGPR(rs1)[31..0] in + let rs2_val = rGPR(rs2)[31..0] in + let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val) in + let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val) in + let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int) in + /* signed overflow case returns zero naturally as required due to -1 divisor */ + wGPR(rd, EXTS(to_bits(32, r))) + +/* ****************************************************************** */ + union clause ast = FENCE : (bits(4), bits(4)) function clause decode 0b0000 @ pred : bits(4) @ succ : bits(4) @ 0b00000 @ 0b000 @ 0b00000 @ 0b0001111 = Some(FENCE(pred, succ)) @@ -282,7 +373,7 @@ function clause execute ECALL = USER => User_ECall, MACHINE => Machine_ECall }, - badaddr = (None : option(regval)) } in + excinfo = (None : option(regval)) } in nextPC = handle_exception_ctl(cur_privilege, CTL_TRAP(t), PC) /* ****************************************************************** */ @@ -486,7 +577,7 @@ function clause execute CSR(csr, rs1, rd, is_imm, op) = let instr : regval = EXTZ(__RISCV_read(PC, 4)); let t : sync_exception = struct { trap = Illegal_Instr, - badaddr = Some (instr) } in + excinfo = Some (instr) } in nextPC = handle_exception_ctl(cur_privilege, CTL_TRAP(t), PC) } else { let csr_val = readCSR(csr); /* could have side-effects, so technically shouldn't perform for CSRW[I] with rd == 0 */ @@ -503,8 +594,325 @@ function clause execute CSR(csr, rs1, rd, is_imm, op) = /* ****************************************************************** */ +union clause ast = NOP + +function clause decodeCompressed (0b000 @ nzi1 : bits(1) @ 0b00000 @ (nzi0 : bits(5)) @ 0b01) : bits(16) = { + if (nzi1 == 0b0) & (nzi0 == 0b00000) then None + else Some(NOP) +} + +function clause execute (NOP) = () + +/* ****************************************************************** */ + +union clause ast = ILLEGAL + +function clause decodeCompressed (0b0000 @ 0b00000 @ 0b00000 @ 0b00) : bits(16) = Some(ILLEGAL) + +function clause execute (ILLEGAL) = { + let t : sync_exception = + struct { trap = Illegal_Instr, + excinfo = Some (EXTZ(0b0)) } in + nextPC = handle_exception_ctl(cur_privilege, CTL_TRAP(t), PC) +} + +/* ****************************************************************** */ + +union clause ast = C_ADDI4SPN : (cregbits, bits(8)) + +function clause decodeCompressed (0b000 @ nz54 : bits(2) @ nz96 : bits(4) @ nz2 : bits(1) @ nz3 : bits(1) @ rd : cregbits @ 0b00) : bits(16) = { + let nzimm = (nz96 @ nz54 @ nz3 @ nz2) : bits(8) in + if nzimm == 0b00000000 then None + else Some(C_ADDI4SPN(rd, nzimm)) +} + +function clause execute (C_ADDI4SPN(rdc, nzimm)) = { + let imm : bits(12) = (0b00 @ nzimm @ 0b00) in + let rd = creg2reg_bits(rdc) in + execute(ITYPE(imm, sp, rd, RISCV_ADDI)) +} + +/* ****************************************************************** */ + +union clause ast = C_LW : (bits(5), cregbits, cregbits) + +function clause decodeCompressed (0b010 @ ui53 : bits(3) @ rs1 : cregbits @ ui2 : bits(1) @ ui6 : bits(1) @ rd : cregbits @ 0b00) : bits(16) = { + let uimm = (ui6 @ ui53 @ ui2) : bits(5) in + Some(C_LW(uimm, rs1, rd)) +} + +function clause execute (C_LW(uimm, rsc, rdc)) = { + let imm : bits(12) = EXTZ(uimm @ 0b00) in + let rd = creg2reg_bits(rdc) in + let rs = creg2reg_bits(rsc) in + execute(LOAD(imm, rs, rd, true, WORD, false, false)) +} + +/* ****************************************************************** */ + +union clause ast = C_SW : (bits(5), cregbits, cregbits) + +function clause decodeCompressed (0b110 @ ui53 : bits(3) @ rs1 : cregbits @ ui2 : bits(1) @ ui6 : bits(1) @ rs2 : cregbits @ 0b00) : bits(16) = { + let uimm = (ui6 @ ui53 @ ui2) : bits(5) in + Some(C_SW(uimm, rs1, rs2)) +} + +function clause execute (C_SW(uimm, rsc1, rsc2)) = { + let imm : bits(12) = EXTZ(uimm @ 0b00) in + let rs1 = creg2reg_bits(rsc1) in + let rs2 = creg2reg_bits(rsc2) in + execute(STORE(imm, rs2, rs1, WORD, false, false)) +} + +/* ****************************************************************** */ + +union clause ast = C_SD : (bits(5), cregbits, cregbits) + +function clause decodeCompressed (0b111 @ ui53 : bits(3) @ rs1 : bits(3) @ ui76 : bits(2) @ rs2 : bits(3) @ 0b00): bits(16) = { + let uimm = (ui76 @ ui53) : bits(5) in + Some(C_SD(uimm, rs1, rs2)) +} + +function clause execute (C_SD(uimm, rsc1, rsc2)) = { + let imm : bits(12) = EXTZ(uimm @ 0b000) in + let rs1 = creg2reg_bits(rsc1) in + let rs2 = creg2reg_bits(rsc2) in + execute(STORE(imm, rs2, rs1, DOUBLE, false, false)) +} + +/* ****************************************************************** */ + +union clause ast = C_ADDI : (bits(6), regbits) + +function clause decodeCompressed (0b000 @ nzi5 : bits(1) @ rsd : regbits @ nzi40 : bits(5) @ 0b01) : bits(16) = { + let nzi = (nzi5 @ nzi40) : bits(6) in + if (nzi == 0b000000) | (rsd == zreg) then None + else Some(C_ADDI(nzi, rsd)) +} + +function clause execute (C_ADDI(nzi, rsd)) = { + let imm : bits(12) = EXTS(nzi) in + execute(ITYPE(imm, rsd, rsd, RISCV_ADDI)) +} + +/* ****************************************************************** */ + +union clause ast = C_JAL : (bits(11)) +union clause ast = C_ADDIW : (bits(6), regbits) + +/* FIXME: decoding differs for RVC32/RVC64. Below, we are assuming + * RV64, and C_JAL is RV32 only. */ + +function clause decodeCompressed (0b001 @ imm5 : bits(1) @ rsd : regbits @ imm40 : bits(5) @ 0b01) = + Some (C_ADDIW((imm5 @ imm40), rsd)) + +function clause execute (C_JAL(imm)) = { + execute(RISCV_JAL(EXTS(imm @ 0b0), ra)) +} + +function clause execute (C_ADDIW(imm, rsd)) = { + let imm : bits(32) = EXTS(imm) in + let rs_val = rGPR(rsd) in + let res : bits(32) = rs_val[31..0] + imm in + wGPR(rsd, EXTS(res)) +} + +/* ****************************************************************** */ + +union clause ast = C_LI : (bits(6), regbits) + +function clause decodeCompressed (0b010 @ imm5 : bits(1) @ rd : regbits @ imm40 : bits(5) @ 0b01) = { + if (rd == zreg) then None + else Some(C_LI(imm5 @ imm40, rd)) +} + +function clause execute (C_LI(imm, rd)) = { + let imm : bits(12) = EXTS(imm) in + execute(ITYPE(imm, zreg, rd, RISCV_ADDI)) +} + +/* ****************************************************************** */ + +union clause ast = C_ADDI16SP : (bits(6)) + +function clause decodeCompressed (0b011 @ nzi9 : bits(1) @ /* x2 */ 0b00010 @ nzi4 : bits(1) @ nzi6 : bits(1) @ nzi87 : bits(2) @ nzi5 : bits(1) @ 0b01) = { + let nzimm = nzi9 @ nzi87 @ nzi6 @ nzi5 @ nzi4 in + if (nzimm == 0b000000) then None + else Some(C_ADDI16SP(nzimm)) +} + +function clause execute (C_ADDI16SP(imm)) = { + let imm : bits(12) = EXTS(imm @ 0x0) in + execute(ITYPE(imm, sp, sp, RISCV_ADDI)) +} + +/* ****************************************************************** */ + +union clause ast = C_LUI : (bits(6), regbits) + +function clause decodeCompressed (0b011 @ imm17 : bits(1) @ rd : regbits @ imm1612 : bits(5) @ 0b01) = { + if (rd == zreg) | (rd == sp) then None + else Some(C_LUI(imm17 @ imm1612, rd)) +} + +function clause execute (C_LUI(imm, rd)) = { + let res : bits(20) = EXTS(imm) in + execute(UTYPE(res, rd, RISCV_LUI)) +} + +/* ****************************************************************** */ + +union clause ast = C_SRLI : (bits(6), cregbits) + +function clause decodeCompressed (0b100 @ nzui5 : bits(1) @ 0b00 @ rsd : cregbits @ nzui40 : bits(5) @ 0b01) = { + let shamt : bits(6) = nzui5 @ nzui40 in + if shamt == 0b000000 /* TODO: On RV32, also need shamt[5] == 0 */ + then None + else Some(C_SRLI(shamt, rsd)) +} + +function clause execute (C_SRLI(shamt, rsd)) = { + let rsd = creg2reg_bits(rsd) in + execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SRLI)) +} + +/* ****************************************************************** */ + +union clause ast = C_SRAI : (bits(6), cregbits) + +function clause decodeCompressed (0b100 @ nzui5 : bits(1) @ 0b01 @ rsd : cregbits @ nzui40 : bits(5) @ 0b01) = { + let shamt : bits(6) = nzui5 @ nzui40 in + if shamt == 0b000000 /* TODO: On RV32, also need shamt[5] == 0 */ + then None + else Some(C_SRAI(shamt, rsd)) +} + +function clause execute (C_SRAI(shamt, rsd)) = { + let rsd = creg2reg_bits(rsd) in + execute(SHIFTIOP(shamt, rsd, rsd, RISCV_SRAI)) +} + +/* ****************************************************************** */ + +union clause ast = C_ANDI : (bits(6), cregbits) + +function clause decodeCompressed (0b100 @ i5 : bits(1) @ 0b10 @ rsd : cregbits @ i40 : bits(5) @ 0b01) = Some(C_ANDI(i5 @ i40, rsd)) + +function clause execute (C_ANDI(imm, rsd)) = { + let rsd = creg2reg_bits(rsd) in + execute(ITYPE(EXTS(imm), rsd, rsd, RISCV_ANDI)) +} + +/* ****************************************************************** */ + +union clause ast = C_SUB : (cregbits, cregbits) + +function clause decodeCompressed (0b100 @ 0b0 @ 0b11 @ rsd : cregbits @ 0b00 @ rs2 : cregbits @ 0b01) = Some(C_SUB(rsd, rs2)) + +function clause execute (C_SUB(rsd, rs2)) = { + let rsd = creg2reg_bits(rsd) in + let rs2 = creg2reg_bits(rs2) in + execute(RTYPE(rs2, rsd, rsd, RISCV_SUB)) +} + +/* ****************************************************************** */ + +union clause ast = C_XOR : (cregbits, cregbits) + +function clause decodeCompressed (0b100 @ 0b0 @ 0b11 @ rsd : cregbits @ 0b01 @ rs2 : cregbits @ 0b01) = Some(C_XOR(rsd, rs2)) + +function clause execute (C_SUB(rsd, rs2)) = { + let rsd = creg2reg_bits(rsd) in + let rs2 = creg2reg_bits(rs2) in + execute(RTYPE(rs2, rsd, rsd, RISCV_XOR)) +} + +/* ****************************************************************** */ + +union clause ast = C_OR : (cregbits, cregbits) + +function clause decodeCompressed (0b100 @ 0b0 @ 0b11 @ rsd : cregbits @ 0b10 @ rs2 : cregbits @ 0b01) = Some(C_OR(rsd, rs2)) + +function clause execute (C_OR(rsd, rs2)) = { + let rsd = creg2reg_bits(rsd) in + let rs2 = creg2reg_bits(rs2) in + execute(RTYPE(rs2, rsd, rsd, RISCV_OR)) +} + +/* ****************************************************************** */ + +union clause ast = C_AND : (cregbits, cregbits) + +function clause decodeCompressed (0b100 @ 0b0 @ 0b11 @ rsd : cregbits @ 0b11 @ rs2 : cregbits @ 0b01) = Some(C_AND(rsd, rs2)) + +function clause execute (C_OR(rsd, rs2)) = { + let rsd = creg2reg_bits(rsd) in + let rs2 = creg2reg_bits(rs2) in + execute(RTYPE(rs2, rsd, rsd, RISCV_OR)) +} + +/* ****************************************************************** */ + +union clause ast = C_SUBW : (cregbits, cregbits) + +/* TODO: invalid on RV32 */ +function clause decodeCompressed (0b100 @ 0b1 @ 0b11 @ rsd : cregbits @ 0b00 @ rs2 : cregbits @ 0b01) = Some(C_SUBW(rsd, rs2)) + +function clause execute (C_SUBW(rsd, rs2)) = { + let rsd = creg2reg_bits(rsd) in + let rs2 = creg2reg_bits(rs2) in + execute(RTYPE(rs2, rsd, rsd, RISCV_SUB)) +} + +/* ****************************************************************** */ + +union clause ast = C_ADDW : (cregbits, cregbits) + +/* TODO: invalid on RV32 */ +function clause decodeCompressed (0b100 @ 0b1 @ 0b11 @ rsd : cregbits @ 0b01 @ rs2 : cregbits @ 0b01) = Some(C_ADDW(rsd, rs2)) + +function clause execute (C_ADDW(rsd, rs2)) = { + let rsd = creg2reg_bits(rsd) in + let rs2 = creg2reg_bits(rs2) in + execute(RTYPE(rs2, rsd, rsd, RISCV_ADD)) +} + +/* ****************************************************************** */ + +union clause ast = C_J : (bits(11)) + +function clause decodeCompressed (0b101 @ i11 : bits(1) @ i4 : bits(1) @ i98 : bits(2) @ i10 : bits(1) @ i6 : bits(1) @ i7 : bits(1) @ i31 : bits(3) @ i5 : bits(1) @ 0b01) = + Some(C_J(i11 @ i10 @ i98 @ i7 @ i6 @ i5 @ i4 @ i31)) + +function clause execute (C_J(imm)) = + execute(RISCV_JAL(EXTS(imm @ 0b0), zreg)) + +/* ****************************************************************** */ + +union clause ast = C_BEQZ : (bits(8), cregbits) + +function clause decodeCompressed (0b110 @ i8 : bits(1) @ i43 : bits(2) @ rs : cregbits @ i76 : bits(2) @ i21 : bits(2) @ i5 : bits(1) @ 0b01) = + Some(C_BEQZ(i8 @ i76 @ i5 @ i43 @ i21, rs)) + +function clause execute (C_BEQZ(imm, rs)) = + execute(BTYPE(EXTS(imm @ 0b0), zreg, creg2reg_bits(rs), RISCV_BEQ)) + +/* ****************************************************************** */ + +union clause ast = C_BNEZ : (bits(8), cregbits) + +function clause decodeCompressed (0b111 @ i8 : bits(1) @ i43 : bits(2) @ rs : cregbits @ i76 : bits(2) @ i21 : bits(2) @ i5 : bits(1) @ 0b01) = + Some(C_BNEZ(i8 @ i76 @ i5 @ i43 @ i21, rs)) + +function clause execute (C_BNEZ(imm, rs)) = + execute(BTYPE(EXTS(imm @ 0b0), zreg, creg2reg_bits(rs), RISCV_BNE)) + +/* ****************************************************************** */ + function clause decode _ = None +function clause decodeCompressed _ = None end ast end decode +end decodeCompressed end execute diff --git a/riscv/riscv_duopod.sail b/riscv/riscv_duopod.sail new file mode 100644 index 00000000..e0eaf949 --- /dev/null +++ b/riscv/riscv_duopod.sail @@ -0,0 +1,82 @@ + +type xlen = atom(64) +type xlen_t = bits(64) + +type regno ('n : Int), 0 <= 'n < 32 = atom('n) +type regbits = bits(5) + +val cast regbits_to_regno : bits(5) -> {'n, 0 <= 'n < 32. regno('n)} +function regbits_to_regno b = let 'r = unsigned(b) in r + +/* Architectural state */ + +register PC : xlen_t +register nextPC : xlen_t + +register Xs : vector(32, dec, xlen_t) + +/* Getters and setters for X registers (special case for zeros register, x0) */ +val rX : forall 'n, 0 <= 'n < 32. regno('n) -> xlen_t effect {rreg} + +function rX 0 = 0x0000000000000000 +and rX (r if r > 0) = Xs[r] + +val wX : forall 'n, 0 <= 'n < 32. (regno('n), xlen_t) -> unit effect {wreg} + +function wX (r, v) = + if (r != 0) then { + Xs[r] = v; + } + +overload X = {rX, wX} + +/* Accessors for memory */ + +val MEMr : forall 'n. (xlen_t, atom('n)) -> bits(8 * 'n) effect {rmem} +function MEMr (addr, width) = __RISCV_read(addr, width) + +/* Instruction decode and execute */ +enum iop = {RISCV_ADDI, RISCV_SLTI, RISCV_SLTIU, RISCV_XORI, RISCV_ORI, RISCV_ANDI} /* immediate ops */ +scattered union ast + +val decode : bits(32) -> option(ast) effect pure +scattered function decode + +val execute : ast -> unit effect {rmem, rreg, wreg} +scattered function execute + +/* ****************************************************************** */ + +/* ADDI */ + +union clause ast = ITYPE : (bits(12), regbits, regbits, iop) + +function clause decode imm : bits(12) @ rs1 : regbits @ 0b000 @ rd : regbits @ 0b0010011 + = Some(ITYPE(imm, rs1, rd, RISCV_ADDI)) + +function clause execute (ITYPE (imm, rs1, rd, RISCV_ADDI)) = + let rs1_val = X(rs1) in + let imm_ext : xlen_t = EXTS(imm) in + let result = rs1_val + imm_ext in + X(rd) = result + +/* ****************************************************************** */ + +/* Load double */ +union clause ast = LOAD : (bits(12), regbits, regbits) + +function clause decode imm : bits(12) @ rs1 : regbits @ 0b011 @ rd : regbits @ 0b0000011 + = Some(LOAD(imm, rs1, rd)) + +function clause execute(LOAD(imm, rs1, rd)) = + let addr : xlen_t = X(rs1) + EXTS(imm) in + let result : xlen_t = MEMr(addr, 8) in + X(rd) = result + +/* ****************************************************************** */ + +function clause decode _ = None + +end ast +end decode +end execute diff --git a/riscv/riscv_extras_embed_sequential.lem b/riscv/riscv_extras_embed_sequential.lem index 044b2aa3..4ef3ed36 100644 --- a/riscv/riscv_extras_embed_sequential.lem +++ b/riscv/riscv_extras_embed_sequential.lem @@ -2,8 +2,11 @@ open import Pervasives open import Pervasives_extra open import Sail_impl_base open import Sail_values -open import Sail_operators +open import Sail_operators_mwords open import State +open import State_monad + +type bitvector 'a = mword 'a let MEM_fence_rw_rw () = barrier Barrier_RISCV_rw_rw let MEM_fence_r_rw () = barrier Barrier_RISCV_r_rw @@ -12,6 +15,13 @@ let MEM_fence_rw_w () = barrier Barrier_RISCV_rw_w let MEM_fence_w_w () = barrier Barrier_RISCV_w_w let MEM_fence_i () = barrier Barrier_RISCV_i +val MEMea : forall 'r 'a 'e. Size 'a => bitvector 'a -> integer -> M 'r unit 'e +val MEMea_release : forall 'r 'a 'e. Size 'a => bitvector 'a -> integer -> M 'r unit 'e +val MEMea_strong_release : forall 'r 'a 'e. Size 'a => bitvector 'a -> integer -> M 'r unit 'e +val MEMea_conditional : forall 'r 'a 'e. Size 'a => bitvector 'a -> integer -> M 'r unit 'e +val MEMea_conditional_release : forall 'r 'a 'e. Size 'a => bitvector 'a -> integer -> M 'r unit 'e +val MEMea_conditional_strong_release : forall 'r 'a 'e. Size 'a => bitvector 'a -> integer -> M 'r unit 'e + let MEMea addr size = write_mem_ea Write_plain addr size let MEMea_release addr size = write_mem_ea Write_RISCV_release addr size let MEMea_strong_release addr size = write_mem_ea Write_RISCV_strong_release addr size @@ -20,26 +30,35 @@ let MEMea_conditional_release addr size = write_mem_ea Write_RISCV_conditional_ let MEMea_conditional_strong_release addr size = write_mem_ea Write_RISCV_conditional_strong_release addr size +val write_ram : forall 'a 'b 'r 'e. Size 'a, Size 'b => + integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> M 'r unit 'e let write_ram addrsize size hexRAM address value = write_mem_ea Write_plain address size >> write_mem_val value >>= fun _ -> return () +val read_ram : forall 'a 'b 'r 'e. Size 'a, Size 'b => + integer -> integer -> bitvector 'a -> bitvector 'a -> M 'r (bitvector 'b) 'e let read_ram addrsize size hexRAM address = read_mem Read_plain address size let speculate_conditional_success () = excl_result () +val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> bitvector 'a let get_slice_int len n lo = (* TODO: Is this the intended behaviour? *) let hi = lo + len - 1 in let bits = bits_of_int (hi + 1) n in of_bits (get_bits false bits hi lo) +val sign_extend : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> integer -> bitvector 'b let sign_extend v len = exts_vec len v +val zero_extend : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> integer -> bitvector 'b let zero_extend v len = extz_vec len v +val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a let shift_bits_right v m = shiftr v (unsigned m) +val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a let shift_bits_left v m = shiftl v (unsigned m) val prerr_endline : string -> unit @@ -49,7 +68,7 @@ declare ocaml target_rep function prerr_endline = `prerr_endline` val print_int : string -> integer -> unit let print_int msg i = prerr_endline (msg ^ (stringFromInteger i)) -val print_bits : forall 'a. Bitvector 'a => string -> 'a -> unit +val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit let print_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs))) val putchar : integer -> unit diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail index 0eaadec4..68ef7a55 100644 --- a/riscv/riscv_sys.sail +++ b/riscv/riscv_sys.sail @@ -68,6 +68,38 @@ function exc_to_bits e = /* FIXME: currently we have only those used by riscv-tests. */ +bitfield Misa : bits(64) = { + MXL : 63 .. 62, + + Z : 25, + Y : 24, + X : 23, + W : 22, + V : 21, + U : 20, + T : 19, + S : 18, + R : 17, + Q : 16, + P : 15, + O : 14, + N : 13, + M : 12, + L : 11, + K : 10, + J : 9, + I : 8, + H : 7, + G : 6, + F : 5, + E : 4, + D : 3, + C : 2, + B : 1, + A : 0 +} +register misa : Misa + bitfield Mstatus : bits(64) = { SD : 63, @@ -180,7 +212,7 @@ register mhartid : regval struct sync_exception = { trap : ExceptionCode, - badaddr : option(regval) + excinfo : option(regval) } union ctl_result = { @@ -228,19 +260,19 @@ function handle_exception_ctl(cur_priv : privilege, ctl : ctl_result, match (e.trap) { Misaligned_Fetch => { - match (e.badaddr) { + match (e.excinfo) { Some(a) => mtval = a, None => throw(Error_internal_error) } }, Fetch_Access => { - match (e.badaddr) { + match (e.excinfo) { Some(a) => mtval = a, None => throw(Error_internal_error) } }, Illegal_Instr => { - match (e.badaddr) { + match (e.excinfo) { Some(a) => mtval = a, None => throw(Error_internal_error) } @@ -249,25 +281,25 @@ function handle_exception_ctl(cur_priv : privilege, ctl : ctl_result, Breakpoint => not_implemented("breakpoint"), Misaligned_Load => { - match (e.badaddr) { + match (e.excinfo) { Some(a) => mtval = a, None => throw(Error_internal_error) } }, Load_Access => { - match (e.badaddr) { + match (e.excinfo) { Some(a) => mtval = a, None => throw(Error_internal_error) } }, Misaligned_Store => { - match (e.badaddr) { + match (e.excinfo) { Some(a) => mtval = a, None => throw(Error_internal_error) } }, Store_Access => { - match (e.badaddr) { + match (e.excinfo) { Some(a) => mtval = a, None => throw(Error_internal_error) } @@ -284,23 +316,24 @@ function handle_exception_ctl(cur_priv : privilege, ctl : ctl_result, }, Fetch_PageFault => { - match (e.badaddr) { + match (e.excinfo) { Some(a) => mtval = a, None => throw(Error_internal_error) } }, Load_PageFault => { - match (e.badaddr) { + match (e.excinfo) { Some(a) => mtval = a, None => throw(Error_internal_error) } }, Store_PageFault => { - match (e.badaddr) { + match (e.excinfo) { Some(a) => mtval = a, None => throw(Error_internal_error) } - } + }, + _ => throw(Error_internal_error) /* Don't expect ReservedExc0 etc. here */ }; /* TODO: make register read explicit */ mtvec diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail index e627518d..477b4902 100644 --- a/riscv/riscv_types.sail +++ b/riscv/riscv_types.sail @@ -12,10 +12,14 @@ type regval = bits(64) type regno ('n : Int), 0 <= 'n < 32 = atom('n) type regbits = bits(5) +type cregbits = bits(3) val cast regbits_to_regno : bits(5) -> {'n, 0 <= 'n < 32. regno('n)} function regbits_to_regno b = let 'r = unsigned(b) in r +val creg2reg_bits : cregbits -> regbits +function creg2reg_bits(creg) = 0b10 @ creg + /* register x0 : regval is hard-wired zero */ register x1 : regval register x2 : regval @@ -49,6 +53,11 @@ register x29 : regval register x30 : regval register x31 : regval +/* some arch and ABI relevant registers */ +let zreg : regbits = 0b00000 +let ra : regbits = 0b00001 /* x1 */ +let sp : regbits = 0b00010 /* x2 */ + register PC : bits(64) register nextPC : bits(64) @@ -75,8 +84,7 @@ val wGPR : forall 'n, 0 <= 'n < 32. (regno('n), regval) -> unit effect {wreg} function wGPR (r, v) = if (r != 0) then { (*GPRs[r - 1]) = v; - print_int("GPR ", r); - print_bits("<- ", v); + print_string("x", concat_str(string_of_int(r), concat_str(" <- ", BitStr(v)))); } function check_alignment (addr : bits(64), width : atom('n)) -> forall 'n. unit = diff --git a/src/ast_util.ml b/src/ast_util.ml index 3f13e6ad..546faf14 100644 --- a/src/ast_util.ml +++ b/src/ast_util.ml @@ -193,6 +193,10 @@ let rec is_nexp_constant (Nexp_aux (nexp, _)) = match nexp with let rec nexp_simp (Nexp_aux (nexp, l)) = Nexp_aux (nexp_simp_aux nexp, l) and nexp_simp_aux = function + (* (n - (n - m)) often appears in foreach loops *) + | Nexp_minus (nexp1, Nexp_aux (Nexp_minus (nexp2, Nexp_aux (n3,_)),_)) + when nexp_identical nexp1 nexp2 -> + nexp_simp_aux n3 | Nexp_minus (Nexp_aux (Nexp_sum (Nexp_aux (n1, _), nexp2), _), nexp3) when nexp_identical nexp2 nexp3 -> nexp_simp_aux n1 diff --git a/src/c_backend.ml b/src/c_backend.ml index b06cd950..42932285 100644 --- a/src/c_backend.ml +++ b/src/c_backend.ml @@ -61,28 +61,9 @@ let zencode_id = function let lvar_typ = function | Local (_, typ) -> typ | Register typ -> typ + | Enum typ -> typ | _ -> assert false -(* - -1) Conversion to ANF - - tannot defs -> (typ, aexp) cdefs - -2) Primitive operation optimizations - -3) Lowering to low-level imperative language - - (typ, aexp) cdefs -> (ctyp, instr list) cdefs - -4) Low level optimizations (e.g. reducing allocations) - -5) Generation of C code - - (ctyp, instr list) -> string - -*) - (**************************************************************************) (* 1. Conversion to A-normal form (ANF) *) (**************************************************************************) @@ -121,16 +102,25 @@ type aexp = | AE_let of id * typ * aexp * aexp * typ | AE_block of aexp list * aexp * typ | AE_return of aval * typ - | AE_throw of aval | AE_if of aval * aexp * aexp * typ + | AE_field of aval * id * typ + | AE_case of aval * (apat * aexp * aexp) list * typ + | AE_record_update of aval * aval Bindings.t * typ | AE_for of id * aexp * aexp * aexp * order * aexp | AE_loop of loop * aexp * aexp +and apat = + | AP_tup of apat list + | AP_id of id + | AP_wild + and aval = | AV_lit of lit * typ | AV_id of id * lvar | AV_ref of id * lvar | AV_tuple of aval list + | AV_list of aval list * typ + | AV_vector of aval list * typ | AV_C_fragment of string * typ (* Map over all the avals in an aexp. *) @@ -145,6 +135,15 @@ let rec map_aval f = function | AE_return (aval, typ) -> AE_return (f aval, typ) | AE_if (aval, aexp1, aexp2, typ2) -> AE_if (f aval, map_aval f aexp1, map_aval f aexp2, typ2) + | AE_loop (loop_typ, aexp1, aexp2) -> AE_loop (loop_typ, map_aval f aexp1, map_aval f aexp2) + | AE_for (id, aexp1, aexp2, aexp3, order, aexp4) -> + AE_for (id, map_aval f aexp1, map_aval f aexp2, map_aval f aexp3, order, map_aval f aexp4) + | AE_record_update (aval, updates, typ) -> + AE_record_update (f aval, Bindings.map f updates, typ) + | AE_field (aval, id, typ) -> + AE_field (f aval, id, typ) + | AE_case (aval, cases, typ) -> + AE_case (f aval, List.map (fun (pat, aexp1, aexp2) -> pat, map_aval f aexp1, map_aval f aexp2) cases, typ) (* Map over all the functions in an aexp. *) let rec map_functions f = function @@ -155,10 +154,15 @@ let rec map_functions f = function | AE_block (aexps, aexp, typ) -> AE_block (List.map (map_functions f) aexps, map_functions f aexp, typ) | AE_if (aval, aexp1, aexp2, typ) -> AE_if (aval, map_functions f aexp1, map_functions f aexp2, typ) - | AE_val _ | AE_return _ as v -> v + | AE_loop (loop_typ, aexp1, aexp2) -> AE_loop (loop_typ, map_functions f aexp1, map_functions f aexp2) + | AE_for (id, aexp1, aexp2, aexp3, order, aexp4) -> + AE_for (id, map_functions f aexp1, map_functions f aexp2, map_functions f aexp3, order, map_functions f aexp4) + | AE_case (aval, cases, typ) -> + AE_case (aval, List.map (fun (pat, aexp1, aexp2) -> pat, map_functions f aexp1, map_functions f aexp2) cases, typ) + | AE_field _ | AE_record_update _ | AE_val _ | AE_return _ as v -> v (* For debugging we provide a pretty printer for ANF expressions. *) - + let pp_id ?color:(color=Util.green) id = string (string_of_id id |> color |> Util.clear) @@ -179,6 +183,11 @@ let pp_lvar lvar doc = let pp_annot typ doc = string "[" ^^ string (string_of_typ typ |> Util.yellow |> Util.clear) ^^ string "]" ^^ doc +let pp_order = function + | Ord_aux (Ord_inc, _) -> string "inc" + | Ord_aux (Ord_dec, _) -> string "dec" + | _ -> assert false (* Order types have been specialised, so no polymorphism in C backend. *) + let rec pp_aexp = function | AE_val v -> pp_aval v | AE_cast (aexp, typ) -> @@ -205,6 +214,35 @@ let rec pp_aexp = function | AE_block (aexps, aexp, typ) -> pp_annot typ (surround 2 0 lbrace (pp_block (aexps @ [aexp])) rbrace) | AE_return (v, typ) -> pp_annot typ (string "return" ^^ parens (pp_aval v)) + | AE_loop (While, aexp1, aexp2) -> + separate space [string "while"; pp_aexp aexp1; string "do"; pp_aexp aexp2] + | AE_loop (Until, aexp1, aexp2) -> + separate space [string "repeat"; pp_aexp aexp2; string "until"; pp_aexp aexp1] + | AE_for (id, aexp1, aexp2, aexp3, order, aexp4) -> + let header = + string "foreach" ^^ space ^^ + group (parens (separate (break 1) + [ pp_id id; + string "from " ^^ pp_aexp aexp1; + string "to " ^^ pp_aexp aexp2; + string "by " ^^ pp_aexp aexp3; + string "in " ^^ pp_order order ])) + in + header ^//^ pp_aexp aexp4 + | AE_field _ -> string "FIELD" + | AE_case (aval, cases, typ) -> + pp_annot typ (separate space [string "match"; pp_aval aval; pp_cases cases]) + | AE_record_update (_, _, typ) -> pp_annot typ (string "RECORD UPDATE") + +and pp_apat = function + | AP_wild -> string "_" + | AP_id id -> pp_id id + | AP_tup apats -> parens (separate_map (comma ^^ space) pp_apat apats) + +and pp_cases cases = surround 2 0 lbrace (separate_map (comma ^^ hardline) pp_case cases) rbrace + +and pp_case (apat, guard, body) = + separate space [pp_apat apat; string "if"; pp_aexp guard; string "=>"; pp_aexp body] and pp_block = function | [] -> string "()" @@ -215,14 +253,22 @@ and pp_aval = function | AV_lit (lit, typ) -> pp_annot typ (string (string_of_lit lit)) | AV_id (id, lvar) -> pp_lvar lvar (pp_id id) | AV_tuple avals -> parens (separate_map (comma ^^ space) pp_aval avals) + | AV_ref (id, lvar) -> string "ref" ^^ space ^^ pp_lvar lvar (pp_id id) | AV_C_fragment (str, typ) -> pp_annot typ (string (str |> Util.cyan |> Util.clear)) + | AV_vector (avals, typ) -> + pp_annot typ (string "[" ^^ separate_map (comma ^^ space) pp_aval avals ^^ string "]") + | AV_list (avals, typ) -> + pp_annot typ (string "[|" ^^ separate_map (comma ^^ space) pp_aval avals ^^ string "|]") let ae_lit lit typ = AE_val (AV_lit (lit, typ)) +(** GLOBAL: gensym_counter is used to generate fresh identifiers where + needed. It should be safe to reset between top level + definitions. **) let gensym_counter = ref 0 let gensym () = - let id = mk_id ("v" ^ string_of_int !gensym_counter) in + let id = mk_id ("gs#" ^ string_of_int !gensym_counter) in incr gensym_counter; id @@ -233,12 +279,30 @@ let rec split_block = function exp :: exps, last | [] -> failwith "empty block" +let rec anf_pat (P_aux (p_aux, _) as pat) = + match p_aux with + | P_id id -> AP_id id + | P_wild -> AP_wild + | P_tup pats -> AP_tup (List.map anf_pat pats) + | _ -> assert false + let rec anf (E_aux (e_aux, exp_annot) as exp) = let to_aval = function | AE_val v -> (v, fun x -> x) - | AE_app (_, _, typ) | AE_let (_, _, _, _, typ) | AE_return (_, typ) | AE_cast (_, typ) as aexp -> + | AE_app (_, _, typ) + | AE_let (_, _, _, _, typ) + | AE_return (_, typ) + | AE_cast (_, typ) + | AE_if (_, _, _, typ) + | AE_field (_, _, typ) + | AE_case (_, _, typ) + | AE_record_update (_, _, typ) + as aexp -> let id = gensym () in (AV_id (id, Local (Immutable, typ)), fun x -> AE_let (id, typ, aexp, x, typ_of exp)) + | AE_assign _ | AE_block _ | AE_for _ | AE_loop _ as aexp -> + let id = gensym () in + (AV_id (id, Local (Immutable, unit_typ)), fun x -> AE_let (id, unit_typ, aexp, x, typ_of exp)) in match e_aux with | E_lit lit -> ae_lit lit (typ_of exp) @@ -253,6 +317,15 @@ let rec anf (E_aux (e_aux, exp_annot) as exp) = let aexp = anf exp in AE_assign (id, lvar_typ (Env.lookup_id id (env_of exp)), aexp) + | E_loop (loop_typ, cond, exp) -> + let acond = anf cond in + let aexp = anf exp in + AE_loop (loop_typ, acond, aexp) + + | E_for (id, exp1, exp2, exp3, order, body) -> + let aexp1, aexp2, aexp3, abody = anf exp1, anf exp2, anf exp3, anf body in + AE_for (id, aexp1, aexp2, aexp3, order, abody) + | E_if (cond, then_exp, else_exp) -> let cond_val, wrap = to_aval (anf cond) in let then_aexp = anf then_exp in @@ -263,7 +336,34 @@ let rec anf (E_aux (e_aux, exp_annot) as exp) = anf (E_aux (E_app (Id_aux (DeIid op, l), [x; y]), exp_annot)) | E_app_infix (x, Id_aux (DeIid op, l), y) -> anf (E_aux (E_app (Id_aux (Id op, l), [x; y]), exp_annot)) - + + | E_vector exps -> + let aexps = List.map anf exps in + let avals = List.map to_aval aexps in + let wrap = List.fold_left (fun f g x -> f (g x)) (fun x -> x) (List.map snd avals) in + wrap (AE_val (AV_vector (List.map fst avals, typ_of exp))) + + | E_list exps -> + let aexps = List.map anf exps in + let avals = List.map to_aval aexps in + let wrap = List.fold_left (fun f g x -> f (g x)) (fun x -> x) (List.map snd avals) in + wrap (AE_val (AV_list (List.map fst avals, typ_of exp))) + + | E_field (exp, id) -> + let aval, wrap = to_aval (anf exp) in + wrap (AE_field (aval, id, typ_of exp)) + + | E_record_update (exp, FES_aux (FES_Fexps (fexps, _), _)) -> + let anf_fexp (FE_aux (FE_Fexp (id, exp), _)) = + let aval, wrap = to_aval (anf exp) in + (id, aval), wrap + in + let aval, exp_wrap = to_aval (anf exp) in + let fexps = List.map anf_fexp fexps in + let wrap = List.fold_left (fun f g x -> f (g x)) (fun x -> x) (List.map snd fexps) in + let record = List.fold_left (fun r (id, aval) -> Bindings.add id aval r) Bindings.empty (List.map fst fexps) in + exp_wrap (wrap (AE_record_update (aval, record, typ_of exp))) + | E_app (id, exps) -> let aexps = List.map anf exps in let avals = List.map to_aval aexps in @@ -301,17 +401,36 @@ let rec anf (E_aux (e_aux, exp_annot) as exp) = | E_id id -> let lvar = Env.lookup_id id (env_of exp) in - AE_val (AV_id (zencode_id id, lvar)) + AE_val (AV_id (id, lvar)) + + | E_ref id -> + let lvar = Env.lookup_id id (env_of exp) in + AE_val (AV_ref (id, lvar)) | E_return exp -> let aval, wrap = to_aval (anf exp) in wrap (AE_return (aval, typ_of exp)) + | E_case (match_exp, pexps) -> + let match_aval, match_wrap = to_aval (anf match_exp) in + let anf_pexp (Pat_aux (pat_aux, _)) = + match pat_aux with + | Pat_when (pat, guard, body) -> + (anf_pat pat, anf guard, anf body) + | Pat_exp (pat, body) -> + (anf_pat pat, AE_val (AV_lit (mk_lit (L_true), bool_typ)), anf body) + in + match_wrap (AE_case (match_aval, List.map anf_pexp pexps, typ_of exp)) + | E_var (LEXP_aux (LEXP_id id, _), binding, body) + | E_var (LEXP_aux (LEXP_cast (_, id), _), binding, body) | E_let (LB_aux (LB_val (P_aux (P_id id, _), binding), _), body) -> let env = env_of body in let lvar = Env.lookup_id id env in - AE_let (zencode_id id, lvar_typ lvar, anf binding, anf body, typ_of exp) + AE_let (id, lvar_typ lvar, anf binding, anf body, typ_of exp) + + | E_let (LB_aux (LB_val (pat, binding), _), body) -> + anf (E_aux (E_case (binding, [Pat_aux (Pat_exp (pat, body), (Parse_ast.Unknown, None))]), exp_annot)) | E_tuple exps -> let aexps = List.map anf exps in @@ -339,10 +458,8 @@ let rec anf (E_aux (e_aux, exp_annot) as exp) = | E_nondet _ -> (* We don't compile E_nondet nodes *) failwith "encountered E_nondet node when converting to ANF" - - (* + | _ -> failwith ("Cannot convert to ANF: " ^ string_of_exp exp) - *) (**************************************************************************) (* 2. Converting sail types to C types *) @@ -375,8 +492,23 @@ type ctyp = | CT_struct of id * ctyp Bindings.t | CT_enum of id * IdSet.t | CT_variant of id * ctyp Bindings.t - -let ctyp_equal ctyp1 ctyp2 = + | CT_string + +type ctx = + { records : (ctyp Bindings.t) Bindings.t; + enums : IdSet.t Bindings.t; + variants : (ctyp Bindings.t) Bindings.t; + tc_env : Env.t + } + +let initial_ctx env = + { records = Bindings.empty; + enums = Bindings.empty; + variants = Bindings.empty; + tc_env = env + } + +let rec ctyp_equal ctyp1 ctyp2 = match ctyp1, ctyp2 with | CT_mpz, CT_mpz -> true | CT_bv d1, CT_bv d2 -> d1 = d2 @@ -385,9 +517,14 @@ let ctyp_equal ctyp1 ctyp2 = | CT_int64, CT_int64 -> true | CT_unit, CT_unit -> true | CT_bool, CT_bool -> true + | CT_struct (id1, _), CT_struct (id2, _) -> Id.compare id1 id2 = 0 + | CT_enum (id1, _), CT_enum (id2, _) -> Id.compare id1 id2 = 0 + | CT_variant (id1, _), CT_variant (id2, _) -> Id.compare id1 id2 = 0 + | CT_tup ctyps1, CT_tup ctyps2 -> List.for_all2 ctyp_equal ctyps1 ctyps2 + | CT_string, CT_string -> true | _, _ -> false -let string_of_ctyp = function +let rec string_of_ctyp = function | CT_mpz -> "mpz_t" | CT_bv true -> "bv_t<dec>" | CT_bv false -> "bv_t<inc>" @@ -397,9 +534,12 @@ let string_of_ctyp = function | CT_int -> "int" | CT_unit -> "unit" | CT_bool -> "bool" + | CT_tup ctyps -> "(" ^ Util.string_of_list ", " string_of_ctyp ctyps ^ ")" + | CT_struct (id, _) | CT_enum (id, _) | CT_variant (id, _) -> string_of_id id + | CT_string -> "string" (* Convert a sail type into a C-type *) -let ctyp_of_typ (Typ_aux (typ_aux, _) as typ) = +let rec ctyp_of_typ ctx (Typ_aux (typ_aux, _) as typ) = match typ_aux with | Typ_id id when string_of_id id = "bit" -> CT_int | Typ_id id when string_of_id id = "bool" -> CT_bool @@ -426,13 +566,24 @@ let ctyp_of_typ (Typ_aux (typ_aux, _) as typ) = | _ -> CT_bv direction end | Typ_id id when string_of_id id = "unit" -> CT_unit + | Typ_id id when string_of_id id = "string" -> CT_string + + | Typ_id id when Bindings.mem id ctx.records -> CT_struct (id, Bindings.find id ctx.records) + | Typ_id id when Bindings.mem id ctx.enums -> CT_enum (id, Bindings.find id ctx.enums) + | Typ_id id when Bindings.mem id ctx.variants -> CT_variant (id, Bindings.find id ctx.variants) + + | Typ_tup typs -> CT_tup (List.map (ctyp_of_typ ctx) typs) + | _ -> failwith ("No C-type for type " ^ string_of_typ typ) -let is_stack_ctyp ctyp = match ctyp with - | CT_uint64 _ | CT_int64 | CT_int | CT_unit | CT_bool -> true - | CT_bv _ | CT_mpz -> false +let rec is_stack_ctyp ctyp = match ctyp with + | CT_uint64 _ | CT_int64 | CT_int | CT_unit | CT_bool | CT_enum _ -> true + | CT_bv _ | CT_mpz | CT_string _ -> false + | CT_struct (_, fields) -> Bindings.for_all (fun _ ctyp -> is_stack_ctyp ctyp) fields + | CT_variant (_, ctors) -> Bindings.for_all (fun _ ctyp -> is_stack_ctyp ctyp) ctors + | CT_tup ctyps -> List.for_all is_stack_ctyp ctyps -let is_stack_typ typ = is_stack_ctyp (ctyp_of_typ typ) +let is_stack_typ ctx typ = is_stack_ctyp (ctyp_of_typ ctx typ) (**************************************************************************) (* 3. Optimization of primitives and literals *) @@ -445,19 +596,20 @@ let literal_to_cstring (L_aux (l_aux, _) as lit) = | L_hex str when String.length str <= 16 -> let padding = 16 - String.length str in Some ("0x" ^ String.make padding '0' ^ str ^ "ul") - | L_unit -> Some "0" + | L_unit -> Some "UNIT" | L_true -> Some "true" | L_false -> Some "false" | _ -> None -let c_literals = - let c_literal = function - | AV_lit (lit, typ) as v when is_stack_ctyp (ctyp_of_typ typ) -> +let c_literals ctx = + let rec c_literal = function + | AV_lit (lit, typ) as v when is_stack_ctyp (ctyp_of_typ ctx typ) -> begin match literal_to_cstring lit with | Some str -> AV_C_fragment (str, typ) | None -> v end + | AV_tuple avals -> AV_tuple (List.map c_literal avals) | v -> v in map_aval c_literal @@ -471,7 +623,7 @@ let mask m = else failwith "Tried to create a mask literal for a vector greater than 64 bits." -let c_aval = function +let rec c_aval ctx = function | AV_lit (lit, typ) as v -> begin match literal_to_cstring lit with @@ -483,11 +635,11 @@ let c_aval = function | AV_id (id, lvar) as v -> begin match lvar with - | Local (_, typ) when is_stack_typ typ -> - AV_C_fragment (string_of_id id, typ) + | Local (_, typ) when is_stack_typ ctx typ -> + AV_C_fragment (Util.zencode_string (string_of_id id), typ) | _ -> v end - | AV_tuple avals -> AV_tuple avals + | AV_tuple avals -> AV_tuple (List.map (c_aval ctx) avals) let is_c_fragment = function | AV_C_fragment _ -> true @@ -497,12 +649,13 @@ let c_fragment_string = function | AV_C_fragment (str, _) -> str | _ -> assert false -let analyze_primop' id args typ = +let analyze_primop' ctx id args typ = let no_change = AE_app (id, args, typ) in (* primops add_range and add_atom *) if string_of_id id = "add_range" || string_of_id id = "add_atom" then begin + prerr_endline "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; let n, m, x, y = match destruct_range typ, args with | Some (n, m), [x; y] -> n, m, x, y | _ -> failwith ("add_range has incorrect return type or arity ^ " ^ string_of_typ typ) @@ -510,16 +663,27 @@ let analyze_primop' id args typ = match nexp_simp n, nexp_simp m with | Nexp_aux (Nexp_constant n, _), Nexp_aux (Nexp_constant m, _) -> if Big_int.less_equal min_int64 n && Big_int.less_equal m max_int64 then - let x, y = c_aval x, c_aval y in + let x, y = c_aval ctx x, c_aval ctx y in if is_c_fragment x && is_c_fragment y then AE_val (AV_C_fragment (c_fragment_string x ^ " + " ^ c_fragment_string y, typ)) else - no_change + (print_endline "QQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQ"; + no_change) else - no_change + (print_endline "YYYYYYYYYYYYYYYYYYYYYYYYYYYYYYY"; + no_change) | _ -> no_change end + else if string_of_id id = "eq_range" || string_of_id id = "eq_atom" then + begin + match List.map (c_aval ctx) args with + | [x; y] when is_c_fragment x && is_c_fragment y -> + AE_val (AV_C_fragment ("(" ^ c_fragment_string x ^ " == " ^ c_fragment_string y ^ ")", typ)) + | _ -> + no_change + end + else if string_of_id id = "xor_vec" then begin let n, x, y = match typ, args with @@ -529,7 +693,7 @@ let analyze_primop' id args typ = in match nexp_simp n with | Nexp_aux (Nexp_constant n, _) when Big_int.less_equal n (Big_int.of_int 64) -> - let x, y = c_aval x, c_aval y in + let x, y = c_aval ctx x, c_aval ctx y in if is_c_fragment x && is_c_fragment y then AE_val (AV_C_fragment (c_fragment_string x ^ " ^ " ^ c_fragment_string y, typ)) else @@ -546,7 +710,7 @@ let analyze_primop' id args typ = in match nexp_simp n with | Nexp_aux (Nexp_constant n, _) when Big_int.less_equal n (Big_int.of_int 64) -> - let x, y = c_aval x, c_aval y in + let x, y = c_aval ctx x, c_aval ctx y in if is_c_fragment x && is_c_fragment y then AE_val (AV_C_fragment ("(" ^ c_fragment_string x ^ " + " ^ c_fragment_string y ^ ") & " ^ mask n, typ)) else @@ -557,15 +721,46 @@ let analyze_primop' id args typ = else no_change -let analyze_primop id args typ = +let analyze_primop ctx id args typ = let no_change = AE_app (id, args, typ) in - try analyze_primop' id args typ with + try analyze_primop' ctx id args typ with | Failure _ -> no_change (**************************************************************************) (* 4. Conversion to low-level AST *) (**************************************************************************) +(** We now define a low-level AST that is only slightly abstracted + away from C. To be succint in comments we usually refer to this as + LLcode rather than low-level AST repeatedly. + + The general idea is ANF expressions are converted into lists of + instructions (type instr) where allocations and deallocations are + now made explicit. ANF values (aval) are mapped to the cval type, + which is even simpler still. Some things are still more abstract + than in C, so the type definitions follow the sail type definition + structure, just with typ (from ast.ml) replaced with + ctyp. Top-level declarations that have no meaning for the backend + are not included at this level. + + The convention used here is that functions of the form compile_X + compile the type X into types in this AST, so compile_aval maps + avals into cvals. Note that the return types for these functions + are often quite complex, and they usually return some tuple + containing setup instructions (to allocate memory for the + expression), cleanup instructions (to deallocate that memory) and + possibly typing information about what has been translated. **) + +type ctype_def = + | CTD_enum of id * IdSet.t + | CTD_record of id * ctyp Bindings.t + | CTD_variant of id * ctyp Bindings.t + +let ctype_def_ctyps = function + | CTD_enum _ -> [] + | CTD_record (_, fields) -> List.map snd (Bindings.bindings fields) + | CTD_variant (_, ctors) -> List.map snd (Bindings.bindings ctors) + type cval = | CV_id of id * ctyp | CV_C_fragment of string * ctyp @@ -574,21 +769,61 @@ let cval_ctyp = function | CV_id (_, ctyp) -> ctyp | CV_C_fragment (_, ctyp) -> ctyp +type clexp = + | CL_id of id + | CL_field of id * id + | CL_addr of clexp + type instr = | I_decl of ctyp * id | I_alloc of ctyp * id | I_init of ctyp * id * cval | I_if of cval * instr list * instr list * ctyp - | I_funcall of id * id * cval list * ctyp - | I_convert of id * ctyp * id * ctyp + | I_funcall of clexp * id * cval list * ctyp + | I_convert of clexp * ctyp * id * ctyp | I_assign of id * cval + | I_copy of clexp * cval | I_clear of ctyp * id - | I_return of id + | I_return of cval + | I_block of instr list | I_comment of string + | I_label of string + | I_goto of string + | I_raw of string + +let rec map_instrs f instr = + match instr with + | I_decl _ | I_alloc _ | I_init _ -> instr + | I_if (cval, instrs1, instrs2, ctyp) -> + I_if (cval, f (List.map (map_instrs f) instrs1), f (List.map (map_instrs f) instrs2), ctyp) + | I_funcall _ | I_convert _ | I_assign _ | I_copy _ | I_clear _ | I_return _ -> instr + | I_block instrs -> I_block (f (List.map (map_instrs f) instrs)) + | I_comment _ | I_label _ | I_goto _ | I_raw _ -> instr type cdef = | CDEF_reg_dec of ctyp * id - | CDEF_fundef of id * id list * instr list + | CDEF_fundef of id * id option * id list * instr list + | CDEF_type of ctype_def + +let rec instr_ctyps = function + | I_decl (ctyp, _) | I_alloc (ctyp, _) | I_clear (ctyp, _) -> [ctyp] + | I_init (ctyp, _, cval) -> [ctyp; cval_ctyp cval] + | I_if (cval, instrs1, instrs2, ctyp) -> + ctyp :: cval_ctyp cval :: List.concat (List.map instr_ctyps instrs1 @ List.map instr_ctyps instrs2) + | I_funcall (_, _, cvals, ctyp) -> + ctyp :: List.map cval_ctyp cvals + | I_convert (_, ctyp1, _, ctyp2) -> [ctyp1; ctyp2] + | I_assign (_, cval) | I_copy (_, cval) -> [cval_ctyp cval] + | I_block instrs -> List.concat (List.map instr_ctyps instrs) + | I_return cval -> [cval_ctyp cval] + | I_comment _ | I_label _ | I_goto _ | I_raw _ -> [] + +let cdef_ctyps = function + | CDEF_reg_dec (ctyp, _) -> [ctyp] + | CDEF_fundef (_, _, _, instrs) -> List.concat (List.map instr_ctyps instrs) + | CDEF_type tdef -> ctype_def_ctyps tdef + +(* For debugging we define a pretty printer for LLcode instructions *) let pp_ctyp ctyp = string (string_of_ctyp ctyp |> Util.yellow |> Util.clear) @@ -596,10 +831,15 @@ let pp_ctyp ctyp = let pp_keyword str = string ((str |> Util.red |> Util.clear) ^ "$") -and pp_cval = function +let pp_cval = function | CV_id (id, ctyp) -> parens (pp_ctyp ctyp) ^^ (pp_id id) | CV_C_fragment (str, ctyp) -> parens (pp_ctyp ctyp) ^^ (string (str |> Util.cyan |> Util.clear)) +let rec pp_clexp = function + | CL_id id -> pp_id id + | CL_field (id, field) -> pp_id id ^^ string "." ^^ pp_id field + | CL_addr clexp -> string "*" ^^ pp_clexp clexp + let rec pp_instr = function | I_decl (ctyp, id) -> parens (pp_ctyp ctyp) ^^ space ^^ pp_id id @@ -609,64 +849,116 @@ let rec pp_instr = function ^^ pp_keyword "IF" ^^ pp_cval cval ^^ pp_keyword "THEN" ^^ pp_if_block then_instrs ^^ pp_keyword "ELSE" ^^ pp_if_block else_instrs + | I_block instrs -> + surround 2 0 lbrace (separate_map hardline pp_instr instrs) rbrace | I_alloc (ctyp, id) -> pp_keyword "ALLOC" ^^ parens (pp_ctyp ctyp) ^^ space ^^ pp_id id | I_init (ctyp, id, cval) -> pp_keyword "INIT" ^^ pp_ctyp ctyp ^^ parens (pp_id id ^^ string ", " ^^ pp_cval cval) | I_funcall (x, f, args, ctyp2) -> - separate space [ pp_id x; string ":="; + separate space [ pp_clexp x; string ":="; pp_id ~color:Util.red f ^^ parens (separate_map (string ", ") pp_cval args); string "->"; pp_ctyp ctyp2 ] | I_convert (x, ctyp1, y, ctyp2) -> - separate space [ pp_id x; string ":="; + separate space [ pp_clexp x; string ":="; pp_keyword "CONVERT" ^^ pp_ctyp ctyp2 ^^ parens (pp_id y); string "->"; pp_ctyp ctyp1 ] | I_assign (id, cval) -> separate space [pp_id id; string ":="; pp_cval cval] + | I_copy (clexp, cval) -> + separate space [string "let"; pp_clexp clexp; string "="; pp_cval cval] | I_clear (ctyp, id) -> pp_keyword "CLEAR" ^^ pp_ctyp ctyp ^^ parens (pp_id id) - | I_return id -> - pp_keyword "RETURN" ^^ pp_id id + | I_return cval -> + pp_keyword "RETURN" ^^ pp_cval cval | I_comment str -> string ("// " ^ str) - -let compile_funcall env id args typ = + | I_label str -> + string (str ^ ":") + | I_goto str -> + pp_keyword "GOTO" ^^ string str + | I_raw str -> + pp_keyword "C" ^^ string str + +let is_ct_enum = function + | CT_enum _ -> true + | _ -> false + +let is_ct_tup = function + | CT_tup _ -> true + | _ -> false + +let rec compile_aval ctx = function + | AV_C_fragment (code, typ) -> + [], CV_C_fragment (code, ctyp_of_typ ctx typ), [] + + | AV_id (id, typ) -> + begin + match ctyp_of_typ ctx (lvar_typ typ) with + | CT_enum (_, elems) when IdSet.mem id elems -> + [], CV_C_fragment (Util.zencode_upper_string (string_of_id id), ctyp_of_typ ctx (lvar_typ typ)), [] + | _ -> + [], CV_id (id, ctyp_of_typ ctx (lvar_typ typ)), [] + end + + | AV_lit (L_aux (L_string str, _), typ) -> + [], CV_C_fragment ("\"" ^ str ^ "\"", ctyp_of_typ ctx typ), [] + + | AV_lit (L_aux (L_num n, _), typ) when Big_int.less_equal min_int64 n && Big_int.less_equal n max_int64 -> + let gs = gensym () in + [I_decl (CT_mpz, gs); + I_init (CT_mpz, gs, CV_C_fragment (Big_int.to_string n ^ "L", CT_int64))], + CV_id (gs, CT_mpz), + [I_clear (CT_mpz, gs)] + + | AV_lit (L_aux (L_num n, _), typ) -> + let gs = gensym () in + [ I_decl (CT_mpz, gs); + I_init (CT_mpz, gs, CV_C_fragment ("\"" ^ Big_int.to_string n ^ "\"", CT_string)) ], + CV_id (gs, CT_mpz), + [I_clear (CT_mpz, gs)] + + | AV_tuple avals -> + let elements = List.map (compile_aval ctx) avals in + let cvals = List.map (fun (_, cval, _) -> cval) elements in + let setup = List.concat (List.map (fun (setup, _, _) -> setup) elements) in + let cleanup = List.concat (List.rev (List.map (fun (_, _, cleanup) -> cleanup) elements)) in + let tup_ctyp = CT_tup (List.map cval_ctyp cvals) in + let gs = gensym () in + setup + @ [I_decl (tup_ctyp, gs)] + @ List.mapi (fun n cval -> I_copy (CL_field (gs, mk_id ("tup" ^ string_of_int n)), cval)) cvals, + CV_id (gs, CT_tup (List.map cval_ctyp cvals)), + cleanup + +let compile_funcall ctx id args typ = let setup = ref [] in let cleanup = ref [] in - let _, Typ_aux (fn_typ, _) = Env.get_val_spec id env in + let _, Typ_aux (fn_typ, _) = Env.get_val_spec id ctx.tc_env in let arg_typs, ret_typ = match fn_typ with | Typ_fn (Typ_aux (Typ_tup arg_typs, _), ret_typ, _) -> arg_typs, ret_typ | Typ_fn (arg_typ, ret_typ, _) -> [arg_typ], ret_typ | _ -> assert false in - let arg_ctyps, ret_ctyp = List.map ctyp_of_typ arg_typs, ctyp_of_typ ret_typ in - let final_ctyp = ctyp_of_typ typ in + let arg_ctyps, ret_ctyp = List.map (ctyp_of_typ ctx) arg_typs, ctyp_of_typ ctx ret_typ in + let final_ctyp = ctyp_of_typ ctx typ in let setup_arg ctyp aval = - match aval with - | AV_C_fragment (c, typ) -> - if is_stack_ctyp ctyp then - CV_C_fragment (c, ctyp_of_typ typ) - else - let gs = gensym () in - setup := I_decl (ctyp, gs) :: !setup; - setup := I_init (ctyp, gs, CV_C_fragment (c, ctyp_of_typ typ)) :: !setup; - cleanup := I_clear (ctyp, gs) :: !cleanup; - CV_id (gs, ctyp) - | AV_id (id, lvar) -> - let have_ctyp = ctyp_of_typ (lvar_typ lvar) in - if ctyp_equal ctyp have_ctyp then - CV_id (id, ctyp) - else if is_stack_ctyp have_ctyp && not (is_stack_ctyp ctyp) then - let gs = gensym () in - setup := I_decl (ctyp, gs) :: !setup; - setup := I_init (ctyp, gs, CV_id (id, have_ctyp)) :: !setup; - cleanup := I_clear (ctyp, gs) :: !cleanup; - CV_id (gs, ctyp) - else - CV_id (mk_id ("????" ^ string_of_ctyp (ctyp_of_typ (lvar_typ lvar))), ctyp) - | _ -> CV_id (mk_id "???", ctyp) + let arg_setup, cval, arg_cleanup = compile_aval ctx aval in + setup := List.rev arg_setup @ !setup; + cleanup := arg_cleanup @ !cleanup; + let have_ctyp = cval_ctyp cval in + if ctyp_equal ctyp have_ctyp then + cval + else if is_stack_ctyp have_ctyp && not (is_stack_ctyp ctyp) then + let gs = gensym () in + setup := I_decl (ctyp, gs) :: !setup; + setup := I_init (ctyp, gs, cval) :: !setup; + cleanup := I_clear (ctyp, gs) :: !cleanup; + CV_id (gs, ctyp) + else + assert false in let sargs = List.map2 setup_arg arg_ctyps args in @@ -677,7 +969,7 @@ let compile_funcall env id args typ = else if not (is_stack_ctyp ret_ctyp) && is_stack_ctyp final_ctyp then let gs = gensym () in setup := I_alloc (ret_ctyp, gs) :: !setup; - setup := I_funcall (gs, id, sargs, ret_ctyp) :: !setup; + setup := I_funcall (CL_id gs, id, sargs, ret_ctyp) :: !setup; cleanup := I_clear (ret_ctyp, gs) :: !cleanup; fun ret -> I_convert (ret, final_ctyp, gs, ret_ctyp) else @@ -686,128 +978,373 @@ let compile_funcall env id args typ = (List.rev !setup, final_ctyp, call, !cleanup) -let rec compile_aexp env = function +let rec compile_match ctx apat cval case_label = + match apat, cval with + | AP_id pid, CV_C_fragment (code, ctyp) when is_ct_enum ctyp -> + [ I_if (CV_C_fragment (Util.zencode_upper_string (string_of_id pid) ^ " != " ^ code, CT_bool), [I_goto case_label], [], CT_unit) ] + | AP_id pid, CV_id (id, ctyp) when is_ct_enum ctyp -> + [ I_if (CV_C_fragment (Util.zencode_upper_string (string_of_id pid) ^ " != " ^ Util.zencode_string (string_of_id id), CT_bool), [I_goto case_label], [], CT_unit) ] + | AP_id pid, CV_C_fragment (code, ctyp) -> + [ I_decl (cval_ctyp cval, pid); I_copy (CL_id pid, cval) ] + | AP_id pid, CV_id _ -> + [ I_decl (cval_ctyp cval, pid); I_copy (CL_id pid, cval) ] + | AP_tup apats, CV_id (id, ctyp) -> + begin + let get_tup n ctyp = CV_C_fragment (Util.zencode_string (string_of_id id) ^ ".ztup" ^ string_of_int n, ctyp) in + match ctyp with + | CT_tup ctyps -> + fst (List.fold_left2 (fun (instrs, n) apat ctyp -> instrs @ compile_match ctx apat (get_tup n ctyp) case_label, n + 1) ([], 0) apats ctyps) + | _ -> assert false + end + | _, _ -> [] + +let unit_fragment = CV_C_fragment ("UNIT", CT_unit) + +(** GLOBAL: label_counter is used to make sure all labels have unique + names. Like gensym_counter it should be safe to reset between + top-level definitions. **) +let label_counter = ref 0 + +let label str = + let str = str ^ string_of_int !label_counter in + incr label_counter; + str + +let rec compile_aexp ctx = function | AE_let (id, _, binding, body, typ) -> - let setup, ctyp, call, cleanup = compile_aexp env binding in + let setup, ctyp, call, cleanup = compile_aexp ctx binding in let letb1, letb1c = if is_stack_ctyp ctyp then - [I_decl (ctyp, id); call id], [] + [I_decl (ctyp, id); call (CL_id id)], [] else - [I_alloc (ctyp, id); call id], [I_clear (ctyp, id)] + [I_alloc (ctyp, id); call (CL_id id)], [I_clear (ctyp, id)] in let letb2 = setup @ letb1 @ cleanup in - let setup, ctyp, call, cleanup = compile_aexp env body in + let setup, ctyp, call, cleanup = compile_aexp ctx body in letb2 @ setup, ctyp, call, cleanup @ letb1c | AE_app (id, vs, typ) -> - compile_funcall env id vs typ - - | AE_val (AV_C_fragment (c, typ)) -> - let ctyp = ctyp_of_typ typ in - [], ctyp, (fun id -> I_assign (id, CV_C_fragment (c, ctyp))), [] - - | AE_val (AV_id (id, lvar)) -> - let ctyp = ctyp_of_typ (lvar_typ lvar) in - [], ctyp, (fun id' -> I_assign (id', CV_id (id, ctyp))), [] - - | AE_val (AV_lit (lit, typ)) -> - let ctyp = ctyp_of_typ typ in - if is_stack_ctyp ctyp then - assert false - else + compile_funcall ctx id vs typ + + | AE_val aval -> + let setup, cval, cleanup = compile_aval ctx aval in + setup, cval_ctyp cval, (fun clexp -> I_copy (clexp, cval)), cleanup + + (* Compile case statements *) + | AE_case (aval, cases, typ) -> + let ctyp = ctyp_of_typ ctx typ in + let aval_setup, cval, aval_cleanup = compile_aval ctx aval in + let case_return_id = gensym () in + let finish_match_label = label "finish_match_" in + let compile_case (apat, guard, body) = + let trivial_guard = match guard with + | AE_val (AV_lit (L_aux (L_true, _), _)) + | AE_val (AV_C_fragment ("true", _)) -> true + | _ -> false + in + let case_label = label "case_" in + let destructure = compile_match ctx apat cval case_label in + let guard_setup, _, guard_call, guard_cleanup = compile_aexp ctx guard in + let body_setup, _, body_call, body_cleanup = compile_aexp ctx body in let gs = gensym () in - [I_alloc (ctyp, gs); I_comment "fix literal init"], - ctyp, - (fun id -> I_assign (id, CV_id (gs, ctyp))), - [I_clear (ctyp, gs)] + let case_instrs = + destructure @ [I_comment "end destructuring"] + @ (if not trivial_guard then + guard_setup @ [I_decl (CT_bool, gs); guard_call (CL_id gs)] @ guard_cleanup + @ [I_if (CV_C_fragment (Printf.sprintf "!%s" (Util.zencode_string (string_of_id gs)), CT_bool), [I_goto case_label], [], CT_unit)] + @ [I_comment "end guard"] + else []) + @ body_setup @ [body_call (CL_id case_return_id)] @ body_cleanup + @ [I_goto finish_match_label] + in + [I_block case_instrs; I_label case_label] + in + [I_comment "begin match"] + @ aval_setup @ [I_decl (ctyp, case_return_id)] + @ List.concat (List.map compile_case cases) + @ [I_raw "sail_match_failure();"] + @ [I_label finish_match_label], + ctyp, + (fun clexp -> I_copy (clexp, CV_id (case_return_id, ctyp))), + aval_cleanup + @ [I_comment "end match"] | AE_if (aval, then_aexp, else_aexp, if_typ) -> - let if_ctyp = ctyp_of_typ if_typ in + let if_ctyp = ctyp_of_typ ctx if_typ in let compile_branch aexp = - let setup, ctyp, call, cleanup = compile_aexp env aexp in - fun id -> setup @ [call id] @ cleanup + let setup, ctyp, call, cleanup = compile_aexp ctx aexp in + fun clexp -> setup @ [call clexp] @ cleanup in - let setup, ctyp, call, cleanup = compile_aexp env (AE_val aval) in + let setup, ctyp, call, cleanup = compile_aexp ctx (AE_val aval) in let gs = gensym () in - setup @ [I_decl (ctyp, gs); call gs], + setup @ [I_decl (ctyp, gs); call (CL_id gs)], if_ctyp, - (fun id -> I_if (CV_id (gs, ctyp), - compile_branch then_aexp id, - compile_branch else_aexp id, - if_ctyp)), + (fun clexp -> I_if (CV_id (gs, ctyp), + compile_branch then_aexp clexp, + compile_branch else_aexp clexp, + if_ctyp)), cleanup - + + | AE_record_update (aval, fields, typ) -> + let update_field (prev_setup, prev_calls, prev_cleanup) (field, aval) = + let setup, _, call, cleanup = compile_aexp ctx (AE_val aval) in + prev_setup @ setup, call :: prev_calls, cleanup @ prev_cleanup + in + let setup, calls, cleanup = List.fold_left update_field ([], [], []) (Bindings.bindings fields) in + let ctyp = ctyp_of_typ ctx typ in + let gs = gensym () in + [I_alloc (ctyp, gs)] @ setup @ List.map (fun call -> call (CL_id gs)) calls, + ctyp, + (fun clexp -> I_copy (clexp, CV_id (gs, ctyp))), + cleanup @ [I_clear (ctyp, gs)] + | AE_assign (id, assign_typ, aexp) -> (* assign_ctyp is the type of the C variable we are assigning to, ctyp is the type of the C expression being assigned. These may be different. *) - let assign_ctyp = ctyp_of_typ assign_typ in - let setup, ctyp, call, cleanup = compile_aexp env aexp in - let unit_fragment = CV_C_fragment ("0", CT_unit) in + let assign_ctyp = ctyp_of_typ ctx assign_typ in + let setup, ctyp, call, cleanup = compile_aexp ctx aexp in let comment = "assign " ^ string_of_ctyp assign_ctyp ^ " := " ^ string_of_ctyp ctyp in if ctyp_equal assign_ctyp ctyp then - setup @ [call id], CT_unit, (fun id -> I_assign (id, unit_fragment)), cleanup + setup @ [call (CL_id id)], CT_unit, (fun clexp -> I_copy (clexp, unit_fragment)), cleanup else if not (is_stack_ctyp assign_ctyp) && is_stack_ctyp ctyp then let gs = gensym () in setup @ [ I_comment comment; I_decl (ctyp, gs); - call gs; - I_convert (id, assign_ctyp, gs, ctyp) + call (CL_id gs); + I_convert (CL_id id, assign_ctyp, gs, ctyp) ], CT_unit, - (fun id -> I_assign (id, unit_fragment)), + (fun clexp -> I_copy (clexp, unit_fragment)), cleanup else - failwith ("Failure: " ^ comment) - + failwith comment + | AE_block (aexps, aexp, _) -> - let block = compile_block env aexps in - let setup, ctyp, call, cleanup = compile_aexp env aexp in + let block = compile_block ctx aexps in + let setup, ctyp, call, cleanup = compile_aexp ctx aexp in block @ setup, ctyp, call, cleanup - | AE_cast (aexp, typ) -> compile_aexp env aexp - -and compile_block env = function + | AE_loop (While, cond, body) -> + let loop_start_label = label "while_" in + let loop_end_label = label "wend_" in + let cond_setup, _, cond_call, cond_cleanup = compile_aexp ctx cond in + let body_setup, _, body_call, body_cleanup = compile_aexp ctx body in + let gs = gensym () in + let unit_gs = gensym () in + let loop_test = CV_C_fragment (Printf.sprintf "!%s" (Util.zencode_string (string_of_id gs)), CT_bool) in + cond_setup @ [I_decl (CT_bool, gs); I_decl (CT_unit, unit_gs)] + @ [I_label loop_start_label] + @ [I_block ([cond_call (CL_id gs); I_if (loop_test, [I_goto loop_end_label], [], CT_unit)] + @ body_setup + @ [body_call (CL_id unit_gs)] + @ body_cleanup + @ [I_goto loop_start_label])] + @ [I_label loop_end_label], + CT_unit, + (fun clexp -> I_copy (clexp, unit_fragment)), + cond_cleanup + + | AE_cast (aexp, typ) -> compile_aexp ctx aexp + + | AE_return (aval, typ) -> + (* Cleanup info will be re-added by fix_early_return *) + let return_setup, cval, _ = compile_aval ctx aval in + return_setup @ [I_return cval], + CT_unit, + (fun clexp -> I_copy (clexp, unit_fragment)), + [] + + | aexp -> failwith ("Cannot compile ANF expression: " ^ Pretty_print_sail.to_string (pp_aexp aexp)) + +and compile_block ctx = function | [] -> [] | exp :: exps -> - let setup, _, call, cleanup = compile_aexp env exp in - let rest = compile_block env exps in + let setup, _, call, cleanup = compile_aexp ctx exp in + let rest = compile_block ctx exps in let gs = gensym () in - setup @ [I_decl (CT_unit, gs); call gs] @ cleanup @ rest + setup @ [I_decl (CT_unit, gs); call (CL_id gs)] @ cleanup @ rest -let rec pat_ids (P_aux (p_aux, _)) = +let rec pat_ids (P_aux (p_aux, _) as pat) = match p_aux with | P_id id -> [id] | P_tup pats -> List.concat (List.map pat_ids pats) - | _ -> failwith "Bad pattern" + | P_lit (L_aux (L_unit, _)) -> let gs = gensym () in [gs] + | P_wild -> let gs = gensym () in [gs] + | _ -> failwith ("Bad pattern " ^ string_of_pat pat) + +(** Compile a sail type definition into a LLcode one. Most of the + actual work of translating the typedefs into C is done by the code + generator, as it's easy to keep track of structs, tuples and unions + in their sail form at this level, and leave the fiddly details of + how they get mapped to C in the next stage. This function also adds + details of the types it compiles to the context, ctx, which is why + it returns a ctypdef * ctx pair. **) +let compile_type_def ctx (TD_aux (type_def, _)) = + match type_def with + | TD_enum (id, _, ids, _) -> + CTD_enum (id, IdSet.of_list ids), + { ctx with enums = Bindings.add id (IdSet.of_list ids) ctx.enums } + + | TD_record (id, _, _, ctors, _) -> + let ctors = List.fold_left (fun ctors (typ, id) -> Bindings.add id (ctyp_of_typ ctx typ) ctors) Bindings.empty ctors in + CTD_record (id, ctors), + { ctx with records = Bindings.add id ctors ctx.records } + + | TD_variant (id, _, _, tus, _) -> + let compile_tu (Tu_aux (tu_aux, _)) = + match tu_aux with + | Tu_id id -> CT_unit, id + | Tu_ty_id (typ, id) -> ctyp_of_typ ctx typ, id + in + let ctus = List.fold_left (fun ctus (ctyp, id) -> Bindings.add id ctyp ctus) Bindings.empty (List.map compile_tu tus) in + CTD_variant (id, ctus), + { ctx with variants = Bindings.add id ctus ctx.variants } + + (* Will be re-written before here, see bitfield.ml *) + | TD_bitfield _ -> failwith "Cannot compile TD_bitfield" + (* All type abbreviations are filtered out in compile_def *) + | TD_abbrev _ -> assert false + +let instr_split_at f = + let rec instr_split_at' f before = function + | [] -> (List.rev before, []) + | instr :: instrs when f instr -> (List.rev before, instr :: instrs) + | instr :: instrs -> instr_split_at' f (instr :: before) instrs + in + instr_split_at' f [] -let compile_def env = function +let generate_cleanup instrs = + let generate_cleanup' = function + | I_decl (ctyp, id) when not (is_stack_ctyp ctyp) -> [(id, I_clear (ctyp, id))] + | I_alloc (ctyp, id) when not (is_stack_ctyp ctyp) -> [(id, I_clear (ctyp, id))] + | _ -> [] + in + let is_clear ids = function + | I_clear (_, id) -> IdSet.add id ids + | _ -> ids + in + let cleaned = List.fold_left is_clear IdSet.empty instrs in + instrs + |> List.map generate_cleanup' + |> List.concat + |> List.filter (fun (id, _) -> not (IdSet.mem id cleaned)) + |> List.map snd + +(** Functions that have heap-allocated return types are implemented by + passing a pointer a location where the return value should be + stored. The ANF -> LLcode pass for expressions simply outputs an + I_return instruction for any return value, so this function walks + over the LLcode ast for expressions and modifies the return + statements into code that sets that pointer, as well as adds extra + control flow to cleanup heap-allocated variables correctly when a + function terminates early. See the generate_cleanup function for + how this is done. *) +let fix_early_return ret ctx instrs = + let end_function_label = label "end_function_" in + let is_return_recur = function + | I_return _ | I_if _ | I_block _ -> true + | _ -> false + in + let rec rewrite_return pre_cleanup instrs = + match instr_split_at is_return_recur instrs with + | instrs, [] -> instrs + | before, I_block instrs :: after -> + before + @ [I_block (rewrite_return (pre_cleanup @ generate_cleanup before) instrs)] + @ rewrite_return pre_cleanup after + | before, I_if (cval, then_instrs, else_instrs, ctyp) :: after -> + let cleanup = pre_cleanup @ generate_cleanup before in + before + @ [I_if (cval, rewrite_return cleanup then_instrs, rewrite_return cleanup else_instrs, ctyp)] + @ rewrite_return pre_cleanup after + | before, I_return cval :: after -> + let cleanup_label = label "cleanup_" in + let end_cleanup_label = label "end_cleanup_" in + before + @ [I_copy (ret, cval); + I_goto cleanup_label] + (* This is probably dead code until cleanup_label, but how can we be sure there are no jumps into it? *) + @ rewrite_return pre_cleanup after + @ [I_goto end_cleanup_label] + @ [I_label cleanup_label] + @ pre_cleanup + @ generate_cleanup before + @ [I_goto end_function_label] + @ [I_label end_cleanup_label] + | _, _ -> assert false + in + rewrite_return [] instrs + @ [I_label end_function_label] + +(** Compile a Sail toplevel definition into an LLcode definition **) +let compile_def ctx = function | DEF_reg_dec (DEC_aux (DEC_reg (typ, id), _)) -> - [CDEF_reg_dec (ctyp_of_typ typ, id)] + [CDEF_reg_dec (ctyp_of_typ ctx typ, id)], ctx | DEF_reg_dec _ -> failwith "Unsupported register declaration" (* FIXME *) - | DEF_spec _ -> [] + | DEF_spec _ -> [], ctx | DEF_fundef (FD_aux (FD_function (_, _, _, [FCL_aux (FCL_Funcl (id, pexp), _)]), _)) -> begin match pexp with | Pat_aux (Pat_exp (pat, exp), _) -> - let aexp = map_functions analyze_primop (c_literals (anf exp)) in - print_endline (Pretty_print_sail.to_string (pp_aexp aexp)); - let setup, ctyp, call, cleanup = compile_aexp env aexp in + let aexp = map_functions (analyze_primop ctx) (c_literals ctx (anf exp)) in + prerr_endline (Pretty_print_sail.to_string (pp_aexp aexp)); + let setup, ctyp, call, cleanup = compile_aexp ctx aexp in let gs = gensym () in - let instrs = - if is_stack_ctyp ctyp then - setup @ [I_decl (ctyp, gs); call gs] @ cleanup @ [I_return gs] - else - assert false - in - [CDEF_fundef (id, pat_ids pat, instrs)] + if is_stack_ctyp ctyp then + let instrs = [I_decl (ctyp, gs)] @ setup @ [call (CL_id gs)] @ cleanup @ [I_return (CV_id (gs, ctyp))] in + [CDEF_fundef (id, None, pat_ids pat, instrs)], ctx + else + let instrs = setup @ [call (CL_addr (CL_id gs))] @ cleanup in + let instrs = fix_early_return (CL_addr (CL_id gs)) ctx instrs in + [CDEF_fundef (id, Some gs, pat_ids pat, instrs)], ctx | _ -> assert false end - | DEF_default _ -> [] - + (* All abbreviations should expanded by the typechecker, so we don't + need to translate type abbreviations into C typedefs. *) + | DEF_type (TD_aux (TD_abbrev _, _)) -> [], ctx + + | DEF_type type_def -> + let tdef, ctx = compile_type_def ctx type_def in + [CDEF_type tdef], ctx + + (* Only DEF_default that matters is default Order, but all order + polymorphism is specialised by this point. *) + | DEF_default _ -> [], ctx + + (* Overloading resolved by type checker *) + | DEF_overload _ -> [], ctx + + (* Only the parser and sail pretty printer care about this. *) + | DEF_fixity _ -> [], ctx + + | _ -> assert false + +(** To keep things neat we use GCC's local labels extension to limit + the scope of labels. We do this by iterating over all the blocks + and adding a __label__ declaration with all the labels local to + that block. The add_local_labels function is called by the code + generator just before it outputs C. + + See https://gcc.gnu.org/onlinedocs/gcc/Local-Labels.html **) +let add_local_labels' instrs = + let is_label = function + | I_label str -> [str] + | _ -> [] + in + let labels = List.concat (List.map is_label instrs) in + let local_label_decl = I_raw ("__label__ " ^ String.concat ", " labels ^ ";\n") in + if labels = [] then + instrs + else + local_label_decl :: instrs + +let add_local_labels instrs = + match map_instrs add_local_labels' (I_block instrs) with + | I_block instrs -> instrs | _ -> assert false (**************************************************************************) @@ -817,114 +1354,291 @@ let compile_def env = function let sgen_id id = Util.zencode_string (string_of_id id) let codegen_id id = string (sgen_id id) +let upper_sgen_id id = Util.zencode_upper_string (string_of_id id) +let upper_codegen_id id = string (upper_sgen_id id) + let sgen_ctyp = function - | CT_unit -> "int" + | CT_unit -> "unit" + | CT_int -> "int" + | CT_bool -> "bool" + | CT_uint64 _ -> "uint64_t" + | CT_int64 -> "int64_t" + | CT_mpz -> "mpz_t" + | CT_bv _ -> "bv_t" + | CT_tup _ as tup -> "struct " ^ Util.zencode_string ("tuple_" ^ string_of_ctyp tup) + | CT_struct (id, _) -> "struct " ^ sgen_id id + | CT_enum (id, _) -> "enum " ^ sgen_id id + | CT_variant (id, _) -> "struct " ^ sgen_id id + | CT_string -> "sail_string" + +let sgen_ctyp_name = function + | CT_unit -> "unit" | CT_int -> "int" | CT_bool -> "bool" | CT_uint64 _ -> "uint64_t" | CT_int64 -> "int64_t" | CT_mpz -> "mpz_t" | CT_bv _ -> "bv_t" + | CT_tup _ as tup -> Util.zencode_string ("tuple_" ^ string_of_ctyp tup) + | CT_struct (id, _) -> sgen_id id + | CT_enum (id, _) -> sgen_id id + | CT_variant (id, _) -> sgen_id id + | CT_string -> "sail_string" let sgen_cval = function | CV_C_fragment (c, _) -> c - | CV_id (id, _) -> string_of_id id + | CV_id (id, _) -> sgen_id id | _ -> "CVAL??" -let rec codegen_instr = function +let sgen_clexp = function + | CL_id id -> "&" ^ sgen_id id + | CL_field (id, field) -> "&(" ^ sgen_id id ^ "." ^ sgen_id field ^ ")" + | CL_addr (CL_id id) -> sgen_id id + | _ -> assert false + +let sgen_clexp_pure = function + | CL_id id -> sgen_id id + | CL_field (id, field) -> sgen_id id ^ "." ^ sgen_id field + | _ -> assert false + +let rec codegen_instr ctx = function | I_decl (ctyp, id) -> - string (Printf.sprintf "%s %s;" (sgen_ctyp ctyp) (string_of_id id)) - | I_assign (id, cval) -> + string (Printf.sprintf " %s %s;" (sgen_ctyp ctyp) (sgen_id id)) + | I_copy (clexp, cval) -> let ctyp = cval_ctyp cval in if is_stack_ctyp ctyp then - string (Printf.sprintf "%s = %s;" (string_of_id id) (sgen_cval cval)) + string (Printf.sprintf " %s = %s;" (sgen_clexp_pure clexp) (sgen_cval cval)) else - string (Printf.sprintf "set_%s(%s, %s);" (sgen_ctyp ctyp) (string_of_id id) (sgen_cval cval)) + string (Printf.sprintf " set_%s(%s, %s);" (sgen_ctyp_name ctyp) (sgen_clexp clexp) (sgen_cval cval)) + | I_if (cval, [then_instr], [], ctyp) -> + string (Printf.sprintf " if (%s)" (sgen_cval cval)) ^^ hardline + ^^ twice space ^^ codegen_instr ctx then_instr | I_if (cval, then_instrs, else_instrs, ctyp) -> - string "if" ^^ space ^^ parens (string (sgen_cval cval)) ^^ space - ^^ surround 2 0 lbrace (separate_map hardline codegen_instr then_instrs) rbrace + string " if" ^^ space ^^ parens (string (sgen_cval cval)) ^^ space + ^^ surround 2 0 lbrace (separate_map hardline (codegen_instr ctx) then_instrs) (twice space ^^ rbrace) ^^ space ^^ string "else" ^^ space - ^^ surround 2 0 lbrace (separate_map hardline codegen_instr else_instrs) rbrace + ^^ surround 2 0 lbrace (separate_map hardline (codegen_instr ctx) else_instrs) (twice space ^^ rbrace) + | I_block instrs -> + string " {" + ^^ jump 2 2 (separate_map hardline (codegen_instr ctx) instrs) ^^ hardline + ^^ string " }" | I_funcall (x, f, args, ctyp) -> let args = Util.string_of_list ", " sgen_cval args in + let fname = if Env.is_extern f ctx.tc_env "c" then Env.get_extern f ctx.tc_env "c" else sgen_id f in if is_stack_ctyp ctyp then - string (Printf.sprintf "%s = %s(%s);" (string_of_id x) (sgen_id f) args) + string (Printf.sprintf " %s = %s(%s);" (sgen_clexp_pure x) fname args) else - string (Printf.sprintf "%s(%s, %s);" (sgen_id f) (string_of_id x) args) + string (Printf.sprintf " %s(%s, %s);" fname (sgen_clexp x) args) | I_clear (ctyp, id) -> - string (Printf.sprintf "clear_%s(%s);" (sgen_ctyp ctyp) (string_of_id id)) + string (Printf.sprintf " clear_%s(&%s);" (sgen_ctyp_name ctyp) (sgen_id id)) | I_init (ctyp, id, cval) -> - string (Printf.sprintf "init_%s_of_%s(%s, %s);" - (sgen_ctyp ctyp) - (sgen_ctyp (cval_ctyp cval)) - (string_of_id id) + string (Printf.sprintf " init_%s_of_%s(&%s, %s);" + (sgen_ctyp_name ctyp) + (sgen_ctyp_name (cval_ctyp cval)) + (sgen_id id) (sgen_cval cval)) | I_alloc (ctyp, id) -> - string (Printf.sprintf "%s %s;" (sgen_ctyp ctyp) (string_of_id id)) + string (Printf.sprintf " %s %s;" (sgen_ctyp ctyp) (sgen_id id)) ^^ hardline - ^^ string (Printf.sprintf "init_%s(%s);" (sgen_ctyp ctyp) (string_of_id id)) + ^^ string (Printf.sprintf " init_%s(&%s);" (sgen_ctyp_name ctyp) (sgen_id id)) | I_convert (x, ctyp1, y, ctyp2) -> if is_stack_ctyp ctyp1 then - string (Printf.sprintf "%s = convert_%s_of_%s(%s);" - (string_of_id x) - (sgen_ctyp ctyp1) - (sgen_ctyp ctyp2) - (string_of_id y)) + string (Printf.sprintf " %s = convert_%s_of_%s(%s);" + (sgen_clexp_pure x) + (sgen_ctyp_name ctyp1) + (sgen_ctyp_name ctyp2) + (sgen_id y)) else - string (Printf.sprintf "convert_%s_of_%s(%s, %s);" - (sgen_ctyp ctyp1) - (sgen_ctyp ctyp2) - (string_of_id x) - (string_of_id y)) - | I_return id -> - string (Printf.sprintf "return %s;" (string_of_id id)) + string (Printf.sprintf " convert_%s_of_%s(%s, %s);" + (sgen_ctyp_name ctyp1) + (sgen_ctyp_name ctyp2) + (sgen_clexp x) + (sgen_id y)) + | I_return cval -> + string (Printf.sprintf " return %s;" (sgen_cval cval)) | I_comment str -> - string ("/* " ^ str ^ " */") - -let codegen_def env = function + string (" /* " ^ str ^ " */") + | I_label str -> + string (str ^ ": ;") + | I_goto str -> + string (Printf.sprintf " goto %s;" str) + | I_raw str -> + string (" " ^ str) + +let codegen_type_def ctx = function + | CTD_enum (id, ids) -> + string (Printf.sprintf "// enum %s" (string_of_id id)) ^^ hardline + ^^ separate space [string "enum"; codegen_id id; lbrace; separate_map (comma ^^ space) upper_codegen_id (IdSet.elements ids); rbrace ^^ semi] + + | CTD_record (id, ctors) -> + (* Generate a set_T function for every struct T *) + let codegen_set (id, ctyp) = + if is_stack_ctyp ctyp then + string (Printf.sprintf "rop->%s = op.%s;" (sgen_id id) (sgen_id id)) + else + string (Printf.sprintf "set_%s(&rop->%s, op.%s);" (sgen_ctyp_name ctyp) (sgen_id id) (sgen_id id)) + in + let codegen_setter id ctors = + string (let n = sgen_id id in Printf.sprintf "void set_%s(struct %s *rop, const struct %s op)" n n n) ^^ space + ^^ surround 2 0 lbrace + (separate_map hardline codegen_set (Bindings.bindings ctors)) + rbrace + in + (* Generate an init/clear_T function for every struct T *) + let codegen_field_init f (id, ctyp) = + if not (is_stack_ctyp ctyp) then + [string (Printf.sprintf "%s_%s(&op->%s);" f (sgen_ctyp_name ctyp) (sgen_id id))] + else [] + in + let codegen_init f id ctors = + string (let n = sgen_id id in Printf.sprintf "void %s_%s(struct %s *op)" f n n) ^^ space + ^^ surround 2 0 lbrace + (separate hardline (Bindings.bindings ctors |> List.map (codegen_field_init f) |> List.concat)) + rbrace + in + (* Generate the struct and add the generated functions *) + let codegen_ctor (id, ctyp) = + string (sgen_ctyp ctyp) ^^ space ^^ codegen_id id + in + string (Printf.sprintf "// struct %s" (string_of_id id)) ^^ hardline + ^^ string "struct" ^^ space ^^ codegen_id id ^^ space + ^^ surround 2 0 lbrace + (separate_map (semi ^^ hardline) codegen_ctor (Bindings.bindings ctors) ^^ semi) + rbrace + ^^ semi ^^ twice hardline + ^^ codegen_setter id ctors + ^^ twice hardline + ^^ codegen_init "init" id ctors + ^^ twice hardline + ^^ codegen_init "clear" id ctors + + | CTD_variant (id, tus) -> + let codegen_tu (id, ctyp) = + separate space [string "struct"; lbrace; string (sgen_ctyp ctyp); codegen_id id ^^ semi; rbrace] + in + string (Printf.sprintf "// union %s" (string_of_id id)) ^^ hardline + ^^ string "enum" ^^ space + ^^ string ("kind_" ^ sgen_id id) ^^ space + ^^ separate space [lbrace; separate_map (comma ^^ space) (fun id -> string ("Kind_" ^ sgen_id id)) (List.map fst (Bindings.bindings tus)); rbrace ^^ semi] + ^^ hardline ^^ hardline + ^^ string "struct" ^^ space ^^ codegen_id id ^^ space + ^^ surround 2 0 lbrace + (separate space [string "enum"; string ("kind_" ^ sgen_id id); string "kind" ^^ semi] + ^^ hardline + ^^ string "union" ^^ space + ^^ surround 2 0 lbrace + (separate_map (semi ^^ hardline) codegen_tu (Bindings.bindings tus) ^^ semi) + rbrace + ^^ semi) + rbrace + ^^ semi + +(** GLOBAL: because C doesn't have real anonymous tuple types + (anonymous structs don't quite work the way we need) every tuple + type in the spec becomes some generated named struct in C. This is + done in such a way that every possible tuple type has a unique name + associated with it. This global variable keeps track of these + generated struct names, so we never generate two copies of the + struct that is used to represent them in C. + + The way this works is that codegen_def scans each definition's type + annotations for tuple types and generates the required structs + using codegen_type_def before the actual definition is generated by + codegen_def'. + + This variable should be reset to empty only when the entire AST has + been translated to C. **) +let generated_tuples = ref IdSet.empty + +let codegen_tup ctx ctyps = + let id = mk_id ("tuple_" ^ string_of_ctyp (CT_tup ctyps)) in + if IdSet.mem id !generated_tuples then + empty + else + let _, fields = List.fold_left (fun (n, fields) ctyp -> n + 1, Bindings.add (mk_id ("tup" ^ string_of_int n)) ctyp fields) + (0, Bindings.empty) + ctyps + in + generated_tuples := IdSet.add id !generated_tuples; + codegen_type_def ctx (CTD_record (id, fields)) ^^ twice hardline + +let codegen_def' ctx = function | CDEF_reg_dec (ctyp, id) -> - string (Printf.sprintf "%s %s;" (sgen_ctyp ctyp) (sgen_id id)) - | CDEF_fundef (id, args, instrs) -> - List.iter (fun instr -> print_endline (Pretty_print_sail.to_string (pp_instr instr))) instrs; - let _, Typ_aux (fn_typ, _) = Env.get_val_spec id env in + string (Printf.sprintf "// register %s" (string_of_id id)) ^^ hardline + ^^ string (Printf.sprintf "%s %s;" (sgen_ctyp ctyp) (sgen_id id)) + + | CDEF_fundef (id, ret_arg, args, instrs) -> + let instrs = add_local_labels instrs in + List.iter (fun instr -> prerr_endline (Pretty_print_sail.to_string (pp_instr instr))) instrs; + let _, Typ_aux (fn_typ, _) = Env.get_val_spec id ctx.tc_env in let arg_typs, ret_typ = match fn_typ with | Typ_fn (Typ_aux (Typ_tup arg_typs, _), ret_typ, _) -> arg_typs, ret_typ | Typ_fn (arg_typ, ret_typ, _) -> [arg_typ], ret_typ | _ -> assert false in - let arg_ctyps, ret_ctyp = List.map ctyp_of_typ arg_typs, ctyp_of_typ ret_typ in - + let arg_ctyps, ret_ctyp = List.map (ctyp_of_typ ctx) arg_typs, ctyp_of_typ ctx ret_typ in let args = Util.string_of_list ", " (fun x -> x) (List.map2 (fun ctyp arg -> sgen_ctyp ctyp ^ " " ^ sgen_id arg) arg_ctyps args) in - - string (sgen_ctyp ret_ctyp) ^^ space ^^ codegen_id id ^^ parens (string args) ^^ hardline + let function_header = + match ret_arg with + | None -> + assert (is_stack_ctyp ret_ctyp); + string (sgen_ctyp ret_ctyp) ^^ space ^^ codegen_id id ^^ parens (string args) ^^ hardline + | Some gs -> + assert (not (is_stack_ctyp ret_ctyp)); + string "void" ^^ space ^^ codegen_id id + ^^ parens (string (sgen_ctyp ret_ctyp ^ " *" ^ sgen_id gs ^ ", ") ^^ string args) + ^^ hardline + in + function_header ^^ string "{" - ^^ jump 2 2 (separate_map hardline codegen_instr instrs) ^^ hardline + ^^ jump 0 2 (separate_map hardline (codegen_instr ctx) instrs) ^^ hardline ^^ string "}" -let compile_ast env (Defs defs) = - let cdefs = List.concat (List.map (compile_def env) defs) in - let docs = List.map (codegen_def env) cdefs in + | CDEF_type ctype_def -> + codegen_type_def ctx ctype_def + +let codegen_def ctx def = + let untup = function + | CT_tup ctyps -> ctyps + | _ -> assert false + in + let tups = List.filter is_ct_tup (cdef_ctyps def) in + let tups = List.map (fun ctyp -> codegen_tup ctx (untup ctyp)) tups in + concat tups + ^^ codegen_def' ctx def + +let compile_ast ctx (Defs defs) = + let chunks, ctx = List.fold_left (fun (chunks, ctx) def -> let defs, ctx = compile_def ctx def in defs :: chunks, ctx) ([], ctx) defs in + let cdefs = List.concat (List.rev chunks) in + let docs = List.map (codegen_def ctx) cdefs in let preamble = separate hardline [ string "#include \"sail.h\"" ] in + let postamble = separate hardline + [ string "int main(void)"; + string "{"; + string " zmain(UNIT);"; + string "}" ] + in + let hlhl = hardline ^^ hardline in - Pretty_print_sail.to_string (preamble ^^ hlhl ^^ separate hlhl docs) + Pretty_print_sail.to_string (preamble ^^ hlhl ^^ separate hlhl docs ^^ hlhl ^^ postamble) |> print_endline let print_compiled (setup, ctyp, call, cleanup) = List.iter (fun instr -> print_endline (Pretty_print_sail.to_string (pp_instr instr))) setup; - print_endline (Pretty_print_sail.to_string (pp_instr (call (mk_id ("?" ^ string_of_ctyp ctyp))))); + print_endline (Pretty_print_sail.to_string (pp_instr (call (CL_id (mk_id ("?" ^ string_of_ctyp ctyp)))))); List.iter (fun instr -> print_endline (Pretty_print_sail.to_string (pp_instr instr))) cleanup -let compile_exp env exp = +let compile_exp ctx exp = let aexp = anf exp in - let aexp = c_literals aexp in - let aexp = map_functions analyze_primop aexp in + let aexp = c_literals ctx aexp in + let aexp = map_functions (analyze_primop ctx) aexp in print_endline "\n###################### COMPILED ######################\n"; - print_compiled (compile_aexp env aexp); + print_compiled (compile_aexp ctx aexp); print_endline "\n###################### ANF ######################\n"; aexp diff --git a/src/gen_lib/prompt.lem b/src/gen_lib/prompt.lem index 5019c2f7..d398ab52 100644 --- a/src/gen_lib/prompt.lem +++ b/src/gen_lib/prompt.lem @@ -1,172 +1,8 @@ open import Pervasives_extra open import Sail_impl_base open import Sail_values - -type M 'a 'e = outcome 'a 'e - -val return : forall 'a 'e. 'a -> M 'a 'e -let return a = Done a - -val bind : forall 'a 'b 'e. M 'a 'e -> ('a -> M 'b 'e) -> M 'b 'e -let rec bind m f = match m with - | Done a -> f a - | Read_mem descr k -> Read_mem descr (fun v -> let (o,opt) = k v in (bind o f,opt)) - | Read_reg descr k -> Read_reg descr (fun v -> let (o,opt) = k v in (bind o f,opt)) - | Write_memv descr k -> Write_memv descr (fun v -> let (o,opt) = k v in (bind o f,opt)) - | Excl_res k -> Excl_res (fun v -> let (o,opt) = k v in (bind o f,opt)) - | Write_ea descr o_s -> Write_ea descr (let (o,opt) = o_s in (bind o f,opt)) - | Barrier descr o_s -> Barrier descr (let (o,opt) = o_s in (bind o f,opt)) - | Footprint o_s -> Footprint (let (o,opt) = o_s in (bind o f,opt)) - | Write_reg descr o_s -> Write_reg descr (let (o,opt) = o_s in (bind o f,opt)) - | Escape descr -> Escape descr - | Fail descr -> Fail descr - | Error descr -> Error descr - | Exception e -> Exception e - | Internal descr o_s -> Internal descr (let (o,opt) = o_s in (bind o f ,opt)) -end - -let inline (>>=) = bind -val (>>) : forall 'b 'e. M unit 'e -> M 'b 'e -> M 'b 'e -let inline (>>) m n = m >>= fun (_ : unit) -> n - -val exit : forall 'a 'e. unit -> M 'a 'e -let exit () = Fail Nothing - -val assert_exp : forall 'e. bool -> string -> M unit 'e -let assert_exp exp msg = if exp then Done () else Fail (Just msg) - -val throw : forall 'a 'e. 'e -> M 'a 'e -let throw e = Exception e - -val try_catch : forall 'a 'e1 'e2. M 'a 'e1 -> ('e1 -> M 'a 'e2) -> M 'a 'e2 -let rec try_catch m h = match m with - | Done a -> Done a - | Read_mem descr k -> Read_mem descr (fun v -> let (o,opt) = k v in (try_catch o h,opt)) - | Read_reg descr k -> Read_reg descr (fun v -> let (o,opt) = k v in (try_catch o h,opt)) - | Write_memv descr k -> Write_memv descr (fun v -> let (o,opt) = k v in (try_catch o h,opt)) - | Excl_res k -> Excl_res (fun v -> let (o,opt) = k v in (try_catch o h,opt)) - | Write_ea descr o_s -> Write_ea descr (let (o,opt) = o_s in (try_catch o h,opt)) - | Barrier descr o_s -> Barrier descr (let (o,opt) = o_s in (try_catch o h,opt)) - | Footprint o_s -> Footprint (let (o,opt) = o_s in (try_catch o h,opt)) - | Write_reg descr o_s -> Write_reg descr (let (o,opt) = o_s in (try_catch o h,opt)) - | Escape descr -> Escape descr - | Fail descr -> Fail descr - | Error descr -> Error descr - | Exception e -> h e - | Internal descr o_s -> Internal descr (let (o,opt) = o_s in (try_catch o h ,opt)) -end - -(* For early return, we abuse exceptions by throwing and catching - the return value. The exception type is "either 'r 'e", where "Right e" - represents a proper exception and "Left r" an early return of value "r". *) -type MR 'a 'r 'e = M 'a (either 'r 'e) - -val early_return : forall 'a 'r 'e. 'r -> MR 'a 'r 'e -let early_return r = throw (Left r) - -val catch_early_return : forall 'a 'e. MR 'a 'a 'e -> M 'a 'e -let catch_early_return m = - try_catch m - (function - | Left a -> return a - | Right e -> throw e - end) - -(* Lift to monad with early return by wrapping exceptions *) -val liftR : forall 'a 'r 'e. M 'a 'e -> MR 'a 'r 'e -let liftR m = try_catch m (fun e -> throw (Right e)) - -(* Catch exceptions in the presence of early returns *) -val try_catchR : forall 'a 'r 'e1 'e2. MR 'a 'r 'e1 -> ('e1 -> MR 'a 'r 'e2) -> MR 'a 'r 'e2 -let try_catchR m h = - try_catch m - (function - | Left r -> throw (Left r) - | Right e -> h e - end) - - -val read_mem : forall 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> M 'b 'e -let read_mem rk addr sz = - let addr = address_lifted_of_bitv (bits_of addr) in - let sz = natFromInteger sz in - let k memory_value = - let bitv = of_bits (internal_mem_value memory_value) in - (Done bitv,Nothing) in - Read_mem (rk,addr,sz) k - -val excl_result : forall 'e. unit -> M bool 'e -let excl_result () = - let k successful = (return successful,Nothing) in - Excl_res k - -val write_mem_ea : forall 'a 'e. Bitvector 'a => write_kind -> 'a -> integer -> M unit 'e -let write_mem_ea wk addr sz = - let addr = address_lifted_of_bitv (bits_of addr) in - let sz = natFromInteger sz in - Write_ea (wk,addr,sz) (Done (),Nothing) - -val write_mem_val : forall 'a 'e. Bitvector 'a => 'a -> M bool 'e -let write_mem_val v = - let v = external_mem_value (bits_of v) in - let k successful = (return successful,Nothing) in - Write_memv v k - -val read_reg_aux : forall 'a 'e. Bitvector 'a => reg_name -> M 'a 'e -let read_reg_aux reg = - let k reg_value = - let v = of_bits (internal_reg_value reg_value) in - (Done v,Nothing) in - Read_reg reg k - -let read_reg reg = - read_reg_aux (external_reg_whole reg) -let read_reg_range reg i j = - read_reg_aux (external_reg_slice reg (natFromInteger i,natFromInteger j)) -let read_reg_bit reg i = - read_reg_aux (external_reg_slice reg (natFromInteger i,natFromInteger i)) >>= fun v -> - return (extract_only_element v) -let read_reg_field reg regfield = - read_reg_aux (external_reg_field_whole reg regfield.field_name) -let read_reg_bitfield reg regfield = - read_reg_aux (external_reg_field_whole reg regfield.field_name) >>= fun v -> - return (extract_only_element v) - -let reg_deref = read_reg - -val write_reg_aux : forall 'a 'e. Bitvector 'a => reg_name -> 'a -> M unit 'e -let write_reg_aux reg_name v = - let regval = external_reg_value reg_name (bits_of v) in - Write_reg (reg_name,regval) (Done (), Nothing) - -let write_reg reg v = - write_reg_aux (external_reg_whole reg) v -let write_reg_range reg i j v = - write_reg_aux (external_reg_slice reg (natFromInteger i,natFromInteger j)) v -let write_reg_pos reg i v = - let iN = natFromInteger i in - write_reg_aux (external_reg_slice reg (iN,iN)) [v] -let write_reg_bit = write_reg_pos -let write_reg_field reg regfield v = - write_reg_aux (external_reg_field_whole reg regfield.field_name) v -(*let write_reg_field_bit reg regfield bit = - write_reg_aux (external_reg_field_whole reg regfield.field_name) - (Vector [bit] 0 (is_inc_of_reg reg))*) -let write_reg_field_range reg regfield i j v = - write_reg_aux (external_reg_field_slice reg regfield.field_name (natFromInteger i,natFromInteger j)) v -let write_reg_field_pos reg regfield i v = - write_reg_field_range reg regfield i i [v] -let write_reg_field_bit = write_reg_field_pos - -let write_reg_ref (reg, v) = write_reg reg v - -val barrier : forall 'e. barrier_kind -> M unit 'e -let barrier bk = Barrier bk (Done (), Nothing) - - -val footprint : forall 'e. M unit 'e -let footprint = Footprint (Done (),Nothing) - +open import Prompt_monad +open import {isabelle} `Prompt_monad_extras` val iter_aux : forall 'a 'e. integer -> (integer -> 'a -> M unit 'e) -> list 'a -> M unit 'e let rec iter_aux i f xs = match xs with diff --git a/src/gen_lib/prompt_monad.lem b/src/gen_lib/prompt_monad.lem new file mode 100644 index 00000000..45733caa --- /dev/null +++ b/src/gen_lib/prompt_monad.lem @@ -0,0 +1,168 @@ +open import Pervasives_extra +open import Sail_impl_base +open import Sail_values + +type M 'a 'e = outcome 'a 'e + +val return : forall 'a 'e. 'a -> M 'a 'e +let return a = Done a + +val bind : forall 'a 'b 'e. M 'a 'e -> ('a -> M 'b 'e) -> M 'b 'e +let rec bind m f = match m with + | Done a -> f a + | Read_mem descr k -> Read_mem descr (fun v -> let (o,opt) = k v in (bind o f,opt)) + | Read_reg descr k -> Read_reg descr (fun v -> let (o,opt) = k v in (bind o f,opt)) + | Write_memv descr k -> Write_memv descr (fun v -> let (o,opt) = k v in (bind o f,opt)) + | Excl_res k -> Excl_res (fun v -> let (o,opt) = k v in (bind o f,opt)) + | Write_ea descr o_s -> Write_ea descr (let (o,opt) = o_s in (bind o f,opt)) + | Barrier descr o_s -> Barrier descr (let (o,opt) = o_s in (bind o f,opt)) + | Footprint o_s -> Footprint (let (o,opt) = o_s in (bind o f,opt)) + | Write_reg descr o_s -> Write_reg descr (let (o,opt) = o_s in (bind o f,opt)) + | Escape descr -> Escape descr + | Fail descr -> Fail descr + | Error descr -> Error descr + | Exception e -> Exception e + | Internal descr o_s -> Internal descr (let (o,opt) = o_s in (bind o f ,opt)) +end + +let inline (>>=) = bind +val (>>) : forall 'b 'e. M unit 'e -> M 'b 'e -> M 'b 'e +let inline (>>) m n = m >>= fun (_ : unit) -> n + +val exit : forall 'a 'e. unit -> M 'a 'e +let exit () = Fail Nothing + +val assert_exp : forall 'e. bool -> string -> M unit 'e +let assert_exp exp msg = if exp then Done () else Fail (Just msg) + +val throw : forall 'a 'e. 'e -> M 'a 'e +let throw e = Exception e + +val try_catch : forall 'a 'e1 'e2. M 'a 'e1 -> ('e1 -> M 'a 'e2) -> M 'a 'e2 +let rec try_catch m h = match m with + | Done a -> Done a + | Read_mem descr k -> Read_mem descr (fun v -> let (o,opt) = k v in (try_catch o h,opt)) + | Read_reg descr k -> Read_reg descr (fun v -> let (o,opt) = k v in (try_catch o h,opt)) + | Write_memv descr k -> Write_memv descr (fun v -> let (o,opt) = k v in (try_catch o h,opt)) + | Excl_res k -> Excl_res (fun v -> let (o,opt) = k v in (try_catch o h,opt)) + | Write_ea descr o_s -> Write_ea descr (let (o,opt) = o_s in (try_catch o h,opt)) + | Barrier descr o_s -> Barrier descr (let (o,opt) = o_s in (try_catch o h,opt)) + | Footprint o_s -> Footprint (let (o,opt) = o_s in (try_catch o h,opt)) + | Write_reg descr o_s -> Write_reg descr (let (o,opt) = o_s in (try_catch o h,opt)) + | Escape descr -> Escape descr + | Fail descr -> Fail descr + | Error descr -> Error descr + | Exception e -> h e + | Internal descr o_s -> Internal descr (let (o,opt) = o_s in (try_catch o h ,opt)) +end + +(* For early return, we abuse exceptions by throwing and catching + the return value. The exception type is "either 'r 'e", where "Right e" + represents a proper exception and "Left r" an early return of value "r". *) +type MR 'a 'r 'e = M 'a (either 'r 'e) + +val early_return : forall 'a 'r 'e. 'r -> MR 'a 'r 'e +let early_return r = throw (Left r) + +val catch_early_return : forall 'a 'e. MR 'a 'a 'e -> M 'a 'e +let catch_early_return m = + try_catch m + (function + | Left a -> return a + | Right e -> throw e + end) + +(* Lift to monad with early return by wrapping exceptions *) +val liftR : forall 'a 'r 'e. M 'a 'e -> MR 'a 'r 'e +let liftR m = try_catch m (fun e -> throw (Right e)) + +(* Catch exceptions in the presence of early returns *) +val try_catchR : forall 'a 'r 'e1 'e2. MR 'a 'r 'e1 -> ('e1 -> MR 'a 'r 'e2) -> MR 'a 'r 'e2 +let try_catchR m h = + try_catch m + (function + | Left r -> throw (Left r) + | Right e -> h e + end) + + +val read_mem : forall 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> M 'b 'e +let read_mem rk addr sz = + let addr = address_lifted_of_bitv (bits_of addr) in + let sz = natFromInteger sz in + let k memory_value = + let bitv = of_bits (internal_mem_value memory_value) in + (Done bitv,Nothing) in + Read_mem (rk,addr,sz) k + +val excl_result : forall 'e. unit -> M bool 'e +let excl_result () = + let k successful = (return successful,Nothing) in + Excl_res k + +val write_mem_ea : forall 'a 'e. Bitvector 'a => write_kind -> 'a -> integer -> M unit 'e +let write_mem_ea wk addr sz = + let addr = address_lifted_of_bitv (bits_of addr) in + let sz = natFromInteger sz in + Write_ea (wk,addr,sz) (Done (),Nothing) + +val write_mem_val : forall 'a 'e. Bitvector 'a => 'a -> M bool 'e +let write_mem_val v = + let v = external_mem_value (bits_of v) in + let k successful = (return successful,Nothing) in + Write_memv v k + +val read_reg_aux : forall 'a 'e. Bitvector 'a => reg_name -> M 'a 'e +let read_reg_aux reg = + let k reg_value = + let v = of_bits (internal_reg_value reg_value) in + (Done v,Nothing) in + Read_reg reg k + +let read_reg reg = + read_reg_aux (external_reg_whole reg) +let read_reg_range reg i j = + read_reg_aux (external_reg_slice reg (natFromInteger i,natFromInteger j)) +let read_reg_bit reg i = + read_reg_aux (external_reg_slice reg (natFromInteger i,natFromInteger i)) >>= fun v -> + return (extract_only_element v) +let read_reg_field reg regfield = + read_reg_aux (external_reg_field_whole reg regfield.field_name) +let read_reg_bitfield reg regfield = + read_reg_aux (external_reg_field_whole reg regfield.field_name) >>= fun v -> + return (extract_only_element v) + +let reg_deref = read_reg + +val write_reg_aux : forall 'a 'e. Bitvector 'a => reg_name -> 'a -> M unit 'e +let write_reg_aux reg_name v = + let regval = external_reg_value reg_name (bits_of v) in + Write_reg (reg_name,regval) (Done (), Nothing) + +let write_reg reg v = + write_reg_aux (external_reg_whole reg) v +let write_reg_range reg i j v = + write_reg_aux (external_reg_slice reg (natFromInteger i,natFromInteger j)) v +let write_reg_pos reg i v = + let iN = natFromInteger i in + write_reg_aux (external_reg_slice reg (iN,iN)) [v] +let write_reg_bit = write_reg_pos +let write_reg_field reg regfield v = + write_reg_aux (external_reg_field_whole reg regfield.field_name) v +(*let write_reg_field_bit reg regfield bit = + write_reg_aux (external_reg_field_whole reg regfield.field_name) + (Vector [bit] 0 (is_inc_of_reg reg))*) +let write_reg_field_range reg regfield i j v = + write_reg_aux (external_reg_field_slice reg regfield.field_name (natFromInteger i,natFromInteger j)) v +let write_reg_field_pos reg regfield i v = + write_reg_field_range reg regfield i i [v] +let write_reg_field_bit = write_reg_field_pos + +let write_reg_ref (reg, v) = write_reg reg v + +val barrier : forall 'e. barrier_kind -> M unit 'e +let barrier bk = Barrier bk (Done (), Nothing) + + +val footprint : forall 'e. M unit 'e +let footprint = Footprint (Done (),Nothing) diff --git a/src/gen_lib/sail_operators.lem b/src/gen_lib/sail_operators.lem index 230ab84e..ada91bd0 100644 --- a/src/gen_lib/sail_operators.lem +++ b/src/gen_lib/sail_operators.lem @@ -5,53 +5,22 @@ open import Sail_values (*** Bit vector operations *) -val concat_vec : forall 'a 'b 'c. Bitvector 'a, Bitvector 'b, Bitvector 'c => 'a -> 'b -> 'c -let concat_vec l r = of_bits (bits_of l ++ bits_of r) +val concat_bv : forall 'a 'b 'c. Bitvector 'a, Bitvector 'b, Bitvector 'c => 'a -> 'b -> 'c +let concat_bv l r = of_bits (bits_of l ++ bits_of r) -val cons_vec : forall 'a 'b 'c. Bitvector 'a, Bitvector 'b => bitU -> 'a -> 'b -let cons_vec b v = of_bits (b :: bits_of v) +val cons_bv : forall 'a 'b 'c. Bitvector 'a, Bitvector 'b => bitU -> 'a -> 'b +let cons_bv b v = of_bits (b :: bits_of v) -let bool_of_vec v = extract_only_element (bits_of v) -let vec_of_bit len b = of_bits (extz_bits len [b]) -let cast_unit_vec b = of_bits [b] +let bool_of_bv v = extract_only_element (bits_of v) +let cast_unit_bv b = of_bits [b] +let bv_of_bit len b = of_bits (extz_bits len [b]) +let int_of_bv sign = if sign then signed else unsigned let most_significant v = match bits_of v with | b :: _ -> b | _ -> failwith "most_significant applied to empty vector" end -let hardware_mod (a: integer) (b:integer) : integer = - if a < 0 && b < 0 - then (abs a) mod (abs b) - else if (a < 0 && b >= 0) - then (a mod b) - b - else a mod b - -(* There are different possible answers for integer divide regarding -rounding behaviour on negative operands. Positive operands always -round down so derive the one we want (trucation towards zero) from -that *) -let hardware_quot (a:integer) (b:integer) : integer = - let q = (abs a) / (abs b) in - if ((a<0) = (b<0)) then - q (* same sign -- result positive *) - else - ~q (* different sign -- result negative *) - -let int_of_vec sign = if sign then signed else unsigned -let vec_of_int len n = of_bits (bits_of_int len n) - -let max_64u = (integerPow 2 64) - 1 -let max_64 = (integerPow 2 63) - 1 -let min_64 = 0 - (integerPow 2 63) -let max_32u = (4294967295 : integer) -let max_32 = (2147483647 : integer) -let min_32 = (0 - 2147483648 : integer) -let max_8 = (127 : integer) -let min_8 = (0 - 128 : integer) -let max_5 = (31 : integer) -let min_5 = (0 - 32 : integer) - let get_max_representable_in sign (n : integer) : integer = if (n = 64) then match sign with | true -> max_64 | false -> max_64u end else if (n=32) then match sign with | true -> max_32 | false -> max_32u end @@ -68,106 +37,106 @@ let get_min_representable_in _ (n : integer) : integer = else if n = 5 then min_5 else 0 - (integerPow 2 (natFromInteger n)) -val bitwise_binop_vec : forall 'a. Bitvector 'a => +val bitwise_binop_bv : forall 'a. Bitvector 'a => (bool -> bool -> bool) -> 'a -> 'a -> 'a -let bitwise_binop_vec op l r = of_bits (binop_bits op (bits_of l) (bits_of r)) +let bitwise_binop_bv op l r = of_bits (binop_bits op (bits_of l) (bits_of r)) -let and_vec = bitwise_binop_vec (&&) -let or_vec = bitwise_binop_vec (||) -let xor_vec = bitwise_binop_vec xor -let not_vec v = of_bits (not_bits (bits_of v)) +let and_bv = bitwise_binop_bv (&&) +let or_bv = bitwise_binop_bv (||) +let xor_bv = bitwise_binop_bv xor +let not_bv v = of_bits (not_bits (bits_of v)) -val arith_op_vec : forall 'a 'b. Bitvector 'a, Bitvector 'b => +val arith_op_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> 'b -let arith_op_vec op sign size l r = - let (l',r') = (int_of_vec sign l, int_of_vec sign r) in +let arith_op_bv op sign size l r = + let (l',r') = (int_of_bv sign l, int_of_bv sign r) in let n = op l' r' in - of_bits (bits_of_int (size * length l) n) + of_int (size * length l) n -let add_vec = arith_op_vec integerAdd false 1 -let addS_vec = arith_op_vec integerAdd true 1 -let sub_vec = arith_op_vec integerMinus false 1 -let mult_vec = arith_op_vec integerMult false 2 -let multS_vec = arith_op_vec integerMult true 2 +let add_bv = arith_op_bv integerAdd false 1 +let addS_bv = arith_op_bv integerAdd true 1 +let sub_bv = arith_op_bv integerMinus false 1 +let mult_bv = arith_op_bv integerMult false 2 +let multS_bv = arith_op_bv integerMult true 2 let inline add_mword = Machine_word.plus let inline sub_mword = Machine_word.minus val mult_mword : forall 'a 'b. Size 'b => mword 'a -> mword 'a -> mword 'b let mult_mword l r = times (zeroExtend l) (zeroExtend r) -val arith_op_vec_int : forall 'a 'b. Bitvector 'a, Bitvector 'b => +val arith_op_bv_int : forall 'a 'b. Bitvector 'a, Bitvector 'b => (integer -> integer -> integer) -> bool -> integer -> 'a -> integer -> 'b -let arith_op_vec_int op sign size l r = - let l' = int_of_vec sign l in +let arith_op_bv_int op sign size l r = + let l' = int_of_bv sign l in let n = op l' r in - of_bits (bits_of_int (size * length l) n) + of_int (size * length l) n -let add_vec_int = arith_op_vec_int integerAdd false 1 -let addS_vec_int = arith_op_vec_int integerAdd true 1 -let sub_vec_int = arith_op_vec_int integerMinus false 1 -let mult_vec_int = arith_op_vec_int integerMult false 2 -let multS_vec_int = arith_op_vec_int integerMult true 2 +let add_bv_int = arith_op_bv_int integerAdd false 1 +let addS_bv_int = arith_op_bv_int integerAdd true 1 +let sub_bv_int = arith_op_bv_int integerMinus false 1 +let mult_bv_int = arith_op_bv_int integerMult false 2 +let multS_bv_int = arith_op_bv_int integerMult true 2 -val arith_op_int_vec : forall 'a 'b. Bitvector 'a, Bitvector 'b => +val arith_op_int_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => (integer -> integer -> integer) -> bool -> integer -> integer -> 'a -> 'b -let arith_op_int_vec op sign size l r = - let r' = int_of_vec sign r in +let arith_op_int_bv op sign size l r = + let r' = int_of_bv sign r in let n = op l r' in - of_bits (bits_of_int (size * length r) n) + of_int (size * length r) n -let add_int_vec = arith_op_int_vec integerAdd false 1 -let addS_int_vec = arith_op_int_vec integerAdd true 1 -let sub_int_vec = arith_op_int_vec integerMinus false 1 -let mult_int_vec = arith_op_int_vec integerMult false 2 -let multS_int_vec = arith_op_int_vec integerMult true 2 +let add_int_bv = arith_op_int_bv integerAdd false 1 +let addS_int_bv = arith_op_int_bv integerAdd true 1 +let sub_int_bv = arith_op_int_bv integerMinus false 1 +let mult_int_bv = arith_op_int_bv integerMult false 2 +let multS_int_bv = arith_op_int_bv integerMult true 2 -let arith_op_vec_bit op sign (size : integer) l r = - let l' = int_of_vec sign l in +let arith_op_bv_bit op sign (size : integer) l r = + let l' = int_of_bv sign l in let n = op l' (match r with | B1 -> (1 : integer) | _ -> 0 end) in - of_bits (bits_of_int (size * length l) n) + of_int (size * length l) n -let add_vec_bit = arith_op_vec_bit integerAdd false 1 -let addS_vec_bit = arith_op_vec_bit integerAdd true 1 -let sub_vec_bit = arith_op_vec_bit integerMinus true 1 +let add_bv_bit = arith_op_bv_bit integerAdd false 1 +let addS_bv_bit = arith_op_bv_bit integerAdd true 1 +let sub_bv_bit = arith_op_bv_bit integerMinus true 1 -val arith_op_overflow_vec : forall 'a 'b. Bitvector 'a, Bitvector 'b => +val arith_op_overflow_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> ('b * bitU * bitU) -let arith_op_overflow_vec op sign size l r = +let arith_op_overflow_bv op sign size l r = let len = length l in let act_size = len * size in - let (l_sign,r_sign) = (int_of_vec sign l,int_of_vec sign r) in - let (l_unsign,r_unsign) = (int_of_vec false l,int_of_vec false r) in + let (l_sign,r_sign) = (int_of_bv sign l,int_of_bv sign r) in + let (l_unsign,r_unsign) = (int_of_bv false l,int_of_bv false r) in let n = op l_sign r_sign in let n_unsign = op l_unsign r_unsign in - let correct_size = bits_of_int act_size n in + let correct_size = of_int act_size n in let one_more_size_u = bits_of_int (act_size + 1) n_unsign in let overflow = if n <= get_max_representable_in sign len && n >= get_min_representable_in sign len then B0 else B1 in let c_out = most_significant one_more_size_u in - (of_bits correct_size,overflow,c_out) + (correct_size,overflow,c_out) -let add_overflow_vec = arith_op_overflow_vec integerAdd false 1 -let add_overflow_vec_signed = arith_op_overflow_vec integerAdd true 1 -let sub_overflow_vec = arith_op_overflow_vec integerMinus false 1 -let sub_overflow_vec_signed = arith_op_overflow_vec integerMinus true 1 -let mult_overflow_vec = arith_op_overflow_vec integerMult false 2 -let mult_overflow_vec_signed = arith_op_overflow_vec integerMult true 2 +let add_overflow_bv = arith_op_overflow_bv integerAdd false 1 +let add_overflow_bv_signed = arith_op_overflow_bv integerAdd true 1 +let sub_overflow_bv = arith_op_overflow_bv integerMinus false 1 +let sub_overflow_bv_signed = arith_op_overflow_bv integerMinus true 1 +let mult_overflow_bv = arith_op_overflow_bv integerMult false 2 +let mult_overflow_bv_signed = arith_op_overflow_bv integerMult true 2 -val arith_op_overflow_vec_bit : forall 'a 'b. Bitvector 'a, Bitvector 'b => +val arith_op_overflow_bv_bit : forall 'a 'b. Bitvector 'a, Bitvector 'b => (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> ('b * bitU * bitU) -let arith_op_overflow_vec_bit op sign size l r_bit = +let arith_op_overflow_bv_bit op sign size l r_bit = let act_size = length l * size in - let l' = int_of_vec sign l in - let l_u = int_of_vec false l in + let l' = int_of_bv sign l in + let l_u = int_of_bv false l in let (n,nu,changed) = match r_bit with | B1 -> (op l' 1, op l_u 1, true) | B0 -> (l',l_u,false) - | BU -> failwith "arith_op_overflow_vec_bit applied to undefined bit" + | BU -> failwith "arith_op_overflow_bv_bit applied to undefined bit" end in - let correct_size = bits_of_int act_size n in + let correct_size = of_int act_size n in let one_larger = bits_of_int (act_size + 1) nu in let overflow = if changed @@ -175,32 +144,35 @@ let arith_op_overflow_vec_bit op sign size l r_bit = if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size then B0 else B1 else B0 in - (of_bits correct_size,overflow,most_significant one_larger) + (correct_size,overflow,most_significant one_larger) -let add_overflow_vec_bit = arith_op_overflow_vec_bit integerAdd false 1 -let add_overflow_vec_bit_signed = arith_op_overflow_vec_bit integerAdd true 1 -let sub_overflow_vec_bit = arith_op_overflow_vec_bit integerMinus false 1 -let sub_overflow_vec_bit_signed = arith_op_overflow_vec_bit integerMinus true 1 +let add_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd false 1 +let add_overflow_bv_bit_signed = arith_op_overflow_bv_bit integerAdd true 1 +let sub_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus false 1 +let sub_overflow_bv_bit_signed = arith_op_overflow_bv_bit integerMinus true 1 -type shift = LL_shift | RR_shift | LL_rot | RR_rot +type shift = LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot -val shift_op_vec : forall 'a. Bitvector 'a => shift -> 'a -> integer -> 'a -let shift_op_vec op v n = +val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> 'a +let shift_op_bv op v n = match op with | LL_shift -> of_bits (get_bits true v n (length v - 1) ++ repeat [B0] n) | RR_shift -> of_bits (repeat [B0] n ++ get_bits true v 0 (length v - n - 1)) + | RR_shift_arith -> + of_bits (repeat [most_significant v] n ++ get_bits true v 0 (length v - n - 1)) | LL_rot -> of_bits (get_bits true v n (length v - 1) ++ get_bits true v 0 (n - 1)) | RR_rot -> of_bits (get_bits false v 0 (n - 1) ++ get_bits false v n (length v - 1)) end -let shiftl = shift_op_vec LL_shift (*"<<"*) -let shiftr = shift_op_vec RR_shift (*">>"*) -let rotl = shift_op_vec LL_rot (*"<<<"*) -let rotr = shift_op_vec LL_rot (*">>>"*) +let shiftl_bv = shift_op_bv LL_shift (*"<<"*) +let shiftr_bv = shift_op_bv RR_shift (*">>"*) +let arith_shiftr_bv = shift_op_bv RR_shift_arith +let rotl_bv = shift_op_bv LL_rot (*"<<<"*) +let rotr_bv = shift_op_bv LL_rot (*">>>"*) let shiftl_mword w n = Machine_word.shiftLeft w (natFromInteger n) let shiftr_mword w n = Machine_word.shiftRight w (natFromInteger n) @@ -212,11 +184,11 @@ let rec arith_op_no0 (op : integer -> integer -> integer) l r = then Nothing else Just (op l r) -val arith_op_vec_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b => +val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b => (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> 'b -let arith_op_vec_no0 op sign size l r = +let arith_op_bv_no0 op sign size l r = let act_size = length l * size in - let (l',r') = (int_of_vec sign l,int_of_vec sign r) in + let (l',r') = (int_of_bv sign l,int_of_bv sign r) in let n = arith_op_no0 op l' r' in let (representable,n') = match n with @@ -225,80 +197,42 @@ let arith_op_vec_no0 op sign size l r = n' >= get_min_representable_in sign act_size, n') | _ -> (false,0) end in - of_bits (if representable then bits_of_int act_size n' else repeat [BU] act_size) + if representable then (of_int act_size n') else (of_bits (repeat [BU] act_size)) -let mod_vec = arith_op_vec_no0 hardware_mod false 1 -let quot_vec = arith_op_vec_no0 hardware_quot false 1 -let quot_vec_signed = arith_op_vec_no0 hardware_quot true 1 +let mod_bv = arith_op_bv_no0 hardware_mod false 1 +let quot_bv = arith_op_bv_no0 hardware_quot false 1 +let quot_bv_signed = arith_op_bv_no0 hardware_quot true 1 let mod_mword = Machine_word.modulo let quot_mword = Machine_word.unsignedDivide let quot_mword_signed = Machine_word.signedDivide -val arith_op_overflow_vec_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b => - (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> ('b * bitU * bitU) -let arith_op_overflow_vec_no0 op sign size l r = - let rep_size = length r * size in - let act_size = length l * size in - let (l',r') = (int_of_vec sign l,int_of_vec sign r) in - let (l_u,r_u) = (int_of_vec false l,int_of_vec false r) in - let n = arith_op_no0 op l' r' in - let n_u = arith_op_no0 op l_u r_u in - let (representable,n',n_u') = - match (n, n_u) with - | (Just n',Just n_u') -> - ((n' <= get_max_representable_in sign rep_size && - n' >= (get_min_representable_in sign rep_size)), n', n_u') - | _ -> (true,0,0) - end in - let (correct_size,one_more) = - if representable then - (bits_of_int act_size n', bits_of_int (act_size + 1) n_u') - else - (repeat [BU] act_size, repeat [BU] (act_size + 1)) in - let overflow = if representable then B0 else B1 in - (of_bits correct_size,overflow,most_significant one_more) - -let quot_overflow_vec = arith_op_overflow_vec_no0 hardware_quot false 1 -let quot_overflow_vec_signed = arith_op_overflow_vec_no0 hardware_quot true 1 - -let arith_op_vec_int_no0 op sign size l r = - arith_op_vec_no0 op sign size l (of_bits (bits_of_int (length l) r)) - -let quot_vec_int = arith_op_vec_int_no0 hardware_quot false 1 -let mod_vec_int = arith_op_vec_int_no0 hardware_mod false 1 - -let replicate_bits v count = of_bits (repeat v count) -let duplicate bit len = replicate_bits [bit] len - -let lt = (<) -let gt = (>) -let lteq = (<=) -let gteq = (>=) +let arith_op_bv_int_no0 op sign size l r = + arith_op_bv_no0 op sign size l (of_int (length l) r) -val eq : forall 'a. Eq 'a => 'a -> 'a -> bool -let eq l r = (l = r) +let quot_bv_int = arith_op_bv_int_no0 hardware_quot false 1 +let mod_bv_int = arith_op_bv_int_no0 hardware_mod false 1 -val eq_vec : forall 'a. Bitvector 'a => 'a -> 'a -> bool -let eq_vec l r = (unsigned l = unsigned r) +let replicate_bits_bv v count = of_bits (repeat (bits_of v) count) +let duplicate_bit_bv bit len = replicate_bits_bv [bit] len -val neq : forall 'a. Eq 'a => 'a -> 'a -> bool -let neq l r = (l <> r) +val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool +let eq_bv l r = (unsigned l = unsigned r) -val neq_vec : forall 'a. Bitvector 'a => 'a -> 'a -> bool -let neq_vec l r = (unsigned l <> unsigned r) +val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool +let neq_bv l r = (unsigned l <> unsigned r) -val ucmp_vec : forall 'a. Bitvector 'a => (integer -> integer -> bool) -> 'a -> 'a -> bool -let ucmp_vec cmp l r = cmp (unsigned l) (unsigned r) +val ucmp_bv : forall 'a. Bitvector 'a => (integer -> integer -> bool) -> 'a -> 'a -> bool +let ucmp_bv cmp l r = cmp (unsigned l) (unsigned r) -val scmp_vec : forall 'a. Bitvector 'a => (integer -> integer -> bool) -> 'a -> 'a -> bool -let scmp_vec cmp l r = cmp (signed l) (signed r) +val scmp_bv : forall 'a. Bitvector 'a => (integer -> integer -> bool) -> 'a -> 'a -> bool +let scmp_bv cmp l r = cmp (signed l) (signed r) -let ult_vec = ucmp_vec (<) -let slt_vec = scmp_vec (<) -let ugt_vec = ucmp_vec (>) -let sgt_vec = scmp_vec (>) -let ulteq_vec = ucmp_vec (<=) -let slteq_vec = scmp_vec (<=) -let ugteq_vec = ucmp_vec (>=) -let sgteq_vec = scmp_vec (>=) +let ult_bv = ucmp_bv (<) +let slt_bv = scmp_bv (<) +let ugt_bv = ucmp_bv (>) +let sgt_bv = scmp_bv (>) +let ulteq_bv = ucmp_bv (<=) +let slteq_bv = scmp_bv (<=) +let ugteq_bv = ucmp_bv (>=) +let sgteq_bv = scmp_bv (>=) diff --git a/src/gen_lib/sail_operators_bitlists.lem b/src/gen_lib/sail_operators_bitlists.lem new file mode 100644 index 00000000..374628a4 --- /dev/null +++ b/src/gen_lib/sail_operators_bitlists.lem @@ -0,0 +1,179 @@ +open import Pervasives_extra +open import Machine_word +open import Sail_impl_base +open import Sail_values +open import Sail_operators + +(* Specialisation of operators to bit lists *) + +val access_vec_inc : list bitU -> integer -> bitU +let access_vec_inc = access_bv_inc + +val access_vec_dec : list bitU -> integer -> bitU +let access_vec_dec = access_bv_dec + +val update_vec_inc : list bitU -> integer -> bitU -> list bitU +let update_vec_inc = update_bv_inc + +val update_vec_dec : list bitU -> integer -> bitU -> list bitU +let update_vec_dec = update_bv_dec + +val subrange_vec_inc : list bitU -> integer -> integer -> list bitU +let subrange_vec_inc = subrange_bv_inc + +val subrange_vec_dec : list bitU -> integer -> integer -> list bitU +let subrange_vec_dec = subrange_bv_dec + +val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU +let update_subrange_vec_inc = update_subrange_bv_inc + +val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU +let update_subrange_vec_dec = update_subrange_bv_dec + +val extz_vec : integer -> list bitU -> list bitU +let extz_vec = extz_bv + +val exts_vec : integer -> list bitU -> list bitU +let exts_vec = exts_bv + +val concat_vec : list bitU -> list bitU -> list bitU +let concat_vec = concat_bv + +val cons_vec : bitU -> list bitU -> list bitU +let cons_vec = cons_bv + +val bool_of_vec : mword ty1 -> bitU +let bool_of_vec = bool_of_bv + +val cast_unit_vec : bitU -> mword ty1 +let cast_unit_vec = cast_unit_bv + +val vec_of_bit : integer -> bitU -> list bitU +let vec_of_bit = bv_of_bit + +val msb : list bitU -> bitU +let msb = most_significant + +val int_of_vec : bool -> list bitU -> integer +let int_of_vec = int_of_bv + +val and_vec : list bitU -> list bitU -> list bitU +val or_vec : list bitU -> list bitU -> list bitU +val xor_vec : list bitU -> list bitU -> list bitU +val not_vec : list bitU -> list bitU +let and_vec = and_bv +let or_vec = or_bv +let xor_vec = xor_bv +let not_vec = not_bv + +val add_vec : list bitU -> list bitU -> list bitU +val addS_vec : list bitU -> list bitU -> list bitU +val sub_vec : list bitU -> list bitU -> list bitU +val mult_vec : list bitU -> list bitU -> list bitU +val multS_vec : list bitU -> list bitU -> list bitU +let add_vec = add_bv +let addS_vec = addS_bv +let sub_vec = sub_bv +let mult_vec = mult_bv +let multS_vec = multS_bv + +val add_vec_int : list bitU -> integer -> list bitU +val addS_vec_int : list bitU -> integer -> list bitU +val sub_vec_int : list bitU -> integer -> list bitU +val mult_vec_int : list bitU -> integer -> list bitU +val multS_vec_int : list bitU -> integer -> list bitU +let add_vec_int = add_bv_int +let addS_vec_int = addS_bv_int +let sub_vec_int = sub_bv_int +let mult_vec_int = mult_bv_int +let multS_vec_int = multS_bv_int + +val add_int_vec : integer -> list bitU -> list bitU +val addS_int_vec : integer -> list bitU -> list bitU +val sub_int_vec : integer -> list bitU -> list bitU +val mult_int_vec : integer -> list bitU -> list bitU +val multS_int_vec : integer -> list bitU -> list bitU +let add_int_vec = add_int_bv +let addS_int_vec = addS_int_bv +let sub_int_vec = sub_int_bv +let mult_int_vec = mult_int_bv +let multS_int_vec = multS_int_bv + +val add_vec_bit : list bitU -> bitU -> list bitU +val addS_vec_bit : list bitU -> bitU -> list bitU +val sub_vec_bit : list bitU -> bitU -> list bitU +let add_vec_bit = add_bv_bit +let addS_vec_bit = addS_bv_bit +let sub_vec_bit = sub_bv_bit + +val add_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val add_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +val mult_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +let add_overflow_vec = add_overflow_bv +let add_overflow_vec_signed = add_overflow_bv_signed +let sub_overflow_vec = sub_overflow_bv +let sub_overflow_vec_signed = sub_overflow_bv_signed +let mult_overflow_vec = mult_overflow_bv +let mult_overflow_vec_signed = mult_overflow_bv_signed + +val add_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) +val add_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) +let add_overflow_vec_bit = add_overflow_bv_bit +let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed +let sub_overflow_vec_bit = sub_overflow_bv_bit +let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed + +val shiftl : list bitU -> integer -> list bitU +val shiftr : list bitU -> integer -> list bitU +val arith_shiftr : list bitU -> integer -> list bitU +val rotl : list bitU -> integer -> list bitU +val rotr : list bitU -> integer -> list bitU +let shiftl = shiftl_bv +let shiftr = shiftr_bv +let arith_shiftr = arith_shiftr_bv +let rotl = rotl_bv +let rotr = rotr_bv + +val mod_vec : list bitU -> list bitU -> list bitU +val quot_vec : list bitU -> list bitU -> list bitU +val quot_vec_signed : list bitU -> list bitU -> list bitU +let mod_vec = mod_bv +let quot_vec = quot_bv +let quot_vec_signed = quot_bv_signed + +val mod_vec_int : list bitU -> integer -> list bitU +val quot_vec_int : list bitU -> integer -> list bitU +let mod_vec_int = mod_bv_int +let quot_vec_int = quot_bv_int + +val replicate_bits : list bitU -> integer -> list bitU +let replicate_bits = replicate_bits_bv + +val duplicate : bitU -> integer -> list bitU +let duplicate = duplicate_bit_bv + +val eq_vec : list bitU -> list bitU -> bool +val neq_vec : list bitU -> list bitU -> bool +val ult_vec : list bitU -> list bitU -> bool +val slt_vec : list bitU -> list bitU -> bool +val ugt_vec : list bitU -> list bitU -> bool +val sgt_vec : list bitU -> list bitU -> bool +val ulteq_vec : list bitU -> list bitU -> bool +val slteq_vec : list bitU -> list bitU -> bool +val ugteq_vec : list bitU -> list bitU -> bool +val sgteq_vec : list bitU -> list bitU -> bool +let eq_vec = eq_bv +let neq_vec = neq_bv +let ult_vec = ult_bv +let slt_vec = slt_bv +let ugt_vec = ugt_bv +let sgt_vec = sgt_bv +let ulteq_vec = ulteq_bv +let slteq_vec = slteq_bv +let ugteq_vec = ugteq_bv +let sgteq_vec = sgteq_bv diff --git a/src/gen_lib/sail_operators_mwords.lem b/src/gen_lib/sail_operators_mwords.lem index ff25c37b..7fa09b9b 100644 --- a/src/gen_lib/sail_operators_mwords.lem +++ b/src/gen_lib/sail_operators_mwords.lem @@ -2,600 +2,178 @@ open import Pervasives_extra open import Machine_word open import Sail_impl_base open import Sail_values - -(* Translating between a type level number (itself 'n) and an integer *) - -let size_itself_int x = integerFromNat (size_itself x) - -(* NB: the corresponding sail type is forall 'n. atom('n) -> itself('n), - the actual integer is ignored. *) - -val make_the_value : forall 'n. integer -> itself 'n -let inline make_the_value x = the_value - -(*** Bit vector operations *) - -let bitvector_length bs = integerFromNat (word_length bs) - -(*val set_bitvector_start : forall 'a. (integer * bitvector 'a) -> bitvector 'a -let set_bitvector_start (new_start, Bitvector bs _ is_inc) = - Bitvector bs new_start is_inc - -let reset_bitvector_start v = - set_bitvector_start (if (bvget_dir v) then 0 else (bvlength v - 1), v) - -let set_bitvector_start_to_length v = - set_bitvector_start (bvlength v - 1, v) - -let bitvector_concat (Bitvector bs start is_inc, Bitvector bs' _ _) = - Bitvector (word_concat bs bs') start is_inc*) - -let bitvector_concat (bs, bs') = word_concat bs bs' - -let inline (^^^) = bitvector_concat - -val bvslice : forall 'a 'b. Size 'a => bool -> integer -> bitvector 'a -> integer -> integer -> bitvector 'b -let bvslice is_inc start bs i j = - let iN = natFromInteger i in - let jN = natFromInteger j in - let startN = natFromInteger start in - let top = word_length bs - 1 in - let (hi,lo) = if is_inc then (top+startN-iN,top+startN-jN) else (top-startN+iN,top-startN+jN) in - word_extract lo hi bs - -let bitvector_subrange_inc (start, v, i, j) = bvslice true start v i j -let bitvector_subrange_dec (start, v, i, j) = bvslice false start v i j - -let vector_subrange_bl_dec (start, v, i, j) = - let v' = slice (bvec_to_vec false start v) i j in - get_elems v' - -(* this is for the vector slicing introduced in vector-concat patterns: i and j -index into the "raw data", the list of bits. Therefore getting the bit list is -easy, but the start index has to be transformed to match the old vector start -and the direction. *) -val bvslice_raw : forall 'a 'b. Size 'b => bitvector 'a -> integer -> integer -> bitvector 'b -let bvslice_raw bs i j = - let iN = natFromInteger i in - let jN = natFromInteger j in - (*let bits =*) word_extract iN jN bs (*in - let len = integerFromNat (word_length bits) in - Bitvector bits (if is_inc then 0 else len - 1) is_inc*) - -val bvupdate_aux : forall 'a 'b. Size 'a => bool -> integer -> bitvector 'a -> integer -> integer -> list bitU -> bitvector 'a -let bvupdate_aux is_inc start bs i j bs' = - let bits = update_aux is_inc start (List.map to_bitU (bitlistFromWord bs)) i j bs' in - wordFromBitlist (List.map of_bitU bits) - (*let iN = natFromInteger i in - let jN = natFromInteger j in - let startN = natFromInteger start in - let top = word_length bs - 1 in - let (hi,lo) = if is_inc then (top+startN-iN,top+startN-jN) else (top-startN+iN,top-startN+jN) in - word_update bs lo hi bs'*) - -val bvupdate : forall 'a 'b. Size 'a => bool -> integer -> bitvector 'a -> integer -> integer -> bitvector 'b -> bitvector 'a -let bvupdate is_inc start bs i j bs' = - bvupdate_aux is_inc start bs i j (List.map to_bitU (bitlistFromWord bs')) - -val bvaccess : forall 'a. Size 'a => bool -> integer -> bitvector 'a -> integer -> bitU -let bvaccess is_inc start bs n = bool_to_bitU ( - let top = integerFromNat (word_length bs) - 1 in - if is_inc then getBit bs (natFromInteger (top + start - n)) - else getBit bs (natFromInteger (top + n - start))) - -val bvupdate_pos : forall 'a. Size 'a => bool -> integer -> bitvector 'a -> integer -> bitU -> bitvector 'a -let bvupdate_pos is_inc start v n b = - bvupdate_aux is_inc start v n n [b] - -let bitvector_access_inc (start, v, i) = bvaccess true start v i -let bitvector_access_dec (start, v, i) = bvaccess false start v i -let bitvector_update_pos_dec (start, v, i, b) = bvupdate_pos false start v i b -let bitvector_update_subrange_dec (start, v, i, j, v') = bvupdate false start v i j v' - -val extract_only_bit : bitvector ty1 -> bitU -let extract_only_bit elems = - let l = word_length elems in - if l = 1 then - bool_to_bitU (msb elems) - else if l = 0 then - failwith "extract_single_bit called for empty vector" - else - failwith "extract_single_bit called for vector with more bits" - - -let norm_dec v = v (*reset_bitvector_start*) -let adjust_start_index (start, v) = v (*set_bitvector_start (start, v)*) - -let cast_vec_bool v = bitU_to_bool (extract_only_bit v) -let cast_bit_vec_basic (start, len, b) = vec_to_bvec (Vector [b] start false) -let cast_boolvec_bitvec (Vector bs start inc) = - vec_to_bvec (Vector (List.map bool_to_bitU bs) start inc) -let cast_vec_bl v = List.map bool_to_bitU (bitlistFromWord v) -let cast_int_vec n = wordFromInteger n -let cast_bl_vec (start, len, bs) = wordFromBitlist (List.map bitU_to_bool bs) -let cast_bl_svec (start, len, bs) = cast_int_vec (bitlist_to_signed bs) - -let pp_bitu_vector (Vector elems start inc) = - let elems_pp = List.foldl (fun acc elem -> acc ^ showBitU elem) "" elems in - "Vector [" ^ elems_pp ^ "] " ^ show start ^ " " ^ show inc - - -let most_significant v = - if word_length v = 0 then - failwith "most_significant applied to empty vector" - else - bool_to_bitU (msb v) - -let bitwise_not_bitlist = List.map bitwise_not_bit - -let bitwise_not bs = lNot bs - -let bitwise_binop op (bsl, bsr) = (op bsl bsr) - -let bitwise_and x = bitwise_binop lAnd x -let bitwise_or x = bitwise_binop lOr x -let bitwise_xor x = bitwise_binop lXor x - -(*let unsigned bs : integer = unsignedIntegerFromWord bs*) -let unsigned_big = unsigned - -let signed v : integer = signedIntegerFromWord v - -let hardware_mod (a: integer) (b:integer) : integer = - if a < 0 && b < 0 - then (abs a) mod (abs b) - else if (a < 0 && b >= 0) - then (a mod b) - b - else a mod b - -(* There are different possible answers for integer divide regarding -rounding behaviour on negative operands. Positive operands always -round down so derive the one we want (trucation towards zero) from -that *) -let hardware_quot (a:integer) (b:integer) : integer = - let q = (abs a) / (abs b) in - if ((a<0) = (b<0)) then - q (* same sign -- result positive *) - else - ~q (* different sign -- result negative *) - -let quot_signed = hardware_quot - - -let signed_big = signed - -let to_num sign = if sign then signed else unsigned - -let max_64u = (integerPow 2 64) - 1 -let max_64 = (integerPow 2 63) - 1 -let min_64 = 0 - (integerPow 2 63) -let max_32u = (4294967295 : integer) -let max_32 = (2147483647 : integer) -let min_32 = (0 - 2147483648 : integer) -let max_8 = (127 : integer) -let min_8 = (0 - 128 : integer) -let max_5 = (31 : integer) -let min_5 = (0 - 32 : integer) - -let get_max_representable_in sign (n : integer) : integer = - if (n = 64) then match sign with | true -> max_64 | false -> max_64u end - else if (n=32) then match sign with | true -> max_32 | false -> max_32u end - else if (n=8) then max_8 - else if (n=5) then max_5 - else match sign with | true -> integerPow 2 ((natFromInteger n) -1) - | false -> integerPow 2 (natFromInteger n) - end - -let get_min_representable_in _ (n : integer) : integer = - if n = 64 then min_64 - else if n = 32 then min_32 - else if n = 8 then min_8 - else if n = 5 then min_5 - else 0 - (integerPow 2 (natFromInteger n)) - -val to_bin_aux : natural -> list bitU -let rec to_bin_aux x = - if x = 0 then [] - else (if x mod 2 = 1 then B1 else B0) :: to_bin_aux (x / 2) -let to_bin n = List.reverse (to_bin_aux n) - -val pad_zero : list bitU -> integer -> list bitU -let rec pad_zero bits n = - if n = 0 then bits else pad_zero (B0 :: bits) (n -1) - - -let rec add_one_bit_ignore_overflow_aux bits = match bits with - | [] -> [] - | B0 :: bits -> B1 :: bits - | B1 :: bits -> B0 :: add_one_bit_ignore_overflow_aux bits - | BU :: _ -> failwith "add_one_bit_ignore_overflow: undefined bit" -end - -let add_one_bit_ignore_overflow bits = - List.reverse (add_one_bit_ignore_overflow_aux (List.reverse bits)) - -val to_norm_vec : forall 'a. Size 'a => integer -> bitvector 'a -let to_norm_vec (n : integer) = wordFromInteger n -(* - (* Bitvector length is determined by return type *) - let bits = wordFromInteger n in - let len = integerFromNat (word_length bits) in - let start = if is_inc then 0 else len - 1 in - (*if integerFromNat (word_length bits) = len then*) - Bitvector bits start is_inc - (*else - failwith "Vector length mismatch in to_vec"*) -*) - -let to_vec_big = to_norm_vec - -let to_vec_inc (start, len, n) = to_norm_vec n -let to_vec_norm_inc (len, n) = to_norm_vec n -let to_vec_dec (start, len, n) = to_norm_vec n -let to_vec_norm_dec (len, n) = to_norm_vec n - -(* TODO: Think about undefined bit(vector)s *) -let to_vec_undef is_inc (len : integer) = - (* Bitvector *) - (failwith "undefined bitvector") - (* (if is_inc then 0 else len-1) is_inc *) - -let to_vec_inc_undef = to_vec_undef true -let to_vec_dec_undef = to_vec_undef false - -let exts (start, len, vec) = to_norm_vec (signed vec) -val extz : forall 'a 'b. Size 'a, Size 'b => (integer * integer * bitvector 'a) -> bitvector 'b -let extz (start, len, vec) = to_norm_vec (unsigned vec) - -let exts_big (start, len, vec) = to_vec_big (signed_big vec) -let extz_big (start, len, vec) = to_vec_big (unsigned_big vec) - -let quot = hardware_quot -let modulo (l,r) = hardware_mod l r - -(* TODO: this, and the definitions that use it, currently require Size for - to_vec, which I'd rather avoid in favour of library versions; the - double-size results for multiplication may be a problem *) -let arith_op_vec op sign (size : integer) l r = - let (l',r') = (to_num sign l, to_num sign r) in - let n = op l' r' in - to_norm_vec n - - -(* add_vec - * add_vec_signed - * minus_vec - * multiply_vec - * multiply_vec_signed - *) -let add_VVV = arith_op_vec integerAdd false 1 -let addS_VVV = arith_op_vec integerAdd true 1 -let minus_VVV = arith_op_vec integerMinus false 1 -let mult_VVV = arith_op_vec integerMult false 2 -let multS_VVV = arith_op_vec integerMult true 2 - -let mult_vec (l, r) = mult_VVV l r -let mult_svec (l, r) = multS_VVV l r - -let add_vec (l, r) = add_VVV l r -let sub_vec (l, r) = minus_VVV l r - -val arith_op_vec_range : forall 'a 'b. Size 'a, Size 'b => (integer -> integer -> integer) -> bool -> integer -> bitvector 'a -> integer -> bitvector 'b -let arith_op_vec_range op sign size l r = - arith_op_vec op sign size l ((to_norm_vec r) : bitvector 'a) - -(* add_vec_range - * add_vec_range_signed - * minus_vec_range - * mult_vec_range - * mult_vec_range_signed - *) -let add_VIV = arith_op_vec_range integerAdd false 1 -let addS_VIV = arith_op_vec_range integerAdd true 1 -let minus_VIV = arith_op_vec_range integerMinus false 1 -let mult_VIV = arith_op_vec_range integerMult false 2 -let multS_VIV = arith_op_vec_range integerMult true 2 - -let add_vec_int (l, r) = add_VIV l r -let sub_vec_int (l, r) = minus_VIV l r - -val arith_op_range_vec : forall 'a 'b. Size 'a, Size 'b => (integer -> integer -> integer) -> bool -> integer -> integer -> bitvector 'a -> bitvector 'b -let arith_op_range_vec op sign size l r = - arith_op_vec op sign size ((to_norm_vec l) : bitvector 'a) r - -(* add_range_vec - * add_range_vec_signed - * minus_range_vec - * mult_range_vec - * mult_range_vec_signed - *) -let add_IVV = arith_op_range_vec integerAdd false 1 -let addS_IVV = arith_op_range_vec integerAdd true 1 -let minus_IVV = arith_op_range_vec integerMinus false 1 -let mult_IVV = arith_op_range_vec integerMult false 2 -let multS_IVV = arith_op_range_vec integerMult true 2 - -let arith_op_range_vec_range op sign l r = op l (to_num sign r) - -(* add_range_vec_range - * add_range_vec_range_signed - * minus_range_vec_range - *) -let add_IVI x = arith_op_range_vec_range integerAdd false x -let addS_IVI x = arith_op_range_vec_range integerAdd true x -let minus_IVI x = arith_op_range_vec_range integerMinus false x - -let arith_op_vec_range_range op sign l r = op (to_num sign l) r - -(* add_vec_range_range - * add_vec_range_range_signed - * minus_vec_range_range - *) -let add_VII x = arith_op_vec_range_range integerAdd false x -let addS_VII x = arith_op_vec_range_range integerAdd true x -let minus_VII x = arith_op_vec_range_range integerMinus false x - - - -let arith_op_vec_vec_range op sign l r = - let (l',r') = (to_num sign l,to_num sign r) in - op l' r' - -(* add_vec_vec_range - * add_vec_vec_range_signed - *) -let add_VVI x = arith_op_vec_vec_range integerAdd false x -let addS_VVI x = arith_op_vec_vec_range integerAdd true x - -let arith_op_vec_bit op sign (size : integer) l r = - let l' = to_num sign l in - let n = op l' (match r with | B1 -> (1 : integer) | _ -> 0 end) in - to_norm_vec n - -(* add_vec_bit - * add_vec_bit_signed - * minus_vec_bit_signed - *) -let add_VBV x = arith_op_vec_bit integerAdd false 1 x -let addS_VBV x = arith_op_vec_bit integerAdd true 1 x -let minus_VBV x = arith_op_vec_bit integerMinus true 1 x - -(* TODO: these can't be done directly in Lem because of the one_more size calculation -val arith_op_overflow_vec : forall 'a 'b. Size 'a, Size 'b => (integer -> integer -> integer) -> bool -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b * bitU * bool -let rec arith_op_overflow_vec op sign size (Bitvector _ _ is_inc as l) r = - let len = bvlength l in - let act_size = len * size in - let (l_sign,r_sign) = (to_num sign l,to_num sign r) in - let (l_unsign,r_unsign) = (to_num false l,to_num false r) in - let n = op l_sign r_sign in - let n_unsign = op l_unsign r_unsign in - let correct_size_num = to_vec_ord is_inc (act_size,n) in - let one_more_size_u = to_vec_ord is_inc (act_size + 1,n_unsign) in - let overflow = - if n <= get_max_representable_in sign len && - n >= get_min_representable_in sign len - then B0 else B1 in - let c_out = most_significant one_more_size_u in - (correct_size_num,overflow,c_out) - -(* add_overflow_vec - * add_overflow_vec_signed - * minus_overflow_vec - * minus_overflow_vec_signed - * mult_overflow_vec - * mult_overflow_vec_signed - *) -let addO_VVV = arith_op_overflow_vec integerAdd false 1 -let addSO_VVV = arith_op_overflow_vec integerAdd true 1 -let minusO_VVV = arith_op_overflow_vec integerMinus false 1 -let minusSO_VVV = arith_op_overflow_vec integerMinus true 1 -let multO_VVV = arith_op_overflow_vec integerMult false 2 -let multSO_VVV = arith_op_overflow_vec integerMult true 2 - -val arith_op_overflow_vec_bit : forall 'a 'b. Size 'a, Size 'b => (integer -> integer -> integer) -> bool -> integer -> - bitvector 'a -> bitU -> bitvector 'b * bitU * bool -let rec arith_op_overflow_vec_bit (op : integer -> integer -> integer) sign (size : integer) - (Bitvector _ _ is_inc as l) r_bit = - let act_size = bvlength l * size in - let l' = to_num sign l in - let l_u = to_num false l in - let (n,nu,changed) = match r_bit with - | B1 -> (op l' 1, op l_u 1, true) - | B0 -> (l',l_u,false) - | BU -> failwith "arith_op_overflow_vec_bit applied to undefined bit" - end in -(* | _ -> assert false *) - let correct_size_num = to_vec_ord is_inc (act_size,n) in - let one_larger = to_vec_ord is_inc (act_size + 1,nu) in - let overflow = - if changed - then - if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size - then B0 else B1 - else B0 in - (correct_size_num,overflow,most_significant one_larger) - -(* add_overflow_vec_bit_signed - * minus_overflow_vec_bit - * minus_overflow_vec_bit_signed - *) -let addSO_VBV = arith_op_overflow_vec_bit integerAdd true 1 -let minusO_VBV = arith_op_overflow_vec_bit integerMinus false 1 -let minusSO_VBV = arith_op_overflow_vec_bit integerMinus true 1 -*) -type shift = LL_shift | RR_shift | LLL_shift - -let shift_op_vec op (bs, (n : integer)) = - let n = natFromInteger n in - match op with - | LL_shift (*"<<"*) -> - shiftLeft bs n - | RR_shift (*">>"*) -> - shiftRight bs n - | LLL_shift (*"<<<"*) -> - rotateLeft n bs - end - -let bitwise_leftshift x = shift_op_vec LL_shift x (*"<<"*) -let bitwise_rightshift x = shift_op_vec RR_shift x (*">>"*) -let bitwise_rotate x = shift_op_vec LLL_shift x (*"<<<"*) - -let shiftl = bitwise_leftshift -let shiftr = bitwise_rightshift - -let rec arith_op_no0 (op : integer -> integer -> integer) l r = - if r = 0 - then Nothing - else Just (op l r) -(* TODO -let rec arith_op_vec_no0 (op : integer -> integer -> integer) sign size ((Bitvector _ start is_inc) as l) r = - let act_size = bvlength l * size in - let (l',r') = (to_num sign l,to_num sign r) in - let n = arith_op_no0 op l' r' in - let (representable,n') = - match n with - | Just n' -> - (n' <= get_max_representable_in sign act_size && - n' >= get_min_representable_in sign act_size, n') - | _ -> (false,0) - end in - if representable - then to_vec_ord is_inc (act_size,n') - else Vector (List.replicate (natFromInteger act_size) BU) start is_inc - -let mod_VVV = arith_op_vec_no0 hardware_mod false 1 -let quot_VVV = arith_op_vec_no0 hardware_quot false 1 -let quotS_VVV = arith_op_vec_no0 hardware_quot true 1 - -let arith_op_overflow_no0_vec op sign size ((Vector _ start is_inc) as l) r = - let rep_size = length r * size in - let act_size = length l * size in - let (l',r') = (to_num sign l,to_num sign r) in - let (l_u,r_u) = (to_num false l,to_num false r) in - let n = arith_op_no0 op l' r' in - let n_u = arith_op_no0 op l_u r_u in - let (representable,n',n_u') = - match (n, n_u) with - | (Just n',Just n_u') -> - ((n' <= get_max_representable_in sign rep_size && - n' >= (get_min_representable_in sign rep_size)), n', n_u') - | _ -> (true,0,0) - end in - let (correct_size_num,one_more) = - if representable then - (to_vec_ord is_inc (act_size,n'),to_vec_ord is_inc (act_size + 1,n_u')) - else - (Vector (List.replicate (natFromInteger act_size) BU) start is_inc, - Vector (List.replicate (natFromInteger (act_size + 1)) BU) start is_inc) in - let overflow = if representable then B0 else B1 in - (correct_size_num,overflow,most_significant one_more) - -let quotO_VVV = arith_op_overflow_no0_vec hardware_quot false 1 -let quotSO_VVV = arith_op_overflow_no0_vec hardware_quot true 1 - -let arith_op_vec_range_no0 op sign size (Vector _ _ is_inc as l) r = - arith_op_vec_no0 op sign size l (to_vec_ord is_inc (length l,r)) - -let mod_VIV = arith_op_vec_range_no0 hardware_mod false 1 -*) - -let duplicate (bit, length) = - vec_to_bvec (Vector (repeat [bit] length) (length - 1) false) - -(* TODO: replace with better native versions *) -let replicate_bits (v, count) = - let v = bvec_to_vec true 0 v in - vec_to_bvec (Vector (repeat (get_elems v) count) ((length v * count) - 1) false) - -let compare_op op (l,r) = (op l r) - -let lt = compare_op (<) -let gt = compare_op (>) -let lteq = compare_op (<=) -let gteq = compare_op (>=) - -let compare_op_vec op sign (l,r) = - let (l',r') = (to_num sign l, to_num sign r) in - compare_op op (l',r') - -let lt_vec x = compare_op_vec (<) true x -let gt_vec x = compare_op_vec (>) true x -let lteq_vec x = compare_op_vec (<=) true x -let gteq_vec x = compare_op_vec (>=) true x - -let lt_vec_signed x = compare_op_vec (<) true x -let gt_vec_signed x = compare_op_vec (>) true x -let lteq_vec_signed x = compare_op_vec (<=) true x -let gteq_vec_signed x = compare_op_vec (>=) true x -let lt_vec_unsigned x = compare_op_vec (<) false x -let gt_vec_unsigned x = compare_op_vec (>) false x -let lteq_vec_unsigned x = compare_op_vec (<=) false x -let gteq_vec_unsigned x = compare_op_vec (>=) false x - -let lt_svec = lt_vec_signed - -let compare_op_vec_range op sign (l,r) = - compare_op op ((to_num sign l),r) - -let lt_vec_range x = compare_op_vec_range (<) true x -let gt_vec_range x = compare_op_vec_range (>) true x -let lteq_vec_range x = compare_op_vec_range (<=) true x -let gteq_vec_range x = compare_op_vec_range (>=) true x - -let compare_op_range_vec op sign (l,r) = - compare_op op (l, (to_num sign r)) - -let lt_range_vec x = compare_op_range_vec (<) true x -let gt_range_vec x = compare_op_range_vec (>) true x -let lteq_range_vec x = compare_op_range_vec (<=) true x -let gteq_range_vec x = compare_op_range_vec (>=) true x - -val eq : forall 'a. Eq 'a => 'a * 'a -> bool -let eq (l,r) = (l = r) -let eq_range (l,r) = (l = r) - -val eq_vec : forall 'a. Size 'a => bitvector 'a * bitvector 'a -> bool -let eq_vec (l,r) = eq (to_num false l, to_num false r) -let eq_bit (l,r) = eq (l, r) -let eq_vec_range (l,r) = eq (to_num false l,r) -let eq_range_vec (l,r) = eq (l, to_num false r) -(*let eq_vec_vec (l,r) = eq (to_num true l, to_num true r)*) - -let neq (l,r) = not (eq (l,r)) -let neq_bit (l,r) = not (eq_bit (l,r)) -let neq_range (l,r) = not (eq_range (l,r)) -let neq_vec (l,r) = not (eq_vec (l,r)) -(*let neq_vec_vec (l,r) = not (eq_vec_vec (l,r))*) -let neq_vec_range (l,r) = not (eq_vec_range (l,r)) -let neq_range_vec (l,r) = not (eq_range_vec (l,r)) - - -val make_indexed_vector : forall 'a. list (integer * 'a) -> 'a -> integer -> integer -> bool -> vector 'a -let make_indexed_vector entries default start length dir = - let length = natFromInteger length in - Vector (List.foldl replace (replicate length default) entries) start dir - -(* -val make_bit_vector_undef : integer -> vector bitU -let make_bitvector_undef length = - Vector (replicate (natFromInteger length) BU) 0 true - *) - -(* let bitwise_not_range_bit n = bitwise_not (to_vec_ord defaultDir n) *) - -(* TODO *) -val mask : forall 'a 'b. Size 'b => (integer * integer * bitvector 'a) -> bitvector 'b -let mask (start, _, w) = (zeroExtend w) - -(* Register operations *) - -(*let update_reg_range reg i j reg_val new_val = bvupdate (reg.reg_is_inc) (reg.reg_start) reg_val i j new_val -let update_reg_pos reg i reg_val bit = bvupdate_pos (reg.reg_is_inc) (reg.reg_start) reg_val i bit -let update_reg_field_range regfield i j reg_val new_val = - let current_field_value = regfield.get_field reg_val in - let new_field_value = bvupdate (regfield.field_is_inc) (regfield.field_start) current_field_value i j new_val in - regfield.set_field reg_val new_field_value -(*let write_reg_field_pos regfield i reg_val bit = - let current_field_value = regfield.get_field reg_val in - let new_field_value = bvupdate_pos (regfield.field_is_inc) (regfield.field_start) current_field_value i bit in - regfield.set_field reg_val new_field_value*)*) +open import Sail_operators + +(* Specialisation of operators to machine words *) + +val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU +let access_vec_inc = access_bv_inc + +val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU +let access_vec_dec = access_bv_dec + +val update_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU -> mword 'a +let update_vec_inc = update_bv_inc + +val update_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU -> mword 'a +let update_vec_dec = update_bv_dec + +val subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b +let subrange_vec_inc = subrange_bv_inc + +val subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b +let subrange_vec_dec = subrange_bv_dec + +val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a +let update_subrange_vec_inc = update_subrange_bv_inc + +val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a +let update_subrange_vec_dec = update_subrange_bv_dec + +val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b +let extz_vec = extz_bv + +val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b +let exts_vec = exts_bv + +val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c +let concat_vec = concat_bv + +val cons_vec : forall 'a 'b 'c. Size 'a, Size 'b => bitU -> mword 'a -> mword 'b +let cons_vec = cons_bv + +val bool_of_vec : mword ty1 -> bitU +let bool_of_vec = bool_of_bv + +val cast_unit_vec : bitU -> mword ty1 +let cast_unit_vec = cast_unit_bv + +val vec_of_bit : forall 'a. Size 'a => integer -> bitU -> mword 'a +let vec_of_bit = bv_of_bit + +val msb : forall 'a. Size 'a => mword 'a -> bitU +let msb = most_significant + +val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer +let int_of_vec = int_of_bv + +val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a +val or_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a +val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a +val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a +let and_vec = and_bv +let or_vec = or_bv +let xor_vec = xor_bv +let not_vec = not_bv + +val add_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a +val addS_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a +val sub_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a +val mult_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b +val multS_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b +let add_vec = add_bv +let addS_vec = addS_bv +let sub_vec = sub_bv +let mult_vec = mult_bv +let multS_vec = multS_bv + +val add_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a +val addS_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a +val sub_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a +val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b +val multS_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b +let add_vec_int = add_bv_int +let addS_vec_int = addS_bv_int +let sub_vec_int = sub_bv_int +let mult_vec_int = mult_bv_int +let multS_vec_int = multS_bv_int + +val add_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a +val addS_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a +val sub_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a +val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b +val multS_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b +let add_int_vec = add_int_bv +let addS_int_vec = addS_int_bv +let sub_int_vec = sub_int_bv +let mult_int_vec = mult_int_bv +let multS_int_vec = multS_int_bv + +val add_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a +val addS_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a +val sub_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> mword 'a +let add_vec_bit = add_bv_bit +let addS_vec_bit = addS_bv_bit +let sub_vec_bit = sub_bv_bit + +val add_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU) +val add_overflow_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU) +val sub_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU) +val sub_overflow_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU) +val mult_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU) +val mult_overflow_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> (mword 'a * bitU * bitU) +let add_overflow_vec = add_overflow_bv +let add_overflow_vec_signed = add_overflow_bv_signed +let sub_overflow_vec = sub_overflow_bv +let sub_overflow_vec_signed = sub_overflow_bv_signed +let mult_overflow_vec = mult_overflow_bv +let mult_overflow_vec_signed = mult_overflow_bv_signed + +val add_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +val add_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +val sub_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +val sub_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +let add_overflow_vec_bit = add_overflow_bv_bit +let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed +let sub_overflow_vec_bit = sub_overflow_bv_bit +let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed + +val shiftl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a +val shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a +val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a +val rotl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a +val rotr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a +let shiftl = shiftl_bv +let shiftr = shiftr_bv +let arith_shiftr = arith_shiftr_bv +let rotl = rotl_bv +let rotr = rotr_bv + +val mod_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a +val quot_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a +val quot_vec_signed : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a +let mod_vec = mod_bv +let quot_vec = quot_bv +let quot_vec_signed = quot_bv_signed + +val mod_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a +val quot_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a +let mod_vec_int = mod_bv_int +let quot_vec_int = quot_bv_int + +val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b +let replicate_bits = replicate_bits_bv + +val duplicate : forall 'a. Size 'a => bitU -> integer -> mword 'a +let duplicate = duplicate_bit_bv + +val eq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool +val neq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool +val ult_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool +val slt_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool +val ugt_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool +val sgt_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool +val ulteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool +val slteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool +val ugteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool +val sgteq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool +let eq_vec = eq_bv +let neq_vec = neq_bv +let ult_vec = ult_bv +let slt_vec = slt_bv +let ugt_vec = ugt_bv +let sgt_vec = sgt_bv +let ulteq_vec = ulteq_bv +let slteq_vec = slteq_bv +let ugteq_vec = ugteq_bv +let sgteq_vec = sgteq_bv diff --git a/src/gen_lib/sail_values.lem b/src/gen_lib/sail_values.lem index 8aee556d..50dacf5e 100644 --- a/src/gen_lib/sail_values.lem +++ b/src/gen_lib/sail_values.lem @@ -13,6 +13,17 @@ let pow m n = m ** (natFromInteger n) let pow2 n = pow 2 n +let inline lt = (<) +let inline gt = (>) +let inline lteq = (<=) +let inline gteq = (>=) + +val eq : forall 'a. Eq 'a => 'a -> 'a -> bool +let inline eq l r = (l = r) + +val neq : forall 'a. Eq 'a => 'a -> 'a -> bool +let inline neq l r = (l <> r) + (*let add_int l r = integerAdd l r let add_signed l r = integerAdd l r let sub_int l r = integerMinus l r @@ -58,6 +69,34 @@ let rec replace bs (n : integer) b' = match bs with let upper n = n +(* Modulus operation corresponding to quot below -- result + has sign of dividend. *) +let hardware_mod (a: integer) (b:integer) : integer = + let m = (abs a) mod (abs b) in + if a < 0 then ~m else m + +(* There are different possible answers for integer divide regarding +rounding behaviour on negative operands. Positive operands always +round down so derive the one we want (trucation towards zero) from +that *) +let hardware_quot (a:integer) (b:integer) : integer = + let q = (abs a) / (abs b) in + if ((a<0) = (b<0)) then + q (* same sign -- result positive *) + else + ~q (* different sign -- result negative *) + +let max_64u = (integerPow 2 64) - 1 +let max_64 = (integerPow 2 63) - 1 +let min_64 = 0 - (integerPow 2 63) +let max_32u = (4294967295 : integer) +let max_32 = (2147483647 : integer) +let min_32 = (0 - 2147483648 : integer) +let max_8 = (127 : integer) +let min_8 = (0 - 128 : integer) +let max_5 = (31 : integer) +let min_5 = (0 - 32 : integer) + (*** Bits *) type bitU = B0 | B1 | BU @@ -83,7 +122,7 @@ end let bool_of_bitU = function | B0 -> false - | B1 -> true + | B1 -> true | BU -> failwith "bool_of_bitU applied to BU" end @@ -272,34 +311,34 @@ let show_bitlist bs = let inline (^^) = append_list -val slice_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a -let slice_list_inc xs i j = +val subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a +let subrange_list_inc xs i j = let (toJ,_suffix) = List.splitAt (natFromInteger j + 1) xs in let (_prefix,fromItoJ) = List.splitAt (natFromInteger i) toJ in fromItoJ -val slice_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a -let slice_list_dec xs i j = +val subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a +let subrange_list_dec xs i j = let top = (length_list xs) - 1 in - slice_list_inc xs (top - i) (top - j) + subrange_list_inc xs (top - i) (top - j) -val slice_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a -let slice_list is_inc xs i j = if is_inc then slice_list_inc xs i j else slice_list_dec xs i j +val subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a +let subrange_list is_inc xs i j = if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j -val update_slice_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a -let update_slice_list_inc xs i j xs' = +val update_subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a +let update_subrange_list_inc xs i j xs' = let (toJ,suffix) = List.splitAt (natFromInteger j + 1) xs in let (prefix,_fromItoJ) = List.splitAt (natFromInteger i) toJ in prefix ++ xs' ++ suffix -val update_slice_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a -let update_slice_list_dec xs i j xs' = +val update_subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a +let update_subrange_list_dec xs i j xs' = let top = (length_list xs) - 1 in - update_slice_list_inc xs (top - i) (top - j) xs' + update_subrange_list_inc xs (top - i) (top - j) xs' -val update_slice_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a -> list 'a -let update_slice_list is_inc xs i j xs' = - if is_inc then update_slice_list_inc xs i j xs' else update_slice_list_dec xs i j xs' +val update_subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a -> list 'a +let update_subrange_list is_inc xs i j xs' = + if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs' val access_list_inc : forall 'a. list 'a -> integer -> 'a let access_list_inc xs n = List_extra.nth xs (natFromInteger n) @@ -383,11 +422,28 @@ val update_mword : forall 'a. bool -> mword 'a -> integer -> bitU -> mword 'a let update_mword is_inc w n b = if is_inc then update_mword_inc w n b else update_mword_dec w n b +val mword_of_int : forall 'a. Size 'a => integer -> integer -> mword 'a +let mword_of_int len n = + let w = wordFromInteger n in + if (length_mword w = len) then w else failwith "unexpected word length" + +(* Translating between a type level number (itself 'n) and an integer *) + +let size_itself_int x = integerFromNat (size_itself x) + +(* NB: the corresponding sail type is forall 'n. atom('n) -> itself('n), + the actual integer is ignored. *) + +val make_the_value : forall 'n. integer -> itself 'n +let inline make_the_value x = the_value + (*** Bitvectors *) class (Bitvector 'a) val bits_of : 'a -> list bitU val of_bits : list bitU -> 'a + (* The first parameter specifies the desired length of the bitvector *) + val of_int : integer -> integer -> 'a val length : 'a -> integer val unsigned : 'a -> integer val signed : 'a -> integer @@ -401,44 +457,46 @@ end instance forall 'a. BitU 'a => (Bitvector (list 'a)) let bits_of v = List.map to_bitU v let of_bits v = List.map of_bitU v - let length v = length_list v + let of_int len n = List.map of_bitU (bits_of_int len n) + let length = length_list let unsigned v = unsigned_of_bits (List.map to_bitU v) let signed v = signed_of_bits (List.map to_bitU v) let get_bit is_inc v n = to_bitU (access_list is_inc v n) let set_bit is_inc v n b = update_list is_inc v n (of_bitU b) - let get_bits is_inc v i j = List.map to_bitU (slice_list is_inc v i j) - let set_bits is_inc v i j v' = update_slice_list is_inc v i j (List.map of_bitU v') + let get_bits is_inc v i j = List.map to_bitU (subrange_list is_inc v i j) + let set_bits is_inc v i j v' = update_subrange_list is_inc v i j (List.map of_bitU v') end instance forall 'a. Size 'a => (Bitvector (mword 'a)) let bits_of v = List.map to_bitU (bitlistFromWord v) let of_bits v = wordFromBitlist (List.map of_bitU v) + let of_int = mword_of_int let length v = integerFromNat (word_length v) - let unsigned v = unsignedIntegerFromWord v - let signed v = signedIntegerFromWord v + let unsigned = unsignedIntegerFromWord + let signed = signedIntegerFromWord let get_bit = access_mword let set_bit = update_mword let get_bits is_inc v i j = get_bits is_inc (bitlistFromWord v) i j let set_bits is_inc v i j v' = wordFromBitlist (set_bits is_inc (bitlistFromWord v) i j v') end -let access_vec_inc v n = get_bit true v n -let access_vec_dec v n = get_bit false v n +let access_bv_inc v n = get_bit true v n +let access_bv_dec v n = get_bit false v n -let update_vec_inc v n b = set_bit true v n b -let update_vec_dec v n b = set_bit false v n b +let update_bv_inc v n b = set_bit true v n b +let update_bv_dec v n b = set_bit false v n b -let subrange_vec_inc v i j = of_bits (get_bits true v i j) -let subrange_vec_dec v i j = of_bits (get_bits false v i j) +let subrange_bv_inc v i j = of_bits (get_bits true v i j) +let subrange_bv_dec v i j = of_bits (get_bits false v i j) -let update_subrange_vec_inc v i j v' = set_bits true v i j (bits_of v') -let update_subrange_vec_dec v i j v' = set_bits false v i j (bits_of v') +let update_subrange_bv_inc v i j v' = set_bits true v i j (bits_of v') +let update_subrange_bv_dec v i j v' = set_bits false v i j (bits_of v') -val extz_vec : forall 'a 'b. Bitvector 'a, Bitvector 'b => integer -> 'a -> 'b -let extz_vec n v = of_bits (extz_bits n (bits_of v)) +val extz_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => integer -> 'a -> 'b +let extz_bv n v = of_bits (extz_bits n (bits_of v)) -val exts_vec : forall 'a 'b. Bitvector 'a, Bitvector 'b => integer -> 'a -> 'b -let exts_vec n v = of_bits (exts_bits n (bits_of v)) +val exts_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => integer -> 'a -> 'b +let exts_bv n v = of_bits (exts_bits n (bits_of v)) (*** Bytes and addresses *) @@ -584,13 +642,13 @@ let rec external_reg_value reg_name v = match reg_name with | Reg _ start size dir -> (start, (if dir = D_increasing then start else (start - (size +1))), dir) - | Reg_slice _ reg_start dir (slice_start, slice_end) -> + | Reg_slice _ reg_start dir (slice_start, _) -> ((if dir = D_increasing then slice_start else (reg_start - slice_start)), slice_start, dir) - | Reg_field _ reg_start dir _ (slice_start, slice_end) -> + | Reg_field _ reg_start dir _ (slice_start, _) -> ((if dir = D_increasing then slice_start else (reg_start - slice_start)), slice_start, dir) - | Reg_f_slice _ reg_start dir _ _ (slice_start, slice_end) -> + | Reg_f_slice _ reg_start dir _ _ (slice_start, _) -> ((if dir = D_increasing then slice_start else (reg_start - slice_start)), slice_start, dir) end in diff --git a/src/gen_lib/state.lem b/src/gen_lib/state.lem index b6852aaf..ac6d55b5 100644 --- a/src/gen_lib/state.lem +++ b/src/gen_lib/state.lem @@ -1,253 +1,8 @@ open import Pervasives_extra open import Sail_impl_base open import Sail_values - -(* 'a is result type *) - -type memstate = map integer memory_byte -type tagstate = map integer bitU -(* type regstate = map string (vector bitU) *) - -type sequential_state 'regs = - <| regstate : 'regs; - memstate : memstate; - tagstate : tagstate; - write_ea : maybe (write_kind * integer * integer); - last_exclusive_operation_was_load : bool|> - -val init_state : forall 'regs. 'regs -> sequential_state 'regs -let init_state regs = - <| regstate = regs; - memstate = Map.empty; - tagstate = Map.empty; - write_ea = Nothing; - last_exclusive_operation_was_load = false |> - -type ex 'e = - | Exit - | Assert of string - | Throw of 'e - -type result 'a 'e = - | Value of 'a - | Exception of (ex 'e) - -(* State, nondeterminism and exception monad with result value type 'a - and exception type 'e. *) -type M 'regs 'a 'e = sequential_state 'regs -> list (result 'a 'e * sequential_state 'regs) - -val return : forall 'regs 'a 'e. 'a -> M 'regs 'a 'e -let return a s = [(Value a,s)] - -val bind : forall 'regs 'a 'b 'e. M 'regs 'a 'e -> ('a -> M 'regs 'b 'e) -> M 'regs 'b 'e -let bind m f (s : sequential_state 'regs) = - List.concatMap (function - | (Value a, s') -> f a s' - | (Exception e, s') -> [(Exception e, s')] - end) (m s) - -let inline (>>=) = bind -val (>>): forall 'regs 'b 'e. M 'regs unit 'e -> M 'regs 'b 'e -> M 'regs 'b 'e -let inline (>>) m n = m >>= fun (_ : unit) -> n - -val throw : forall 'regs 'a 'e. 'e -> M 'regs 'a 'e -let throw e s = [(Exception (Throw e), s)] - -val try_catch : forall 'regs 'a 'e1 'e2. M 'regs 'a 'e1 -> ('e1 -> M 'regs 'a 'e2) -> M 'regs 'a 'e2 -let try_catch m h s = - List.concatMap (function - | (Value a, s') -> return a s' - | (Exception (Throw e), s') -> h e s' - | (Exception Exit, s') -> [(Exception Exit, s')] - | (Exception (Assert msg), s') -> [(Exception (Assert msg), s')] - end) (m s) - -val exit : forall 'regs 'e 'a. unit -> M 'regs 'a 'e -let exit () s = [(Exception Exit, s)] - -val assert_exp : forall 'regs 'e. bool -> string -> M 'regs unit 'e -let assert_exp exp msg s = if exp then [(Value (), s)] else [(Exception (Assert msg), s)] - -(* For early return, we abuse exceptions by throwing and catching - the return value. The exception type is "either 'r 'e", where "Right e" - represents a proper exception and "Left r" an early return of value "r". *) -type MR 'regs 'a 'r 'e = M 'regs 'a (either 'r 'e) - -val early_return : forall 'regs 'a 'r 'e. 'r -> MR 'regs 'a 'r 'e -let early_return r = throw (Left r) - -val catch_early_return : forall 'regs 'a 'e. MR 'regs 'a 'a 'e -> M 'regs 'a 'e -let catch_early_return m = - try_catch m - (function - | Left a -> return a - | Right e -> throw e - end) - -(* Lift to monad with early return by wrapping exceptions *) -val liftR : forall 'a 'r 'regs 'e. M 'regs 'a 'e -> MR 'regs 'a 'r 'e -let liftR m = try_catch m (fun e -> throw (Right e)) - -(* Catch exceptions in the presence of early returns *) -val try_catchR : forall 'regs 'a 'r 'e1 'e2. MR 'regs 'a 'r 'e1 -> ('e1 -> MR 'regs 'a 'r 'e2) -> MR 'regs 'a 'r 'e2 -let try_catchR m h = - try_catch m - (function - | Left r -> throw (Left r) - | Right e -> h e - end) - -val range : integer -> integer -> list integer -let rec range i j = - if j < i then [] - else if i = j then [i] - else i :: range (i+1) j - -val get_reg : forall 'regs 'a. sequential_state 'regs -> register_ref 'regs 'a -> 'a -let get_reg state reg = reg.read_from state.regstate - -val set_reg : forall 'regs 'a. sequential_state 'regs -> register_ref 'regs 'a -> 'a -> sequential_state 'regs -let set_reg state reg v = - <| state with regstate = reg.write_to state.regstate v |> - - -let is_exclusive = function - | Sail_impl_base.Read_plain -> false - | Sail_impl_base.Read_reserve -> true - | Sail_impl_base.Read_acquire -> false - | Sail_impl_base.Read_exclusive -> true - | Sail_impl_base.Read_exclusive_acquire -> true - | Sail_impl_base.Read_stream -> false - | Sail_impl_base.Read_RISCV_acquire -> false - | Sail_impl_base.Read_RISCV_strong_acquire -> false - | Sail_impl_base.Read_RISCV_reserved -> true - | Sail_impl_base.Read_RISCV_reserved_acquire -> true - | Sail_impl_base.Read_RISCV_reserved_strong_acquire -> true - | Sail_impl_base.Read_X86_locked -> true -end - - -val read_mem : forall 'regs 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> M 'regs 'b 'e -let read_mem read_kind addr sz state = - let addr = unsigned addr in - let addrs = range addr (addr+sz-1) in - let memory_value = List.map (fun addr -> Map_extra.find addr state.memstate) addrs in - let value = of_bits (Sail_values.internal_mem_value memory_value) in - if is_exclusive read_kind - then [(Value value, <| state with last_exclusive_operation_was_load = true |>)] - else [(Value value, state)] - -(* caps are aligned at 32 bytes *) -let cap_alignment = (32 : integer) - -val read_tag : forall 'regs 'a 'e. Bitvector 'a => read_kind -> 'a -> M 'regs bitU 'e -let read_tag read_kind addr state = - let addr = (unsigned addr) / cap_alignment in - let tag = match (Map.lookup addr state.tagstate) with - | Just t -> t - | Nothing -> B0 - end in - if is_exclusive read_kind - then [(Value tag, <| state with last_exclusive_operation_was_load = true |>)] - else [(Value tag, state)] - -val excl_result : forall 'regs 'e. unit -> M 'regs bool 'e -let excl_result () state = - let success = - (Value true, <| state with last_exclusive_operation_was_load = false |>) in - (Value false, state) :: if state.last_exclusive_operation_was_load then [success] else [] - -val write_mem_ea : forall 'regs 'a 'e. Bitvector 'a => write_kind -> 'a -> integer -> M 'regs unit 'e -let write_mem_ea write_kind addr sz state = - [(Value (), <| state with write_ea = Just (write_kind,unsigned addr,sz) |>)] - -val write_mem_val : forall 'a 'regs 'b 'e. Bitvector 'a => 'a -> M 'regs bool 'e -let write_mem_val v state = - let (write_kind,addr,sz) = match state.write_ea with - | Nothing -> failwith "write ea has not been announced yet" - | Just write_ea -> write_ea end in - let addrs = range addr (addr+sz-1) in - let v = external_mem_value (bits_of v) in - let addresses_with_value = List.zip addrs v in - let memstate = List.foldl (fun mem (addr,v) -> Map.insert addr v mem) - state.memstate addresses_with_value in - [(Value true, <| state with memstate = memstate |>)] - -val write_tag : forall 'regs 'e. bitU -> M 'regs bool 'e -let write_tag t state = - let (write_kind,addr,sz) = match state.write_ea with - | Nothing -> failwith "write ea has not been announced yet" - | Just write_ea -> write_ea end in - let taddr = addr / cap_alignment in - let tagstate = Map.insert taddr t state.tagstate in - [(Value true, <| state with tagstate = tagstate |>)] - -val read_reg : forall 'regs 'a 'e. register_ref 'regs 'a -> M 'regs 'a 'e -let read_reg reg state = - let v = reg.read_from state.regstate in - [(Value v,state)] -(*let read_reg_range reg i j state = - let v = slice (get_reg state (name_of_reg reg)) i j in - [(Value (vec_to_bvec v),state)] -let read_reg_bit reg i state = - let v = access (get_reg state (name_of_reg reg)) i in - [(Value v,state)] -let read_reg_field reg regfield = - let (i,j) = register_field_indices reg regfield in - read_reg_range reg i j -let read_reg_bitfield reg regfield = - let (i,_) = register_field_indices reg regfield in - read_reg_bit reg i *) - -let reg_deref = read_reg - -val write_reg : forall 'regs 'a 'e. register_ref 'regs 'a -> 'a -> M 'regs unit 'e -let write_reg reg v state = - [(Value (), <| state with regstate = reg.write_to state.regstate v |>)] - -let write_reg_ref (reg, v) = write_reg reg v - -val update_reg : forall 'regs 'a 'b 'e. register_ref 'regs 'a -> ('a -> 'b -> 'a) -> 'b -> M 'regs unit 'e -let update_reg reg f v state = - let current_value = get_reg state reg in - let new_value = f current_value v in - [(Value (), set_reg state reg new_value)] - -let write_reg_field reg regfield = update_reg reg regfield.set_field - -val update_reg_range : forall 'regs 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'a -> integer -> integer -> 'a -> 'b -> 'a -let update_reg_range reg i j reg_val new_val = set_bits (reg.reg_is_inc) reg_val i j (bits_of new_val) -let write_reg_range reg i j = update_reg reg (update_reg_range reg i j) - -let update_reg_pos reg i reg_val x = update_list reg.reg_is_inc reg_val i x -let write_reg_pos reg i = update_reg reg (update_reg_pos reg i) - -let update_reg_bit reg i reg_val bit = set_bit (reg.reg_is_inc) reg_val i (to_bitU bit) -let write_reg_bit reg i = update_reg reg (update_reg_bit reg i) - -let update_reg_field_range regfield i j reg_val new_val = - let current_field_value = regfield.get_field reg_val in - let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in - regfield.set_field reg_val new_field_value -let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j) - -let update_reg_field_pos regfield i reg_val x = - let current_field_value = regfield.get_field reg_val in - let new_field_value = update_list regfield.field_is_inc current_field_value i x in - regfield.set_field reg_val new_field_value -let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i) - -let update_reg_field_bit regfield i reg_val bit = - let current_field_value = regfield.get_field reg_val in - let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in - regfield.set_field reg_val new_field_value -let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i) - -val barrier : forall 'regs 'e. barrier_kind -> M 'regs unit 'e -let barrier _ = return () - -val footprint : forall 'regs 'e. M 'regs unit 'e -let footprint s = return () s +open import State_monad +open import {isabelle} `State_monad_extras` val iter_aux : forall 'regs 'e 'a. integer -> (integer -> 'a -> M 'regs unit 'e) -> list 'a -> M 'regs unit 'e let rec iter_aux i f xs = match xs with @@ -286,24 +41,30 @@ let rec while_PP vars cond body = val while_PM : forall 'regs 'vars 'e. 'vars -> ('vars -> bool) -> ('vars -> M 'regs 'vars 'e) -> M 'regs 'vars 'e -let rec while_PM vars cond body = +let rec while_PM vars cond body s = if cond vars then - body vars >>= fun vars -> while_PM vars cond body - else return vars + bind (body vars) (fun vars s' -> while_PM vars cond body s') s + else return vars s val while_MP : forall 'regs 'vars 'e. 'vars -> ('vars -> M 'regs bool 'e) -> ('vars -> 'vars) -> M 'regs 'vars 'e -let rec while_MP vars cond body = - cond vars >>= fun cond_val -> - if cond_val then while_MP (body vars) cond body else return vars +let rec while_MP vars cond body s = + bind + (cond vars) + (fun cond_val s' -> + if cond_val then while_MP (body vars) cond body s' else return vars s') s val while_MM : forall 'regs 'vars 'e. 'vars -> ('vars -> M 'regs bool 'e) -> ('vars -> M 'regs 'vars 'e) -> M 'regs 'vars 'e -let rec while_MM vars cond body = - cond vars >>= fun cond_val -> - if cond_val then - body vars >>= fun vars -> while_MM vars cond body - else return vars +let rec while_MM vars cond body s = + bind + (cond vars) + (fun cond_val s' -> + if cond_val then + bind + (body vars) + (fun vars s'' -> while_MM vars cond body s'') s' + else return vars s') s val until_PP : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars let rec until_PP vars cond body = @@ -312,44 +73,28 @@ let rec until_PP vars cond body = val until_PM : forall 'regs 'vars 'e. 'vars -> ('vars -> bool) -> ('vars -> M 'regs 'vars 'e) -> M 'regs 'vars 'e -let rec until_PM vars cond body = - body vars >>= fun vars -> - if (cond vars) then return vars else until_PM vars cond body +let rec until_PM vars cond body s = + bind + (body vars) + (fun vars s' -> + if (cond vars) then return vars s' else until_PM vars cond body s') s val until_MP : forall 'regs 'vars 'e. 'vars -> ('vars -> M 'regs bool 'e) -> ('vars -> 'vars) -> M 'regs 'vars 'e -let rec until_MP vars cond body = +let rec until_MP vars cond body s = let vars = body vars in - cond vars >>= fun cond_val -> - if cond_val then return vars else until_MP vars cond body + bind + (cond vars) + (fun cond_val s' -> + if cond_val then return vars s' else until_MP vars cond body s') s val until_MM : forall 'regs 'vars 'e. 'vars -> ('vars -> M 'regs bool 'e) -> ('vars -> M 'regs 'vars 'e) -> M 'regs 'vars 'e -let rec until_MM vars cond body = - body vars >>= fun vars -> - cond vars >>= fun cond_val -> - if cond_val then return vars else until_MM vars cond body - -(*let write_two_regs r1 r2 bvec state = - let vec = bvec_to_vec bvec in - let is_inc = - let is_inc_r1 = is_inc_of_reg r1 in - let is_inc_r2 = is_inc_of_reg r2 in - let () = ensure (is_inc_r1 = is_inc_r2) - "write_two_regs called with vectors of different direction" in - is_inc_r1 in - - let (size_r1 : integer) = size_of_reg r1 in - let (start_vec : integer) = get_start vec in - let size_vec = length vec in - let r1_v = - if is_inc - then slice vec start_vec (size_r1 - start_vec - 1) - else slice vec start_vec (start_vec - size_r1 - 1) in - let r2_v = - if is_inc - then slice vec (size_r1 - start_vec) (size_vec - start_vec) - else slice vec (start_vec - size_r1) (start_vec - size_vec) in - let state1 = set_reg state (name_of_reg r1) r1_v in - let state2 = set_reg state1 (name_of_reg r2) r2_v in - [(Left (), state2)]*) +let rec until_MM vars cond body s = + bind + (body vars) + (fun vars s' -> + bind + (cond vars) + (fun cond_val s''-> + if cond_val then return vars s'' else until_MM vars cond body s'') s') s diff --git a/src/gen_lib/state_monad.lem b/src/gen_lib/state_monad.lem new file mode 100644 index 00000000..2d8e412e --- /dev/null +++ b/src/gen_lib/state_monad.lem @@ -0,0 +1,250 @@ +open import Pervasives_extra +open import Sail_impl_base +open import Sail_values + +(* 'a is result type *) + +type memstate = map integer memory_byte +type tagstate = map integer bitU +(* type regstate = map string (vector bitU) *) + +type sequential_state 'regs = + <| regstate : 'regs; + memstate : memstate; + tagstate : tagstate; + write_ea : maybe (write_kind * integer * integer); + last_exclusive_operation_was_load : bool|> + +val init_state : forall 'regs. 'regs -> sequential_state 'regs +let init_state regs = + <| regstate = regs; + memstate = Map.empty; + tagstate = Map.empty; + write_ea = Nothing; + last_exclusive_operation_was_load = false |> + +type ex 'e = + | Exit + | Assert of string + | Throw of 'e + +type result 'a 'e = + | Value of 'a + | Exception of (ex 'e) + +(* State, nondeterminism and exception monad with result value type 'a + and exception type 'e. *) +type M 'regs 'a 'e = sequential_state 'regs -> list (result 'a 'e * sequential_state 'regs) + +val return : forall 'regs 'a 'e. 'a -> M 'regs 'a 'e +let return a s = [(Value a,s)] + +val bind : forall 'regs 'a 'b 'e. M 'regs 'a 'e -> ('a -> M 'regs 'b 'e) -> M 'regs 'b 'e +let bind m f (s : sequential_state 'regs) = + List.concatMap (function + | (Value a, s') -> f a s' + | (Exception e, s') -> [(Exception e, s')] + end) (m s) + +let inline (>>=) = bind +val (>>): forall 'regs 'b 'e. M 'regs unit 'e -> M 'regs 'b 'e -> M 'regs 'b 'e +let inline (>>) m n = m >>= fun (_ : unit) -> n + +val throw : forall 'regs 'a 'e. 'e -> M 'regs 'a 'e +let throw e s = [(Exception (Throw e), s)] + +val try_catch : forall 'regs 'a 'e1 'e2. M 'regs 'a 'e1 -> ('e1 -> M 'regs 'a 'e2) -> M 'regs 'a 'e2 +let try_catch m h s = + List.concatMap (function + | (Value a, s') -> return a s' + | (Exception (Throw e), s') -> h e s' + | (Exception Exit, s') -> [(Exception Exit, s')] + | (Exception (Assert msg), s') -> [(Exception (Assert msg), s')] + end) (m s) + +val exit : forall 'regs 'e 'a. unit -> M 'regs 'a 'e +let exit () s = [(Exception Exit, s)] + +val assert_exp : forall 'regs 'e. bool -> string -> M 'regs unit 'e +let assert_exp exp msg s = if exp then [(Value (), s)] else [(Exception (Assert msg), s)] + +(* For early return, we abuse exceptions by throwing and catching + the return value. The exception type is "either 'r 'e", where "Right e" + represents a proper exception and "Left r" an early return of value "r". *) +type MR 'regs 'a 'r 'e = M 'regs 'a (either 'r 'e) + +val early_return : forall 'regs 'a 'r 'e. 'r -> MR 'regs 'a 'r 'e +let early_return r = throw (Left r) + +val catch_early_return : forall 'regs 'a 'e. MR 'regs 'a 'a 'e -> M 'regs 'a 'e +let catch_early_return m = + try_catch m + (function + | Left a -> return a + | Right e -> throw e + end) + +(* Lift to monad with early return by wrapping exceptions *) +val liftR : forall 'a 'r 'regs 'e. M 'regs 'a 'e -> MR 'regs 'a 'r 'e +let liftR m = try_catch m (fun e -> throw (Right e)) + +(* Catch exceptions in the presence of early returns *) +val try_catchR : forall 'regs 'a 'r 'e1 'e2. MR 'regs 'a 'r 'e1 -> ('e1 -> MR 'regs 'a 'r 'e2) -> MR 'regs 'a 'r 'e2 +let try_catchR m h = + try_catch m + (function + | Left r -> throw (Left r) + | Right e -> h e + end) + +val range : integer -> integer -> list integer +let rec range i j = + if j < i then [] + else if i = j then [i] + else i :: range (i+1) j + +val get_reg : forall 'regs 'a. sequential_state 'regs -> register_ref 'regs 'a -> 'a +let get_reg state reg = reg.read_from state.regstate + +val set_reg : forall 'regs 'a. sequential_state 'regs -> register_ref 'regs 'a -> 'a -> sequential_state 'regs +let set_reg state reg v = + <| state with regstate = reg.write_to state.regstate v |> + + +let is_exclusive = function + | Sail_impl_base.Read_plain -> false + | Sail_impl_base.Read_reserve -> true + | Sail_impl_base.Read_acquire -> false + | Sail_impl_base.Read_exclusive -> true + | Sail_impl_base.Read_exclusive_acquire -> true + | Sail_impl_base.Read_stream -> false + | Sail_impl_base.Read_RISCV_acquire -> false + | Sail_impl_base.Read_RISCV_strong_acquire -> false + | Sail_impl_base.Read_RISCV_reserved -> true + | Sail_impl_base.Read_RISCV_reserved_acquire -> true + | Sail_impl_base.Read_RISCV_reserved_strong_acquire -> true + | Sail_impl_base.Read_X86_locked -> true +end + + +val read_mem : forall 'regs 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> M 'regs 'b 'e +let read_mem read_kind addr sz state = + let addr = unsigned addr in + let addrs = range addr (addr+sz-1) in + let memory_value = List.map (fun addr -> Map_extra.find addr state.memstate) addrs in + let value = of_bits (Sail_values.internal_mem_value memory_value) in + if is_exclusive read_kind + then [(Value value, <| state with last_exclusive_operation_was_load = true |>)] + else [(Value value, state)] + +(* caps are aligned at 32 bytes *) +let cap_alignment = (32 : integer) + +val read_tag : forall 'regs 'a 'e. Bitvector 'a => read_kind -> 'a -> M 'regs bitU 'e +let read_tag read_kind addr state = + let addr = (unsigned addr) / cap_alignment in + let tag = match (Map.lookup addr state.tagstate) with + | Just t -> t + | Nothing -> B0 + end in + if is_exclusive read_kind + then [(Value tag, <| state with last_exclusive_operation_was_load = true |>)] + else [(Value tag, state)] + +val excl_result : forall 'regs 'e. unit -> M 'regs bool 'e +let excl_result () state = + let success = + (Value true, <| state with last_exclusive_operation_was_load = false |>) in + (Value false, state) :: if state.last_exclusive_operation_was_load then [success] else [] + +val write_mem_ea : forall 'regs 'a 'e. Bitvector 'a => write_kind -> 'a -> integer -> M 'regs unit 'e +let write_mem_ea write_kind addr sz state = + [(Value (), <| state with write_ea = Just (write_kind,unsigned addr,sz) |>)] + +val write_mem_val : forall 'a 'regs 'b 'e. Bitvector 'a => 'a -> M 'regs bool 'e +let write_mem_val v state = + let (_,addr,sz) = match state.write_ea with + | Nothing -> failwith "write ea has not been announced yet" + | Just write_ea -> write_ea end in + let addrs = range addr (addr+sz-1) in + let v = external_mem_value (bits_of v) in + let addresses_with_value = List.zip addrs v in + let memstate = List.foldl (fun mem (addr,v) -> Map.insert addr v mem) + state.memstate addresses_with_value in + [(Value true, <| state with memstate = memstate |>)] + +val write_tag : forall 'regs 'e. bitU -> M 'regs bool 'e +let write_tag t state = + let (_,addr,_) = match state.write_ea with + | Nothing -> failwith "write ea has not been announced yet" + | Just write_ea -> write_ea end in + let taddr = addr / cap_alignment in + let tagstate = Map.insert taddr t state.tagstate in + [(Value true, <| state with tagstate = tagstate |>)] + +val read_reg : forall 'regs 'a 'e. register_ref 'regs 'a -> M 'regs 'a 'e +let read_reg reg state = + let v = reg.read_from state.regstate in + [(Value v,state)] +(*let read_reg_range reg i j state = + let v = slice (get_reg state (name_of_reg reg)) i j in + [(Value (vec_to_bvec v),state)] +let read_reg_bit reg i state = + let v = access (get_reg state (name_of_reg reg)) i in + [(Value v,state)] +let read_reg_field reg regfield = + let (i,j) = register_field_indices reg regfield in + read_reg_range reg i j +let read_reg_bitfield reg regfield = + let (i,_) = register_field_indices reg regfield in + read_reg_bit reg i *) + +let reg_deref = read_reg + +val write_reg : forall 'regs 'a 'e. register_ref 'regs 'a -> 'a -> M 'regs unit 'e +let write_reg reg v state = + [(Value (), <| state with regstate = reg.write_to state.regstate v |>)] + +let write_reg_ref (reg, v) = write_reg reg v + +val update_reg : forall 'regs 'a 'b 'e. register_ref 'regs 'a -> ('a -> 'b -> 'a) -> 'b -> M 'regs unit 'e +let update_reg reg f v state = + let current_value = get_reg state reg in + let new_value = f current_value v in + [(Value (), set_reg state reg new_value)] + +let write_reg_field reg regfield = update_reg reg regfield.set_field + +val update_reg_range : forall 'regs 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'a -> integer -> integer -> 'a -> 'b -> 'a +let update_reg_range reg i j reg_val new_val = set_bits (reg.reg_is_inc) reg_val i j (bits_of new_val) +let write_reg_range reg i j = update_reg reg (update_reg_range reg i j) + +let update_reg_pos reg i reg_val x = update_list reg.reg_is_inc reg_val i x +let write_reg_pos reg i = update_reg reg (update_reg_pos reg i) + +let update_reg_bit reg i reg_val bit = set_bit (reg.reg_is_inc) reg_val i (to_bitU bit) +let write_reg_bit reg i = update_reg reg (update_reg_bit reg i) + +let update_reg_field_range regfield i j reg_val new_val = + let current_field_value = regfield.get_field reg_val in + let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in + regfield.set_field reg_val new_field_value +let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j) + +let update_reg_field_pos regfield i reg_val x = + let current_field_value = regfield.get_field reg_val in + let new_field_value = update_list regfield.field_is_inc current_field_value i x in + regfield.set_field reg_val new_field_value +let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i) + +let update_reg_field_bit regfield i reg_val bit = + let current_field_value = regfield.get_field reg_val in + let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in + regfield.set_field reg_val new_field_value +let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i) + +val barrier : forall 'regs 'e. barrier_kind -> M 'regs unit 'e +let barrier _ = return () + +val footprint : forall 'regs 'e. M 'regs unit 'e +let footprint s = return () s diff --git a/src/isail.ml b/src/isail.ml index 07a72bd2..ffeb1442 100644 --- a/src/isail.ml +++ b/src/isail.ml @@ -296,7 +296,7 @@ let handle_input' input = vs_ids := Initial_check.val_spec_ids !interactive_ast | ":compile" -> let exp = Type_check.infer_exp !interactive_env (Initial_check.exp_of_string Ast_util.dec_ord arg) in - let anf = C_backend.compile_exp !interactive_env exp in + let anf = C_backend.compile_exp (C_backend.initial_ctx !interactive_env) exp in print_endline (Pretty_print_sail.to_string (C_backend.pp_aexp anf)) | ":u" | ":unload" -> interactive_ast := Ast.Defs []; diff --git a/src/lexer.mll b/src/lexer.mll index 77fba70b..3538d5cb 100644 --- a/src/lexer.mll +++ b/src/lexer.mll @@ -93,7 +93,14 @@ let mk_operator prec n op = | InfixR, 9 -> Op9r op | _, _ -> assert false -let operators = ref M.empty +let operators = ref + (List.fold_left + (fun r (x, y) -> M.add x y r) + M.empty + [ ("==", mk_operator Infix 4 "=="); + ("/", mk_operator InfixL 7 "/"); + ("%", mk_operator InfixL 7 "%"); + ]) let kw_table = List.fold_left diff --git a/src/monomorphise.ml b/src/monomorphise.ml index a4d404e1..3b8a5073 100644 --- a/src/monomorphise.ml +++ b/src/monomorphise.ml @@ -520,7 +520,12 @@ let nexp_subst_fns substs = | E_id _ | E_lit _ | E_comment _ -> re e - | E_sizeof ne -> re (E_sizeof ne) (* TODO: does this need done? does it appear in type checked code? *) + | E_sizeof ne -> begin + let ne' = subst_nexp substs ne in + match ne' with + | Nexp_aux (Nexp_constant i,l) -> re (E_lit (L_aux (L_num i,l))) + | _ -> re (E_sizeof ne') + end | E_constraint nc -> re (E_constraint (subst_nc substs nc)) | E_internal_exp (l,annot) -> re (E_internal_exp (l, s_tannot annot)) | E_sizeof_internal (l,annot) -> re (E_sizeof_internal (l, s_tannot annot)) @@ -789,14 +794,17 @@ let construct_lit_vector args = | _ -> None in aux [] args +type pat_choice = Parse_ast.l * (int * int * (id * tannot exp) list) + (* We may need to split up a pattern match if (1) we've been told to case split on a variable by the user or analysis, or (2) we monomorphised a constructor that's used in the pattern. *) type split = | NoSplit - | VarSplit of (tannot pat * (* pattern for this case *) - (id * tannot Ast.exp) list * (* substitutions for arguments *) - (Parse_ast.l * (int * (id * tannot exp) list)) list) (* optional locations of case expressions to reduce *) + | VarSplit of (tannot pat * (* pattern for this case *) + (id * tannot Ast.exp) list * (* substitutions for arguments *) + pat_choice list * (* optional locations of constraints/case expressions to reduce *) + (kid * nexp) list) (* substitutions for type variables *) list | ConstrSplit of (tannot pat * nexp KBindings.t) list @@ -896,23 +904,96 @@ let rec freshen_pat_bindings p = FP_aux (FP_Fpat (id, p),(Generated l,annot)), vs in aux p +(* This cuts off function bodies at false assertions that we may have produced + in a wildcard pattern match. It should handle the same assertions that + find_set_assertions does. *) +let stop_at_false_assertions e = + let dummy_value_of_typ typ = + let l = Generated Unknown in + E_aux (E_exit (E_aux (E_lit (L_aux (L_unit,l)),(l,None))),(l,None)) + in + let rec exp (E_aux (e,ann) as ea) = + match e with + | E_block es -> + let rec aux = function + | [] -> [], None + | e::es -> let e,stop = exp e in + match stop with + | Some _ -> [e],stop + | None -> + let es',stop = aux es in + e::es',stop + in let es,stop = aux es in begin + match stop with + | None -> E_aux (E_block es,ann), stop + | Some typ -> + let typ' = typ_of_annot ann in + if Type_check.alpha_equivalent (env_of_annot ann) typ typ' + then E_aux (E_block es,ann), stop + else E_aux (E_block (es@[dummy_value_of_typ typ']),ann), Some typ' + end + | E_nondet es -> + let es,stops = List.split (List.map exp es) in + let stop = List.exists (function Some _ -> true | _ -> false) stops in + let stop = if stop then Some (typ_of_annot ann) else None in + E_aux (E_nondet es,ann), stop + | E_cast (typ,e) -> let e,stop = exp e in + let stop = match stop with Some _ -> Some typ | None -> None in + E_aux (E_cast (typ,e),ann),stop + | E_let (LB_aux (LB_val (p,e1),lbann),e2) -> + let e1,stop = exp e1 in begin + match stop with + | Some _ -> e1,stop + | None -> + let e2,stop = exp e2 in + E_aux (E_let (LB_aux (LB_val (p,e1),lbann),e2),ann), stop + end + | E_assert (E_aux (E_constraint (NC_aux (NC_false,_)),_),_) -> + ea, Some (typ_of_annot ann) + | E_assert (E_aux (E_lit (L_aux (L_false,_)),_),_) -> + ea, Some (typ_of_annot ann) + | _ -> ea, None + in fst (exp e) + (* Use the location pairs in choices to reduce case expressions at the first location to the given case at the second. *) let apply_pat_choices choices = - let rewrite_constraint (NC_aux (nc,l) as nconstr) = E_constraint nconstr (* - Not right now - false cases may not type check + let rec rewrite_ncs (NC_aux (nc,l) as nconstr) = + match nc with + | NC_set (kid,is) -> begin + match List.assoc l choices with + | choice,max,_ -> + NC_aux ((if choice < max then NC_true else NC_false), Generated l) + | exception Not_found -> nconstr + end + | NC_and (nc1,nc2) -> begin + match rewrite_ncs nc1, rewrite_ncs nc2 with + | NC_aux (NC_false,l), _ + | _, NC_aux (NC_false,l) -> NC_aux (NC_false,l) + | nc1,nc2 -> NC_aux (NC_and (nc1,nc2),l) + end + | _ -> nconstr + in + let rec rewrite_assert_cond (E_aux (e,(l,ann)) as exp) = match List.assoc l choices with - | choice,_ -> begin - match nc with - | NC_set (kid,is) -> - E_constraint (NC_aux ((if choice < List.length is then NC_true else NC_false), Generated l)) - | _ -> E_constraint nconstr - end - | exception Not_found -> E_constraint nconstr*) + | choice,max,_ -> + E_aux (E_lit (L_aux ((if choice < max then L_true else L_false (* wildcard *)), + Generated l)),(Generated l,ann)) + | exception Not_found -> + match e with + | E_constraint nc -> E_aux (E_constraint (rewrite_ncs nc),(l,ann)) + | E_app (Id_aux (Id "and_bool",andl), [e1;e2]) -> + E_aux (E_app (Id_aux (Id "and_bool",andl), + [rewrite_assert_cond e1; + rewrite_assert_cond e2]),(l,ann)) + | _ -> exp + in + let rewrite_assert (e1,e2) = + E_assert (rewrite_assert_cond e1, e2) in let rewrite_case (e,cases) = match List.assoc (exp_loc e) choices with - | choice,subst -> + | choice,max,subst -> (match List.nth cases choice with | Pat_aux (Pat_exp (p,E_aux (e,_)),_) -> let dummyannot = (Generated Unknown,None) in @@ -929,10 +1010,11 @@ let apply_pat_choices choices = in let open Rewriter in fold_exp { id_exp_alg with - e_constraint = rewrite_constraint; + e_assert = rewrite_assert; e_case = rewrite_case } -let split_defs continue_anyway splits defs = +let split_defs all_errors splits defs = + let no_errors_happened = ref true in let split_constructors (Defs defs) = let sc_type_union q (Tu_aux (tu,l) as tua) = match tu with @@ -1374,27 +1456,29 @@ let split_defs continue_anyway splits defs = let error = Err_general (pat_l, ("Cannot split type " ^ string_of_typ typ ^ " for variable " ^ v ^ ": " ^ msg)) - in if continue_anyway - then (print_error error; [P_aux (P_id var,(pat_l,annot)),[],[]]) + in if all_errors + then (no_errors_happened := false; + print_error error; + [P_aux (P_id var,(pat_l,annot)),[],[],[]]) else raise (Fatal_error error) in match ty with | Typ_id (Id_aux (Id "bool",_)) -> - [P_aux (P_lit (L_aux (L_true,new_l)),(l,annot)),[var, E_aux (E_lit (L_aux (L_true,new_l)),(new_l,annot))],[]; - P_aux (P_lit (L_aux (L_false,new_l)),(l,annot)),[var, E_aux (E_lit (L_aux (L_false,new_l)),(new_l,annot))],[]] + [P_aux (P_lit (L_aux (L_true,new_l)),(l,annot)),[var, E_aux (E_lit (L_aux (L_true,new_l)),(new_l,annot))],[],[]; + P_aux (P_lit (L_aux (L_false,new_l)),(l,annot)),[var, E_aux (E_lit (L_aux (L_false,new_l)),(new_l,annot))],[],[]] | Typ_id id -> (try (* enumerations *) let ns = Env.get_enum id env in List.map (fun n -> (P_aux (P_id (renew_id n),(l,annot)), - [var,E_aux (E_id (renew_id n),(new_l,annot))],[])) ns + [var,E_aux (E_id (renew_id n),(new_l,annot))],[],[])) ns with Type_error _ -> match id with | Id_aux (Id "bit",_) -> List.map (fun b -> P_aux (P_lit (L_aux (b,new_l)),(l,annot)), - [var,E_aux (E_lit (L_aux (b,new_l)),(new_l, annot))],[]) + [var,E_aux (E_lit (L_aux (b,new_l)),(new_l, annot))],[],[]) [L_zero; L_one] | _ -> cannot ("don't know about type " ^ string_of_id id)) @@ -1404,25 +1488,26 @@ let split_defs continue_anyway splits defs = let lits = make_vectors (Big_int.to_int sz) in List.map (fun lit -> P_aux (P_lit lit,(l,annot)), - [var,E_aux (E_lit lit,(new_l,annot))],[]) lits + [var,E_aux (E_lit lit,(new_l,annot))],[],[]) lits | _ -> cannot ("length not constant, " ^ string_of_nexp len) ) (* set constrained numbers *) | Typ_app (Id_aux (Id "atom",_), [Typ_arg_aux (Typ_arg_nexp (Nexp_aux (value,_) as nexp),_)]) -> begin - let mk_lit i = + let mk_lit kid i = let lit = L_aux (L_num i,new_l) in P_aux (P_lit lit,(l,annot)), - [var,E_aux (E_lit lit,(new_l,annot))],[] + [var,E_aux (E_lit lit,(new_l,annot))],[], + match kid with None -> [] | Some k -> [(k,nconstant i)] in match value with - | Nexp_constant i -> [mk_lit i] + | Nexp_constant i -> [mk_lit None i] | Nexp_var kvar -> let ncs = Env.get_constraints env in let nc = List.fold_left nc_and nc_true ncs in (match extract_set_nc l kvar nc with - | (is,_) -> List.map mk_lit is + | (is,_) -> List.map (mk_lit (Some kvar)) is | exception Reporting_basic.Fatal_error (Reporting_basic.Err_general (_,msg)) -> cannot msg) | _ -> cannot ("unsupport atom nexp " ^ string_of_nexp nexp) end @@ -1456,32 +1541,32 @@ let split_defs continue_anyway splits defs = | h::t -> let t' = match list f t with - | None -> [t,[],[]] + | None -> [t,[],[],[]] | Some t' -> t' in let h' = match f h with - | None -> [h,[],[]] + | None -> [h,[],[],[]] | Some ps -> ps in Some (List.concat - (List.map (fun (h,hsubs,hpchoices) -> - List.map (fun (t,tsubs,tpchoices) -> - (h::t, hsubs@tsubs, hpchoices@tpchoices)) t') h')) + (List.map (fun (h,hsubs,hpchoices,hksubs) -> + List.map (fun (t,tsubs,tpchoices,tksubs) -> + (h::t, hsubs@tsubs, hpchoices@tpchoices, hksubs@tksubs)) t') h')) in let rec spl (P_aux (p,(l,annot))) = let relist f ctx ps = optmap (list f ps) (fun ps -> - List.map (fun (ps,sub,pchoices) -> P_aux (ctx ps,(l,annot)),sub,pchoices) ps) + List.map (fun (ps,sub,pchoices,ksub) -> P_aux (ctx ps,(l,annot)),sub,pchoices,ksub) ps) in let re f p = optmap (spl p) - (fun ps -> List.map (fun (p,sub,pchoices) -> (P_aux (f p,(l,annot)), sub, pchoices)) ps) + (fun ps -> List.map (fun (p,sub,pchoices,ksub) -> (P_aux (f p,(l,annot)), sub, pchoices, ksub)) ps) in let fpat (FP_aux ((FP_Fpat (id,p),annot))) = optmap (spl p) - (fun ps -> List.map (fun (p,sub,pchoices) -> FP_aux (FP_Fpat (id,p), annot), sub, pchoices) ps) + (fun ps -> List.map (fun (p,sub,pchoices,ksub) -> FP_aux (FP_Fpat (id,p), annot), sub, pchoices, ksub) ps) in match p with | P_lit _ @@ -1503,18 +1588,29 @@ let split_defs continue_anyway splits defs = literal as normal, but perform a more careful transformation otherwise *) | Some (Some (pats,l)) -> + let max = List.length pats - 1 in Some (List.mapi (fun i p -> match p with | P_aux (P_lit lit,(pl,pannot)) when (match lit with L_aux (L_undef,_) -> false | _ -> true) -> - p,[id,E_aux (E_lit lit,(Generated pl,pannot))],[l,(i,[])] + let orig_typ = Env.base_typ_of (env_of_annot (l,annot)) (typ_of_annot (l,annot)) in + let kid_subst = match lit, orig_typ with + | L_aux (L_num i,_), + Typ_aux + (Typ_app (Id_aux (Id "atom",_), + [Typ_arg_aux (Typ_arg_nexp + (Nexp_aux (Nexp_var var,_)),_)]),_) -> + [var,nconstant i] + | _ -> [] + in + p,[id,E_aux (E_lit lit,(Generated pl,pannot))],[l,(i,max,[])],kid_subst | _ -> let p',subst = freshen_pat_bindings p in match p' with | P_aux (P_wild,_) -> - P_aux (P_id id,(l,annot)),[],[l,(i,subst)] + P_aux (P_id id,(l,annot)),[],[l,(i,max,subst)],[] | _ -> - P_aux (P_as (p',id),(l,annot)),[],[l,(i,subst)]) + P_aux (P_as (p',id),(l,annot)),[],[l,(i,max,subst)],[]) pats) ) | P_app (id,ps) -> @@ -1533,10 +1629,10 @@ let split_defs continue_anyway splits defs = match spl p1, spl p2 with | None, None -> None | p1', p2' -> - let p1' = match p1' with None -> [p1,[],[]] | Some p1' -> p1' in - let p2' = match p2' with None -> [p2,[],[]] | Some p2' -> p2' in - let ps = List.map (fun (p1',subs1,pchoices1) -> List.map (fun (p2',subs2,pchoices2) -> - P_aux (P_cons (p1',p2'),(l,annot)),subs1@subs2,pchoices1@pchoices2) p2') p1' in + let p1' = match p1' with None -> [p1,[],[],[]] | Some p1' -> p1' in + let p2' = match p2' with None -> [p2,[],[],[]] | Some p2' -> p2' in + let ps = List.map (fun (p1',subs1,pchoices1,ksub1) -> List.map (fun (p2',subs2,pchoices2,ksub2) -> + P_aux (P_cons (p1',p2'),(l,annot)),subs1@subs2,pchoices1@pchoices2,ksub1@ksub2) p2') p1' in Some (List.concat ps) in spl p in @@ -1604,8 +1700,9 @@ let split_defs continue_anyway splits defs = let error = Err_general (l, "Case split is too large (" ^ string_of_int size ^ " > limit " ^ string_of_int size_set_limit ^ ")") - in if continue_anyway - then (print_error error; false) + in if all_errors + then (no_errors_happened := false; + print_error error; false) else raise (Fatal_error error) else true in @@ -1677,9 +1774,11 @@ let split_defs continue_anyway splits defs = | NoSplit -> nosplit | VarSplit patsubsts -> if check_split_size patsubsts (pat_loc p) then - List.map (fun (pat',substs,pchoices) -> - let exp' = subst_exp substs e in + List.map (fun (pat',substs,pchoices,ksubsts) -> + let exp' = nexp_subst_exp (kbindings_from_list ksubsts) e in + let exp' = subst_exp substs exp' in let exp' = apply_pat_choices pchoices exp' in + let exp' = stop_at_false_assertions exp' in Pat_aux (Pat_exp (pat', map_exp exp'),l)) patsubsts else nosplit @@ -1695,11 +1794,14 @@ let split_defs continue_anyway splits defs = | NoSplit -> nosplit | VarSplit patsubsts -> if check_split_size patsubsts (pat_loc p) then - List.map (fun (pat',substs,pchoices) -> - let exp1' = subst_exp substs e1 in + List.map (fun (pat',substs,pchoices,ksubsts) -> + let exp1' = nexp_subst_exp (kbindings_from_list ksubsts) e1 in + let exp1' = subst_exp substs exp1' in let exp1' = apply_pat_choices pchoices exp1' in - let exp2' = subst_exp substs e2 in + let exp2' = nexp_subst_exp (kbindings_from_list ksubsts) e2 in + let exp2' = subst_exp substs exp2' in let exp2' = apply_pat_choices pchoices exp2' in + let exp2' = stop_at_false_assertions exp2' in Pat_aux (Pat_when (pat', map_exp exp1', map_exp exp2'),l)) patsubsts else nosplit @@ -1757,7 +1859,8 @@ let split_defs continue_anyway splits defs = in Defs (List.concat (List.map map_def defs)) in - map_locs splits defs' + let defs'' = map_locs splits defs' in + !no_errors_happened, defs'' @@ -1902,7 +2005,7 @@ let rewrite_size_parameters env (Defs defs) = pat_exp = (fun ((sp,pat),(s,e)) -> KidSet.diff s (tyvars_bound_in_pat pat), Pat_exp (pat,e))} pexp) in - let sizes_funcl fsizes (FCL_aux (FCL_Funcl (id,pexp),(l,_))) = + let exposed_sizes_funcl fnsizes (FCL_aux (FCL_Funcl (id,pexp),(l,_))) = let sizes = size_vars pexp in let pat,guard,exp,pannot = destruct_pexp pexp in let visible_tyvars = @@ -1911,6 +2014,10 @@ let rewrite_size_parameters env (Defs defs) = (Pretty_print_lem.lem_tyvars_of_typ (typ_of exp)) in let expose_tyvars = KidSet.diff sizes visible_tyvars in + KidSet.union fnsizes expose_tyvars + in + let sizes_funcl expose_tyvars fsizes (FCL_aux (FCL_Funcl (id,pexp),(l,_))) = + let pat,guard,exp,pannot = destruct_pexp pexp in let parameters = match pat with | P_aux (P_tup ps,_) -> ps | _ -> [pat] @@ -1942,13 +2049,16 @@ let rewrite_size_parameters env (Defs defs) = let to_change = List.sort ik_compare to_change in match Bindings.find id fsizes with | old -> if List.for_all2 (fun x y -> ik_compare x y = 0) old to_change then fsizes else + let str l = String.concat "," (List.map (fun (i,k) -> string_of_int i ^ "." ^ string_of_kid k) l) in raise (Reporting_basic.err_general l - ("Different size type variables in different clauses of " ^ string_of_id id)) + ("Different size type variables in different clauses of " ^ string_of_id id ^ + " old: " ^ str old ^ " new: " ^ str to_change)) | exception Not_found -> Bindings.add id to_change fsizes in let sizes_def fsizes = function | DEF_fundef (FD_aux (FD_function (_,_,_,funcls),_)) -> - List.fold_left sizes_funcl fsizes funcls + let expose_tyvars = List.fold_left exposed_sizes_funcl KidSet.empty funcls in + List.fold_left (sizes_funcl expose_tyvars) fsizes funcls | _ -> fsizes in let fn_sizes = List.fold_left sizes_def Bindings.empty defs in @@ -2098,6 +2208,17 @@ module ArgSplits = Map.Make (struct end) type arg_splits = match_detail ArgSplits.t +(* Function id, funcl loc for adding splits on sizes in the body when + there's no corresponding argument *) +module ExtraSplits = Map.Make (struct + type t = id * Parse_ast.l + let compare (id,l) (id',l') = + let x = Id.compare id id' in + if x <> 0 then x else + compare l l' +end) +type extra_splits = (match_detail KBindings.t) ExtraSplits.t + (* Arguments that we should look at in callers *) module CallerArgSet = Set.Make (struct type t = id * int @@ -2124,8 +2245,7 @@ module StringSet = Set.Make (struct end) type dependencies = - | Have of arg_splits * CallerArgSet.t * CallerKidSet.t - (* args to split inside fn * caller args to split * caller kids that are bitvector parameters *) + | Have of arg_splits * extra_splits | Unknown of Parse_ast.l * string let string_of_match_detail = function @@ -2138,6 +2258,26 @@ let string_of_argsplits s = string_of_id id ^ "." ^ string_of_loc l ^ string_of_match_detail detail) (ArgSplits.bindings s)) +let string_of_lx lx = + let open Lexing in + Printf.sprintf "%s,%d,%d,%d" lx.pos_fname lx.pos_lnum lx.pos_bol lx.pos_cnum + +let rec simple_string_of_loc = function + | Parse_ast.Unknown -> "Unknown" + | Parse_ast.Int (s,None) -> "Int(" ^ s ^ ",None)" + | Parse_ast.Int (s,Some l) -> "Int(" ^ s ^ ",Some("^simple_string_of_loc l^"))" + | Parse_ast.Generated l -> "Generated(" ^ simple_string_of_loc l ^ ")" + | Parse_ast.Range (lx1,lx2) -> "Range(" ^ string_of_lx lx1 ^ "->" ^ string_of_lx lx2 ^ ")" + +let string_of_extra_splits s = + String.concat ", " + (List.map (fun ((id,l),ks) -> + string_of_id id ^ "." ^ simple_string_of_loc l ^ ":" ^ + (String.concat "," (List.map (fun (kid,detail) -> + string_of_kid kid ^ "." ^ string_of_match_detail detail) + (KBindings.bindings ks)))) + (ExtraSplits.bindings s)) + let string_of_callerset s = String.concat ", " (List.map (fun (id,arg) -> string_of_id id ^ "." ^ string_of_int arg) (CallerArgSet.elements s)) @@ -2147,31 +2287,40 @@ let string_of_callerkidset s = (CallerKidSet.elements s)) let string_of_dep = function - | Have (args,callset,kidset) -> - "Have (" ^ string_of_argsplits args ^ "; " ^ string_of_callerset callset ^ "; " ^ - string_of_callerkidset kidset ^ ")" + | Have (args,extras) -> + "Have (" ^ string_of_argsplits args ^ ";" ^ string_of_extra_splits extras ^ ")" | Unknown (l,msg) -> "Unknown " ^ msg ^ " at " ^ Reporting_basic.loc_to_string l +(* If a callee uses a type variable as a size, does it need to be split in the + current function, or is it also a parameter? (Note that there may be multiple + calls, so more than one parameter can be involved) *) +type call_dep = + | InFun of dependencies + | Parents of CallerKidSet.t + (* Result of analysing the body of a function. The split field gives - the arguments to split based on the body alone, and the failures - field where we couldn't do anything. The other fields are used at - the end for the interprocedural phase. *) + the arguments to split based on the body alone, the extra_splits + field where we want to case split on a size type variable but + there's no corresponding argument so we introduce a case + expression, and the failures field where we couldn't do anything. + The other fields are used at the end for the interprocedural + phase. *) type result = { split : arg_splits; + extra_splits : extra_splits; failures : StringSet.t Failures.t; - (* Dependencies for arguments and type variables of each fn called, so that + (* Dependencies for type variables of each fn called, so that if the fn uses one for a bitvector size we can track it back *) - split_on_call : (dependencies list * dependencies KBindings.t) Bindings.t; (* (arguments, kids) per fn *) - split_in_caller : CallerArgSet.t; + split_on_call : (call_dep KBindings.t) Bindings.t; (* kids per fn *) kid_in_caller : CallerKidSet.t } let empty = { split = ArgSplits.empty; + extra_splits = ExtraSplits.empty; failures = Failures.empty; split_on_call = Bindings.empty; - split_in_caller = CallerArgSet.empty; kid_in_caller = CallerKidSet.empty } @@ -2183,39 +2332,48 @@ let merge_detail _ x y = when l1 = l2 && forall2 pat_eq ps1 ps2 -> x | _ -> Some Total +let opt_merge f _ x y = + match x,y with + | None, _ -> y + | _, None -> x + | Some x, Some y -> Some (f x y) + +let merge_extras = ExtraSplits.merge (opt_merge (KBindings.merge merge_detail)) + let dmerge x y = match x,y with | Unknown (l,s), _ -> Unknown (l,s) | _, Unknown (l,s) -> Unknown (l,s) - | Have (a,c,k), Have (a',c',k') -> - Have (ArgSplits.merge merge_detail a a', CallerArgSet.union c c', CallerKidSet.union k k') - -let dempty = Have (ArgSplits.empty, CallerArgSet.empty, CallerKidSet.empty) + | Have (args,extras), Have (args',extras') -> + Have (ArgSplits.merge merge_detail args args', + merge_extras extras extras') -let dopt_merge k x y = - match x, y with - | None, _ -> y - | _, None -> x - | Some x, Some y -> Some (dmerge x y) +let dempty = Have (ArgSplits.empty, ExtraSplits.empty) let dep_bindings_merge a1 a2 = - Bindings.merge dopt_merge a1 a2 + Bindings.merge (opt_merge dmerge) a1 a2 let dep_kbindings_merge a1 a2 = - KBindings.merge dopt_merge a1 a2 + KBindings.merge (opt_merge dmerge) a1 a2 let call_kid_merge k x y = match x, y with | None, x -> x | x, None -> x - | Some d, Some d' -> Some (dmerge d d') + | Some (InFun deps), Some (Parents _) + | Some (Parents _), Some (InFun deps) + -> Some (InFun deps) + | Some (InFun deps), Some (InFun deps') + -> Some (InFun (dmerge deps deps')) + | Some (Parents fns), Some (Parents fns') + -> Some (Parents (CallerKidSet.union fns fns')) let call_arg_merge k args args' = match args, args' with | None, x -> x | x, None -> x - | Some (args,kdep), Some (args',kdep') - -> Some (List.map2 dmerge args args', KBindings.merge call_kid_merge kdep kdep') + | Some kdep, Some kdep' + -> Some (KBindings.merge call_kid_merge kdep kdep') let failure_merge _ x y = match x, y with @@ -2225,9 +2383,9 @@ let failure_merge _ x y = let merge rs rs' = { split = ArgSplits.merge merge_detail rs.split rs'.split; + extra_splits = merge_extras rs.extra_splits rs'.extra_splits; failures = Failures.merge failure_merge rs.failures rs'.failures; split_on_call = Bindings.merge call_arg_merge rs.split_on_call rs'.split_on_call; - split_in_caller = CallerArgSet.union rs.split_in_caller rs'.split_in_caller; kid_in_caller = CallerKidSet.union rs.kid_in_caller rs'.kid_in_caller } @@ -2316,11 +2474,14 @@ let rec deps_of_nc kid_deps (NC_aux (nc,l)) = let deps_of_typ kid_deps arg_deps typ = deps_of_tyvars kid_deps arg_deps (tyvars_of_typ typ) -let deps_of_uvar kid_deps arg_deps = function - | U_nexp nexp -> deps_of_nexp kid_deps arg_deps nexp +let deps_of_uvar fn_id env arg_deps = function + | U_nexp (Nexp_aux (Nexp_var kid,_)) + when List.exists (fun k -> Kid.compare kid k == 0) env.top_kids -> + Parents (CallerKidSet.singleton (fn_id,kid)) + | U_nexp nexp -> InFun (deps_of_nexp env.kid_deps arg_deps nexp) | U_order _ - | U_effect _ -> dempty - | U_typ typ -> deps_of_typ kid_deps arg_deps typ + | U_effect _ -> InFun dempty + | U_typ typ -> InFun (deps_of_typ env.kid_deps arg_deps typ) let mk_subrange_pattern vannot vstart vend = let (_,len,ord,typ) = vector_typ_args_of (Env.base_typ_of (env_of_annot vannot) (typ_of_annot vannot)) in @@ -2358,27 +2519,27 @@ let mk_subrange_pattern vannot vstart vend = let refine_dependency env (E_aux (e,(l,annot)) as exp) pexps = let check_dep id ctx = match Bindings.find id env.var_deps with - | Have (args,callargs,callkids) -> - if CallerArgSet.is_empty callargs && CallerKidSet.is_empty callkids then - match ArgSplits.bindings args with - | [(id',loc),Total] when Id.compare id id' == 0 -> - (match Util.map_all (function - | Pat_aux (Pat_exp (pat,_),_) -> Some (ctx pat) - | Pat_aux (Pat_when (_,_,_),_) -> None) pexps - with - | Some pats -> - if l = Parse_ast.Unknown then - (Reporting_basic.print_error - (Reporting_basic.Err_general - (l, "No location for pattern match: " ^ string_of_exp exp)); - None) - else - Some (Have (ArgSplits.singleton (id,loc) (Partial (pats,l)),callargs,callkids)) - | None -> None) - | _ -> None - else None - | Unknown _ -> None - | exception Not_found -> None + | Have (args,extras) -> begin + match ArgSplits.bindings args, ExtraSplits.bindings extras with + | [(id',loc),Total], [] when Id.compare id id' == 0 -> + (match Util.map_all (function + | Pat_aux (Pat_exp (pat,_),_) -> Some (ctx pat) + | Pat_aux (Pat_when (_,_,_),_) -> None) pexps + with + | Some pats -> + if l = Parse_ast.Unknown then + (Reporting_basic.print_error + (Reporting_basic.Err_general + (l, "No location for pattern match: " ^ string_of_exp exp)); + None) + else + Some (Have (ArgSplits.singleton (id,loc) (Partial (pats,l)), + ExtraSplits.empty)) + | None -> None) + | _ -> None + end + | Unknown _ -> None + | exception Not_found -> None in match e with | E_id id -> check_dep id (fun x -> x) @@ -2466,15 +2627,14 @@ let rec analyse_exp fn_id env assigns (E_aux (e,(l,annot)) as exp) = let kid_inst = instantiation_of exp in (* Change kids in instantiation to the canonical ones from the type signature *) let kid_inst = KBindings.fold (fun kid -> KBindings.add (orig_kid kid)) kid_inst KBindings.empty in - let kid_deps = KBindings.map (deps_of_uvar env.kid_deps deps) kid_inst in + let kid_deps = KBindings.map (deps_of_uvar fn_id env deps) kid_inst in let rdep,r' = if Id.compare fn_id id == 0 then let bad = Unknown (l,"Recursive call of " ^ string_of_id id) in - let deps = List.map (fun _ -> bad) deps in - let kid_deps = KBindings.map (fun _ -> bad) kid_deps in - bad, { empty with split_on_call = Bindings.singleton id (deps, kid_deps) } + let kid_deps = KBindings.map (fun _ -> InFun bad) kid_deps in + bad, { empty with split_on_call = Bindings.singleton id kid_deps } else - dempty, { empty with split_on_call = Bindings.singleton id (deps, kid_deps) } in + dempty, { empty with split_on_call = Bindings.singleton id kid_deps } in (merge_deps (rdep::eff_dep::deps), assigns, merge r r') | E_tuple es | E_list es -> @@ -2619,19 +2779,26 @@ let rec analyse_exp fn_id env assigns (E_aux (e,(l,annot)) as exp) = let typ = Env.expand_synonyms tenv typ in if is_bitvector_typ typ then let _,size,_,_ = vector_typ_args_of typ in - let size = simplify_size_nexp env tenv size in - match deps_of_nexp env.kid_deps [] size with - | Have (args,caller,caller_kids) -> - { r with - split = ArgSplits.merge merge_detail r.split args; - split_in_caller = CallerArgSet.union r.split_in_caller caller; - kid_in_caller = CallerKidSet.union r.kid_in_caller caller_kids - } - | Unknown (l,msg) -> - { r with - failures = - Failures.add l (StringSet.singleton ("Unable to monomorphise " ^ string_of_nexp size ^ ": " ^ msg)) - r.failures } + let Nexp_aux (size,_) as size_nexp = simplify_size_nexp env tenv size in + let is_tyvar_parameter v = + List.exists (fun k -> Kid.compare k v == 0) env.top_kids + in + match size with + | Nexp_constant _ -> r + | Nexp_var v when is_tyvar_parameter v -> + { r with kid_in_caller = CallerKidSet.add (fn_id,v) r.kid_in_caller } + | _ -> + match deps_of_nexp env.kid_deps [] size_nexp with + | Have (args,extras) -> + { r with + split = ArgSplits.merge merge_detail r.split args; + extra_splits = merge_extras r.extra_splits extras + } + | Unknown (l,msg) -> + { r with + failures = + Failures.add l (StringSet.singleton ("Unable to monomorphise " ^ string_of_nexp size_nexp ^ ": " ^ msg)) + r.failures } else r in (deps, assigns, r) @@ -2662,33 +2829,36 @@ and analyse_lexp fn_id env assigns deps (LEXP_aux (lexp,_)) = | LEXP_field (lexp,_) -> analyse_lexp fn_id env assigns deps lexp -let translate_id (Id_aux (_,l) as id) = - let rec aux l = - match l with - | Range (pos,_) -> Some (id,(pos.Lexing.pos_fname,pos.Lexing.pos_lnum)) - | Generated l -> aux l - | _ -> None - in aux l +let rec translate_loc l = + match l with + | Range (pos,_) -> Some (pos.Lexing.pos_fname,pos.Lexing.pos_lnum) + | Generated l -> translate_loc l + | _ -> None -let initial_env fn_id (TypQ_aux (tq,_)) pat set_assertions = +let initial_env fn_id fn_l (TypQ_aux (tq,_)) pat set_assertions = let pats = match pat with | P_aux (P_tup pats,_) -> pats | _ -> [pat] in - let default_split annot = + (* For the type in an annotation, produce the corresponding tyvar (if any), + and a default case split (a set if there's one, a full case split if not). *) + let kid_of_annot annot = let env = env_of_annot annot in let Typ_aux (typ,_) = Env.base_typ_of env (typ_of_annot annot) in match typ with | Typ_app (Id_aux (Id "atom",_),[Typ_arg_aux (Typ_arg_nexp (Nexp_aux (Nexp_var kid,_)),_)]) -> - (match KBindings.find kid set_assertions with - | (l,is) -> - let l' = Generated l in - let pats = List.map (fun n -> P_aux (P_lit (L_aux (L_num n,l')),(l',snd annot))) is in - let pats = pats @ [P_aux (P_wild,(l',snd annot))] in - Partial (pats,l) - | exception Not_found -> Total) - | _ -> Total + Some kid + | _ -> None + in + let default_split annot kid = + match KBindings.find kid set_assertions with + | (l,is) -> + let l' = Generated l in + let pats = List.map (fun n -> P_aux (P_lit (L_aux (L_num n,l')),(l',annot))) is in + let pats = pats @ [P_aux (P_wild,(l',annot))] in + Partial (pats,l) + | exception Not_found -> Total in let arg i pat = let rec aux (P_aux (p,(l,annot))) = @@ -2706,10 +2876,10 @@ let initial_env fn_id (TypQ_aux (tq,_)) pat set_assertions = | P_as (pat,id) -> begin let s,v,k = aux pat in - match translate_id id with - | Some id' -> - ArgSplits.add id' Total s, - Bindings.add id (Have (ArgSplits.singleton id' Total,CallerArgSet.empty,CallerKidSet.empty)) v, + match translate_loc (id_loc id) with + | Some loc -> + ArgSplits.add (id,loc) Total s, + Bindings.add id (Have (ArgSplits.singleton (id,loc) Total, ExtraSplits.empty)) v, k | None -> s, @@ -2719,12 +2889,16 @@ let initial_env fn_id (TypQ_aux (tq,_)) pat set_assertions = | P_typ (_,pat) -> aux pat | P_id id -> begin - match translate_id id with - | Some id' -> - let s = ArgSplits.singleton id' (default_split (l,annot)) in + match translate_loc (id_loc id) with + | Some loc -> + let kid_opt = kid_of_annot (l,annot) in + let split = Util.option_cases kid_opt (default_split annot) (fun () -> Total) in + let s = ArgSplits.singleton (id,loc) split in s, - Bindings.singleton id (Have (s,CallerArgSet.empty,CallerKidSet.empty)), - KBindings.empty + Bindings.singleton id (Have (s, ExtraSplits.empty)), + (match kid_opt with + | None -> KBindings.empty + | Some kid -> KBindings.singleton kid (Have (s, ExtraSplits.empty))) | None -> ArgSplits.empty, Bindings.singleton id (Unknown (l, ("Unable to give location for " ^ string_of_id id))), @@ -2732,7 +2906,7 @@ let initial_env fn_id (TypQ_aux (tq,_)) pat set_assertions = end | P_var (pat, TP_var kid) -> let s,v,k = aux pat in - s,v,KBindings.add kid (Have (ArgSplits.empty,CallerArgSet.singleton (fn_id,i),CallerKidSet.empty)) k + s,v,KBindings.add kid (Have (s, ExtraSplits.empty)) k | P_app (_,pats) -> of_list pats | P_record (fpats,_) -> of_list (List.map (fun (FP_aux (FP_Fpat (_,p),_)) -> p) fpats) | P_vector pats @@ -2743,20 +2917,31 @@ let initial_env fn_id (TypQ_aux (tq,_)) pat set_assertions = | P_cons (p1,p2) -> of_list [p1;p2] in aux pat in - let quant k = function + let quant = function | QI_aux (QI_id (KOpt_aux ((KOpt_none kid | KOpt_kind (_,kid)),_)),_) -> - KBindings.add kid (Have (ArgSplits.empty,CallerArgSet.empty,CallerKidSet.singleton (fn_id,kid))) k - | QI_aux (QI_const _,_) -> k + Some kid + | QI_aux (QI_const _,_) -> None in - let kid_quant_deps = + let top_kids = match tq with - | TypQ_no_forall -> KBindings.empty - | TypQ_tq qs -> List.fold_left quant KBindings.empty qs + | TypQ_no_forall -> [] + | TypQ_tq qs -> Util.map_filter quant qs in let _,var_deps,kid_deps = split3 (List.mapi arg pats) in let var_deps = List.fold_left dep_bindings_merge Bindings.empty var_deps in - let kid_deps = List.fold_left dep_kbindings_merge kid_quant_deps kid_deps in - let top_kids = List.map fst (KBindings.bindings kid_quant_deps) in + let kid_deps = List.fold_left dep_kbindings_merge KBindings.empty kid_deps in + let note_no_arg kid_deps kid = + if KBindings.mem kid kid_deps then kid_deps + else + (* When there's no argument to case split on for a kid, we'll add a + case expression instead *) + let env = pat_env_of pat in + let split = default_split (Some (env,int_typ,no_effect)) kid in + let extra_splits = ExtraSplits.singleton (fn_id, fn_l) + (KBindings.singleton kid split) in + KBindings.add kid (Have (ArgSplits.empty, extra_splits)) kid_deps + in + let kid_deps = List.fold_left note_no_arg kid_deps top_kids in { top_kids = top_kids; var_deps = var_deps; kid_deps = kid_deps } (* When there's more than one pick the first *) @@ -2767,8 +2952,48 @@ let merge_set_asserts _ x y = let merge_set_asserts_by_kid sets1 sets2 = KBindings.merge merge_set_asserts sets1 sets2 +(* Set constraints in assertions don't always use the set syntax, so we also + handle assert('N == 1 | ...) style set constraints *) +let rec sets_from_assert e = + let set_from_or_exps (E_aux (_,(l,_)) as e) = + let mykid = ref None in + let check_kid kid = + match !mykid with + | None -> mykid := Some kid + | Some kid' -> if Kid.compare kid kid' == 0 then () + else raise Not_found + in + let rec aux (E_aux (e,_)) = + match e with + | E_app (Id_aux (Id "or_bool",_),[e1;e2]) -> + aux e1 @ aux e2 + | E_app (Id_aux (Id "eq_atom",_), + [E_aux (E_sizeof (Nexp_aux (Nexp_var kid,_)),_); + E_aux (E_lit (L_aux (L_num i,_)),_)]) -> + (check_kid kid; [i]) + | _ -> raise Not_found + in try + let is = aux e in + match !mykid with + | None -> KBindings.empty + | Some kid -> KBindings.singleton kid (l,is) + with Not_found -> KBindings.empty + in + let rec sets_from_nc (NC_aux (nc,l)) = + match nc with + | NC_and (nc1,nc2) -> merge_set_asserts_by_kid (sets_from_nc nc1) (sets_from_nc nc2) + | NC_set (kid,is) -> KBindings.singleton kid (l,is) + | _ -> KBindings.empty + in + match e with + | E_aux (E_app (Id_aux (Id "and_bool",_),[e1;e2]),_) -> + merge_set_asserts_by_kid (sets_from_assert e1) (sets_from_assert e2) + | E_aux (E_constraint nc,_) -> sets_from_nc nc + | _ -> set_from_or_exps e + (* Find all the easily reached set assertions in a function body, to use as - case splits *) + case splits. Note that this should be mirrored in stop_at_false_assertions, + above. *) let rec find_set_assertions (E_aux (e,_)) = match e with | E_block es @@ -2781,11 +3006,7 @@ let rec find_set_assertions (E_aux (e,_)) = let kbound = kids_bound_by_pat p in let sets2 = KBindings.filter (fun kid _ -> not (KidSet.mem kid kbound)) sets2 in merge_set_asserts_by_kid sets1 sets2 - | E_assert (E_aux (e1,_),_) -> begin - match e1 with - | E_constraint (NC_aux (NC_set (kid,is),l)) -> KBindings.singleton kid (l,is) - | _ -> KBindings.empty - end + | E_assert (exp1,_) -> sets_from_assert exp1 | _ -> KBindings.empty let print_set_assertions set_assertions = @@ -2802,18 +3023,20 @@ let print_set_assertions set_assertions = let print_result r = let _ = print_endline (" splits: " ^ string_of_argsplits r.split) in let print_kbinding kid dep = - let _ = print_endline (" " ^ string_of_kid kid ^ ": " ^ string_of_dep dep) in + let s = match dep with + | InFun dep -> "InFun " ^ string_of_dep dep + | Parents cks -> string_of_callerkidset cks + in + let _ = print_endline (" " ^ string_of_kid kid ^ ": " ^ s) in () in - let print_binding id (deps,kdep) = + let print_binding id kdep = let _ = print_endline (" " ^ string_of_id id ^ ":") in - let _ = List.iter (fun dep -> print_endline (" " ^ string_of_dep dep)) deps in let _ = KBindings.iter print_kbinding kdep in () in let _ = print_endline " split_on_call: " in let _ = Bindings.iter print_binding r.split_on_call in - let _ = print_endline (" split_in_caller: " ^ string_of_callerset r.split_in_caller) in let _ = print_endline (" kid_in_caller: " ^ string_of_callerkidset r.kid_in_caller) in let _ = print_endline (" failures: \n " ^ (String.concat "\n " @@ -2822,17 +3045,24 @@ let print_result r = (Failures.bindings r.failures)))) in () -let analyse_funcl debug tenv (FCL_aux (FCL_Funcl (id,pexp),_)) = +let analyse_funcl debug tenv (FCL_aux (FCL_Funcl (id,pexp),(l,_))) = let _ = if debug > 2 then print_endline (string_of_id id) else () in let pat,guard,body,_ = destruct_pexp pexp in let (tq,_) = Env.get_val_spec id tenv in let set_assertions = find_set_assertions body in let _ = if debug > 2 then print_set_assertions set_assertions in - let aenv = initial_env id tq pat set_assertions in + let aenv = initial_env id l tq pat set_assertions in let _,_,r = analyse_exp id aenv Bindings.empty body in let r = match guard with | None -> r | Some exp -> let _,_,r' = analyse_exp id aenv Bindings.empty exp in + let r' = + if ExtraSplits.is_empty r'.extra_splits + then r' + else merge r' { empty with failures = + Failures.singleton l (StringSet.singleton + "Case splitting size tyvars in guards not supported") } + in merge r r' in let _ = if debug > 2 then print_result r else () @@ -2844,65 +3074,110 @@ let analyse_def debug env = function | _ -> empty +let detail_to_split = function + | Total -> None + | Partial (pats,l) -> Some (pats,l) + +let argset_to_list splits = + let l = ArgSplits.bindings splits in + let argelt = function + | ((id,(file,loc)),detail) -> ((file,loc),string_of_id id,detail_to_split detail) + in + List.map argelt l + let analyse_defs debug env (Defs defs) = let r = List.fold_left (fun r d -> merge r (analyse_def debug env d)) empty defs in (* Resolve the interprocedural dependencies *) - let rec chase_deps = function - | Have (splits, caller_args, caller_kids) -> - let splits,fails = CallerArgSet.fold add_arg caller_args (splits,Failures.empty) in - let splits,fails = CallerKidSet.fold add_kid caller_kids (splits,fails) in - splits, fails + let rec separate_deps = function + | Have (splits, extras) -> + splits, extras, Failures.empty | Unknown (l,msg) -> - ArgSplits.empty , Failures.singleton l (StringSet.singleton ("Unable to monomorphise dependency: " ^ msg)) + ArgSplits.empty, ExtraSplits.empty, + Failures.singleton l (StringSet.singleton ("Unable to monomorphise dependency: " ^ msg)) and chase_kid_caller (id,kid) = match Bindings.find id r.split_on_call with - | (_,kid_deps) -> begin + | kid_deps -> begin match KBindings.find kid kid_deps with - | deps -> chase_deps deps - | exception Not_found -> ArgSplits.empty,Failures.empty + | InFun deps -> separate_deps deps + | Parents fns -> CallerKidSet.fold add_kid fns (ArgSplits.empty, ExtraSplits.empty, Failures.empty) + | exception Not_found -> ArgSplits.empty,ExtraSplits.empty,Failures.empty end - | exception Not_found -> ArgSplits.empty,Failures.empty - and chase_arg_caller (id,i) = - match Bindings.find id r.split_on_call with - | (arg_deps,_) -> chase_deps (List.nth arg_deps i) - | exception Not_found -> ArgSplits.empty,Failures.empty - and add_arg arg (splits,fails) = - let splits',fails' = chase_arg_caller arg in - ArgSplits.merge merge_detail splits splits', Failures.merge failure_merge fails fails' - and add_kid k (splits,fails) = - let splits',fails' = chase_kid_caller k in - ArgSplits.merge merge_detail splits splits', Failures.merge failure_merge fails fails' + | exception Not_found -> ArgSplits.empty,ExtraSplits.empty,Failures.empty + and add_kid k (splits,extras,fails) = + let splits',extras',fails' = chase_kid_caller k in + ArgSplits.merge merge_detail splits splits', + merge_extras extras extras', + Failures.merge failure_merge fails fails' in let _ = if debug > 1 then print_result r else () in - let splits,fails = CallerArgSet.fold add_arg r.split_in_caller (r.split,r.failures) in - let splits,fails = CallerKidSet.fold add_kid r.kid_in_caller (splits,fails) in + let splits,extras,fails = CallerKidSet.fold add_kid r.kid_in_caller (r.split,r.extra_splits,r.failures) in let _ = if debug > 0 then (print_endline "Final splits:"; - print_endline (string_of_argsplits splits)) + print_endline (string_of_argsplits splits); + print_endline (string_of_extra_splits extras)) else () in - let _ = - if Failures.is_empty fails then () else - begin - Failures.iter (fun l msgs -> - Reporting_basic.print_err false false l "Monomorphisation" (String.concat "\n" (StringSet.elements msgs))) - fails; - raise (Reporting_basic.err_general Unknown "Unable to monomorphise program") - end - in splits + let splits = argset_to_list splits in + if Failures.is_empty fails + then (true,splits,extras) else + begin + Failures.iter (fun l msgs -> + Reporting_basic.print_err false false l "Monomorphisation" (String.concat "\n" (StringSet.elements msgs))) + fails; + (false, splits,extras) + end -let argset_to_list splits = - let l = ArgSplits.bindings splits in - let argelt = function - | ((id,(file,loc)),Total) -> ((file,loc),string_of_id id,None) - | ((id,(file,loc)),Partial (pats,l)) -> ((file,loc),string_of_id id,Some (pats,l)) - in - List.map argelt l end +let fresh_sz_var = + let counter = ref 0 in + fun () -> + let n = !counter in + let () = counter := n+1 in + mk_id ("sz#" ^ string_of_int n) + +let add_extra_splits extras (Defs defs) = + let success = ref true in + let add_to_body extras (E_aux (_,(l,annot)) as e) = + let l' = Generated l in + KBindings.fold (fun kid detail (exp,split_list) -> + let nexp = Nexp_aux (Nexp_var kid,l) in + let var = fresh_sz_var () in + let size_annot = Some (env_of e,atom_typ nexp,no_effect) in + let loc = match Analysis.translate_loc l with + | Some l -> l + | None -> + (Reporting_basic.print_err false false l "Monomorphisation" + "Internal error: bad location for added case"; + ("",0)) + in + let pexps = [Pat_aux (Pat_exp (P_aux (P_id var,(l,size_annot)),exp),(l',annot))] in + E_aux (E_case (E_aux (E_sizeof nexp, (l',size_annot)), pexps),(l',annot)), + ((loc, string_of_id var, Analysis.detail_to_split detail)::split_list) + ) extras (e,[]) + in + let add_to_funcl (FCL_aux (FCL_Funcl (id,Pat_aux (pexp,peannot)),(l,annot))) = + let pexp, splits = + match Analysis.ExtraSplits.find (id,l) extras with + | extras -> + (match pexp with + | Pat_exp (p,e) -> let e',sp = add_to_body extras e in Pat_exp (p,e'), sp + | Pat_when (p,g,e) -> let e',sp = add_to_body extras e in Pat_when (p,g,e'), sp) + | exception Not_found -> pexp, [] + in FCL_aux (FCL_Funcl (id,Pat_aux (pexp,peannot)),(l,annot)), splits + in + let add_to_def = function + | DEF_fundef (FD_aux (FD_function (re,ta,ef,funcls),annot)) -> + let funcls,splits = List.split (List.map add_to_funcl funcls) in + DEF_fundef (FD_aux (FD_function (re,ta,ef,funcls),annot)), List.concat splits + | d -> d, [] + in + let defs, splits = List.split (List.map add_to_def defs) in + !success, Defs defs, List.concat splits + module MonoRewrites = struct @@ -3125,6 +3400,7 @@ type options = { rewrites : bool; rewrite_size_parameters : bool; all_split_errors : bool; + continue_anyway : bool; dump_raw: bool } @@ -3144,13 +3420,26 @@ let monomorphise opts splits env defs = else (defs,env) in (*let _ = Pretty_print.pp_defs stdout defs in*) - let new_splits = + let ok_analysis, new_splits, extra_splits = if opts.auto - then Analysis.argset_to_list (Analysis.analyse_defs opts.debug_analysis env defs) - else [] in + then + let f,r,ex = Analysis.analyse_defs opts.debug_analysis env defs in + if f || opts.all_split_errors || opts.continue_anyway + then f, r, ex + else raise (Reporting_basic.err_general Unknown "Unable to monomorphise program") + else true, [], Analysis.ExtraSplits.empty in let splits = new_splits @ (List.map (fun (loc,id) -> (loc,id,None)) splits) in - let defs = split_defs opts.all_split_errors splits defs in - (* TODO: stop if opts.all_split_errors && something went wrong *) + let ok_extras, defs, extra_splits = add_extra_splits extra_splits defs in + let splits = splits @ extra_splits in + let () = if ok_extras || opts.all_split_errors || opts.continue_anyway + then () + else raise (Reporting_basic.err_general Unknown "Unable to monomorphise program") + in + let ok_split, defs = split_defs opts.all_split_errors splits defs in + let () = if (ok_analysis && ok_extras && ok_split) || opts.continue_anyway + then () + else raise (Reporting_basic.err_general Unknown "Unable to monomorphise program") + in (* TODO: currently doing this because constant propagation leaves numeric literals as int, try to avoid this later; also use final env for DEF_spec case above, because the type checker doesn't store the env at that point :( *) diff --git a/src/monomorphise.mli b/src/monomorphise.mli index 11713511..3e561e32 100644 --- a/src/monomorphise.mli +++ b/src/monomorphise.mli @@ -54,6 +54,7 @@ type options = { rewrites : bool; (* Experimental rewrites for variable-sized operations *) rewrite_size_parameters : bool; (* Make implicit type parameters explicit for (e.g.) lem *) all_split_errors : bool; + continue_anyway : bool; dump_raw: bool } diff --git a/src/pretty_print_lem.ml b/src/pretty_print_lem.ml index 40d373b2..350b5388 100644 --- a/src/pretty_print_lem.ml +++ b/src/pretty_print_lem.ml @@ -1210,7 +1210,8 @@ let doc_mutrec_lem = function let rec doc_fundef_lem (FD_aux(FD_function(r, typa, efa, fcls),fannot) as fd) = match fcls with | [] -> failwith "FD_function with empty function list" - | FCL_aux (FCL_Funcl(id,_),_) :: _ + (* TODO: Move splitting of execute function to the rewriter *) + (*| FCL_aux (FCL_Funcl(id,_),_) :: _ when string_of_id id = "execute" (*|| string_of_id id = "initial_analysis"*) -> let (_,auxiliary_functions,clauses) = List.fold_left @@ -1273,7 +1274,7 @@ let rec doc_fundef_lem (FD_aux(FD_function(r, typa, efa, fcls),fannot) as fd) = auxiliary_functions ^^ hardline ^^ hardline ^^ (prefix 2 1) ((separate space) [string "let" ^^ doc_rec_lem false r ^^ doc_id_lem id;equals;string "function"]) - (clauses ^/^ string "end") + (clauses ^/^ string "end")*) | FCL_aux (FCL_Funcl(id,_),annot) :: _ when not (Env.is_extern id (env_of_annot annot) "lem") -> string "let" ^^ (doc_rec_lem (List.length fcls > 1) r) ^^ (doc_fundef_rhs_lem fd) @@ -1495,15 +1496,15 @@ let pp_defs_lem (types_file,types_modules) (defs_file,defs_modules) d top_line = if !opt_sequential then concat [regstate_def; hardline; hardline; - string ("type MR 'a 'r = State.MR regstate 'a 'r " ^ exc_typ); hardline; - string ("type M 'a = State.M regstate 'a " ^ exc_typ); hardline; + string ("type MR 'a 'r = State_monad.MR regstate 'a 'r " ^ exc_typ); hardline; + string ("type M 'a = State_monad.M regstate 'a " ^ exc_typ); hardline; hardline; register_refs ] else concat [ - string ("type MR 'a 'r = Prompt.MR 'a 'r " ^ exc_typ); hardline; - string ("type M 'a = Prompt.M 'a " ^ exc_typ); hardline + string ("type MR 'a 'r = Prompt_monad.MR 'a 'r " ^ exc_typ); hardline; + string ("type M 'a = Prompt_monad.M 'a " ^ exc_typ); hardline ] ]); (print defs_file) diff --git a/src/process_file.ml b/src/process_file.ml index 1ba8069f..1da893c3 100644 --- a/src/process_file.ml +++ b/src/process_file.ml @@ -93,7 +93,7 @@ let cond_pragma defs = else else_defs := (def :: !else_defs) in - + let rec scan = function | Parse_ast.DEF_pragma ("endif", _, _) :: defs when !depth = 0 -> (List.rev !then_defs, List.rev !else_defs, defs) @@ -108,13 +108,13 @@ let cond_pragma defs = | [] -> failwith "$ifdef or $ifndef never ended" in scan defs - + let rec preprocess = function | [] -> [] | Parse_ast.DEF_pragma ("define", symbol, _) :: defs -> symbols := StringSet.add symbol !symbols; preprocess defs - + | Parse_ast.DEF_pragma ("ifndef", symbol, _) :: defs -> let then_defs, else_defs, defs = cond_pragma defs in if not (StringSet.mem symbol !symbols) then @@ -128,7 +128,7 @@ let rec preprocess = function preprocess (then_defs @ defs) else preprocess (else_defs @ defs) - + | Parse_ast.DEF_pragma ("include", file, l) :: defs -> let len = String.length file in if len = 0 then @@ -151,18 +151,18 @@ let rec preprocess = function let file = Filename.concat sail_dir ("lib/" ^ file) in let (Parse_ast.Defs include_defs) = parse_file file in let include_defs = preprocess include_defs in - include_defs @ preprocess defs + include_defs @ preprocess defs else let help = "Make sure the filename is surrounded by quotes or angle brackets" in (Util.warn ("Skipping bad $include " ^ file ^ ". " ^ help); preprocess defs) | Parse_ast.DEF_pragma (p, arg, _) :: defs -> - (Util.warn ("Bad pragma $" ^ p ^ " " ^ arg); preprocess defs) - + (Util.warn ("Bad pragma $" ^ p ^ " " ^ arg); preprocess defs) + | def :: defs -> def :: preprocess defs let preprocess_ast (Parse_ast.Defs defs) = Parse_ast.Defs (preprocess defs) - + let convert_ast (order : Ast.order) (defs : Parse_ast.defs) : unit Ast.defs = Initial_check.process_ast order defs let load_file_no_check order f = convert_ast order (preprocess_ast (parse_file f)) @@ -188,6 +188,7 @@ let opt_dmono_analysis = ref 0 let opt_auto_mono = ref false let opt_mono_rewrites = ref false let opt_dall_split_errors = ref false +let opt_dmono_continue = ref false let monomorphise_ast locs type_env ast = let open Monomorphise in @@ -197,6 +198,7 @@ let monomorphise_ast locs type_env ast = rewrites = !opt_mono_rewrites; rewrite_size_parameters = !Pretty_print_lem.opt_mwords; all_split_errors = !opt_dall_split_errors; + continue_anyway = !opt_dmono_continue; dump_raw = !opt_ddump_raw_mono_ast } in monomorphise opts locs type_env ast @@ -226,16 +228,22 @@ let output_lem filename libs defs = let generated_line = generated_line filename in let seq_suffix = if !Pretty_print_lem.opt_sequential then "_sequential" else "" in let types_module = (filename ^ "_embed_types" ^ seq_suffix) in - let monad_module = if !Pretty_print_lem.opt_sequential then "State" else "Prompt" in - let operators_module = "Sail_operators" (* if !Pretty_print_lem.opt_mwords then "Sail_operators_mwords" else "Sail_operators" *) in + let monad_modules = + if !Pretty_print_lem.opt_sequential + then ["State_monad"; "State"] + else ["Prompt_monad"; "Prompt"] in + let operators_module = + if !Pretty_print_lem.opt_mwords + then "Sail_operators_mwords" + else "Sail_operators_bitlists" in let libs = List.map (fun lib -> lib ^ seq_suffix) libs in let base_imports = [ "Pervasives_extra"; "Sail_impl_base"; "Sail_values"; - operators_module; - monad_module - ] in + operators_module + ] @ monad_modules + in let ((ot,_, _) as ext_ot) = open_output_with_check_unformatted (filename ^ "_embed_types" ^ seq_suffix ^ ".lem") in let ((o,_, _) as ext_o) = diff --git a/src/process_file.mli b/src/process_file.mli index d8094682..54415621 100644 --- a/src/process_file.mli +++ b/src/process_file.mli @@ -72,6 +72,7 @@ val opt_ddump_rewrite_ast : ((string * int) option) ref val opt_dno_cast : bool ref val opt_ddump_raw_mono_ast : bool ref val opt_dmono_analysis : int ref +val opt_dmono_continue : bool ref val opt_auto_mono : bool ref val opt_mono_rewrites : bool ref val opt_dall_split_errors : bool ref diff --git a/src/rewrites.ml b/src/rewrites.ml index e38169cc..6146e73b 100644 --- a/src/rewrites.ml +++ b/src/rewrites.ml @@ -1203,43 +1203,50 @@ let remove_bitvector_pat (P_aux (_, (l, _)) as pat) = let guard_bitvector_pat = let collect_guards_decls ps rootid t = let (start,_,ord,_) = vector_typ_args_of t in - let rec collect current (guards,dls) idx ps = - let idx' = if is_order_inc ord then Big_int.add idx (Big_int.of_int 1) else Big_int.sub idx (Big_int.of_int 1) in - (match ps with - | pat :: ps' -> - (match pat with - | P_aux (P_lit lit, (l,annot)) -> - let e = E_aux (E_lit lit, (gen_loc l, annot)) in - let current' = (match current with - | Some (l,i,j,lits) -> Some (l,i,idx,lits @ [e]) - | None -> Some (l,idx,idx,[e])) in - collect current' (guards, dls) idx' ps' - | P_aux (P_as (pat',id), (l,annot)) -> - let dl = letbind_bit_exp rootid l t idx id in - collect current (guards, dls @ [dl]) idx (pat' :: ps') - | _ -> - let dls' = (match pat with - | P_aux (P_id id, (l,annot)) -> - dls @ [letbind_bit_exp rootid l t idx id] - | _ -> dls) in - let guards' = (match current with - | Some (l,i,j,lits) -> - guards @ [Some (test_subvec_exp rootid l t i j lits)] - | None -> guards) in - collect None (guards', dls') idx' ps') - | [] -> - let guards' = (match current with - | Some (l,i,j,lits) -> - guards @ [Some (test_subvec_exp rootid l t i j lits)] - | None -> guards) in - (guards',dls)) in - let (guards,dls) = match start with - | Nexp_aux (Nexp_constant s, _) -> - collect None ([],[]) s ps + let start_idx = match start with + | Nexp_aux (Nexp_constant s, _) -> s | _ -> - let (P_aux (_, (l,_))) = pat in raise (Reporting_basic.err_unreachable l "guard_bitvector_pat called on pattern with non-constant start index") in + let add_bit_pat (idx, current, guards, dls) pat = + let idx' = + if is_order_inc ord + then Big_int.add idx (Big_int.of_int 1) + else Big_int.sub idx (Big_int.of_int 1) in + let ids = fst (fold_pat + { (compute_pat_alg IdSet.empty IdSet.union) with + p_id = (fun id -> IdSet.singleton id, P_id id); + p_as = (fun ((ids, pat), id) -> IdSet.add id ids, P_as (pat, id)) } + pat) in + let lits = fst (fold_pat + { (compute_pat_alg [] (@)) with + p_aux = (fun ((lits, paux), (l, annot)) -> + let lits = match paux with + | P_lit lit -> E_aux (E_lit lit, (l, annot)) :: lits + | _ -> lits in + lits, P_aux (paux, (l, annot))) } + pat) in + let add_letbind id dls = dls @ [letbind_bit_exp rootid l t idx id] in + let dls' = IdSet.fold add_letbind ids dls in + let current', guards' = + match current with + | Some (l, i, j, lits') -> + if lits = [] + then None, guards @ [Some (test_subvec_exp rootid l t i j lits')] + else Some (l, i, idx, lits' @ lits), guards + | None -> + begin + match lits with + | E_aux (_, (l, _)) :: _ -> Some (l, idx, idx, lits), guards + | [] -> None, guards + end + in + (idx', current', guards', dls') in + let (_, final, guards, dls) = List.fold_left add_bit_pat (start_idx, None, [], []) ps in + let guards = match final with + | Some (l,i,j,lits) -> + guards @ [Some (test_subvec_exp rootid l t i j lits)] + | None -> guards in let (decls,letbinds) = List.split dls in (compose_guards guards, List.fold_right (@@) decls, letbinds) in @@ -2951,10 +2958,10 @@ let rewrite_defs_lem = [ ("remove_bitvector_pats", rewrite_defs_remove_bitvector_pats); ("remove_numeral_pats", rewrite_defs_remove_numeral_pats); ("guarded_pats", rewrite_defs_guarded_pats); - ("exp_lift_assign", rewrite_defs_exp_lift_assign); (* ("register_ref_writes", rewrite_register_ref_writes); *) ("fix_val_specs", rewrite_fix_val_specs); ("recheck_defs", recheck_defs); + ("exp_lift_assign", rewrite_defs_exp_lift_assign); (* ("constraint", rewrite_constraint); *) (* ("remove_assert", rewrite_defs_remove_assert); *) ("top_sort_defs", top_sort_defs); @@ -3021,15 +3028,25 @@ let rewrite_check_annot = try prerr_endline ("CHECKING: " ^ string_of_exp exp ^ " : " ^ string_of_typ (typ_of exp)); let _ = check_exp (env_of exp) (strip_exp exp) (typ_of exp) in - (if not (alpha_equivalent (env_of exp) (typ_of exp) (Env.expand_synonyms (env_of exp) (typ_of exp))) - then raise (Reporting_basic.err_typ Parse_ast.Unknown "Found synonym in annotation") + let typ1 = typ_of exp in + let typ2 = Env.expand_synonyms (env_of exp) (typ_of exp) in + (if not (alpha_equivalent (env_of exp) typ1 typ2) + then raise (Reporting_basic.err_typ Parse_ast.Unknown + ("Found synonym in annotation " ^ string_of_typ typ1 ^ " vs " ^ string_of_typ typ2)) else ()); exp with Type_error (l, err) -> raise (Reporting_basic.err_typ l (string_of_type_error err)) in + let check_pat pat = + prerr_endline ("CHECKING PAT: " ^ string_of_pat pat ^ " : " ^ string_of_typ (pat_typ_of pat)); + let _, _ = bind_pat_no_guard (pat_env_of pat) (strip_pat pat) (pat_typ_of pat) in + pat + in + let rewrite_exp = { id_exp_alg with e_aux = (fun (exp, annot) -> check_annot (E_aux (exp, annot))) } in - rewrite_defs_base { rewriters_base with rewrite_exp = (fun _ -> fold_exp rewrite_exp) } + rewrite_defs_base { rewriters_base with rewrite_exp = (fun _ -> fold_exp rewrite_exp); + rewrite_pat = (fun _ -> check_pat) } let rewrite_defs_check = [ ("check_annotations", rewrite_check_annot); diff --git a/src/sail.ml b/src/sail.ml index bbe26a0d..dac2f841 100644 --- a/src/sail.ml +++ b/src/sail.ml @@ -152,6 +152,9 @@ let options = Arg.align ([ ( "-dall_split_errors", Arg.Set Process_file.opt_dall_split_errors, " display all case split errors from monomorphisation, rather than one"); + ( "-dmono_continue", + Arg.Set Process_file.opt_dmono_continue, + " continue despite monomorphisation errors"); ( "-verbose", Arg.Set opt_print_verbose, " (debug) pretty-print the input to standard output"); @@ -256,7 +259,8 @@ let main() = (if !(opt_print_c) then let ast_c = rewrite_ast_c ast in - C_backend.compile_ast type_envs ast_c + let ast_c, type_envs = Specialize.specialize ast_c type_envs in + C_backend.compile_ast (C_backend.initial_ctx type_envs) ast_c else ()); (if !(opt_print_lem) then let ast_lem = rewrite_ast_lem ast in diff --git a/src/sail_lib.ml b/src/sail_lib.ml index 7a8dc88c..4d6e32bc 100644 --- a/src/sail_lib.ml +++ b/src/sail_lib.ml @@ -176,6 +176,31 @@ let add_int (x, y) = Big_int.add x y let sub_int (x, y) = Big_int.sub x y let mult (x, y) = Big_int.mul x y let quotient (x, y) = Big_int.div x y + +(* Big_int does not provide divide with rounding towards zero so roll + our own, assuming that division of positive integers rounds down *) +let quot_round_zero (x, y) = + let posX = Big_int.greater_equal x Big_int.zero in + let posY = Big_int.greater_equal y Big_int.zero in + let absX = Big_int.abs x in + let absY = Big_int.abs y in + let q = Big_int.div absX absY in + if posX != posY then + Big_int.negate q + else + q + +(* The corresponding remainder function for above just respects the sign of x *) +let rem_round_zero (x, y) = + let posX = Big_int.greater_equal x Big_int.zero in + let absX = Big_int.abs x in + let absY = Big_int.abs y in + let r = Big_int.modulus absX absY in + if posX then + r + else + Big_int.negate r + let modulus (x, y) = Big_int.modulus x y let negate x = Big_int.negate x @@ -425,6 +450,7 @@ let round_up x = failwith "round_up" (* Num.big_int_of_num (Num.ceiling_num x) * let quotient_real (x, y) = Rational.div x y let mult_real (x, y) = Rational.mul x y (* Num.mult_num x y *) let real_power (x, y) = failwith "real_power" (* Num.power_num x (Num.num_of_big_int y) *) +let int_power (x, y) = Big_int.pow_int x (Big_int.to_int y) let add_real (x, y) = Rational.add x y let sub_real (x, y) = Rational.sub x y diff --git a/src/trace_viewer/.gitignore b/src/trace_viewer/.gitignore deleted file mode 100644 index c1f9aea6..00000000 --- a/src/trace_viewer/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -*~ -*.js -*.js.map - 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\ No newline at end of file diff --git a/src/trace_viewer/README b/src/trace_viewer/README deleted file mode 100644 index 547a1435..00000000 --- a/src/trace_viewer/README +++ /dev/null @@ -1,11 +0,0 @@ - -To use, first make sure node.js and npm are installed (e.g. via the -Ubuntu package manager), then run the following in this directory: - -> npm install - -> npm run tsc - -> ./node_modules/.bin/electron . - -and point the file selector at a trace produced by sail -ocaml_trace
\ No newline at end of file diff --git a/src/trace_viewer/index.css b/src/trace_viewer/index.css deleted file mode 100644 index 35ebcb23..00000000 --- a/src/trace_viewer/index.css +++ /dev/null @@ -1,86 +0,0 @@ - -body { - background-color: #202020; - color: #DCDCCC; - font-family: monospace; - font-size: 14pt; - font-weight: bold; -} - -img { - height: 30px; -} - -#control { - position: fixed; - bottom: 0px; - left:10%; - right:10%; - width:80%; -} - -#command { - font-size: 16pt; - width: 100%; -} - -.call { - background-color: #313131; - border: 1px; - border-left: 5px; - border-color: rgb(118, 173, 160); - border-style: solid; - padding-top: 2px; - padding-bottom: 2px; - margin: 0px; - min-height: 32px; - display: flex; - align-items: center; -} - -.write { - background-color: #313131; - border: 1px; - border-left: 5px; - border-color: rgb(255, 40, 40); - border-style: solid; - padding-top: 2px; - padding-bottom: 2px; - margin: 0px; - min-height: 32px; - display: flex; - align-items: center; -} - -.load { - background-color: #313131; - color: white; - border: 1px; - border-left: 5px; - border-color: #ff9100; - border-style: solid; - padding-top: 2px; - padding-bottom: 2px; - margin: 0px; - min-height: 32px; - display: flex; - align-items: center; -} - -.read { - background-color: #313131; - border: 1px; - border-left: 5px; - border-color: rgb(107, 199, 47); - border-style: solid; - padding-top: 2px; - padding-bottom: 2px; - margin: 0px; - min-height: 32px; - display: flex; - align-items: center; -} - -.tree { - padding-left: 20px; -}
\ No newline at end of file diff --git a/src/trace_viewer/index.html b/src/trace_viewer/index.html deleted file mode 100644 index 9efcca56..00000000 --- a/src/trace_viewer/index.html +++ /dev/null @@ -1,19 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <meta charset="UTF-8"> - <title>Sail Trace Viewer</title> - <script type="text/javascript"> - var exports = {} - </script> - <script type="text/javascript" src="index.js"></script> - <link rel="stylesheet" type="text/css" href="index.css"> - </head> - <body> - <div id="container"> - </div> - <div id="control"> - <input type="text" id="command"> - </div> - </body> -</html>
\ No newline at end of file diff --git a/src/trace_viewer/index.ts b/src/trace_viewer/index.ts deleted file mode 100644 index f9b5041b..00000000 --- a/src/trace_viewer/index.ts +++ /dev/null @@ -1,287 +0,0 @@ -import {remote} from "electron" -import fs = require("fs") -const dialog = remote.dialog -const app = remote.app - -let topCallDiv = document.createElement("div") - -const max_arg_length = 5000 - -abstract class Event { - caller: Call - - protected div: HTMLDivElement | null = null - - public hide(): void { - if (this.div != null) { - this.div.remove() - this.div = null - } - } - - protected abstract showText(text: HTMLParagraphElement): void - - public show(): HTMLDivElement { - let callerDiv: HTMLDivElement = (this.caller != null) ? this.caller.show() : topCallDiv - - if (this.div != null) { - return this.div - } else { - this.div = document.createElement("div") - this.div.className = "tree" - callerDiv.appendChild(this.div) - let text = document.createElement("p") - this.showText(text) - this.div.appendChild(text) - return this.div - } - } -} - -class Load extends Event { - loc: string - val: string - - constructor(loc: string, val: string) { - super() - this.loc = loc - this.val = val - } - - protected showText(text: HTMLParagraphElement): void { - text.className = "load" - text.insertAdjacentText('beforeend', this.loc + " " + this.val) - } -} - -class Read extends Event { - reg: string - value: string - - constructor(reg: string, value: string) { - super() - this.reg = reg - this.value = value - } - - public showText(text: HTMLParagraphElement): void { - text.className = "read" - text.insertAdjacentText('beforeend', this.reg + " " + this.value) - } -} - -class Write extends Event { - reg: string - value: string - - constructor(reg: string, value: string) { - super() - this.reg = reg - this.value = value - } - - public showText(text: HTMLParagraphElement): void { - text.className = "write" - text.insertAdjacentText('beforeend', this.reg + " " + this.value) - } -} - -class Call { - fn: string - arg: string - ret: string - callees: (Call | Event)[] = [] - caller: Call - - private div: HTMLDivElement | null = null - - private toggle: boolean = false - private toggleImg: HTMLImageElement | null = null - - constructor(fn: string, arg: string, ret: string) { - this.fn = fn - this.arg = arg - this.ret = ret - } - - public expand() { - if (this.caller != undefined) { - this.caller.expand() - } - this.showChildren() - } - - public iter(f: (call: Call) => void): void { - f(this) - this.callees.forEach((callee) => { - if (callee instanceof Call) { callee.iter(f) } - }) - - } - - public show(): HTMLDivElement { - let callerDiv: HTMLDivElement = (this.caller != null) ? this.caller.show() : topCallDiv - - if (this.div != null) { - return this.div - } else { - this.div = document.createElement("div") - this.div.className = "tree" - callerDiv.appendChild(this.div) - let text = document.createElement("p") - text.className = "call" - if (this.callees.length > 0) { - this.toggleImg = document.createElement("img") - this.toggleImg.src = "List-add.svg" - this.toggleImg.addEventListener('click', () => { - if (this.toggle) { - this.hideChildren() - } else { - this.showChildren() - } - }) - text.appendChild(this.toggleImg) - } - this.toggle = false - let display_arg = this.arg - if (this.arg.length > max_arg_length) { - display_arg = this.arg.slice(0, max_arg_length) - } - let display_ret = this.ret - if (this.ret.length > max_arg_length) { - display_ret = this.ret.slice(0, max_arg_length) - } - - text.insertAdjacentText('beforeend', this.fn + " " + display_arg + " -> " + display_ret) - this.div.appendChild(text) - return this.div - } - } - - public hide(): void { - if (this.toggle == true) { - this.hideChildren() - } - - if (this.div != null) { - this.div.remove() - this.div = null - } - if (this.toggleImg != null) { - this.toggleImg.remove() - this.toggleImg = null - } - } - - public hideChildren(): void { - this.callees.forEach(call => { - call.hide() - }) - - if (this.toggleImg != null) { - this.toggleImg.src = "List-add.svg" - this.toggle = false - } else { - alert("this.toggleImg was null!") - } - } - - public showChildren(): void { - this.callees.forEach(call => { - call.show() - }); - - if (this.toggleImg != null) { - this.toggleImg.src = "List-remove.svg" - this.toggle = true - } else { - alert("this.toggleImg was null!") - } - } - - public appendChild(child: Call | Write | Read | Load): void { - child.caller = this - - this.callees.push(child) - } -} - -document.addEventListener('DOMContentLoaded', () => { - let rootCall = new Call("ROOT", "", "") - topCallDiv.id = "root" - document.getElementById("container")!.appendChild(topCallDiv) - - let commandInput = document.getElementById("command") as HTMLInputElement - - commandInput.addEventListener("keydown", (event) => { - if(event.keyCode == 13) { - let cmd = commandInput.value.split(" ") - commandInput.value = "" - - if (cmd[0] == "function") { - rootCall.iter((call) => { - if (call.fn == cmd[1]) { call.caller.expand() } - }) - } - } - }) - - let files = dialog.showOpenDialog(remote.getCurrentWindow(), {title: "Select log file", defaultPath: app.getAppPath()}) - - if (files == [] || files == undefined) { - dialog.showErrorBox("Error", "No file selected") - app.exit(1) - } - - fs.readFile(files[0], 'utf-8', (err, data) => { - if (err) { - dialog.showErrorBox("Error", "An error occurred when reading the log: " + err.message) - app.exit(1) - } - - let lines = data.split("\n") - // let indents = lines.map(line => line.search(/[^\s]/) / 2) - lines = lines.map(line => line.trim()) - - let stack : Call[] = [rootCall] - - lines.forEach(line => { - if (line.match(/^Call:/)) { - let words = line.slice(6).split(" ") - let call = new Call(words[0], words.slice(1).join(" "), "") - if (stack.length > 0) { - stack[stack.length - 1].appendChild(call) - } - stack.push(call) - } else if (line.match(/^Return:/)) { - let call = stack.pop() - if (call == undefined) { - alert("Unbalanced return") - app.exit(1) - } else { - call.ret = line.slice(8) - } - } else if (line.match(/^Write:/)) { - let words = line.slice(7).split(" ") - let write = new Write(words[0], words.slice(1).join(" ")) - if (stack.length > 0) { - stack[stack.length - 1].appendChild(write) - } - } else if (line.match(/^Read:/)) { - let words = line.slice(6).split(" ") - let read = new Read(words[0], words.slice(1).join(" ")) - if (stack.length > 0) { - stack[stack.length - 1].appendChild(read) - } - } else if (line.match(/^Load:/)) { - let words = line.slice(6).split(" ") - let load = new Load(words[0], words[1]) - if (stack.length > 0) { - stack[stack.length - 1].appendChild(load) - } - } - }) - - rootCall.show() - }) -})
\ No newline at end of file diff --git a/src/trace_viewer/main.ts b/src/trace_viewer/main.ts deleted file mode 100644 index 5cc33452..00000000 --- a/src/trace_viewer/main.ts +++ /dev/null @@ -1,12 +0,0 @@ -import {app, BrowserWindow} from 'electron' - -let win : BrowserWindow | null = null - -app.on('ready', () => { - win = new BrowserWindow({width: 1920, height: 1200}) - win.loadURL('file://' + __dirname + '/index.html') - //win.webContents.openDevTools() - win.on('close', () => { - win = null - }) -})
\ No newline at end of file diff --git a/src/trace_viewer/package.json b/src/trace_viewer/package.json deleted file mode 100644 index e3a88d30..00000000 --- a/src/trace_viewer/package.json +++ /dev/null @@ -1,15 +0,0 @@ -{ - "name": "trace_viewer", - "version": "1.0.0", - "description": "", - "main": "main.js", - "scripts": { - "test": "echo \"Error: no test specified\" && exit 1", - "tsc": "./node_modules/typescript/bin/tsc" - }, - "devDependencies": { - "@types/node": "^8.0.46", - "electron": "1.7.9", - "typescript": "^2.5.3" - } -} diff --git a/src/trace_viewer/tsconfig.json b/src/trace_viewer/tsconfig.json deleted file mode 100644 index e66156b3..00000000 --- a/src/trace_viewer/tsconfig.json +++ /dev/null @@ -1,18 +0,0 @@ -{ - "compileOnSave": true, - "compilerOptions": { - "target": "es5", - "moduleResolution": "node", - "pretty": true, - "newLine": "LF", - "allowSyntheticDefaultImports": true, - "strict": true, - "noUnusedLocals": true, - "noUnusedParameters": true, - "sourceMap": true, - "strictNullChecks": true, - "skipLibCheck": true, - "allowJs": true, - "jsx": "preserve" - } -}
\ No newline at end of file diff --git a/src/type_check.ml b/src/type_check.ml index 9b704a90..2fcfb309 100644 --- a/src/type_check.ml +++ b/src/type_check.ml @@ -746,6 +746,9 @@ end = struct let add_local id mtyp env = begin wf_typ env (snd mtyp); + if Bindings.mem id env.top_val_specs then + typ_error (id_loc id) ("Local variable " ^ string_of_id id ^ " is already bound as a function name") + else (); typ_print ("Adding local binding " ^ string_of_id id ^ " :: " ^ string_of_mtyp mtyp); { env with locals = Bindings.add id mtyp env.locals } end @@ -1283,6 +1286,8 @@ let rec nexp_identical (Nexp_aux (nexp1, _)) (Nexp_aux (nexp2, _)) = | Nexp_minus (n1a, n1b), Nexp_minus (n2a, n2b) -> nexp_identical n1a n2a && nexp_identical n1b n2b | Nexp_exp n1, Nexp_exp n2 -> nexp_identical n1 n2 | Nexp_neg n1, Nexp_neg n2 -> nexp_identical n1 n2 + | Nexp_app (f1, args1), Nexp_app (f2, args2) when List.length args1 = List.length args2 -> + Id.compare f1 f2 = 0 && List.for_all2 nexp_identical args1 args2 | _, _ -> false let ord_identical (Ord_aux (ord1, _)) (Ord_aux (ord2, _)) = @@ -3401,16 +3406,16 @@ and propagate_lexp_effect_aux = function (* 6. Checking toplevel definitions *) (**************************************************************************) -let check_letdef env (LB_aux (letbind, (l, _))) = +let check_letdef orig_env (LB_aux (letbind, (l, _))) = begin match letbind with | LB_val (P_aux (P_typ (typ_annot, pat), _), bind) -> - let checked_bind = crule check_exp env (strip_exp bind) typ_annot in - let tpat, env = bind_pat_no_guard env (strip_pat pat) typ_annot in - [DEF_val (LB_aux (LB_val (P_aux (P_typ (typ_annot, tpat), (l, Some (env, typ_annot, no_effect))), checked_bind), (l, None)))], env + let checked_bind = crule check_exp orig_env (strip_exp bind) typ_annot in + let tpat, env = bind_pat_no_guard orig_env (strip_pat pat) typ_annot in + [DEF_val (LB_aux (LB_val (P_aux (P_typ (typ_annot, tpat), (l, Some (orig_env, typ_annot, no_effect))), checked_bind), (l, None)))], env | LB_val (pat, bind) -> - let inferred_bind = irule infer_exp env (strip_exp bind) in - let tpat, env = bind_pat_no_guard env (strip_pat pat) (typ_of inferred_bind) in + let inferred_bind = irule infer_exp orig_env (strip_exp bind) in + let tpat, env = bind_pat_no_guard orig_env (strip_pat pat) (typ_of inferred_bind) in [DEF_val (LB_aux (LB_val (tpat, inferred_bind), (l, None)))], env end diff --git a/src/util.ml b/src/util.ml index e2dc9b9f..b8670b84 100644 --- a/src/util.ml +++ b/src/util.ml @@ -389,12 +389,16 @@ let rec take n xs = match n, xs with | n, (x :: xs) -> x :: take (n - 1) xs let termcode n = "\x1B[" ^ string_of_int n ^ "m" + let bold str = termcode 1 ^ str + +let red str = termcode 91 ^ str let green str = termcode 92 ^ str let yellow str = termcode 93 ^ str -let red str = termcode 91 ^ str -let cyan str = termcode 96 ^ str let blue str = termcode 94 ^ str +let magenta str = termcode 95 ^ str +let cyan str = termcode 96 ^ str + let clear str = str ^ termcode 0 let zchar c = diff --git a/src/util.mli b/src/util.mli index 2b4d2e93..46d99002 100644 --- a/src/util.mli +++ b/src/util.mli @@ -240,6 +240,7 @@ val red : string -> string val yellow : string -> string val cyan : string -> string val blue : string -> string +val magenta : string -> string val clear : string -> string val warn : string -> unit diff --git a/test/mono/assert.sail b/test/mono/assert.sail index 4b782398..5b4a013a 100644 --- a/test/mono/assert.sail +++ b/test/mono/assert.sail @@ -1,8 +1,25 @@ -val f : forall 'n. atom('n) -> unit effect {escape} +val f : forall 'n 'm. (atom('n), atom('m)) -> unit effect {escape} -function f(n) = { - assert(constraint('n in {8,16})); - let 'm = 2 * n in - let x : bits('m) = replicate_bits(0b0,'m) in +function f(n,m) = { + assert(constraint('n in {8,16} & 'm < 'n)); + let 'p = 2 * n in + let x : bits('p) = replicate_bits(0b0,'p) in + () +} + +val g : forall 'n 'm. (atom('n), atom('m)) -> unit effect {escape} + +function g(n,m) = { + assert(constraint('n in {8,16}) & 'm < 'n); + let 'p = 2 * n in + let x : bits('p) = replicate_bits(0b0,'p) in + () +} +val h : forall 'n 'm. (atom('n), atom('m)) -> unit effect {escape} + +function h(n,m) = { + assert(('n == 8 | 'n == 16) & 'm < 'n); + let 'p = 2 * n in + let x : bits('p) = replicate_bits(0b0,'p) in () } diff --git a/test/ocaml/run_tests.sh b/test/ocaml/run_tests.sh index 62fe9950..370048a0 100755 --- a/test/ocaml/run_tests.sh +++ b/test/ocaml/run_tests.sh @@ -50,7 +50,7 @@ printf "<testsuites>\n" >> $DIR/tests.xml for i in `ls -d */`; do cd $DIR/$i; - if $SAILDIR/sail -o out -ocaml ../prelude.sail `ls *.sail` 1> /dev/null; + if $SAILDIR/sail -no_warn -o out -ocaml ../prelude.sail `ls *.sail` 1> /dev/null; then ./out > result; if diff expect result; @@ -74,7 +74,7 @@ cd $DIR for i in `ls -d */`; do cd $DIR/$i; - if $SAILDIR/sail -o out -ocaml_trace ../prelude.sail `ls *.sail` 1> /dev/null; + if $SAILDIR/sail -no_warn -o out -ocaml_trace ../prelude.sail `ls *.sail` 1> /dev/null; then ./out > result 2> /dev/null; if diff expect result; @@ -98,7 +98,7 @@ cd $DIR for i in `ls -d */`; do cd $DIR/$i; - if $SAILDIR/sail -is test.isail ../prelude.sail `ls *.sail` 1> /dev/null; + if $SAILDIR/sail -no_warn -is test.isail ../prelude.sail `ls *.sail` 1> /dev/null; then if diff expect result; then diff --git a/test/ocaml/vec_32_64/vec_32_64.sail b/test/ocaml/vec_32_64/vec_32_64.sail index 60fa0e46..5afd421d 100644 --- a/test/ocaml/vec_32_64/vec_32_64.sail +++ b/test/ocaml/vec_32_64/vec_32_64.sail @@ -16,9 +16,9 @@ function zeros n = val main : unit -> unit function main () = { - let 'length = get_size (); - let xs = zeros(length); - if (length == 32) then { + let 'len = get_size (); + let xs = zeros(len); + if (len == 32) then { () } else { only64(xs) diff --git a/test/riscv/run_tests.sh b/test/riscv/run_tests.sh index d52caeb4..dd19bd72 100755 --- a/test/riscv/run_tests.sh +++ b/test/riscv/run_tests.sh @@ -49,15 +49,24 @@ printf "<testsuites>\n" >> $DIR/tests.xml cd $SAILDIR/riscv -printf "Checking specification...\n" +printf "Building RISCV specification...\n" -if make -C $SAILDIR/riscv check; +if make -C $SAILDIR/riscv riscv ; then - green "checked RISCV specification" "ok" + green "Building RISCV specification" "ok" else - red "checking RISCV specification" "fail" + red "Building RISCV specification" "fail" fi +for test in $DIR/tests/*.elf; do + if $SAILDIR/riscv/riscv "$test" >"${test/.elf/.out}" 2>&1 && grep -q SUCCESS "${test/.elf/.out}" + then + green "$test" "ok" + else + red "$test" "fail" + fi +done + finish_suite "RISCV tests" printf "</testsuites>\n" >> $DIR/tests.xml diff --git a/test/riscv/tests/README b/test/riscv/tests/README new file mode 100644 index 00000000..4dcfeb11 --- /dev/null +++ b/test/riscv/tests/README @@ -0,0 +1,27 @@ +Copyright (c) 2012-2015, The Regents of the University of California (Regents). +All Rights Reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the Regents nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, +SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING +OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS +BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED +HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE +MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + +The tests in this directory were built from +https://github.com/riscv/riscv-tools commit 98682995dc4a1ab8777ff45ba673cf2658e54ae2 . diff --git a/test/riscv/tests/rv64ua-p-amoadd_d.dump b/test/riscv/tests/rv64ua-p-amoadd_d.dump new file mode 100644 index 00000000..e90473bb --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoadd_d.dump @@ -0,0 +1,153 @@ + +rv64ua-p-amoadd_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6b023 sd a0,0(a3) + 80000110: 00b6b72f amoadd.d a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71863 bne a4,t4,8000016c <fail> + +0000000080000120 <test_3>: + 80000120: 0006b783 ld a5,0(a3) + 80000124: fff00e9b addiw t4,zero,-1 + 80000128: 01fe9e93 slli t4,t4,0x1f + 8000012c: 800e8e93 addi t4,t4,-2048 # ffffffff7ffff800 <_end+0xfffffffeffffd7f8> + 80000130: 00300193 li gp,3 + 80000134: 03d79c63 bne a5,t4,8000016c <fail> + +0000000080000138 <test_4>: + 80000138: 00b6b72f amoadd.d a4,a1,(a3) + 8000013c: fff00e9b addiw t4,zero,-1 + 80000140: 01fe9e93 slli t4,t4,0x1f + 80000144: 800e8e93 addi t4,t4,-2048 + 80000148: 00400193 li gp,4 + 8000014c: 03d71063 bne a4,t4,8000016c <fail> + +0000000080000150 <test_5>: + 80000150: 0006b783 ld a5,0(a3) + 80000154: fff80eb7 lui t4,0xfff80 + 80000158: fffe8e9b addiw t4,t4,-1 + 8000015c: 00ce9e93 slli t4,t4,0xc + 80000160: 00500193 li gp,5 + 80000164: 01d79463 bne a5,t4,8000016c <fail> + 80000168: 00301c63 bne zero,gp,80000180 <pass> + +000000008000016c <fail>: + 8000016c: 0ff0000f fence + 80000170: 00018063 beqz gp,80000170 <fail+0x4> + 80000174: 00119193 slli gp,gp,0x1 + 80000178: 0011e193 ori gp,gp,1 + 8000017c: 00000073 ecall + +0000000080000180 <pass>: + 80000180: 0ff0000f fence + 80000184: 00100193 li gp,1 + 80000188: 00000073 ecall + 8000018c: c0001073 unimp + 80000190: 0000 unimp + 80000192: 0000 unimp + 80000194: 0000 unimp + 80000196: 0000 unimp + 80000198: 0000 unimp + 8000019a: 0000 unimp + 8000019c: 0000 unimp + 8000019e: 0000 unimp + 800001a0: 0000 unimp + 800001a2: 0000 unimp + 800001a4: 0000 unimp + 800001a6: 0000 unimp + 800001a8: 0000 unimp + 800001aa: 0000 unimp + 800001ac: 0000 unimp + 800001ae: 0000 unimp + 800001b0: 0000 unimp + 800001b2: 0000 unimp + 800001b4: 0000 unimp + 800001b6: 0000 unimp + 800001b8: 0000 unimp + 800001ba: 0000 unimp + 800001bc: 0000 unimp + 800001be: 0000 unimp + 800001c0: 0000 unimp + 800001c2: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoadd_d.elf b/test/riscv/tests/rv64ua-p-amoadd_d.elf Binary files differnew file mode 100755 index 00000000..f4fac374 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoadd_d.elf diff --git a/test/riscv/tests/rv64ua-p-amoadd_w.dump b/test/riscv/tests/rv64ua-p-amoadd_w.dump new file mode 100644 index 00000000..a0bc84ef --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoadd_w.dump @@ -0,0 +1,124 @@ + +rv64ua-p-amoadd_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6a023 sw a0,0(a3) + 80000110: 00b6a72f amoadd.w a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71263 bne a4,t4,80000160 <fail> + +0000000080000120 <test_3>: + 80000120: 0006a783 lw a5,0(a3) + 80000124: 80000eb7 lui t4,0x80000 + 80000128: 800e8e9b addiw t4,t4,-2048 + 8000012c: 00300193 li gp,3 + 80000130: 03d79863 bne a5,t4,80000160 <fail> + +0000000080000134 <test_4>: + 80000134: 800005b7 lui a1,0x80000 + 80000138: 00b6a72f amoadd.w a4,a1,(a3) + 8000013c: 80000eb7 lui t4,0x80000 + 80000140: 800e8e9b addiw t4,t4,-2048 + 80000144: 00400193 li gp,4 + 80000148: 01d71c63 bne a4,t4,80000160 <fail> + +000000008000014c <test_5>: + 8000014c: 0006a783 lw a5,0(a3) + 80000150: 80000e93 li t4,-2048 + 80000154: 00500193 li gp,5 + 80000158: 01d79463 bne a5,t4,80000160 <fail> + 8000015c: 00301c63 bne zero,gp,80000174 <pass> + +0000000080000160 <fail>: + 80000160: 0ff0000f fence + 80000164: 00018063 beqz gp,80000164 <fail+0x4> + 80000168: 00119193 slli gp,gp,0x1 + 8000016c: 0011e193 ori gp,gp,1 + 80000170: 00000073 ecall + +0000000080000174 <pass>: + 80000174: 0ff0000f fence + 80000178: 00100193 li gp,1 + 8000017c: 00000073 ecall + 80000180: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-p-amoadd_w.elf b/test/riscv/tests/rv64ua-p-amoadd_w.elf Binary files differnew file mode 100755 index 00000000..4b3457d8 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoadd_w.elf diff --git a/test/riscv/tests/rv64ua-p-amoand_d.dump b/test/riscv/tests/rv64ua-p-amoand_d.dump new file mode 100644 index 00000000..cb398f8d --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoand_d.dump @@ -0,0 +1,124 @@ + +rv64ua-p-amoand_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6b023 sd a0,0(a3) + 80000110: 60b6b72f amoand.d a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71263 bne a4,t4,80000160 <fail> + +0000000080000120 <test_3>: + 80000120: 0006b783 ld a5,0(a3) + 80000124: 80000eb7 lui t4,0x80000 + 80000128: 00300193 li gp,3 + 8000012c: 03d79a63 bne a5,t4,80000160 <fail> + +0000000080000130 <test_4>: + 80000130: 0010059b addiw a1,zero,1 + 80000134: 01f59593 slli a1,a1,0x1f + 80000138: 60b6b72f amoand.d a4,a1,(a3) + 8000013c: 80000eb7 lui t4,0x80000 + 80000140: 00400193 li gp,4 + 80000144: 01d71e63 bne a4,t4,80000160 <fail> + +0000000080000148 <test_5>: + 80000148: 0006b783 ld a5,0(a3) + 8000014c: 00100e9b addiw t4,zero,1 + 80000150: 01fe9e93 slli t4,t4,0x1f + 80000154: 00500193 li gp,5 + 80000158: 01d79463 bne a5,t4,80000160 <fail> + 8000015c: 00301c63 bne zero,gp,80000174 <pass> + +0000000080000160 <fail>: + 80000160: 0ff0000f fence + 80000164: 00018063 beqz gp,80000164 <fail+0x4> + 80000168: 00119193 slli gp,gp,0x1 + 8000016c: 0011e193 ori gp,gp,1 + 80000170: 00000073 ecall + +0000000080000174 <pass>: + 80000174: 0ff0000f fence + 80000178: 00100193 li gp,1 + 8000017c: 00000073 ecall + 80000180: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-p-amoand_d.elf b/test/riscv/tests/rv64ua-p-amoand_d.elf Binary files differnew file mode 100755 index 00000000..47e8b321 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoand_d.elf diff --git a/test/riscv/tests/rv64ua-p-amoand_w.dump b/test/riscv/tests/rv64ua-p-amoand_w.dump new file mode 100644 index 00000000..83ce206d --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoand_w.dump @@ -0,0 +1,125 @@ + +rv64ua-p-amoand_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6a023 sw a0,0(a3) + 80000110: 60b6a72f amoand.w a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71063 bne a4,t4,8000015c <fail> + +0000000080000120 <test_3>: + 80000120: 0006a783 lw a5,0(a3) + 80000124: 80000eb7 lui t4,0x80000 + 80000128: 00300193 li gp,3 + 8000012c: 03d79863 bne a5,t4,8000015c <fail> + +0000000080000130 <test_4>: + 80000130: 0010059b addiw a1,zero,1 + 80000134: 01f59593 slli a1,a1,0x1f + 80000138: 60b6a72f amoand.w a4,a1,(a3) + 8000013c: 80000eb7 lui t4,0x80000 + 80000140: 00400193 li gp,4 + 80000144: 01d71c63 bne a4,t4,8000015c <fail> + +0000000080000148 <test_5>: + 80000148: 0006a783 lw a5,0(a3) + 8000014c: 80000eb7 lui t4,0x80000 + 80000150: 00500193 li gp,5 + 80000154: 01d79463 bne a5,t4,8000015c <fail> + 80000158: 00301c63 bne zero,gp,80000170 <pass> + +000000008000015c <fail>: + 8000015c: 0ff0000f fence + 80000160: 00018063 beqz gp,80000160 <fail+0x4> + 80000164: 00119193 slli gp,gp,0x1 + 80000168: 0011e193 ori gp,gp,1 + 8000016c: 00000073 ecall + +0000000080000170 <pass>: + 80000170: 0ff0000f fence + 80000174: 00100193 li gp,1 + 80000178: 00000073 ecall + 8000017c: c0001073 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoand_w.elf b/test/riscv/tests/rv64ua-p-amoand_w.elf Binary files differnew file mode 100755 index 00000000..06c29f8b --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoand_w.elf diff --git a/test/riscv/tests/rv64ua-p-amomax_d.dump b/test/riscv/tests/rv64ua-p-amomax_d.dump new file mode 100644 index 00000000..c91c2c8a --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amomax_d.dump @@ -0,0 +1,125 @@ + +rv64ua-p-amomax_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6b023 sd a0,0(a3) + 80000110: a0b6b72f amomax.d a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71063 bne a4,t4,8000015c <fail> + +0000000080000120 <test_3>: + 80000120: 0006b783 ld a5,0(a3) + 80000124: 80000e93 li t4,-2048 + 80000128: 00300193 li gp,3 + 8000012c: 03d79863 bne a5,t4,8000015c <fail> + +0000000080000130 <test_4>: + 80000130: 00100593 li a1,1 + 80000134: 0006b023 sd zero,0(a3) + 80000138: a0b6b72f amomax.d a4,a1,(a3) + 8000013c: 00000e93 li t4,0 + 80000140: 00400193 li gp,4 + 80000144: 01d71c63 bne a4,t4,8000015c <fail> + +0000000080000148 <test_5>: + 80000148: 0006b783 ld a5,0(a3) + 8000014c: 00100e93 li t4,1 + 80000150: 00500193 li gp,5 + 80000154: 01d79463 bne a5,t4,8000015c <fail> + 80000158: 00301c63 bne zero,gp,80000170 <pass> + +000000008000015c <fail>: + 8000015c: 0ff0000f fence + 80000160: 00018063 beqz gp,80000160 <fail+0x4> + 80000164: 00119193 slli gp,gp,0x1 + 80000168: 0011e193 ori gp,gp,1 + 8000016c: 00000073 ecall + +0000000080000170 <pass>: + 80000170: 0ff0000f fence + 80000174: 00100193 li gp,1 + 80000178: 00000073 ecall + 8000017c: c0001073 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amomax_d.elf b/test/riscv/tests/rv64ua-p-amomax_d.elf Binary files differnew file mode 100755 index 00000000..4828a226 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amomax_d.elf diff --git a/test/riscv/tests/rv64ua-p-amomax_w.dump b/test/riscv/tests/rv64ua-p-amomax_w.dump new file mode 100644 index 00000000..5de2185e --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amomax_w.dump @@ -0,0 +1,125 @@ + +rv64ua-p-amomax_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6a023 sw a0,0(a3) + 80000110: a0b6a72f amomax.w a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71063 bne a4,t4,8000015c <fail> + +0000000080000120 <test_3>: + 80000120: 0006a783 lw a5,0(a3) + 80000124: 80000e93 li t4,-2048 + 80000128: 00300193 li gp,3 + 8000012c: 03d79863 bne a5,t4,8000015c <fail> + +0000000080000130 <test_4>: + 80000130: 00100593 li a1,1 + 80000134: 0006a023 sw zero,0(a3) + 80000138: a0b6a72f amomax.w a4,a1,(a3) + 8000013c: 00000e93 li t4,0 + 80000140: 00400193 li gp,4 + 80000144: 01d71c63 bne a4,t4,8000015c <fail> + +0000000080000148 <test_5>: + 80000148: 0006a783 lw a5,0(a3) + 8000014c: 00100e93 li t4,1 + 80000150: 00500193 li gp,5 + 80000154: 01d79463 bne a5,t4,8000015c <fail> + 80000158: 00301c63 bne zero,gp,80000170 <pass> + +000000008000015c <fail>: + 8000015c: 0ff0000f fence + 80000160: 00018063 beqz gp,80000160 <fail+0x4> + 80000164: 00119193 slli gp,gp,0x1 + 80000168: 0011e193 ori gp,gp,1 + 8000016c: 00000073 ecall + +0000000080000170 <pass>: + 80000170: 0ff0000f fence + 80000174: 00100193 li gp,1 + 80000178: 00000073 ecall + 8000017c: c0001073 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amomax_w.elf b/test/riscv/tests/rv64ua-p-amomax_w.elf Binary files differnew file mode 100755 index 00000000..1336c9c7 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amomax_w.elf diff --git a/test/riscv/tests/rv64ua-p-amomaxu_d.dump b/test/riscv/tests/rv64ua-p-amomaxu_d.dump new file mode 100644 index 00000000..8492cd4d --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amomaxu_d.dump @@ -0,0 +1,125 @@ + +rv64ua-p-amomaxu_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6b023 sd a0,0(a3) + 80000110: e0b6b72f amomaxu.d a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71063 bne a4,t4,8000015c <fail> + +0000000080000120 <test_3>: + 80000120: 0006b783 ld a5,0(a3) + 80000124: 80000e93 li t4,-2048 + 80000128: 00300193 li gp,3 + 8000012c: 03d79863 bne a5,t4,8000015c <fail> + +0000000080000130 <test_4>: + 80000130: fff00593 li a1,-1 + 80000134: 0006b023 sd zero,0(a3) + 80000138: e0b6b72f amomaxu.d a4,a1,(a3) + 8000013c: 00000e93 li t4,0 + 80000140: 00400193 li gp,4 + 80000144: 01d71c63 bne a4,t4,8000015c <fail> + +0000000080000148 <test_5>: + 80000148: 0006b783 ld a5,0(a3) + 8000014c: fff00e93 li t4,-1 + 80000150: 00500193 li gp,5 + 80000154: 01d79463 bne a5,t4,8000015c <fail> + 80000158: 00301c63 bne zero,gp,80000170 <pass> + +000000008000015c <fail>: + 8000015c: 0ff0000f fence + 80000160: 00018063 beqz gp,80000160 <fail+0x4> + 80000164: 00119193 slli gp,gp,0x1 + 80000168: 0011e193 ori gp,gp,1 + 8000016c: 00000073 ecall + +0000000080000170 <pass>: + 80000170: 0ff0000f fence + 80000174: 00100193 li gp,1 + 80000178: 00000073 ecall + 8000017c: c0001073 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amomaxu_d.elf b/test/riscv/tests/rv64ua-p-amomaxu_d.elf Binary files differnew file mode 100755 index 00000000..04a36aad --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amomaxu_d.elf diff --git a/test/riscv/tests/rv64ua-p-amomaxu_w.dump b/test/riscv/tests/rv64ua-p-amomaxu_w.dump new file mode 100644 index 00000000..1f01067b --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amomaxu_w.dump @@ -0,0 +1,125 @@ + +rv64ua-p-amomaxu_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6a023 sw a0,0(a3) + 80000110: e0b6a72f amomaxu.w a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71063 bne a4,t4,8000015c <fail> + +0000000080000120 <test_3>: + 80000120: 0006a783 lw a5,0(a3) + 80000124: 80000e93 li t4,-2048 + 80000128: 00300193 li gp,3 + 8000012c: 03d79863 bne a5,t4,8000015c <fail> + +0000000080000130 <test_4>: + 80000130: fff00593 li a1,-1 + 80000134: 0006a023 sw zero,0(a3) + 80000138: e0b6a72f amomaxu.w a4,a1,(a3) + 8000013c: 00000e93 li t4,0 + 80000140: 00400193 li gp,4 + 80000144: 01d71c63 bne a4,t4,8000015c <fail> + +0000000080000148 <test_5>: + 80000148: 0006a783 lw a5,0(a3) + 8000014c: fff00e93 li t4,-1 + 80000150: 00500193 li gp,5 + 80000154: 01d79463 bne a5,t4,8000015c <fail> + 80000158: 00301c63 bne zero,gp,80000170 <pass> + +000000008000015c <fail>: + 8000015c: 0ff0000f fence + 80000160: 00018063 beqz gp,80000160 <fail+0x4> + 80000164: 00119193 slli gp,gp,0x1 + 80000168: 0011e193 ori gp,gp,1 + 8000016c: 00000073 ecall + +0000000080000170 <pass>: + 80000170: 0ff0000f fence + 80000174: 00100193 li gp,1 + 80000178: 00000073 ecall + 8000017c: c0001073 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amomaxu_w.elf b/test/riscv/tests/rv64ua-p-amomaxu_w.elf Binary files differnew file mode 100755 index 00000000..37b392f4 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amomaxu_w.elf diff --git a/test/riscv/tests/rv64ua-p-amomin_d.dump b/test/riscv/tests/rv64ua-p-amomin_d.dump new file mode 100644 index 00000000..a45ab4fd --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amomin_d.dump @@ -0,0 +1,125 @@ + +rv64ua-p-amomin_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6b023 sd a0,0(a3) + 80000110: 80b6b72f amomin.d a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71063 bne a4,t4,8000015c <fail> + +0000000080000120 <test_3>: + 80000120: 0006b783 ld a5,0(a3) + 80000124: 80000eb7 lui t4,0x80000 + 80000128: 00300193 li gp,3 + 8000012c: 03d79863 bne a5,t4,8000015c <fail> + +0000000080000130 <test_4>: + 80000130: fff00593 li a1,-1 + 80000134: 0006b023 sd zero,0(a3) + 80000138: 80b6b72f amomin.d a4,a1,(a3) + 8000013c: 00000e93 li t4,0 + 80000140: 00400193 li gp,4 + 80000144: 01d71c63 bne a4,t4,8000015c <fail> + +0000000080000148 <test_5>: + 80000148: 0006b783 ld a5,0(a3) + 8000014c: fff00e93 li t4,-1 + 80000150: 00500193 li gp,5 + 80000154: 01d79463 bne a5,t4,8000015c <fail> + 80000158: 00301c63 bne zero,gp,80000170 <pass> + +000000008000015c <fail>: + 8000015c: 0ff0000f fence + 80000160: 00018063 beqz gp,80000160 <fail+0x4> + 80000164: 00119193 slli gp,gp,0x1 + 80000168: 0011e193 ori gp,gp,1 + 8000016c: 00000073 ecall + +0000000080000170 <pass>: + 80000170: 0ff0000f fence + 80000174: 00100193 li gp,1 + 80000178: 00000073 ecall + 8000017c: c0001073 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amomin_d.elf b/test/riscv/tests/rv64ua-p-amomin_d.elf Binary files differnew file mode 100755 index 00000000..87a28983 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amomin_d.elf diff --git a/test/riscv/tests/rv64ua-p-amomin_w.dump b/test/riscv/tests/rv64ua-p-amomin_w.dump new file mode 100644 index 00000000..b97ec5a8 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amomin_w.dump @@ -0,0 +1,125 @@ + +rv64ua-p-amomin_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6a023 sw a0,0(a3) + 80000110: 80b6a72f amomin.w a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71063 bne a4,t4,8000015c <fail> + +0000000080000120 <test_3>: + 80000120: 0006a783 lw a5,0(a3) + 80000124: 80000eb7 lui t4,0x80000 + 80000128: 00300193 li gp,3 + 8000012c: 03d79863 bne a5,t4,8000015c <fail> + +0000000080000130 <test_4>: + 80000130: fff00593 li a1,-1 + 80000134: 0006a023 sw zero,0(a3) + 80000138: 80b6a72f amomin.w a4,a1,(a3) + 8000013c: 00000e93 li t4,0 + 80000140: 00400193 li gp,4 + 80000144: 01d71c63 bne a4,t4,8000015c <fail> + +0000000080000148 <test_5>: + 80000148: 0006a783 lw a5,0(a3) + 8000014c: fff00e93 li t4,-1 + 80000150: 00500193 li gp,5 + 80000154: 01d79463 bne a5,t4,8000015c <fail> + 80000158: 00301c63 bne zero,gp,80000170 <pass> + +000000008000015c <fail>: + 8000015c: 0ff0000f fence + 80000160: 00018063 beqz gp,80000160 <fail+0x4> + 80000164: 00119193 slli gp,gp,0x1 + 80000168: 0011e193 ori gp,gp,1 + 8000016c: 00000073 ecall + +0000000080000170 <pass>: + 80000170: 0ff0000f fence + 80000174: 00100193 li gp,1 + 80000178: 00000073 ecall + 8000017c: c0001073 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amomin_w.elf b/test/riscv/tests/rv64ua-p-amomin_w.elf Binary files differnew file mode 100755 index 00000000..201e7deb --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amomin_w.elf diff --git a/test/riscv/tests/rv64ua-p-amominu_d.dump b/test/riscv/tests/rv64ua-p-amominu_d.dump new file mode 100644 index 00000000..c4b90c66 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amominu_d.dump @@ -0,0 +1,125 @@ + +rv64ua-p-amominu_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6b023 sd a0,0(a3) + 80000110: c0b6b72f amominu.d a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71063 bne a4,t4,8000015c <fail> + +0000000080000120 <test_3>: + 80000120: 0006b783 ld a5,0(a3) + 80000124: 80000eb7 lui t4,0x80000 + 80000128: 00300193 li gp,3 + 8000012c: 03d79863 bne a5,t4,8000015c <fail> + +0000000080000130 <test_4>: + 80000130: fff00593 li a1,-1 + 80000134: 0006b023 sd zero,0(a3) + 80000138: c0b6b72f amominu.d a4,a1,(a3) + 8000013c: 00000e93 li t4,0 + 80000140: 00400193 li gp,4 + 80000144: 01d71c63 bne a4,t4,8000015c <fail> + +0000000080000148 <test_5>: + 80000148: 0006b783 ld a5,0(a3) + 8000014c: 00000e93 li t4,0 + 80000150: 00500193 li gp,5 + 80000154: 01d79463 bne a5,t4,8000015c <fail> + 80000158: 00301c63 bne zero,gp,80000170 <pass> + +000000008000015c <fail>: + 8000015c: 0ff0000f fence + 80000160: 00018063 beqz gp,80000160 <fail+0x4> + 80000164: 00119193 slli gp,gp,0x1 + 80000168: 0011e193 ori gp,gp,1 + 8000016c: 00000073 ecall + +0000000080000170 <pass>: + 80000170: 0ff0000f fence + 80000174: 00100193 li gp,1 + 80000178: 00000073 ecall + 8000017c: c0001073 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amominu_d.elf b/test/riscv/tests/rv64ua-p-amominu_d.elf Binary files differnew file mode 100755 index 00000000..a5cee277 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amominu_d.elf diff --git a/test/riscv/tests/rv64ua-p-amominu_w.dump b/test/riscv/tests/rv64ua-p-amominu_w.dump new file mode 100644 index 00000000..7a80790f --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amominu_w.dump @@ -0,0 +1,125 @@ + +rv64ua-p-amominu_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6a023 sw a0,0(a3) + 80000110: c0b6a72f amominu.w a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71063 bne a4,t4,8000015c <fail> + +0000000080000120 <test_3>: + 80000120: 0006a783 lw a5,0(a3) + 80000124: 80000eb7 lui t4,0x80000 + 80000128: 00300193 li gp,3 + 8000012c: 03d79863 bne a5,t4,8000015c <fail> + +0000000080000130 <test_4>: + 80000130: fff00593 li a1,-1 + 80000134: 0006a023 sw zero,0(a3) + 80000138: c0b6a72f amominu.w a4,a1,(a3) + 8000013c: 00000e93 li t4,0 + 80000140: 00400193 li gp,4 + 80000144: 01d71c63 bne a4,t4,8000015c <fail> + +0000000080000148 <test_5>: + 80000148: 0006a783 lw a5,0(a3) + 8000014c: 00000e93 li t4,0 + 80000150: 00500193 li gp,5 + 80000154: 01d79463 bne a5,t4,8000015c <fail> + 80000158: 00301c63 bne zero,gp,80000170 <pass> + +000000008000015c <fail>: + 8000015c: 0ff0000f fence + 80000160: 00018063 beqz gp,80000160 <fail+0x4> + 80000164: 00119193 slli gp,gp,0x1 + 80000168: 0011e193 ori gp,gp,1 + 8000016c: 00000073 ecall + +0000000080000170 <pass>: + 80000170: 0ff0000f fence + 80000174: 00100193 li gp,1 + 80000178: 00000073 ecall + 8000017c: c0001073 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amominu_w.elf b/test/riscv/tests/rv64ua-p-amominu_w.elf Binary files differnew file mode 100755 index 00000000..a2b0bfdd --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amominu_w.elf diff --git a/test/riscv/tests/rv64ua-p-amoor_d.dump b/test/riscv/tests/rv64ua-p-amoor_d.dump new file mode 100644 index 00000000..0248704e --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoor_d.dump @@ -0,0 +1,126 @@ + +rv64ua-p-amoor_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6b023 sd a0,0(a3) + 80000110: 40b6b72f amoor.d a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 03d71e63 bne a4,t4,80000158 <fail> + +0000000080000120 <test_3>: + 80000120: 0006b783 ld a5,0(a3) + 80000124: 80000e93 li t4,-2048 + 80000128: 00300193 li gp,3 + 8000012c: 03d79663 bne a5,t4,80000158 <fail> + +0000000080000130 <test_4>: + 80000130: 00100593 li a1,1 + 80000134: 40b6b72f amoor.d a4,a1,(a3) + 80000138: 80000e93 li t4,-2048 + 8000013c: 00400193 li gp,4 + 80000140: 01d71c63 bne a4,t4,80000158 <fail> + +0000000080000144 <test_5>: + 80000144: 0006b783 ld a5,0(a3) + 80000148: 80100e93 li t4,-2047 + 8000014c: 00500193 li gp,5 + 80000150: 01d79463 bne a5,t4,80000158 <fail> + 80000154: 00301c63 bne zero,gp,8000016c <pass> + +0000000080000158 <fail>: + 80000158: 0ff0000f fence + 8000015c: 00018063 beqz gp,8000015c <fail+0x4> + 80000160: 00119193 slli gp,gp,0x1 + 80000164: 0011e193 ori gp,gp,1 + 80000168: 00000073 ecall + +000000008000016c <pass>: + 8000016c: 0ff0000f fence + 80000170: 00100193 li gp,1 + 80000174: 00000073 ecall + 80000178: c0001073 unimp + 8000017c: 0000 unimp + 8000017e: 0000 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoor_d.elf b/test/riscv/tests/rv64ua-p-amoor_d.elf Binary files differnew file mode 100755 index 00000000..3549d35f --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoor_d.elf diff --git a/test/riscv/tests/rv64ua-p-amoor_w.dump b/test/riscv/tests/rv64ua-p-amoor_w.dump new file mode 100644 index 00000000..d20d20a6 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoor_w.dump @@ -0,0 +1,126 @@ + +rv64ua-p-amoor_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6a023 sw a0,0(a3) + 80000110: 40b6a72f amoor.w a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 03d71e63 bne a4,t4,80000158 <fail> + +0000000080000120 <test_3>: + 80000120: 0006a783 lw a5,0(a3) + 80000124: 80000e93 li t4,-2048 + 80000128: 00300193 li gp,3 + 8000012c: 03d79663 bne a5,t4,80000158 <fail> + +0000000080000130 <test_4>: + 80000130: 00100593 li a1,1 + 80000134: 40b6a72f amoor.w a4,a1,(a3) + 80000138: 80000e93 li t4,-2048 + 8000013c: 00400193 li gp,4 + 80000140: 01d71c63 bne a4,t4,80000158 <fail> + +0000000080000144 <test_5>: + 80000144: 0006a783 lw a5,0(a3) + 80000148: 80100e93 li t4,-2047 + 8000014c: 00500193 li gp,5 + 80000150: 01d79463 bne a5,t4,80000158 <fail> + 80000154: 00301c63 bne zero,gp,8000016c <pass> + +0000000080000158 <fail>: + 80000158: 0ff0000f fence + 8000015c: 00018063 beqz gp,8000015c <fail+0x4> + 80000160: 00119193 slli gp,gp,0x1 + 80000164: 0011e193 ori gp,gp,1 + 80000168: 00000073 ecall + +000000008000016c <pass>: + 8000016c: 0ff0000f fence + 80000170: 00100193 li gp,1 + 80000174: 00000073 ecall + 80000178: c0001073 unimp + 8000017c: 0000 unimp + 8000017e: 0000 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoor_w.elf b/test/riscv/tests/rv64ua-p-amoor_w.elf Binary files differnew file mode 100755 index 00000000..4e408f28 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoor_w.elf diff --git a/test/riscv/tests/rv64ua-p-amoswap_d.dump b/test/riscv/tests/rv64ua-p-amoswap_d.dump new file mode 100644 index 00000000..f61e23bd --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoswap_d.dump @@ -0,0 +1,124 @@ + +rv64ua-p-amoswap_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6b023 sd a0,0(a3) + 80000110: 08b6b72f amoswap.d a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71263 bne a4,t4,80000160 <fail> + +0000000080000120 <test_3>: + 80000120: 0006b783 ld a5,0(a3) + 80000124: 80000e93 li t4,-2048 + 80000128: 00300193 li gp,3 + 8000012c: 03d79a63 bne a5,t4,80000160 <fail> + +0000000080000130 <test_4>: + 80000130: 0010059b addiw a1,zero,1 + 80000134: 01f59593 slli a1,a1,0x1f + 80000138: 08b6b72f amoswap.d a4,a1,(a3) + 8000013c: 80000e93 li t4,-2048 + 80000140: 00400193 li gp,4 + 80000144: 01d71e63 bne a4,t4,80000160 <fail> + +0000000080000148 <test_5>: + 80000148: 0006b783 ld a5,0(a3) + 8000014c: 00100e9b addiw t4,zero,1 + 80000150: 01fe9e93 slli t4,t4,0x1f + 80000154: 00500193 li gp,5 + 80000158: 01d79463 bne a5,t4,80000160 <fail> + 8000015c: 00301c63 bne zero,gp,80000174 <pass> + +0000000080000160 <fail>: + 80000160: 0ff0000f fence + 80000164: 00018063 beqz gp,80000164 <fail+0x4> + 80000168: 00119193 slli gp,gp,0x1 + 8000016c: 0011e193 ori gp,gp,1 + 80000170: 00000073 ecall + +0000000080000174 <pass>: + 80000174: 0ff0000f fence + 80000178: 00100193 li gp,1 + 8000017c: 00000073 ecall + 80000180: c0001073 unimp diff --git a/test/riscv/tests/rv64ua-p-amoswap_d.elf b/test/riscv/tests/rv64ua-p-amoswap_d.elf Binary files differnew file mode 100755 index 00000000..642c648d --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoswap_d.elf diff --git a/test/riscv/tests/rv64ua-p-amoswap_w.dump b/test/riscv/tests/rv64ua-p-amoswap_w.dump new file mode 100644 index 00000000..e43f3820 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoswap_w.dump @@ -0,0 +1,125 @@ + +rv64ua-p-amoswap_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6a023 sw a0,0(a3) + 80000110: 08b6a72f amoswap.w a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71063 bne a4,t4,8000015c <fail> + +0000000080000120 <test_3>: + 80000120: 0006a783 lw a5,0(a3) + 80000124: 80000e93 li t4,-2048 + 80000128: 00300193 li gp,3 + 8000012c: 03d79863 bne a5,t4,8000015c <fail> + +0000000080000130 <test_4>: + 80000130: 0010059b addiw a1,zero,1 + 80000134: 01f59593 slli a1,a1,0x1f + 80000138: 08b6a72f amoswap.w a4,a1,(a3) + 8000013c: 80000e93 li t4,-2048 + 80000140: 00400193 li gp,4 + 80000144: 01d71c63 bne a4,t4,8000015c <fail> + +0000000080000148 <test_5>: + 80000148: 0006a783 lw a5,0(a3) + 8000014c: 80000eb7 lui t4,0x80000 + 80000150: 00500193 li gp,5 + 80000154: 01d79463 bne a5,t4,8000015c <fail> + 80000158: 00301c63 bne zero,gp,80000170 <pass> + +000000008000015c <fail>: + 8000015c: 0ff0000f fence + 80000160: 00018063 beqz gp,80000160 <fail+0x4> + 80000164: 00119193 slli gp,gp,0x1 + 80000168: 0011e193 ori gp,gp,1 + 8000016c: 00000073 ecall + +0000000080000170 <pass>: + 80000170: 0ff0000f fence + 80000174: 00100193 li gp,1 + 80000178: 00000073 ecall + 8000017c: c0001073 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoswap_w.elf b/test/riscv/tests/rv64ua-p-amoswap_w.elf Binary files differnew file mode 100755 index 00000000..e0b9e58e --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoswap_w.elf diff --git a/test/riscv/tests/rv64ua-p-amoxor_d.dump b/test/riscv/tests/rv64ua-p-amoxor_d.dump new file mode 100644 index 00000000..992a22e1 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoxor_d.dump @@ -0,0 +1,155 @@ + +rv64ua-p-amoxor_d: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6b023 sd a0,0(a3) + 80000110: 20b6b72f amoxor.d a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71463 bne a4,t4,80000164 <fail> + +0000000080000120 <test_3>: + 80000120: 0006b783 ld a5,0(a3) + 80000124: 80000eb7 lui t4,0x80000 + 80000128: 800e8e9b addiw t4,t4,-2048 + 8000012c: 00300193 li gp,3 + 80000130: 03d79a63 bne a5,t4,80000164 <fail> + +0000000080000134 <test_4>: + 80000134: 00100593 li a1,1 + 80000138: 20b6b72f amoxor.d a4,a1,(a3) + 8000013c: 80000eb7 lui t4,0x80000 + 80000140: 800e8e9b addiw t4,t4,-2048 + 80000144: 00400193 li gp,4 + 80000148: 01d71e63 bne a4,t4,80000164 <fail> + +000000008000014c <test_5>: + 8000014c: 0006b783 ld a5,0(a3) + 80000150: 80000eb7 lui t4,0x80000 + 80000154: 801e8e9b addiw t4,t4,-2047 + 80000158: 00500193 li gp,5 + 8000015c: 01d79463 bne a5,t4,80000164 <fail> + 80000160: 00301c63 bne zero,gp,80000178 <pass> + +0000000080000164 <fail>: + 80000164: 0ff0000f fence + 80000168: 00018063 beqz gp,80000168 <fail+0x4> + 8000016c: 00119193 slli gp,gp,0x1 + 80000170: 0011e193 ori gp,gp,1 + 80000174: 00000073 ecall + +0000000080000178 <pass>: + 80000178: 0ff0000f fence + 8000017c: 00100193 li gp,1 + 80000180: 00000073 ecall + 80000184: c0001073 unimp + 80000188: 0000 unimp + 8000018a: 0000 unimp + 8000018c: 0000 unimp + 8000018e: 0000 unimp + 80000190: 0000 unimp + 80000192: 0000 unimp + 80000194: 0000 unimp + 80000196: 0000 unimp + 80000198: 0000 unimp + 8000019a: 0000 unimp + 8000019c: 0000 unimp + 8000019e: 0000 unimp + 800001a0: 0000 unimp + 800001a2: 0000 unimp + 800001a4: 0000 unimp + 800001a6: 0000 unimp + 800001a8: 0000 unimp + 800001aa: 0000 unimp + 800001ac: 0000 unimp + 800001ae: 0000 unimp + 800001b0: 0000 unimp + 800001b2: 0000 unimp + 800001b4: 0000 unimp + 800001b6: 0000 unimp + 800001b8: 0000 unimp + 800001ba: 0000 unimp + 800001bc: 0000 unimp + 800001be: 0000 unimp + 800001c0: 0000 unimp + 800001c2: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoxor_d.elf b/test/riscv/tests/rv64ua-p-amoxor_d.elf Binary files differnew file mode 100755 index 00000000..a04e1f1c --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoxor_d.elf diff --git a/test/riscv/tests/rv64ua-p-amoxor_w.dump b/test/riscv/tests/rv64ua-p-amoxor_w.dump new file mode 100644 index 00000000..6bca3f65 --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoxor_w.dump @@ -0,0 +1,153 @@ + +rv64ua-p-amoxor_w: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 80000537 lui a0,0x80000 + 80000100: 80000593 li a1,-2048 + 80000104: 00002697 auipc a3,0x2 + 80000108: efc68693 addi a3,a3,-260 # 80002000 <begin_signature> + 8000010c: 00a6a023 sw a0,0(a3) + 80000110: 20b6a72f amoxor.w a4,a1,(a3) + 80000114: 80000eb7 lui t4,0x80000 + 80000118: 00200193 li gp,2 + 8000011c: 05d71863 bne a4,t4,8000016c <fail> + +0000000080000120 <test_3>: + 80000120: 0006a783 lw a5,0(a3) + 80000124: 80000eb7 lui t4,0x80000 + 80000128: 800e8e9b addiw t4,t4,-2048 + 8000012c: 00300193 li gp,3 + 80000130: 03d79e63 bne a5,t4,8000016c <fail> + +0000000080000134 <test_4>: + 80000134: 0030059b addiw a1,zero,3 + 80000138: 01e59593 slli a1,a1,0x1e + 8000013c: 00158593 addi a1,a1,1 + 80000140: 20b6a72f amoxor.w a4,a1,(a3) + 80000144: 80000eb7 lui t4,0x80000 + 80000148: 800e8e9b addiw t4,t4,-2048 + 8000014c: 00400193 li gp,4 + 80000150: 01d71e63 bne a4,t4,8000016c <fail> + +0000000080000154 <test_5>: + 80000154: 0006a783 lw a5,0(a3) + 80000158: c0000eb7 lui t4,0xc0000 + 8000015c: 801e8e9b addiw t4,t4,-2047 + 80000160: 00500193 li gp,5 + 80000164: 01d79463 bne a5,t4,8000016c <fail> + 80000168: 00301c63 bne zero,gp,80000180 <pass> + +000000008000016c <fail>: + 8000016c: 0ff0000f fence + 80000170: 00018063 beqz gp,80000170 <fail+0x4> + 80000174: 00119193 slli gp,gp,0x1 + 80000178: 0011e193 ori gp,gp,1 + 8000017c: 00000073 ecall + +0000000080000180 <pass>: + 80000180: 0ff0000f fence + 80000184: 00100193 li gp,1 + 80000188: 00000073 ecall + 8000018c: c0001073 unimp + 80000190: 0000 unimp + 80000192: 0000 unimp + 80000194: 0000 unimp + 80000196: 0000 unimp + 80000198: 0000 unimp + 8000019a: 0000 unimp + 8000019c: 0000 unimp + 8000019e: 0000 unimp + 800001a0: 0000 unimp + 800001a2: 0000 unimp + 800001a4: 0000 unimp + 800001a6: 0000 unimp + 800001a8: 0000 unimp + 800001aa: 0000 unimp + 800001ac: 0000 unimp + 800001ae: 0000 unimp + 800001b0: 0000 unimp + 800001b2: 0000 unimp + 800001b4: 0000 unimp + 800001b6: 0000 unimp + 800001b8: 0000 unimp + 800001ba: 0000 unimp + 800001bc: 0000 unimp + 800001be: 0000 unimp + 800001c0: 0000 unimp + 800001c2: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-amoxor_w.elf b/test/riscv/tests/rv64ua-p-amoxor_w.elf Binary files differnew file mode 100755 index 00000000..fc27683f --- /dev/null +++ b/test/riscv/tests/rv64ua-p-amoxor_w.elf diff --git a/test/riscv/tests/rv64ua-p-lrsc.dump b/test/riscv/tests/rv64ua-p-lrsc.dump new file mode 100644 index 00000000..4aec511e --- /dev/null +++ b/test/riscv/tests/rv64ua-p-lrsc.dump @@ -0,0 +1,178 @@ + +rv64ua-p-lrsc: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <reset_vector+0xb0> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + 800000fc: 00002517 auipc a0,0x2 + 80000100: f0450513 addi a0,a0,-252 # 80002000 <begin_signature> + 80000104: 00100593 li a1,1 + 80000108: 00b5262f amoadd.w a2,a1,(a0) + 8000010c: 00100693 li a3,1 + 80000110: fed67ee3 bleu a3,a2,8000010c <reset_vector+0xc0> + 80000114: 00052583 lw a1,0(a0) + 80000118: fed5eee3 bltu a1,a3,80000114 <reset_vector+0xc8> + +000000008000011c <test_2>: + 8000011c: 00002517 auipc a0,0x2 + 80000120: eec50513 addi a0,a0,-276 # 80002008 <foo> + 80000124: 1805272f sc.w a4,zero,(a0) + 80000128: 00100e93 li t4,1 + 8000012c: 00200193 li gp,2 + 80000130: 09d71863 bne a4,t4,800001c0 <fail> + +0000000080000134 <test_3>: + 80000134: 00002517 auipc a0,0x2 + 80000138: ed450513 addi a0,a0,-300 # 80002008 <foo> + 8000013c: 40050593 addi a1,a0,1024 + 80000140: 1005a5af lr.w a1,(a1) + 80000144: 18b5272f sc.w a4,a1,(a0) + 80000148: 00100e93 li t4,1 + 8000014c: 00300193 li gp,3 + 80000150: 07d71863 bne a4,t4,800001c0 <fail> + 80000154: 00002517 auipc a0,0x2 + 80000158: eb450513 addi a0,a0,-332 # 80002008 <foo> + 8000015c: 40000593 li a1,1024 + 80000160: 00160613 addi a2,a2,1 + 80000164: 1005272f lr.w a4,(a0) + 80000168: 00c70733 add a4,a4,a2 + 8000016c: 18e5272f sc.w a4,a4,(a0) + 80000170: fe071ae3 bnez a4,80000164 <test_3+0x30> + 80000174: fff58593 addi a1,a1,-1 + 80000178: fe0596e3 bnez a1,80000164 <test_3+0x30> + 8000017c: 00002517 auipc a0,0x2 + 80000180: e8850513 addi a0,a0,-376 # 80002004 <barrier> + 80000184: 00100593 li a1,1 + 80000188: 00b5202f amoadd.w zero,a1,(a0) + 8000018c: 00052583 lw a1,0(a0) + 80000190: fed5cee3 blt a1,a3,8000018c <test_3+0x58> + 80000194: 0ff0000f fence + +0000000080000198 <test_4>: + 80000198: 00002517 auipc a0,0x2 + 8000019c: e7052503 lw a0,-400(a0) # 80002008 <foo> + 800001a0: 00969593 slli a1,a3,0x9 + 800001a4: 40b50533 sub a0,a0,a1 + 800001a8: fff68693 addi a3,a3,-1 + 800001ac: fe06dce3 bgez a3,800001a4 <test_4+0xc> + 800001b0: 00000e93 li t4,0 + 800001b4: 00400193 li gp,4 + 800001b8: 01d51463 bne a0,t4,800001c0 <fail> + 800001bc: 00301c63 bne zero,gp,800001d4 <pass> + +00000000800001c0 <fail>: + 800001c0: 0ff0000f fence + 800001c4: 00018063 beqz gp,800001c4 <fail+0x4> + 800001c8: 00119193 slli gp,gp,0x1 + 800001cc: 0011e193 ori gp,gp,1 + 800001d0: 00000073 ecall + +00000000800001d4 <pass>: + 800001d4: 0ff0000f fence + 800001d8: 00100193 li gp,1 + 800001dc: 00000073 ecall + 800001e0: c0001073 unimp + 800001e4: 0000 unimp + 800001e6: 0000 unimp + 800001e8: 0000 unimp + 800001ea: 0000 unimp + 800001ec: 0000 unimp + 800001ee: 0000 unimp + 800001f0: 0000 unimp + 800001f2: 0000 unimp + 800001f4: 0000 unimp + 800001f6: 0000 unimp + 800001f8: 0000 unimp + 800001fa: 0000 unimp + 800001fc: 0000 unimp + 800001fe: 0000 unimp + 80000200: 0000 unimp + 80000202: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: 0000 unimp + 80002002: 0000 unimp + +0000000080002004 <barrier>: + 80002004: 0000 unimp + 80002006: 0000 unimp + +0000000080002008 <foo>: + 80002008: 0000 unimp + 8000200a: 0000 unimp + 8000200c: 0000 unimp + 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64ua-p-lrsc.elf b/test/riscv/tests/rv64ua-p-lrsc.elf Binary files differnew file mode 100755 index 00000000..f9b7fc2e --- /dev/null +++ b/test/riscv/tests/rv64ua-p-lrsc.elf diff --git a/test/riscv/tests/rv64uc-p-rvc.dump b/test/riscv/tests/rv64uc-p-rvc.dump new file mode 100644 index 00000000..616e38fe --- /dev/null +++ b/test/riscv/tests/rv64uc-p-rvc.dump @@ -0,0 +1,4878 @@ + +rv64uc-p-rvc: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00003f17 auipc t5,0x3 + 80000044: fc3f2023 sw gp,-64(t5) # 80003000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <reset_vector+0xb0> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + 800000fc: 00200193 li gp,2 + 80000100: 29a00593 li a1,666 + +0000000080000104 <test_2>: + 80000104: 6fb0106f j 80001ffe <data+0x1ef6> + +0000000080000108 <data>: + 80000108: 3210 fld fa2,32(a2) + 8000010a: 7654 ld a3,168(a2) + 8000010c: ba98 fsd fa4,48(a3) + 8000010e: fedc sd a5,184(a3) + 80000110: 3210 fld fa2,32(a2) + 80000112: 7654 ld a3,168(a2) + 80000114: ba98 fsd fa4,48(a3) + 80000116: fedc sd a5,184(a3) + 80000118: 00000013 nop + 8000011c: 00000013 nop + 80000120: 00000013 nop + 80000124: 00000013 nop + 80000128: 00000013 nop + 8000012c: 00000013 nop + 80000130: 00000013 nop + 80000134: 00000013 nop + 80000138: 00000013 nop + 8000013c: 00000013 nop + 80000140: 00000013 nop + 80000144: 00000013 nop + 80000148: 00000013 nop + 8000014c: 00000013 nop + 80000150: 00000013 nop + 80000154: 00000013 nop + 80000158: 00000013 nop + 8000015c: 00000013 nop + 80000160: 00000013 nop + 80000164: 00000013 nop + 80000168: 00000013 nop + 8000016c: 00000013 nop + 80000170: 00000013 nop + 80000174: 00000013 nop + 80000178: 00000013 nop + 8000017c: 00000013 nop + 80000180: 00000013 nop + 80000184: 00000013 nop + 80000188: 00000013 nop + 8000018c: 00000013 nop + 80000190: 00000013 nop + 80000194: 00000013 nop + 80000198: 00000013 nop + 8000019c: 00000013 nop + 800001a0: 00000013 nop + 800001a4: 00000013 nop + 800001a8: 00000013 nop + 800001ac: 00000013 nop + 800001b0: 00000013 nop + 800001b4: 00000013 nop + 800001b8: 00000013 nop + 800001bc: 00000013 nop + 800001c0: 00000013 nop + 800001c4: 00000013 nop + 800001c8: 00000013 nop + 800001cc: 00000013 nop + 800001d0: 00000013 nop + 800001d4: 00000013 nop + 800001d8: 00000013 nop + 800001dc: 00000013 nop + 800001e0: 00000013 nop + 800001e4: 00000013 nop + 800001e8: 00000013 nop + 800001ec: 00000013 nop + 800001f0: 00000013 nop + 800001f4: 00000013 nop + 800001f8: 00000013 nop + 800001fc: 00000013 nop + 80000200: 00000013 nop + 80000204: 00000013 nop + 80000208: 00000013 nop + 8000020c: 00000013 nop + 80000210: 00000013 nop + 80000214: 00000013 nop + 80000218: 00000013 nop + 8000021c: 00000013 nop + 80000220: 00000013 nop + 80000224: 00000013 nop + 80000228: 00000013 nop + 8000022c: 00000013 nop + 80000230: 00000013 nop + 80000234: 00000013 nop + 80000238: 00000013 nop + 8000023c: 00000013 nop + 80000240: 00000013 nop + 80000244: 00000013 nop + 80000248: 00000013 nop + 8000024c: 00000013 nop + 80000250: 00000013 nop + 80000254: 00000013 nop + 80000258: 00000013 nop + 8000025c: 00000013 nop + 80000260: 00000013 nop + 80000264: 00000013 nop + 80000268: 00000013 nop + 8000026c: 00000013 nop + 80000270: 00000013 nop + 80000274: 00000013 nop + 80000278: 00000013 nop + 8000027c: 00000013 nop + 80000280: 00000013 nop + 80000284: 00000013 nop + 80000288: 00000013 nop + 8000028c: 00000013 nop + 80000290: 00000013 nop + 80000294: 00000013 nop + 80000298: 00000013 nop + 8000029c: 00000013 nop + 800002a0: 00000013 nop + 800002a4: 00000013 nop + 800002a8: 00000013 nop + 800002ac: 00000013 nop + 800002b0: 00000013 nop + 800002b4: 00000013 nop + 800002b8: 00000013 nop + 800002bc: 00000013 nop + 800002c0: 00000013 nop + 800002c4: 00000013 nop + 800002c8: 00000013 nop + 800002cc: 00000013 nop + 800002d0: 00000013 nop + 800002d4: 00000013 nop + 800002d8: 00000013 nop + 800002dc: 00000013 nop + 800002e0: 00000013 nop + 800002e4: 00000013 nop + 800002e8: 00000013 nop + 800002ec: 00000013 nop + 800002f0: 00000013 nop + 800002f4: 00000013 nop + 800002f8: 00000013 nop + 800002fc: 00000013 nop + 80000300: 00000013 nop + 80000304: 00000013 nop + 80000308: 00000013 nop + 8000030c: 00000013 nop + 80000310: 00000013 nop + 80000314: 00000013 nop + 80000318: 00000013 nop + 8000031c: 00000013 nop + 80000320: 00000013 nop + 80000324: 00000013 nop + 80000328: 00000013 nop + 8000032c: 00000013 nop + 80000330: 00000013 nop + 80000334: 00000013 nop + 80000338: 00000013 nop + 8000033c: 00000013 nop + 80000340: 00000013 nop + 80000344: 00000013 nop + 80000348: 00000013 nop + 8000034c: 00000013 nop + 80000350: 00000013 nop + 80000354: 00000013 nop + 80000358: 00000013 nop + 8000035c: 00000013 nop + 80000360: 00000013 nop + 80000364: 00000013 nop + 80000368: 00000013 nop + 8000036c: 00000013 nop + 80000370: 00000013 nop + 80000374: 00000013 nop + 80000378: 00000013 nop + 8000037c: 00000013 nop + 80000380: 00000013 nop + 80000384: 00000013 nop + 80000388: 00000013 nop + 8000038c: 00000013 nop + 80000390: 00000013 nop + 80000394: 00000013 nop + 80000398: 00000013 nop + 8000039c: 00000013 nop + 800003a0: 00000013 nop + 800003a4: 00000013 nop + 800003a8: 00000013 nop + 800003ac: 00000013 nop + 800003b0: 00000013 nop + 800003b4: 00000013 nop + 800003b8: 00000013 nop + 800003bc: 00000013 nop + 800003c0: 00000013 nop + 800003c4: 00000013 nop + 800003c8: 00000013 nop + 800003cc: 00000013 nop + 800003d0: 00000013 nop + 800003d4: 00000013 nop + 800003d8: 00000013 nop + 800003dc: 00000013 nop + 800003e0: 00000013 nop + 800003e4: 00000013 nop + 800003e8: 00000013 nop + 800003ec: 00000013 nop + 800003f0: 00000013 nop + 800003f4: 00000013 nop + 800003f8: 00000013 nop + 800003fc: 00000013 nop + 80000400: 00000013 nop + 80000404: 00000013 nop + 80000408: 00000013 nop + 8000040c: 00000013 nop + 80000410: 00000013 nop + 80000414: 00000013 nop + 80000418: 00000013 nop + 8000041c: 00000013 nop + 80000420: 00000013 nop + 80000424: 00000013 nop + 80000428: 00000013 nop + 8000042c: 00000013 nop + 80000430: 00000013 nop + 80000434: 00000013 nop + 80000438: 00000013 nop + 8000043c: 00000013 nop + 80000440: 00000013 nop + 80000444: 00000013 nop + 80000448: 00000013 nop + 8000044c: 00000013 nop + 80000450: 00000013 nop + 80000454: 00000013 nop + 80000458: 00000013 nop + 8000045c: 00000013 nop + 80000460: 00000013 nop + 80000464: 00000013 nop + 80000468: 00000013 nop + 8000046c: 00000013 nop + 80000470: 00000013 nop + 80000474: 00000013 nop + 80000478: 00000013 nop + 8000047c: 00000013 nop + 80000480: 00000013 nop + 80000484: 00000013 nop + 80000488: 00000013 nop + 8000048c: 00000013 nop + 80000490: 00000013 nop + 80000494: 00000013 nop + 80000498: 00000013 nop + 8000049c: 00000013 nop + 800004a0: 00000013 nop + 800004a4: 00000013 nop + 800004a8: 00000013 nop + 800004ac: 00000013 nop + 800004b0: 00000013 nop + 800004b4: 00000013 nop + 800004b8: 00000013 nop + 800004bc: 00000013 nop + 800004c0: 00000013 nop + 800004c4: 00000013 nop + 800004c8: 00000013 nop + 800004cc: 00000013 nop + 800004d0: 00000013 nop + 800004d4: 00000013 nop + 800004d8: 00000013 nop + 800004dc: 00000013 nop + 800004e0: 00000013 nop + 800004e4: 00000013 nop + 800004e8: 00000013 nop + 800004ec: 00000013 nop + 800004f0: 00000013 nop + 800004f4: 00000013 nop + 800004f8: 00000013 nop + 800004fc: 00000013 nop + 80000500: 00000013 nop + 80000504: 00000013 nop + 80000508: 00000013 nop + 8000050c: 00000013 nop + 80000510: 00000013 nop + 80000514: 00000013 nop + 80000518: 00000013 nop + 8000051c: 00000013 nop + 80000520: 00000013 nop + 80000524: 00000013 nop + 80000528: 00000013 nop + 8000052c: 00000013 nop + 80000530: 00000013 nop + 80000534: 00000013 nop + 80000538: 00000013 nop + 8000053c: 00000013 nop + 80000540: 00000013 nop + 80000544: 00000013 nop + 80000548: 00000013 nop + 8000054c: 00000013 nop + 80000550: 00000013 nop + 80000554: 00000013 nop + 80000558: 00000013 nop + 8000055c: 00000013 nop + 80000560: 00000013 nop + 80000564: 00000013 nop + 80000568: 00000013 nop + 8000056c: 00000013 nop + 80000570: 00000013 nop + 80000574: 00000013 nop + 80000578: 00000013 nop + 8000057c: 00000013 nop + 80000580: 00000013 nop + 80000584: 00000013 nop + 80000588: 00000013 nop + 8000058c: 00000013 nop + 80000590: 00000013 nop + 80000594: 00000013 nop + 80000598: 00000013 nop + 8000059c: 00000013 nop + 800005a0: 00000013 nop + 800005a4: 00000013 nop + 800005a8: 00000013 nop + 800005ac: 00000013 nop + 800005b0: 00000013 nop + 800005b4: 00000013 nop + 800005b8: 00000013 nop + 800005bc: 00000013 nop + 800005c0: 00000013 nop + 800005c4: 00000013 nop + 800005c8: 00000013 nop + 800005cc: 00000013 nop + 800005d0: 00000013 nop + 800005d4: 00000013 nop + 800005d8: 00000013 nop + 800005dc: 00000013 nop + 800005e0: 00000013 nop + 800005e4: 00000013 nop + 800005e8: 00000013 nop + 800005ec: 00000013 nop + 800005f0: 00000013 nop + 800005f4: 00000013 nop + 800005f8: 00000013 nop + 800005fc: 00000013 nop + 80000600: 00000013 nop + 80000604: 00000013 nop + 80000608: 00000013 nop + 8000060c: 00000013 nop + 80000610: 00000013 nop + 80000614: 00000013 nop + 80000618: 00000013 nop + 8000061c: 00000013 nop + 80000620: 00000013 nop + 80000624: 00000013 nop + 80000628: 00000013 nop + 8000062c: 00000013 nop + 80000630: 00000013 nop + 80000634: 00000013 nop + 80000638: 00000013 nop + 8000063c: 00000013 nop + 80000640: 00000013 nop + 80000644: 00000013 nop + 80000648: 00000013 nop + 8000064c: 00000013 nop + 80000650: 00000013 nop + 80000654: 00000013 nop + 80000658: 00000013 nop + 8000065c: 00000013 nop + 80000660: 00000013 nop + 80000664: 00000013 nop + 80000668: 00000013 nop + 8000066c: 00000013 nop + 80000670: 00000013 nop + 80000674: 00000013 nop + 80000678: 00000013 nop + 8000067c: 00000013 nop + 80000680: 00000013 nop + 80000684: 00000013 nop + 80000688: 00000013 nop + 8000068c: 00000013 nop + 80000690: 00000013 nop + 80000694: 00000013 nop + 80000698: 00000013 nop + 8000069c: 00000013 nop + 800006a0: 00000013 nop + 800006a4: 00000013 nop + 800006a8: 00000013 nop + 800006ac: 00000013 nop + 800006b0: 00000013 nop + 800006b4: 00000013 nop + 800006b8: 00000013 nop + 800006bc: 00000013 nop + 800006c0: 00000013 nop + 800006c4: 00000013 nop + 800006c8: 00000013 nop + 800006cc: 00000013 nop + 800006d0: 00000013 nop + 800006d4: 00000013 nop + 800006d8: 00000013 nop + 800006dc: 00000013 nop + 800006e0: 00000013 nop + 800006e4: 00000013 nop + 800006e8: 00000013 nop + 800006ec: 00000013 nop + 800006f0: 00000013 nop + 800006f4: 00000013 nop + 800006f8: 00000013 nop + 800006fc: 00000013 nop + 80000700: 00000013 nop + 80000704: 00000013 nop + 80000708: 00000013 nop + 8000070c: 00000013 nop + 80000710: 00000013 nop + 80000714: 00000013 nop + 80000718: 00000013 nop + 8000071c: 00000013 nop + 80000720: 00000013 nop + 80000724: 00000013 nop + 80000728: 00000013 nop + 8000072c: 00000013 nop + 80000730: 00000013 nop + 80000734: 00000013 nop + 80000738: 00000013 nop + 8000073c: 00000013 nop + 80000740: 00000013 nop + 80000744: 00000013 nop + 80000748: 00000013 nop + 8000074c: 00000013 nop + 80000750: 00000013 nop + 80000754: 00000013 nop + 80000758: 00000013 nop + 8000075c: 00000013 nop + 80000760: 00000013 nop + 80000764: 00000013 nop + 80000768: 00000013 nop + 8000076c: 00000013 nop + 80000770: 00000013 nop + 80000774: 00000013 nop + 80000778: 00000013 nop + 8000077c: 00000013 nop + 80000780: 00000013 nop + 80000784: 00000013 nop + 80000788: 00000013 nop + 8000078c: 00000013 nop + 80000790: 00000013 nop + 80000794: 00000013 nop + 80000798: 00000013 nop + 8000079c: 00000013 nop + 800007a0: 00000013 nop + 800007a4: 00000013 nop + 800007a8: 00000013 nop + 800007ac: 00000013 nop + 800007b0: 00000013 nop + 800007b4: 00000013 nop + 800007b8: 00000013 nop + 800007bc: 00000013 nop + 800007c0: 00000013 nop + 800007c4: 00000013 nop + 800007c8: 00000013 nop + 800007cc: 00000013 nop + 800007d0: 00000013 nop + 800007d4: 00000013 nop + 800007d8: 00000013 nop + 800007dc: 00000013 nop + 800007e0: 00000013 nop + 800007e4: 00000013 nop + 800007e8: 00000013 nop + 800007ec: 00000013 nop + 800007f0: 00000013 nop + 800007f4: 00000013 nop + 800007f8: 00000013 nop + 800007fc: 00000013 nop + 80000800: 00000013 nop + 80000804: 00000013 nop + 80000808: 00000013 nop + 8000080c: 00000013 nop + 80000810: 00000013 nop + 80000814: 00000013 nop + 80000818: 00000013 nop + 8000081c: 00000013 nop + 80000820: 00000013 nop + 80000824: 00000013 nop + 80000828: 00000013 nop + 8000082c: 00000013 nop + 80000830: 00000013 nop + 80000834: 00000013 nop + 80000838: 00000013 nop + 8000083c: 00000013 nop + 80000840: 00000013 nop + 80000844: 00000013 nop + 80000848: 00000013 nop + 8000084c: 00000013 nop + 80000850: 00000013 nop + 80000854: 00000013 nop + 80000858: 00000013 nop + 8000085c: 00000013 nop + 80000860: 00000013 nop + 80000864: 00000013 nop + 80000868: 00000013 nop + 8000086c: 00000013 nop + 80000870: 00000013 nop + 80000874: 00000013 nop + 80000878: 00000013 nop + 8000087c: 00000013 nop + 80000880: 00000013 nop + 80000884: 00000013 nop + 80000888: 00000013 nop + 8000088c: 00000013 nop + 80000890: 00000013 nop + 80000894: 00000013 nop + 80000898: 00000013 nop + 8000089c: 00000013 nop + 800008a0: 00000013 nop + 800008a4: 00000013 nop + 800008a8: 00000013 nop + 800008ac: 00000013 nop + 800008b0: 00000013 nop + 800008b4: 00000013 nop + 800008b8: 00000013 nop + 800008bc: 00000013 nop + 800008c0: 00000013 nop + 800008c4: 00000013 nop + 800008c8: 00000013 nop + 800008cc: 00000013 nop + 800008d0: 00000013 nop + 800008d4: 00000013 nop + 800008d8: 00000013 nop + 800008dc: 00000013 nop + 800008e0: 00000013 nop + 800008e4: 00000013 nop + 800008e8: 00000013 nop + 800008ec: 00000013 nop + 800008f0: 00000013 nop + 800008f4: 00000013 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nop + 80000998: 00000013 nop + 8000099c: 00000013 nop + 800009a0: 00000013 nop + 800009a4: 00000013 nop + 800009a8: 00000013 nop + 800009ac: 00000013 nop + 800009b0: 00000013 nop + 800009b4: 00000013 nop + 800009b8: 00000013 nop + 800009bc: 00000013 nop + 800009c0: 00000013 nop + 800009c4: 00000013 nop + 800009c8: 00000013 nop + 800009cc: 00000013 nop + 800009d0: 00000013 nop + 800009d4: 00000013 nop + 800009d8: 00000013 nop + 800009dc: 00000013 nop + 800009e0: 00000013 nop + 800009e4: 00000013 nop + 800009e8: 00000013 nop + 800009ec: 00000013 nop + 800009f0: 00000013 nop + 800009f4: 00000013 nop + 800009f8: 00000013 nop + 800009fc: 00000013 nop + 80000a00: 00000013 nop + 80000a04: 00000013 nop + 80000a08: 00000013 nop + 80000a0c: 00000013 nop + 80000a10: 00000013 nop + 80000a14: 00000013 nop + 80000a18: 00000013 nop + 80000a1c: 00000013 nop + 80000a20: 00000013 nop + 80000a24: 00000013 nop + 80000a28: 00000013 nop + 80000a2c: 00000013 nop + 80000a30: 00000013 nop + 80000a34: 00000013 nop + 80000a38: 00000013 nop + 80000a3c: 00000013 nop + 80000a40: 00000013 nop + 80000a44: 00000013 nop + 80000a48: 00000013 nop + 80000a4c: 00000013 nop + 80000a50: 00000013 nop + 80000a54: 00000013 nop + 80000a58: 00000013 nop + 80000a5c: 00000013 nop + 80000a60: 00000013 nop + 80000a64: 00000013 nop + 80000a68: 00000013 nop + 80000a6c: 00000013 nop + 80000a70: 00000013 nop + 80000a74: 00000013 nop + 80000a78: 00000013 nop + 80000a7c: 00000013 nop + 80000a80: 00000013 nop + 80000a84: 00000013 nop + 80000a88: 00000013 nop + 80000a8c: 00000013 nop + 80000a90: 00000013 nop + 80000a94: 00000013 nop + 80000a98: 00000013 nop + 80000a9c: 00000013 nop + 80000aa0: 00000013 nop + 80000aa4: 00000013 nop + 80000aa8: 00000013 nop + 80000aac: 00000013 nop + 80000ab0: 00000013 nop + 80000ab4: 00000013 nop + 80000ab8: 00000013 nop + 80000abc: 00000013 nop + 80000ac0: 00000013 nop + 80000ac4: 00000013 nop + 80000ac8: 00000013 nop + 80000acc: 00000013 nop + 80000ad0: 00000013 nop + 80000ad4: 00000013 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nop + 80000b78: 00000013 nop + 80000b7c: 00000013 nop + 80000b80: 00000013 nop + 80000b84: 00000013 nop + 80000b88: 00000013 nop + 80000b8c: 00000013 nop + 80000b90: 00000013 nop + 80000b94: 00000013 nop + 80000b98: 00000013 nop + 80000b9c: 00000013 nop + 80000ba0: 00000013 nop + 80000ba4: 00000013 nop + 80000ba8: 00000013 nop + 80000bac: 00000013 nop + 80000bb0: 00000013 nop + 80000bb4: 00000013 nop + 80000bb8: 00000013 nop + 80000bbc: 00000013 nop + 80000bc0: 00000013 nop + 80000bc4: 00000013 nop + 80000bc8: 00000013 nop + 80000bcc: 00000013 nop + 80000bd0: 00000013 nop + 80000bd4: 00000013 nop + 80000bd8: 00000013 nop + 80000bdc: 00000013 nop + 80000be0: 00000013 nop + 80000be4: 00000013 nop + 80000be8: 00000013 nop + 80000bec: 00000013 nop + 80000bf0: 00000013 nop + 80000bf4: 00000013 nop + 80000bf8: 00000013 nop + 80000bfc: 00000013 nop + 80000c00: 00000013 nop + 80000c04: 00000013 nop + 80000c08: 00000013 nop + 80000c0c: 00000013 nop + 80000c10: 00000013 nop + 80000c14: 00000013 nop + 80000c18: 00000013 nop + 80000c1c: 00000013 nop + 80000c20: 00000013 nop + 80000c24: 00000013 nop + 80000c28: 00000013 nop + 80000c2c: 00000013 nop + 80000c30: 00000013 nop + 80000c34: 00000013 nop + 80000c38: 00000013 nop + 80000c3c: 00000013 nop + 80000c40: 00000013 nop + 80000c44: 00000013 nop + 80000c48: 00000013 nop + 80000c4c: 00000013 nop + 80000c50: 00000013 nop + 80000c54: 00000013 nop + 80000c58: 00000013 nop + 80000c5c: 00000013 nop + 80000c60: 00000013 nop + 80000c64: 00000013 nop + 80000c68: 00000013 nop + 80000c6c: 00000013 nop + 80000c70: 00000013 nop + 80000c74: 00000013 nop + 80000c78: 00000013 nop + 80000c7c: 00000013 nop + 80000c80: 00000013 nop + 80000c84: 00000013 nop + 80000c88: 00000013 nop + 80000c8c: 00000013 nop + 80000c90: 00000013 nop + 80000c94: 00000013 nop + 80000c98: 00000013 nop + 80000c9c: 00000013 nop + 80000ca0: 00000013 nop + 80000ca4: 00000013 nop + 80000ca8: 00000013 nop + 80000cac: 00000013 nop + 80000cb0: 00000013 nop + 80000cb4: 00000013 nop + 80000cb8: 00000013 nop + 80000cbc: 00000013 nop + 80000cc0: 00000013 nop + 80000cc4: 00000013 nop + 80000cc8: 00000013 nop + 80000ccc: 00000013 nop + 80000cd0: 00000013 nop + 80000cd4: 00000013 nop + 80000cd8: 00000013 nop + 80000cdc: 00000013 nop + 80000ce0: 00000013 nop + 80000ce4: 00000013 nop + 80000ce8: 00000013 nop + 80000cec: 00000013 nop + 80000cf0: 00000013 nop + 80000cf4: 00000013 nop + 80000cf8: 00000013 nop + 80000cfc: 00000013 nop + 80000d00: 00000013 nop + 80000d04: 00000013 nop + 80000d08: 00000013 nop + 80000d0c: 00000013 nop + 80000d10: 00000013 nop + 80000d14: 00000013 nop + 80000d18: 00000013 nop + 80000d1c: 00000013 nop + 80000d20: 00000013 nop + 80000d24: 00000013 nop + 80000d28: 00000013 nop + 80000d2c: 00000013 nop + 80000d30: 00000013 nop + 80000d34: 00000013 nop + 80000d38: 00000013 nop + 80000d3c: 00000013 nop + 80000d40: 00000013 nop + 80000d44: 00000013 nop + 80000d48: 00000013 nop + 80000d4c: 00000013 nop + 80000d50: 00000013 nop + 80000d54: 00000013 nop + 80000d58: 00000013 nop + 80000d5c: 00000013 nop + 80000d60: 00000013 nop + 80000d64: 00000013 nop + 80000d68: 00000013 nop + 80000d6c: 00000013 nop + 80000d70: 00000013 nop + 80000d74: 00000013 nop + 80000d78: 00000013 nop + 80000d7c: 00000013 nop + 80000d80: 00000013 nop + 80000d84: 00000013 nop + 80000d88: 00000013 nop + 80000d8c: 00000013 nop + 80000d90: 00000013 nop + 80000d94: 00000013 nop + 80000d98: 00000013 nop + 80000d9c: 00000013 nop + 80000da0: 00000013 nop + 80000da4: 00000013 nop + 80000da8: 00000013 nop + 80000dac: 00000013 nop + 80000db0: 00000013 nop + 80000db4: 00000013 nop + 80000db8: 00000013 nop + 80000dbc: 00000013 nop + 80000dc0: 00000013 nop + 80000dc4: 00000013 nop + 80000dc8: 00000013 nop + 80000dcc: 00000013 nop + 80000dd0: 00000013 nop + 80000dd4: 00000013 nop + 80000dd8: 00000013 nop + 80000ddc: 00000013 nop + 80000de0: 00000013 nop + 80000de4: 00000013 nop + 80000de8: 00000013 nop + 80000dec: 00000013 nop + 80000df0: 00000013 nop + 80000df4: 00000013 nop + 80000df8: 00000013 nop + 80000dfc: 00000013 nop + 80000e00: 00000013 nop + 80000e04: 00000013 nop + 80000e08: 00000013 nop + 80000e0c: 00000013 nop + 80000e10: 00000013 nop + 80000e14: 00000013 nop + 80000e18: 00000013 nop + 80000e1c: 00000013 nop + 80000e20: 00000013 nop + 80000e24: 00000013 nop + 80000e28: 00000013 nop + 80000e2c: 00000013 nop + 80000e30: 00000013 nop + 80000e34: 00000013 nop + 80000e38: 00000013 nop + 80000e3c: 00000013 nop + 80000e40: 00000013 nop + 80000e44: 00000013 nop + 80000e48: 00000013 nop + 80000e4c: 00000013 nop + 80000e50: 00000013 nop + 80000e54: 00000013 nop + 80000e58: 00000013 nop + 80000e5c: 00000013 nop + 80000e60: 00000013 nop + 80000e64: 00000013 nop + 80000e68: 00000013 nop + 80000e6c: 00000013 nop + 80000e70: 00000013 nop + 80000e74: 00000013 nop + 80000e78: 00000013 nop + 80000e7c: 00000013 nop + 80000e80: 00000013 nop + 80000e84: 00000013 nop + 80000e88: 00000013 nop + 80000e8c: 00000013 nop + 80000e90: 00000013 nop + 80000e94: 00000013 nop + 80000e98: 00000013 nop + 80000e9c: 00000013 nop + 80000ea0: 00000013 nop + 80000ea4: 00000013 nop + 80000ea8: 00000013 nop + 80000eac: 00000013 nop + 80000eb0: 00000013 nop + 80000eb4: 00000013 nop + 80000eb8: 00000013 nop + 80000ebc: 00000013 nop + 80000ec0: 00000013 nop + 80000ec4: 00000013 nop + 80000ec8: 00000013 nop + 80000ecc: 00000013 nop + 80000ed0: 00000013 nop + 80000ed4: 00000013 nop + 80000ed8: 00000013 nop + 80000edc: 00000013 nop + 80000ee0: 00000013 nop + 80000ee4: 00000013 nop + 80000ee8: 00000013 nop + 80000eec: 00000013 nop + 80000ef0: 00000013 nop + 80000ef4: 00000013 nop + 80000ef8: 00000013 nop + 80000efc: 00000013 nop + 80000f00: 00000013 nop + 80000f04: 00000013 nop + 80000f08: 00000013 nop + 80000f0c: 00000013 nop + 80000f10: 00000013 nop + 80000f14: 00000013 nop + 80000f18: 00000013 nop + 80000f1c: 00000013 nop + 80000f20: 00000013 nop + 80000f24: 00000013 nop + 80000f28: 00000013 nop + 80000f2c: 00000013 nop + 80000f30: 00000013 nop + 80000f34: 00000013 nop + 80000f38: 00000013 nop + 80000f3c: 00000013 nop + 80000f40: 00000013 nop + 80000f44: 00000013 nop + 80000f48: 00000013 nop + 80000f4c: 00000013 nop + 80000f50: 00000013 nop + 80000f54: 00000013 nop + 80000f58: 00000013 nop + 80000f5c: 00000013 nop + 80000f60: 00000013 nop + 80000f64: 00000013 nop + 80000f68: 00000013 nop + 80000f6c: 00000013 nop + 80000f70: 00000013 nop + 80000f74: 00000013 nop + 80000f78: 00000013 nop + 80000f7c: 00000013 nop + 80000f80: 00000013 nop + 80000f84: 00000013 nop + 80000f88: 00000013 nop + 80000f8c: 00000013 nop + 80000f90: 00000013 nop + 80000f94: 00000013 nop + 80000f98: 00000013 nop + 80000f9c: 00000013 nop + 80000fa0: 00000013 nop + 80000fa4: 00000013 nop + 80000fa8: 00000013 nop + 80000fac: 00000013 nop + 80000fb0: 00000013 nop + 80000fb4: 00000013 nop + 80000fb8: 00000013 nop + 80000fbc: 00000013 nop + 80000fc0: 00000013 nop + 80000fc4: 00000013 nop + 80000fc8: 00000013 nop + 80000fcc: 00000013 nop + 80000fd0: 00000013 nop + 80000fd4: 00000013 nop + 80000fd8: 00000013 nop + 80000fdc: 00000013 nop + 80000fe0: 00000013 nop + 80000fe4: 00000013 nop + 80000fe8: 00000013 nop + 80000fec: 00000013 nop + 80000ff0: 00000013 nop + 80000ff4: 00000013 nop + 80000ff8: 00000013 nop + 80000ffc: 00000013 nop + 80001000: 0000 unimp + 80001002: 0000 unimp + 80001004: 0000 unimp + 80001006: 0000 unimp + 80001008: 0000 unimp + 8000100a: 0000 unimp + 8000100c: 0000 unimp + 8000100e: 0000 unimp + 80001010: 0000 unimp + 80001012: 0000 unimp + 80001014: 0000 unimp + 80001016: 0000 unimp + 80001018: 0000 unimp + 8000101a: 0000 unimp + 8000101c: 0000 unimp + 8000101e: 0000 unimp + 80001020: 0000 unimp + 80001022: 0000 unimp + 80001024: 0000 unimp + 80001026: 0000 unimp + 80001028: 0000 unimp + 8000102a: 0000 unimp + 8000102c: 0000 unimp + 8000102e: 0000 unimp + 80001030: 0000 unimp + 80001032: 0000 unimp + 80001034: 0000 unimp + 80001036: 0000 unimp + 80001038: 0000 unimp + 8000103a: 0000 unimp + 8000103c: 0000 unimp + 8000103e: 0000 unimp + 80001040: 0000 unimp + 80001042: 0000 unimp + 80001044: 0000 unimp + 80001046: 0000 unimp + 80001048: 0000 unimp + 8000104a: 0000 unimp + 8000104c: 0000 unimp + 8000104e: 0000 unimp + 80001050: 0000 unimp + 80001052: 0000 unimp + 80001054: 0000 unimp + 80001056: 0000 unimp + 80001058: 0000 unimp + 8000105a: 0000 unimp + 8000105c: 0000 unimp + 8000105e: 0000 unimp + 80001060: 0000 unimp + 80001062: 0000 unimp + 80001064: 0000 unimp + 80001066: 0000 unimp + 80001068: 0000 unimp + 8000106a: 0000 unimp + 8000106c: 0000 unimp + 8000106e: 0000 unimp + 80001070: 0000 unimp + 80001072: 0000 unimp + 80001074: 0000 unimp + 80001076: 0000 unimp + 80001078: 0000 unimp + 8000107a: 0000 unimp + 8000107c: 0000 unimp + 8000107e: 0000 unimp + 80001080: 0000 unimp + 80001082: 0000 unimp + 80001084: 0000 unimp + 80001086: 0000 unimp + 80001088: 0000 unimp + 8000108a: 0000 unimp + 8000108c: 0000 unimp + 8000108e: 0000 unimp + 80001090: 0000 unimp + 80001092: 0000 unimp + 80001094: 0000 unimp + 80001096: 0000 unimp + 80001098: 0000 unimp + 8000109a: 0000 unimp + 8000109c: 0000 unimp + 8000109e: 0000 unimp + 800010a0: 0000 unimp + 800010a2: 0000 unimp + 800010a4: 0000 unimp + 800010a6: 0000 unimp + 800010a8: 0000 unimp + 800010aa: 0000 unimp + 800010ac: 0000 unimp + 800010ae: 0000 unimp + 800010b0: 0000 unimp + 800010b2: 0000 unimp + 800010b4: 0000 unimp + 800010b6: 0000 unimp + 800010b8: 0000 unimp + 800010ba: 0000 unimp + 800010bc: 0000 unimp + 800010be: 0000 unimp + 800010c0: 0000 unimp + 800010c2: 0000 unimp + 800010c4: 0000 unimp + 800010c6: 0000 unimp + 800010c8: 0000 unimp + 800010ca: 0000 unimp + 800010cc: 0000 unimp + 800010ce: 0000 unimp + 800010d0: 0000 unimp + 800010d2: 0000 unimp + 800010d4: 0000 unimp + 800010d6: 0000 unimp + 800010d8: 0000 unimp + 800010da: 0000 unimp + 800010dc: 0000 unimp + 800010de: 0000 unimp + 800010e0: 0000 unimp + 800010e2: 0000 unimp + 800010e4: 0000 unimp + 800010e6: 0000 unimp + 800010e8: 0000 unimp + 800010ea: 0000 unimp + 800010ec: 0000 unimp + 800010ee: 0000 unimp + 800010f0: 0000 unimp + 800010f2: 0000 unimp + 800010f4: 0000 unimp + 800010f6: 0000 unimp + 800010f8: 0000 unimp + 800010fa: 0000 unimp + 800010fc: 0000 unimp + 800010fe: 0000 unimp + 80001100: 0000 unimp + 80001102: 0000 unimp + 80001104: 0000 unimp + 80001106: 0000 unimp + 80001108: 0000 unimp + 8000110a: 0000 unimp + 8000110c: 0000 unimp + 8000110e: 0000 unimp + 80001110: 0000 unimp + 80001112: 0000 unimp + 80001114: 0000 unimp + 80001116: 0000 unimp + 80001118: 0000 unimp + 8000111a: 0000 unimp + 8000111c: 0000 unimp + 8000111e: 0000 unimp + 80001120: 0000 unimp + 80001122: 0000 unimp + 80001124: 0000 unimp + 80001126: 0000 unimp + 80001128: 0000 unimp + 8000112a: 0000 unimp + 8000112c: 0000 unimp + 8000112e: 0000 unimp + 80001130: 0000 unimp + 80001132: 0000 unimp + 80001134: 0000 unimp + 80001136: 0000 unimp + 80001138: 0000 unimp + 8000113a: 0000 unimp + 8000113c: 0000 unimp + 8000113e: 0000 unimp + 80001140: 0000 unimp + 80001142: 0000 unimp + 80001144: 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+ 80001e86: 0000 unimp + 80001e88: 0000 unimp + 80001e8a: 0000 unimp + 80001e8c: 0000 unimp + 80001e8e: 0000 unimp + 80001e90: 0000 unimp + 80001e92: 0000 unimp + 80001e94: 0000 unimp + 80001e96: 0000 unimp + 80001e98: 0000 unimp + 80001e9a: 0000 unimp + 80001e9c: 0000 unimp + 80001e9e: 0000 unimp + 80001ea0: 0000 unimp + 80001ea2: 0000 unimp + 80001ea4: 0000 unimp + 80001ea6: 0000 unimp + 80001ea8: 0000 unimp + 80001eaa: 0000 unimp + 80001eac: 0000 unimp + 80001eae: 0000 unimp + 80001eb0: 0000 unimp + 80001eb2: 0000 unimp + 80001eb4: 0000 unimp + 80001eb6: 0000 unimp + 80001eb8: 0000 unimp + 80001eba: 0000 unimp + 80001ebc: 0000 unimp + 80001ebe: 0000 unimp + 80001ec0: 0000 unimp + 80001ec2: 0000 unimp + 80001ec4: 0000 unimp + 80001ec6: 0000 unimp + 80001ec8: 0000 unimp + 80001eca: 0000 unimp + 80001ecc: 0000 unimp + 80001ece: 0000 unimp + 80001ed0: 0000 unimp + 80001ed2: 0000 unimp + 80001ed4: 0000 unimp + 80001ed6: 0000 unimp + 80001ed8: 0000 unimp + 80001eda: 0000 unimp + 80001edc: 0000 unimp + 80001ede: 0000 unimp + 80001ee0: 0000 unimp + 80001ee2: 0000 unimp + 80001ee4: 0000 unimp + 80001ee6: 0000 unimp + 80001ee8: 0000 unimp + 80001eea: 0000 unimp + 80001eec: 0000 unimp + 80001eee: 0000 unimp + 80001ef0: 0000 unimp + 80001ef2: 0000 unimp + 80001ef4: 0000 unimp + 80001ef6: 0000 unimp + 80001ef8: 0000 unimp + 80001efa: 0000 unimp + 80001efc: 0000 unimp + 80001efe: 0000 unimp + 80001f00: 0000 unimp + 80001f02: 0000 unimp + 80001f04: 0000 unimp + 80001f06: 0000 unimp + 80001f08: 0000 unimp + 80001f0a: 0000 unimp + 80001f0c: 0000 unimp + 80001f0e: 0000 unimp + 80001f10: 0000 unimp + 80001f12: 0000 unimp + 80001f14: 0000 unimp + 80001f16: 0000 unimp + 80001f18: 0000 unimp + 80001f1a: 0000 unimp + 80001f1c: 0000 unimp + 80001f1e: 0000 unimp + 80001f20: 0000 unimp + 80001f22: 0000 unimp + 80001f24: 0000 unimp + 80001f26: 0000 unimp + 80001f28: 0000 unimp + 80001f2a: 0000 unimp + 80001f2c: 0000 unimp + 80001f2e: 0000 unimp + 80001f30: 0000 unimp + 80001f32: 0000 unimp + 80001f34: 0000 unimp + 80001f36: 0000 unimp + 80001f38: 0000 unimp + 80001f3a: 0000 unimp + 80001f3c: 0000 unimp + 80001f3e: 0000 unimp + 80001f40: 0000 unimp + 80001f42: 0000 unimp + 80001f44: 0000 unimp + 80001f46: 0000 unimp + 80001f48: 0000 unimp + 80001f4a: 0000 unimp + 80001f4c: 0000 unimp + 80001f4e: 0000 unimp + 80001f50: 0000 unimp + 80001f52: 0000 unimp + 80001f54: 0000 unimp + 80001f56: 0000 unimp + 80001f58: 0000 unimp + 80001f5a: 0000 unimp + 80001f5c: 0000 unimp + 80001f5e: 0000 unimp + 80001f60: 0000 unimp + 80001f62: 0000 unimp + 80001f64: 0000 unimp + 80001f66: 0000 unimp + 80001f68: 0000 unimp + 80001f6a: 0000 unimp + 80001f6c: 0000 unimp + 80001f6e: 0000 unimp + 80001f70: 0000 unimp + 80001f72: 0000 unimp + 80001f74: 0000 unimp + 80001f76: 0000 unimp + 80001f78: 0000 unimp + 80001f7a: 0000 unimp + 80001f7c: 0000 unimp + 80001f7e: 0000 unimp + 80001f80: 0000 unimp + 80001f82: 0000 unimp + 80001f84: 0000 unimp + 80001f86: 0000 unimp + 80001f88: 0000 unimp + 80001f8a: 0000 unimp + 80001f8c: 0000 unimp + 80001f8e: 0000 unimp + 80001f90: 0000 unimp + 80001f92: 0000 unimp + 80001f94: 0000 unimp + 80001f96: 0000 unimp + 80001f98: 0000 unimp + 80001f9a: 0000 unimp + 80001f9c: 0000 unimp + 80001f9e: 0000 unimp + 80001fa0: 0000 unimp + 80001fa2: 0000 unimp + 80001fa4: 0000 unimp + 80001fa6: 0000 unimp + 80001fa8: 0000 unimp + 80001faa: 0000 unimp + 80001fac: 0000 unimp + 80001fae: 0000 unimp + 80001fb0: 0000 unimp + 80001fb2: 0000 unimp + 80001fb4: 0000 unimp + 80001fb6: 0000 unimp + 80001fb8: 0000 unimp + 80001fba: 0000 unimp + 80001fbc: 0000 unimp + 80001fbe: 0000 unimp + 80001fc0: 0000 unimp + 80001fc2: 0000 unimp + 80001fc4: 0000 unimp + 80001fc6: 0000 unimp + 80001fc8: 0000 unimp + 80001fca: 0000 unimp + 80001fcc: 0000 unimp + 80001fce: 0000 unimp + 80001fd0: 0000 unimp + 80001fd2: 0000 unimp + 80001fd4: 0000 unimp + 80001fd6: 0000 unimp + 80001fd8: 0000 unimp + 80001fda: 0000 unimp + 80001fdc: 0000 unimp + 80001fde: 0000 unimp + 80001fe0: 0000 unimp + 80001fe2: 0000 unimp + 80001fe4: 0000 unimp + 80001fe6: 0000 unimp + 80001fe8: 0000 unimp + 80001fea: 0000 unimp + 80001fec: 0000 unimp + 80001fee: 0000 unimp + 80001ff0: 0000 unimp + 80001ff2: 0000 unimp + 80001ff4: 0000 unimp + 80001ff6: 0000 unimp + 80001ff8: 0000 unimp + 80001ffa: 0000 unimp + 80001ffc: 0000 unimp + 80001ffe: 00158593 addi a1,a1,1 + 80002002: 29b00e93 li t4,667 + 80002006: 00200193 li gp,2 + 8000200a: 2dd59163 bne a1,t4,800022cc <fail> + 8000200e: 00001137 lui sp,0x1 + 80002012: 2341011b addiw sp,sp,564 + +0000000080002016 <test_3>: + 80002016: 1fe8 addi a0,sp,1020 + 80002018: 00001eb7 lui t4,0x1 + 8000201c: 630e8e9b addiw t4,t4,1584 + 80002020: 00300193 li gp,3 + 80002024: 2bd51463 bne a0,t4,800022cc <fail> + +0000000080002028 <test_4>: + 80002028: 617d addi sp,sp,496 + 8000202a: 0001 nop + 8000202c: 00001eb7 lui t4,0x1 + 80002030: 424e8e9b addiw t4,t4,1060 + 80002034: 00400193 li gp,4 + 80002038: 29d11a63 bne sp,t4,800022cc <fail> + +000000008000203c <test_5>: + 8000203c: 7101 addi sp,sp,-512 + 8000203e: 0001 nop + 80002040: 00001eb7 lui t4,0x1 + 80002044: 224e8e9b addiw t4,t4,548 + 80002048: 00500193 li gp,5 + 8000204c: 29d11063 bne sp,t4,800022cc <fail> + 80002050: ffffe597 auipc a1,0xffffe + 80002054: 0b858593 addi a1,a1,184 # 80000108 <data> + +0000000080002058 <test_6>: + 80002058: 41c8 lw a0,4(a1) + 8000205a: 0505 addi a0,a0,1 + 8000205c: c1c8 sw a0,4(a1) + 8000205e: 41d0 lw a2,4(a1) + 80002060: fedcceb7 lui t4,0xfedcc + 80002064: a99e8e9b addiw t4,t4,-1383 + 80002068: 00600193 li gp,6 + 8000206c: 27d61063 bne a2,t4,800022cc <fail> + +0000000080002070 <test_7>: + 80002070: 6188 ld a0,0(a1) + 80002072: 0505 addi a0,a0,1 + 80002074: e188 sd a0,0(a1) + 80002076: 6190 ld a2,0(a1) + 80002078: fff6eeb7 lui t4,0xfff6e + 8000207c: 5d5e8e9b addiw t4,t4,1493 + 80002080: 00ce9e93 slli t4,t4,0xc + 80002084: cbbe8e93 addi t4,t4,-837 # fffffffffff6dcbb <_end+0xffffffff7ff69cbb> + 80002088: 00de9e93 slli t4,t4,0xd + 8000208c: 543e8e93 addi t4,t4,1347 + 80002090: 00ce9e93 slli t4,t4,0xc + 80002094: 211e8e93 addi t4,t4,529 + 80002098: 00700193 li gp,7 + 8000209c: 23d61863 bne a2,t4,800022cc <fail> + +00000000800020a0 <test_8>: + 800020a0: 00106513 ori a0,zero,1 + 800020a4: 1541 addi a0,a0,-16 + 800020a6: 0001 nop + 800020a8: ff100e93 li t4,-15 + 800020ac: 00800193 li gp,8 + 800020b0: 21d51e63 bne a0,t4,800022cc <fail> + +00000000800020b4 <test_9>: + 800020b4: 00106793 ori a5,zero,1 + 800020b8: 57c1 li a5,-16 + 800020ba: 0001 nop + 800020bc: ff000e93 li t4,-16 + 800020c0: 00900193 li gp,9 + 800020c4: 21d79463 bne a5,t4,800022cc <fail> + +00000000800020c8 <test_10>: + 800020c8: 6188 ld a0,0(a1) + 800020ca: 357d addiw a0,a0,-1 + 800020cc: 76543eb7 lui t4,0x76543 + 800020d0: 210e8e9b addiw t4,t4,528 + 800020d4: 00a00193 li gp,10 + 800020d8: 1fd51a63 bne a0,t4,800022cc <fail> + +00000000800020dc <test_11>: + 800020dc: 7405 lui s0,0xfffe1 + 800020de: 8431 srai s0,s0,0xc + 800020e0: fe100e93 li t4,-31 + 800020e4: 00b00193 li gp,11 + 800020e8: 1fd41263 bne s0,t4,800022cc <fail> + +00000000800020ec <test_12>: + 800020ec: 7405 lui s0,0xfffe1 + 800020ee: 8031 srli s0,s0,0xc + 800020f0: 00100e9b addiw t4,zero,1 + 800020f4: 034e9e93 slli t4,t4,0x34 + 800020f8: fe1e8e93 addi t4,t4,-31 # 76542fe1 <_start-0x9abd01f> + 800020fc: 00c00193 li gp,12 + 80002100: 1dd41663 bne s0,t4,800022cc <fail> + +0000000080002104 <test_14>: + 80002104: 5479 li s0,-2 + 80002106: 983d andi s0,s0,-17 + 80002108: fee00e93 li t4,-18 + 8000210c: 00e00193 li gp,14 + 80002110: 1bd41e63 bne s0,t4,800022cc <fail> + +0000000080002114 <test_15>: + 80002114: 44d1 li s1,20 + 80002116: 4519 li a0,6 + 80002118: 8c89 sub s1,s1,a0 + 8000211a: 0001 nop + 8000211c: 00e00e93 li t4,14 + 80002120: 00f00193 li gp,15 + 80002124: 1bd49463 bne s1,t4,800022cc <fail> + +0000000080002128 <test_16>: + 80002128: 44d1 li s1,20 + 8000212a: 4519 li a0,6 + 8000212c: 8ca9 xor s1,s1,a0 + 8000212e: 0001 nop + 80002130: 01200e93 li t4,18 + 80002134: 01000193 li gp,16 + 80002138: 19d49a63 bne s1,t4,800022cc <fail> + +000000008000213c <test_17>: + 8000213c: 44d1 li s1,20 + 8000213e: 4519 li a0,6 + 80002140: 8cc9 or s1,s1,a0 + 80002142: 0001 nop + 80002144: 01600e93 li t4,22 + 80002148: 01100193 li gp,17 + 8000214c: 19d49063 bne s1,t4,800022cc <fail> + +0000000080002150 <test_18>: + 80002150: 44d1 li s1,20 + 80002152: 4519 li a0,6 + 80002154: 8ce9 and s1,s1,a0 + 80002156: 0001 nop + 80002158: 00400e93 li t4,4 + 8000215c: 01200193 li gp,18 + 80002160: 17d49663 bne s1,t4,800022cc <fail> + +0000000080002164 <test_19>: + 80002164: 800004b7 lui s1,0x80000 + 80002168: fff4849b addiw s1,s1,-1 + 8000216c: 557d li a0,-1 + 8000216e: 9c89 subw s1,s1,a0 + 80002170: 80000eb7 lui t4,0x80000 + 80002174: 01300193 li gp,19 + 80002178: 15d49a63 bne s1,t4,800022cc <fail> + +000000008000217c <test_20>: + 8000217c: 800004b7 lui s1,0x80000 + 80002180: fff4849b addiw s1,s1,-1 + 80002184: 4505 li a0,1 + 80002186: 9ca9 addw s1,s1,a0 + 80002188: 80000eb7 lui t4,0x80000 + 8000218c: 01400193 li gp,20 + 80002190: 13d49e63 bne s1,t4,800022cc <fail> + +0000000080002194 <test_21>: + 80002194: 00001437 lui s0,0x1 + 80002198: 2344041b addiw s0,s0,564 + 8000219c: 0412 slli s0,s0,0x4 + 8000219e: 0001 nop + 800021a0: 00012eb7 lui t4,0x12 + 800021a4: 340e8e9b addiw t4,t4,832 + 800021a8: 01500193 li gp,21 + 800021ac: 13d41063 bne s0,t4,800022cc <fail> + +00000000800021b0 <test_30>: + 800021b0: 4081 li ra,0 + 800021b2: a011 j 800021b6 <test_30+0x6> + 800021b4: a011 j 800021b8 <test_30+0x8> + 800021b6: a011 j 800021ba <test_30+0xa> + 800021b8: aa11 j 800022cc <fail> + 800021ba: 0001 nop + 800021bc: 00000e93 li t4,0 + 800021c0: 01e00193 li gp,30 + 800021c4: 11d09463 bne ra,t4,800022cc <fail> + +00000000800021c8 <test_31>: + 800021c8: 4501 li a0,0 + 800021ca: c111 beqz a0,800021ce <test_31+0x6> + 800021cc: a011 j 800021d0 <test_31+0x8> + 800021ce: a011 j 800021d2 <test_31+0xa> + 800021d0: a8f5 j 800022cc <fail> + 800021d2: 0001 nop + 800021d4: 00000e93 li t4,0 + 800021d8: 01f00193 li gp,31 + 800021dc: 0fd01863 bne zero,t4,800022cc <fail> + +00000000800021e0 <test_32>: + 800021e0: 4505 li a0,1 + 800021e2: e111 bnez a0,800021e6 <test_32+0x6> + 800021e4: a011 j 800021e8 <test_32+0x8> + 800021e6: a011 j 800021ea <test_32+0xa> + 800021e8: a0d5 j 800022cc <fail> + 800021ea: 0001 nop + 800021ec: 00000e93 li t4,0 + 800021f0: 02000193 li gp,32 + 800021f4: 0dd01c63 bne zero,t4,800022cc <fail> + +00000000800021f8 <test_33>: + 800021f8: 4505 li a0,1 + 800021fa: c111 beqz a0,800021fe <test_33+0x6> + 800021fc: a011 j 80002200 <test_33+0x8> + 800021fe: a0f9 j 800022cc <fail> + 80002200: 00000e93 li t4,0 + 80002204: 02100193 li gp,33 + 80002208: 0dd01263 bne zero,t4,800022cc <fail> + +000000008000220c <test_34>: + 8000220c: 4501 li a0,0 + 8000220e: e111 bnez a0,80002212 <test_34+0x6> + 80002210: a011 j 80002214 <test_34+0x8> + 80002212: a86d j 800022cc <fail> + 80002214: 00000e93 li t4,0 + 80002218: 02200193 li gp,34 + 8000221c: 0bd01863 bne zero,t4,800022cc <fail> + +0000000080002220 <test_35>: + 80002220: 00000297 auipc t0,0x0 + 80002224: 00e28293 addi t0,t0,14 # 8000222e <test_35+0xe> + 80002228: 4081 li ra,0 + 8000222a: 8282 jr t0 + 8000222c: a011 j 80002230 <test_35+0x10> + 8000222e: a011 j 80002232 <test_35+0x12> + 80002230: a871 j 800022cc <fail> + 80002232: 0001 nop + 80002234: 00000e93 li t4,0 + 80002238: 02300193 li gp,35 + 8000223c: 09d09863 bne ra,t4,800022cc <fail> + +0000000080002240 <test_36>: + 80002240: 00000297 auipc t0,0x0 + 80002244: 00e28293 addi t0,t0,14 # 8000224e <test_36+0xe> + 80002248: 4081 li ra,0 + 8000224a: 9282 jalr t0 + 8000224c: a011 j 80002250 <test_36+0x10> + 8000224e: a011 j 80002252 <test_36+0x12> + 80002250: a8b5 j 800022cc <fail> + 80002252: 405080b3 sub ra,ra,t0 + 80002256: 0001 nop + 80002258: ffe00e93 li t4,-2 + 8000225c: 02400193 li gp,36 + 80002260: 07d09663 bne ra,t4,800022cc <fail> + 80002264: ffffe117 auipc sp,0xffffe + 80002268: ea410113 addi sp,sp,-348 # 80000108 <data> + +000000008000226c <test_40>: + 8000226c: 4532 lw a0,12(sp) + 8000226e: 0505 addi a0,a0,1 + 80002270: c62a sw a0,12(sp) + 80002272: 4632 lw a2,12(sp) + 80002274: fedcceb7 lui t4,0xfedcc + 80002278: a99e8e9b addiw t4,t4,-1383 + 8000227c: 02800193 li gp,40 + 80002280: 05d61663 bne a2,t4,800022cc <fail> + +0000000080002284 <test_41>: + 80002284: 6522 ld a0,8(sp) + 80002286: 0505 addi a0,a0,1 + 80002288: e42a sd a0,8(sp) + 8000228a: 6622 ld a2,8(sp) + 8000228c: fff6eeb7 lui t4,0xfff6e + 80002290: 5d5e8e9b addiw t4,t4,1493 + 80002294: 00ce9e93 slli t4,t4,0xc + 80002298: cbbe8e93 addi t4,t4,-837 # fffffffffff6dcbb <_end+0xffffffff7ff69cbb> + 8000229c: 00de9e93 slli t4,t4,0xd + 800022a0: 543e8e93 addi t4,t4,1347 + 800022a4: 00ce9e93 slli t4,t4,0xc + 800022a8: 211e8e93 addi t4,t4,529 + 800022ac: 02900193 li gp,41 + 800022b0: 01d61e63 bne a2,t4,800022cc <fail> + +00000000800022b4 <test_42>: + 800022b4: 12300513 li a0,291 + 800022b8: 82aa mv t0,a0 + 800022ba: 92aa add t0,t0,a0 + 800022bc: 24600e93 li t4,582 + 800022c0: 02a00193 li gp,42 + 800022c4: 01d29463 bne t0,t4,800022cc <fail> + 800022c8: 00301c63 bne zero,gp,800022e0 <pass> + +00000000800022cc <fail>: + 800022cc: 0ff0000f fence + 800022d0: 00018063 beqz gp,800022d0 <fail+0x4> + 800022d4: 00119193 slli gp,gp,0x1 + 800022d8: 0011e193 ori gp,gp,1 + 800022dc: 00000073 ecall + +00000000800022e0 <pass>: + 800022e0: 0ff0000f fence + 800022e4: 00100193 li gp,1 + 800022e8: 00000073 ecall + 800022ec: c0001073 unimp + 800022f0: 0000 unimp + 800022f2: 0000 unimp + 800022f4: 0000 unimp + 800022f6: 0000 unimp + 800022f8: 0000 unimp + 800022fa: 0000 unimp + 800022fc: 0000 unimp + 800022fe: 0000 unimp + 80002300: 0000 unimp + 80002302: 0000 unimp + 80002304: 0000 unimp + 80002306: 0000 unimp + 80002308: 0000 unimp + 8000230a: 0000 unimp + 8000230c: 0000 unimp + 8000230e: 0000 unimp + 80002310: 0000 unimp + 80002312: 0000 unimp + 80002314: 0000 unimp + 80002316: 0000 unimp + 80002318: 0000 unimp + 8000231a: 0000 unimp + 8000231c: 0000 unimp + 8000231e: 0000 unimp + 80002320: 0000 unimp + 80002322: 0000 unimp + 80002324: 0000 unimp + 80002326: 0000 unimp + 80002328: 0000 unimp + 8000232a: 0000 unimp + 8000232c: 0000 unimp + 8000232e: 0000 unimp + 80002330: 0000 unimp + 80002332: 0000 unimp + 80002334: 0000 unimp + 80002336: 0000 unimp + 80002338: 0000 unimp + 8000233a: 0000 unimp + 8000233c: 0000 unimp + 8000233e: 0000 unimp + 80002340: 0000 unimp + 80002342: 0000 unimp + 80002344: 0000 unimp + 80002346: 0000 unimp + 80002348: 0000 unimp + 8000234a: 0000 unimp + 8000234c: 0000 unimp + 8000234e: 0000 unimp + 80002350: 0000 unimp + 80002352: 0000 unimp + 80002354: 0000 unimp + 80002356: 0000 unimp + 80002358: 0000 unimp + 8000235a: 0000 unimp + 8000235c: 0000 unimp + 8000235e: 0000 unimp + 80002360: 0000 unimp + 80002362: 0000 unimp + 80002364: 0000 unimp + 80002366: 0000 unimp + 80002368: 0000 unimp + 8000236a: 0000 unimp + 8000236c: 0000 unimp + 8000236e: 0000 unimp + 80002370: 0000 unimp + 80002372: 0000 unimp + 80002374: 0000 unimp + 80002376: 0000 unimp + 80002378: 0000 unimp + 8000237a: 0000 unimp + 8000237c: 0000 unimp + 8000237e: 0000 unimp + 80002380: 0000 unimp + 80002382: 0000 unimp + 80002384: 0000 unimp + 80002386: 0000 unimp + 80002388: 0000 unimp + 8000238a: 0000 unimp + 8000238c: 0000 unimp + 8000238e: 0000 unimp + 80002390: 0000 unimp + 80002392: 0000 unimp + 80002394: 0000 unimp + 80002396: 0000 unimp + 80002398: 0000 unimp + 8000239a: 0000 unimp + 8000239c: 0000 unimp + 8000239e: 0000 unimp + 800023a0: 0000 unimp + 800023a2: 0000 unimp + 800023a4: 0000 unimp + 800023a6: 0000 unimp + 800023a8: 0000 unimp + 800023aa: 0000 unimp + 800023ac: 0000 unimp + 800023ae: 0000 unimp + 800023b0: 0000 unimp + 800023b2: 0000 unimp + 800023b4: 0000 unimp + 800023b6: 0000 unimp + 800023b8: 0000 unimp + 800023ba: 0000 unimp + 800023bc: 0000 unimp + 800023be: 0000 unimp + 800023c0: 0000 unimp + 800023c2: 0000 unimp + 800023c4: 0000 unimp + 800023c6: 0000 unimp + 800023c8: 0000 unimp + 800023ca: 0000 unimp + 800023cc: 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0000 unimp + 80002a9a: 0000 unimp + 80002a9c: 0000 unimp + 80002a9e: 0000 unimp + 80002aa0: 0000 unimp + 80002aa2: 0000 unimp + 80002aa4: 0000 unimp + 80002aa6: 0000 unimp + 80002aa8: 0000 unimp + 80002aaa: 0000 unimp + 80002aac: 0000 unimp + 80002aae: 0000 unimp + 80002ab0: 0000 unimp + 80002ab2: 0000 unimp + 80002ab4: 0000 unimp + 80002ab6: 0000 unimp + 80002ab8: 0000 unimp + 80002aba: 0000 unimp + 80002abc: 0000 unimp + 80002abe: 0000 unimp + 80002ac0: 0000 unimp + 80002ac2: 0000 unimp + 80002ac4: 0000 unimp + 80002ac6: 0000 unimp + 80002ac8: 0000 unimp + 80002aca: 0000 unimp + 80002acc: 0000 unimp + 80002ace: 0000 unimp + 80002ad0: 0000 unimp + 80002ad2: 0000 unimp + 80002ad4: 0000 unimp + 80002ad6: 0000 unimp + 80002ad8: 0000 unimp + 80002ada: 0000 unimp + 80002adc: 0000 unimp + 80002ade: 0000 unimp + 80002ae0: 0000 unimp + 80002ae2: 0000 unimp + 80002ae4: 0000 unimp + 80002ae6: 0000 unimp + 80002ae8: 0000 unimp + 80002aea: 0000 unimp + 80002aec: 0000 unimp + 80002aee: 0000 unimp + 80002af0: 0000 unimp + 80002af2: 0000 unimp + 80002af4: 0000 unimp + 80002af6: 0000 unimp + 80002af8: 0000 unimp + 80002afa: 0000 unimp + 80002afc: 0000 unimp + 80002afe: 0000 unimp + 80002b00: 0000 unimp + 80002b02: 0000 unimp + 80002b04: 0000 unimp + 80002b06: 0000 unimp + 80002b08: 0000 unimp + 80002b0a: 0000 unimp + 80002b0c: 0000 unimp + 80002b0e: 0000 unimp + 80002b10: 0000 unimp + 80002b12: 0000 unimp + 80002b14: 0000 unimp + 80002b16: 0000 unimp + 80002b18: 0000 unimp + 80002b1a: 0000 unimp + 80002b1c: 0000 unimp + 80002b1e: 0000 unimp + 80002b20: 0000 unimp + 80002b22: 0000 unimp + 80002b24: 0000 unimp + 80002b26: 0000 unimp + 80002b28: 0000 unimp + 80002b2a: 0000 unimp + 80002b2c: 0000 unimp + 80002b2e: 0000 unimp + 80002b30: 0000 unimp + 80002b32: 0000 unimp + 80002b34: 0000 unimp + 80002b36: 0000 unimp + 80002b38: 0000 unimp + 80002b3a: 0000 unimp + 80002b3c: 0000 unimp + 80002b3e: 0000 unimp + 80002b40: 0000 unimp + 80002b42: 0000 unimp + 80002b44: 0000 unimp + 80002b46: 0000 unimp + 80002b48: 0000 unimp + 80002b4a: 0000 unimp + 80002b4c: 0000 unimp + 80002b4e: 0000 unimp + 80002b50: 0000 unimp + 80002b52: 0000 unimp + 80002b54: 0000 unimp + 80002b56: 0000 unimp + 80002b58: 0000 unimp + 80002b5a: 0000 unimp + 80002b5c: 0000 unimp + 80002b5e: 0000 unimp + 80002b60: 0000 unimp + 80002b62: 0000 unimp + 80002b64: 0000 unimp + 80002b66: 0000 unimp + 80002b68: 0000 unimp + 80002b6a: 0000 unimp + 80002b6c: 0000 unimp + 80002b6e: 0000 unimp + 80002b70: 0000 unimp + 80002b72: 0000 unimp + 80002b74: 0000 unimp + 80002b76: 0000 unimp + 80002b78: 0000 unimp + 80002b7a: 0000 unimp + 80002b7c: 0000 unimp + 80002b7e: 0000 unimp + 80002b80: 0000 unimp + 80002b82: 0000 unimp + 80002b84: 0000 unimp + 80002b86: 0000 unimp + 80002b88: 0000 unimp + 80002b8a: 0000 unimp + 80002b8c: 0000 unimp + 80002b8e: 0000 unimp + 80002b90: 0000 unimp + 80002b92: 0000 unimp + 80002b94: 0000 unimp + 80002b96: 0000 unimp + 80002b98: 0000 unimp + 80002b9a: 0000 unimp + 80002b9c: 0000 unimp + 80002b9e: 0000 unimp + 80002ba0: 0000 unimp + 80002ba2: 0000 unimp + 80002ba4: 0000 unimp + 80002ba6: 0000 unimp + 80002ba8: 0000 unimp + 80002baa: 0000 unimp + 80002bac: 0000 unimp + 80002bae: 0000 unimp + 80002bb0: 0000 unimp + 80002bb2: 0000 unimp + 80002bb4: 0000 unimp + 80002bb6: 0000 unimp + 80002bb8: 0000 unimp + 80002bba: 0000 unimp + 80002bbc: 0000 unimp + 80002bbe: 0000 unimp + 80002bc0: 0000 unimp + 80002bc2: 0000 unimp + 80002bc4: 0000 unimp + 80002bc6: 0000 unimp + 80002bc8: 0000 unimp + 80002bca: 0000 unimp + 80002bcc: 0000 unimp + 80002bce: 0000 unimp + 80002bd0: 0000 unimp + 80002bd2: 0000 unimp + 80002bd4: 0000 unimp + 80002bd6: 0000 unimp + 80002bd8: 0000 unimp + 80002bda: 0000 unimp + 80002bdc: 0000 unimp + 80002bde: 0000 unimp + 80002be0: 0000 unimp + 80002be2: 0000 unimp + 80002be4: 0000 unimp + 80002be6: 0000 unimp + 80002be8: 0000 unimp + 80002bea: 0000 unimp + 80002bec: 0000 unimp + 80002bee: 0000 unimp + 80002bf0: 0000 unimp + 80002bf2: 0000 unimp + 80002bf4: 0000 unimp + 80002bf6: 0000 unimp + 80002bf8: 0000 unimp + 80002bfa: 0000 unimp + 80002bfc: 0000 unimp + 80002bfe: 0000 unimp + 80002c00: 0000 unimp + 80002c02: 0000 unimp + 80002c04: 0000 unimp + 80002c06: 0000 unimp + 80002c08: 0000 unimp + 80002c0a: 0000 unimp + 80002c0c: 0000 unimp + 80002c0e: 0000 unimp + 80002c10: 0000 unimp + 80002c12: 0000 unimp + 80002c14: 0000 unimp + 80002c16: 0000 unimp + 80002c18: 0000 unimp + 80002c1a: 0000 unimp + 80002c1c: 0000 unimp + 80002c1e: 0000 unimp + 80002c20: 0000 unimp + 80002c22: 0000 unimp + 80002c24: 0000 unimp + 80002c26: 0000 unimp + 80002c28: 0000 unimp + 80002c2a: 0000 unimp + 80002c2c: 0000 unimp + 80002c2e: 0000 unimp + 80002c30: 0000 unimp + 80002c32: 0000 unimp + 80002c34: 0000 unimp + 80002c36: 0000 unimp + 80002c38: 0000 unimp + 80002c3a: 0000 unimp + 80002c3c: 0000 unimp + 80002c3e: 0000 unimp + 80002c40: 0000 unimp + 80002c42: 0000 unimp + 80002c44: 0000 unimp + 80002c46: 0000 unimp + 80002c48: 0000 unimp + 80002c4a: 0000 unimp + 80002c4c: 0000 unimp + 80002c4e: 0000 unimp + 80002c50: 0000 unimp + 80002c52: 0000 unimp + 80002c54: 0000 unimp + 80002c56: 0000 unimp + 80002c58: 0000 unimp + 80002c5a: 0000 unimp + 80002c5c: 0000 unimp + 80002c5e: 0000 unimp + 80002c60: 0000 unimp + 80002c62: 0000 unimp + 80002c64: 0000 unimp + 80002c66: 0000 unimp + 80002c68: 0000 unimp + 80002c6a: 0000 unimp + 80002c6c: 0000 unimp + 80002c6e: 0000 unimp + 80002c70: 0000 unimp + 80002c72: 0000 unimp + 80002c74: 0000 unimp + 80002c76: 0000 unimp + 80002c78: 0000 unimp + 80002c7a: 0000 unimp + 80002c7c: 0000 unimp + 80002c7e: 0000 unimp + 80002c80: 0000 unimp + 80002c82: 0000 unimp + 80002c84: 0000 unimp + 80002c86: 0000 unimp + 80002c88: 0000 unimp + 80002c8a: 0000 unimp + 80002c8c: 0000 unimp + 80002c8e: 0000 unimp + 80002c90: 0000 unimp + 80002c92: 0000 unimp + 80002c94: 0000 unimp + 80002c96: 0000 unimp + 80002c98: 0000 unimp + 80002c9a: 0000 unimp + 80002c9c: 0000 unimp + 80002c9e: 0000 unimp + 80002ca0: 0000 unimp + 80002ca2: 0000 unimp + 80002ca4: 0000 unimp + 80002ca6: 0000 unimp + 80002ca8: 0000 unimp + 80002caa: 0000 unimp + 80002cac: 0000 unimp + 80002cae: 0000 unimp + 80002cb0: 0000 unimp + 80002cb2: 0000 unimp + 80002cb4: 0000 unimp + 80002cb6: 0000 unimp + 80002cb8: 0000 unimp + 80002cba: 0000 unimp + 80002cbc: 0000 unimp + 80002cbe: 0000 unimp + 80002cc0: 0000 unimp + 80002cc2: 0000 unimp + 80002cc4: 0000 unimp + 80002cc6: 0000 unimp + 80002cc8: 0000 unimp + 80002cca: 0000 unimp + 80002ccc: 0000 unimp + 80002cce: 0000 unimp + 80002cd0: 0000 unimp + 80002cd2: 0000 unimp + 80002cd4: 0000 unimp + 80002cd6: 0000 unimp + 80002cd8: 0000 unimp + 80002cda: 0000 unimp + 80002cdc: 0000 unimp + 80002cde: 0000 unimp + 80002ce0: 0000 unimp + 80002ce2: 0000 unimp + 80002ce4: 0000 unimp + 80002ce6: 0000 unimp + 80002ce8: 0000 unimp + 80002cea: 0000 unimp + 80002cec: 0000 unimp + 80002cee: 0000 unimp + 80002cf0: 0000 unimp + 80002cf2: 0000 unimp + 80002cf4: 0000 unimp + 80002cf6: 0000 unimp + 80002cf8: 0000 unimp + 80002cfa: 0000 unimp + 80002cfc: 0000 unimp + 80002cfe: 0000 unimp + 80002d00: 0000 unimp + 80002d02: 0000 unimp + 80002d04: 0000 unimp + 80002d06: 0000 unimp + 80002d08: 0000 unimp + 80002d0a: 0000 unimp + 80002d0c: 0000 unimp + 80002d0e: 0000 unimp + 80002d10: 0000 unimp + 80002d12: 0000 unimp + 80002d14: 0000 unimp + 80002d16: 0000 unimp + 80002d18: 0000 unimp + 80002d1a: 0000 unimp + 80002d1c: 0000 unimp + 80002d1e: 0000 unimp + 80002d20: 0000 unimp + 80002d22: 0000 unimp + 80002d24: 0000 unimp + 80002d26: 0000 unimp + 80002d28: 0000 unimp + 80002d2a: 0000 unimp + 80002d2c: 0000 unimp + 80002d2e: 0000 unimp + 80002d30: 0000 unimp + 80002d32: 0000 unimp + 80002d34: 0000 unimp + 80002d36: 0000 unimp + 80002d38: 0000 unimp + 80002d3a: 0000 unimp + 80002d3c: 0000 unimp + 80002d3e: 0000 unimp + 80002d40: 0000 unimp + 80002d42: 0000 unimp + 80002d44: 0000 unimp + 80002d46: 0000 unimp + 80002d48: 0000 unimp + 80002d4a: 0000 unimp + 80002d4c: 0000 unimp + 80002d4e: 0000 unimp + 80002d50: 0000 unimp + 80002d52: 0000 unimp + 80002d54: 0000 unimp + 80002d56: 0000 unimp + 80002d58: 0000 unimp + 80002d5a: 0000 unimp + 80002d5c: 0000 unimp + 80002d5e: 0000 unimp + 80002d60: 0000 unimp + 80002d62: 0000 unimp + 80002d64: 0000 unimp + 80002d66: 0000 unimp + 80002d68: 0000 unimp + 80002d6a: 0000 unimp + 80002d6c: 0000 unimp + 80002d6e: 0000 unimp + 80002d70: 0000 unimp + 80002d72: 0000 unimp + 80002d74: 0000 unimp + 80002d76: 0000 unimp + 80002d78: 0000 unimp + 80002d7a: 0000 unimp + 80002d7c: 0000 unimp + 80002d7e: 0000 unimp + 80002d80: 0000 unimp + 80002d82: 0000 unimp + 80002d84: 0000 unimp + 80002d86: 0000 unimp + 80002d88: 0000 unimp + 80002d8a: 0000 unimp + 80002d8c: 0000 unimp + 80002d8e: 0000 unimp + 80002d90: 0000 unimp + 80002d92: 0000 unimp + 80002d94: 0000 unimp + 80002d96: 0000 unimp + 80002d98: 0000 unimp + 80002d9a: 0000 unimp + 80002d9c: 0000 unimp + 80002d9e: 0000 unimp + 80002da0: 0000 unimp + 80002da2: 0000 unimp + 80002da4: 0000 unimp + 80002da6: 0000 unimp + 80002da8: 0000 unimp + 80002daa: 0000 unimp + 80002dac: 0000 unimp + 80002dae: 0000 unimp + 80002db0: 0000 unimp + 80002db2: 0000 unimp + 80002db4: 0000 unimp + 80002db6: 0000 unimp + 80002db8: 0000 unimp + 80002dba: 0000 unimp + 80002dbc: 0000 unimp + 80002dbe: 0000 unimp + 80002dc0: 0000 unimp + 80002dc2: 0000 unimp + 80002dc4: 0000 unimp + 80002dc6: 0000 unimp + 80002dc8: 0000 unimp + 80002dca: 0000 unimp + 80002dcc: 0000 unimp + 80002dce: 0000 unimp + 80002dd0: 0000 unimp + 80002dd2: 0000 unimp + 80002dd4: 0000 unimp + 80002dd6: 0000 unimp + 80002dd8: 0000 unimp + 80002dda: 0000 unimp + 80002ddc: 0000 unimp + 80002dde: 0000 unimp + 80002de0: 0000 unimp + 80002de2: 0000 unimp + 80002de4: 0000 unimp + 80002de6: 0000 unimp + 80002de8: 0000 unimp + 80002dea: 0000 unimp + 80002dec: 0000 unimp + 80002dee: 0000 unimp + 80002df0: 0000 unimp + 80002df2: 0000 unimp + 80002df4: 0000 unimp + 80002df6: 0000 unimp + 80002df8: 0000 unimp + 80002dfa: 0000 unimp + 80002dfc: 0000 unimp + 80002dfe: 0000 unimp + 80002e00: 0000 unimp + 80002e02: 0000 unimp + 80002e04: 0000 unimp + 80002e06: 0000 unimp + 80002e08: 0000 unimp + 80002e0a: 0000 unimp + 80002e0c: 0000 unimp + 80002e0e: 0000 unimp + 80002e10: 0000 unimp + 80002e12: 0000 unimp + 80002e14: 0000 unimp + 80002e16: 0000 unimp + 80002e18: 0000 unimp + 80002e1a: 0000 unimp + 80002e1c: 0000 unimp + 80002e1e: 0000 unimp + 80002e20: 0000 unimp + 80002e22: 0000 unimp + 80002e24: 0000 unimp + 80002e26: 0000 unimp + 80002e28: 0000 unimp + 80002e2a: 0000 unimp + 80002e2c: 0000 unimp + 80002e2e: 0000 unimp + 80002e30: 0000 unimp + 80002e32: 0000 unimp + 80002e34: 0000 unimp + 80002e36: 0000 unimp + 80002e38: 0000 unimp + 80002e3a: 0000 unimp + 80002e3c: 0000 unimp + 80002e3e: 0000 unimp + 80002e40: 0000 unimp + 80002e42: 0000 unimp + 80002e44: 0000 unimp + 80002e46: 0000 unimp + 80002e48: 0000 unimp + 80002e4a: 0000 unimp + 80002e4c: 0000 unimp + 80002e4e: 0000 unimp + 80002e50: 0000 unimp + 80002e52: 0000 unimp + 80002e54: 0000 unimp + 80002e56: 0000 unimp + 80002e58: 0000 unimp + 80002e5a: 0000 unimp + 80002e5c: 0000 unimp + 80002e5e: 0000 unimp + 80002e60: 0000 unimp + 80002e62: 0000 unimp + 80002e64: 0000 unimp + 80002e66: 0000 unimp + 80002e68: 0000 unimp + 80002e6a: 0000 unimp + 80002e6c: 0000 unimp + 80002e6e: 0000 unimp + 80002e70: 0000 unimp + 80002e72: 0000 unimp + 80002e74: 0000 unimp + 80002e76: 0000 unimp + 80002e78: 0000 unimp + 80002e7a: 0000 unimp + 80002e7c: 0000 unimp + 80002e7e: 0000 unimp + 80002e80: 0000 unimp + 80002e82: 0000 unimp + 80002e84: 0000 unimp + 80002e86: 0000 unimp + 80002e88: 0000 unimp + 80002e8a: 0000 unimp + 80002e8c: 0000 unimp + 80002e8e: 0000 unimp diff --git a/test/riscv/tests/rv64uc-p-rvc.elf b/test/riscv/tests/rv64uc-p-rvc.elf Binary files differnew file mode 100755 index 00000000..dbfdfcc3 --- /dev/null +++ b/test/riscv/tests/rv64uc-p-rvc.elf diff --git a/test/riscv/tests/rv64ui-p-add.dump b/test/riscv/tests/rv64ui-p-add.dump new file mode 100644 index 00000000..83e5cedc --- /dev/null +++ b/test/riscv/tests/rv64ui-p-add.dump @@ -0,0 +1,506 @@ + +rv64ui-p-add: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 00000113 li sp,0 + 80000104: 00208f33 add t5,ra,sp + 80000108: 00000e93 li t4,0 + 8000010c: 00200193 li gp,2 + 80000110: 4fdf1063 bne t5,t4,800005f0 <fail> + +0000000080000114 <test_3>: + 80000114: 00100093 li ra,1 + 80000118: 00100113 li sp,1 + 8000011c: 00208f33 add t5,ra,sp + 80000120: 00200e93 li t4,2 + 80000124: 00300193 li gp,3 + 80000128: 4ddf1463 bne t5,t4,800005f0 <fail> + +000000008000012c <test_4>: + 8000012c: 00300093 li ra,3 + 80000130: 00700113 li sp,7 + 80000134: 00208f33 add t5,ra,sp + 80000138: 00a00e93 li t4,10 + 8000013c: 00400193 li gp,4 + 80000140: 4bdf1863 bne t5,t4,800005f0 <fail> + +0000000080000144 <test_5>: + 80000144: 00000093 li ra,0 + 80000148: ffff8137 lui sp,0xffff8 + 8000014c: 00208f33 add t5,ra,sp + 80000150: ffff8eb7 lui t4,0xffff8 + 80000154: 00500193 li gp,5 + 80000158: 49df1c63 bne t5,t4,800005f0 <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 00000113 li sp,0 + 80000164: 00208f33 add t5,ra,sp + 80000168: 80000eb7 lui t4,0x80000 + 8000016c: 00600193 li gp,6 + 80000170: 49df1063 bne t5,t4,800005f0 <fail> + +0000000080000174 <test_7>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: ffff8137 lui sp,0xffff8 + 8000017c: 00208f33 add t5,ra,sp + 80000180: ffff0eb7 lui t4,0xffff0 + 80000184: fffe8e9b addiw t4,t4,-1 + 80000188: 00fe9e93 slli t4,t4,0xf + 8000018c: 00700193 li gp,7 + 80000190: 47df1063 bne t5,t4,800005f0 <fail> + +0000000080000194 <test_8>: + 80000194: 00000093 li ra,0 + 80000198: 00008137 lui sp,0x8 + 8000019c: fff1011b addiw sp,sp,-1 + 800001a0: 00208f33 add t5,ra,sp + 800001a4: 00008eb7 lui t4,0x8 + 800001a8: fffe8e9b addiw t4,t4,-1 + 800001ac: 00800193 li gp,8 + 800001b0: 45df1063 bne t5,t4,800005f0 <fail> + +00000000800001b4 <test_9>: + 800001b4: 800000b7 lui ra,0x80000 + 800001b8: fff0809b addiw ra,ra,-1 + 800001bc: 00000113 li sp,0 + 800001c0: 00208f33 add t5,ra,sp + 800001c4: 80000eb7 lui t4,0x80000 + 800001c8: fffe8e9b addiw t4,t4,-1 + 800001cc: 00900193 li gp,9 + 800001d0: 43df1063 bne t5,t4,800005f0 <fail> + +00000000800001d4 <test_10>: + 800001d4: 800000b7 lui ra,0x80000 + 800001d8: fff0809b addiw ra,ra,-1 + 800001dc: 00008137 lui sp,0x8 + 800001e0: fff1011b addiw sp,sp,-1 + 800001e4: 00208f33 add t5,ra,sp + 800001e8: 00010eb7 lui t4,0x10 + 800001ec: 001e8e9b addiw t4,t4,1 + 800001f0: 00fe9e93 slli t4,t4,0xf + 800001f4: ffee8e93 addi t4,t4,-2 # fffe <_start-0x7fff0002> + 800001f8: 00a00193 li gp,10 + 800001fc: 3fdf1a63 bne t5,t4,800005f0 <fail> + +0000000080000200 <test_11>: + 80000200: 800000b7 lui ra,0x80000 + 80000204: 00008137 lui sp,0x8 + 80000208: fff1011b addiw sp,sp,-1 + 8000020c: 00208f33 add t5,ra,sp + 80000210: 80008eb7 lui t4,0x80008 + 80000214: fffe8e9b addiw t4,t4,-1 + 80000218: 00b00193 li gp,11 + 8000021c: 3ddf1a63 bne t5,t4,800005f0 <fail> + +0000000080000220 <test_12>: + 80000220: 800000b7 lui ra,0x80000 + 80000224: fff0809b addiw ra,ra,-1 + 80000228: ffff8137 lui sp,0xffff8 + 8000022c: 00208f33 add t5,ra,sp + 80000230: 7fff8eb7 lui t4,0x7fff8 + 80000234: fffe8e9b addiw t4,t4,-1 + 80000238: 00c00193 li gp,12 + 8000023c: 3bdf1a63 bne t5,t4,800005f0 <fail> + +0000000080000240 <test_13>: + 80000240: 00000093 li ra,0 + 80000244: fff00113 li sp,-1 + 80000248: 00208f33 add t5,ra,sp + 8000024c: fff00e93 li t4,-1 + 80000250: 00d00193 li gp,13 + 80000254: 39df1e63 bne t5,t4,800005f0 <fail> + +0000000080000258 <test_14>: + 80000258: fff00093 li ra,-1 + 8000025c: 00100113 li sp,1 + 80000260: 00208f33 add t5,ra,sp + 80000264: 00000e93 li t4,0 + 80000268: 00e00193 li gp,14 + 8000026c: 39df1263 bne t5,t4,800005f0 <fail> + +0000000080000270 <test_15>: + 80000270: fff00093 li ra,-1 + 80000274: fff00113 li sp,-1 + 80000278: 00208f33 add t5,ra,sp + 8000027c: ffe00e93 li t4,-2 + 80000280: 00f00193 li gp,15 + 80000284: 37df1663 bne t5,t4,800005f0 <fail> + +0000000080000288 <test_16>: + 80000288: 00100093 li ra,1 + 8000028c: 80000137 lui sp,0x80000 + 80000290: fff1011b addiw sp,sp,-1 + 80000294: 00208f33 add t5,ra,sp + 80000298: 00100e9b addiw t4,zero,1 + 8000029c: 01fe9e93 slli t4,t4,0x1f + 800002a0: 01000193 li gp,16 + 800002a4: 35df1663 bne t5,t4,800005f0 <fail> + +00000000800002a8 <test_17>: + 800002a8: 00d00093 li ra,13 + 800002ac: 00b00113 li sp,11 + 800002b0: 002080b3 add ra,ra,sp + 800002b4: 01800e93 li t4,24 + 800002b8: 01100193 li gp,17 + 800002bc: 33d09a63 bne ra,t4,800005f0 <fail> + +00000000800002c0 <test_18>: + 800002c0: 00e00093 li ra,14 + 800002c4: 00b00113 li sp,11 + 800002c8: 00208133 add sp,ra,sp + 800002cc: 01900e93 li t4,25 + 800002d0: 01200193 li gp,18 + 800002d4: 31d11e63 bne sp,t4,800005f0 <fail> + +00000000800002d8 <test_19>: + 800002d8: 00d00093 li ra,13 + 800002dc: 001080b3 add ra,ra,ra + 800002e0: 01a00e93 li t4,26 + 800002e4: 01300193 li gp,19 + 800002e8: 31d09463 bne ra,t4,800005f0 <fail> + +00000000800002ec <test_20>: + 800002ec: 00000213 li tp,0 + 800002f0: 00d00093 li ra,13 + 800002f4: 00b00113 li sp,11 + 800002f8: 00208f33 add t5,ra,sp + 800002fc: 000f0313 mv t1,t5 + 80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000304: 00200293 li t0,2 + 80000308: fe5214e3 bne tp,t0,800002f0 <test_20+0x4> + 8000030c: 01800e93 li t4,24 + 80000310: 01400193 li gp,20 + 80000314: 2dd31e63 bne t1,t4,800005f0 <fail> + +0000000080000318 <test_21>: + 80000318: 00000213 li tp,0 + 8000031c: 00e00093 li ra,14 + 80000320: 00b00113 li sp,11 + 80000324: 00208f33 add t5,ra,sp + 80000328: 00000013 nop + 8000032c: 000f0313 mv t1,t5 + 80000330: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000334: 00200293 li t0,2 + 80000338: fe5212e3 bne tp,t0,8000031c <test_21+0x4> + 8000033c: 01900e93 li t4,25 + 80000340: 01500193 li gp,21 + 80000344: 2bd31663 bne t1,t4,800005f0 <fail> + +0000000080000348 <test_22>: + 80000348: 00000213 li tp,0 + 8000034c: 00f00093 li ra,15 + 80000350: 00b00113 li sp,11 + 80000354: 00208f33 add t5,ra,sp + 80000358: 00000013 nop + 8000035c: 00000013 nop + 80000360: 000f0313 mv t1,t5 + 80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000368: 00200293 li t0,2 + 8000036c: fe5210e3 bne tp,t0,8000034c <test_22+0x4> + 80000370: 01a00e93 li t4,26 + 80000374: 01600193 li gp,22 + 80000378: 27d31c63 bne t1,t4,800005f0 <fail> + +000000008000037c <test_23>: + 8000037c: 00000213 li tp,0 + 80000380: 00d00093 li ra,13 + 80000384: 00b00113 li sp,11 + 80000388: 00208f33 add t5,ra,sp + 8000038c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000390: 00200293 li t0,2 + 80000394: fe5216e3 bne tp,t0,80000380 <test_23+0x4> + 80000398: 01800e93 li t4,24 + 8000039c: 01700193 li gp,23 + 800003a0: 25df1863 bne t5,t4,800005f0 <fail> + +00000000800003a4 <test_24>: + 800003a4: 00000213 li tp,0 + 800003a8: 00e00093 li ra,14 + 800003ac: 00b00113 li sp,11 + 800003b0: 00000013 nop + 800003b4: 00208f33 add t5,ra,sp + 800003b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003bc: 00200293 li t0,2 + 800003c0: fe5214e3 bne tp,t0,800003a8 <test_24+0x4> + 800003c4: 01900e93 li t4,25 + 800003c8: 01800193 li gp,24 + 800003cc: 23df1263 bne t5,t4,800005f0 <fail> + +00000000800003d0 <test_25>: + 800003d0: 00000213 li tp,0 + 800003d4: 00f00093 li ra,15 + 800003d8: 00b00113 li sp,11 + 800003dc: 00000013 nop + 800003e0: 00000013 nop + 800003e4: 00208f33 add t5,ra,sp + 800003e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003ec: 00200293 li t0,2 + 800003f0: fe5212e3 bne tp,t0,800003d4 <test_25+0x4> + 800003f4: 01a00e93 li t4,26 + 800003f8: 01900193 li gp,25 + 800003fc: 1fdf1a63 bne t5,t4,800005f0 <fail> + +0000000080000400 <test_26>: + 80000400: 00000213 li tp,0 + 80000404: 00d00093 li ra,13 + 80000408: 00000013 nop + 8000040c: 00b00113 li sp,11 + 80000410: 00208f33 add t5,ra,sp + 80000414: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000418: 00200293 li t0,2 + 8000041c: fe5214e3 bne tp,t0,80000404 <test_26+0x4> + 80000420: 01800e93 li t4,24 + 80000424: 01a00193 li gp,26 + 80000428: 1ddf1463 bne t5,t4,800005f0 <fail> + +000000008000042c <test_27>: + 8000042c: 00000213 li tp,0 + 80000430: 00e00093 li ra,14 + 80000434: 00000013 nop + 80000438: 00b00113 li sp,11 + 8000043c: 00000013 nop + 80000440: 00208f33 add t5,ra,sp + 80000444: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000448: 00200293 li t0,2 + 8000044c: fe5212e3 bne tp,t0,80000430 <test_27+0x4> + 80000450: 01900e93 li t4,25 + 80000454: 01b00193 li gp,27 + 80000458: 19df1c63 bne t5,t4,800005f0 <fail> + +000000008000045c <test_28>: + 8000045c: 00000213 li tp,0 + 80000460: 00f00093 li ra,15 + 80000464: 00000013 nop + 80000468: 00000013 nop + 8000046c: 00b00113 li sp,11 + 80000470: 00208f33 add t5,ra,sp + 80000474: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000478: 00200293 li t0,2 + 8000047c: fe5212e3 bne tp,t0,80000460 <test_28+0x4> + 80000480: 01a00e93 li t4,26 + 80000484: 01c00193 li gp,28 + 80000488: 17df1463 bne t5,t4,800005f0 <fail> + +000000008000048c <test_29>: + 8000048c: 00000213 li tp,0 + 80000490: 00b00113 li sp,11 + 80000494: 00d00093 li ra,13 + 80000498: 00208f33 add t5,ra,sp + 8000049c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004a0: 00200293 li t0,2 + 800004a4: fe5216e3 bne tp,t0,80000490 <test_29+0x4> + 800004a8: 01800e93 li t4,24 + 800004ac: 01d00193 li gp,29 + 800004b0: 15df1063 bne t5,t4,800005f0 <fail> + +00000000800004b4 <test_30>: + 800004b4: 00000213 li tp,0 + 800004b8: 00b00113 li sp,11 + 800004bc: 00e00093 li ra,14 + 800004c0: 00000013 nop + 800004c4: 00208f33 add t5,ra,sp + 800004c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004cc: 00200293 li t0,2 + 800004d0: fe5214e3 bne tp,t0,800004b8 <test_30+0x4> + 800004d4: 01900e93 li t4,25 + 800004d8: 01e00193 li gp,30 + 800004dc: 11df1a63 bne t5,t4,800005f0 <fail> + +00000000800004e0 <test_31>: + 800004e0: 00000213 li tp,0 + 800004e4: 00b00113 li sp,11 + 800004e8: 00f00093 li ra,15 + 800004ec: 00000013 nop + 800004f0: 00000013 nop + 800004f4: 00208f33 add t5,ra,sp + 800004f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004fc: 00200293 li t0,2 + 80000500: fe5212e3 bne tp,t0,800004e4 <test_31+0x4> + 80000504: 01a00e93 li t4,26 + 80000508: 01f00193 li gp,31 + 8000050c: 0fdf1263 bne t5,t4,800005f0 <fail> + +0000000080000510 <test_32>: + 80000510: 00000213 li tp,0 + 80000514: 00b00113 li sp,11 + 80000518: 00000013 nop + 8000051c: 00d00093 li ra,13 + 80000520: 00208f33 add t5,ra,sp + 80000524: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000528: 00200293 li t0,2 + 8000052c: fe5214e3 bne tp,t0,80000514 <test_32+0x4> + 80000530: 01800e93 li t4,24 + 80000534: 02000193 li gp,32 + 80000538: 0bdf1c63 bne t5,t4,800005f0 <fail> + +000000008000053c <test_33>: + 8000053c: 00000213 li tp,0 + 80000540: 00b00113 li sp,11 + 80000544: 00000013 nop + 80000548: 00e00093 li ra,14 + 8000054c: 00000013 nop + 80000550: 00208f33 add t5,ra,sp + 80000554: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000558: 00200293 li t0,2 + 8000055c: fe5212e3 bne tp,t0,80000540 <test_33+0x4> + 80000560: 01900e93 li t4,25 + 80000564: 02100193 li gp,33 + 80000568: 09df1463 bne t5,t4,800005f0 <fail> + +000000008000056c <test_34>: + 8000056c: 00000213 li tp,0 + 80000570: 00b00113 li sp,11 + 80000574: 00000013 nop + 80000578: 00000013 nop + 8000057c: 00f00093 li ra,15 + 80000580: 00208f33 add t5,ra,sp + 80000584: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000588: 00200293 li t0,2 + 8000058c: fe5212e3 bne tp,t0,80000570 <test_34+0x4> + 80000590: 01a00e93 li t4,26 + 80000594: 02200193 li gp,34 + 80000598: 05df1c63 bne t5,t4,800005f0 <fail> + +000000008000059c <test_35>: + 8000059c: 00f00093 li ra,15 + 800005a0: 00100133 add sp,zero,ra + 800005a4: 00f00e93 li t4,15 + 800005a8: 02300193 li gp,35 + 800005ac: 05d11263 bne sp,t4,800005f0 <fail> + +00000000800005b0 <test_36>: + 800005b0: 02000093 li ra,32 + 800005b4: 00008133 add sp,ra,zero + 800005b8: 02000e93 li t4,32 + 800005bc: 02400193 li gp,36 + 800005c0: 03d11863 bne sp,t4,800005f0 <fail> + +00000000800005c4 <test_37>: + 800005c4: 000000b3 add ra,zero,zero + 800005c8: 00000e93 li t4,0 + 800005cc: 02500193 li gp,37 + 800005d0: 03d09063 bne ra,t4,800005f0 <fail> + +00000000800005d4 <test_38>: + 800005d4: 01000093 li ra,16 + 800005d8: 01e00113 li sp,30 + 800005dc: 00208033 add zero,ra,sp + 800005e0: 00000e93 li t4,0 + 800005e4: 02600193 li gp,38 + 800005e8: 01d01463 bne zero,t4,800005f0 <fail> + 800005ec: 00301c63 bne zero,gp,80000604 <pass> + +00000000800005f0 <fail>: + 800005f0: 0ff0000f fence + 800005f4: 00018063 beqz gp,800005f4 <fail+0x4> + 800005f8: 00119193 slli gp,gp,0x1 + 800005fc: 0011e193 ori gp,gp,1 + 80000600: 00000073 ecall + +0000000080000604 <pass>: + 80000604: 0ff0000f fence + 80000608: 00100193 li gp,1 + 8000060c: 00000073 ecall + 80000610: c0001073 unimp + 80000614: 0000 unimp + 80000616: 0000 unimp + 80000618: 0000 unimp + 8000061a: 0000 unimp + 8000061c: 0000 unimp + 8000061e: 0000 unimp + 80000620: 0000 unimp + 80000622: 0000 unimp + 80000624: 0000 unimp + 80000626: 0000 unimp + 80000628: 0000 unimp + 8000062a: 0000 unimp + 8000062c: 0000 unimp + 8000062e: 0000 unimp + 80000630: 0000 unimp + 80000632: 0000 unimp + 80000634: 0000 unimp + 80000636: 0000 unimp + 80000638: 0000 unimp + 8000063a: 0000 unimp + 8000063c: 0000 unimp + 8000063e: 0000 unimp + 80000640: 0000 unimp + 80000642: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-add.elf b/test/riscv/tests/rv64ui-p-add.elf Binary files differnew file mode 100755 index 00000000..cd560ee7 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-add.elf diff --git a/test/riscv/tests/rv64ui-p-addi.dump b/test/riscv/tests/rv64ui-p-addi.dump new file mode 100644 index 00000000..dc5acc09 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-addi.dump @@ -0,0 +1,312 @@ + +rv64ui-p-addi: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 00008f13 mv t5,ra + 80000104: 00000e93 li t4,0 + 80000108: 00200193 li gp,2 + 8000010c: 29df1263 bne t5,t4,80000390 <fail> + +0000000080000110 <test_3>: + 80000110: 00100093 li ra,1 + 80000114: 00108f13 addi t5,ra,1 + 80000118: 00200e93 li t4,2 + 8000011c: 00300193 li gp,3 + 80000120: 27df1863 bne t5,t4,80000390 <fail> + +0000000080000124 <test_4>: + 80000124: 00300093 li ra,3 + 80000128: 00708f13 addi t5,ra,7 + 8000012c: 00a00e93 li t4,10 + 80000130: 00400193 li gp,4 + 80000134: 25df1e63 bne t5,t4,80000390 <fail> + +0000000080000138 <test_5>: + 80000138: 00000093 li ra,0 + 8000013c: 80008f13 addi t5,ra,-2048 + 80000140: 80000e93 li t4,-2048 + 80000144: 00500193 li gp,5 + 80000148: 25df1463 bne t5,t4,80000390 <fail> + +000000008000014c <test_6>: + 8000014c: 800000b7 lui ra,0x80000 + 80000150: 00008f13 mv t5,ra + 80000154: 80000eb7 lui t4,0x80000 + 80000158: 00600193 li gp,6 + 8000015c: 23df1a63 bne t5,t4,80000390 <fail> + +0000000080000160 <test_7>: + 80000160: 800000b7 lui ra,0x80000 + 80000164: 80008f13 addi t5,ra,-2048 # ffffffff7ffff800 <_end+0xfffffffeffffd800> + 80000168: fff00e9b addiw t4,zero,-1 + 8000016c: 01fe9e93 slli t4,t4,0x1f + 80000170: 800e8e93 addi t4,t4,-2048 # ffffffff7ffff800 <_end+0xfffffffeffffd800> + 80000174: 00700193 li gp,7 + 80000178: 21df1c63 bne t5,t4,80000390 <fail> + +000000008000017c <test_8>: + 8000017c: 00000093 li ra,0 + 80000180: 7ff08f13 addi t5,ra,2047 + 80000184: 7ff00e93 li t4,2047 + 80000188: 00800193 li gp,8 + 8000018c: 21df1263 bne t5,t4,80000390 <fail> + +0000000080000190 <test_9>: + 80000190: 800000b7 lui ra,0x80000 + 80000194: fff0809b addiw ra,ra,-1 + 80000198: 00008f13 mv t5,ra + 8000019c: 80000eb7 lui t4,0x80000 + 800001a0: fffe8e9b addiw t4,t4,-1 + 800001a4: 00900193 li gp,9 + 800001a8: 1fdf1463 bne t5,t4,80000390 <fail> + +00000000800001ac <test_10>: + 800001ac: 800000b7 lui ra,0x80000 + 800001b0: fff0809b addiw ra,ra,-1 + 800001b4: 7ff08f13 addi t5,ra,2047 # ffffffff800007ff <_end+0xfffffffeffffe7ff> + 800001b8: 00100e9b addiw t4,zero,1 + 800001bc: 01fe9e93 slli t4,t4,0x1f + 800001c0: 7fee8e93 addi t4,t4,2046 # ffffffff800007fe <_end+0xfffffffeffffe7fe> + 800001c4: 00a00193 li gp,10 + 800001c8: 1ddf1463 bne t5,t4,80000390 <fail> + +00000000800001cc <test_11>: + 800001cc: 800000b7 lui ra,0x80000 + 800001d0: 7ff08f13 addi t5,ra,2047 # ffffffff800007ff <_end+0xfffffffeffffe7ff> + 800001d4: 80000eb7 lui t4,0x80000 + 800001d8: 7ffe8e9b addiw t4,t4,2047 + 800001dc: 00b00193 li gp,11 + 800001e0: 1bdf1863 bne t5,t4,80000390 <fail> + +00000000800001e4 <test_12>: + 800001e4: 800000b7 lui ra,0x80000 + 800001e8: fff0809b addiw ra,ra,-1 + 800001ec: 80008f13 addi t5,ra,-2048 # ffffffff7ffff800 <_end+0xfffffffeffffd800> + 800001f0: 7ffffeb7 lui t4,0x7ffff + 800001f4: 7ffe8e9b addiw t4,t4,2047 + 800001f8: 00c00193 li gp,12 + 800001fc: 19df1a63 bne t5,t4,80000390 <fail> + +0000000080000200 <test_13>: + 80000200: 00000093 li ra,0 + 80000204: fff08f13 addi t5,ra,-1 + 80000208: fff00e93 li t4,-1 + 8000020c: 00d00193 li gp,13 + 80000210: 19df1063 bne t5,t4,80000390 <fail> + +0000000080000214 <test_14>: + 80000214: fff00093 li ra,-1 + 80000218: 00108f13 addi t5,ra,1 + 8000021c: 00000e93 li t4,0 + 80000220: 00e00193 li gp,14 + 80000224: 17df1663 bne t5,t4,80000390 <fail> + +0000000080000228 <test_15>: + 80000228: fff00093 li ra,-1 + 8000022c: fff08f13 addi t5,ra,-1 + 80000230: ffe00e93 li t4,-2 + 80000234: 00f00193 li gp,15 + 80000238: 15df1c63 bne t5,t4,80000390 <fail> + +000000008000023c <test_16>: + 8000023c: 800000b7 lui ra,0x80000 + 80000240: fff0809b addiw ra,ra,-1 + 80000244: 00108f13 addi t5,ra,1 # ffffffff80000001 <_end+0xfffffffeffffe001> + 80000248: 00100e9b addiw t4,zero,1 + 8000024c: 01fe9e93 slli t4,t4,0x1f + 80000250: 01000193 li gp,16 + 80000254: 13df1e63 bne t5,t4,80000390 <fail> + +0000000080000258 <test_17>: + 80000258: 00d00093 li ra,13 + 8000025c: 00b08093 addi ra,ra,11 + 80000260: 01800e93 li t4,24 + 80000264: 01100193 li gp,17 + 80000268: 13d09463 bne ra,t4,80000390 <fail> + +000000008000026c <test_18>: + 8000026c: 00000213 li tp,0 + 80000270: 00d00093 li ra,13 + 80000274: 00b08f13 addi t5,ra,11 + 80000278: 000f0313 mv t1,t5 + 8000027c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000280: 00200293 li t0,2 + 80000284: fe5216e3 bne tp,t0,80000270 <test_18+0x4> + 80000288: 01800e93 li t4,24 + 8000028c: 01200193 li gp,18 + 80000290: 11d31063 bne t1,t4,80000390 <fail> + +0000000080000294 <test_19>: + 80000294: 00000213 li tp,0 + 80000298: 00d00093 li ra,13 + 8000029c: 00a08f13 addi t5,ra,10 + 800002a0: 00000013 nop + 800002a4: 000f0313 mv t1,t5 + 800002a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002ac: 00200293 li t0,2 + 800002b0: fe5214e3 bne tp,t0,80000298 <test_19+0x4> + 800002b4: 01700e93 li t4,23 + 800002b8: 01300193 li gp,19 + 800002bc: 0dd31a63 bne t1,t4,80000390 <fail> + +00000000800002c0 <test_20>: + 800002c0: 00000213 li tp,0 + 800002c4: 00d00093 li ra,13 + 800002c8: 00908f13 addi t5,ra,9 + 800002cc: 00000013 nop + 800002d0: 00000013 nop + 800002d4: 000f0313 mv t1,t5 + 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002dc: 00200293 li t0,2 + 800002e0: fe5212e3 bne tp,t0,800002c4 <test_20+0x4> + 800002e4: 01600e93 li t4,22 + 800002e8: 01400193 li gp,20 + 800002ec: 0bd31263 bne t1,t4,80000390 <fail> + +00000000800002f0 <test_21>: + 800002f0: 00000213 li tp,0 + 800002f4: 00d00093 li ra,13 + 800002f8: 00b08f13 addi t5,ra,11 + 800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000300: 00200293 li t0,2 + 80000304: fe5218e3 bne tp,t0,800002f4 <test_21+0x4> + 80000308: 01800e93 li t4,24 + 8000030c: 01500193 li gp,21 + 80000310: 09df1063 bne t5,t4,80000390 <fail> + +0000000080000314 <test_22>: + 80000314: 00000213 li tp,0 + 80000318: 00d00093 li ra,13 + 8000031c: 00000013 nop + 80000320: 00a08f13 addi t5,ra,10 + 80000324: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000328: 00200293 li t0,2 + 8000032c: fe5216e3 bne tp,t0,80000318 <test_22+0x4> + 80000330: 01700e93 li t4,23 + 80000334: 01600193 li gp,22 + 80000338: 05df1c63 bne t5,t4,80000390 <fail> + +000000008000033c <test_23>: + 8000033c: 00000213 li tp,0 + 80000340: 00d00093 li ra,13 + 80000344: 00000013 nop + 80000348: 00000013 nop + 8000034c: 00908f13 addi t5,ra,9 + 80000350: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000354: 00200293 li t0,2 + 80000358: fe5214e3 bne tp,t0,80000340 <test_23+0x4> + 8000035c: 01600e93 li t4,22 + 80000360: 01700193 li gp,23 + 80000364: 03df1663 bne t5,t4,80000390 <fail> + +0000000080000368 <test_24>: + 80000368: 02000093 li ra,32 + 8000036c: 02000e93 li t4,32 + 80000370: 01800193 li gp,24 + 80000374: 01d09e63 bne ra,t4,80000390 <fail> + +0000000080000378 <test_25>: + 80000378: 02100093 li ra,33 + 8000037c: 03208013 addi zero,ra,50 + 80000380: 00000e93 li t4,0 + 80000384: 01900193 li gp,25 + 80000388: 01d01463 bne zero,t4,80000390 <fail> + 8000038c: 00301c63 bne zero,gp,800003a4 <pass> + +0000000080000390 <fail>: + 80000390: 0ff0000f fence + 80000394: 00018063 beqz gp,80000394 <fail+0x4> + 80000398: 00119193 slli gp,gp,0x1 + 8000039c: 0011e193 ori gp,gp,1 + 800003a0: 00000073 ecall + +00000000800003a4 <pass>: + 800003a4: 0ff0000f fence + 800003a8: 00100193 li gp,1 + 800003ac: 00000073 ecall + 800003b0: c0001073 unimp + 800003b4: 0000 unimp + 800003b6: 0000 unimp + 800003b8: 0000 unimp + 800003ba: 0000 unimp + 800003bc: 0000 unimp + 800003be: 0000 unimp + 800003c0: 0000 unimp + 800003c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-addi.elf b/test/riscv/tests/rv64ui-p-addi.elf Binary files differnew file mode 100755 index 00000000..3cbc838d --- /dev/null +++ b/test/riscv/tests/rv64ui-p-addi.elf diff --git a/test/riscv/tests/rv64ui-p-addiw.dump b/test/riscv/tests/rv64ui-p-addiw.dump new file mode 100644 index 00000000..a84bd35c --- /dev/null +++ b/test/riscv/tests/rv64ui-p-addiw.dump @@ -0,0 +1,315 @@ + +rv64ui-p-addiw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 00008f1b sext.w t5,ra + 80000104: 00000e93 li t4,0 + 80000108: 00200193 li gp,2 + 8000010c: 27df1c63 bne t5,t4,80000384 <fail> + +0000000080000110 <test_3>: + 80000110: 00100093 li ra,1 + 80000114: 00108f1b addiw t5,ra,1 + 80000118: 00200e93 li t4,2 + 8000011c: 00300193 li gp,3 + 80000120: 27df1263 bne t5,t4,80000384 <fail> + +0000000080000124 <test_4>: + 80000124: 00300093 li ra,3 + 80000128: 00708f1b addiw t5,ra,7 + 8000012c: 00a00e93 li t4,10 + 80000130: 00400193 li gp,4 + 80000134: 25df1863 bne t5,t4,80000384 <fail> + +0000000080000138 <test_5>: + 80000138: 00000093 li ra,0 + 8000013c: 80008f1b addiw t5,ra,-2048 + 80000140: 80000e93 li t4,-2048 + 80000144: 00500193 li gp,5 + 80000148: 23df1e63 bne t5,t4,80000384 <fail> + +000000008000014c <test_6>: + 8000014c: 800000b7 lui ra,0x80000 + 80000150: 00008f1b sext.w t5,ra + 80000154: 80000eb7 lui t4,0x80000 + 80000158: 00600193 li gp,6 + 8000015c: 23df1463 bne t5,t4,80000384 <fail> + +0000000080000160 <test_7>: + 80000160: 800000b7 lui ra,0x80000 + 80000164: 80008f1b addiw t5,ra,-2048 + 80000168: 80000eb7 lui t4,0x80000 + 8000016c: 800e8e9b addiw t4,t4,-2048 + 80000170: 00700193 li gp,7 + 80000174: 21df1863 bne t5,t4,80000384 <fail> + +0000000080000178 <test_8>: + 80000178: 00000093 li ra,0 + 8000017c: 7ff08f1b addiw t5,ra,2047 + 80000180: 7ff00e93 li t4,2047 + 80000184: 00800193 li gp,8 + 80000188: 1fdf1e63 bne t5,t4,80000384 <fail> + +000000008000018c <test_9>: + 8000018c: 800000b7 lui ra,0x80000 + 80000190: fff0809b addiw ra,ra,-1 + 80000194: 00008f1b sext.w t5,ra + 80000198: 80000eb7 lui t4,0x80000 + 8000019c: fffe8e9b addiw t4,t4,-1 + 800001a0: 00900193 li gp,9 + 800001a4: 1fdf1063 bne t5,t4,80000384 <fail> + +00000000800001a8 <test_10>: + 800001a8: 800000b7 lui ra,0x80000 + 800001ac: fff0809b addiw ra,ra,-1 + 800001b0: 7ff08f1b addiw t5,ra,2047 + 800001b4: 80000eb7 lui t4,0x80000 + 800001b8: 7fee8e9b addiw t4,t4,2046 + 800001bc: 00a00193 li gp,10 + 800001c0: 1ddf1263 bne t5,t4,80000384 <fail> + +00000000800001c4 <test_11>: + 800001c4: 800000b7 lui ra,0x80000 + 800001c8: 7ff08f1b addiw t5,ra,2047 + 800001cc: 80000eb7 lui t4,0x80000 + 800001d0: 7ffe8e9b addiw t4,t4,2047 + 800001d4: 00b00193 li gp,11 + 800001d8: 1bdf1663 bne t5,t4,80000384 <fail> + +00000000800001dc <test_12>: + 800001dc: 800000b7 lui ra,0x80000 + 800001e0: fff0809b addiw ra,ra,-1 + 800001e4: 80008f1b addiw t5,ra,-2048 + 800001e8: 7ffffeb7 lui t4,0x7ffff + 800001ec: 7ffe8e9b addiw t4,t4,2047 + 800001f0: 00c00193 li gp,12 + 800001f4: 19df1863 bne t5,t4,80000384 <fail> + +00000000800001f8 <test_13>: + 800001f8: 00000093 li ra,0 + 800001fc: fff08f1b addiw t5,ra,-1 + 80000200: fff00e93 li t4,-1 + 80000204: 00d00193 li gp,13 + 80000208: 17df1e63 bne t5,t4,80000384 <fail> + +000000008000020c <test_14>: + 8000020c: fff00093 li ra,-1 + 80000210: 00108f1b addiw t5,ra,1 + 80000214: 00000e93 li t4,0 + 80000218: 00e00193 li gp,14 + 8000021c: 17df1463 bne t5,t4,80000384 <fail> + +0000000080000220 <test_15>: + 80000220: fff00093 li ra,-1 + 80000224: fff08f1b addiw t5,ra,-1 + 80000228: ffe00e93 li t4,-2 + 8000022c: 00f00193 li gp,15 + 80000230: 15df1a63 bne t5,t4,80000384 <fail> + +0000000080000234 <test_16>: + 80000234: 800000b7 lui ra,0x80000 + 80000238: fff0809b addiw ra,ra,-1 + 8000023c: 00108f1b addiw t5,ra,1 + 80000240: 80000eb7 lui t4,0x80000 + 80000244: 01000193 li gp,16 + 80000248: 13df1e63 bne t5,t4,80000384 <fail> + +000000008000024c <test_17>: + 8000024c: 00d00093 li ra,13 + 80000250: 00b0809b addiw ra,ra,11 + 80000254: 01800e93 li t4,24 + 80000258: 01100193 li gp,17 + 8000025c: 13d09463 bne ra,t4,80000384 <fail> + +0000000080000260 <test_18>: + 80000260: 00000213 li tp,0 + 80000264: 00d00093 li ra,13 + 80000268: 00b08f1b addiw t5,ra,11 + 8000026c: 000f0313 mv t1,t5 + 80000270: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000274: 00200293 li t0,2 + 80000278: fe5216e3 bne tp,t0,80000264 <test_18+0x4> + 8000027c: 01800e93 li t4,24 + 80000280: 01200193 li gp,18 + 80000284: 11d31063 bne t1,t4,80000384 <fail> + +0000000080000288 <test_19>: + 80000288: 00000213 li tp,0 + 8000028c: 00d00093 li ra,13 + 80000290: 00a08f1b addiw t5,ra,10 + 80000294: 00000013 nop + 80000298: 000f0313 mv t1,t5 + 8000029c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a0: 00200293 li t0,2 + 800002a4: fe5214e3 bne tp,t0,8000028c <test_19+0x4> + 800002a8: 01700e93 li t4,23 + 800002ac: 01300193 li gp,19 + 800002b0: 0dd31a63 bne t1,t4,80000384 <fail> + +00000000800002b4 <test_20>: + 800002b4: 00000213 li tp,0 + 800002b8: 00d00093 li ra,13 + 800002bc: 00908f1b addiw t5,ra,9 + 800002c0: 00000013 nop + 800002c4: 00000013 nop + 800002c8: 000f0313 mv t1,t5 + 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002d0: 00200293 li t0,2 + 800002d4: fe5212e3 bne tp,t0,800002b8 <test_20+0x4> + 800002d8: 01600e93 li t4,22 + 800002dc: 01400193 li gp,20 + 800002e0: 0bd31263 bne t1,t4,80000384 <fail> + +00000000800002e4 <test_21>: + 800002e4: 00000213 li tp,0 + 800002e8: 00d00093 li ra,13 + 800002ec: 00b08f1b addiw t5,ra,11 + 800002f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002f4: 00200293 li t0,2 + 800002f8: fe5218e3 bne tp,t0,800002e8 <test_21+0x4> + 800002fc: 01800e93 li t4,24 + 80000300: 01500193 li gp,21 + 80000304: 09df1063 bne t5,t4,80000384 <fail> + +0000000080000308 <test_22>: + 80000308: 00000213 li tp,0 + 8000030c: 00d00093 li ra,13 + 80000310: 00000013 nop + 80000314: 00a08f1b addiw t5,ra,10 + 80000318: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000031c: 00200293 li t0,2 + 80000320: fe5216e3 bne tp,t0,8000030c <test_22+0x4> + 80000324: 01700e93 li t4,23 + 80000328: 01600193 li gp,22 + 8000032c: 05df1c63 bne t5,t4,80000384 <fail> + +0000000080000330 <test_23>: + 80000330: 00000213 li tp,0 + 80000334: 00d00093 li ra,13 + 80000338: 00000013 nop + 8000033c: 00000013 nop + 80000340: 00908f1b addiw t5,ra,9 + 80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000348: 00200293 li t0,2 + 8000034c: fe5214e3 bne tp,t0,80000334 <test_23+0x4> + 80000350: 01600e93 li t4,22 + 80000354: 01700193 li gp,23 + 80000358: 03df1663 bne t5,t4,80000384 <fail> + +000000008000035c <test_24>: + 8000035c: 0200009b addiw ra,zero,32 + 80000360: 02000e93 li t4,32 + 80000364: 01800193 li gp,24 + 80000368: 01d09e63 bne ra,t4,80000384 <fail> + +000000008000036c <test_25>: + 8000036c: 02100093 li ra,33 + 80000370: 0320801b addiw zero,ra,50 + 80000374: 00000e93 li t4,0 + 80000378: 01900193 li gp,25 + 8000037c: 01d01463 bne zero,t4,80000384 <fail> + 80000380: 00301c63 bne zero,gp,80000398 <pass> + +0000000080000384 <fail>: + 80000384: 0ff0000f fence + 80000388: 00018063 beqz gp,80000388 <fail+0x4> + 8000038c: 00119193 slli gp,gp,0x1 + 80000390: 0011e193 ori gp,gp,1 + 80000394: 00000073 ecall + +0000000080000398 <pass>: + 80000398: 0ff0000f fence + 8000039c: 00100193 li gp,1 + 800003a0: 00000073 ecall + 800003a4: c0001073 unimp + 800003a8: 0000 unimp + 800003aa: 0000 unimp + 800003ac: 0000 unimp + 800003ae: 0000 unimp + 800003b0: 0000 unimp + 800003b2: 0000 unimp + 800003b4: 0000 unimp + 800003b6: 0000 unimp + 800003b8: 0000 unimp + 800003ba: 0000 unimp + 800003bc: 0000 unimp + 800003be: 0000 unimp + 800003c0: 0000 unimp + 800003c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-addiw.elf b/test/riscv/tests/rv64ui-p-addiw.elf Binary files differnew file mode 100755 index 00000000..adee4ac2 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-addiw.elf diff --git a/test/riscv/tests/rv64ui-p-addw.dump b/test/riscv/tests/rv64ui-p-addw.dump new file mode 100644 index 00000000..626af6d9 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-addw.dump @@ -0,0 +1,479 @@ + +rv64ui-p-addw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 00000113 li sp,0 + 80000104: 00208f3b addw t5,ra,sp + 80000108: 00000e93 li t4,0 + 8000010c: 00200193 li gp,2 + 80000110: 4ddf1663 bne t5,t4,800005dc <fail> + +0000000080000114 <test_3>: + 80000114: 00100093 li ra,1 + 80000118: 00100113 li sp,1 + 8000011c: 00208f3b addw t5,ra,sp + 80000120: 00200e93 li t4,2 + 80000124: 00300193 li gp,3 + 80000128: 4bdf1a63 bne t5,t4,800005dc <fail> + +000000008000012c <test_4>: + 8000012c: 00300093 li ra,3 + 80000130: 00700113 li sp,7 + 80000134: 00208f3b addw t5,ra,sp + 80000138: 00a00e93 li t4,10 + 8000013c: 00400193 li gp,4 + 80000140: 49df1e63 bne t5,t4,800005dc <fail> + +0000000080000144 <test_5>: + 80000144: 00000093 li ra,0 + 80000148: ffff8137 lui sp,0xffff8 + 8000014c: 00208f3b addw t5,ra,sp + 80000150: ffff8eb7 lui t4,0xffff8 + 80000154: 00500193 li gp,5 + 80000158: 49df1263 bne t5,t4,800005dc <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 00000113 li sp,0 + 80000164: 00208f3b addw t5,ra,sp + 80000168: 80000eb7 lui t4,0x80000 + 8000016c: 00600193 li gp,6 + 80000170: 47df1663 bne t5,t4,800005dc <fail> + +0000000080000174 <test_7>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: ffff8137 lui sp,0xffff8 + 8000017c: 00208f3b addw t5,ra,sp + 80000180: 7fff8eb7 lui t4,0x7fff8 + 80000184: 00700193 li gp,7 + 80000188: 45df1a63 bne t5,t4,800005dc <fail> + +000000008000018c <test_8>: + 8000018c: 00000093 li ra,0 + 80000190: 00008137 lui sp,0x8 + 80000194: fff1011b addiw sp,sp,-1 + 80000198: 00208f3b addw t5,ra,sp + 8000019c: 00008eb7 lui t4,0x8 + 800001a0: fffe8e9b addiw t4,t4,-1 + 800001a4: 00800193 li gp,8 + 800001a8: 43df1a63 bne t5,t4,800005dc <fail> + +00000000800001ac <test_9>: + 800001ac: 800000b7 lui ra,0x80000 + 800001b0: fff0809b addiw ra,ra,-1 + 800001b4: 00000113 li sp,0 + 800001b8: 00208f3b addw t5,ra,sp + 800001bc: 80000eb7 lui t4,0x80000 + 800001c0: fffe8e9b addiw t4,t4,-1 + 800001c4: 00900193 li gp,9 + 800001c8: 41df1a63 bne t5,t4,800005dc <fail> + +00000000800001cc <test_10>: + 800001cc: 800000b7 lui ra,0x80000 + 800001d0: fff0809b addiw ra,ra,-1 + 800001d4: 00008137 lui sp,0x8 + 800001d8: fff1011b addiw sp,sp,-1 + 800001dc: 00208f3b addw t5,ra,sp + 800001e0: 80008eb7 lui t4,0x80008 + 800001e4: ffee8e9b addiw t4,t4,-2 + 800001e8: 00a00193 li gp,10 + 800001ec: 3fdf1863 bne t5,t4,800005dc <fail> + +00000000800001f0 <test_11>: + 800001f0: 800000b7 lui ra,0x80000 + 800001f4: 00008137 lui sp,0x8 + 800001f8: fff1011b addiw sp,sp,-1 + 800001fc: 00208f3b addw t5,ra,sp + 80000200: 80008eb7 lui t4,0x80008 + 80000204: fffe8e9b addiw t4,t4,-1 + 80000208: 00b00193 li gp,11 + 8000020c: 3ddf1863 bne t5,t4,800005dc <fail> + +0000000080000210 <test_12>: + 80000210: 800000b7 lui ra,0x80000 + 80000214: fff0809b addiw ra,ra,-1 + 80000218: ffff8137 lui sp,0xffff8 + 8000021c: 00208f3b addw t5,ra,sp + 80000220: 7fff8eb7 lui t4,0x7fff8 + 80000224: fffe8e9b addiw t4,t4,-1 + 80000228: 00c00193 li gp,12 + 8000022c: 3bdf1863 bne t5,t4,800005dc <fail> + +0000000080000230 <test_13>: + 80000230: 00000093 li ra,0 + 80000234: fff00113 li sp,-1 + 80000238: 00208f3b addw t5,ra,sp + 8000023c: fff00e93 li t4,-1 + 80000240: 00d00193 li gp,13 + 80000244: 39df1c63 bne t5,t4,800005dc <fail> + +0000000080000248 <test_14>: + 80000248: fff00093 li ra,-1 + 8000024c: 00100113 li sp,1 + 80000250: 00208f3b addw t5,ra,sp + 80000254: 00000e93 li t4,0 + 80000258: 00e00193 li gp,14 + 8000025c: 39df1063 bne t5,t4,800005dc <fail> + +0000000080000260 <test_15>: + 80000260: fff00093 li ra,-1 + 80000264: fff00113 li sp,-1 + 80000268: 00208f3b addw t5,ra,sp + 8000026c: ffe00e93 li t4,-2 + 80000270: 00f00193 li gp,15 + 80000274: 37df1463 bne t5,t4,800005dc <fail> + +0000000080000278 <test_16>: + 80000278: 00100093 li ra,1 + 8000027c: 80000137 lui sp,0x80000 + 80000280: fff1011b addiw sp,sp,-1 + 80000284: 00208f3b addw t5,ra,sp + 80000288: 80000eb7 lui t4,0x80000 + 8000028c: 01000193 li gp,16 + 80000290: 35df1663 bne t5,t4,800005dc <fail> + +0000000080000294 <test_17>: + 80000294: 00d00093 li ra,13 + 80000298: 00b00113 li sp,11 + 8000029c: 002080bb addw ra,ra,sp + 800002a0: 01800e93 li t4,24 + 800002a4: 01100193 li gp,17 + 800002a8: 33d09a63 bne ra,t4,800005dc <fail> + +00000000800002ac <test_18>: + 800002ac: 00e00093 li ra,14 + 800002b0: 00b00113 li sp,11 + 800002b4: 0020813b addw sp,ra,sp + 800002b8: 01900e93 li t4,25 + 800002bc: 01200193 li gp,18 + 800002c0: 31d11e63 bne sp,t4,800005dc <fail> + +00000000800002c4 <test_19>: + 800002c4: 00d00093 li ra,13 + 800002c8: 001080bb addw ra,ra,ra + 800002cc: 01a00e93 li t4,26 + 800002d0: 01300193 li gp,19 + 800002d4: 31d09463 bne ra,t4,800005dc <fail> + +00000000800002d8 <test_20>: + 800002d8: 00000213 li tp,0 + 800002dc: 00d00093 li ra,13 + 800002e0: 00b00113 li sp,11 + 800002e4: 00208f3b addw t5,ra,sp + 800002e8: 000f0313 mv t1,t5 + 800002ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002f0: 00200293 li t0,2 + 800002f4: fe5214e3 bne tp,t0,800002dc <test_20+0x4> + 800002f8: 01800e93 li t4,24 + 800002fc: 01400193 li gp,20 + 80000300: 2dd31e63 bne t1,t4,800005dc <fail> + +0000000080000304 <test_21>: + 80000304: 00000213 li tp,0 + 80000308: 00e00093 li ra,14 + 8000030c: 00b00113 li sp,11 + 80000310: 00208f3b addw t5,ra,sp + 80000314: 00000013 nop + 80000318: 000f0313 mv t1,t5 + 8000031c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000320: 00200293 li t0,2 + 80000324: fe5212e3 bne tp,t0,80000308 <test_21+0x4> + 80000328: 01900e93 li t4,25 + 8000032c: 01500193 li gp,21 + 80000330: 2bd31663 bne t1,t4,800005dc <fail> + +0000000080000334 <test_22>: + 80000334: 00000213 li tp,0 + 80000338: 00f00093 li ra,15 + 8000033c: 00b00113 li sp,11 + 80000340: 00208f3b addw t5,ra,sp + 80000344: 00000013 nop + 80000348: 00000013 nop + 8000034c: 000f0313 mv t1,t5 + 80000350: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000354: 00200293 li t0,2 + 80000358: fe5210e3 bne tp,t0,80000338 <test_22+0x4> + 8000035c: 01a00e93 li t4,26 + 80000360: 01600193 li gp,22 + 80000364: 27d31c63 bne t1,t4,800005dc <fail> + +0000000080000368 <test_23>: + 80000368: 00000213 li tp,0 + 8000036c: 00d00093 li ra,13 + 80000370: 00b00113 li sp,11 + 80000374: 00208f3b addw t5,ra,sp + 80000378: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000037c: 00200293 li t0,2 + 80000380: fe5216e3 bne tp,t0,8000036c <test_23+0x4> + 80000384: 01800e93 li t4,24 + 80000388: 01700193 li gp,23 + 8000038c: 25df1863 bne t5,t4,800005dc <fail> + +0000000080000390 <test_24>: + 80000390: 00000213 li tp,0 + 80000394: 00e00093 li ra,14 + 80000398: 00b00113 li sp,11 + 8000039c: 00000013 nop + 800003a0: 00208f3b addw t5,ra,sp + 800003a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003a8: 00200293 li t0,2 + 800003ac: fe5214e3 bne tp,t0,80000394 <test_24+0x4> + 800003b0: 01900e93 li t4,25 + 800003b4: 01800193 li gp,24 + 800003b8: 23df1263 bne t5,t4,800005dc <fail> + +00000000800003bc <test_25>: + 800003bc: 00000213 li tp,0 + 800003c0: 00f00093 li ra,15 + 800003c4: 00b00113 li sp,11 + 800003c8: 00000013 nop + 800003cc: 00000013 nop + 800003d0: 00208f3b addw t5,ra,sp + 800003d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003d8: 00200293 li t0,2 + 800003dc: fe5212e3 bne tp,t0,800003c0 <test_25+0x4> + 800003e0: 01a00e93 li t4,26 + 800003e4: 01900193 li gp,25 + 800003e8: 1fdf1a63 bne t5,t4,800005dc <fail> + +00000000800003ec <test_26>: + 800003ec: 00000213 li tp,0 + 800003f0: 00d00093 li ra,13 + 800003f4: 00000013 nop + 800003f8: 00b00113 li sp,11 + 800003fc: 00208f3b addw t5,ra,sp + 80000400: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000404: 00200293 li t0,2 + 80000408: fe5214e3 bne tp,t0,800003f0 <test_26+0x4> + 8000040c: 01800e93 li t4,24 + 80000410: 01a00193 li gp,26 + 80000414: 1ddf1463 bne t5,t4,800005dc <fail> + +0000000080000418 <test_27>: + 80000418: 00000213 li tp,0 + 8000041c: 00e00093 li ra,14 + 80000420: 00000013 nop + 80000424: 00b00113 li sp,11 + 80000428: 00000013 nop + 8000042c: 00208f3b addw t5,ra,sp + 80000430: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000434: 00200293 li t0,2 + 80000438: fe5212e3 bne tp,t0,8000041c <test_27+0x4> + 8000043c: 01900e93 li t4,25 + 80000440: 01b00193 li gp,27 + 80000444: 19df1c63 bne t5,t4,800005dc <fail> + +0000000080000448 <test_28>: + 80000448: 00000213 li tp,0 + 8000044c: 00f00093 li ra,15 + 80000450: 00000013 nop + 80000454: 00000013 nop + 80000458: 00b00113 li sp,11 + 8000045c: 00208f3b addw t5,ra,sp + 80000460: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000464: 00200293 li t0,2 + 80000468: fe5212e3 bne tp,t0,8000044c <test_28+0x4> + 8000046c: 01a00e93 li t4,26 + 80000470: 01c00193 li gp,28 + 80000474: 17df1463 bne t5,t4,800005dc <fail> + +0000000080000478 <test_29>: + 80000478: 00000213 li tp,0 + 8000047c: 00b00113 li sp,11 + 80000480: 00d00093 li ra,13 + 80000484: 00208f3b addw t5,ra,sp + 80000488: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000048c: 00200293 li t0,2 + 80000490: fe5216e3 bne tp,t0,8000047c <test_29+0x4> + 80000494: 01800e93 li t4,24 + 80000498: 01d00193 li gp,29 + 8000049c: 15df1063 bne t5,t4,800005dc <fail> + +00000000800004a0 <test_30>: + 800004a0: 00000213 li tp,0 + 800004a4: 00b00113 li sp,11 + 800004a8: 00e00093 li ra,14 + 800004ac: 00000013 nop + 800004b0: 00208f3b addw t5,ra,sp + 800004b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004b8: 00200293 li t0,2 + 800004bc: fe5214e3 bne tp,t0,800004a4 <test_30+0x4> + 800004c0: 01900e93 li t4,25 + 800004c4: 01e00193 li gp,30 + 800004c8: 11df1a63 bne t5,t4,800005dc <fail> + +00000000800004cc <test_31>: + 800004cc: 00000213 li tp,0 + 800004d0: 00b00113 li sp,11 + 800004d4: 00f00093 li ra,15 + 800004d8: 00000013 nop + 800004dc: 00000013 nop + 800004e0: 00208f3b addw t5,ra,sp + 800004e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004e8: 00200293 li t0,2 + 800004ec: fe5212e3 bne tp,t0,800004d0 <test_31+0x4> + 800004f0: 01a00e93 li t4,26 + 800004f4: 01f00193 li gp,31 + 800004f8: 0fdf1263 bne t5,t4,800005dc <fail> + +00000000800004fc <test_32>: + 800004fc: 00000213 li tp,0 + 80000500: 00b00113 li sp,11 + 80000504: 00000013 nop + 80000508: 00d00093 li ra,13 + 8000050c: 00208f3b addw t5,ra,sp + 80000510: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000514: 00200293 li t0,2 + 80000518: fe5214e3 bne tp,t0,80000500 <test_32+0x4> + 8000051c: 01800e93 li t4,24 + 80000520: 02000193 li gp,32 + 80000524: 0bdf1c63 bne t5,t4,800005dc <fail> + +0000000080000528 <test_33>: + 80000528: 00000213 li tp,0 + 8000052c: 00b00113 li sp,11 + 80000530: 00000013 nop + 80000534: 00e00093 li ra,14 + 80000538: 00000013 nop + 8000053c: 00208f3b addw t5,ra,sp + 80000540: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000544: 00200293 li t0,2 + 80000548: fe5212e3 bne tp,t0,8000052c <test_33+0x4> + 8000054c: 01900e93 li t4,25 + 80000550: 02100193 li gp,33 + 80000554: 09df1463 bne t5,t4,800005dc <fail> + +0000000080000558 <test_34>: + 80000558: 00000213 li tp,0 + 8000055c: 00b00113 li sp,11 + 80000560: 00000013 nop + 80000564: 00000013 nop + 80000568: 00f00093 li ra,15 + 8000056c: 00208f3b addw t5,ra,sp + 80000570: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000574: 00200293 li t0,2 + 80000578: fe5212e3 bne tp,t0,8000055c <test_34+0x4> + 8000057c: 01a00e93 li t4,26 + 80000580: 02200193 li gp,34 + 80000584: 05df1c63 bne t5,t4,800005dc <fail> + +0000000080000588 <test_35>: + 80000588: 00f00093 li ra,15 + 8000058c: 0010013b addw sp,zero,ra + 80000590: 00f00e93 li t4,15 + 80000594: 02300193 li gp,35 + 80000598: 05d11263 bne sp,t4,800005dc <fail> + +000000008000059c <test_36>: + 8000059c: 02000093 li ra,32 + 800005a0: 0000813b addw sp,ra,zero + 800005a4: 02000e93 li t4,32 + 800005a8: 02400193 li gp,36 + 800005ac: 03d11863 bne sp,t4,800005dc <fail> + +00000000800005b0 <test_37>: + 800005b0: 000000bb addw ra,zero,zero + 800005b4: 00000e93 li t4,0 + 800005b8: 02500193 li gp,37 + 800005bc: 03d09063 bne ra,t4,800005dc <fail> + +00000000800005c0 <test_38>: + 800005c0: 01000093 li ra,16 + 800005c4: 01e00113 li sp,30 + 800005c8: 0020803b addw zero,ra,sp + 800005cc: 00000e93 li t4,0 + 800005d0: 02600193 li gp,38 + 800005d4: 01d01463 bne zero,t4,800005dc <fail> + 800005d8: 00301c63 bne zero,gp,800005f0 <pass> + +00000000800005dc <fail>: + 800005dc: 0ff0000f fence + 800005e0: 00018063 beqz gp,800005e0 <fail+0x4> + 800005e4: 00119193 slli gp,gp,0x1 + 800005e8: 0011e193 ori gp,gp,1 + 800005ec: 00000073 ecall + +00000000800005f0 <pass>: + 800005f0: 0ff0000f fence + 800005f4: 00100193 li gp,1 + 800005f8: 00000073 ecall + 800005fc: c0001073 unimp + 80000600: 0000 unimp + 80000602: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-addw.elf b/test/riscv/tests/rv64ui-p-addw.elf Binary files differnew file mode 100755 index 00000000..b36a71c1 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-addw.elf diff --git a/test/riscv/tests/rv64ui-p-and.dump b/test/riscv/tests/rv64ui-p-and.dump new file mode 100644 index 00000000..5851df86 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-and.dump @@ -0,0 +1,491 @@ + +rv64ui-p-and: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 000100b7 lui ra,0x10 + 80000100: f010809b addiw ra,ra,-255 + 80000104: 01009093 slli ra,ra,0x10 + 80000108: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 8000010c: 0f0f1137 lui sp,0xf0f1 + 80000110: f0f1011b addiw sp,sp,-241 + 80000114: 0020ff33 and t5,ra,sp + 80000118: 0f001eb7 lui t4,0xf001 + 8000011c: f00e8e9b addiw t4,t4,-256 + 80000120: 00200193 li gp,2 + 80000124: 53df1863 bne t5,t4,80000654 <fail> + +0000000080000128 <test_3>: + 80000128: 0ff010b7 lui ra,0xff01 + 8000012c: ff00809b addiw ra,ra,-16 + 80000130: 000f1137 lui sp,0xf1 + 80000134: f0f1011b addiw sp,sp,-241 + 80000138: 00c11113 slli sp,sp,0xc + 8000013c: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80000140: 0020ff33 and t5,ra,sp + 80000144: 00f00eb7 lui t4,0xf00 + 80000148: 0f0e8e9b addiw t4,t4,240 + 8000014c: 00300193 li gp,3 + 80000150: 51df1263 bne t5,t4,80000654 <fail> + +0000000080000154 <test_4>: + 80000154: 00ff00b7 lui ra,0xff0 + 80000158: 0ff0809b addiw ra,ra,255 + 8000015c: 0f0f1137 lui sp,0xf0f1 + 80000160: f0f1011b addiw sp,sp,-241 + 80000164: 0020ff33 and t5,ra,sp + 80000168: 000f0eb7 lui t4,0xf0 + 8000016c: 00fe8e9b addiw t4,t4,15 + 80000170: 00400193 li gp,4 + 80000174: 4fdf1063 bne t5,t4,80000654 <fail> + +0000000080000178 <test_5>: + 80000178: 000f00b7 lui ra,0xf0 + 8000017c: 0ff0809b addiw ra,ra,255 + 80000180: 00c09093 slli ra,ra,0xc + 80000184: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> + 80000188: 000f1137 lui sp,0xf1 + 8000018c: f0f1011b addiw sp,sp,-241 + 80000190: 00c11113 slli sp,sp,0xc + 80000194: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80000198: 0020ff33 and t5,ra,sp + 8000019c: 000f0eb7 lui t4,0xf0 + 800001a0: 00fe8e9b addiw t4,t4,15 + 800001a4: 00ce9e93 slli t4,t4,0xc + 800001a8: 00500193 li gp,5 + 800001ac: 4bdf1463 bne t5,t4,80000654 <fail> + +00000000800001b0 <test_6>: + 800001b0: 000100b7 lui ra,0x10 + 800001b4: f010809b addiw ra,ra,-255 + 800001b8: 01009093 slli ra,ra,0x10 + 800001bc: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 800001c0: 0f0f1137 lui sp,0xf0f1 + 800001c4: f0f1011b addiw sp,sp,-241 + 800001c8: 0020f0b3 and ra,ra,sp + 800001cc: 0f001eb7 lui t4,0xf001 + 800001d0: f00e8e9b addiw t4,t4,-256 + 800001d4: 00600193 li gp,6 + 800001d8: 47d09e63 bne ra,t4,80000654 <fail> + +00000000800001dc <test_7>: + 800001dc: 0ff010b7 lui ra,0xff01 + 800001e0: ff00809b addiw ra,ra,-16 + 800001e4: 000f1137 lui sp,0xf1 + 800001e8: f0f1011b addiw sp,sp,-241 + 800001ec: 00c11113 slli sp,sp,0xc + 800001f0: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 800001f4: 0020f133 and sp,ra,sp + 800001f8: 00f00eb7 lui t4,0xf00 + 800001fc: 0f0e8e9b addiw t4,t4,240 + 80000200: 00700193 li gp,7 + 80000204: 45d11863 bne sp,t4,80000654 <fail> + +0000000080000208 <test_8>: + 80000208: 000100b7 lui ra,0x10 + 8000020c: f010809b addiw ra,ra,-255 + 80000210: 01009093 slli ra,ra,0x10 + 80000214: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000218: 0010f0b3 and ra,ra,ra + 8000021c: 00010eb7 lui t4,0x10 + 80000220: f01e8e9b addiw t4,t4,-255 + 80000224: 010e9e93 slli t4,t4,0x10 + 80000228: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 8000022c: 00800193 li gp,8 + 80000230: 43d09263 bne ra,t4,80000654 <fail> + +0000000080000234 <test_9>: + 80000234: 00000213 li tp,0 + 80000238: 000100b7 lui ra,0x10 + 8000023c: f010809b addiw ra,ra,-255 + 80000240: 01009093 slli ra,ra,0x10 + 80000244: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000248: 0f0f1137 lui sp,0xf0f1 + 8000024c: f0f1011b addiw sp,sp,-241 + 80000250: 0020ff33 and t5,ra,sp + 80000254: 000f0313 mv t1,t5 + 80000258: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000025c: 00200293 li t0,2 + 80000260: fc521ce3 bne tp,t0,80000238 <test_9+0x4> + 80000264: 0f001eb7 lui t4,0xf001 + 80000268: f00e8e9b addiw t4,t4,-256 + 8000026c: 00900193 li gp,9 + 80000270: 3fd31263 bne t1,t4,80000654 <fail> + +0000000080000274 <test_10>: + 80000274: 00000213 li tp,0 + 80000278: 0ff010b7 lui ra,0xff01 + 8000027c: ff00809b addiw ra,ra,-16 + 80000280: 000f1137 lui sp,0xf1 + 80000284: f0f1011b addiw sp,sp,-241 + 80000288: 00c11113 slli sp,sp,0xc + 8000028c: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80000290: 0020ff33 and t5,ra,sp + 80000294: 00000013 nop + 80000298: 000f0313 mv t1,t5 + 8000029c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a0: 00200293 li t0,2 + 800002a4: fc521ae3 bne tp,t0,80000278 <test_10+0x4> + 800002a8: 00f00eb7 lui t4,0xf00 + 800002ac: 0f0e8e9b addiw t4,t4,240 + 800002b0: 00a00193 li gp,10 + 800002b4: 3bd31063 bne t1,t4,80000654 <fail> + +00000000800002b8 <test_11>: + 800002b8: 00000213 li tp,0 + 800002bc: 00ff00b7 lui ra,0xff0 + 800002c0: 0ff0809b addiw ra,ra,255 + 800002c4: 0f0f1137 lui sp,0xf0f1 + 800002c8: f0f1011b addiw sp,sp,-241 + 800002cc: 0020ff33 and t5,ra,sp + 800002d0: 00000013 nop + 800002d4: 00000013 nop + 800002d8: 000f0313 mv t1,t5 + 800002dc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002e0: 00200293 li t0,2 + 800002e4: fc521ce3 bne tp,t0,800002bc <test_11+0x4> + 800002e8: 000f0eb7 lui t4,0xf0 + 800002ec: 00fe8e9b addiw t4,t4,15 + 800002f0: 00b00193 li gp,11 + 800002f4: 37d31063 bne t1,t4,80000654 <fail> + +00000000800002f8 <test_12>: + 800002f8: 00000213 li tp,0 + 800002fc: 000100b7 lui ra,0x10 + 80000300: f010809b addiw ra,ra,-255 + 80000304: 01009093 slli ra,ra,0x10 + 80000308: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 8000030c: 0f0f1137 lui sp,0xf0f1 + 80000310: f0f1011b addiw sp,sp,-241 + 80000314: 0020ff33 and t5,ra,sp + 80000318: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000031c: 00200293 li t0,2 + 80000320: fc521ee3 bne tp,t0,800002fc <test_12+0x4> + 80000324: 0f001eb7 lui t4,0xf001 + 80000328: f00e8e9b addiw t4,t4,-256 + 8000032c: 00c00193 li gp,12 + 80000330: 33df1263 bne t5,t4,80000654 <fail> + +0000000080000334 <test_13>: + 80000334: 00000213 li tp,0 + 80000338: 0ff010b7 lui ra,0xff01 + 8000033c: ff00809b addiw ra,ra,-16 + 80000340: 000f1137 lui sp,0xf1 + 80000344: f0f1011b addiw sp,sp,-241 + 80000348: 00c11113 slli sp,sp,0xc + 8000034c: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80000350: 00000013 nop + 80000354: 0020ff33 and t5,ra,sp + 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000035c: 00200293 li t0,2 + 80000360: fc521ce3 bne tp,t0,80000338 <test_13+0x4> + 80000364: 00f00eb7 lui t4,0xf00 + 80000368: 0f0e8e9b addiw t4,t4,240 + 8000036c: 00d00193 li gp,13 + 80000370: 2fdf1263 bne t5,t4,80000654 <fail> + +0000000080000374 <test_14>: + 80000374: 00000213 li tp,0 + 80000378: 00ff00b7 lui ra,0xff0 + 8000037c: 0ff0809b addiw ra,ra,255 + 80000380: 0f0f1137 lui sp,0xf0f1 + 80000384: f0f1011b addiw sp,sp,-241 + 80000388: 00000013 nop + 8000038c: 00000013 nop + 80000390: 0020ff33 and t5,ra,sp + 80000394: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000398: 00200293 li t0,2 + 8000039c: fc521ee3 bne tp,t0,80000378 <test_14+0x4> + 800003a0: 000f0eb7 lui t4,0xf0 + 800003a4: 00fe8e9b addiw t4,t4,15 + 800003a8: 00e00193 li gp,14 + 800003ac: 2bdf1463 bne t5,t4,80000654 <fail> + +00000000800003b0 <test_15>: + 800003b0: 00000213 li tp,0 + 800003b4: 000100b7 lui ra,0x10 + 800003b8: f010809b addiw ra,ra,-255 + 800003bc: 01009093 slli ra,ra,0x10 + 800003c0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 800003c4: 00000013 nop + 800003c8: 0f0f1137 lui sp,0xf0f1 + 800003cc: f0f1011b addiw sp,sp,-241 + 800003d0: 0020ff33 and t5,ra,sp + 800003d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003d8: 00200293 li t0,2 + 800003dc: fc521ce3 bne tp,t0,800003b4 <test_15+0x4> + 800003e0: 0f001eb7 lui t4,0xf001 + 800003e4: f00e8e9b addiw t4,t4,-256 + 800003e8: 00f00193 li gp,15 + 800003ec: 27df1463 bne t5,t4,80000654 <fail> + +00000000800003f0 <test_16>: + 800003f0: 00000213 li tp,0 + 800003f4: 0ff010b7 lui ra,0xff01 + 800003f8: ff00809b addiw ra,ra,-16 + 800003fc: 00000013 nop + 80000400: 000f1137 lui sp,0xf1 + 80000404: f0f1011b addiw sp,sp,-241 + 80000408: 00c11113 slli sp,sp,0xc + 8000040c: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80000410: 00000013 nop + 80000414: 0020ff33 and t5,ra,sp + 80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000041c: 00200293 li t0,2 + 80000420: fc521ae3 bne tp,t0,800003f4 <test_16+0x4> + 80000424: 00f00eb7 lui t4,0xf00 + 80000428: 0f0e8e9b addiw t4,t4,240 + 8000042c: 01000193 li gp,16 + 80000430: 23df1263 bne t5,t4,80000654 <fail> + +0000000080000434 <test_17>: + 80000434: 00000213 li tp,0 + 80000438: 00ff00b7 lui ra,0xff0 + 8000043c: 0ff0809b addiw ra,ra,255 + 80000440: 00000013 nop + 80000444: 00000013 nop + 80000448: 0f0f1137 lui sp,0xf0f1 + 8000044c: f0f1011b addiw sp,sp,-241 + 80000450: 0020ff33 and t5,ra,sp + 80000454: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000458: 00200293 li t0,2 + 8000045c: fc521ee3 bne tp,t0,80000438 <test_17+0x4> + 80000460: 000f0eb7 lui t4,0xf0 + 80000464: 00fe8e9b addiw t4,t4,15 + 80000468: 01100193 li gp,17 + 8000046c: 1fdf1463 bne t5,t4,80000654 <fail> + +0000000080000470 <test_18>: + 80000470: 00000213 li tp,0 + 80000474: 0f0f1137 lui sp,0xf0f1 + 80000478: f0f1011b addiw sp,sp,-241 + 8000047c: 000100b7 lui ra,0x10 + 80000480: f010809b addiw ra,ra,-255 + 80000484: 01009093 slli ra,ra,0x10 + 80000488: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 8000048c: 0020ff33 and t5,ra,sp + 80000490: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000494: 00200293 li t0,2 + 80000498: fc521ee3 bne tp,t0,80000474 <test_18+0x4> + 8000049c: 0f001eb7 lui t4,0xf001 + 800004a0: f00e8e9b addiw t4,t4,-256 + 800004a4: 01200193 li gp,18 + 800004a8: 1bdf1663 bne t5,t4,80000654 <fail> + +00000000800004ac <test_19>: + 800004ac: 00000213 li tp,0 + 800004b0: 000f1137 lui sp,0xf1 + 800004b4: f0f1011b addiw sp,sp,-241 + 800004b8: 00c11113 slli sp,sp,0xc + 800004bc: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 800004c0: 0ff010b7 lui ra,0xff01 + 800004c4: ff00809b addiw ra,ra,-16 + 800004c8: 00000013 nop + 800004cc: 0020ff33 and t5,ra,sp + 800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004d4: 00200293 li t0,2 + 800004d8: fc521ce3 bne tp,t0,800004b0 <test_19+0x4> + 800004dc: 00f00eb7 lui t4,0xf00 + 800004e0: 0f0e8e9b addiw t4,t4,240 + 800004e4: 01300193 li gp,19 + 800004e8: 17df1663 bne t5,t4,80000654 <fail> + +00000000800004ec <test_20>: + 800004ec: 00000213 li tp,0 + 800004f0: 0f0f1137 lui sp,0xf0f1 + 800004f4: f0f1011b addiw sp,sp,-241 + 800004f8: 00ff00b7 lui ra,0xff0 + 800004fc: 0ff0809b addiw ra,ra,255 + 80000500: 00000013 nop + 80000504: 00000013 nop + 80000508: 0020ff33 and t5,ra,sp + 8000050c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000510: 00200293 li t0,2 + 80000514: fc521ee3 bne tp,t0,800004f0 <test_20+0x4> + 80000518: 000f0eb7 lui t4,0xf0 + 8000051c: 00fe8e9b addiw t4,t4,15 + 80000520: 01400193 li gp,20 + 80000524: 13df1863 bne t5,t4,80000654 <fail> + +0000000080000528 <test_21>: + 80000528: 00000213 li tp,0 + 8000052c: 0f0f1137 lui sp,0xf0f1 + 80000530: f0f1011b addiw sp,sp,-241 + 80000534: 00000013 nop + 80000538: 000100b7 lui ra,0x10 + 8000053c: f010809b addiw ra,ra,-255 + 80000540: 01009093 slli ra,ra,0x10 + 80000544: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000548: 0020ff33 and t5,ra,sp + 8000054c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000550: 00200293 li t0,2 + 80000554: fc521ce3 bne tp,t0,8000052c <test_21+0x4> + 80000558: 0f001eb7 lui t4,0xf001 + 8000055c: f00e8e9b addiw t4,t4,-256 + 80000560: 01500193 li gp,21 + 80000564: 0fdf1863 bne t5,t4,80000654 <fail> + +0000000080000568 <test_22>: + 80000568: 00000213 li tp,0 + 8000056c: 000f1137 lui sp,0xf1 + 80000570: f0f1011b addiw sp,sp,-241 + 80000574: 00c11113 slli sp,sp,0xc + 80000578: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 8000057c: 00000013 nop + 80000580: 0ff010b7 lui ra,0xff01 + 80000584: ff00809b addiw ra,ra,-16 + 80000588: 00000013 nop + 8000058c: 0020ff33 and t5,ra,sp + 80000590: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000594: 00200293 li t0,2 + 80000598: fc521ae3 bne tp,t0,8000056c <test_22+0x4> + 8000059c: 00f00eb7 lui t4,0xf00 + 800005a0: 0f0e8e9b addiw t4,t4,240 + 800005a4: 01600193 li gp,22 + 800005a8: 0bdf1663 bne t5,t4,80000654 <fail> + +00000000800005ac <test_23>: + 800005ac: 00000213 li tp,0 + 800005b0: 0f0f1137 lui sp,0xf0f1 + 800005b4: f0f1011b addiw sp,sp,-241 + 800005b8: 00000013 nop + 800005bc: 00000013 nop + 800005c0: 00ff00b7 lui ra,0xff0 + 800005c4: 0ff0809b addiw ra,ra,255 + 800005c8: 0020ff33 and t5,ra,sp + 800005cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005d0: 00200293 li t0,2 + 800005d4: fc521ee3 bne tp,t0,800005b0 <test_23+0x4> + 800005d8: 000f0eb7 lui t4,0xf0 + 800005dc: 00fe8e9b addiw t4,t4,15 + 800005e0: 01700193 li gp,23 + 800005e4: 07df1863 bne t5,t4,80000654 <fail> + +00000000800005e8 <test_24>: + 800005e8: 000100b7 lui ra,0x10 + 800005ec: f010809b addiw ra,ra,-255 + 800005f0: 01009093 slli ra,ra,0x10 + 800005f4: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 800005f8: 00107133 and sp,zero,ra + 800005fc: 00000e93 li t4,0 + 80000600: 01800193 li gp,24 + 80000604: 05d11863 bne sp,t4,80000654 <fail> + +0000000080000608 <test_25>: + 80000608: 00ff00b7 lui ra,0xff0 + 8000060c: 0ff0809b addiw ra,ra,255 + 80000610: 0000f133 and sp,ra,zero + 80000614: 00000e93 li t4,0 + 80000618: 01900193 li gp,25 + 8000061c: 03d11c63 bne sp,t4,80000654 <fail> + +0000000080000620 <test_26>: + 80000620: 000070b3 and ra,zero,zero + 80000624: 00000e93 li t4,0 + 80000628: 01a00193 li gp,26 + 8000062c: 03d09463 bne ra,t4,80000654 <fail> + +0000000080000630 <test_27>: + 80000630: 111110b7 lui ra,0x11111 + 80000634: 1110809b addiw ra,ra,273 + 80000638: 22222137 lui sp,0x22222 + 8000063c: 2221011b addiw sp,sp,546 + 80000640: 0020f033 and zero,ra,sp + 80000644: 00000e93 li t4,0 + 80000648: 01b00193 li gp,27 + 8000064c: 01d01463 bne zero,t4,80000654 <fail> + 80000650: 00301c63 bne zero,gp,80000668 <pass> + +0000000080000654 <fail>: + 80000654: 0ff0000f fence + 80000658: 00018063 beqz gp,80000658 <fail+0x4> + 8000065c: 00119193 slli gp,gp,0x1 + 80000660: 0011e193 ori gp,gp,1 + 80000664: 00000073 ecall + +0000000080000668 <pass>: + 80000668: 0ff0000f fence + 8000066c: 00100193 li gp,1 + 80000670: 00000073 ecall + 80000674: c0001073 unimp + 80000678: 0000 unimp + 8000067a: 0000 unimp + 8000067c: 0000 unimp + 8000067e: 0000 unimp + 80000680: 0000 unimp + 80000682: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-and.elf b/test/riscv/tests/rv64ui-p-and.elf Binary files differnew file mode 100755 index 00000000..66d59699 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-and.elf diff --git a/test/riscv/tests/rv64ui-p-andi.dump b/test/riscv/tests/rv64ui-p-andi.dump new file mode 100644 index 00000000..2349dd1c --- /dev/null +++ b/test/riscv/tests/rv64ui-p-andi.dump @@ -0,0 +1,265 @@ + +rv64ui-p-andi: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 000100b7 lui ra,0x10 + 80000100: f010809b addiw ra,ra,-255 + 80000104: 01009093 slli ra,ra,0x10 + 80000108: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 8000010c: f0f0ff13 andi t5,ra,-241 + 80000110: 00010eb7 lui t4,0x10 + 80000114: f01e8e9b addiw t4,t4,-255 + 80000118: 010e9e93 slli t4,t4,0x10 + 8000011c: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80000120: 00200193 li gp,2 + 80000124: 1ddf1863 bne t5,t4,800002f4 <fail> + +0000000080000128 <test_3>: + 80000128: 0ff010b7 lui ra,0xff01 + 8000012c: ff00809b addiw ra,ra,-16 + 80000130: 0f00ff13 andi t5,ra,240 + 80000134: 0f000e93 li t4,240 + 80000138: 00300193 li gp,3 + 8000013c: 1bdf1c63 bne t5,t4,800002f4 <fail> + +0000000080000140 <test_4>: + 80000140: 00ff00b7 lui ra,0xff0 + 80000144: 0ff0809b addiw ra,ra,255 + 80000148: 70f0ff13 andi t5,ra,1807 + 8000014c: 00f00e93 li t4,15 + 80000150: 00400193 li gp,4 + 80000154: 1bdf1063 bne t5,t4,800002f4 <fail> + +0000000080000158 <test_5>: + 80000158: 000f00b7 lui ra,0xf0 + 8000015c: 0ff0809b addiw ra,ra,255 + 80000160: 00c09093 slli ra,ra,0xc + 80000164: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> + 80000168: 0f00ff13 andi t5,ra,240 + 8000016c: 00000e93 li t4,0 + 80000170: 00500193 li gp,5 + 80000174: 19df1063 bne t5,t4,800002f4 <fail> + +0000000080000178 <test_6>: + 80000178: 000100b7 lui ra,0x10 + 8000017c: f010809b addiw ra,ra,-255 + 80000180: 01009093 slli ra,ra,0x10 + 80000184: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000188: 0f00f093 andi ra,ra,240 + 8000018c: 00000e93 li t4,0 + 80000190: 00600193 li gp,6 + 80000194: 17d09063 bne ra,t4,800002f4 <fail> + +0000000080000198 <test_7>: + 80000198: 00000213 li tp,0 + 8000019c: 0ff010b7 lui ra,0xff01 + 800001a0: ff00809b addiw ra,ra,-16 + 800001a4: 70f0ff13 andi t5,ra,1807 + 800001a8: 000f0313 mv t1,t5 + 800001ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800001b0: 00200293 li t0,2 + 800001b4: fe5214e3 bne tp,t0,8000019c <test_7+0x4> + 800001b8: 70000e93 li t4,1792 + 800001bc: 00700193 li gp,7 + 800001c0: 13d31a63 bne t1,t4,800002f4 <fail> + +00000000800001c4 <test_8>: + 800001c4: 00000213 li tp,0 + 800001c8: 00ff00b7 lui ra,0xff0 + 800001cc: 0ff0809b addiw ra,ra,255 + 800001d0: 0f00ff13 andi t5,ra,240 + 800001d4: 00000013 nop + 800001d8: 000f0313 mv t1,t5 + 800001dc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800001e0: 00200293 li t0,2 + 800001e4: fe5212e3 bne tp,t0,800001c8 <test_8+0x4> + 800001e8: 0f000e93 li t4,240 + 800001ec: 00800193 li gp,8 + 800001f0: 11d31263 bne t1,t4,800002f4 <fail> + +00000000800001f4 <test_9>: + 800001f4: 00000213 li tp,0 + 800001f8: 000f00b7 lui ra,0xf0 + 800001fc: 0ff0809b addiw ra,ra,255 + 80000200: 00c09093 slli ra,ra,0xc + 80000204: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> + 80000208: f0f0ff13 andi t5,ra,-241 + 8000020c: 00000013 nop + 80000210: 00000013 nop + 80000214: 000f0313 mv t1,t5 + 80000218: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000021c: 00200293 li t0,2 + 80000220: fc521ce3 bne tp,t0,800001f8 <test_9+0x4> + 80000224: 000f0eb7 lui t4,0xf0 + 80000228: 0ffe8e9b addiw t4,t4,255 + 8000022c: 00ce9e93 slli t4,t4,0xc + 80000230: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80000234: 00900193 li gp,9 + 80000238: 0bd31e63 bne t1,t4,800002f4 <fail> + +000000008000023c <test_10>: + 8000023c: 00000213 li tp,0 + 80000240: 0ff010b7 lui ra,0xff01 + 80000244: ff00809b addiw ra,ra,-16 + 80000248: 70f0ff13 andi t5,ra,1807 + 8000024c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000250: 00200293 li t0,2 + 80000254: fe5216e3 bne tp,t0,80000240 <test_10+0x4> + 80000258: 70000e93 li t4,1792 + 8000025c: 00a00193 li gp,10 + 80000260: 09df1a63 bne t5,t4,800002f4 <fail> + +0000000080000264 <test_11>: + 80000264: 00000213 li tp,0 + 80000268: 00ff00b7 lui ra,0xff0 + 8000026c: 0ff0809b addiw ra,ra,255 + 80000270: 00000013 nop + 80000274: 0f00ff13 andi t5,ra,240 + 80000278: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000027c: 00200293 li t0,2 + 80000280: fe5214e3 bne tp,t0,80000268 <test_11+0x4> + 80000284: 0f000e93 li t4,240 + 80000288: 00b00193 li gp,11 + 8000028c: 07df1463 bne t5,t4,800002f4 <fail> + +0000000080000290 <test_12>: + 80000290: 00000213 li tp,0 + 80000294: 000f00b7 lui ra,0xf0 + 80000298: 0ff0809b addiw ra,ra,255 + 8000029c: 00c09093 slli ra,ra,0xc + 800002a0: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> + 800002a4: 00000013 nop + 800002a8: 00000013 nop + 800002ac: 70f0ff13 andi t5,ra,1807 + 800002b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002b4: 00200293 li t0,2 + 800002b8: fc521ee3 bne tp,t0,80000294 <test_12+0x4> + 800002bc: 00f00e93 li t4,15 + 800002c0: 00c00193 li gp,12 + 800002c4: 03df1863 bne t5,t4,800002f4 <fail> + +00000000800002c8 <test_13>: + 800002c8: 0f007093 andi ra,zero,240 + 800002cc: 00000e93 li t4,0 + 800002d0: 00d00193 li gp,13 + 800002d4: 03d09063 bne ra,t4,800002f4 <fail> + +00000000800002d8 <test_14>: + 800002d8: 00ff00b7 lui ra,0xff0 + 800002dc: 0ff0809b addiw ra,ra,255 + 800002e0: 70f0f013 andi zero,ra,1807 + 800002e4: 00000e93 li t4,0 + 800002e8: 00e00193 li gp,14 + 800002ec: 01d01463 bne zero,t4,800002f4 <fail> + 800002f0: 00301c63 bne zero,gp,80000308 <pass> + +00000000800002f4 <fail>: + 800002f4: 0ff0000f fence + 800002f8: 00018063 beqz gp,800002f8 <fail+0x4> + 800002fc: 00119193 slli gp,gp,0x1 + 80000300: 0011e193 ori gp,gp,1 + 80000304: 00000073 ecall + +0000000080000308 <pass>: + 80000308: 0ff0000f fence + 8000030c: 00100193 li gp,1 + 80000310: 00000073 ecall + 80000314: c0001073 unimp + 80000318: 0000 unimp + 8000031a: 0000 unimp + 8000031c: 0000 unimp + 8000031e: 0000 unimp + 80000320: 0000 unimp + 80000322: 0000 unimp + 80000324: 0000 unimp + 80000326: 0000 unimp + 80000328: 0000 unimp + 8000032a: 0000 unimp + 8000032c: 0000 unimp + 8000032e: 0000 unimp + 80000330: 0000 unimp + 80000332: 0000 unimp + 80000334: 0000 unimp + 80000336: 0000 unimp + 80000338: 0000 unimp + 8000033a: 0000 unimp + 8000033c: 0000 unimp + 8000033e: 0000 unimp + 80000340: 0000 unimp + 80000342: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-andi.elf b/test/riscv/tests/rv64ui-p-andi.elf Binary files differnew file mode 100755 index 00000000..2886a877 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-andi.elf diff --git a/test/riscv/tests/rv64ui-p-auipc.dump b/test/riscv/tests/rv64ui-p-auipc.dump new file mode 100644 index 00000000..0302a06d --- /dev/null +++ b/test/riscv/tests/rv64ui-p-auipc.dump @@ -0,0 +1,125 @@ + +rv64ui-p-auipc: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000013 nop + 80000100: 00002517 auipc a0,0x2 + 80000104: 71c50513 addi a0,a0,1820 # 8000281c <_end+0x81c> + 80000108: 004005ef jal a1,8000010c <test_2+0x10> + 8000010c: 40b50533 sub a0,a0,a1 + 80000110: 00002eb7 lui t4,0x2 + 80000114: 710e8e9b addiw t4,t4,1808 + 80000118: 00200193 li gp,2 + 8000011c: 03d51463 bne a0,t4,80000144 <fail> + +0000000080000120 <test_3>: + 80000120: ffffe517 auipc a0,0xffffe + 80000124: 8fc50513 addi a0,a0,-1796 # 7fffda1c <_start-0x25e4> + 80000128: 004005ef jal a1,8000012c <test_3+0xc> + 8000012c: 40b50533 sub a0,a0,a1 + 80000130: ffffeeb7 lui t4,0xffffe + 80000134: 8f0e8e9b addiw t4,t4,-1808 + 80000138: 00300193 li gp,3 + 8000013c: 01d51463 bne a0,t4,80000144 <fail> + 80000140: 00301c63 bne zero,gp,80000158 <pass> + +0000000080000144 <fail>: + 80000144: 0ff0000f fence + 80000148: 00018063 beqz gp,80000148 <fail+0x4> + 8000014c: 00119193 slli gp,gp,0x1 + 80000150: 0011e193 ori gp,gp,1 + 80000154: 00000073 ecall + +0000000080000158 <pass>: + 80000158: 0ff0000f fence + 8000015c: 00100193 li gp,1 + 80000160: 00000073 ecall + 80000164: c0001073 unimp + 80000168: 0000 unimp + 8000016a: 0000 unimp + 8000016c: 0000 unimp + 8000016e: 0000 unimp + 80000170: 0000 unimp + 80000172: 0000 unimp + 80000174: 0000 unimp + 80000176: 0000 unimp + 80000178: 0000 unimp + 8000017a: 0000 unimp + 8000017c: 0000 unimp + 8000017e: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-auipc.elf b/test/riscv/tests/rv64ui-p-auipc.elf Binary files differnew file mode 100755 index 00000000..4ef544d1 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-auipc.elf diff --git a/test/riscv/tests/rv64ui-p-beq.dump b/test/riscv/tests/rv64ui-p-beq.dump new file mode 100644 index 00000000..d09e1753 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-beq.dump @@ -0,0 +1,325 @@ + +rv64ui-p-beq: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00200193 li gp,2 + 80000100: 00000093 li ra,0 + 80000104: 00000113 li sp,0 + 80000108: 00208663 beq ra,sp,80000114 <test_2+0x18> + 8000010c: 2a301863 bne zero,gp,800003bc <fail> + 80000110: 00301663 bne zero,gp,8000011c <test_3> + 80000114: fe208ee3 beq ra,sp,80000110 <test_2+0x14> + 80000118: 2a301263 bne zero,gp,800003bc <fail> + +000000008000011c <test_3>: + 8000011c: 00300193 li gp,3 + 80000120: 00100093 li ra,1 + 80000124: 00100113 li sp,1 + 80000128: 00208663 beq ra,sp,80000134 <test_3+0x18> + 8000012c: 28301863 bne zero,gp,800003bc <fail> + 80000130: 00301663 bne zero,gp,8000013c <test_4> + 80000134: fe208ee3 beq ra,sp,80000130 <test_3+0x14> + 80000138: 28301263 bne zero,gp,800003bc <fail> + +000000008000013c <test_4>: + 8000013c: 00400193 li gp,4 + 80000140: fff00093 li ra,-1 + 80000144: fff00113 li sp,-1 + 80000148: 00208663 beq ra,sp,80000154 <test_4+0x18> + 8000014c: 26301863 bne zero,gp,800003bc <fail> + 80000150: 00301663 bne zero,gp,8000015c <test_5> + 80000154: fe208ee3 beq ra,sp,80000150 <test_4+0x14> + 80000158: 26301263 bne zero,gp,800003bc <fail> + +000000008000015c <test_5>: + 8000015c: 00500193 li gp,5 + 80000160: 00000093 li ra,0 + 80000164: 00100113 li sp,1 + 80000168: 00208463 beq ra,sp,80000170 <test_5+0x14> + 8000016c: 00301463 bne zero,gp,80000174 <test_5+0x18> + 80000170: 24301663 bne zero,gp,800003bc <fail> + 80000174: fe208ee3 beq ra,sp,80000170 <test_5+0x14> + +0000000080000178 <test_6>: + 80000178: 00600193 li gp,6 + 8000017c: 00100093 li ra,1 + 80000180: 00000113 li sp,0 + 80000184: 00208463 beq ra,sp,8000018c <test_6+0x14> + 80000188: 00301463 bne zero,gp,80000190 <test_6+0x18> + 8000018c: 22301863 bne zero,gp,800003bc <fail> + 80000190: fe208ee3 beq ra,sp,8000018c <test_6+0x14> + +0000000080000194 <test_7>: + 80000194: 00700193 li gp,7 + 80000198: fff00093 li ra,-1 + 8000019c: 00100113 li sp,1 + 800001a0: 00208463 beq ra,sp,800001a8 <test_7+0x14> + 800001a4: 00301463 bne zero,gp,800001ac <test_7+0x18> + 800001a8: 20301a63 bne zero,gp,800003bc <fail> + 800001ac: fe208ee3 beq ra,sp,800001a8 <test_7+0x14> + +00000000800001b0 <test_8>: + 800001b0: 00800193 li gp,8 + 800001b4: 00100093 li ra,1 + 800001b8: fff00113 li sp,-1 + 800001bc: 00208463 beq ra,sp,800001c4 <test_8+0x14> + 800001c0: 00301463 bne zero,gp,800001c8 <test_8+0x18> + 800001c4: 1e301c63 bne zero,gp,800003bc <fail> + 800001c8: fe208ee3 beq ra,sp,800001c4 <test_8+0x14> + +00000000800001cc <test_9>: + 800001cc: 00900193 li gp,9 + 800001d0: 00000213 li tp,0 + 800001d4: 00000093 li ra,0 + 800001d8: fff00113 li sp,-1 + 800001dc: 1e208063 beq ra,sp,800003bc <fail> + 800001e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800001e4: 00200293 li t0,2 + 800001e8: fe5216e3 bne tp,t0,800001d4 <test_9+0x8> + +00000000800001ec <test_10>: + 800001ec: 00a00193 li gp,10 + 800001f0: 00000213 li tp,0 + 800001f4: 00000093 li ra,0 + 800001f8: fff00113 li sp,-1 + 800001fc: 00000013 nop + 80000200: 1a208e63 beq ra,sp,800003bc <fail> + 80000204: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000208: 00200293 li t0,2 + 8000020c: fe5214e3 bne tp,t0,800001f4 <test_10+0x8> + +0000000080000210 <test_11>: + 80000210: 00b00193 li gp,11 + 80000214: 00000213 li tp,0 + 80000218: 00000093 li ra,0 + 8000021c: fff00113 li sp,-1 + 80000220: 00000013 nop + 80000224: 00000013 nop + 80000228: 18208a63 beq ra,sp,800003bc <fail> + 8000022c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000230: 00200293 li t0,2 + 80000234: fe5212e3 bne tp,t0,80000218 <test_11+0x8> + +0000000080000238 <test_12>: + 80000238: 00c00193 li gp,12 + 8000023c: 00000213 li tp,0 + 80000240: 00000093 li ra,0 + 80000244: 00000013 nop + 80000248: fff00113 li sp,-1 + 8000024c: 16208863 beq ra,sp,800003bc <fail> + 80000250: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000254: 00200293 li t0,2 + 80000258: fe5214e3 bne tp,t0,80000240 <test_12+0x8> + +000000008000025c <test_13>: + 8000025c: 00d00193 li gp,13 + 80000260: 00000213 li tp,0 + 80000264: 00000093 li ra,0 + 80000268: 00000013 nop + 8000026c: fff00113 li sp,-1 + 80000270: 00000013 nop + 80000274: 14208463 beq ra,sp,800003bc <fail> + 80000278: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000027c: 00200293 li t0,2 + 80000280: fe5212e3 bne tp,t0,80000264 <test_13+0x8> + +0000000080000284 <test_14>: + 80000284: 00e00193 li gp,14 + 80000288: 00000213 li tp,0 + 8000028c: 00000093 li ra,0 + 80000290: 00000013 nop + 80000294: 00000013 nop + 80000298: fff00113 li sp,-1 + 8000029c: 12208063 beq ra,sp,800003bc <fail> + 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a4: 00200293 li t0,2 + 800002a8: fe5212e3 bne tp,t0,8000028c <test_14+0x8> + +00000000800002ac <test_15>: + 800002ac: 00f00193 li gp,15 + 800002b0: 00000213 li tp,0 + 800002b4: 00000093 li ra,0 + 800002b8: fff00113 li sp,-1 + 800002bc: 10208063 beq ra,sp,800003bc <fail> + 800002c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002c4: 00200293 li t0,2 + 800002c8: fe5216e3 bne tp,t0,800002b4 <test_15+0x8> + +00000000800002cc <test_16>: + 800002cc: 01000193 li gp,16 + 800002d0: 00000213 li tp,0 + 800002d4: 00000093 li ra,0 + 800002d8: fff00113 li sp,-1 + 800002dc: 00000013 nop + 800002e0: 0c208e63 beq ra,sp,800003bc <fail> + 800002e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002e8: 00200293 li t0,2 + 800002ec: fe5214e3 bne tp,t0,800002d4 <test_16+0x8> + +00000000800002f0 <test_17>: + 800002f0: 01100193 li gp,17 + 800002f4: 00000213 li tp,0 + 800002f8: 00000093 li ra,0 + 800002fc: fff00113 li sp,-1 + 80000300: 00000013 nop + 80000304: 00000013 nop + 80000308: 0a208a63 beq ra,sp,800003bc <fail> + 8000030c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000310: 00200293 li t0,2 + 80000314: fe5212e3 bne tp,t0,800002f8 <test_17+0x8> + +0000000080000318 <test_18>: + 80000318: 01200193 li gp,18 + 8000031c: 00000213 li tp,0 + 80000320: 00000093 li ra,0 + 80000324: 00000013 nop + 80000328: fff00113 li sp,-1 + 8000032c: 08208863 beq ra,sp,800003bc <fail> + 80000330: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000334: 00200293 li t0,2 + 80000338: fe5214e3 bne tp,t0,80000320 <test_18+0x8> + +000000008000033c <test_19>: + 8000033c: 01300193 li gp,19 + 80000340: 00000213 li tp,0 + 80000344: 00000093 li ra,0 + 80000348: 00000013 nop + 8000034c: fff00113 li sp,-1 + 80000350: 00000013 nop + 80000354: 06208463 beq ra,sp,800003bc <fail> + 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000035c: 00200293 li t0,2 + 80000360: fe5212e3 bne tp,t0,80000344 <test_19+0x8> + +0000000080000364 <test_20>: + 80000364: 01400193 li gp,20 + 80000368: 00000213 li tp,0 + 8000036c: 00000093 li ra,0 + 80000370: 00000013 nop + 80000374: 00000013 nop + 80000378: fff00113 li sp,-1 + 8000037c: 04208063 beq ra,sp,800003bc <fail> + 80000380: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000384: 00200293 li t0,2 + 80000388: fe5212e3 bne tp,t0,8000036c <test_20+0x8> + +000000008000038c <test_21>: + 8000038c: 00100093 li ra,1 + 80000390: 00000a63 beqz zero,800003a4 <test_21+0x18> + 80000394: 00108093 addi ra,ra,1 + 80000398: 00108093 addi ra,ra,1 + 8000039c: 00108093 addi ra,ra,1 + 800003a0: 00108093 addi ra,ra,1 + 800003a4: 00108093 addi ra,ra,1 + 800003a8: 00108093 addi ra,ra,1 + 800003ac: 00300e93 li t4,3 + 800003b0: 01500193 li gp,21 + 800003b4: 01d09463 bne ra,t4,800003bc <fail> + 800003b8: 00301c63 bne zero,gp,800003d0 <pass> + +00000000800003bc <fail>: + 800003bc: 0ff0000f fence + 800003c0: 00018063 beqz gp,800003c0 <fail+0x4> + 800003c4: 00119193 slli gp,gp,0x1 + 800003c8: 0011e193 ori gp,gp,1 + 800003cc: 00000073 ecall + +00000000800003d0 <pass>: + 800003d0: 0ff0000f fence + 800003d4: 00100193 li gp,1 + 800003d8: 00000073 ecall + 800003dc: c0001073 unimp + 800003e0: 0000 unimp + 800003e2: 0000 unimp + 800003e4: 0000 unimp + 800003e6: 0000 unimp + 800003e8: 0000 unimp + 800003ea: 0000 unimp + 800003ec: 0000 unimp + 800003ee: 0000 unimp + 800003f0: 0000 unimp + 800003f2: 0000 unimp + 800003f4: 0000 unimp + 800003f6: 0000 unimp + 800003f8: 0000 unimp + 800003fa: 0000 unimp + 800003fc: 0000 unimp + 800003fe: 0000 unimp + 80000400: 0000 unimp + 80000402: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-beq.elf b/test/riscv/tests/rv64ui-p-beq.elf Binary files differnew file mode 100755 index 00000000..38481b96 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-beq.elf diff --git a/test/riscv/tests/rv64ui-p-bge.dump b/test/riscv/tests/rv64ui-p-bge.dump new file mode 100644 index 00000000..bd863ee8 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-bge.dump @@ -0,0 +1,339 @@ + +rv64ui-p-bge: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00200193 li gp,2 + 80000100: 00000093 li ra,0 + 80000104: 00000113 li sp,0 + 80000108: 0020d663 ble sp,ra,80000114 <test_2+0x18> + 8000010c: 30301863 bne zero,gp,8000041c <fail> + 80000110: 00301663 bne zero,gp,8000011c <test_3> + 80000114: fe20dee3 ble sp,ra,80000110 <test_2+0x14> + 80000118: 30301263 bne zero,gp,8000041c <fail> + +000000008000011c <test_3>: + 8000011c: 00300193 li gp,3 + 80000120: 00100093 li ra,1 + 80000124: 00100113 li sp,1 + 80000128: 0020d663 ble sp,ra,80000134 <test_3+0x18> + 8000012c: 2e301863 bne zero,gp,8000041c <fail> + 80000130: 00301663 bne zero,gp,8000013c <test_4> + 80000134: fe20dee3 ble sp,ra,80000130 <test_3+0x14> + 80000138: 2e301263 bne zero,gp,8000041c <fail> + +000000008000013c <test_4>: + 8000013c: 00400193 li gp,4 + 80000140: fff00093 li ra,-1 + 80000144: fff00113 li sp,-1 + 80000148: 0020d663 ble sp,ra,80000154 <test_4+0x18> + 8000014c: 2c301863 bne zero,gp,8000041c <fail> + 80000150: 00301663 bne zero,gp,8000015c <test_5> + 80000154: fe20dee3 ble sp,ra,80000150 <test_4+0x14> + 80000158: 2c301263 bne zero,gp,8000041c <fail> + +000000008000015c <test_5>: + 8000015c: 00500193 li gp,5 + 80000160: 00100093 li ra,1 + 80000164: 00000113 li sp,0 + 80000168: 0020d663 ble sp,ra,80000174 <test_5+0x18> + 8000016c: 2a301863 bne zero,gp,8000041c <fail> + 80000170: 00301663 bne zero,gp,8000017c <test_6> + 80000174: fe20dee3 ble sp,ra,80000170 <test_5+0x14> + 80000178: 2a301263 bne zero,gp,8000041c <fail> + +000000008000017c <test_6>: + 8000017c: 00600193 li gp,6 + 80000180: 00100093 li ra,1 + 80000184: fff00113 li sp,-1 + 80000188: 0020d663 ble sp,ra,80000194 <test_6+0x18> + 8000018c: 28301863 bne zero,gp,8000041c <fail> + 80000190: 00301663 bne zero,gp,8000019c <test_7> + 80000194: fe20dee3 ble sp,ra,80000190 <test_6+0x14> + 80000198: 28301263 bne zero,gp,8000041c <fail> + +000000008000019c <test_7>: + 8000019c: 00700193 li gp,7 + 800001a0: fff00093 li ra,-1 + 800001a4: ffe00113 li sp,-2 + 800001a8: 0020d663 ble sp,ra,800001b4 <test_7+0x18> + 800001ac: 26301863 bne zero,gp,8000041c <fail> + 800001b0: 00301663 bne zero,gp,800001bc <test_8> + 800001b4: fe20dee3 ble sp,ra,800001b0 <test_7+0x14> + 800001b8: 26301263 bne zero,gp,8000041c <fail> + +00000000800001bc <test_8>: + 800001bc: 00800193 li gp,8 + 800001c0: 00000093 li ra,0 + 800001c4: 00100113 li sp,1 + 800001c8: 0020d463 ble sp,ra,800001d0 <test_8+0x14> + 800001cc: 00301463 bne zero,gp,800001d4 <test_8+0x18> + 800001d0: 24301663 bne zero,gp,8000041c <fail> + 800001d4: fe20dee3 ble sp,ra,800001d0 <test_8+0x14> + +00000000800001d8 <test_9>: + 800001d8: 00900193 li gp,9 + 800001dc: fff00093 li ra,-1 + 800001e0: 00100113 li sp,1 + 800001e4: 0020d463 ble sp,ra,800001ec <test_9+0x14> + 800001e8: 00301463 bne zero,gp,800001f0 <test_9+0x18> + 800001ec: 22301863 bne zero,gp,8000041c <fail> + 800001f0: fe20dee3 ble sp,ra,800001ec <test_9+0x14> + +00000000800001f4 <test_10>: + 800001f4: 00a00193 li gp,10 + 800001f8: ffe00093 li ra,-2 + 800001fc: fff00113 li sp,-1 + 80000200: 0020d463 ble sp,ra,80000208 <test_10+0x14> + 80000204: 00301463 bne zero,gp,8000020c <test_10+0x18> + 80000208: 20301a63 bne zero,gp,8000041c <fail> + 8000020c: fe20dee3 ble sp,ra,80000208 <test_10+0x14> + +0000000080000210 <test_11>: + 80000210: 00b00193 li gp,11 + 80000214: ffe00093 li ra,-2 + 80000218: 00100113 li sp,1 + 8000021c: 0020d463 ble sp,ra,80000224 <test_11+0x14> + 80000220: 00301463 bne zero,gp,80000228 <test_11+0x18> + 80000224: 1e301c63 bne zero,gp,8000041c <fail> + 80000228: fe20dee3 ble sp,ra,80000224 <test_11+0x14> + +000000008000022c <test_12>: + 8000022c: 00c00193 li gp,12 + 80000230: 00000213 li tp,0 + 80000234: fff00093 li ra,-1 + 80000238: 00000113 li sp,0 + 8000023c: 1e20d063 ble sp,ra,8000041c <fail> + 80000240: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000244: 00200293 li t0,2 + 80000248: fe5216e3 bne tp,t0,80000234 <test_12+0x8> + +000000008000024c <test_13>: + 8000024c: 00d00193 li gp,13 + 80000250: 00000213 li tp,0 + 80000254: fff00093 li ra,-1 + 80000258: 00000113 li sp,0 + 8000025c: 00000013 nop + 80000260: 1a20de63 ble sp,ra,8000041c <fail> + 80000264: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000268: 00200293 li t0,2 + 8000026c: fe5214e3 bne tp,t0,80000254 <test_13+0x8> + +0000000080000270 <test_14>: + 80000270: 00e00193 li gp,14 + 80000274: 00000213 li tp,0 + 80000278: fff00093 li ra,-1 + 8000027c: 00000113 li sp,0 + 80000280: 00000013 nop + 80000284: 00000013 nop + 80000288: 1820da63 ble sp,ra,8000041c <fail> + 8000028c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000290: 00200293 li t0,2 + 80000294: fe5212e3 bne tp,t0,80000278 <test_14+0x8> + +0000000080000298 <test_15>: + 80000298: 00f00193 li gp,15 + 8000029c: 00000213 li tp,0 + 800002a0: fff00093 li ra,-1 + 800002a4: 00000013 nop + 800002a8: 00000113 li sp,0 + 800002ac: 1620d863 ble sp,ra,8000041c <fail> + 800002b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002b4: 00200293 li t0,2 + 800002b8: fe5214e3 bne tp,t0,800002a0 <test_15+0x8> + +00000000800002bc <test_16>: + 800002bc: 01000193 li gp,16 + 800002c0: 00000213 li tp,0 + 800002c4: fff00093 li ra,-1 + 800002c8: 00000013 nop + 800002cc: 00000113 li sp,0 + 800002d0: 00000013 nop + 800002d4: 1420d463 ble sp,ra,8000041c <fail> + 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002dc: 00200293 li t0,2 + 800002e0: fe5212e3 bne tp,t0,800002c4 <test_16+0x8> + +00000000800002e4 <test_17>: + 800002e4: 01100193 li gp,17 + 800002e8: 00000213 li tp,0 + 800002ec: fff00093 li ra,-1 + 800002f0: 00000013 nop + 800002f4: 00000013 nop + 800002f8: 00000113 li sp,0 + 800002fc: 1220d063 ble sp,ra,8000041c <fail> + 80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000304: 00200293 li t0,2 + 80000308: fe5212e3 bne tp,t0,800002ec <test_17+0x8> + +000000008000030c <test_18>: + 8000030c: 01200193 li gp,18 + 80000310: 00000213 li tp,0 + 80000314: fff00093 li ra,-1 + 80000318: 00000113 li sp,0 + 8000031c: 1020d063 ble sp,ra,8000041c <fail> + 80000320: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000324: 00200293 li t0,2 + 80000328: fe5216e3 bne tp,t0,80000314 <test_18+0x8> + +000000008000032c <test_19>: + 8000032c: 01300193 li gp,19 + 80000330: 00000213 li tp,0 + 80000334: fff00093 li ra,-1 + 80000338: 00000113 li sp,0 + 8000033c: 00000013 nop + 80000340: 0c20de63 ble sp,ra,8000041c <fail> + 80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000348: 00200293 li t0,2 + 8000034c: fe5214e3 bne tp,t0,80000334 <test_19+0x8> + +0000000080000350 <test_20>: + 80000350: 01400193 li gp,20 + 80000354: 00000213 li tp,0 + 80000358: fff00093 li ra,-1 + 8000035c: 00000113 li sp,0 + 80000360: 00000013 nop + 80000364: 00000013 nop + 80000368: 0a20da63 ble sp,ra,8000041c <fail> + 8000036c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000370: 00200293 li t0,2 + 80000374: fe5212e3 bne tp,t0,80000358 <test_20+0x8> + +0000000080000378 <test_21>: + 80000378: 01500193 li gp,21 + 8000037c: 00000213 li tp,0 + 80000380: fff00093 li ra,-1 + 80000384: 00000013 nop + 80000388: 00000113 li sp,0 + 8000038c: 0820d863 ble sp,ra,8000041c <fail> + 80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000394: 00200293 li t0,2 + 80000398: fe5214e3 bne tp,t0,80000380 <test_21+0x8> + +000000008000039c <test_22>: + 8000039c: 01600193 li gp,22 + 800003a0: 00000213 li tp,0 + 800003a4: fff00093 li ra,-1 + 800003a8: 00000013 nop + 800003ac: 00000113 li sp,0 + 800003b0: 00000013 nop + 800003b4: 0620d463 ble sp,ra,8000041c <fail> + 800003b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003bc: 00200293 li t0,2 + 800003c0: fe5212e3 bne tp,t0,800003a4 <test_22+0x8> + +00000000800003c4 <test_23>: + 800003c4: 01700193 li gp,23 + 800003c8: 00000213 li tp,0 + 800003cc: fff00093 li ra,-1 + 800003d0: 00000013 nop + 800003d4: 00000013 nop + 800003d8: 00000113 li sp,0 + 800003dc: 0420d063 ble sp,ra,8000041c <fail> + 800003e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003e4: 00200293 li t0,2 + 800003e8: fe5212e3 bne tp,t0,800003cc <test_23+0x8> + +00000000800003ec <test_24>: + 800003ec: 00100093 li ra,1 + 800003f0: 0000da63 bgez ra,80000404 <test_24+0x18> + 800003f4: 00108093 addi ra,ra,1 + 800003f8: 00108093 addi ra,ra,1 + 800003fc: 00108093 addi ra,ra,1 + 80000400: 00108093 addi ra,ra,1 + 80000404: 00108093 addi ra,ra,1 + 80000408: 00108093 addi ra,ra,1 + 8000040c: 00300e93 li t4,3 + 80000410: 01800193 li gp,24 + 80000414: 01d09463 bne ra,t4,8000041c <fail> + 80000418: 00301c63 bne zero,gp,80000430 <pass> + +000000008000041c <fail>: + 8000041c: 0ff0000f fence + 80000420: 00018063 beqz gp,80000420 <fail+0x4> + 80000424: 00119193 slli gp,gp,0x1 + 80000428: 0011e193 ori gp,gp,1 + 8000042c: 00000073 ecall + +0000000080000430 <pass>: + 80000430: 0ff0000f fence + 80000434: 00100193 li gp,1 + 80000438: 00000073 ecall + 8000043c: c0001073 unimp + 80000440: 0000 unimp + 80000442: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-bge.elf b/test/riscv/tests/rv64ui-p-bge.elf Binary files differnew file mode 100755 index 00000000..31d9ecd4 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-bge.elf diff --git a/test/riscv/tests/rv64ui-p-bgeu.dump b/test/riscv/tests/rv64ui-p-bgeu.dump new file mode 100644 index 00000000..c773c7de --- /dev/null +++ b/test/riscv/tests/rv64ui-p-bgeu.dump @@ -0,0 +1,413 @@ + +rv64ui-p-bgeu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00200193 li gp,2 + 80000100: 00000093 li ra,0 + 80000104: 00000113 li sp,0 + 80000108: 0020f663 bleu sp,ra,80000114 <test_2+0x18> + 8000010c: 3e301463 bne zero,gp,800004f4 <fail> + 80000110: 00301663 bne zero,gp,8000011c <test_3> + 80000114: fe20fee3 bleu sp,ra,80000110 <test_2+0x14> + 80000118: 3c301e63 bne zero,gp,800004f4 <fail> + +000000008000011c <test_3>: + 8000011c: 00300193 li gp,3 + 80000120: 00100093 li ra,1 + 80000124: 00100113 li sp,1 + 80000128: 0020f663 bleu sp,ra,80000134 <test_3+0x18> + 8000012c: 3c301463 bne zero,gp,800004f4 <fail> + 80000130: 00301663 bne zero,gp,8000013c <test_4> + 80000134: fe20fee3 bleu sp,ra,80000130 <test_3+0x14> + 80000138: 3a301e63 bne zero,gp,800004f4 <fail> + +000000008000013c <test_4>: + 8000013c: 00400193 li gp,4 + 80000140: 0010009b addiw ra,zero,1 + 80000144: 02009093 slli ra,ra,0x20 + 80000148: fff08093 addi ra,ra,-1 + 8000014c: 0010011b addiw sp,zero,1 + 80000150: 02011113 slli sp,sp,0x20 + 80000154: fff10113 addi sp,sp,-1 + 80000158: 0020f663 bleu sp,ra,80000164 <test_4+0x28> + 8000015c: 38301c63 bne zero,gp,800004f4 <fail> + 80000160: 00301663 bne zero,gp,8000016c <test_5> + 80000164: fe20fee3 bleu sp,ra,80000160 <test_4+0x24> + 80000168: 38301663 bne zero,gp,800004f4 <fail> + +000000008000016c <test_5>: + 8000016c: 00500193 li gp,5 + 80000170: 00100093 li ra,1 + 80000174: 00000113 li sp,0 + 80000178: 0020f663 bleu sp,ra,80000184 <test_5+0x18> + 8000017c: 36301c63 bne zero,gp,800004f4 <fail> + 80000180: 00301663 bne zero,gp,8000018c <test_6> + 80000184: fe20fee3 bleu sp,ra,80000180 <test_5+0x14> + 80000188: 36301663 bne zero,gp,800004f4 <fail> + +000000008000018c <test_6>: + 8000018c: 00600193 li gp,6 + 80000190: 0010009b addiw ra,zero,1 + 80000194: 02009093 slli ra,ra,0x20 + 80000198: fff08093 addi ra,ra,-1 + 8000019c: 0010011b addiw sp,zero,1 + 800001a0: 02011113 slli sp,sp,0x20 + 800001a4: ffe10113 addi sp,sp,-2 + 800001a8: 0020f663 bleu sp,ra,800001b4 <test_6+0x28> + 800001ac: 34301463 bne zero,gp,800004f4 <fail> + 800001b0: 00301663 bne zero,gp,800001bc <test_7> + 800001b4: fe20fee3 bleu sp,ra,800001b0 <test_6+0x24> + 800001b8: 32301e63 bne zero,gp,800004f4 <fail> + +00000000800001bc <test_7>: + 800001bc: 00700193 li gp,7 + 800001c0: 0010009b addiw ra,zero,1 + 800001c4: 02009093 slli ra,ra,0x20 + 800001c8: fff08093 addi ra,ra,-1 + 800001cc: 00000113 li sp,0 + 800001d0: 0020f663 bleu sp,ra,800001dc <test_7+0x20> + 800001d4: 32301063 bne zero,gp,800004f4 <fail> + 800001d8: 00301663 bne zero,gp,800001e4 <test_8> + 800001dc: fe20fee3 bleu sp,ra,800001d8 <test_7+0x1c> + 800001e0: 30301a63 bne zero,gp,800004f4 <fail> + +00000000800001e4 <test_8>: + 800001e4: 00800193 li gp,8 + 800001e8: 00000093 li ra,0 + 800001ec: 00100113 li sp,1 + 800001f0: 0020f463 bleu sp,ra,800001f8 <test_8+0x14> + 800001f4: 00301463 bne zero,gp,800001fc <test_8+0x18> + 800001f8: 2e301e63 bne zero,gp,800004f4 <fail> + 800001fc: fe20fee3 bleu sp,ra,800001f8 <test_8+0x14> + +0000000080000200 <test_9>: + 80000200: 00900193 li gp,9 + 80000204: 0010009b addiw ra,zero,1 + 80000208: 02009093 slli ra,ra,0x20 + 8000020c: ffe08093 addi ra,ra,-2 + 80000210: 0010011b addiw sp,zero,1 + 80000214: 02011113 slli sp,sp,0x20 + 80000218: fff10113 addi sp,sp,-1 + 8000021c: 0020f463 bleu sp,ra,80000224 <test_9+0x24> + 80000220: 00301463 bne zero,gp,80000228 <test_9+0x28> + 80000224: 2c301863 bne zero,gp,800004f4 <fail> + 80000228: fe20fee3 bleu sp,ra,80000224 <test_9+0x24> + +000000008000022c <test_10>: + 8000022c: 00a00193 li gp,10 + 80000230: 00000093 li ra,0 + 80000234: 0010011b addiw sp,zero,1 + 80000238: 02011113 slli sp,sp,0x20 + 8000023c: fff10113 addi sp,sp,-1 + 80000240: 0020f463 bleu sp,ra,80000248 <test_10+0x1c> + 80000244: 00301463 bne zero,gp,8000024c <test_10+0x20> + 80000248: 2a301663 bne zero,gp,800004f4 <fail> + 8000024c: fe20fee3 bleu sp,ra,80000248 <test_10+0x1c> + +0000000080000250 <test_11>: + 80000250: 00b00193 li gp,11 + 80000254: 800000b7 lui ra,0x80000 + 80000258: fff0809b addiw ra,ra,-1 + 8000025c: 0010011b addiw sp,zero,1 + 80000260: 01f11113 slli sp,sp,0x1f + 80000264: 0020f463 bleu sp,ra,8000026c <test_11+0x1c> + 80000268: 00301463 bne zero,gp,80000270 <test_11+0x20> + 8000026c: 28301463 bne zero,gp,800004f4 <fail> + 80000270: fe20fee3 bleu sp,ra,8000026c <test_11+0x1c> + +0000000080000274 <test_12>: + 80000274: 00c00193 li gp,12 + 80000278: 00000213 li tp,0 + 8000027c: 00f0009b addiw ra,zero,15 + 80000280: 01c09093 slli ra,ra,0x1c + 80000284: fff08093 addi ra,ra,-1 # ffffffff7fffffff <_end+0xfffffffeffffdfff> + 80000288: 00f0011b addiw sp,zero,15 + 8000028c: 01c11113 slli sp,sp,0x1c + 80000290: 2620f263 bleu sp,ra,800004f4 <fail> + 80000294: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000298: 00200293 li t0,2 + 8000029c: fe5210e3 bne tp,t0,8000027c <test_12+0x8> + +00000000800002a0 <test_13>: + 800002a0: 00d00193 li gp,13 + 800002a4: 00000213 li tp,0 + 800002a8: 00f0009b addiw ra,zero,15 + 800002ac: 01c09093 slli ra,ra,0x1c + 800002b0: fff08093 addi ra,ra,-1 + 800002b4: 00f0011b addiw sp,zero,15 + 800002b8: 01c11113 slli sp,sp,0x1c + 800002bc: 00000013 nop + 800002c0: 2220fa63 bleu sp,ra,800004f4 <fail> + 800002c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002c8: 00200293 li t0,2 + 800002cc: fc521ee3 bne tp,t0,800002a8 <test_13+0x8> + +00000000800002d0 <test_14>: + 800002d0: 00e00193 li gp,14 + 800002d4: 00000213 li tp,0 + 800002d8: 00f0009b addiw ra,zero,15 + 800002dc: 01c09093 slli ra,ra,0x1c + 800002e0: fff08093 addi ra,ra,-1 + 800002e4: 00f0011b addiw sp,zero,15 + 800002e8: 01c11113 slli sp,sp,0x1c + 800002ec: 00000013 nop + 800002f0: 00000013 nop + 800002f4: 2020f063 bleu sp,ra,800004f4 <fail> + 800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002fc: 00200293 li t0,2 + 80000300: fc521ce3 bne tp,t0,800002d8 <test_14+0x8> + +0000000080000304 <test_15>: + 80000304: 00f00193 li gp,15 + 80000308: 00000213 li tp,0 + 8000030c: 00f0009b addiw ra,zero,15 + 80000310: 01c09093 slli ra,ra,0x1c + 80000314: fff08093 addi ra,ra,-1 + 80000318: 00000013 nop + 8000031c: 00f0011b addiw sp,zero,15 + 80000320: 01c11113 slli sp,sp,0x1c + 80000324: 1c20f863 bleu sp,ra,800004f4 <fail> + 80000328: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000032c: 00200293 li t0,2 + 80000330: fc521ee3 bne tp,t0,8000030c <test_15+0x8> + +0000000080000334 <test_16>: + 80000334: 01000193 li gp,16 + 80000338: 00000213 li tp,0 + 8000033c: 00f0009b addiw ra,zero,15 + 80000340: 01c09093 slli ra,ra,0x1c + 80000344: fff08093 addi ra,ra,-1 + 80000348: 00000013 nop + 8000034c: 00f0011b addiw sp,zero,15 + 80000350: 01c11113 slli sp,sp,0x1c + 80000354: 00000013 nop + 80000358: 1820fe63 bleu sp,ra,800004f4 <fail> + 8000035c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000360: 00200293 li t0,2 + 80000364: fc521ce3 bne tp,t0,8000033c <test_16+0x8> + +0000000080000368 <test_17>: + 80000368: 01100193 li gp,17 + 8000036c: 00000213 li tp,0 + 80000370: 00f0009b addiw ra,zero,15 + 80000374: 01c09093 slli ra,ra,0x1c + 80000378: fff08093 addi ra,ra,-1 + 8000037c: 00000013 nop + 80000380: 00000013 nop + 80000384: 00f0011b addiw sp,zero,15 + 80000388: 01c11113 slli sp,sp,0x1c + 8000038c: 1620f463 bleu sp,ra,800004f4 <fail> + 80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000394: 00200293 li t0,2 + 80000398: fc521ce3 bne tp,t0,80000370 <test_17+0x8> + +000000008000039c <test_18>: + 8000039c: 01200193 li gp,18 + 800003a0: 00000213 li tp,0 + 800003a4: 00f0009b addiw ra,zero,15 + 800003a8: 01c09093 slli ra,ra,0x1c + 800003ac: fff08093 addi ra,ra,-1 + 800003b0: 00f0011b addiw sp,zero,15 + 800003b4: 01c11113 slli sp,sp,0x1c + 800003b8: 1220fe63 bleu sp,ra,800004f4 <fail> + 800003bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003c0: 00200293 li t0,2 + 800003c4: fe5210e3 bne tp,t0,800003a4 <test_18+0x8> + +00000000800003c8 <test_19>: + 800003c8: 01300193 li gp,19 + 800003cc: 00000213 li tp,0 + 800003d0: 00f0009b addiw ra,zero,15 + 800003d4: 01c09093 slli ra,ra,0x1c + 800003d8: fff08093 addi ra,ra,-1 + 800003dc: 00f0011b addiw sp,zero,15 + 800003e0: 01c11113 slli sp,sp,0x1c + 800003e4: 00000013 nop + 800003e8: 1020f663 bleu sp,ra,800004f4 <fail> + 800003ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003f0: 00200293 li t0,2 + 800003f4: fc521ee3 bne tp,t0,800003d0 <test_19+0x8> + +00000000800003f8 <test_20>: + 800003f8: 01400193 li gp,20 + 800003fc: 00000213 li tp,0 + 80000400: 00f0009b addiw ra,zero,15 + 80000404: 01c09093 slli ra,ra,0x1c + 80000408: fff08093 addi ra,ra,-1 + 8000040c: 00f0011b addiw sp,zero,15 + 80000410: 01c11113 slli sp,sp,0x1c + 80000414: 00000013 nop + 80000418: 00000013 nop + 8000041c: 0c20fc63 bleu sp,ra,800004f4 <fail> + 80000420: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000424: 00200293 li t0,2 + 80000428: fc521ce3 bne tp,t0,80000400 <test_20+0x8> + +000000008000042c <test_21>: + 8000042c: 01500193 li gp,21 + 80000430: 00000213 li tp,0 + 80000434: 00f0009b addiw ra,zero,15 + 80000438: 01c09093 slli ra,ra,0x1c + 8000043c: fff08093 addi ra,ra,-1 + 80000440: 00000013 nop + 80000444: 00f0011b addiw sp,zero,15 + 80000448: 01c11113 slli sp,sp,0x1c + 8000044c: 0a20f463 bleu sp,ra,800004f4 <fail> + 80000450: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000454: 00200293 li t0,2 + 80000458: fc521ee3 bne tp,t0,80000434 <test_21+0x8> + +000000008000045c <test_22>: + 8000045c: 01600193 li gp,22 + 80000460: 00000213 li tp,0 + 80000464: 00f0009b addiw ra,zero,15 + 80000468: 01c09093 slli ra,ra,0x1c + 8000046c: fff08093 addi ra,ra,-1 + 80000470: 00000013 nop + 80000474: 00f0011b addiw sp,zero,15 + 80000478: 01c11113 slli sp,sp,0x1c + 8000047c: 00000013 nop + 80000480: 0620fa63 bleu sp,ra,800004f4 <fail> + 80000484: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000488: 00200293 li t0,2 + 8000048c: fc521ce3 bne tp,t0,80000464 <test_22+0x8> + +0000000080000490 <test_23>: + 80000490: 01700193 li gp,23 + 80000494: 00000213 li tp,0 + 80000498: 00f0009b addiw ra,zero,15 + 8000049c: 01c09093 slli ra,ra,0x1c + 800004a0: fff08093 addi ra,ra,-1 + 800004a4: 00000013 nop + 800004a8: 00000013 nop + 800004ac: 00f0011b addiw sp,zero,15 + 800004b0: 01c11113 slli sp,sp,0x1c + 800004b4: 0420f063 bleu sp,ra,800004f4 <fail> + 800004b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004bc: 00200293 li t0,2 + 800004c0: fc521ce3 bne tp,t0,80000498 <test_23+0x8> + +00000000800004c4 <test_24>: + 800004c4: 00100093 li ra,1 + 800004c8: 0000fa63 bleu zero,ra,800004dc <test_24+0x18> + 800004cc: 00108093 addi ra,ra,1 + 800004d0: 00108093 addi ra,ra,1 + 800004d4: 00108093 addi ra,ra,1 + 800004d8: 00108093 addi ra,ra,1 + 800004dc: 00108093 addi ra,ra,1 + 800004e0: 00108093 addi ra,ra,1 + 800004e4: 00300e93 li t4,3 + 800004e8: 01800193 li gp,24 + 800004ec: 01d09463 bne ra,t4,800004f4 <fail> + 800004f0: 00301c63 bne zero,gp,80000508 <pass> + +00000000800004f4 <fail>: + 800004f4: 0ff0000f fence + 800004f8: 00018063 beqz gp,800004f8 <fail+0x4> + 800004fc: 00119193 slli gp,gp,0x1 + 80000500: 0011e193 ori gp,gp,1 + 80000504: 00000073 ecall + +0000000080000508 <pass>: + 80000508: 0ff0000f fence + 8000050c: 00100193 li gp,1 + 80000510: 00000073 ecall + 80000514: c0001073 unimp + 80000518: 0000 unimp + 8000051a: 0000 unimp + 8000051c: 0000 unimp + 8000051e: 0000 unimp + 80000520: 0000 unimp + 80000522: 0000 unimp + 80000524: 0000 unimp + 80000526: 0000 unimp + 80000528: 0000 unimp + 8000052a: 0000 unimp + 8000052c: 0000 unimp + 8000052e: 0000 unimp + 80000530: 0000 unimp + 80000532: 0000 unimp + 80000534: 0000 unimp + 80000536: 0000 unimp + 80000538: 0000 unimp + 8000053a: 0000 unimp + 8000053c: 0000 unimp + 8000053e: 0000 unimp + 80000540: 0000 unimp + 80000542: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-bgeu.elf b/test/riscv/tests/rv64ui-p-bgeu.elf Binary files differnew file mode 100755 index 00000000..a7e14bac --- /dev/null +++ b/test/riscv/tests/rv64ui-p-bgeu.elf diff --git a/test/riscv/tests/rv64ui-p-blt.dump b/test/riscv/tests/rv64ui-p-blt.dump new file mode 100644 index 00000000..3e6b518b --- /dev/null +++ b/test/riscv/tests/rv64ui-p-blt.dump @@ -0,0 +1,325 @@ + +rv64ui-p-blt: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00200193 li gp,2 + 80000100: 00000093 li ra,0 + 80000104: 00100113 li sp,1 + 80000108: 0020c663 blt ra,sp,80000114 <test_2+0x18> + 8000010c: 2a301863 bne zero,gp,800003bc <fail> + 80000110: 00301663 bne zero,gp,8000011c <test_3> + 80000114: fe20cee3 blt ra,sp,80000110 <test_2+0x14> + 80000118: 2a301263 bne zero,gp,800003bc <fail> + +000000008000011c <test_3>: + 8000011c: 00300193 li gp,3 + 80000120: fff00093 li ra,-1 + 80000124: 00100113 li sp,1 + 80000128: 0020c663 blt ra,sp,80000134 <test_3+0x18> + 8000012c: 28301863 bne zero,gp,800003bc <fail> + 80000130: 00301663 bne zero,gp,8000013c <test_4> + 80000134: fe20cee3 blt ra,sp,80000130 <test_3+0x14> + 80000138: 28301263 bne zero,gp,800003bc <fail> + +000000008000013c <test_4>: + 8000013c: 00400193 li gp,4 + 80000140: ffe00093 li ra,-2 + 80000144: fff00113 li sp,-1 + 80000148: 0020c663 blt ra,sp,80000154 <test_4+0x18> + 8000014c: 26301863 bne zero,gp,800003bc <fail> + 80000150: 00301663 bne zero,gp,8000015c <test_5> + 80000154: fe20cee3 blt ra,sp,80000150 <test_4+0x14> + 80000158: 26301263 bne zero,gp,800003bc <fail> + +000000008000015c <test_5>: + 8000015c: 00500193 li gp,5 + 80000160: 00100093 li ra,1 + 80000164: 00000113 li sp,0 + 80000168: 0020c463 blt ra,sp,80000170 <test_5+0x14> + 8000016c: 00301463 bne zero,gp,80000174 <test_5+0x18> + 80000170: 24301663 bne zero,gp,800003bc <fail> + 80000174: fe20cee3 blt ra,sp,80000170 <test_5+0x14> + +0000000080000178 <test_6>: + 80000178: 00600193 li gp,6 + 8000017c: 00100093 li ra,1 + 80000180: fff00113 li sp,-1 + 80000184: 0020c463 blt ra,sp,8000018c <test_6+0x14> + 80000188: 00301463 bne zero,gp,80000190 <test_6+0x18> + 8000018c: 22301863 bne zero,gp,800003bc <fail> + 80000190: fe20cee3 blt ra,sp,8000018c <test_6+0x14> + +0000000080000194 <test_7>: + 80000194: 00700193 li gp,7 + 80000198: fff00093 li ra,-1 + 8000019c: ffe00113 li sp,-2 + 800001a0: 0020c463 blt ra,sp,800001a8 <test_7+0x14> + 800001a4: 00301463 bne zero,gp,800001ac <test_7+0x18> + 800001a8: 20301a63 bne zero,gp,800003bc <fail> + 800001ac: fe20cee3 blt ra,sp,800001a8 <test_7+0x14> + +00000000800001b0 <test_8>: + 800001b0: 00800193 li gp,8 + 800001b4: 00100093 li ra,1 + 800001b8: ffe00113 li sp,-2 + 800001bc: 0020c463 blt ra,sp,800001c4 <test_8+0x14> + 800001c0: 00301463 bne zero,gp,800001c8 <test_8+0x18> + 800001c4: 1e301c63 bne zero,gp,800003bc <fail> + 800001c8: fe20cee3 blt ra,sp,800001c4 <test_8+0x14> + +00000000800001cc <test_9>: + 800001cc: 00900193 li gp,9 + 800001d0: 00000213 li tp,0 + 800001d4: 00000093 li ra,0 + 800001d8: fff00113 li sp,-1 + 800001dc: 1e20c063 blt ra,sp,800003bc <fail> + 800001e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800001e4: 00200293 li t0,2 + 800001e8: fe5216e3 bne tp,t0,800001d4 <test_9+0x8> + +00000000800001ec <test_10>: + 800001ec: 00a00193 li gp,10 + 800001f0: 00000213 li tp,0 + 800001f4: 00000093 li ra,0 + 800001f8: fff00113 li sp,-1 + 800001fc: 00000013 nop + 80000200: 1a20ce63 blt ra,sp,800003bc <fail> + 80000204: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000208: 00200293 li t0,2 + 8000020c: fe5214e3 bne tp,t0,800001f4 <test_10+0x8> + +0000000080000210 <test_11>: + 80000210: 00b00193 li gp,11 + 80000214: 00000213 li tp,0 + 80000218: 00000093 li ra,0 + 8000021c: fff00113 li sp,-1 + 80000220: 00000013 nop + 80000224: 00000013 nop + 80000228: 1820ca63 blt ra,sp,800003bc <fail> + 8000022c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000230: 00200293 li t0,2 + 80000234: fe5212e3 bne tp,t0,80000218 <test_11+0x8> + +0000000080000238 <test_12>: + 80000238: 00c00193 li gp,12 + 8000023c: 00000213 li tp,0 + 80000240: 00000093 li ra,0 + 80000244: 00000013 nop + 80000248: fff00113 li sp,-1 + 8000024c: 1620c863 blt ra,sp,800003bc <fail> + 80000250: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000254: 00200293 li t0,2 + 80000258: fe5214e3 bne tp,t0,80000240 <test_12+0x8> + +000000008000025c <test_13>: + 8000025c: 00d00193 li gp,13 + 80000260: 00000213 li tp,0 + 80000264: 00000093 li ra,0 + 80000268: 00000013 nop + 8000026c: fff00113 li sp,-1 + 80000270: 00000013 nop + 80000274: 1420c463 blt ra,sp,800003bc <fail> + 80000278: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000027c: 00200293 li t0,2 + 80000280: fe5212e3 bne tp,t0,80000264 <test_13+0x8> + +0000000080000284 <test_14>: + 80000284: 00e00193 li gp,14 + 80000288: 00000213 li tp,0 + 8000028c: 00000093 li ra,0 + 80000290: 00000013 nop + 80000294: 00000013 nop + 80000298: fff00113 li sp,-1 + 8000029c: 1220c063 blt ra,sp,800003bc <fail> + 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a4: 00200293 li t0,2 + 800002a8: fe5212e3 bne tp,t0,8000028c <test_14+0x8> + +00000000800002ac <test_15>: + 800002ac: 00f00193 li gp,15 + 800002b0: 00000213 li tp,0 + 800002b4: 00000093 li ra,0 + 800002b8: fff00113 li sp,-1 + 800002bc: 1020c063 blt ra,sp,800003bc <fail> + 800002c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002c4: 00200293 li t0,2 + 800002c8: fe5216e3 bne tp,t0,800002b4 <test_15+0x8> + +00000000800002cc <test_16>: + 800002cc: 01000193 li gp,16 + 800002d0: 00000213 li tp,0 + 800002d4: 00000093 li ra,0 + 800002d8: fff00113 li sp,-1 + 800002dc: 00000013 nop + 800002e0: 0c20ce63 blt ra,sp,800003bc <fail> + 800002e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002e8: 00200293 li t0,2 + 800002ec: fe5214e3 bne tp,t0,800002d4 <test_16+0x8> + +00000000800002f0 <test_17>: + 800002f0: 01100193 li gp,17 + 800002f4: 00000213 li tp,0 + 800002f8: 00000093 li ra,0 + 800002fc: fff00113 li sp,-1 + 80000300: 00000013 nop + 80000304: 00000013 nop + 80000308: 0a20ca63 blt ra,sp,800003bc <fail> + 8000030c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000310: 00200293 li t0,2 + 80000314: fe5212e3 bne tp,t0,800002f8 <test_17+0x8> + +0000000080000318 <test_18>: + 80000318: 01200193 li gp,18 + 8000031c: 00000213 li tp,0 + 80000320: 00000093 li ra,0 + 80000324: 00000013 nop + 80000328: fff00113 li sp,-1 + 8000032c: 0820c863 blt ra,sp,800003bc <fail> + 80000330: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000334: 00200293 li t0,2 + 80000338: fe5214e3 bne tp,t0,80000320 <test_18+0x8> + +000000008000033c <test_19>: + 8000033c: 01300193 li gp,19 + 80000340: 00000213 li tp,0 + 80000344: 00000093 li ra,0 + 80000348: 00000013 nop + 8000034c: fff00113 li sp,-1 + 80000350: 00000013 nop + 80000354: 0620c463 blt ra,sp,800003bc <fail> + 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000035c: 00200293 li t0,2 + 80000360: fe5212e3 bne tp,t0,80000344 <test_19+0x8> + +0000000080000364 <test_20>: + 80000364: 01400193 li gp,20 + 80000368: 00000213 li tp,0 + 8000036c: 00000093 li ra,0 + 80000370: 00000013 nop + 80000374: 00000013 nop + 80000378: fff00113 li sp,-1 + 8000037c: 0420c063 blt ra,sp,800003bc <fail> + 80000380: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000384: 00200293 li t0,2 + 80000388: fe5212e3 bne tp,t0,8000036c <test_20+0x8> + +000000008000038c <test_21>: + 8000038c: 00100093 li ra,1 + 80000390: 00104a63 bgtz ra,800003a4 <test_21+0x18> + 80000394: 00108093 addi ra,ra,1 + 80000398: 00108093 addi ra,ra,1 + 8000039c: 00108093 addi ra,ra,1 + 800003a0: 00108093 addi ra,ra,1 + 800003a4: 00108093 addi ra,ra,1 + 800003a8: 00108093 addi ra,ra,1 + 800003ac: 00300e93 li t4,3 + 800003b0: 01500193 li gp,21 + 800003b4: 01d09463 bne ra,t4,800003bc <fail> + 800003b8: 00301c63 bne zero,gp,800003d0 <pass> + +00000000800003bc <fail>: + 800003bc: 0ff0000f fence + 800003c0: 00018063 beqz gp,800003c0 <fail+0x4> + 800003c4: 00119193 slli gp,gp,0x1 + 800003c8: 0011e193 ori gp,gp,1 + 800003cc: 00000073 ecall + +00000000800003d0 <pass>: + 800003d0: 0ff0000f fence + 800003d4: 00100193 li gp,1 + 800003d8: 00000073 ecall + 800003dc: c0001073 unimp + 800003e0: 0000 unimp + 800003e2: 0000 unimp + 800003e4: 0000 unimp + 800003e6: 0000 unimp + 800003e8: 0000 unimp + 800003ea: 0000 unimp + 800003ec: 0000 unimp + 800003ee: 0000 unimp + 800003f0: 0000 unimp + 800003f2: 0000 unimp + 800003f4: 0000 unimp + 800003f6: 0000 unimp + 800003f8: 0000 unimp + 800003fa: 0000 unimp + 800003fc: 0000 unimp + 800003fe: 0000 unimp + 80000400: 0000 unimp + 80000402: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-blt.elf b/test/riscv/tests/rv64ui-p-blt.elf Binary files differnew file mode 100755 index 00000000..eec6ce60 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-blt.elf diff --git a/test/riscv/tests/rv64ui-p-bltu.dump b/test/riscv/tests/rv64ui-p-bltu.dump new file mode 100644 index 00000000..ec344211 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-bltu.dump @@ -0,0 +1,371 @@ + +rv64ui-p-bltu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00200193 li gp,2 + 80000100: 00000093 li ra,0 + 80000104: 00100113 li sp,1 + 80000108: 0020e663 bltu ra,sp,80000114 <test_2+0x18> + 8000010c: 36301c63 bne zero,gp,80000484 <fail> + 80000110: 00301663 bne zero,gp,8000011c <test_3> + 80000114: fe20eee3 bltu ra,sp,80000110 <test_2+0x14> + 80000118: 36301663 bne zero,gp,80000484 <fail> + +000000008000011c <test_3>: + 8000011c: 00300193 li gp,3 + 80000120: 0010009b addiw ra,zero,1 + 80000124: 02009093 slli ra,ra,0x20 + 80000128: ffe08093 addi ra,ra,-2 + 8000012c: 0010011b addiw sp,zero,1 + 80000130: 02011113 slli sp,sp,0x20 + 80000134: fff10113 addi sp,sp,-1 + 80000138: 0020e663 bltu ra,sp,80000144 <test_3+0x28> + 8000013c: 34301463 bne zero,gp,80000484 <fail> + 80000140: 00301663 bne zero,gp,8000014c <test_4> + 80000144: fe20eee3 bltu ra,sp,80000140 <test_3+0x24> + 80000148: 32301e63 bne zero,gp,80000484 <fail> + +000000008000014c <test_4>: + 8000014c: 00400193 li gp,4 + 80000150: 00000093 li ra,0 + 80000154: 0010011b addiw sp,zero,1 + 80000158: 02011113 slli sp,sp,0x20 + 8000015c: fff10113 addi sp,sp,-1 + 80000160: 0020e663 bltu ra,sp,8000016c <test_4+0x20> + 80000164: 32301063 bne zero,gp,80000484 <fail> + 80000168: 00301663 bne zero,gp,80000174 <test_5> + 8000016c: fe20eee3 bltu ra,sp,80000168 <test_4+0x1c> + 80000170: 30301a63 bne zero,gp,80000484 <fail> + +0000000080000174 <test_5>: + 80000174: 00500193 li gp,5 + 80000178: 00100093 li ra,1 + 8000017c: 00000113 li sp,0 + 80000180: 0020e463 bltu ra,sp,80000188 <test_5+0x14> + 80000184: 00301463 bne zero,gp,8000018c <test_5+0x18> + 80000188: 2e301e63 bne zero,gp,80000484 <fail> + 8000018c: fe20eee3 bltu ra,sp,80000188 <test_5+0x14> + +0000000080000190 <test_6>: + 80000190: 00600193 li gp,6 + 80000194: 0010009b addiw ra,zero,1 + 80000198: 02009093 slli ra,ra,0x20 + 8000019c: fff08093 addi ra,ra,-1 + 800001a0: 0010011b addiw sp,zero,1 + 800001a4: 02011113 slli sp,sp,0x20 + 800001a8: ffe10113 addi sp,sp,-2 + 800001ac: 0020e463 bltu ra,sp,800001b4 <test_6+0x24> + 800001b0: 00301463 bne zero,gp,800001b8 <test_6+0x28> + 800001b4: 2c301863 bne zero,gp,80000484 <fail> + 800001b8: fe20eee3 bltu ra,sp,800001b4 <test_6+0x24> + +00000000800001bc <test_7>: + 800001bc: 00700193 li gp,7 + 800001c0: 0010009b addiw ra,zero,1 + 800001c4: 02009093 slli ra,ra,0x20 + 800001c8: fff08093 addi ra,ra,-1 + 800001cc: 00000113 li sp,0 + 800001d0: 0020e463 bltu ra,sp,800001d8 <test_7+0x1c> + 800001d4: 00301463 bne zero,gp,800001dc <test_7+0x20> + 800001d8: 2a301663 bne zero,gp,80000484 <fail> + 800001dc: fe20eee3 bltu ra,sp,800001d8 <test_7+0x1c> + +00000000800001e0 <test_8>: + 800001e0: 00800193 li gp,8 + 800001e4: 0010009b addiw ra,zero,1 + 800001e8: 01f09093 slli ra,ra,0x1f + 800001ec: 80000137 lui sp,0x80000 + 800001f0: fff1011b addiw sp,sp,-1 + 800001f4: 0020e463 bltu ra,sp,800001fc <test_8+0x1c> + 800001f8: 00301463 bne zero,gp,80000200 <test_8+0x20> + 800001fc: 28301463 bne zero,gp,80000484 <fail> + 80000200: fe20eee3 bltu ra,sp,800001fc <test_8+0x1c> + +0000000080000204 <test_9>: + 80000204: 00900193 li gp,9 + 80000208: 00000213 li tp,0 + 8000020c: 00f0009b addiw ra,zero,15 + 80000210: 01c09093 slli ra,ra,0x1c + 80000214: 00f0011b addiw sp,zero,15 + 80000218: 01c11113 slli sp,sp,0x1c + 8000021c: fff10113 addi sp,sp,-1 # ffffffff7fffffff <_end+0xfffffffeffffdfff> + 80000220: 2620e263 bltu ra,sp,80000484 <fail> + 80000224: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000228: 00200293 li t0,2 + 8000022c: fe5210e3 bne tp,t0,8000020c <test_9+0x8> + +0000000080000230 <test_10>: + 80000230: 00a00193 li gp,10 + 80000234: 00000213 li tp,0 + 80000238: 00f0009b addiw ra,zero,15 + 8000023c: 01c09093 slli ra,ra,0x1c + 80000240: 00f0011b addiw sp,zero,15 + 80000244: 01c11113 slli sp,sp,0x1c + 80000248: fff10113 addi sp,sp,-1 + 8000024c: 00000013 nop + 80000250: 2220ea63 bltu ra,sp,80000484 <fail> + 80000254: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000258: 00200293 li t0,2 + 8000025c: fc521ee3 bne tp,t0,80000238 <test_10+0x8> + +0000000080000260 <test_11>: + 80000260: 00b00193 li gp,11 + 80000264: 00000213 li tp,0 + 80000268: 00f0009b addiw ra,zero,15 + 8000026c: 01c09093 slli ra,ra,0x1c + 80000270: 00f0011b addiw sp,zero,15 + 80000274: 01c11113 slli sp,sp,0x1c + 80000278: fff10113 addi sp,sp,-1 + 8000027c: 00000013 nop + 80000280: 00000013 nop + 80000284: 2020e063 bltu ra,sp,80000484 <fail> + 80000288: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000028c: 00200293 li t0,2 + 80000290: fc521ce3 bne tp,t0,80000268 <test_11+0x8> + +0000000080000294 <test_12>: + 80000294: 00c00193 li gp,12 + 80000298: 00000213 li tp,0 + 8000029c: 00f0009b addiw ra,zero,15 + 800002a0: 01c09093 slli ra,ra,0x1c + 800002a4: 00000013 nop + 800002a8: 00f0011b addiw sp,zero,15 + 800002ac: 01c11113 slli sp,sp,0x1c + 800002b0: fff10113 addi sp,sp,-1 + 800002b4: 1c20e863 bltu ra,sp,80000484 <fail> + 800002b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002bc: 00200293 li t0,2 + 800002c0: fc521ee3 bne tp,t0,8000029c <test_12+0x8> + +00000000800002c4 <test_13>: + 800002c4: 00d00193 li gp,13 + 800002c8: 00000213 li tp,0 + 800002cc: 00f0009b addiw ra,zero,15 + 800002d0: 01c09093 slli ra,ra,0x1c + 800002d4: 00000013 nop + 800002d8: 00f0011b addiw sp,zero,15 + 800002dc: 01c11113 slli sp,sp,0x1c + 800002e0: fff10113 addi sp,sp,-1 + 800002e4: 00000013 nop + 800002e8: 1820ee63 bltu ra,sp,80000484 <fail> + 800002ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002f0: 00200293 li t0,2 + 800002f4: fc521ce3 bne tp,t0,800002cc <test_13+0x8> + +00000000800002f8 <test_14>: + 800002f8: 00e00193 li gp,14 + 800002fc: 00000213 li tp,0 + 80000300: 00f0009b addiw ra,zero,15 + 80000304: 01c09093 slli ra,ra,0x1c + 80000308: 00000013 nop + 8000030c: 00000013 nop + 80000310: 00f0011b addiw sp,zero,15 + 80000314: 01c11113 slli sp,sp,0x1c + 80000318: fff10113 addi sp,sp,-1 + 8000031c: 1620e463 bltu ra,sp,80000484 <fail> + 80000320: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000324: 00200293 li t0,2 + 80000328: fc521ce3 bne tp,t0,80000300 <test_14+0x8> + +000000008000032c <test_15>: + 8000032c: 00f00193 li gp,15 + 80000330: 00000213 li tp,0 + 80000334: 00f0009b addiw ra,zero,15 + 80000338: 01c09093 slli ra,ra,0x1c + 8000033c: 00f0011b addiw sp,zero,15 + 80000340: 01c11113 slli sp,sp,0x1c + 80000344: fff10113 addi sp,sp,-1 + 80000348: 1220ee63 bltu ra,sp,80000484 <fail> + 8000034c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000350: 00200293 li t0,2 + 80000354: fe5210e3 bne tp,t0,80000334 <test_15+0x8> + +0000000080000358 <test_16>: + 80000358: 01000193 li gp,16 + 8000035c: 00000213 li tp,0 + 80000360: 00f0009b addiw ra,zero,15 + 80000364: 01c09093 slli ra,ra,0x1c + 80000368: 00f0011b addiw sp,zero,15 + 8000036c: 01c11113 slli sp,sp,0x1c + 80000370: fff10113 addi sp,sp,-1 + 80000374: 00000013 nop + 80000378: 1020e663 bltu ra,sp,80000484 <fail> + 8000037c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000380: 00200293 li t0,2 + 80000384: fc521ee3 bne tp,t0,80000360 <test_16+0x8> + +0000000080000388 <test_17>: + 80000388: 01100193 li gp,17 + 8000038c: 00000213 li tp,0 + 80000390: 00f0009b addiw ra,zero,15 + 80000394: 01c09093 slli ra,ra,0x1c + 80000398: 00f0011b addiw sp,zero,15 + 8000039c: 01c11113 slli sp,sp,0x1c + 800003a0: fff10113 addi sp,sp,-1 + 800003a4: 00000013 nop + 800003a8: 00000013 nop + 800003ac: 0c20ec63 bltu ra,sp,80000484 <fail> + 800003b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003b4: 00200293 li t0,2 + 800003b8: fc521ce3 bne tp,t0,80000390 <test_17+0x8> + +00000000800003bc <test_18>: + 800003bc: 01200193 li gp,18 + 800003c0: 00000213 li tp,0 + 800003c4: 00f0009b addiw ra,zero,15 + 800003c8: 01c09093 slli ra,ra,0x1c + 800003cc: 00000013 nop + 800003d0: 00f0011b addiw sp,zero,15 + 800003d4: 01c11113 slli sp,sp,0x1c + 800003d8: fff10113 addi sp,sp,-1 + 800003dc: 0a20e463 bltu ra,sp,80000484 <fail> + 800003e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003e4: 00200293 li t0,2 + 800003e8: fc521ee3 bne tp,t0,800003c4 <test_18+0x8> + +00000000800003ec <test_19>: + 800003ec: 01300193 li gp,19 + 800003f0: 00000213 li tp,0 + 800003f4: 00f0009b addiw ra,zero,15 + 800003f8: 01c09093 slli ra,ra,0x1c + 800003fc: 00000013 nop + 80000400: 00f0011b addiw sp,zero,15 + 80000404: 01c11113 slli sp,sp,0x1c + 80000408: fff10113 addi sp,sp,-1 + 8000040c: 00000013 nop + 80000410: 0620ea63 bltu ra,sp,80000484 <fail> + 80000414: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000418: 00200293 li t0,2 + 8000041c: fc521ce3 bne tp,t0,800003f4 <test_19+0x8> + +0000000080000420 <test_20>: + 80000420: 01400193 li gp,20 + 80000424: 00000213 li tp,0 + 80000428: 00f0009b addiw ra,zero,15 + 8000042c: 01c09093 slli ra,ra,0x1c + 80000430: 00000013 nop + 80000434: 00000013 nop + 80000438: 00f0011b addiw sp,zero,15 + 8000043c: 01c11113 slli sp,sp,0x1c + 80000440: fff10113 addi sp,sp,-1 + 80000444: 0420e063 bltu ra,sp,80000484 <fail> + 80000448: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000044c: 00200293 li t0,2 + 80000450: fc521ce3 bne tp,t0,80000428 <test_20+0x8> + +0000000080000454 <test_21>: + 80000454: 00100093 li ra,1 + 80000458: 00106a63 bltu zero,ra,8000046c <test_21+0x18> + 8000045c: 00108093 addi ra,ra,1 + 80000460: 00108093 addi ra,ra,1 + 80000464: 00108093 addi ra,ra,1 + 80000468: 00108093 addi ra,ra,1 + 8000046c: 00108093 addi ra,ra,1 + 80000470: 00108093 addi ra,ra,1 + 80000474: 00300e93 li t4,3 + 80000478: 01500193 li gp,21 + 8000047c: 01d09463 bne ra,t4,80000484 <fail> + 80000480: 00301c63 bne zero,gp,80000498 <pass> + +0000000080000484 <fail>: + 80000484: 0ff0000f fence + 80000488: 00018063 beqz gp,80000488 <fail+0x4> + 8000048c: 00119193 slli gp,gp,0x1 + 80000490: 0011e193 ori gp,gp,1 + 80000494: 00000073 ecall + +0000000080000498 <pass>: + 80000498: 0ff0000f fence + 8000049c: 00100193 li gp,1 + 800004a0: 00000073 ecall + 800004a4: c0001073 unimp + 800004a8: 0000 unimp + 800004aa: 0000 unimp + 800004ac: 0000 unimp + 800004ae: 0000 unimp + 800004b0: 0000 unimp + 800004b2: 0000 unimp + 800004b4: 0000 unimp + 800004b6: 0000 unimp + 800004b8: 0000 unimp + 800004ba: 0000 unimp + 800004bc: 0000 unimp + 800004be: 0000 unimp + 800004c0: 0000 unimp + 800004c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-bltu.elf b/test/riscv/tests/rv64ui-p-bltu.elf Binary files differnew file mode 100755 index 00000000..05ee4bec --- /dev/null +++ b/test/riscv/tests/rv64ui-p-bltu.elf diff --git a/test/riscv/tests/rv64ui-p-bne.dump b/test/riscv/tests/rv64ui-p-bne.dump new file mode 100644 index 00000000..42f4613f --- /dev/null +++ b/test/riscv/tests/rv64ui-p-bne.dump @@ -0,0 +1,324 @@ + +rv64ui-p-bne: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00200193 li gp,2 + 80000100: 00000093 li ra,0 + 80000104: 00100113 li sp,1 + 80000108: 00209663 bne ra,sp,80000114 <test_2+0x18> + 8000010c: 2a301a63 bne zero,gp,800003c0 <fail> + 80000110: 00301663 bne zero,gp,8000011c <test_3> + 80000114: fe209ee3 bne ra,sp,80000110 <test_2+0x14> + 80000118: 2a301463 bne zero,gp,800003c0 <fail> + +000000008000011c <test_3>: + 8000011c: 00300193 li gp,3 + 80000120: 00100093 li ra,1 + 80000124: 00000113 li sp,0 + 80000128: 00209663 bne ra,sp,80000134 <test_3+0x18> + 8000012c: 28301a63 bne zero,gp,800003c0 <fail> + 80000130: 00301663 bne zero,gp,8000013c <test_4> + 80000134: fe209ee3 bne ra,sp,80000130 <test_3+0x14> + 80000138: 28301463 bne zero,gp,800003c0 <fail> + +000000008000013c <test_4>: + 8000013c: 00400193 li gp,4 + 80000140: fff00093 li ra,-1 + 80000144: 00100113 li sp,1 + 80000148: 00209663 bne ra,sp,80000154 <test_4+0x18> + 8000014c: 26301a63 bne zero,gp,800003c0 <fail> + 80000150: 00301663 bne zero,gp,8000015c <test_5> + 80000154: fe209ee3 bne ra,sp,80000150 <test_4+0x14> + 80000158: 26301463 bne zero,gp,800003c0 <fail> + +000000008000015c <test_5>: + 8000015c: 00500193 li gp,5 + 80000160: 00100093 li ra,1 + 80000164: fff00113 li sp,-1 + 80000168: 00209663 bne ra,sp,80000174 <test_5+0x18> + 8000016c: 24301a63 bne zero,gp,800003c0 <fail> + 80000170: 00301663 bne zero,gp,8000017c <test_6> + 80000174: fe209ee3 bne ra,sp,80000170 <test_5+0x14> + 80000178: 24301463 bne zero,gp,800003c0 <fail> + +000000008000017c <test_6>: + 8000017c: 00600193 li gp,6 + 80000180: 00000093 li ra,0 + 80000184: 00000113 li sp,0 + 80000188: 00209463 bne ra,sp,80000190 <test_6+0x14> + 8000018c: 00301463 bne zero,gp,80000194 <test_6+0x18> + 80000190: 22301863 bne zero,gp,800003c0 <fail> + 80000194: fe209ee3 bne ra,sp,80000190 <test_6+0x14> + +0000000080000198 <test_7>: + 80000198: 00700193 li gp,7 + 8000019c: 00100093 li ra,1 + 800001a0: 00100113 li sp,1 + 800001a4: 00209463 bne ra,sp,800001ac <test_7+0x14> + 800001a8: 00301463 bne zero,gp,800001b0 <test_7+0x18> + 800001ac: 20301a63 bne zero,gp,800003c0 <fail> + 800001b0: fe209ee3 bne ra,sp,800001ac <test_7+0x14> + +00000000800001b4 <test_8>: + 800001b4: 00800193 li gp,8 + 800001b8: fff00093 li ra,-1 + 800001bc: fff00113 li sp,-1 + 800001c0: 00209463 bne ra,sp,800001c8 <test_8+0x14> + 800001c4: 00301463 bne zero,gp,800001cc <test_8+0x18> + 800001c8: 1e301c63 bne zero,gp,800003c0 <fail> + 800001cc: fe209ee3 bne ra,sp,800001c8 <test_8+0x14> + +00000000800001d0 <test_9>: + 800001d0: 00900193 li gp,9 + 800001d4: 00000213 li tp,0 + 800001d8: 00000093 li ra,0 + 800001dc: 00000113 li sp,0 + 800001e0: 1e209063 bne ra,sp,800003c0 <fail> + 800001e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800001e8: 00200293 li t0,2 + 800001ec: fe5216e3 bne tp,t0,800001d8 <test_9+0x8> + +00000000800001f0 <test_10>: + 800001f0: 00a00193 li gp,10 + 800001f4: 00000213 li tp,0 + 800001f8: 00000093 li ra,0 + 800001fc: 00000113 li sp,0 + 80000200: 00000013 nop + 80000204: 1a209e63 bne ra,sp,800003c0 <fail> + 80000208: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000020c: 00200293 li t0,2 + 80000210: fe5214e3 bne tp,t0,800001f8 <test_10+0x8> + +0000000080000214 <test_11>: + 80000214: 00b00193 li gp,11 + 80000218: 00000213 li tp,0 + 8000021c: 00000093 li ra,0 + 80000220: 00000113 li sp,0 + 80000224: 00000013 nop + 80000228: 00000013 nop + 8000022c: 18209a63 bne ra,sp,800003c0 <fail> + 80000230: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000234: 00200293 li t0,2 + 80000238: fe5212e3 bne tp,t0,8000021c <test_11+0x8> + +000000008000023c <test_12>: + 8000023c: 00c00193 li gp,12 + 80000240: 00000213 li tp,0 + 80000244: 00000093 li ra,0 + 80000248: 00000013 nop + 8000024c: 00000113 li sp,0 + 80000250: 16209863 bne ra,sp,800003c0 <fail> + 80000254: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000258: 00200293 li t0,2 + 8000025c: fe5214e3 bne tp,t0,80000244 <test_12+0x8> + +0000000080000260 <test_13>: + 80000260: 00d00193 li gp,13 + 80000264: 00000213 li tp,0 + 80000268: 00000093 li ra,0 + 8000026c: 00000013 nop + 80000270: 00000113 li sp,0 + 80000274: 00000013 nop + 80000278: 14209463 bne ra,sp,800003c0 <fail> + 8000027c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000280: 00200293 li t0,2 + 80000284: fe5212e3 bne tp,t0,80000268 <test_13+0x8> + +0000000080000288 <test_14>: + 80000288: 00e00193 li gp,14 + 8000028c: 00000213 li tp,0 + 80000290: 00000093 li ra,0 + 80000294: 00000013 nop + 80000298: 00000013 nop + 8000029c: 00000113 li sp,0 + 800002a0: 12209063 bne ra,sp,800003c0 <fail> + 800002a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a8: 00200293 li t0,2 + 800002ac: fe5212e3 bne tp,t0,80000290 <test_14+0x8> + +00000000800002b0 <test_15>: + 800002b0: 00f00193 li gp,15 + 800002b4: 00000213 li tp,0 + 800002b8: 00000093 li ra,0 + 800002bc: 00000113 li sp,0 + 800002c0: 10209063 bne ra,sp,800003c0 <fail> + 800002c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002c8: 00200293 li t0,2 + 800002cc: fe5216e3 bne tp,t0,800002b8 <test_15+0x8> + +00000000800002d0 <test_16>: + 800002d0: 01000193 li gp,16 + 800002d4: 00000213 li tp,0 + 800002d8: 00000093 li ra,0 + 800002dc: 00000113 li sp,0 + 800002e0: 00000013 nop + 800002e4: 0c209e63 bne ra,sp,800003c0 <fail> + 800002e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002ec: 00200293 li t0,2 + 800002f0: fe5214e3 bne tp,t0,800002d8 <test_16+0x8> + +00000000800002f4 <test_17>: + 800002f4: 01100193 li gp,17 + 800002f8: 00000213 li tp,0 + 800002fc: 00000093 li ra,0 + 80000300: 00000113 li sp,0 + 80000304: 00000013 nop + 80000308: 00000013 nop + 8000030c: 0a209a63 bne ra,sp,800003c0 <fail> + 80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000314: 00200293 li t0,2 + 80000318: fe5212e3 bne tp,t0,800002fc <test_17+0x8> + +000000008000031c <test_18>: + 8000031c: 01200193 li gp,18 + 80000320: 00000213 li tp,0 + 80000324: 00000093 li ra,0 + 80000328: 00000013 nop + 8000032c: 00000113 li sp,0 + 80000330: 08209863 bne ra,sp,800003c0 <fail> + 80000334: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000338: 00200293 li t0,2 + 8000033c: fe5214e3 bne tp,t0,80000324 <test_18+0x8> + +0000000080000340 <test_19>: + 80000340: 01300193 li gp,19 + 80000344: 00000213 li tp,0 + 80000348: 00000093 li ra,0 + 8000034c: 00000013 nop + 80000350: 00000113 li sp,0 + 80000354: 00000013 nop + 80000358: 06209463 bne ra,sp,800003c0 <fail> + 8000035c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000360: 00200293 li t0,2 + 80000364: fe5212e3 bne tp,t0,80000348 <test_19+0x8> + +0000000080000368 <test_20>: + 80000368: 01400193 li gp,20 + 8000036c: 00000213 li tp,0 + 80000370: 00000093 li ra,0 + 80000374: 00000013 nop + 80000378: 00000013 nop + 8000037c: 00000113 li sp,0 + 80000380: 04209063 bne ra,sp,800003c0 <fail> + 80000384: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000388: 00200293 li t0,2 + 8000038c: fe5212e3 bne tp,t0,80000370 <test_20+0x8> + +0000000080000390 <test_21>: + 80000390: 00100093 li ra,1 + 80000394: 00009a63 bnez ra,800003a8 <test_21+0x18> + 80000398: 00108093 addi ra,ra,1 + 8000039c: 00108093 addi ra,ra,1 + 800003a0: 00108093 addi ra,ra,1 + 800003a4: 00108093 addi ra,ra,1 + 800003a8: 00108093 addi ra,ra,1 + 800003ac: 00108093 addi ra,ra,1 + 800003b0: 00300e93 li t4,3 + 800003b4: 01500193 li gp,21 + 800003b8: 01d09463 bne ra,t4,800003c0 <fail> + 800003bc: 00301c63 bne zero,gp,800003d4 <pass> + +00000000800003c0 <fail>: + 800003c0: 0ff0000f fence + 800003c4: 00018063 beqz gp,800003c4 <fail+0x4> + 800003c8: 00119193 slli gp,gp,0x1 + 800003cc: 0011e193 ori gp,gp,1 + 800003d0: 00000073 ecall + +00000000800003d4 <pass>: + 800003d4: 0ff0000f fence + 800003d8: 00100193 li gp,1 + 800003dc: 00000073 ecall + 800003e0: c0001073 unimp + 800003e4: 0000 unimp + 800003e6: 0000 unimp + 800003e8: 0000 unimp + 800003ea: 0000 unimp + 800003ec: 0000 unimp + 800003ee: 0000 unimp + 800003f0: 0000 unimp + 800003f2: 0000 unimp + 800003f4: 0000 unimp + 800003f6: 0000 unimp + 800003f8: 0000 unimp + 800003fa: 0000 unimp + 800003fc: 0000 unimp + 800003fe: 0000 unimp + 80000400: 0000 unimp + 80000402: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-bne.elf b/test/riscv/tests/rv64ui-p-bne.elf Binary files differnew file mode 100755 index 00000000..f44e9132 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-bne.elf diff --git a/test/riscv/tests/rv64ui-p-fence_i.dump b/test/riscv/tests/rv64ui-p-fence_i.dump new file mode 100644 index 00000000..8bbfcfdb --- /dev/null +++ b/test/riscv/tests/rv64ui-p-fence_i.dump @@ -0,0 +1,189 @@ + +rv64ui-p-fence_i: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <reset_vector+0xb0> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + 800000fc: 06f00693 li a3,111 + 80000100: 00002517 auipc a0,0x2 + 80000104: f0051503 lh a0,-256(a0) # 80002000 <begin_signature> + 80000108: 00002597 auipc a1,0x2 + 8000010c: efa59583 lh a1,-262(a1) # 80002002 <begin_signature+0x2> + 80000110: 00000013 nop + 80000114: 00000013 nop + 80000118: 00000013 nop + 8000011c: 00000013 nop + 80000120: 00000013 nop + 80000124: 00000013 nop + 80000128: 00000013 nop + 8000012c: 00000013 nop + 80000130: 00000013 nop + 80000134: 00000013 nop + 80000138: 00000013 nop + 8000013c: 00000013 nop + 80000140: 00000297 auipc t0,0x0 + 80000144: 00a29a23 sh a0,20(t0) # 80000154 <reset_vector+0x108> + 80000148: 00000297 auipc t0,0x0 + 8000014c: 00b29723 sh a1,14(t0) # 80000156 <reset_vector+0x10a> + 80000150: 0000100f fence.i + 80000154: 0de68693 addi a3,a3,222 + +0000000080000158 <test_2>: + 80000158: 00000013 nop + 8000015c: 1bc00e93 li t4,444 + 80000160: 00200193 li gp,2 + 80000164: 07d69a63 bne a3,t4,800001d8 <fail> + 80000168: 06400713 li a4,100 + 8000016c: fff70713 addi a4,a4,-1 + 80000170: fe071ee3 bnez a4,8000016c <test_2+0x14> + 80000174: 00000297 auipc t0,0x0 + 80000178: 04a29623 sh a0,76(t0) # 800001c0 <test_2+0x68> + 8000017c: 00000297 auipc t0,0x0 + 80000180: 04b29323 sh a1,70(t0) # 800001c2 <test_2+0x6a> + 80000184: 0000100f fence.i + 80000188: 00000013 nop + 8000018c: 00000013 nop + 80000190: 00000013 nop + 80000194: 00000013 nop + 80000198: 00000013 nop + 8000019c: 00000013 nop + 800001a0: 00000013 nop + 800001a4: 00000013 nop + 800001a8: 00000013 nop + 800001ac: 00000013 nop + 800001b0: 00000013 nop + 800001b4: 00000013 nop + 800001b8: 00000013 nop + 800001bc: 00000013 nop + 800001c0: 22b68693 addi a3,a3,555 + +00000000800001c4 <test_3>: + 800001c4: 00000013 nop + 800001c8: 30900e93 li t4,777 + 800001cc: 00300193 li gp,3 + 800001d0: 01d69463 bne a3,t4,800001d8 <fail> + 800001d4: 00301c63 bne zero,gp,800001ec <pass> + +00000000800001d8 <fail>: + 800001d8: 0ff0000f fence + 800001dc: 00018063 beqz gp,800001dc <fail+0x4> + 800001e0: 00119193 slli gp,gp,0x1 + 800001e4: 0011e193 ori gp,gp,1 + 800001e8: 00000073 ecall + +00000000800001ec <pass>: + 800001ec: 0ff0000f fence + 800001f0: 00100193 li gp,1 + 800001f4: 00000073 ecall + 800001f8: c0001073 unimp + 800001fc: 0000 unimp + 800001fe: 0000 unimp + 80000200: 0000 unimp + 80000202: 0000 unimp + 80000204: 0000 unimp + 80000206: 0000 unimp + 80000208: 0000 unimp + 8000020a: 0000 unimp + 8000020c: 0000 unimp + 8000020e: 0000 unimp + 80000210: 0000 unimp + 80000212: 0000 unimp + 80000214: 0000 unimp + 80000216: 0000 unimp + 80000218: 0000 unimp + 8000021a: 0000 unimp + 8000021c: 0000 unimp + 8000021e: 0000 unimp + 80000220: 0000 unimp + 80000222: 0000 unimp + 80000224: 0000 unimp + 80000226: 0000 unimp + 80000228: 0000 unimp + 8000022a: 0000 unimp + 8000022c: 0000 unimp + 8000022e: 0000 unimp + 80000230: 0000 unimp + 80000232: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: 14d68693 addi a3,a3,333 + 80002004: 0000 unimp + 80002006: 0000 unimp + 80002008: 0000 unimp + 8000200a: 0000 unimp + 8000200c: 0000 unimp + 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-fence_i.elf b/test/riscv/tests/rv64ui-p-fence_i.elf Binary files differnew file mode 100755 index 00000000..da16800e --- /dev/null +++ b/test/riscv/tests/rv64ui-p-fence_i.elf diff --git a/test/riscv/tests/rv64ui-p-jal.dump b/test/riscv/tests/rv64ui-p-jal.dump new file mode 100644 index 00000000..2a86bb86 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-jal.dump @@ -0,0 +1,128 @@ + +rv64ui-p-jal: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00200193 li gp,2 + 80000100: 00000093 li ra,0 + 80000104: 0100026f jal tp,80000114 <target_2> + +0000000080000108 <linkaddr_2>: + 80000108: 00000013 nop + 8000010c: 00000013 nop + 80000110: 0400006f j 80000150 <fail> + +0000000080000114 <target_2>: + 80000114: 00000117 auipc sp,0x0 + 80000118: ff410113 addi sp,sp,-12 # 80000108 <linkaddr_2> + 8000011c: 02411a63 bne sp,tp,80000150 <fail> + +0000000080000120 <test_3>: + 80000120: 00100093 li ra,1 + 80000124: 0140006f j 80000138 <test_3+0x18> + 80000128: 00108093 addi ra,ra,1 + 8000012c: 00108093 addi ra,ra,1 + 80000130: 00108093 addi ra,ra,1 + 80000134: 00108093 addi ra,ra,1 + 80000138: 00108093 addi ra,ra,1 + 8000013c: 00108093 addi ra,ra,1 + 80000140: 00300e93 li t4,3 + 80000144: 00300193 li gp,3 + 80000148: 01d09463 bne ra,t4,80000150 <fail> + 8000014c: 00301c63 bne zero,gp,80000164 <pass> + +0000000080000150 <fail>: + 80000150: 0ff0000f fence + 80000154: 00018063 beqz gp,80000154 <fail+0x4> + 80000158: 00119193 slli gp,gp,0x1 + 8000015c: 0011e193 ori gp,gp,1 + 80000160: 00000073 ecall + +0000000080000164 <pass>: + 80000164: 0ff0000f fence + 80000168: 00100193 li gp,1 + 8000016c: 00000073 ecall + 80000170: c0001073 unimp + 80000174: 0000 unimp + 80000176: 0000 unimp + 80000178: 0000 unimp + 8000017a: 0000 unimp + 8000017c: 0000 unimp + 8000017e: 0000 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-jal.elf b/test/riscv/tests/rv64ui-p-jal.elf Binary files differnew file mode 100755 index 00000000..a6a2933f --- /dev/null +++ b/test/riscv/tests/rv64ui-p-jal.elf diff --git a/test/riscv/tests/rv64ui-p-jalr.dump b/test/riscv/tests/rv64ui-p-jalr.dump new file mode 100644 index 00000000..029a6922 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-jalr.dump @@ -0,0 +1,166 @@ + +rv64ui-p-jalr: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00200193 li gp,2 + 80000100: 00000293 li t0,0 + 80000104: 00000317 auipc t1,0x0 + 80000108: 01030313 addi t1,t1,16 # 80000114 <target_2> + 8000010c: 000302e7 jalr t0,t1 + +0000000080000110 <linkaddr_2>: + 80000110: 0c00006f j 800001d0 <fail> + +0000000080000114 <target_2>: + 80000114: 00000317 auipc t1,0x0 + 80000118: ffc30313 addi t1,t1,-4 # 80000110 <linkaddr_2> + 8000011c: 0a629a63 bne t0,t1,800001d0 <fail> + +0000000080000120 <test_4>: + 80000120: 00400193 li gp,4 + 80000124: 00000213 li tp,0 + 80000128: 00000317 auipc t1,0x0 + 8000012c: 01030313 addi t1,t1,16 # 80000138 <test_4+0x18> + 80000130: 000309e7 jalr s3,t1 + 80000134: 08301e63 bne zero,gp,800001d0 <fail> + 80000138: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000013c: 00200293 li t0,2 + 80000140: fe5214e3 bne tp,t0,80000128 <test_4+0x8> + +0000000080000144 <test_5>: + 80000144: 00500193 li gp,5 + 80000148: 00000213 li tp,0 + 8000014c: 00000317 auipc t1,0x0 + 80000150: 01430313 addi t1,t1,20 # 80000160 <test_5+0x1c> + 80000154: 00000013 nop + 80000158: 000309e7 jalr s3,t1 + 8000015c: 06301a63 bne zero,gp,800001d0 <fail> + 80000160: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000164: 00200293 li t0,2 + 80000168: fe5212e3 bne tp,t0,8000014c <test_5+0x8> + +000000008000016c <test_6>: + 8000016c: 00600193 li gp,6 + 80000170: 00000213 li tp,0 + 80000174: 00000317 auipc t1,0x0 + 80000178: 01830313 addi t1,t1,24 # 8000018c <test_6+0x20> + 8000017c: 00000013 nop + 80000180: 00000013 nop + 80000184: 000309e7 jalr s3,t1 + 80000188: 04301463 bne zero,gp,800001d0 <fail> + 8000018c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000190: 00200293 li t0,2 + 80000194: fe5210e3 bne tp,t0,80000174 <test_6+0x8> + +0000000080000198 <test_7>: + 80000198: 00100293 li t0,1 + 8000019c: 00000317 auipc t1,0x0 + 800001a0: 01c30313 addi t1,t1,28 # 800001b8 <test_7+0x20> + 800001a4: ffc30067 jr -4(t1) + 800001a8: 00128293 addi t0,t0,1 + 800001ac: 00128293 addi t0,t0,1 + 800001b0: 00128293 addi t0,t0,1 + 800001b4: 00128293 addi t0,t0,1 + 800001b8: 00128293 addi t0,t0,1 + 800001bc: 00128293 addi t0,t0,1 + 800001c0: 00400e93 li t4,4 + 800001c4: 00700193 li gp,7 + 800001c8: 01d29463 bne t0,t4,800001d0 <fail> + 800001cc: 00301c63 bne zero,gp,800001e4 <pass> + +00000000800001d0 <fail>: + 800001d0: 0ff0000f fence + 800001d4: 00018063 beqz gp,800001d4 <fail+0x4> + 800001d8: 00119193 slli gp,gp,0x1 + 800001dc: 0011e193 ori gp,gp,1 + 800001e0: 00000073 ecall + +00000000800001e4 <pass>: + 800001e4: 0ff0000f fence + 800001e8: 00100193 li gp,1 + 800001ec: 00000073 ecall + 800001f0: c0001073 unimp + 800001f4: 0000 unimp + 800001f6: 0000 unimp + 800001f8: 0000 unimp + 800001fa: 0000 unimp + 800001fc: 0000 unimp + 800001fe: 0000 unimp + 80000200: 0000 unimp + 80000202: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-jalr.elf b/test/riscv/tests/rv64ui-p-jalr.elf Binary files differnew file mode 100755 index 00000000..709778a9 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-jalr.elf diff --git a/test/riscv/tests/rv64ui-p-lb.dump b/test/riscv/tests/rv64ui-p-lb.dump new file mode 100644 index 00000000..dbf78e7d --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lb.dump @@ -0,0 +1,306 @@ + +rv64ui-p-lb: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00002097 auipc ra,0x2 + 80000100: f0408093 addi ra,ra,-252 # 80002000 <begin_signature> + 80000104: 00008f03 lb t5,0(ra) + 80000108: fff00e93 li t4,-1 + 8000010c: 00200193 li gp,2 + 80000110: 23df1c63 bne t5,t4,80000348 <fail> + +0000000080000114 <test_3>: + 80000114: 00002097 auipc ra,0x2 + 80000118: eec08093 addi ra,ra,-276 # 80002000 <begin_signature> + 8000011c: 00108f03 lb t5,1(ra) + 80000120: 00000e93 li t4,0 + 80000124: 00300193 li gp,3 + 80000128: 23df1063 bne t5,t4,80000348 <fail> + +000000008000012c <test_4>: + 8000012c: 00002097 auipc ra,0x2 + 80000130: ed408093 addi ra,ra,-300 # 80002000 <begin_signature> + 80000134: 00208f03 lb t5,2(ra) + 80000138: ff000e93 li t4,-16 + 8000013c: 00400193 li gp,4 + 80000140: 21df1463 bne t5,t4,80000348 <fail> + +0000000080000144 <test_5>: + 80000144: 00002097 auipc ra,0x2 + 80000148: ebc08093 addi ra,ra,-324 # 80002000 <begin_signature> + 8000014c: 00308f03 lb t5,3(ra) + 80000150: 00f00e93 li t4,15 + 80000154: 00500193 li gp,5 + 80000158: 1fdf1863 bne t5,t4,80000348 <fail> + +000000008000015c <test_6>: + 8000015c: 00002097 auipc ra,0x2 + 80000160: ea708093 addi ra,ra,-345 # 80002003 <tdat4> + 80000164: ffd08f03 lb t5,-3(ra) + 80000168: fff00e93 li t4,-1 + 8000016c: 00600193 li gp,6 + 80000170: 1ddf1c63 bne t5,t4,80000348 <fail> + +0000000080000174 <test_7>: + 80000174: 00002097 auipc ra,0x2 + 80000178: e8f08093 addi ra,ra,-369 # 80002003 <tdat4> + 8000017c: ffe08f03 lb t5,-2(ra) + 80000180: 00000e93 li t4,0 + 80000184: 00700193 li gp,7 + 80000188: 1ddf1063 bne t5,t4,80000348 <fail> + +000000008000018c <test_8>: + 8000018c: 00002097 auipc ra,0x2 + 80000190: e7708093 addi ra,ra,-393 # 80002003 <tdat4> + 80000194: fff08f03 lb t5,-1(ra) + 80000198: ff000e93 li t4,-16 + 8000019c: 00800193 li gp,8 + 800001a0: 1bdf1463 bne t5,t4,80000348 <fail> + +00000000800001a4 <test_9>: + 800001a4: 00002097 auipc ra,0x2 + 800001a8: e5f08093 addi ra,ra,-417 # 80002003 <tdat4> + 800001ac: 00008f03 lb t5,0(ra) + 800001b0: 00f00e93 li t4,15 + 800001b4: 00900193 li gp,9 + 800001b8: 19df1863 bne t5,t4,80000348 <fail> + +00000000800001bc <test_10>: + 800001bc: 00002097 auipc ra,0x2 + 800001c0: e4408093 addi ra,ra,-444 # 80002000 <begin_signature> + 800001c4: fe008093 addi ra,ra,-32 + 800001c8: 02008283 lb t0,32(ra) + 800001cc: fff00e93 li t4,-1 + 800001d0: 00a00193 li gp,10 + 800001d4: 17d29a63 bne t0,t4,80000348 <fail> + +00000000800001d8 <test_11>: + 800001d8: 00002097 auipc ra,0x2 + 800001dc: e2808093 addi ra,ra,-472 # 80002000 <begin_signature> + 800001e0: ffa08093 addi ra,ra,-6 + 800001e4: 00708283 lb t0,7(ra) + 800001e8: 00000e93 li t4,0 + 800001ec: 00b00193 li gp,11 + 800001f0: 15d29c63 bne t0,t4,80000348 <fail> + +00000000800001f4 <test_12>: + 800001f4: 00c00193 li gp,12 + 800001f8: 00000213 li tp,0 + 800001fc: 00002097 auipc ra,0x2 + 80000200: e0508093 addi ra,ra,-507 # 80002001 <tdat2> + 80000204: 00108f03 lb t5,1(ra) + 80000208: 000f0313 mv t1,t5 + 8000020c: ff000e93 li t4,-16 + 80000210: 13d31c63 bne t1,t4,80000348 <fail> + 80000214: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000218: 00200293 li t0,2 + 8000021c: fe5210e3 bne tp,t0,800001fc <test_12+0x8> + +0000000080000220 <test_13>: + 80000220: 00d00193 li gp,13 + 80000224: 00000213 li tp,0 + 80000228: 00002097 auipc ra,0x2 + 8000022c: dda08093 addi ra,ra,-550 # 80002002 <tdat3> + 80000230: 00108f03 lb t5,1(ra) + 80000234: 00000013 nop + 80000238: 000f0313 mv t1,t5 + 8000023c: 00f00e93 li t4,15 + 80000240: 11d31463 bne t1,t4,80000348 <fail> + 80000244: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000248: 00200293 li t0,2 + 8000024c: fc521ee3 bne tp,t0,80000228 <test_13+0x8> + +0000000080000250 <test_14>: + 80000250: 00e00193 li gp,14 + 80000254: 00000213 li tp,0 + 80000258: 00002097 auipc ra,0x2 + 8000025c: da808093 addi ra,ra,-600 # 80002000 <begin_signature> + 80000260: 00108f03 lb t5,1(ra) + 80000264: 00000013 nop + 80000268: 00000013 nop + 8000026c: 000f0313 mv t1,t5 + 80000270: 00000e93 li t4,0 + 80000274: 0dd31a63 bne t1,t4,80000348 <fail> + 80000278: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000027c: 00200293 li t0,2 + 80000280: fc521ce3 bne tp,t0,80000258 <test_14+0x8> + +0000000080000284 <test_15>: + 80000284: 00f00193 li gp,15 + 80000288: 00000213 li tp,0 + 8000028c: 00002097 auipc ra,0x2 + 80000290: d7508093 addi ra,ra,-651 # 80002001 <tdat2> + 80000294: 00108f03 lb t5,1(ra) + 80000298: ff000e93 li t4,-16 + 8000029c: 0bdf1663 bne t5,t4,80000348 <fail> + 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a4: 00200293 li t0,2 + 800002a8: fe5212e3 bne tp,t0,8000028c <test_15+0x8> + +00000000800002ac <test_16>: + 800002ac: 01000193 li gp,16 + 800002b0: 00000213 li tp,0 + 800002b4: 00002097 auipc ra,0x2 + 800002b8: d4e08093 addi ra,ra,-690 # 80002002 <tdat3> + 800002bc: 00000013 nop + 800002c0: 00108f03 lb t5,1(ra) + 800002c4: 00f00e93 li t4,15 + 800002c8: 09df1063 bne t5,t4,80000348 <fail> + 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002d0: 00200293 li t0,2 + 800002d4: fe5210e3 bne tp,t0,800002b4 <test_16+0x8> + +00000000800002d8 <test_17>: + 800002d8: 01100193 li gp,17 + 800002dc: 00000213 li tp,0 + 800002e0: 00002097 auipc ra,0x2 + 800002e4: d2008093 addi ra,ra,-736 # 80002000 <begin_signature> + 800002e8: 00000013 nop + 800002ec: 00000013 nop + 800002f0: 00108f03 lb t5,1(ra) + 800002f4: 00000e93 li t4,0 + 800002f8: 05df1863 bne t5,t4,80000348 <fail> + 800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000300: 00200293 li t0,2 + 80000304: fc521ee3 bne tp,t0,800002e0 <test_17+0x8> + +0000000080000308 <test_18>: + 80000308: 00002297 auipc t0,0x2 + 8000030c: cf828293 addi t0,t0,-776 # 80002000 <begin_signature> + 80000310: 00028103 lb sp,0(t0) + 80000314: 00200113 li sp,2 + 80000318: 00200e93 li t4,2 + 8000031c: 01200193 li gp,18 + 80000320: 03d11463 bne sp,t4,80000348 <fail> + +0000000080000324 <test_19>: + 80000324: 00002297 auipc t0,0x2 + 80000328: cdc28293 addi t0,t0,-804 # 80002000 <begin_signature> + 8000032c: 00028103 lb sp,0(t0) + 80000330: 00000013 nop + 80000334: 00200113 li sp,2 + 80000338: 00200e93 li t4,2 + 8000033c: 01300193 li gp,19 + 80000340: 01d11463 bne sp,t4,80000348 <fail> + 80000344: 00301c63 bne zero,gp,8000035c <pass> + +0000000080000348 <fail>: + 80000348: 0ff0000f fence + 8000034c: 00018063 beqz gp,8000034c <fail+0x4> + 80000350: 00119193 slli gp,gp,0x1 + 80000354: 0011e193 ori gp,gp,1 + 80000358: 00000073 ecall + +000000008000035c <pass>: + 8000035c: 0ff0000f fence + 80000360: 00100193 li gp,1 + 80000364: 00000073 ecall + 80000368: c0001073 unimp + 8000036c: 0000 unimp + 8000036e: 0000 unimp + 80000370: 0000 unimp + 80000372: 0000 unimp + 80000374: 0000 unimp + 80000376: 0000 unimp + 80000378: 0000 unimp + 8000037a: 0000 unimp + 8000037c: 0000 unimp + 8000037e: 0000 unimp + 80000380: 0000 unimp + 80000382: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: 0xff + +0000000080002001 <tdat2>: + 80002001: sd s0,32(s0) + +0000000080002002 <tdat3>: + 80002002: addi a2,sp,988 + +0000000080002003 <tdat4>: + 80002003: 0000000f fence unknown,unknown + 80002007: 0000 unimp + 80002009: 0000 unimp + 8000200b: 0000 unimp + 8000200d: 0000 unimp + 8000200f: 00 Address 0x000000008000200f is out of bounds. + diff --git a/test/riscv/tests/rv64ui-p-lb.elf b/test/riscv/tests/rv64ui-p-lb.elf Binary files differnew file mode 100755 index 00000000..c1723c06 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lb.elf diff --git a/test/riscv/tests/rv64ui-p-lbu.dump b/test/riscv/tests/rv64ui-p-lbu.dump new file mode 100644 index 00000000..4365b07b --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lbu.dump @@ -0,0 +1,306 @@ + +rv64ui-p-lbu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00002097 auipc ra,0x2 + 80000100: f0408093 addi ra,ra,-252 # 80002000 <begin_signature> + 80000104: 0000cf03 lbu t5,0(ra) + 80000108: 0ff00e93 li t4,255 + 8000010c: 00200193 li gp,2 + 80000110: 23df1c63 bne t5,t4,80000348 <fail> + +0000000080000114 <test_3>: + 80000114: 00002097 auipc ra,0x2 + 80000118: eec08093 addi ra,ra,-276 # 80002000 <begin_signature> + 8000011c: 0010cf03 lbu t5,1(ra) + 80000120: 00000e93 li t4,0 + 80000124: 00300193 li gp,3 + 80000128: 23df1063 bne t5,t4,80000348 <fail> + +000000008000012c <test_4>: + 8000012c: 00002097 auipc ra,0x2 + 80000130: ed408093 addi ra,ra,-300 # 80002000 <begin_signature> + 80000134: 0020cf03 lbu t5,2(ra) + 80000138: 0f000e93 li t4,240 + 8000013c: 00400193 li gp,4 + 80000140: 21df1463 bne t5,t4,80000348 <fail> + +0000000080000144 <test_5>: + 80000144: 00002097 auipc ra,0x2 + 80000148: ebc08093 addi ra,ra,-324 # 80002000 <begin_signature> + 8000014c: 0030cf03 lbu t5,3(ra) + 80000150: 00f00e93 li t4,15 + 80000154: 00500193 li gp,5 + 80000158: 1fdf1863 bne t5,t4,80000348 <fail> + +000000008000015c <test_6>: + 8000015c: 00002097 auipc ra,0x2 + 80000160: ea708093 addi ra,ra,-345 # 80002003 <tdat4> + 80000164: ffd0cf03 lbu t5,-3(ra) + 80000168: 0ff00e93 li t4,255 + 8000016c: 00600193 li gp,6 + 80000170: 1ddf1c63 bne t5,t4,80000348 <fail> + +0000000080000174 <test_7>: + 80000174: 00002097 auipc ra,0x2 + 80000178: e8f08093 addi ra,ra,-369 # 80002003 <tdat4> + 8000017c: ffe0cf03 lbu t5,-2(ra) + 80000180: 00000e93 li t4,0 + 80000184: 00700193 li gp,7 + 80000188: 1ddf1063 bne t5,t4,80000348 <fail> + +000000008000018c <test_8>: + 8000018c: 00002097 auipc ra,0x2 + 80000190: e7708093 addi ra,ra,-393 # 80002003 <tdat4> + 80000194: fff0cf03 lbu t5,-1(ra) + 80000198: 0f000e93 li t4,240 + 8000019c: 00800193 li gp,8 + 800001a0: 1bdf1463 bne t5,t4,80000348 <fail> + +00000000800001a4 <test_9>: + 800001a4: 00002097 auipc ra,0x2 + 800001a8: e5f08093 addi ra,ra,-417 # 80002003 <tdat4> + 800001ac: 0000cf03 lbu t5,0(ra) + 800001b0: 00f00e93 li t4,15 + 800001b4: 00900193 li gp,9 + 800001b8: 19df1863 bne t5,t4,80000348 <fail> + +00000000800001bc <test_10>: + 800001bc: 00002097 auipc ra,0x2 + 800001c0: e4408093 addi ra,ra,-444 # 80002000 <begin_signature> + 800001c4: fe008093 addi ra,ra,-32 + 800001c8: 0200c283 lbu t0,32(ra) + 800001cc: 0ff00e93 li t4,255 + 800001d0: 00a00193 li gp,10 + 800001d4: 17d29a63 bne t0,t4,80000348 <fail> + +00000000800001d8 <test_11>: + 800001d8: 00002097 auipc ra,0x2 + 800001dc: e2808093 addi ra,ra,-472 # 80002000 <begin_signature> + 800001e0: ffa08093 addi ra,ra,-6 + 800001e4: 0070c283 lbu t0,7(ra) + 800001e8: 00000e93 li t4,0 + 800001ec: 00b00193 li gp,11 + 800001f0: 15d29c63 bne t0,t4,80000348 <fail> + +00000000800001f4 <test_12>: + 800001f4: 00c00193 li gp,12 + 800001f8: 00000213 li tp,0 + 800001fc: 00002097 auipc ra,0x2 + 80000200: e0508093 addi ra,ra,-507 # 80002001 <tdat2> + 80000204: 0010cf03 lbu t5,1(ra) + 80000208: 000f0313 mv t1,t5 + 8000020c: 0f000e93 li t4,240 + 80000210: 13d31c63 bne t1,t4,80000348 <fail> + 80000214: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000218: 00200293 li t0,2 + 8000021c: fe5210e3 bne tp,t0,800001fc <test_12+0x8> + +0000000080000220 <test_13>: + 80000220: 00d00193 li gp,13 + 80000224: 00000213 li tp,0 + 80000228: 00002097 auipc ra,0x2 + 8000022c: dda08093 addi ra,ra,-550 # 80002002 <tdat3> + 80000230: 0010cf03 lbu t5,1(ra) + 80000234: 00000013 nop + 80000238: 000f0313 mv t1,t5 + 8000023c: 00f00e93 li t4,15 + 80000240: 11d31463 bne t1,t4,80000348 <fail> + 80000244: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000248: 00200293 li t0,2 + 8000024c: fc521ee3 bne tp,t0,80000228 <test_13+0x8> + +0000000080000250 <test_14>: + 80000250: 00e00193 li gp,14 + 80000254: 00000213 li tp,0 + 80000258: 00002097 auipc ra,0x2 + 8000025c: da808093 addi ra,ra,-600 # 80002000 <begin_signature> + 80000260: 0010cf03 lbu t5,1(ra) + 80000264: 00000013 nop + 80000268: 00000013 nop + 8000026c: 000f0313 mv t1,t5 + 80000270: 00000e93 li t4,0 + 80000274: 0dd31a63 bne t1,t4,80000348 <fail> + 80000278: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000027c: 00200293 li t0,2 + 80000280: fc521ce3 bne tp,t0,80000258 <test_14+0x8> + +0000000080000284 <test_15>: + 80000284: 00f00193 li gp,15 + 80000288: 00000213 li tp,0 + 8000028c: 00002097 auipc ra,0x2 + 80000290: d7508093 addi ra,ra,-651 # 80002001 <tdat2> + 80000294: 0010cf03 lbu t5,1(ra) + 80000298: 0f000e93 li t4,240 + 8000029c: 0bdf1663 bne t5,t4,80000348 <fail> + 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a4: 00200293 li t0,2 + 800002a8: fe5212e3 bne tp,t0,8000028c <test_15+0x8> + +00000000800002ac <test_16>: + 800002ac: 01000193 li gp,16 + 800002b0: 00000213 li tp,0 + 800002b4: 00002097 auipc ra,0x2 + 800002b8: d4e08093 addi ra,ra,-690 # 80002002 <tdat3> + 800002bc: 00000013 nop + 800002c0: 0010cf03 lbu t5,1(ra) + 800002c4: 00f00e93 li t4,15 + 800002c8: 09df1063 bne t5,t4,80000348 <fail> + 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002d0: 00200293 li t0,2 + 800002d4: fe5210e3 bne tp,t0,800002b4 <test_16+0x8> + +00000000800002d8 <test_17>: + 800002d8: 01100193 li gp,17 + 800002dc: 00000213 li tp,0 + 800002e0: 00002097 auipc ra,0x2 + 800002e4: d2008093 addi ra,ra,-736 # 80002000 <begin_signature> + 800002e8: 00000013 nop + 800002ec: 00000013 nop + 800002f0: 0010cf03 lbu t5,1(ra) + 800002f4: 00000e93 li t4,0 + 800002f8: 05df1863 bne t5,t4,80000348 <fail> + 800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000300: 00200293 li t0,2 + 80000304: fc521ee3 bne tp,t0,800002e0 <test_17+0x8> + +0000000080000308 <test_18>: + 80000308: 00002297 auipc t0,0x2 + 8000030c: cf828293 addi t0,t0,-776 # 80002000 <begin_signature> + 80000310: 0002c103 lbu sp,0(t0) + 80000314: 00200113 li sp,2 + 80000318: 00200e93 li t4,2 + 8000031c: 01200193 li gp,18 + 80000320: 03d11463 bne sp,t4,80000348 <fail> + +0000000080000324 <test_19>: + 80000324: 00002297 auipc t0,0x2 + 80000328: cdc28293 addi t0,t0,-804 # 80002000 <begin_signature> + 8000032c: 0002c103 lbu sp,0(t0) + 80000330: 00000013 nop + 80000334: 00200113 li sp,2 + 80000338: 00200e93 li t4,2 + 8000033c: 01300193 li gp,19 + 80000340: 01d11463 bne sp,t4,80000348 <fail> + 80000344: 00301c63 bne zero,gp,8000035c <pass> + +0000000080000348 <fail>: + 80000348: 0ff0000f fence + 8000034c: 00018063 beqz gp,8000034c <fail+0x4> + 80000350: 00119193 slli gp,gp,0x1 + 80000354: 0011e193 ori gp,gp,1 + 80000358: 00000073 ecall + +000000008000035c <pass>: + 8000035c: 0ff0000f fence + 80000360: 00100193 li gp,1 + 80000364: 00000073 ecall + 80000368: c0001073 unimp + 8000036c: 0000 unimp + 8000036e: 0000 unimp + 80000370: 0000 unimp + 80000372: 0000 unimp + 80000374: 0000 unimp + 80000376: 0000 unimp + 80000378: 0000 unimp + 8000037a: 0000 unimp + 8000037c: 0000 unimp + 8000037e: 0000 unimp + 80000380: 0000 unimp + 80000382: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: 0xff + +0000000080002001 <tdat2>: + 80002001: sd s0,32(s0) + +0000000080002002 <tdat3>: + 80002002: addi a2,sp,988 + +0000000080002003 <tdat4>: + 80002003: 0000000f fence unknown,unknown + 80002007: 0000 unimp + 80002009: 0000 unimp + 8000200b: 0000 unimp + 8000200d: 0000 unimp + 8000200f: 00 Address 0x000000008000200f is out of bounds. + diff --git a/test/riscv/tests/rv64ui-p-lbu.elf b/test/riscv/tests/rv64ui-p-lbu.elf Binary files differnew file mode 100755 index 00000000..e14ea798 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lbu.elf diff --git a/test/riscv/tests/rv64ui-p-ld.dump b/test/riscv/tests/rv64ui-p-ld.dump new file mode 100644 index 00000000..dcebe2d6 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-ld.dump @@ -0,0 +1,406 @@ + +rv64ui-p-ld: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00002097 auipc ra,0x2 + 80000100: f0408093 addi ra,ra,-252 # 80002000 <begin_signature> + 80000104: 0000bf03 ld t5,0(ra) + 80000108: 00ff0eb7 lui t4,0xff0 + 8000010c: 0ffe8e9b addiw t4,t4,255 + 80000110: 010e9e93 slli t4,t4,0x10 + 80000114: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> + 80000118: 010e9e93 slli t4,t4,0x10 + 8000011c: 0ffe8e93 addi t4,t4,255 + 80000120: 00200193 li gp,2 + 80000124: 3bdf1263 bne t5,t4,800004c8 <fail> + +0000000080000128 <test_3>: + 80000128: 00002097 auipc ra,0x2 + 8000012c: ed808093 addi ra,ra,-296 # 80002000 <begin_signature> + 80000130: 0080bf03 ld t5,8(ra) + 80000134: ff010eb7 lui t4,0xff010 + 80000138: f01e8e9b addiw t4,t4,-255 + 8000013c: 010e9e93 slli t4,t4,0x10 + 80000140: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f00dee1> + 80000144: 010e9e93 slli t4,t4,0x10 + 80000148: f00e8e93 addi t4,t4,-256 + 8000014c: 00300193 li gp,3 + 80000150: 37df1c63 bne t5,t4,800004c8 <fail> + +0000000080000154 <test_4>: + 80000154: 00002097 auipc ra,0x2 + 80000158: eac08093 addi ra,ra,-340 # 80002000 <begin_signature> + 8000015c: 0100bf03 ld t5,16(ra) + 80000160: 00010eb7 lui t4,0x10 + 80000164: f01e8e9b addiw t4,t4,-255 + 80000168: 010e9e93 slli t4,t4,0x10 + 8000016c: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> + 80000170: 010e9e93 slli t4,t4,0x10 + 80000174: f01e8e93 addi t4,t4,-255 + 80000178: 00ce9e93 slli t4,t4,0xc + 8000017c: ff0e8e93 addi t4,t4,-16 + 80000180: 00400193 li gp,4 + 80000184: 35df1263 bne t5,t4,800004c8 <fail> + +0000000080000188 <test_5>: + 80000188: 00002097 auipc ra,0x2 + 8000018c: e7808093 addi ra,ra,-392 # 80002000 <begin_signature> + 80000190: 0180bf03 ld t5,24(ra) + 80000194: ffff0eb7 lui t4,0xffff0 + 80000198: 0ffe8e9b addiw t4,t4,255 + 8000019c: 010e9e93 slli t4,t4,0x10 + 800001a0: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffee0df> + 800001a4: 010e9e93 slli t4,t4,0x10 + 800001a8: 0ffe8e93 addi t4,t4,255 + 800001ac: 00ce9e93 slli t4,t4,0xc + 800001b0: 00fe8e93 addi t4,t4,15 + 800001b4: 00500193 li gp,5 + 800001b8: 31df1863 bne t5,t4,800004c8 <fail> + +00000000800001bc <test_6>: + 800001bc: 00002097 auipc ra,0x2 + 800001c0: e5c08093 addi ra,ra,-420 # 80002018 <tdat4> + 800001c4: fe80bf03 ld t5,-24(ra) + 800001c8: 00ff0eb7 lui t4,0xff0 + 800001cc: 0ffe8e9b addiw t4,t4,255 + 800001d0: 010e9e93 slli t4,t4,0x10 + 800001d4: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> + 800001d8: 010e9e93 slli t4,t4,0x10 + 800001dc: 0ffe8e93 addi t4,t4,255 + 800001e0: 00600193 li gp,6 + 800001e4: 2fdf1263 bne t5,t4,800004c8 <fail> + +00000000800001e8 <test_7>: + 800001e8: 00002097 auipc ra,0x2 + 800001ec: e3008093 addi ra,ra,-464 # 80002018 <tdat4> + 800001f0: ff00bf03 ld t5,-16(ra) + 800001f4: ff010eb7 lui t4,0xff010 + 800001f8: f01e8e9b addiw t4,t4,-255 + 800001fc: 010e9e93 slli t4,t4,0x10 + 80000200: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f00dee1> + 80000204: 010e9e93 slli t4,t4,0x10 + 80000208: f00e8e93 addi t4,t4,-256 + 8000020c: 00700193 li gp,7 + 80000210: 2bdf1c63 bne t5,t4,800004c8 <fail> + +0000000080000214 <test_8>: + 80000214: 00002097 auipc ra,0x2 + 80000218: e0408093 addi ra,ra,-508 # 80002018 <tdat4> + 8000021c: ff80bf03 ld t5,-8(ra) + 80000220: 00010eb7 lui t4,0x10 + 80000224: f01e8e9b addiw t4,t4,-255 + 80000228: 010e9e93 slli t4,t4,0x10 + 8000022c: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> + 80000230: 010e9e93 slli t4,t4,0x10 + 80000234: f01e8e93 addi t4,t4,-255 + 80000238: 00ce9e93 slli t4,t4,0xc + 8000023c: ff0e8e93 addi t4,t4,-16 + 80000240: 00800193 li gp,8 + 80000244: 29df1263 bne t5,t4,800004c8 <fail> + +0000000080000248 <test_9>: + 80000248: 00002097 auipc ra,0x2 + 8000024c: dd008093 addi ra,ra,-560 # 80002018 <tdat4> + 80000250: 0000bf03 ld t5,0(ra) + 80000254: ffff0eb7 lui t4,0xffff0 + 80000258: 0ffe8e9b addiw t4,t4,255 + 8000025c: 010e9e93 slli t4,t4,0x10 + 80000260: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffee0df> + 80000264: 010e9e93 slli t4,t4,0x10 + 80000268: 0ffe8e93 addi t4,t4,255 + 8000026c: 00ce9e93 slli t4,t4,0xc + 80000270: 00fe8e93 addi t4,t4,15 + 80000274: 00900193 li gp,9 + 80000278: 25df1863 bne t5,t4,800004c8 <fail> + +000000008000027c <test_10>: + 8000027c: 00002097 auipc ra,0x2 + 80000280: d8408093 addi ra,ra,-636 # 80002000 <begin_signature> + 80000284: fe008093 addi ra,ra,-32 + 80000288: 0200b283 ld t0,32(ra) + 8000028c: 00ff0eb7 lui t4,0xff0 + 80000290: 0ffe8e9b addiw t4,t4,255 + 80000294: 010e9e93 slli t4,t4,0x10 + 80000298: 0ffe8e93 addi t4,t4,255 # ff00ff <_start-0x7f00ff01> + 8000029c: 010e9e93 slli t4,t4,0x10 + 800002a0: 0ffe8e93 addi t4,t4,255 + 800002a4: 00a00193 li gp,10 + 800002a8: 23d29063 bne t0,t4,800004c8 <fail> + +00000000800002ac <test_11>: + 800002ac: 00002097 auipc ra,0x2 + 800002b0: d5408093 addi ra,ra,-684 # 80002000 <begin_signature> + 800002b4: ffd08093 addi ra,ra,-3 + 800002b8: 00b0b283 ld t0,11(ra) + 800002bc: ff010eb7 lui t4,0xff010 + 800002c0: f01e8e9b addiw t4,t4,-255 + 800002c4: 010e9e93 slli t4,t4,0x10 + 800002c8: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f00dee1> + 800002cc: 010e9e93 slli t4,t4,0x10 + 800002d0: f00e8e93 addi t4,t4,-256 + 800002d4: 00b00193 li gp,11 + 800002d8: 1fd29863 bne t0,t4,800004c8 <fail> + +00000000800002dc <test_12>: + 800002dc: 00c00193 li gp,12 + 800002e0: 00000213 li tp,0 + 800002e4: 00002097 auipc ra,0x2 + 800002e8: d2408093 addi ra,ra,-732 # 80002008 <tdat2> + 800002ec: 0080bf03 ld t5,8(ra) + 800002f0: 000f0313 mv t1,t5 + 800002f4: 00010eb7 lui t4,0x10 + 800002f8: f01e8e9b addiw t4,t4,-255 + 800002fc: 010e9e93 slli t4,t4,0x10 + 80000300: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> + 80000304: 010e9e93 slli t4,t4,0x10 + 80000308: f01e8e93 addi t4,t4,-255 + 8000030c: 00ce9e93 slli t4,t4,0xc + 80000310: ff0e8e93 addi t4,t4,-16 + 80000314: 1bd31a63 bne t1,t4,800004c8 <fail> + 80000318: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000031c: 00200293 li t0,2 + 80000320: fc5212e3 bne tp,t0,800002e4 <test_12+0x8> + +0000000080000324 <test_13>: + 80000324: 00d00193 li gp,13 + 80000328: 00000213 li tp,0 + 8000032c: 00002097 auipc ra,0x2 + 80000330: ce408093 addi ra,ra,-796 # 80002010 <tdat3> + 80000334: 0080bf03 ld t5,8(ra) + 80000338: 00000013 nop + 8000033c: 000f0313 mv t1,t5 + 80000340: ffff0eb7 lui t4,0xffff0 + 80000344: 0ffe8e9b addiw t4,t4,255 + 80000348: 010e9e93 slli t4,t4,0x10 + 8000034c: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffee0df> + 80000350: 010e9e93 slli t4,t4,0x10 + 80000354: 0ffe8e93 addi t4,t4,255 + 80000358: 00ce9e93 slli t4,t4,0xc + 8000035c: 00fe8e93 addi t4,t4,15 + 80000360: 17d31463 bne t1,t4,800004c8 <fail> + 80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000368: 00200293 li t0,2 + 8000036c: fc5210e3 bne tp,t0,8000032c <test_13+0x8> + +0000000080000370 <test_14>: + 80000370: 00e00193 li gp,14 + 80000374: 00000213 li tp,0 + 80000378: 00002097 auipc ra,0x2 + 8000037c: c8808093 addi ra,ra,-888 # 80002000 <begin_signature> + 80000380: 0080bf03 ld t5,8(ra) + 80000384: 00000013 nop + 80000388: 00000013 nop + 8000038c: 000f0313 mv t1,t5 + 80000390: ff010eb7 lui t4,0xff010 + 80000394: f01e8e9b addiw t4,t4,-255 + 80000398: 010e9e93 slli t4,t4,0x10 + 8000039c: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f00dee1> + 800003a0: 010e9e93 slli t4,t4,0x10 + 800003a4: f00e8e93 addi t4,t4,-256 + 800003a8: 13d31063 bne t1,t4,800004c8 <fail> + 800003ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003b0: 00200293 li t0,2 + 800003b4: fc5212e3 bne tp,t0,80000378 <test_14+0x8> + +00000000800003b8 <test_15>: + 800003b8: 00f00193 li gp,15 + 800003bc: 00000213 li tp,0 + 800003c0: 00002097 auipc ra,0x2 + 800003c4: c4808093 addi ra,ra,-952 # 80002008 <tdat2> + 800003c8: 0080bf03 ld t5,8(ra) + 800003cc: 00010eb7 lui t4,0x10 + 800003d0: f01e8e9b addiw t4,t4,-255 + 800003d4: 010e9e93 slli t4,t4,0x10 + 800003d8: f01e8e93 addi t4,t4,-255 # ff01 <_start-0x7fff00ff> + 800003dc: 010e9e93 slli t4,t4,0x10 + 800003e0: f01e8e93 addi t4,t4,-255 + 800003e4: 00ce9e93 slli t4,t4,0xc + 800003e8: ff0e8e93 addi t4,t4,-16 + 800003ec: 0ddf1e63 bne t5,t4,800004c8 <fail> + 800003f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003f4: 00200293 li t0,2 + 800003f8: fc5214e3 bne tp,t0,800003c0 <test_15+0x8> + +00000000800003fc <test_16>: + 800003fc: 01000193 li gp,16 + 80000400: 00000213 li tp,0 + 80000404: 00002097 auipc ra,0x2 + 80000408: c0c08093 addi ra,ra,-1012 # 80002010 <tdat3> + 8000040c: 00000013 nop + 80000410: 0080bf03 ld t5,8(ra) + 80000414: ffff0eb7 lui t4,0xffff0 + 80000418: 0ffe8e9b addiw t4,t4,255 + 8000041c: 010e9e93 slli t4,t4,0x10 + 80000420: 0ffe8e93 addi t4,t4,255 # ffffffffffff00ff <_end+0xffffffff7ffee0df> + 80000424: 010e9e93 slli t4,t4,0x10 + 80000428: 0ffe8e93 addi t4,t4,255 + 8000042c: 00ce9e93 slli t4,t4,0xc + 80000430: 00fe8e93 addi t4,t4,15 + 80000434: 09df1a63 bne t5,t4,800004c8 <fail> + 80000438: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000043c: 00200293 li t0,2 + 80000440: fc5212e3 bne tp,t0,80000404 <test_16+0x8> + +0000000080000444 <test_17>: + 80000444: 01100193 li gp,17 + 80000448: 00000213 li tp,0 + 8000044c: 00002097 auipc ra,0x2 + 80000450: bb408093 addi ra,ra,-1100 # 80002000 <begin_signature> + 80000454: 00000013 nop + 80000458: 00000013 nop + 8000045c: 0080bf03 ld t5,8(ra) + 80000460: ff010eb7 lui t4,0xff010 + 80000464: f01e8e9b addiw t4,t4,-255 + 80000468: 010e9e93 slli t4,t4,0x10 + 8000046c: f01e8e93 addi t4,t4,-255 # ffffffffff00ff01 <_end+0xffffffff7f00dee1> + 80000470: 010e9e93 slli t4,t4,0x10 + 80000474: f00e8e93 addi t4,t4,-256 + 80000478: 05df1863 bne t5,t4,800004c8 <fail> + 8000047c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000480: 00200293 li t0,2 + 80000484: fc5214e3 bne tp,t0,8000044c <test_17+0x8> + +0000000080000488 <test_18>: + 80000488: 00002297 auipc t0,0x2 + 8000048c: b7828293 addi t0,t0,-1160 # 80002000 <begin_signature> + 80000490: 0002b103 ld sp,0(t0) + 80000494: 00200113 li sp,2 + 80000498: 00200e93 li t4,2 + 8000049c: 01200193 li gp,18 + 800004a0: 03d11463 bne sp,t4,800004c8 <fail> + +00000000800004a4 <test_19>: + 800004a4: 00002297 auipc t0,0x2 + 800004a8: b5c28293 addi t0,t0,-1188 # 80002000 <begin_signature> + 800004ac: 0002b103 ld sp,0(t0) + 800004b0: 00000013 nop + 800004b4: 00200113 li sp,2 + 800004b8: 00200e93 li t4,2 + 800004bc: 01300193 li gp,19 + 800004c0: 01d11463 bne sp,t4,800004c8 <fail> + 800004c4: 00301c63 bne zero,gp,800004dc <pass> + +00000000800004c8 <fail>: + 800004c8: 0ff0000f fence + 800004cc: 00018063 beqz gp,800004cc <fail+0x4> + 800004d0: 00119193 slli gp,gp,0x1 + 800004d4: 0011e193 ori gp,gp,1 + 800004d8: 00000073 ecall + +00000000800004dc <pass>: + 800004dc: 0ff0000f fence + 800004e0: 00100193 li gp,1 + 800004e4: 00000073 ecall + 800004e8: c0001073 unimp + 800004ec: 0000 unimp + 800004ee: 0000 unimp + 800004f0: 0000 unimp + 800004f2: 0000 unimp + 800004f4: 0000 unimp + 800004f6: 0000 unimp + 800004f8: 0000 unimp + 800004fa: 0000 unimp + 800004fc: 0000 unimp + 800004fe: 0000 unimp + 80000500: 0000 unimp + 80000502: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: 00ff 0xff + 80002002: 00ff 0xff + 80002004: 00ff 0xff + 80002006: 00ff 0xff + +0000000080002008 <tdat2>: + 80002008: ff00 sd s0,56(a4) + 8000200a: ff00 sd s0,56(a4) + 8000200c: ff00 sd s0,56(a4) + 8000200e: ff00 sd s0,56(a4) + +0000000080002010 <tdat3>: + 80002010: 0ff0 addi a2,sp,988 + 80002012: 0ff0 addi a2,sp,988 + 80002014: 0ff0 addi a2,sp,988 + 80002016: 0ff0 addi a2,sp,988 + +0000000080002018 <tdat4>: + 80002018: f00ff00f 0xf00ff00f + 8000201c: f00ff00f 0xf00ff00f diff --git a/test/riscv/tests/rv64ui-p-ld.elf b/test/riscv/tests/rv64ui-p-ld.elf Binary files differnew file mode 100755 index 00000000..5aa623b0 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-ld.elf diff --git a/test/riscv/tests/rv64ui-p-lh.dump b/test/riscv/tests/rv64ui-p-lh.dump new file mode 100644 index 00000000..214e5b07 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lh.dump @@ -0,0 +1,327 @@ + +rv64ui-p-lh: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00002097 auipc ra,0x2 + 80000100: f0408093 addi ra,ra,-252 # 80002000 <begin_signature> + 80000104: 00009f03 lh t5,0(ra) + 80000108: 0ff00e93 li t4,255 + 8000010c: 00200193 li gp,2 + 80000110: 25df1c63 bne t5,t4,80000368 <fail> + +0000000080000114 <test_3>: + 80000114: 00002097 auipc ra,0x2 + 80000118: eec08093 addi ra,ra,-276 # 80002000 <begin_signature> + 8000011c: 00209f03 lh t5,2(ra) + 80000120: f0000e93 li t4,-256 + 80000124: 00300193 li gp,3 + 80000128: 25df1063 bne t5,t4,80000368 <fail> + +000000008000012c <test_4>: + 8000012c: 00002097 auipc ra,0x2 + 80000130: ed408093 addi ra,ra,-300 # 80002000 <begin_signature> + 80000134: 00409f03 lh t5,4(ra) + 80000138: 00001eb7 lui t4,0x1 + 8000013c: ff0e8e9b addiw t4,t4,-16 + 80000140: 00400193 li gp,4 + 80000144: 23df1263 bne t5,t4,80000368 <fail> + +0000000080000148 <test_5>: + 80000148: 00002097 auipc ra,0x2 + 8000014c: eb808093 addi ra,ra,-328 # 80002000 <begin_signature> + 80000150: 00609f03 lh t5,6(ra) + 80000154: fffffeb7 lui t4,0xfffff + 80000158: 00fe8e9b addiw t4,t4,15 + 8000015c: 00500193 li gp,5 + 80000160: 21df1463 bne t5,t4,80000368 <fail> + +0000000080000164 <test_6>: + 80000164: 00002097 auipc ra,0x2 + 80000168: ea208093 addi ra,ra,-350 # 80002006 <tdat4> + 8000016c: ffa09f03 lh t5,-6(ra) + 80000170: 0ff00e93 li t4,255 + 80000174: 00600193 li gp,6 + 80000178: 1fdf1863 bne t5,t4,80000368 <fail> + +000000008000017c <test_7>: + 8000017c: 00002097 auipc ra,0x2 + 80000180: e8a08093 addi ra,ra,-374 # 80002006 <tdat4> + 80000184: ffc09f03 lh t5,-4(ra) + 80000188: f0000e93 li t4,-256 + 8000018c: 00700193 li gp,7 + 80000190: 1ddf1c63 bne t5,t4,80000368 <fail> + +0000000080000194 <test_8>: + 80000194: 00002097 auipc ra,0x2 + 80000198: e7208093 addi ra,ra,-398 # 80002006 <tdat4> + 8000019c: ffe09f03 lh t5,-2(ra) + 800001a0: 00001eb7 lui t4,0x1 + 800001a4: ff0e8e9b addiw t4,t4,-16 + 800001a8: 00800193 li gp,8 + 800001ac: 1bdf1e63 bne t5,t4,80000368 <fail> + +00000000800001b0 <test_9>: + 800001b0: 00002097 auipc ra,0x2 + 800001b4: e5608093 addi ra,ra,-426 # 80002006 <tdat4> + 800001b8: 00009f03 lh t5,0(ra) + 800001bc: fffffeb7 lui t4,0xfffff + 800001c0: 00fe8e9b addiw t4,t4,15 + 800001c4: 00900193 li gp,9 + 800001c8: 1bdf1063 bne t5,t4,80000368 <fail> + +00000000800001cc <test_10>: + 800001cc: 00002097 auipc ra,0x2 + 800001d0: e3408093 addi ra,ra,-460 # 80002000 <begin_signature> + 800001d4: fe008093 addi ra,ra,-32 + 800001d8: 02009283 lh t0,32(ra) + 800001dc: 0ff00e93 li t4,255 + 800001e0: 00a00193 li gp,10 + 800001e4: 19d29263 bne t0,t4,80000368 <fail> + +00000000800001e8 <test_11>: + 800001e8: 00002097 auipc ra,0x2 + 800001ec: e1808093 addi ra,ra,-488 # 80002000 <begin_signature> + 800001f0: ffb08093 addi ra,ra,-5 + 800001f4: 00709283 lh t0,7(ra) + 800001f8: f0000e93 li t4,-256 + 800001fc: 00b00193 li gp,11 + 80000200: 17d29463 bne t0,t4,80000368 <fail> + +0000000080000204 <test_12>: + 80000204: 00c00193 li gp,12 + 80000208: 00000213 li tp,0 + 8000020c: 00002097 auipc ra,0x2 + 80000210: df608093 addi ra,ra,-522 # 80002002 <tdat2> + 80000214: 00209f03 lh t5,2(ra) + 80000218: 000f0313 mv t1,t5 + 8000021c: 00001eb7 lui t4,0x1 + 80000220: ff0e8e9b addiw t4,t4,-16 + 80000224: 15d31263 bne t1,t4,80000368 <fail> + 80000228: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000022c: 00200293 li t0,2 + 80000230: fc521ee3 bne tp,t0,8000020c <test_12+0x8> + +0000000080000234 <test_13>: + 80000234: 00d00193 li gp,13 + 80000238: 00000213 li tp,0 + 8000023c: 00002097 auipc ra,0x2 + 80000240: dc808093 addi ra,ra,-568 # 80002004 <tdat3> + 80000244: 00209f03 lh t5,2(ra) + 80000248: 00000013 nop + 8000024c: 000f0313 mv t1,t5 + 80000250: fffffeb7 lui t4,0xfffff + 80000254: 00fe8e9b addiw t4,t4,15 + 80000258: 11d31863 bne t1,t4,80000368 <fail> + 8000025c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000260: 00200293 li t0,2 + 80000264: fc521ce3 bne tp,t0,8000023c <test_13+0x8> + +0000000080000268 <test_14>: + 80000268: 00e00193 li gp,14 + 8000026c: 00000213 li tp,0 + 80000270: 00002097 auipc ra,0x2 + 80000274: d9008093 addi ra,ra,-624 # 80002000 <begin_signature> + 80000278: 00209f03 lh t5,2(ra) + 8000027c: 00000013 nop + 80000280: 00000013 nop + 80000284: 000f0313 mv t1,t5 + 80000288: f0000e93 li t4,-256 + 8000028c: 0dd31e63 bne t1,t4,80000368 <fail> + 80000290: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000294: 00200293 li t0,2 + 80000298: fc521ce3 bne tp,t0,80000270 <test_14+0x8> + +000000008000029c <test_15>: + 8000029c: 00f00193 li gp,15 + 800002a0: 00000213 li tp,0 + 800002a4: 00002097 auipc ra,0x2 + 800002a8: d5e08093 addi ra,ra,-674 # 80002002 <tdat2> + 800002ac: 00209f03 lh t5,2(ra) + 800002b0: 00001eb7 lui t4,0x1 + 800002b4: ff0e8e9b addiw t4,t4,-16 + 800002b8: 0bdf1863 bne t5,t4,80000368 <fail> + 800002bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002c0: 00200293 li t0,2 + 800002c4: fe5210e3 bne tp,t0,800002a4 <test_15+0x8> + +00000000800002c8 <test_16>: + 800002c8: 01000193 li gp,16 + 800002cc: 00000213 li tp,0 + 800002d0: 00002097 auipc ra,0x2 + 800002d4: d3408093 addi ra,ra,-716 # 80002004 <tdat3> + 800002d8: 00000013 nop + 800002dc: 00209f03 lh t5,2(ra) + 800002e0: fffffeb7 lui t4,0xfffff + 800002e4: 00fe8e9b addiw t4,t4,15 + 800002e8: 09df1063 bne t5,t4,80000368 <fail> + 800002ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002f0: 00200293 li t0,2 + 800002f4: fc521ee3 bne tp,t0,800002d0 <test_16+0x8> + +00000000800002f8 <test_17>: + 800002f8: 01100193 li gp,17 + 800002fc: 00000213 li tp,0 + 80000300: 00002097 auipc ra,0x2 + 80000304: d0008093 addi ra,ra,-768 # 80002000 <begin_signature> + 80000308: 00000013 nop + 8000030c: 00000013 nop + 80000310: 00209f03 lh t5,2(ra) + 80000314: f0000e93 li t4,-256 + 80000318: 05df1863 bne t5,t4,80000368 <fail> + 8000031c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000320: 00200293 li t0,2 + 80000324: fc521ee3 bne tp,t0,80000300 <test_17+0x8> + +0000000080000328 <test_18>: + 80000328: 00002297 auipc t0,0x2 + 8000032c: cd828293 addi t0,t0,-808 # 80002000 <begin_signature> + 80000330: 00029103 lh sp,0(t0) + 80000334: 00200113 li sp,2 + 80000338: 00200e93 li t4,2 + 8000033c: 01200193 li gp,18 + 80000340: 03d11463 bne sp,t4,80000368 <fail> + +0000000080000344 <test_19>: + 80000344: 00002297 auipc t0,0x2 + 80000348: cbc28293 addi t0,t0,-836 # 80002000 <begin_signature> + 8000034c: 00029103 lh sp,0(t0) + 80000350: 00000013 nop + 80000354: 00200113 li sp,2 + 80000358: 00200e93 li t4,2 + 8000035c: 01300193 li gp,19 + 80000360: 01d11463 bne sp,t4,80000368 <fail> + 80000364: 00301c63 bne zero,gp,8000037c <pass> + +0000000080000368 <fail>: + 80000368: 0ff0000f fence + 8000036c: 00018063 beqz gp,8000036c <fail+0x4> + 80000370: 00119193 slli gp,gp,0x1 + 80000374: 0011e193 ori gp,gp,1 + 80000378: 00000073 ecall + +000000008000037c <pass>: + 8000037c: 0ff0000f fence + 80000380: 00100193 li gp,1 + 80000384: 00000073 ecall + 80000388: c0001073 unimp + 8000038c: 0000 unimp + 8000038e: 0000 unimp + 80000390: 0000 unimp + 80000392: 0000 unimp + 80000394: 0000 unimp + 80000396: 0000 unimp + 80000398: 0000 unimp + 8000039a: 0000 unimp + 8000039c: 0000 unimp + 8000039e: 0000 unimp + 800003a0: 0000 unimp + 800003a2: 0000 unimp + 800003a4: 0000 unimp + 800003a6: 0000 unimp + 800003a8: 0000 unimp + 800003aa: 0000 unimp + 800003ac: 0000 unimp + 800003ae: 0000 unimp + 800003b0: 0000 unimp + 800003b2: 0000 unimp + 800003b4: 0000 unimp + 800003b6: 0000 unimp + 800003b8: 0000 unimp + 800003ba: 0000 unimp + 800003bc: 0000 unimp + 800003be: 0000 unimp + 800003c0: 0000 unimp + 800003c2: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: 00ff 0xff + +0000000080002002 <tdat2>: + 80002002: ff00 sd s0,56(a4) + +0000000080002004 <tdat3>: + 80002004: 0ff0 addi a2,sp,988 + +0000000080002006 <tdat4>: + 80002006: 0000f00f 0xf00f + 8000200a: 0000 unimp + 8000200c: 0000 unimp + 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-lh.elf b/test/riscv/tests/rv64ui-p-lh.elf Binary files differnew file mode 100755 index 00000000..30db6615 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lh.elf diff --git a/test/riscv/tests/rv64ui-p-lhu.dump b/test/riscv/tests/rv64ui-p-lhu.dump new file mode 100644 index 00000000..6cc3defc --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lhu.dump @@ -0,0 +1,322 @@ + +rv64ui-p-lhu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00002097 auipc ra,0x2 + 80000100: f0408093 addi ra,ra,-252 # 80002000 <begin_signature> + 80000104: 0000df03 lhu t5,0(ra) + 80000108: 0ff00e93 li t4,255 + 8000010c: 00200193 li gp,2 + 80000110: 27df1663 bne t5,t4,8000037c <fail> + +0000000080000114 <test_3>: + 80000114: 00002097 auipc ra,0x2 + 80000118: eec08093 addi ra,ra,-276 # 80002000 <begin_signature> + 8000011c: 0020df03 lhu t5,2(ra) + 80000120: 00010eb7 lui t4,0x10 + 80000124: f00e8e9b addiw t4,t4,-256 + 80000128: 00300193 li gp,3 + 8000012c: 25df1863 bne t5,t4,8000037c <fail> + +0000000080000130 <test_4>: + 80000130: 00002097 auipc ra,0x2 + 80000134: ed008093 addi ra,ra,-304 # 80002000 <begin_signature> + 80000138: 0040df03 lhu t5,4(ra) + 8000013c: 00001eb7 lui t4,0x1 + 80000140: ff0e8e9b addiw t4,t4,-16 + 80000144: 00400193 li gp,4 + 80000148: 23df1a63 bne t5,t4,8000037c <fail> + +000000008000014c <test_5>: + 8000014c: 00002097 auipc ra,0x2 + 80000150: eb408093 addi ra,ra,-332 # 80002000 <begin_signature> + 80000154: 0060df03 lhu t5,6(ra) + 80000158: 0000feb7 lui t4,0xf + 8000015c: 00fe8e9b addiw t4,t4,15 + 80000160: 00500193 li gp,5 + 80000164: 21df1c63 bne t5,t4,8000037c <fail> + +0000000080000168 <test_6>: + 80000168: 00002097 auipc ra,0x2 + 8000016c: e9e08093 addi ra,ra,-354 # 80002006 <tdat4> + 80000170: ffa0df03 lhu t5,-6(ra) + 80000174: 0ff00e93 li t4,255 + 80000178: 00600193 li gp,6 + 8000017c: 21df1063 bne t5,t4,8000037c <fail> + +0000000080000180 <test_7>: + 80000180: 00002097 auipc ra,0x2 + 80000184: e8608093 addi ra,ra,-378 # 80002006 <tdat4> + 80000188: ffc0df03 lhu t5,-4(ra) + 8000018c: 00010eb7 lui t4,0x10 + 80000190: f00e8e9b addiw t4,t4,-256 + 80000194: 00700193 li gp,7 + 80000198: 1fdf1263 bne t5,t4,8000037c <fail> + +000000008000019c <test_8>: + 8000019c: 00002097 auipc ra,0x2 + 800001a0: e6a08093 addi ra,ra,-406 # 80002006 <tdat4> + 800001a4: ffe0df03 lhu t5,-2(ra) + 800001a8: 00001eb7 lui t4,0x1 + 800001ac: ff0e8e9b addiw t4,t4,-16 + 800001b0: 00800193 li gp,8 + 800001b4: 1ddf1463 bne t5,t4,8000037c <fail> + +00000000800001b8 <test_9>: + 800001b8: 00002097 auipc ra,0x2 + 800001bc: e4e08093 addi ra,ra,-434 # 80002006 <tdat4> + 800001c0: 0000df03 lhu t5,0(ra) + 800001c4: 0000feb7 lui t4,0xf + 800001c8: 00fe8e9b addiw t4,t4,15 + 800001cc: 00900193 li gp,9 + 800001d0: 1bdf1663 bne t5,t4,8000037c <fail> + +00000000800001d4 <test_10>: + 800001d4: 00002097 auipc ra,0x2 + 800001d8: e2c08093 addi ra,ra,-468 # 80002000 <begin_signature> + 800001dc: fe008093 addi ra,ra,-32 + 800001e0: 0200d283 lhu t0,32(ra) + 800001e4: 0ff00e93 li t4,255 + 800001e8: 00a00193 li gp,10 + 800001ec: 19d29863 bne t0,t4,8000037c <fail> + +00000000800001f0 <test_11>: + 800001f0: 00002097 auipc ra,0x2 + 800001f4: e1008093 addi ra,ra,-496 # 80002000 <begin_signature> + 800001f8: ffb08093 addi ra,ra,-5 + 800001fc: 0070d283 lhu t0,7(ra) + 80000200: 00010eb7 lui t4,0x10 + 80000204: f00e8e9b addiw t4,t4,-256 + 80000208: 00b00193 li gp,11 + 8000020c: 17d29863 bne t0,t4,8000037c <fail> + +0000000080000210 <test_12>: + 80000210: 00c00193 li gp,12 + 80000214: 00000213 li tp,0 + 80000218: 00002097 auipc ra,0x2 + 8000021c: dea08093 addi ra,ra,-534 # 80002002 <tdat2> + 80000220: 0020df03 lhu t5,2(ra) + 80000224: 000f0313 mv t1,t5 + 80000228: 00001eb7 lui t4,0x1 + 8000022c: ff0e8e9b addiw t4,t4,-16 + 80000230: 15d31663 bne t1,t4,8000037c <fail> + 80000234: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000238: 00200293 li t0,2 + 8000023c: fc521ee3 bne tp,t0,80000218 <test_12+0x8> + +0000000080000240 <test_13>: + 80000240: 00d00193 li gp,13 + 80000244: 00000213 li tp,0 + 80000248: 00002097 auipc ra,0x2 + 8000024c: dbc08093 addi ra,ra,-580 # 80002004 <tdat3> + 80000250: 0020df03 lhu t5,2(ra) + 80000254: 00000013 nop + 80000258: 000f0313 mv t1,t5 + 8000025c: 0000feb7 lui t4,0xf + 80000260: 00fe8e9b addiw t4,t4,15 + 80000264: 11d31c63 bne t1,t4,8000037c <fail> + 80000268: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000026c: 00200293 li t0,2 + 80000270: fc521ce3 bne tp,t0,80000248 <test_13+0x8> + +0000000080000274 <test_14>: + 80000274: 00e00193 li gp,14 + 80000278: 00000213 li tp,0 + 8000027c: 00002097 auipc ra,0x2 + 80000280: d8408093 addi ra,ra,-636 # 80002000 <begin_signature> + 80000284: 0020df03 lhu t5,2(ra) + 80000288: 00000013 nop + 8000028c: 00000013 nop + 80000290: 000f0313 mv t1,t5 + 80000294: 00010eb7 lui t4,0x10 + 80000298: f00e8e9b addiw t4,t4,-256 + 8000029c: 0fd31063 bne t1,t4,8000037c <fail> + 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a4: 00200293 li t0,2 + 800002a8: fc521ae3 bne tp,t0,8000027c <test_14+0x8> + +00000000800002ac <test_15>: + 800002ac: 00f00193 li gp,15 + 800002b0: 00000213 li tp,0 + 800002b4: 00002097 auipc ra,0x2 + 800002b8: d4e08093 addi ra,ra,-690 # 80002002 <tdat2> + 800002bc: 0020df03 lhu t5,2(ra) + 800002c0: 00001eb7 lui t4,0x1 + 800002c4: ff0e8e9b addiw t4,t4,-16 + 800002c8: 0bdf1a63 bne t5,t4,8000037c <fail> + 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002d0: 00200293 li t0,2 + 800002d4: fe5210e3 bne tp,t0,800002b4 <test_15+0x8> + +00000000800002d8 <test_16>: + 800002d8: 01000193 li gp,16 + 800002dc: 00000213 li tp,0 + 800002e0: 00002097 auipc ra,0x2 + 800002e4: d2408093 addi ra,ra,-732 # 80002004 <tdat3> + 800002e8: 00000013 nop + 800002ec: 0020df03 lhu t5,2(ra) + 800002f0: 0000feb7 lui t4,0xf + 800002f4: 00fe8e9b addiw t4,t4,15 + 800002f8: 09df1263 bne t5,t4,8000037c <fail> + 800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000300: 00200293 li t0,2 + 80000304: fc521ee3 bne tp,t0,800002e0 <test_16+0x8> + +0000000080000308 <test_17>: + 80000308: 01100193 li gp,17 + 8000030c: 00000213 li tp,0 + 80000310: 00002097 auipc ra,0x2 + 80000314: cf008093 addi ra,ra,-784 # 80002000 <begin_signature> + 80000318: 00000013 nop + 8000031c: 00000013 nop + 80000320: 0020df03 lhu t5,2(ra) + 80000324: 00010eb7 lui t4,0x10 + 80000328: f00e8e9b addiw t4,t4,-256 + 8000032c: 05df1863 bne t5,t4,8000037c <fail> + 80000330: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000334: 00200293 li t0,2 + 80000338: fc521ce3 bne tp,t0,80000310 <test_17+0x8> + +000000008000033c <test_18>: + 8000033c: 00002297 auipc t0,0x2 + 80000340: cc428293 addi t0,t0,-828 # 80002000 <begin_signature> + 80000344: 0002d103 lhu sp,0(t0) + 80000348: 00200113 li sp,2 + 8000034c: 00200e93 li t4,2 + 80000350: 01200193 li gp,18 + 80000354: 03d11463 bne sp,t4,8000037c <fail> + +0000000080000358 <test_19>: + 80000358: 00002297 auipc t0,0x2 + 8000035c: ca828293 addi t0,t0,-856 # 80002000 <begin_signature> + 80000360: 0002d103 lhu sp,0(t0) + 80000364: 00000013 nop + 80000368: 00200113 li sp,2 + 8000036c: 00200e93 li t4,2 + 80000370: 01300193 li gp,19 + 80000374: 01d11463 bne sp,t4,8000037c <fail> + 80000378: 00301c63 bne zero,gp,80000390 <pass> + +000000008000037c <fail>: + 8000037c: 0ff0000f fence + 80000380: 00018063 beqz gp,80000380 <fail+0x4> + 80000384: 00119193 slli gp,gp,0x1 + 80000388: 0011e193 ori gp,gp,1 + 8000038c: 00000073 ecall + +0000000080000390 <pass>: + 80000390: 0ff0000f fence + 80000394: 00100193 li gp,1 + 80000398: 00000073 ecall + 8000039c: c0001073 unimp + 800003a0: 0000 unimp + 800003a2: 0000 unimp + 800003a4: 0000 unimp + 800003a6: 0000 unimp + 800003a8: 0000 unimp + 800003aa: 0000 unimp + 800003ac: 0000 unimp + 800003ae: 0000 unimp + 800003b0: 0000 unimp + 800003b2: 0000 unimp + 800003b4: 0000 unimp + 800003b6: 0000 unimp + 800003b8: 0000 unimp + 800003ba: 0000 unimp + 800003bc: 0000 unimp + 800003be: 0000 unimp + 800003c0: 0000 unimp + 800003c2: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: 00ff 0xff + +0000000080002002 <tdat2>: + 80002002: ff00 sd s0,56(a4) + +0000000080002004 <tdat3>: + 80002004: 0ff0 addi a2,sp,988 + +0000000080002006 <tdat4>: + 80002006: 0000f00f 0xf00f + 8000200a: 0000 unimp + 8000200c: 0000 unimp + 8000200e: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-lhu.elf b/test/riscv/tests/rv64ui-p-lhu.elf Binary files differnew file mode 100755 index 00000000..bae5bc05 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lhu.elf diff --git a/test/riscv/tests/rv64ui-p-lui.dump b/test/riscv/tests/rv64ui-p-lui.dump new file mode 100644 index 00000000..329a3c5d --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lui.dump @@ -0,0 +1,127 @@ + +rv64ui-p-lui: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 000000b7 lui ra,0x0 + 80000100: 00000e93 li t4,0 + 80000104: 00200193 li gp,2 + 80000108: 05d09a63 bne ra,t4,8000015c <fail> + +000000008000010c <test_3>: + 8000010c: fffff0b7 lui ra,0xfffff + 80000110: 4010d093 srai ra,ra,0x1 + 80000114: 80000e93 li t4,-2048 + 80000118: 00300193 li gp,3 + 8000011c: 05d09063 bne ra,t4,8000015c <fail> + +0000000080000120 <test_4>: + 80000120: 7ffff0b7 lui ra,0x7ffff + 80000124: 4140d093 srai ra,ra,0x14 + 80000128: 7ff00e93 li t4,2047 + 8000012c: 00400193 li gp,4 + 80000130: 03d09663 bne ra,t4,8000015c <fail> + +0000000080000134 <test_5>: + 80000134: 800000b7 lui ra,0x80000 + 80000138: 4140d093 srai ra,ra,0x14 + 8000013c: 80000e93 li t4,-2048 + 80000140: 00500193 li gp,5 + 80000144: 01d09c63 bne ra,t4,8000015c <fail> + +0000000080000148 <test_6>: + 80000148: 80000037 lui zero,0x80000 + 8000014c: 00000e93 li t4,0 + 80000150: 00600193 li gp,6 + 80000154: 01d01463 bne zero,t4,8000015c <fail> + 80000158: 00301c63 bne zero,gp,80000170 <pass> + +000000008000015c <fail>: + 8000015c: 0ff0000f fence + 80000160: 00018063 beqz gp,80000160 <fail+0x4> + 80000164: 00119193 slli gp,gp,0x1 + 80000168: 0011e193 ori gp,gp,1 + 8000016c: 00000073 ecall + +0000000080000170 <pass>: + 80000170: 0ff0000f fence + 80000174: 00100193 li gp,1 + 80000178: 00000073 ecall + 8000017c: c0001073 unimp + 80000180: 0000 unimp + 80000182: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-lui.elf b/test/riscv/tests/rv64ui-p-lui.elf Binary files differnew file mode 100755 index 00000000..4bf8d97b --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lui.elf diff --git a/test/riscv/tests/rv64ui-p-lw.dump b/test/riscv/tests/rv64ui-p-lw.dump new file mode 100644 index 00000000..889c4521 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lw.dump @@ -0,0 +1,319 @@ + +rv64ui-p-lw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00002097 auipc ra,0x2 + 80000100: f0408093 addi ra,ra,-252 # 80002000 <begin_signature> + 80000104: 0000af03 lw t5,0(ra) + 80000108: 00ff0eb7 lui t4,0xff0 + 8000010c: 0ffe8e9b addiw t4,t4,255 + 80000110: 00200193 li gp,2 + 80000114: 27df1a63 bne t5,t4,80000388 <fail> + +0000000080000118 <test_3>: + 80000118: 00002097 auipc ra,0x2 + 8000011c: ee808093 addi ra,ra,-280 # 80002000 <begin_signature> + 80000120: 0040af03 lw t5,4(ra) + 80000124: ff010eb7 lui t4,0xff010 + 80000128: f00e8e9b addiw t4,t4,-256 + 8000012c: 00300193 li gp,3 + 80000130: 25df1c63 bne t5,t4,80000388 <fail> + +0000000080000134 <test_4>: + 80000134: 00002097 auipc ra,0x2 + 80000138: ecc08093 addi ra,ra,-308 # 80002000 <begin_signature> + 8000013c: 0080af03 lw t5,8(ra) + 80000140: 0ff01eb7 lui t4,0xff01 + 80000144: ff0e8e9b addiw t4,t4,-16 + 80000148: 00400193 li gp,4 + 8000014c: 23df1e63 bne t5,t4,80000388 <fail> + +0000000080000150 <test_5>: + 80000150: 00002097 auipc ra,0x2 + 80000154: eb008093 addi ra,ra,-336 # 80002000 <begin_signature> + 80000158: 00c0af03 lw t5,12(ra) + 8000015c: f00ffeb7 lui t4,0xf00ff + 80000160: 00fe8e9b addiw t4,t4,15 + 80000164: 00500193 li gp,5 + 80000168: 23df1063 bne t5,t4,80000388 <fail> + +000000008000016c <test_6>: + 8000016c: 00002097 auipc ra,0x2 + 80000170: ea008093 addi ra,ra,-352 # 8000200c <tdat4> + 80000174: ff40af03 lw t5,-12(ra) + 80000178: 00ff0eb7 lui t4,0xff0 + 8000017c: 0ffe8e9b addiw t4,t4,255 + 80000180: 00600193 li gp,6 + 80000184: 21df1263 bne t5,t4,80000388 <fail> + +0000000080000188 <test_7>: + 80000188: 00002097 auipc ra,0x2 + 8000018c: e8408093 addi ra,ra,-380 # 8000200c <tdat4> + 80000190: ff80af03 lw t5,-8(ra) + 80000194: ff010eb7 lui t4,0xff010 + 80000198: f00e8e9b addiw t4,t4,-256 + 8000019c: 00700193 li gp,7 + 800001a0: 1fdf1463 bne t5,t4,80000388 <fail> + +00000000800001a4 <test_8>: + 800001a4: 00002097 auipc ra,0x2 + 800001a8: e6808093 addi ra,ra,-408 # 8000200c <tdat4> + 800001ac: ffc0af03 lw t5,-4(ra) + 800001b0: 0ff01eb7 lui t4,0xff01 + 800001b4: ff0e8e9b addiw t4,t4,-16 + 800001b8: 00800193 li gp,8 + 800001bc: 1ddf1663 bne t5,t4,80000388 <fail> + +00000000800001c0 <test_9>: + 800001c0: 00002097 auipc ra,0x2 + 800001c4: e4c08093 addi ra,ra,-436 # 8000200c <tdat4> + 800001c8: 0000af03 lw t5,0(ra) + 800001cc: f00ffeb7 lui t4,0xf00ff + 800001d0: 00fe8e9b addiw t4,t4,15 + 800001d4: 00900193 li gp,9 + 800001d8: 1bdf1863 bne t5,t4,80000388 <fail> + +00000000800001dc <test_10>: + 800001dc: 00002097 auipc ra,0x2 + 800001e0: e2408093 addi ra,ra,-476 # 80002000 <begin_signature> + 800001e4: fe008093 addi ra,ra,-32 + 800001e8: 0200a283 lw t0,32(ra) + 800001ec: 00ff0eb7 lui t4,0xff0 + 800001f0: 0ffe8e9b addiw t4,t4,255 + 800001f4: 00a00193 li gp,10 + 800001f8: 19d29863 bne t0,t4,80000388 <fail> + +00000000800001fc <test_11>: + 800001fc: 00002097 auipc ra,0x2 + 80000200: e0408093 addi ra,ra,-508 # 80002000 <begin_signature> + 80000204: ffd08093 addi ra,ra,-3 + 80000208: 0070a283 lw t0,7(ra) + 8000020c: ff010eb7 lui t4,0xff010 + 80000210: f00e8e9b addiw t4,t4,-256 + 80000214: 00b00193 li gp,11 + 80000218: 17d29863 bne t0,t4,80000388 <fail> + +000000008000021c <test_12>: + 8000021c: 00c00193 li gp,12 + 80000220: 00000213 li tp,0 + 80000224: 00002097 auipc ra,0x2 + 80000228: de008093 addi ra,ra,-544 # 80002004 <tdat2> + 8000022c: 0040af03 lw t5,4(ra) + 80000230: 000f0313 mv t1,t5 + 80000234: 0ff01eb7 lui t4,0xff01 + 80000238: ff0e8e9b addiw t4,t4,-16 + 8000023c: 15d31663 bne t1,t4,80000388 <fail> + 80000240: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000244: 00200293 li t0,2 + 80000248: fc521ee3 bne tp,t0,80000224 <test_12+0x8> + +000000008000024c <test_13>: + 8000024c: 00d00193 li gp,13 + 80000250: 00000213 li tp,0 + 80000254: 00002097 auipc ra,0x2 + 80000258: db408093 addi ra,ra,-588 # 80002008 <tdat3> + 8000025c: 0040af03 lw t5,4(ra) + 80000260: 00000013 nop + 80000264: 000f0313 mv t1,t5 + 80000268: f00ffeb7 lui t4,0xf00ff + 8000026c: 00fe8e9b addiw t4,t4,15 + 80000270: 11d31c63 bne t1,t4,80000388 <fail> + 80000274: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000278: 00200293 li t0,2 + 8000027c: fc521ce3 bne tp,t0,80000254 <test_13+0x8> + +0000000080000280 <test_14>: + 80000280: 00e00193 li gp,14 + 80000284: 00000213 li tp,0 + 80000288: 00002097 auipc ra,0x2 + 8000028c: d7808093 addi ra,ra,-648 # 80002000 <begin_signature> + 80000290: 0040af03 lw t5,4(ra) + 80000294: 00000013 nop + 80000298: 00000013 nop + 8000029c: 000f0313 mv t1,t5 + 800002a0: ff010eb7 lui t4,0xff010 + 800002a4: f00e8e9b addiw t4,t4,-256 + 800002a8: 0fd31063 bne t1,t4,80000388 <fail> + 800002ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002b0: 00200293 li t0,2 + 800002b4: fc521ae3 bne tp,t0,80000288 <test_14+0x8> + +00000000800002b8 <test_15>: + 800002b8: 00f00193 li gp,15 + 800002bc: 00000213 li tp,0 + 800002c0: 00002097 auipc ra,0x2 + 800002c4: d4408093 addi ra,ra,-700 # 80002004 <tdat2> + 800002c8: 0040af03 lw t5,4(ra) + 800002cc: 0ff01eb7 lui t4,0xff01 + 800002d0: ff0e8e9b addiw t4,t4,-16 + 800002d4: 0bdf1a63 bne t5,t4,80000388 <fail> + 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002dc: 00200293 li t0,2 + 800002e0: fe5210e3 bne tp,t0,800002c0 <test_15+0x8> + +00000000800002e4 <test_16>: + 800002e4: 01000193 li gp,16 + 800002e8: 00000213 li tp,0 + 800002ec: 00002097 auipc ra,0x2 + 800002f0: d1c08093 addi ra,ra,-740 # 80002008 <tdat3> + 800002f4: 00000013 nop + 800002f8: 0040af03 lw t5,4(ra) + 800002fc: f00ffeb7 lui t4,0xf00ff + 80000300: 00fe8e9b addiw t4,t4,15 + 80000304: 09df1263 bne t5,t4,80000388 <fail> + 80000308: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000030c: 00200293 li t0,2 + 80000310: fc521ee3 bne tp,t0,800002ec <test_16+0x8> + +0000000080000314 <test_17>: + 80000314: 01100193 li gp,17 + 80000318: 00000213 li tp,0 + 8000031c: 00002097 auipc ra,0x2 + 80000320: ce408093 addi ra,ra,-796 # 80002000 <begin_signature> + 80000324: 00000013 nop + 80000328: 00000013 nop + 8000032c: 0040af03 lw t5,4(ra) + 80000330: ff010eb7 lui t4,0xff010 + 80000334: f00e8e9b addiw t4,t4,-256 + 80000338: 05df1863 bne t5,t4,80000388 <fail> + 8000033c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000340: 00200293 li t0,2 + 80000344: fc521ce3 bne tp,t0,8000031c <test_17+0x8> + +0000000080000348 <test_18>: + 80000348: 00002297 auipc t0,0x2 + 8000034c: cb828293 addi t0,t0,-840 # 80002000 <begin_signature> + 80000350: 0002a103 lw sp,0(t0) + 80000354: 00200113 li sp,2 + 80000358: 00200e93 li t4,2 + 8000035c: 01200193 li gp,18 + 80000360: 03d11463 bne sp,t4,80000388 <fail> + +0000000080000364 <test_19>: + 80000364: 00002297 auipc t0,0x2 + 80000368: c9c28293 addi t0,t0,-868 # 80002000 <begin_signature> + 8000036c: 0002a103 lw sp,0(t0) + 80000370: 00000013 nop + 80000374: 00200113 li sp,2 + 80000378: 00200e93 li t4,2 + 8000037c: 01300193 li gp,19 + 80000380: 01d11463 bne sp,t4,80000388 <fail> + 80000384: 00301c63 bne zero,gp,8000039c <pass> + +0000000080000388 <fail>: + 80000388: 0ff0000f fence + 8000038c: 00018063 beqz gp,8000038c <fail+0x4> + 80000390: 00119193 slli gp,gp,0x1 + 80000394: 0011e193 ori gp,gp,1 + 80000398: 00000073 ecall + +000000008000039c <pass>: + 8000039c: 0ff0000f fence + 800003a0: 00100193 li gp,1 + 800003a4: 00000073 ecall + 800003a8: c0001073 unimp + 800003ac: 0000 unimp + 800003ae: 0000 unimp + 800003b0: 0000 unimp + 800003b2: 0000 unimp + 800003b4: 0000 unimp + 800003b6: 0000 unimp + 800003b8: 0000 unimp + 800003ba: 0000 unimp + 800003bc: 0000 unimp + 800003be: 0000 unimp + 800003c0: 0000 unimp + 800003c2: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: 00ff 0xff + 80002002: 00ff 0xff + +0000000080002004 <tdat2>: + 80002004: ff00 sd s0,56(a4) + 80002006: ff00 sd s0,56(a4) + +0000000080002008 <tdat3>: + 80002008: 0ff0 addi a2,sp,988 + 8000200a: 0ff0 addi a2,sp,988 + +000000008000200c <tdat4>: + 8000200c: f00ff00f 0xf00ff00f diff --git a/test/riscv/tests/rv64ui-p-lw.elf b/test/riscv/tests/rv64ui-p-lw.elf Binary files differnew file mode 100755 index 00000000..d371f1c9 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lw.elf diff --git a/test/riscv/tests/rv64ui-p-lwu.dump b/test/riscv/tests/rv64ui-p-lwu.dump new file mode 100644 index 00000000..21f50ee3 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lwu.dump @@ -0,0 +1,333 @@ + +rv64ui-p-lwu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00002097 auipc ra,0x2 + 80000100: f0408093 addi ra,ra,-252 # 80002000 <begin_signature> + 80000104: 0000ef03 lwu t5,0(ra) + 80000108: 00ff0eb7 lui t4,0xff0 + 8000010c: 0ffe8e9b addiw t4,t4,255 + 80000110: 00200193 li gp,2 + 80000114: 2bdf1e63 bne t5,t4,800003d0 <fail> + +0000000080000118 <test_3>: + 80000118: 00002097 auipc ra,0x2 + 8000011c: ee808093 addi ra,ra,-280 # 80002000 <begin_signature> + 80000120: 0040ef03 lwu t5,4(ra) + 80000124: 00010eb7 lui t4,0x10 + 80000128: f01e8e9b addiw t4,t4,-255 + 8000012c: 010e9e93 slli t4,t4,0x10 + 80000130: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80000134: 00300193 li gp,3 + 80000138: 29df1c63 bne t5,t4,800003d0 <fail> + +000000008000013c <test_4>: + 8000013c: 00002097 auipc ra,0x2 + 80000140: ec408093 addi ra,ra,-316 # 80002000 <begin_signature> + 80000144: 0080ef03 lwu t5,8(ra) + 80000148: 0ff01eb7 lui t4,0xff01 + 8000014c: ff0e8e9b addiw t4,t4,-16 + 80000150: 00400193 li gp,4 + 80000154: 27df1e63 bne t5,t4,800003d0 <fail> + +0000000080000158 <test_5>: + 80000158: 00002097 auipc ra,0x2 + 8000015c: ea808093 addi ra,ra,-344 # 80002000 <begin_signature> + 80000160: 00c0ef03 lwu t5,12(ra) + 80000164: 000f0eb7 lui t4,0xf0 + 80000168: 0ffe8e9b addiw t4,t4,255 + 8000016c: 00ce9e93 slli t4,t4,0xc + 80000170: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80000174: 00500193 li gp,5 + 80000178: 25df1c63 bne t5,t4,800003d0 <fail> + +000000008000017c <test_6>: + 8000017c: 00002097 auipc ra,0x2 + 80000180: e9008093 addi ra,ra,-368 # 8000200c <tdat4> + 80000184: ff40ef03 lwu t5,-12(ra) + 80000188: 00ff0eb7 lui t4,0xff0 + 8000018c: 0ffe8e9b addiw t4,t4,255 + 80000190: 00600193 li gp,6 + 80000194: 23df1e63 bne t5,t4,800003d0 <fail> + +0000000080000198 <test_7>: + 80000198: 00002097 auipc ra,0x2 + 8000019c: e7408093 addi ra,ra,-396 # 8000200c <tdat4> + 800001a0: ff80ef03 lwu t5,-8(ra) + 800001a4: 00010eb7 lui t4,0x10 + 800001a8: f01e8e9b addiw t4,t4,-255 + 800001ac: 010e9e93 slli t4,t4,0x10 + 800001b0: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 800001b4: 00700193 li gp,7 + 800001b8: 21df1c63 bne t5,t4,800003d0 <fail> + +00000000800001bc <test_8>: + 800001bc: 00002097 auipc ra,0x2 + 800001c0: e5008093 addi ra,ra,-432 # 8000200c <tdat4> + 800001c4: ffc0ef03 lwu t5,-4(ra) + 800001c8: 0ff01eb7 lui t4,0xff01 + 800001cc: ff0e8e9b addiw t4,t4,-16 + 800001d0: 00800193 li gp,8 + 800001d4: 1fdf1e63 bne t5,t4,800003d0 <fail> + +00000000800001d8 <test_9>: + 800001d8: 00002097 auipc ra,0x2 + 800001dc: e3408093 addi ra,ra,-460 # 8000200c <tdat4> + 800001e0: 0000ef03 lwu t5,0(ra) + 800001e4: 000f0eb7 lui t4,0xf0 + 800001e8: 0ffe8e9b addiw t4,t4,255 + 800001ec: 00ce9e93 slli t4,t4,0xc + 800001f0: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 800001f4: 00900193 li gp,9 + 800001f8: 1ddf1c63 bne t5,t4,800003d0 <fail> + +00000000800001fc <test_10>: + 800001fc: 00002097 auipc ra,0x2 + 80000200: e0408093 addi ra,ra,-508 # 80002000 <begin_signature> + 80000204: fe008093 addi ra,ra,-32 + 80000208: 0200e283 lwu t0,32(ra) + 8000020c: 00ff0eb7 lui t4,0xff0 + 80000210: 0ffe8e9b addiw t4,t4,255 + 80000214: 00a00193 li gp,10 + 80000218: 1bd29c63 bne t0,t4,800003d0 <fail> + +000000008000021c <test_11>: + 8000021c: 00002097 auipc ra,0x2 + 80000220: de408093 addi ra,ra,-540 # 80002000 <begin_signature> + 80000224: ffd08093 addi ra,ra,-3 + 80000228: 0070e283 lwu t0,7(ra) + 8000022c: 00010eb7 lui t4,0x10 + 80000230: f01e8e9b addiw t4,t4,-255 + 80000234: 010e9e93 slli t4,t4,0x10 + 80000238: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 8000023c: 00b00193 li gp,11 + 80000240: 19d29863 bne t0,t4,800003d0 <fail> + +0000000080000244 <test_12>: + 80000244: 00c00193 li gp,12 + 80000248: 00000213 li tp,0 + 8000024c: 00002097 auipc ra,0x2 + 80000250: db808093 addi ra,ra,-584 # 80002004 <tdat2> + 80000254: 0040ef03 lwu t5,4(ra) + 80000258: 000f0313 mv t1,t5 + 8000025c: 0ff01eb7 lui t4,0xff01 + 80000260: ff0e8e9b addiw t4,t4,-16 + 80000264: 17d31663 bne t1,t4,800003d0 <fail> + 80000268: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000026c: 00200293 li t0,2 + 80000270: fc521ee3 bne tp,t0,8000024c <test_12+0x8> + +0000000080000274 <test_13>: + 80000274: 00d00193 li gp,13 + 80000278: 00000213 li tp,0 + 8000027c: 00002097 auipc ra,0x2 + 80000280: d8c08093 addi ra,ra,-628 # 80002008 <tdat3> + 80000284: 0040ef03 lwu t5,4(ra) + 80000288: 00000013 nop + 8000028c: 000f0313 mv t1,t5 + 80000290: 000f0eb7 lui t4,0xf0 + 80000294: 0ffe8e9b addiw t4,t4,255 + 80000298: 00ce9e93 slli t4,t4,0xc + 8000029c: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 800002a0: 13d31863 bne t1,t4,800003d0 <fail> + 800002a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a8: 00200293 li t0,2 + 800002ac: fc5218e3 bne tp,t0,8000027c <test_13+0x8> + +00000000800002b0 <test_14>: + 800002b0: 00e00193 li gp,14 + 800002b4: 00000213 li tp,0 + 800002b8: 00002097 auipc ra,0x2 + 800002bc: d4808093 addi ra,ra,-696 # 80002000 <begin_signature> + 800002c0: 0040ef03 lwu t5,4(ra) + 800002c4: 00000013 nop + 800002c8: 00000013 nop + 800002cc: 000f0313 mv t1,t5 + 800002d0: 00010eb7 lui t4,0x10 + 800002d4: f01e8e9b addiw t4,t4,-255 + 800002d8: 010e9e93 slli t4,t4,0x10 + 800002dc: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 800002e0: 0fd31863 bne t1,t4,800003d0 <fail> + 800002e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002e8: 00200293 li t0,2 + 800002ec: fc5216e3 bne tp,t0,800002b8 <test_14+0x8> + +00000000800002f0 <test_15>: + 800002f0: 00f00193 li gp,15 + 800002f4: 00000213 li tp,0 + 800002f8: 00002097 auipc ra,0x2 + 800002fc: d0c08093 addi ra,ra,-756 # 80002004 <tdat2> + 80000300: 0040ef03 lwu t5,4(ra) + 80000304: 0ff01eb7 lui t4,0xff01 + 80000308: ff0e8e9b addiw t4,t4,-16 + 8000030c: 0ddf1263 bne t5,t4,800003d0 <fail> + 80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000314: 00200293 li t0,2 + 80000318: fe5210e3 bne tp,t0,800002f8 <test_15+0x8> + +000000008000031c <test_16>: + 8000031c: 01000193 li gp,16 + 80000320: 00000213 li tp,0 + 80000324: 00002097 auipc ra,0x2 + 80000328: ce408093 addi ra,ra,-796 # 80002008 <tdat3> + 8000032c: 00000013 nop + 80000330: 0040ef03 lwu t5,4(ra) + 80000334: 000f0eb7 lui t4,0xf0 + 80000338: 0ffe8e9b addiw t4,t4,255 + 8000033c: 00ce9e93 slli t4,t4,0xc + 80000340: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80000344: 09df1663 bne t5,t4,800003d0 <fail> + 80000348: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000034c: 00200293 li t0,2 + 80000350: fc521ae3 bne tp,t0,80000324 <test_16+0x8> + +0000000080000354 <test_17>: + 80000354: 01100193 li gp,17 + 80000358: 00000213 li tp,0 + 8000035c: 00002097 auipc ra,0x2 + 80000360: ca408093 addi ra,ra,-860 # 80002000 <begin_signature> + 80000364: 00000013 nop + 80000368: 00000013 nop + 8000036c: 0040ef03 lwu t5,4(ra) + 80000370: 00010eb7 lui t4,0x10 + 80000374: f01e8e9b addiw t4,t4,-255 + 80000378: 010e9e93 slli t4,t4,0x10 + 8000037c: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80000380: 05df1863 bne t5,t4,800003d0 <fail> + 80000384: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000388: 00200293 li t0,2 + 8000038c: fc5218e3 bne tp,t0,8000035c <test_17+0x8> + +0000000080000390 <test_18>: + 80000390: 00002297 auipc t0,0x2 + 80000394: c7028293 addi t0,t0,-912 # 80002000 <begin_signature> + 80000398: 0002e103 lwu sp,0(t0) + 8000039c: 00200113 li sp,2 + 800003a0: 00200e93 li t4,2 + 800003a4: 01200193 li gp,18 + 800003a8: 03d11463 bne sp,t4,800003d0 <fail> + +00000000800003ac <test_19>: + 800003ac: 00002297 auipc t0,0x2 + 800003b0: c5428293 addi t0,t0,-940 # 80002000 <begin_signature> + 800003b4: 0002e103 lwu sp,0(t0) + 800003b8: 00000013 nop + 800003bc: 00200113 li sp,2 + 800003c0: 00200e93 li t4,2 + 800003c4: 01300193 li gp,19 + 800003c8: 01d11463 bne sp,t4,800003d0 <fail> + 800003cc: 00301c63 bne zero,gp,800003e4 <pass> + +00000000800003d0 <fail>: + 800003d0: 0ff0000f fence + 800003d4: 00018063 beqz gp,800003d4 <fail+0x4> + 800003d8: 00119193 slli gp,gp,0x1 + 800003dc: 0011e193 ori gp,gp,1 + 800003e0: 00000073 ecall + +00000000800003e4 <pass>: + 800003e4: 0ff0000f fence + 800003e8: 00100193 li gp,1 + 800003ec: 00000073 ecall + 800003f0: c0001073 unimp + 800003f4: 0000 unimp + 800003f6: 0000 unimp + 800003f8: 0000 unimp + 800003fa: 0000 unimp + 800003fc: 0000 unimp + 800003fe: 0000 unimp + 80000400: 0000 unimp + 80000402: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: 00ff 0xff + 80002002: 00ff 0xff + +0000000080002004 <tdat2>: + 80002004: ff00 sd s0,56(a4) + 80002006: ff00 sd s0,56(a4) + +0000000080002008 <tdat3>: + 80002008: 0ff0 addi a2,sp,988 + 8000200a: 0ff0 addi a2,sp,988 + +000000008000200c <tdat4>: + 8000200c: f00ff00f 0xf00ff00f diff --git a/test/riscv/tests/rv64ui-p-lwu.elf b/test/riscv/tests/rv64ui-p-lwu.elf Binary files differnew file mode 100755 index 00000000..c7fedede --- /dev/null +++ b/test/riscv/tests/rv64ui-p-lwu.elf diff --git a/test/riscv/tests/rv64ui-p-or.dump b/test/riscv/tests/rv64ui-p-or.dump new file mode 100644 index 00000000..4ca0b79b --- /dev/null +++ b/test/riscv/tests/rv64ui-p-or.dump @@ -0,0 +1,522 @@ + +rv64ui-p-or: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 000100b7 lui ra,0x10 + 80000100: f010809b addiw ra,ra,-255 + 80000104: 01009093 slli ra,ra,0x10 + 80000108: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 8000010c: 0f0f1137 lui sp,0xf0f1 + 80000110: f0f1011b addiw sp,sp,-241 + 80000114: 0020ef33 or t5,ra,sp + 80000118: 00001eb7 lui t4,0x1 + 8000011c: ff1e8e9b addiw t4,t4,-15 + 80000120: 014e9e93 slli t4,t4,0x14 + 80000124: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80000128: 00200193 li gp,2 + 8000012c: 5bdf1663 bne t5,t4,800006d8 <fail> + +0000000080000130 <test_3>: + 80000130: 0ff010b7 lui ra,0xff01 + 80000134: ff00809b addiw ra,ra,-16 + 80000138: 000f1137 lui sp,0xf1 + 8000013c: f0f1011b addiw sp,sp,-241 + 80000140: 00c11113 slli sp,sp,0xc + 80000144: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80000148: 0020ef33 or t5,ra,sp + 8000014c: 00010eb7 lui t4,0x10 + 80000150: ff1e8e9b addiw t4,t4,-15 + 80000154: 010e9e93 slli t4,t4,0x10 + 80000158: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 8000015c: 00300193 li gp,3 + 80000160: 57df1c63 bne t5,t4,800006d8 <fail> + +0000000080000164 <test_4>: + 80000164: 00ff00b7 lui ra,0xff0 + 80000168: 0ff0809b addiw ra,ra,255 + 8000016c: 0f0f1137 lui sp,0xf0f1 + 80000170: f0f1011b addiw sp,sp,-241 + 80000174: 0020ef33 or t5,ra,sp + 80000178: 0fff1eb7 lui t4,0xfff1 + 8000017c: fffe8e9b addiw t4,t4,-1 + 80000180: 00400193 li gp,4 + 80000184: 55df1a63 bne t5,t4,800006d8 <fail> + +0000000080000188 <test_5>: + 80000188: 000f00b7 lui ra,0xf0 + 8000018c: 0ff0809b addiw ra,ra,255 + 80000190: 00c09093 slli ra,ra,0xc + 80000194: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> + 80000198: 000f1137 lui sp,0xf1 + 8000019c: f0f1011b addiw sp,sp,-241 + 800001a0: 00c11113 slli sp,sp,0xc + 800001a4: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 800001a8: 0020ef33 or t5,ra,sp + 800001ac: 000f1eb7 lui t4,0xf1 + 800001b0: fffe8e9b addiw t4,t4,-1 + 800001b4: 00ce9e93 slli t4,t4,0xc + 800001b8: 0ffe8e93 addi t4,t4,255 # f10ff <_start-0x7ff0ef01> + 800001bc: 00500193 li gp,5 + 800001c0: 51df1c63 bne t5,t4,800006d8 <fail> + +00000000800001c4 <test_6>: + 800001c4: 000100b7 lui ra,0x10 + 800001c8: f010809b addiw ra,ra,-255 + 800001cc: 01009093 slli ra,ra,0x10 + 800001d0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 800001d4: 0f0f1137 lui sp,0xf0f1 + 800001d8: f0f1011b addiw sp,sp,-241 + 800001dc: 0020e0b3 or ra,ra,sp + 800001e0: 00001eb7 lui t4,0x1 + 800001e4: ff1e8e9b addiw t4,t4,-15 + 800001e8: 014e9e93 slli t4,t4,0x14 + 800001ec: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 800001f0: 00600193 li gp,6 + 800001f4: 4fd09263 bne ra,t4,800006d8 <fail> + +00000000800001f8 <test_7>: + 800001f8: 000100b7 lui ra,0x10 + 800001fc: f010809b addiw ra,ra,-255 + 80000200: 01009093 slli ra,ra,0x10 + 80000204: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000208: 0f0f1137 lui sp,0xf0f1 + 8000020c: f0f1011b addiw sp,sp,-241 + 80000210: 0020e133 or sp,ra,sp + 80000214: 00001eb7 lui t4,0x1 + 80000218: ff1e8e9b addiw t4,t4,-15 + 8000021c: 014e9e93 slli t4,t4,0x14 + 80000220: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80000224: 00700193 li gp,7 + 80000228: 4bd11863 bne sp,t4,800006d8 <fail> + +000000008000022c <test_8>: + 8000022c: 000100b7 lui ra,0x10 + 80000230: f010809b addiw ra,ra,-255 + 80000234: 01009093 slli ra,ra,0x10 + 80000238: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 8000023c: 0010e0b3 or ra,ra,ra + 80000240: 00010eb7 lui t4,0x10 + 80000244: f01e8e9b addiw t4,t4,-255 + 80000248: 010e9e93 slli t4,t4,0x10 + 8000024c: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80000250: 00800193 li gp,8 + 80000254: 49d09263 bne ra,t4,800006d8 <fail> + +0000000080000258 <test_9>: + 80000258: 00000213 li tp,0 + 8000025c: 000100b7 lui ra,0x10 + 80000260: f010809b addiw ra,ra,-255 + 80000264: 01009093 slli ra,ra,0x10 + 80000268: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 8000026c: 0f0f1137 lui sp,0xf0f1 + 80000270: f0f1011b addiw sp,sp,-241 + 80000274: 0020ef33 or t5,ra,sp + 80000278: 000f0313 mv t1,t5 + 8000027c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000280: 00200293 li t0,2 + 80000284: fc521ce3 bne tp,t0,8000025c <test_9+0x4> + 80000288: 00001eb7 lui t4,0x1 + 8000028c: ff1e8e9b addiw t4,t4,-15 + 80000290: 014e9e93 slli t4,t4,0x14 + 80000294: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80000298: 00900193 li gp,9 + 8000029c: 43d31e63 bne t1,t4,800006d8 <fail> + +00000000800002a0 <test_10>: + 800002a0: 00000213 li tp,0 + 800002a4: 0ff010b7 lui ra,0xff01 + 800002a8: ff00809b addiw ra,ra,-16 + 800002ac: 000f1137 lui sp,0xf1 + 800002b0: f0f1011b addiw sp,sp,-241 + 800002b4: 00c11113 slli sp,sp,0xc + 800002b8: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 800002bc: 0020ef33 or t5,ra,sp + 800002c0: 00000013 nop + 800002c4: 000f0313 mv t1,t5 + 800002c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002cc: 00200293 li t0,2 + 800002d0: fc521ae3 bne tp,t0,800002a4 <test_10+0x4> + 800002d4: 00010eb7 lui t4,0x10 + 800002d8: ff1e8e9b addiw t4,t4,-15 + 800002dc: 010e9e93 slli t4,t4,0x10 + 800002e0: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 800002e4: 00a00193 li gp,10 + 800002e8: 3fd31863 bne t1,t4,800006d8 <fail> + +00000000800002ec <test_11>: + 800002ec: 00000213 li tp,0 + 800002f0: 00ff00b7 lui ra,0xff0 + 800002f4: 0ff0809b addiw ra,ra,255 + 800002f8: 0f0f1137 lui sp,0xf0f1 + 800002fc: f0f1011b addiw sp,sp,-241 + 80000300: 0020ef33 or t5,ra,sp + 80000304: 00000013 nop + 80000308: 00000013 nop + 8000030c: 000f0313 mv t1,t5 + 80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000314: 00200293 li t0,2 + 80000318: fc521ce3 bne tp,t0,800002f0 <test_11+0x4> + 8000031c: 0fff1eb7 lui t4,0xfff1 + 80000320: fffe8e9b addiw t4,t4,-1 + 80000324: 00b00193 li gp,11 + 80000328: 3bd31863 bne t1,t4,800006d8 <fail> + +000000008000032c <test_12>: + 8000032c: 00000213 li tp,0 + 80000330: 000100b7 lui ra,0x10 + 80000334: f010809b addiw ra,ra,-255 + 80000338: 01009093 slli ra,ra,0x10 + 8000033c: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000340: 0f0f1137 lui sp,0xf0f1 + 80000344: f0f1011b addiw sp,sp,-241 + 80000348: 0020ef33 or t5,ra,sp + 8000034c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000350: 00200293 li t0,2 + 80000354: fc521ee3 bne tp,t0,80000330 <test_12+0x4> + 80000358: 00001eb7 lui t4,0x1 + 8000035c: ff1e8e9b addiw t4,t4,-15 + 80000360: 014e9e93 slli t4,t4,0x14 + 80000364: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80000368: 00c00193 li gp,12 + 8000036c: 37df1663 bne t5,t4,800006d8 <fail> + +0000000080000370 <test_13>: + 80000370: 00000213 li tp,0 + 80000374: 0ff010b7 lui ra,0xff01 + 80000378: ff00809b addiw ra,ra,-16 + 8000037c: 000f1137 lui sp,0xf1 + 80000380: f0f1011b addiw sp,sp,-241 + 80000384: 00c11113 slli sp,sp,0xc + 80000388: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 8000038c: 00000013 nop + 80000390: 0020ef33 or t5,ra,sp + 80000394: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000398: 00200293 li t0,2 + 8000039c: fc521ce3 bne tp,t0,80000374 <test_13+0x4> + 800003a0: 00010eb7 lui t4,0x10 + 800003a4: ff1e8e9b addiw t4,t4,-15 + 800003a8: 010e9e93 slli t4,t4,0x10 + 800003ac: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 800003b0: 00d00193 li gp,13 + 800003b4: 33df1263 bne t5,t4,800006d8 <fail> + +00000000800003b8 <test_14>: + 800003b8: 00000213 li tp,0 + 800003bc: 00ff00b7 lui ra,0xff0 + 800003c0: 0ff0809b addiw ra,ra,255 + 800003c4: 0f0f1137 lui sp,0xf0f1 + 800003c8: f0f1011b addiw sp,sp,-241 + 800003cc: 00000013 nop + 800003d0: 00000013 nop + 800003d4: 0020ef33 or t5,ra,sp + 800003d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003dc: 00200293 li t0,2 + 800003e0: fc521ee3 bne tp,t0,800003bc <test_14+0x4> + 800003e4: 0fff1eb7 lui t4,0xfff1 + 800003e8: fffe8e9b addiw t4,t4,-1 + 800003ec: 00e00193 li gp,14 + 800003f0: 2fdf1463 bne t5,t4,800006d8 <fail> + +00000000800003f4 <test_15>: + 800003f4: 00000213 li tp,0 + 800003f8: 000100b7 lui ra,0x10 + 800003fc: f010809b addiw ra,ra,-255 + 80000400: 01009093 slli ra,ra,0x10 + 80000404: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000408: 00000013 nop + 8000040c: 0f0f1137 lui sp,0xf0f1 + 80000410: f0f1011b addiw sp,sp,-241 + 80000414: 0020ef33 or t5,ra,sp + 80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000041c: 00200293 li t0,2 + 80000420: fc521ce3 bne tp,t0,800003f8 <test_15+0x4> + 80000424: 00001eb7 lui t4,0x1 + 80000428: ff1e8e9b addiw t4,t4,-15 + 8000042c: 014e9e93 slli t4,t4,0x14 + 80000430: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80000434: 00f00193 li gp,15 + 80000438: 2bdf1063 bne t5,t4,800006d8 <fail> + +000000008000043c <test_16>: + 8000043c: 00000213 li tp,0 + 80000440: 0ff010b7 lui ra,0xff01 + 80000444: ff00809b addiw ra,ra,-16 + 80000448: 00000013 nop + 8000044c: 000f1137 lui sp,0xf1 + 80000450: f0f1011b addiw sp,sp,-241 + 80000454: 00c11113 slli sp,sp,0xc + 80000458: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 8000045c: 00000013 nop + 80000460: 0020ef33 or t5,ra,sp + 80000464: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000468: 00200293 li t0,2 + 8000046c: fc521ae3 bne tp,t0,80000440 <test_16+0x4> + 80000470: 00010eb7 lui t4,0x10 + 80000474: ff1e8e9b addiw t4,t4,-15 + 80000478: 010e9e93 slli t4,t4,0x10 + 8000047c: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 80000480: 01000193 li gp,16 + 80000484: 25df1a63 bne t5,t4,800006d8 <fail> + +0000000080000488 <test_17>: + 80000488: 00000213 li tp,0 + 8000048c: 00ff00b7 lui ra,0xff0 + 80000490: 0ff0809b addiw ra,ra,255 + 80000494: 00000013 nop + 80000498: 00000013 nop + 8000049c: 0f0f1137 lui sp,0xf0f1 + 800004a0: f0f1011b addiw sp,sp,-241 + 800004a4: 0020ef33 or t5,ra,sp + 800004a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004ac: 00200293 li t0,2 + 800004b0: fc521ee3 bne tp,t0,8000048c <test_17+0x4> + 800004b4: 0fff1eb7 lui t4,0xfff1 + 800004b8: fffe8e9b addiw t4,t4,-1 + 800004bc: 01100193 li gp,17 + 800004c0: 21df1c63 bne t5,t4,800006d8 <fail> + +00000000800004c4 <test_18>: + 800004c4: 00000213 li tp,0 + 800004c8: 0f0f1137 lui sp,0xf0f1 + 800004cc: f0f1011b addiw sp,sp,-241 + 800004d0: 000100b7 lui ra,0x10 + 800004d4: f010809b addiw ra,ra,-255 + 800004d8: 01009093 slli ra,ra,0x10 + 800004dc: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 800004e0: 0020ef33 or t5,ra,sp + 800004e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004e8: 00200293 li t0,2 + 800004ec: fc521ee3 bne tp,t0,800004c8 <test_18+0x4> + 800004f0: 00001eb7 lui t4,0x1 + 800004f4: ff1e8e9b addiw t4,t4,-15 + 800004f8: 014e9e93 slli t4,t4,0x14 + 800004fc: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 80000500: 01200193 li gp,18 + 80000504: 1ddf1a63 bne t5,t4,800006d8 <fail> + +0000000080000508 <test_19>: + 80000508: 00000213 li tp,0 + 8000050c: 000f1137 lui sp,0xf1 + 80000510: f0f1011b addiw sp,sp,-241 + 80000514: 00c11113 slli sp,sp,0xc + 80000518: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 8000051c: 0ff010b7 lui ra,0xff01 + 80000520: ff00809b addiw ra,ra,-16 + 80000524: 00000013 nop + 80000528: 0020ef33 or t5,ra,sp + 8000052c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000530: 00200293 li t0,2 + 80000534: fc521ce3 bne tp,t0,8000050c <test_19+0x4> + 80000538: 00010eb7 lui t4,0x10 + 8000053c: ff1e8e9b addiw t4,t4,-15 + 80000540: 010e9e93 slli t4,t4,0x10 + 80000544: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 80000548: 01300193 li gp,19 + 8000054c: 19df1663 bne t5,t4,800006d8 <fail> + +0000000080000550 <test_20>: + 80000550: 00000213 li tp,0 + 80000554: 0f0f1137 lui sp,0xf0f1 + 80000558: f0f1011b addiw sp,sp,-241 + 8000055c: 00ff00b7 lui ra,0xff0 + 80000560: 0ff0809b addiw ra,ra,255 + 80000564: 00000013 nop + 80000568: 00000013 nop + 8000056c: 0020ef33 or t5,ra,sp + 80000570: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000574: 00200293 li t0,2 + 80000578: fc521ee3 bne tp,t0,80000554 <test_20+0x4> + 8000057c: 0fff1eb7 lui t4,0xfff1 + 80000580: fffe8e9b addiw t4,t4,-1 + 80000584: 01400193 li gp,20 + 80000588: 15df1863 bne t5,t4,800006d8 <fail> + +000000008000058c <test_21>: + 8000058c: 00000213 li tp,0 + 80000590: 0f0f1137 lui sp,0xf0f1 + 80000594: f0f1011b addiw sp,sp,-241 + 80000598: 00000013 nop + 8000059c: 000100b7 lui ra,0x10 + 800005a0: f010809b addiw ra,ra,-255 + 800005a4: 01009093 slli ra,ra,0x10 + 800005a8: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 800005ac: 0020ef33 or t5,ra,sp + 800005b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005b4: 00200293 li t0,2 + 800005b8: fc521ce3 bne tp,t0,80000590 <test_21+0x4> + 800005bc: 00001eb7 lui t4,0x1 + 800005c0: ff1e8e9b addiw t4,t4,-15 + 800005c4: 014e9e93 slli t4,t4,0x14 + 800005c8: f0fe8e93 addi t4,t4,-241 # f0f <_start-0x7ffff0f1> + 800005cc: 01500193 li gp,21 + 800005d0: 11df1463 bne t5,t4,800006d8 <fail> + +00000000800005d4 <test_22>: + 800005d4: 00000213 li tp,0 + 800005d8: 000f1137 lui sp,0xf1 + 800005dc: f0f1011b addiw sp,sp,-241 + 800005e0: 00c11113 slli sp,sp,0xc + 800005e4: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 800005e8: 00000013 nop + 800005ec: 0ff010b7 lui ra,0xff01 + 800005f0: ff00809b addiw ra,ra,-16 + 800005f4: 00000013 nop + 800005f8: 0020ef33 or t5,ra,sp + 800005fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000600: 00200293 li t0,2 + 80000604: fc521ae3 bne tp,t0,800005d8 <test_22+0x4> + 80000608: 00010eb7 lui t4,0x10 + 8000060c: ff1e8e9b addiw t4,t4,-15 + 80000610: 010e9e93 slli t4,t4,0x10 + 80000614: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 80000618: 01600193 li gp,22 + 8000061c: 0bdf1e63 bne t5,t4,800006d8 <fail> + +0000000080000620 <test_23>: + 80000620: 00000213 li tp,0 + 80000624: 0f0f1137 lui sp,0xf0f1 + 80000628: f0f1011b addiw sp,sp,-241 + 8000062c: 00000013 nop + 80000630: 00000013 nop + 80000634: 00ff00b7 lui ra,0xff0 + 80000638: 0ff0809b addiw ra,ra,255 + 8000063c: 0020ef33 or t5,ra,sp + 80000640: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000644: 00200293 li t0,2 + 80000648: fc521ee3 bne tp,t0,80000624 <test_23+0x4> + 8000064c: 0fff1eb7 lui t4,0xfff1 + 80000650: fffe8e9b addiw t4,t4,-1 + 80000654: 01700193 li gp,23 + 80000658: 09df1063 bne t5,t4,800006d8 <fail> + +000000008000065c <test_24>: + 8000065c: 000100b7 lui ra,0x10 + 80000660: f010809b addiw ra,ra,-255 + 80000664: 01009093 slli ra,ra,0x10 + 80000668: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 8000066c: 00106133 or sp,zero,ra + 80000670: 00010eb7 lui t4,0x10 + 80000674: f01e8e9b addiw t4,t4,-255 + 80000678: 010e9e93 slli t4,t4,0x10 + 8000067c: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80000680: 01800193 li gp,24 + 80000684: 05d11a63 bne sp,t4,800006d8 <fail> + +0000000080000688 <test_25>: + 80000688: 00ff00b7 lui ra,0xff0 + 8000068c: 0ff0809b addiw ra,ra,255 + 80000690: 0000e133 or sp,ra,zero + 80000694: 00ff0eb7 lui t4,0xff0 + 80000698: 0ffe8e9b addiw t4,t4,255 + 8000069c: 01900193 li gp,25 + 800006a0: 03d11c63 bne sp,t4,800006d8 <fail> + +00000000800006a4 <test_26>: + 800006a4: 000060b3 or ra,zero,zero + 800006a8: 00000e93 li t4,0 + 800006ac: 01a00193 li gp,26 + 800006b0: 03d09463 bne ra,t4,800006d8 <fail> + +00000000800006b4 <test_27>: + 800006b4: 111110b7 lui ra,0x11111 + 800006b8: 1110809b addiw ra,ra,273 + 800006bc: 22222137 lui sp,0x22222 + 800006c0: 2221011b addiw sp,sp,546 + 800006c4: 0020e033 or zero,ra,sp + 800006c8: 00000e93 li t4,0 + 800006cc: 01b00193 li gp,27 + 800006d0: 01d01463 bne zero,t4,800006d8 <fail> + 800006d4: 00301c63 bne zero,gp,800006ec <pass> + +00000000800006d8 <fail>: + 800006d8: 0ff0000f fence + 800006dc: 00018063 beqz gp,800006dc <fail+0x4> + 800006e0: 00119193 slli gp,gp,0x1 + 800006e4: 0011e193 ori gp,gp,1 + 800006e8: 00000073 ecall + +00000000800006ec <pass>: + 800006ec: 0ff0000f fence + 800006f0: 00100193 li gp,1 + 800006f4: 00000073 ecall + 800006f8: c0001073 unimp + 800006fc: 0000 unimp + 800006fe: 0000 unimp + 80000700: 0000 unimp + 80000702: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-or.elf b/test/riscv/tests/rv64ui-p-or.elf Binary files differnew file mode 100755 index 00000000..e180a180 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-or.elf diff --git a/test/riscv/tests/rv64ui-p-ori.dump b/test/riscv/tests/rv64ui-p-ori.dump new file mode 100644 index 00000000..c49630b2 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-ori.dump @@ -0,0 +1,268 @@ + +rv64ui-p-ori: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: ff0100b7 lui ra,0xff010 + 80000100: f000809b addiw ra,ra,-256 + 80000104: f0f0ef13 ori t5,ra,-241 + 80000108: f0f00e93 li t4,-241 + 8000010c: 00200193 li gp,2 + 80000110: 1ddf1c63 bne t5,t4,800002e8 <fail> + +0000000080000114 <test_3>: + 80000114: 0ff010b7 lui ra,0xff01 + 80000118: ff00809b addiw ra,ra,-16 + 8000011c: 0f00ef13 ori t5,ra,240 + 80000120: 0ff01eb7 lui t4,0xff01 + 80000124: ff0e8e9b addiw t4,t4,-16 + 80000128: 00300193 li gp,3 + 8000012c: 1bdf1e63 bne t5,t4,800002e8 <fail> + +0000000080000130 <test_4>: + 80000130: 00ff00b7 lui ra,0xff0 + 80000134: 0ff0809b addiw ra,ra,255 + 80000138: 70f0ef13 ori t5,ra,1807 + 8000013c: 00ff0eb7 lui t4,0xff0 + 80000140: 7ffe8e9b addiw t4,t4,2047 + 80000144: 00400193 li gp,4 + 80000148: 1bdf1063 bne t5,t4,800002e8 <fail> + +000000008000014c <test_5>: + 8000014c: f00ff0b7 lui ra,0xf00ff + 80000150: 00f0809b addiw ra,ra,15 + 80000154: 0f00ef13 ori t5,ra,240 + 80000158: f00ffeb7 lui t4,0xf00ff + 8000015c: 0ffe8e9b addiw t4,t4,255 + 80000160: 00500193 li gp,5 + 80000164: 19df1263 bne t5,t4,800002e8 <fail> + +0000000080000168 <test_6>: + 80000168: 000100b7 lui ra,0x10 + 8000016c: f010809b addiw ra,ra,-255 + 80000170: 01009093 slli ra,ra,0x10 + 80000174: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000178: 0f00e093 ori ra,ra,240 + 8000017c: 00010eb7 lui t4,0x10 + 80000180: f01e8e9b addiw t4,t4,-255 + 80000184: 010e9e93 slli t4,t4,0x10 + 80000188: ff0e8e93 addi t4,t4,-16 # fff0 <_start-0x7fff0010> + 8000018c: 00600193 li gp,6 + 80000190: 15d09c63 bne ra,t4,800002e8 <fail> + +0000000080000194 <test_7>: + 80000194: 00000213 li tp,0 + 80000198: 0ff010b7 lui ra,0xff01 + 8000019c: ff00809b addiw ra,ra,-16 + 800001a0: 0f00ef13 ori t5,ra,240 + 800001a4: 000f0313 mv t1,t5 + 800001a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800001ac: 00200293 li t0,2 + 800001b0: fe5214e3 bne tp,t0,80000198 <test_7+0x4> + 800001b4: 0ff01eb7 lui t4,0xff01 + 800001b8: ff0e8e9b addiw t4,t4,-16 + 800001bc: 00700193 li gp,7 + 800001c0: 13d31463 bne t1,t4,800002e8 <fail> + +00000000800001c4 <test_8>: + 800001c4: 00000213 li tp,0 + 800001c8: 00ff00b7 lui ra,0xff0 + 800001cc: 0ff0809b addiw ra,ra,255 + 800001d0: 70f0ef13 ori t5,ra,1807 + 800001d4: 00000013 nop + 800001d8: 000f0313 mv t1,t5 + 800001dc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800001e0: 00200293 li t0,2 + 800001e4: fe5212e3 bne tp,t0,800001c8 <test_8+0x4> + 800001e8: 00ff0eb7 lui t4,0xff0 + 800001ec: 7ffe8e9b addiw t4,t4,2047 + 800001f0: 00800193 li gp,8 + 800001f4: 0fd31a63 bne t1,t4,800002e8 <fail> + +00000000800001f8 <test_9>: + 800001f8: 00000213 li tp,0 + 800001fc: f00ff0b7 lui ra,0xf00ff + 80000200: 00f0809b addiw ra,ra,15 + 80000204: 0f00ef13 ori t5,ra,240 + 80000208: 00000013 nop + 8000020c: 00000013 nop + 80000210: 000f0313 mv t1,t5 + 80000214: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000218: 00200293 li t0,2 + 8000021c: fe5210e3 bne tp,t0,800001fc <test_9+0x4> + 80000220: f00ffeb7 lui t4,0xf00ff + 80000224: 0ffe8e9b addiw t4,t4,255 + 80000228: 00900193 li gp,9 + 8000022c: 0bd31e63 bne t1,t4,800002e8 <fail> + +0000000080000230 <test_10>: + 80000230: 00000213 li tp,0 + 80000234: 0ff010b7 lui ra,0xff01 + 80000238: ff00809b addiw ra,ra,-16 + 8000023c: 0f00ef13 ori t5,ra,240 + 80000240: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000244: 00200293 li t0,2 + 80000248: fe5216e3 bne tp,t0,80000234 <test_10+0x4> + 8000024c: 0ff01eb7 lui t4,0xff01 + 80000250: ff0e8e9b addiw t4,t4,-16 + 80000254: 00a00193 li gp,10 + 80000258: 09df1863 bne t5,t4,800002e8 <fail> + +000000008000025c <test_11>: + 8000025c: 00000213 li tp,0 + 80000260: 00ff00b7 lui ra,0xff0 + 80000264: 0ff0809b addiw ra,ra,255 + 80000268: 00000013 nop + 8000026c: f0f0ef13 ori t5,ra,-241 + 80000270: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000274: 00200293 li t0,2 + 80000278: fe5214e3 bne tp,t0,80000260 <test_11+0x4> + 8000027c: fff00e93 li t4,-1 + 80000280: 00b00193 li gp,11 + 80000284: 07df1263 bne t5,t4,800002e8 <fail> + +0000000080000288 <test_12>: + 80000288: 00000213 li tp,0 + 8000028c: f00ff0b7 lui ra,0xf00ff + 80000290: 00f0809b addiw ra,ra,15 + 80000294: 00000013 nop + 80000298: 00000013 nop + 8000029c: 0f00ef13 ori t5,ra,240 + 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a4: 00200293 li t0,2 + 800002a8: fe5212e3 bne tp,t0,8000028c <test_12+0x4> + 800002ac: f00ffeb7 lui t4,0xf00ff + 800002b0: 0ffe8e9b addiw t4,t4,255 + 800002b4: 00c00193 li gp,12 + 800002b8: 03df1863 bne t5,t4,800002e8 <fail> + +00000000800002bc <test_13>: + 800002bc: 0f006093 ori ra,zero,240 + 800002c0: 0f000e93 li t4,240 + 800002c4: 00d00193 li gp,13 + 800002c8: 03d09063 bne ra,t4,800002e8 <fail> + +00000000800002cc <test_14>: + 800002cc: 00ff00b7 lui ra,0xff0 + 800002d0: 0ff0809b addiw ra,ra,255 + 800002d4: 70f0e013 ori zero,ra,1807 + 800002d8: 00000e93 li t4,0 + 800002dc: 00e00193 li gp,14 + 800002e0: 01d01463 bne zero,t4,800002e8 <fail> + 800002e4: 00301c63 bne zero,gp,800002fc <pass> + +00000000800002e8 <fail>: + 800002e8: 0ff0000f fence + 800002ec: 00018063 beqz gp,800002ec <fail+0x4> + 800002f0: 00119193 slli gp,gp,0x1 + 800002f4: 0011e193 ori gp,gp,1 + 800002f8: 00000073 ecall + +00000000800002fc <pass>: + 800002fc: 0ff0000f fence + 80000300: 00100193 li gp,1 + 80000304: 00000073 ecall + 80000308: c0001073 unimp + 8000030c: 0000 unimp + 8000030e: 0000 unimp + 80000310: 0000 unimp + 80000312: 0000 unimp + 80000314: 0000 unimp + 80000316: 0000 unimp + 80000318: 0000 unimp + 8000031a: 0000 unimp + 8000031c: 0000 unimp + 8000031e: 0000 unimp + 80000320: 0000 unimp + 80000322: 0000 unimp + 80000324: 0000 unimp + 80000326: 0000 unimp + 80000328: 0000 unimp + 8000032a: 0000 unimp + 8000032c: 0000 unimp + 8000032e: 0000 unimp + 80000330: 0000 unimp + 80000332: 0000 unimp + 80000334: 0000 unimp + 80000336: 0000 unimp + 80000338: 0000 unimp + 8000033a: 0000 unimp + 8000033c: 0000 unimp + 8000033e: 0000 unimp + 80000340: 0000 unimp + 80000342: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-ori.elf b/test/riscv/tests/rv64ui-p-ori.elf Binary files differnew file mode 100755 index 00000000..c1f8f066 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-ori.elf diff --git a/test/riscv/tests/rv64ui-p-sb.dump b/test/riscv/tests/rv64ui-p-sb.dump new file mode 100644 index 00000000..5bf111f7 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sb.dump @@ -0,0 +1,447 @@ + +rv64ui-p-sb: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00002097 auipc ra,0x2 + 80000100: f0408093 addi ra,ra,-252 # 80002000 <begin_signature> + 80000104: faa00113 li sp,-86 + 80000108: 00208023 sb sp,0(ra) + 8000010c: 00008f03 lb t5,0(ra) + 80000110: faa00e93 li t4,-86 + 80000114: 00200193 li gp,2 + 80000118: 3ddf1c63 bne t5,t4,800004f0 <fail> + +000000008000011c <test_3>: + 8000011c: 00002097 auipc ra,0x2 + 80000120: ee408093 addi ra,ra,-284 # 80002000 <begin_signature> + 80000124: 00000113 li sp,0 + 80000128: 002080a3 sb sp,1(ra) + 8000012c: 00108f03 lb t5,1(ra) + 80000130: 00000e93 li t4,0 + 80000134: 00300193 li gp,3 + 80000138: 3bdf1c63 bne t5,t4,800004f0 <fail> + +000000008000013c <test_4>: + 8000013c: 00002097 auipc ra,0x2 + 80000140: ec408093 addi ra,ra,-316 # 80002000 <begin_signature> + 80000144: fffff137 lui sp,0xfffff + 80000148: fa01011b addiw sp,sp,-96 + 8000014c: 00208123 sb sp,2(ra) + 80000150: 00209f03 lh t5,2(ra) + 80000154: fffffeb7 lui t4,0xfffff + 80000158: fa0e8e9b addiw t4,t4,-96 + 8000015c: 00400193 li gp,4 + 80000160: 39df1863 bne t5,t4,800004f0 <fail> + +0000000080000164 <test_5>: + 80000164: 00002097 auipc ra,0x2 + 80000168: e9c08093 addi ra,ra,-356 # 80002000 <begin_signature> + 8000016c: 00a00113 li sp,10 + 80000170: 002081a3 sb sp,3(ra) + 80000174: 00308f03 lb t5,3(ra) + 80000178: 00a00e93 li t4,10 + 8000017c: 00500193 li gp,5 + 80000180: 37df1863 bne t5,t4,800004f0 <fail> + +0000000080000184 <test_6>: + 80000184: 00002097 auipc ra,0x2 + 80000188: e8308093 addi ra,ra,-381 # 80002007 <tdat8> + 8000018c: faa00113 li sp,-86 + 80000190: fe208ea3 sb sp,-3(ra) + 80000194: ffd08f03 lb t5,-3(ra) + 80000198: faa00e93 li t4,-86 + 8000019c: 00600193 li gp,6 + 800001a0: 35df1863 bne t5,t4,800004f0 <fail> + +00000000800001a4 <test_7>: + 800001a4: 00002097 auipc ra,0x2 + 800001a8: e6308093 addi ra,ra,-413 # 80002007 <tdat8> + 800001ac: 00000113 li sp,0 + 800001b0: fe208f23 sb sp,-2(ra) + 800001b4: ffe08f03 lb t5,-2(ra) + 800001b8: 00000e93 li t4,0 + 800001bc: 00700193 li gp,7 + 800001c0: 33df1863 bne t5,t4,800004f0 <fail> + +00000000800001c4 <test_8>: + 800001c4: 00002097 auipc ra,0x2 + 800001c8: e4308093 addi ra,ra,-445 # 80002007 <tdat8> + 800001cc: fa000113 li sp,-96 + 800001d0: fe208fa3 sb sp,-1(ra) + 800001d4: fff08f03 lb t5,-1(ra) + 800001d8: fa000e93 li t4,-96 + 800001dc: 00800193 li gp,8 + 800001e0: 31df1863 bne t5,t4,800004f0 <fail> + +00000000800001e4 <test_9>: + 800001e4: 00002097 auipc ra,0x2 + 800001e8: e2308093 addi ra,ra,-477 # 80002007 <tdat8> + 800001ec: 00a00113 li sp,10 + 800001f0: 00208023 sb sp,0(ra) + 800001f4: 00008f03 lb t5,0(ra) + 800001f8: 00a00e93 li t4,10 + 800001fc: 00900193 li gp,9 + 80000200: 2fdf1863 bne t5,t4,800004f0 <fail> + +0000000080000204 <test_10>: + 80000204: 00002097 auipc ra,0x2 + 80000208: e0408093 addi ra,ra,-508 # 80002008 <tdat9> + 8000020c: 12345137 lui sp,0x12345 + 80000210: 6781011b addiw sp,sp,1656 + 80000214: fe008213 addi tp,ra,-32 + 80000218: 02220023 sb sp,32(tp) # 20 <_start-0x7fffffe0> + 8000021c: 00008283 lb t0,0(ra) + 80000220: 07800e93 li t4,120 + 80000224: 00a00193 li gp,10 + 80000228: 2dd29463 bne t0,t4,800004f0 <fail> + +000000008000022c <test_11>: + 8000022c: 00002097 auipc ra,0x2 + 80000230: ddc08093 addi ra,ra,-548 # 80002008 <tdat9> + 80000234: 00003137 lui sp,0x3 + 80000238: 0981011b addiw sp,sp,152 + 8000023c: ffa08093 addi ra,ra,-6 + 80000240: 002083a3 sb sp,7(ra) + 80000244: 00002217 auipc tp,0x2 + 80000248: dc520213 addi tp,tp,-571 # 80002009 <tdat10> + 8000024c: 00020283 lb t0,0(tp) # 0 <_start-0x80000000> + 80000250: f9800e93 li t4,-104 + 80000254: 00b00193 li gp,11 + 80000258: 29d29c63 bne t0,t4,800004f0 <fail> + +000000008000025c <test_12>: + 8000025c: 00c00193 li gp,12 + 80000260: 00000213 li tp,0 + 80000264: fdd00093 li ra,-35 + 80000268: 00002117 auipc sp,0x2 + 8000026c: d9810113 addi sp,sp,-616 # 80002000 <begin_signature> + 80000270: 00110023 sb ra,0(sp) + 80000274: 00010f03 lb t5,0(sp) + 80000278: fdd00e93 li t4,-35 + 8000027c: 27df1a63 bne t5,t4,800004f0 <fail> + 80000280: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000284: 00200293 li t0,2 + 80000288: fc521ee3 bne tp,t0,80000264 <test_12+0x8> + +000000008000028c <test_13>: + 8000028c: 00d00193 li gp,13 + 80000290: 00000213 li tp,0 + 80000294: fcd00093 li ra,-51 + 80000298: 00002117 auipc sp,0x2 + 8000029c: d6810113 addi sp,sp,-664 # 80002000 <begin_signature> + 800002a0: 00000013 nop + 800002a4: 001100a3 sb ra,1(sp) + 800002a8: 00110f03 lb t5,1(sp) + 800002ac: fcd00e93 li t4,-51 + 800002b0: 25df1063 bne t5,t4,800004f0 <fail> + 800002b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002b8: 00200293 li t0,2 + 800002bc: fc521ce3 bne tp,t0,80000294 <test_13+0x8> + +00000000800002c0 <test_14>: + 800002c0: 00e00193 li gp,14 + 800002c4: 00000213 li tp,0 + 800002c8: fcc00093 li ra,-52 + 800002cc: 00002117 auipc sp,0x2 + 800002d0: d3410113 addi sp,sp,-716 # 80002000 <begin_signature> + 800002d4: 00000013 nop + 800002d8: 00000013 nop + 800002dc: 00110123 sb ra,2(sp) + 800002e0: 00210f03 lb t5,2(sp) + 800002e4: fcc00e93 li t4,-52 + 800002e8: 21df1463 bne t5,t4,800004f0 <fail> + 800002ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002f0: 00200293 li t0,2 + 800002f4: fc521ae3 bne tp,t0,800002c8 <test_14+0x8> + +00000000800002f8 <test_15>: + 800002f8: 00f00193 li gp,15 + 800002fc: 00000213 li tp,0 + 80000300: fbc00093 li ra,-68 + 80000304: 00000013 nop + 80000308: 00002117 auipc sp,0x2 + 8000030c: cf810113 addi sp,sp,-776 # 80002000 <begin_signature> + 80000310: 001101a3 sb ra,3(sp) + 80000314: 00310f03 lb t5,3(sp) + 80000318: fbc00e93 li t4,-68 + 8000031c: 1ddf1a63 bne t5,t4,800004f0 <fail> + 80000320: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000324: 00200293 li t0,2 + 80000328: fc521ce3 bne tp,t0,80000300 <test_15+0x8> + +000000008000032c <test_16>: + 8000032c: 01000193 li gp,16 + 80000330: 00000213 li tp,0 + 80000334: fbb00093 li ra,-69 + 80000338: 00000013 nop + 8000033c: 00002117 auipc sp,0x2 + 80000340: cc410113 addi sp,sp,-828 # 80002000 <begin_signature> + 80000344: 00000013 nop + 80000348: 00110223 sb ra,4(sp) + 8000034c: 00410f03 lb t5,4(sp) + 80000350: fbb00e93 li t4,-69 + 80000354: 19df1e63 bne t5,t4,800004f0 <fail> + 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000035c: 00200293 li t0,2 + 80000360: fc521ae3 bne tp,t0,80000334 <test_16+0x8> + +0000000080000364 <test_17>: + 80000364: 01100193 li gp,17 + 80000368: 00000213 li tp,0 + 8000036c: fab00093 li ra,-85 + 80000370: 00000013 nop + 80000374: 00000013 nop + 80000378: 00002117 auipc sp,0x2 + 8000037c: c8810113 addi sp,sp,-888 # 80002000 <begin_signature> + 80000380: 001102a3 sb ra,5(sp) + 80000384: 00510f03 lb t5,5(sp) + 80000388: fab00e93 li t4,-85 + 8000038c: 17df1263 bne t5,t4,800004f0 <fail> + 80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000394: 00200293 li t0,2 + 80000398: fc521ae3 bne tp,t0,8000036c <test_17+0x8> + +000000008000039c <test_18>: + 8000039c: 01200193 li gp,18 + 800003a0: 00000213 li tp,0 + 800003a4: 00002117 auipc sp,0x2 + 800003a8: c5c10113 addi sp,sp,-932 # 80002000 <begin_signature> + 800003ac: 03300093 li ra,51 + 800003b0: 00110023 sb ra,0(sp) + 800003b4: 00010f03 lb t5,0(sp) + 800003b8: 03300e93 li t4,51 + 800003bc: 13df1a63 bne t5,t4,800004f0 <fail> + 800003c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003c4: 00200293 li t0,2 + 800003c8: fc521ee3 bne tp,t0,800003a4 <test_18+0x8> + +00000000800003cc <test_19>: + 800003cc: 01300193 li gp,19 + 800003d0: 00000213 li tp,0 + 800003d4: 00002117 auipc sp,0x2 + 800003d8: c2c10113 addi sp,sp,-980 # 80002000 <begin_signature> + 800003dc: 02300093 li ra,35 + 800003e0: 00000013 nop + 800003e4: 001100a3 sb ra,1(sp) + 800003e8: 00110f03 lb t5,1(sp) + 800003ec: 02300e93 li t4,35 + 800003f0: 11df1063 bne t5,t4,800004f0 <fail> + 800003f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003f8: 00200293 li t0,2 + 800003fc: fc521ce3 bne tp,t0,800003d4 <test_19+0x8> + +0000000080000400 <test_20>: + 80000400: 01400193 li gp,20 + 80000404: 00000213 li tp,0 + 80000408: 00002117 auipc sp,0x2 + 8000040c: bf810113 addi sp,sp,-1032 # 80002000 <begin_signature> + 80000410: 02200093 li ra,34 + 80000414: 00000013 nop + 80000418: 00000013 nop + 8000041c: 00110123 sb ra,2(sp) + 80000420: 00210f03 lb t5,2(sp) + 80000424: 02200e93 li t4,34 + 80000428: 0ddf1463 bne t5,t4,800004f0 <fail> + 8000042c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000430: 00200293 li t0,2 + 80000434: fc521ae3 bne tp,t0,80000408 <test_20+0x8> + +0000000080000438 <test_21>: + 80000438: 01500193 li gp,21 + 8000043c: 00000213 li tp,0 + 80000440: 00002117 auipc sp,0x2 + 80000444: bc010113 addi sp,sp,-1088 # 80002000 <begin_signature> + 80000448: 00000013 nop + 8000044c: 01200093 li ra,18 + 80000450: 001101a3 sb ra,3(sp) + 80000454: 00310f03 lb t5,3(sp) + 80000458: 01200e93 li t4,18 + 8000045c: 09df1a63 bne t5,t4,800004f0 <fail> + 80000460: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000464: 00200293 li t0,2 + 80000468: fc521ce3 bne tp,t0,80000440 <test_21+0x8> + +000000008000046c <test_22>: + 8000046c: 01600193 li gp,22 + 80000470: 00000213 li tp,0 + 80000474: 00002117 auipc sp,0x2 + 80000478: b8c10113 addi sp,sp,-1140 # 80002000 <begin_signature> + 8000047c: 00000013 nop + 80000480: 01100093 li ra,17 + 80000484: 00000013 nop + 80000488: 00110223 sb ra,4(sp) + 8000048c: 00410f03 lb t5,4(sp) + 80000490: 01100e93 li t4,17 + 80000494: 05df1e63 bne t5,t4,800004f0 <fail> + 80000498: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000049c: 00200293 li t0,2 + 800004a0: fc521ae3 bne tp,t0,80000474 <test_22+0x8> + +00000000800004a4 <test_23>: + 800004a4: 01700193 li gp,23 + 800004a8: 00000213 li tp,0 + 800004ac: 00002117 auipc sp,0x2 + 800004b0: b5410113 addi sp,sp,-1196 # 80002000 <begin_signature> + 800004b4: 00000013 nop + 800004b8: 00000013 nop + 800004bc: 00100093 li ra,1 + 800004c0: 001102a3 sb ra,5(sp) + 800004c4: 00510f03 lb t5,5(sp) + 800004c8: 00100e93 li t4,1 + 800004cc: 03df1263 bne t5,t4,800004f0 <fail> + 800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004d4: 00200293 li t0,2 + 800004d8: fc521ae3 bne tp,t0,800004ac <test_23+0x8> + 800004dc: 0ef00513 li a0,239 + 800004e0: 00002597 auipc a1,0x2 + 800004e4: b2058593 addi a1,a1,-1248 # 80002000 <begin_signature> + 800004e8: 00a581a3 sb a0,3(a1) + 800004ec: 00301c63 bne zero,gp,80000504 <pass> + +00000000800004f0 <fail>: + 800004f0: 0ff0000f fence + 800004f4: 00018063 beqz gp,800004f4 <fail+0x4> + 800004f8: 00119193 slli gp,gp,0x1 + 800004fc: 0011e193 ori gp,gp,1 + 80000500: 00000073 ecall + +0000000080000504 <pass>: + 80000504: 0ff0000f fence + 80000508: 00100193 li gp,1 + 8000050c: 00000073 ecall + 80000510: c0001073 unimp + 80000514: 0000 unimp + 80000516: 0000 unimp + 80000518: 0000 unimp + 8000051a: 0000 unimp + 8000051c: 0000 unimp + 8000051e: 0000 unimp + 80000520: 0000 unimp + 80000522: 0000 unimp + 80000524: 0000 unimp + 80000526: 0000 unimp + 80000528: 0000 unimp + 8000052a: 0000 unimp + 8000052c: 0000 unimp + 8000052e: 0000 unimp + 80000530: 0000 unimp + 80000532: 0000 unimp + 80000534: 0000 unimp + 80000536: 0000 unimp + 80000538: 0000 unimp + 8000053a: 0000 unimp + 8000053c: 0000 unimp + 8000053e: 0000 unimp + 80000540: 0000 unimp + 80000542: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: jal t6,800006fe <pass+0x1fa> + +0000000080002001 <tdat2>: + 80002001: jal t6,800006ff <pass+0x1fb> + +0000000080002002 <tdat3>: + 80002002: jal t6,80000700 <pass+0x1fc> + +0000000080002003 <tdat4>: + 80002003: jal t6,80000701 <pass+0x1fd> + +0000000080002004 <tdat5>: + 80002004: jal t6,80000702 <pass+0x1fe> + +0000000080002005 <tdat6>: + 80002005: jal t6,80000703 <pass+0x1ff> + +0000000080002006 <tdat7>: + 80002006: jal t6,80000704 <pass+0x200> + +0000000080002007 <tdat8>: + 80002007: jal t6,80100015 <_end+0xfe005> + +0000000080002008 <tdat9>: + 80002008: jal t6,80010008 <_end+0xdff8> + +0000000080002009 <tdat10>: + 80002009: 000000ef jal ra,80002009 <tdat10> + 8000200d: 0000 unimp + 8000200f: 00 Address 0x000000008000200f is out of bounds. + diff --git a/test/riscv/tests/rv64ui-p-sb.elf b/test/riscv/tests/rv64ui-p-sb.elf Binary files differnew file mode 100755 index 00000000..85999d6b --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sb.elf diff --git a/test/riscv/tests/rv64ui-p-sd.dump b/test/riscv/tests/rv64ui-p-sd.dump new file mode 100644 index 00000000..56249fa2 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sd.dump @@ -0,0 +1,594 @@ + +rv64ui-p-sd: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00002097 auipc ra,0x2 + 80000100: f0408093 addi ra,ra,-252 # 80002000 <begin_signature> + 80000104: 00550137 lui sp,0x550 + 80000108: 0551011b addiw sp,sp,85 + 8000010c: 01011113 slli sp,sp,0x10 + 80000110: 05510113 addi sp,sp,85 # 550055 <_start-0x7faaffab> + 80000114: 01111113 slli sp,sp,0x11 + 80000118: 0aa10113 addi sp,sp,170 + 8000011c: 0020b023 sd sp,0(ra) + 80000120: 0000bf03 ld t5,0(ra) + 80000124: 00550eb7 lui t4,0x550 + 80000128: 055e8e9b addiw t4,t4,85 + 8000012c: 010e9e93 slli t4,t4,0x10 + 80000130: 055e8e93 addi t4,t4,85 # 550055 <_start-0x7faaffab> + 80000134: 011e9e93 slli t4,t4,0x11 + 80000138: 0aae8e93 addi t4,t4,170 + 8000013c: 00200193 li gp,2 + 80000140: 61df1063 bne t5,t4,80000740 <fail> + +0000000080000144 <test_3>: + 80000144: 00002097 auipc ra,0x2 + 80000148: ebc08093 addi ra,ra,-324 # 80002000 <begin_signature> + 8000014c: ffd50137 lui sp,0xffd50 + 80000150: 0551011b addiw sp,sp,85 + 80000154: 01011113 slli sp,sp,0x10 + 80000158: 05510113 addi sp,sp,85 # ffffffffffd50055 <_end+0xffffffff7fd4e005> + 8000015c: 00d11113 slli sp,sp,0xd + 80000160: 00b10113 addi sp,sp,11 + 80000164: 00c11113 slli sp,sp,0xc + 80000168: a0010113 addi sp,sp,-1536 + 8000016c: 0020b423 sd sp,8(ra) + 80000170: 0080bf03 ld t5,8(ra) + 80000174: ffd50eb7 lui t4,0xffd50 + 80000178: 055e8e9b addiw t4,t4,85 + 8000017c: 010e9e93 slli t4,t4,0x10 + 80000180: 055e8e93 addi t4,t4,85 # ffffffffffd50055 <_end+0xffffffff7fd4e005> + 80000184: 00de9e93 slli t4,t4,0xd + 80000188: 00be8e93 addi t4,t4,11 + 8000018c: 00ce9e93 slli t4,t4,0xc + 80000190: a00e8e93 addi t4,t4,-1536 + 80000194: 00300193 li gp,3 + 80000198: 5bdf1463 bne t5,t4,80000740 <fail> + +000000008000019c <test_4>: + 8000019c: 00002097 auipc ra,0x2 + 800001a0: e6408093 addi ra,ra,-412 # 80002000 <begin_signature> + 800001a4: 00550137 lui sp,0x550 + 800001a8: 0551011b addiw sp,sp,85 + 800001ac: 00d11113 slli sp,sp,0xd + 800001b0: 00b10113 addi sp,sp,11 # 55000b <_start-0x7faafff5> + 800001b4: 00c11113 slli sp,sp,0xc + 800001b8: a0110113 addi sp,sp,-1535 + 800001bc: 00c11113 slli sp,sp,0xc + 800001c0: aa010113 addi sp,sp,-1376 + 800001c4: 0020b823 sd sp,16(ra) + 800001c8: 0100bf03 ld t5,16(ra) + 800001cc: 00550eb7 lui t4,0x550 + 800001d0: 055e8e9b addiw t4,t4,85 + 800001d4: 00de9e93 slli t4,t4,0xd + 800001d8: 00be8e93 addi t4,t4,11 # 55000b <_start-0x7faafff5> + 800001dc: 00ce9e93 slli t4,t4,0xc + 800001e0: a01e8e93 addi t4,t4,-1535 + 800001e4: 00ce9e93 slli t4,t4,0xc + 800001e8: aa0e8e93 addi t4,t4,-1376 + 800001ec: 00400193 li gp,4 + 800001f0: 55df1863 bne t5,t4,80000740 <fail> + +00000000800001f4 <test_5>: + 800001f4: 00002097 auipc ra,0x2 + 800001f8: e0c08093 addi ra,ra,-500 # 80002000 <begin_signature> + 800001fc: fffd0137 lui sp,0xfffd0 + 80000200: 0551011b addiw sp,sp,85 + 80000204: 01011113 slli sp,sp,0x10 + 80000208: 05510113 addi sp,sp,85 # fffffffffffd0055 <_end+0xffffffff7ffce005> + 8000020c: 01011113 slli sp,sp,0x10 + 80000210: 05510113 addi sp,sp,85 + 80000214: 00d11113 slli sp,sp,0xd + 80000218: 00a10113 addi sp,sp,10 + 8000021c: 0020bc23 sd sp,24(ra) + 80000220: 0180bf03 ld t5,24(ra) + 80000224: fffd0eb7 lui t4,0xfffd0 + 80000228: 055e8e9b addiw t4,t4,85 + 8000022c: 010e9e93 slli t4,t4,0x10 + 80000230: 055e8e93 addi t4,t4,85 # fffffffffffd0055 <_end+0xffffffff7ffce005> + 80000234: 010e9e93 slli t4,t4,0x10 + 80000238: 055e8e93 addi t4,t4,85 + 8000023c: 00de9e93 slli t4,t4,0xd + 80000240: 00ae8e93 addi t4,t4,10 + 80000244: 00500193 li gp,5 + 80000248: 4fdf1c63 bne t5,t4,80000740 <fail> + +000000008000024c <test_6>: + 8000024c: 00002097 auipc ra,0x2 + 80000250: dec08093 addi ra,ra,-532 # 80002038 <tdat8> + 80000254: 00550137 lui sp,0x550 + 80000258: 0551011b addiw sp,sp,85 + 8000025c: 01011113 slli sp,sp,0x10 + 80000260: 05510113 addi sp,sp,85 # 550055 <_start-0x7faaffab> + 80000264: 01111113 slli sp,sp,0x11 + 80000268: 0aa10113 addi sp,sp,170 + 8000026c: fe20b423 sd sp,-24(ra) + 80000270: fe80bf03 ld t5,-24(ra) + 80000274: 00550eb7 lui t4,0x550 + 80000278: 055e8e9b addiw t4,t4,85 + 8000027c: 010e9e93 slli t4,t4,0x10 + 80000280: 055e8e93 addi t4,t4,85 # 550055 <_start-0x7faaffab> + 80000284: 011e9e93 slli t4,t4,0x11 + 80000288: 0aae8e93 addi t4,t4,170 + 8000028c: 00600193 li gp,6 + 80000290: 4bdf1863 bne t5,t4,80000740 <fail> + +0000000080000294 <test_7>: + 80000294: 00002097 auipc ra,0x2 + 80000298: da408093 addi ra,ra,-604 # 80002038 <tdat8> + 8000029c: ffd50137 lui sp,0xffd50 + 800002a0: 0551011b addiw sp,sp,85 + 800002a4: 01011113 slli sp,sp,0x10 + 800002a8: 05510113 addi sp,sp,85 # ffffffffffd50055 <_end+0xffffffff7fd4e005> + 800002ac: 00d11113 slli sp,sp,0xd + 800002b0: 00b10113 addi sp,sp,11 + 800002b4: 00c11113 slli sp,sp,0xc + 800002b8: a0010113 addi sp,sp,-1536 + 800002bc: fe20b823 sd sp,-16(ra) + 800002c0: ff00bf03 ld t5,-16(ra) + 800002c4: ffd50eb7 lui t4,0xffd50 + 800002c8: 055e8e9b addiw t4,t4,85 + 800002cc: 010e9e93 slli t4,t4,0x10 + 800002d0: 055e8e93 addi t4,t4,85 # ffffffffffd50055 <_end+0xffffffff7fd4e005> + 800002d4: 00de9e93 slli t4,t4,0xd + 800002d8: 00be8e93 addi t4,t4,11 + 800002dc: 00ce9e93 slli t4,t4,0xc + 800002e0: a00e8e93 addi t4,t4,-1536 + 800002e4: 00700193 li gp,7 + 800002e8: 45df1c63 bne t5,t4,80000740 <fail> + +00000000800002ec <test_8>: + 800002ec: 00002097 auipc ra,0x2 + 800002f0: d4c08093 addi ra,ra,-692 # 80002038 <tdat8> + 800002f4: 00550137 lui sp,0x550 + 800002f8: 0551011b addiw sp,sp,85 + 800002fc: 00d11113 slli sp,sp,0xd + 80000300: 00b10113 addi sp,sp,11 # 55000b <_start-0x7faafff5> + 80000304: 00c11113 slli sp,sp,0xc + 80000308: a0110113 addi sp,sp,-1535 + 8000030c: 00c11113 slli sp,sp,0xc + 80000310: aa010113 addi sp,sp,-1376 + 80000314: fe20bc23 sd sp,-8(ra) + 80000318: ff80bf03 ld t5,-8(ra) + 8000031c: 00550eb7 lui t4,0x550 + 80000320: 055e8e9b addiw t4,t4,85 + 80000324: 00de9e93 slli t4,t4,0xd + 80000328: 00be8e93 addi t4,t4,11 # 55000b <_start-0x7faafff5> + 8000032c: 00ce9e93 slli t4,t4,0xc + 80000330: a01e8e93 addi t4,t4,-1535 + 80000334: 00ce9e93 slli t4,t4,0xc + 80000338: aa0e8e93 addi t4,t4,-1376 + 8000033c: 00800193 li gp,8 + 80000340: 41df1063 bne t5,t4,80000740 <fail> + +0000000080000344 <test_9>: + 80000344: 00002097 auipc ra,0x2 + 80000348: cf408093 addi ra,ra,-780 # 80002038 <tdat8> + 8000034c: fffd0137 lui sp,0xfffd0 + 80000350: 0551011b addiw sp,sp,85 + 80000354: 01011113 slli sp,sp,0x10 + 80000358: 05510113 addi sp,sp,85 # fffffffffffd0055 <_end+0xffffffff7ffce005> + 8000035c: 01011113 slli sp,sp,0x10 + 80000360: 05510113 addi sp,sp,85 + 80000364: 00d11113 slli sp,sp,0xd + 80000368: 00a10113 addi sp,sp,10 + 8000036c: 0020b023 sd sp,0(ra) + 80000370: 0000bf03 ld t5,0(ra) + 80000374: fffd0eb7 lui t4,0xfffd0 + 80000378: 055e8e9b addiw t4,t4,85 + 8000037c: 010e9e93 slli t4,t4,0x10 + 80000380: 055e8e93 addi t4,t4,85 # fffffffffffd0055 <_end+0xffffffff7ffce005> + 80000384: 010e9e93 slli t4,t4,0x10 + 80000388: 055e8e93 addi t4,t4,85 + 8000038c: 00de9e93 slli t4,t4,0xd + 80000390: 00ae8e93 addi t4,t4,10 + 80000394: 00900193 li gp,9 + 80000398: 3bdf1463 bne t5,t4,80000740 <fail> + +000000008000039c <test_10>: + 8000039c: 00002097 auipc ra,0x2 + 800003a0: ca408093 addi ra,ra,-860 # 80002040 <tdat9> + 800003a4: 00247137 lui sp,0x247 + 800003a8: 8ad1011b addiw sp,sp,-1875 + 800003ac: 00e11113 slli sp,sp,0xe + 800003b0: c0910113 addi sp,sp,-1015 # 246c09 <_start-0x7fdb93f7> + 800003b4: 00d11113 slli sp,sp,0xd + 800003b8: 34510113 addi sp,sp,837 + 800003bc: 00c11113 slli sp,sp,0xc + 800003c0: 67810113 addi sp,sp,1656 + 800003c4: fe008213 addi tp,ra,-32 + 800003c8: 02223023 sd sp,32(tp) # 20 <_start-0x7fffffe0> + 800003cc: 0000b283 ld t0,0(ra) + 800003d0: 00247eb7 lui t4,0x247 + 800003d4: 8ade8e9b addiw t4,t4,-1875 + 800003d8: 00ee9e93 slli t4,t4,0xe + 800003dc: c09e8e93 addi t4,t4,-1015 # 246c09 <_start-0x7fdb93f7> + 800003e0: 00de9e93 slli t4,t4,0xd + 800003e4: 345e8e93 addi t4,t4,837 + 800003e8: 00ce9e93 slli t4,t4,0xc + 800003ec: 678e8e93 addi t4,t4,1656 + 800003f0: 00a00193 li gp,10 + 800003f4: 35d29663 bne t0,t4,80000740 <fail> + +00000000800003f8 <test_11>: + 800003f8: 00002097 auipc ra,0x2 + 800003fc: c4808093 addi ra,ra,-952 # 80002040 <tdat9> + 80000400: 00b04137 lui sp,0xb04 + 80000404: 2611011b addiw sp,sp,609 + 80000408: 00c11113 slli sp,sp,0xc + 8000040c: 30b10113 addi sp,sp,779 # b0430b <_start-0x7f4fbcf5> + 80000410: 00f11113 slli sp,sp,0xf + 80000414: 21310113 addi sp,sp,531 + 80000418: 00c11113 slli sp,sp,0xc + 8000041c: 09810113 addi sp,sp,152 + 80000420: ffd08093 addi ra,ra,-3 + 80000424: 0020b5a3 sd sp,11(ra) + 80000428: 00002217 auipc tp,0x2 + 8000042c: c2020213 addi tp,tp,-992 # 80002048 <tdat10> + 80000430: 00023283 ld t0,0(tp) # 0 <_start-0x80000000> + 80000434: 00b04eb7 lui t4,0xb04 + 80000438: 261e8e9b addiw t4,t4,609 + 8000043c: 00ce9e93 slli t4,t4,0xc + 80000440: 30be8e93 addi t4,t4,779 # b0430b <_start-0x7f4fbcf5> + 80000444: 00fe9e93 slli t4,t4,0xf + 80000448: 213e8e93 addi t4,t4,531 + 8000044c: 00ce9e93 slli t4,t4,0xc + 80000450: 098e8e93 addi t4,t4,152 + 80000454: 00b00193 li gp,11 + 80000458: 2fd29463 bne t0,t4,80000740 <fail> + +000000008000045c <test_12>: + 8000045c: 00c00193 li gp,12 + 80000460: 00000213 li tp,0 + 80000464: 0abbd0b7 lui ra,0xabbd + 80000468: cdd0809b addiw ra,ra,-803 + 8000046c: 00002117 auipc sp,0x2 + 80000470: b9410113 addi sp,sp,-1132 # 80002000 <begin_signature> + 80000474: 00113023 sd ra,0(sp) + 80000478: 00013f03 ld t5,0(sp) + 8000047c: 0abbdeb7 lui t4,0xabbd + 80000480: cdde8e9b addiw t4,t4,-803 + 80000484: 2bdf1e63 bne t5,t4,80000740 <fail> + 80000488: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000048c: 00200293 li t0,2 + 80000490: fc521ae3 bne tp,t0,80000464 <test_12+0x8> + +0000000080000494 <test_13>: + 80000494: 00d00193 li gp,13 + 80000498: 00000213 li tp,0 + 8000049c: 0aabc0b7 lui ra,0xaabc + 800004a0: ccd0809b addiw ra,ra,-819 + 800004a4: 00002117 auipc sp,0x2 + 800004a8: b5c10113 addi sp,sp,-1188 # 80002000 <begin_signature> + 800004ac: 00000013 nop + 800004b0: 00113423 sd ra,8(sp) + 800004b4: 00813f03 ld t5,8(sp) + 800004b8: 0aabceb7 lui t4,0xaabc + 800004bc: ccde8e9b addiw t4,t4,-819 + 800004c0: 29df1063 bne t5,t4,80000740 <fail> + 800004c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004c8: 00200293 li t0,2 + 800004cc: fc5218e3 bne tp,t0,8000049c <test_13+0x8> + +00000000800004d0 <test_14>: + 800004d0: 00e00193 li gp,14 + 800004d4: 00000213 li tp,0 + 800004d8: 0daac0b7 lui ra,0xdaac + 800004dc: bcc0809b addiw ra,ra,-1076 + 800004e0: 00002117 auipc sp,0x2 + 800004e4: b2010113 addi sp,sp,-1248 # 80002000 <begin_signature> + 800004e8: 00000013 nop + 800004ec: 00000013 nop + 800004f0: 00113823 sd ra,16(sp) + 800004f4: 01013f03 ld t5,16(sp) + 800004f8: 0daaceb7 lui t4,0xdaac + 800004fc: bcce8e9b addiw t4,t4,-1076 + 80000500: 25df1063 bne t5,t4,80000740 <fail> + 80000504: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000508: 00200293 li t0,2 + 8000050c: fc5216e3 bne tp,t0,800004d8 <test_14+0x8> + +0000000080000510 <test_15>: + 80000510: 00f00193 li gp,15 + 80000514: 00000213 li tp,0 + 80000518: 0ddab0b7 lui ra,0xddab + 8000051c: bbc0809b addiw ra,ra,-1092 + 80000520: 00000013 nop + 80000524: 00002117 auipc sp,0x2 + 80000528: adc10113 addi sp,sp,-1316 # 80002000 <begin_signature> + 8000052c: 00113c23 sd ra,24(sp) + 80000530: 01813f03 ld t5,24(sp) + 80000534: 0ddabeb7 lui t4,0xddab + 80000538: bbce8e9b addiw t4,t4,-1092 + 8000053c: 21df1263 bne t5,t4,80000740 <fail> + 80000540: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000544: 00200293 li t0,2 + 80000548: fc5218e3 bne tp,t0,80000518 <test_15+0x8> + +000000008000054c <test_16>: + 8000054c: 01000193 li gp,16 + 80000550: 00000213 li tp,0 + 80000554: 0cddb0b7 lui ra,0xcddb + 80000558: abb0809b addiw ra,ra,-1349 + 8000055c: 00000013 nop + 80000560: 00002117 auipc sp,0x2 + 80000564: aa010113 addi sp,sp,-1376 # 80002000 <begin_signature> + 80000568: 00000013 nop + 8000056c: 02113023 sd ra,32(sp) + 80000570: 02013f03 ld t5,32(sp) + 80000574: 0cddbeb7 lui t4,0xcddb + 80000578: abbe8e9b addiw t4,t4,-1349 + 8000057c: 1ddf1263 bne t5,t4,80000740 <fail> + 80000580: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000584: 00200293 li t0,2 + 80000588: fc5216e3 bne tp,t0,80000554 <test_16+0x8> + +000000008000058c <test_17>: + 8000058c: 01100193 li gp,17 + 80000590: 00000213 li tp,0 + 80000594: 0ccde0b7 lui ra,0xccde + 80000598: aab0809b addiw ra,ra,-1365 + 8000059c: 00000013 nop + 800005a0: 00000013 nop + 800005a4: 00002117 auipc sp,0x2 + 800005a8: a5c10113 addi sp,sp,-1444 # 80002000 <begin_signature> + 800005ac: 02113423 sd ra,40(sp) + 800005b0: 02813f03 ld t5,40(sp) + 800005b4: 0ccdeeb7 lui t4,0xccde + 800005b8: aabe8e9b addiw t4,t4,-1365 + 800005bc: 19df1263 bne t5,t4,80000740 <fail> + 800005c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005c4: 00200293 li t0,2 + 800005c8: fc5216e3 bne tp,t0,80000594 <test_17+0x8> + +00000000800005cc <test_18>: + 800005cc: 01200193 li gp,18 + 800005d0: 00000213 li tp,0 + 800005d4: 00002117 auipc sp,0x2 + 800005d8: a2c10113 addi sp,sp,-1492 # 80002000 <begin_signature> + 800005dc: 001120b7 lui ra,0x112 + 800005e0: 2330809b addiw ra,ra,563 + 800005e4: 00113023 sd ra,0(sp) + 800005e8: 00013f03 ld t5,0(sp) + 800005ec: 00112eb7 lui t4,0x112 + 800005f0: 233e8e9b addiw t4,t4,563 + 800005f4: 15df1663 bne t5,t4,80000740 <fail> + 800005f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005fc: 00200293 li t0,2 + 80000600: fc521ae3 bne tp,t0,800005d4 <test_18+0x8> + +0000000080000604 <test_19>: + 80000604: 01300193 li gp,19 + 80000608: 00000213 li tp,0 + 8000060c: 00002117 auipc sp,0x2 + 80000610: 9f410113 addi sp,sp,-1548 # 80002000 <begin_signature> + 80000614: 300110b7 lui ra,0x30011 + 80000618: 2230809b addiw ra,ra,547 + 8000061c: 00000013 nop + 80000620: 00113423 sd ra,8(sp) + 80000624: 00813f03 ld t5,8(sp) + 80000628: 30011eb7 lui t4,0x30011 + 8000062c: 223e8e9b addiw t4,t4,547 + 80000630: 11df1863 bne t5,t4,80000740 <fail> + 80000634: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000638: 00200293 li t0,2 + 8000063c: fc5218e3 bne tp,t0,8000060c <test_19+0x8> + +0000000080000640 <test_20>: + 80000640: 01400193 li gp,20 + 80000644: 00000213 li tp,0 + 80000648: 00002117 auipc sp,0x2 + 8000064c: 9b810113 addi sp,sp,-1608 # 80002000 <begin_signature> + 80000650: 330010b7 lui ra,0x33001 + 80000654: 1220809b addiw ra,ra,290 + 80000658: 00000013 nop + 8000065c: 00000013 nop + 80000660: 00113823 sd ra,16(sp) + 80000664: 01013f03 ld t5,16(sp) + 80000668: 33001eb7 lui t4,0x33001 + 8000066c: 122e8e9b addiw t4,t4,290 + 80000670: 0ddf1863 bne t5,t4,80000740 <fail> + 80000674: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000678: 00200293 li t0,2 + 8000067c: fc5216e3 bne tp,t0,80000648 <test_20+0x8> + +0000000080000680 <test_21>: + 80000680: 01500193 li gp,21 + 80000684: 00000213 li tp,0 + 80000688: 00002117 auipc sp,0x2 + 8000068c: 97810113 addi sp,sp,-1672 # 80002000 <begin_signature> + 80000690: 00000013 nop + 80000694: 233000b7 lui ra,0x23300 + 80000698: 1120809b addiw ra,ra,274 + 8000069c: 00113c23 sd ra,24(sp) + 800006a0: 01813f03 ld t5,24(sp) + 800006a4: 23300eb7 lui t4,0x23300 + 800006a8: 112e8e9b addiw t4,t4,274 + 800006ac: 09df1a63 bne t5,t4,80000740 <fail> + 800006b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800006b4: 00200293 li t0,2 + 800006b8: fc5218e3 bne tp,t0,80000688 <test_21+0x8> + +00000000800006bc <test_22>: + 800006bc: 01600193 li gp,22 + 800006c0: 00000213 li tp,0 + 800006c4: 00002117 auipc sp,0x2 + 800006c8: 93c10113 addi sp,sp,-1732 # 80002000 <begin_signature> + 800006cc: 00000013 nop + 800006d0: 223300b7 lui ra,0x22330 + 800006d4: 0110809b addiw ra,ra,17 + 800006d8: 00000013 nop + 800006dc: 02113023 sd ra,32(sp) + 800006e0: 02013f03 ld t5,32(sp) + 800006e4: 22330eb7 lui t4,0x22330 + 800006e8: 011e8e9b addiw t4,t4,17 + 800006ec: 05df1a63 bne t5,t4,80000740 <fail> + 800006f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800006f4: 00200293 li t0,2 + 800006f8: fc5216e3 bne tp,t0,800006c4 <test_22+0x8> + +00000000800006fc <test_23>: + 800006fc: 01700193 li gp,23 + 80000700: 00000213 li tp,0 + 80000704: 00002117 auipc sp,0x2 + 80000708: 8fc10113 addi sp,sp,-1796 # 80002000 <begin_signature> + 8000070c: 00000013 nop + 80000710: 00000013 nop + 80000714: 122330b7 lui ra,0x12233 + 80000718: 0010809b addiw ra,ra,1 + 8000071c: 02113423 sd ra,40(sp) + 80000720: 02813f03 ld t5,40(sp) + 80000724: 12233eb7 lui t4,0x12233 + 80000728: 001e8e9b addiw t4,t4,1 + 8000072c: 01df1a63 bne t5,t4,80000740 <fail> + 80000730: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000734: 00200293 li t0,2 + 80000738: fc5216e3 bne tp,t0,80000704 <test_23+0x8> + 8000073c: 00301c63 bne zero,gp,80000754 <pass> + +0000000080000740 <fail>: + 80000740: 0ff0000f fence + 80000744: 00018063 beqz gp,80000744 <fail+0x4> + 80000748: 00119193 slli gp,gp,0x1 + 8000074c: 0011e193 ori gp,gp,1 + 80000750: 00000073 ecall + +0000000080000754 <pass>: + 80000754: 0ff0000f fence + 80000758: 00100193 li gp,1 + 8000075c: 00000073 ecall + 80000760: c0001073 unimp + 80000764: 0000 unimp + 80000766: 0000 unimp + 80000768: 0000 unimp + 8000076a: 0000 unimp + 8000076c: 0000 unimp + 8000076e: 0000 unimp + 80000770: 0000 unimp + 80000772: 0000 unimp + 80000774: 0000 unimp + 80000776: 0000 unimp + 80000778: 0000 unimp + 8000077a: 0000 unimp + 8000077c: 0000 unimp + 8000077e: 0000 unimp + 80000780: 0000 unimp + 80000782: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: deadbeef jal t4,7ffdd5ea <_start-0x22a16> + 80002004: deadbeef jal t4,7ffdd5ee <_start-0x22a12> + +0000000080002008 <tdat2>: + 80002008: deadbeef jal t4,7ffdd5f2 <_start-0x22a0e> + 8000200c: deadbeef jal t4,7ffdd5f6 <_start-0x22a0a> + +0000000080002010 <tdat3>: + 80002010: deadbeef jal t4,7ffdd5fa <_start-0x22a06> + 80002014: deadbeef jal t4,7ffdd5fe <_start-0x22a02> + +0000000080002018 <tdat4>: + 80002018: deadbeef jal t4,7ffdd602 <_start-0x229fe> + 8000201c: deadbeef jal t4,7ffdd606 <_start-0x229fa> + +0000000080002020 <tdat5>: + 80002020: deadbeef jal t4,7ffdd60a <_start-0x229f6> + 80002024: deadbeef jal t4,7ffdd60e <_start-0x229f2> + +0000000080002028 <tdat6>: + 80002028: deadbeef jal t4,7ffdd612 <_start-0x229ee> + 8000202c: deadbeef jal t4,7ffdd616 <_start-0x229ea> + +0000000080002030 <tdat7>: + 80002030: deadbeef jal t4,7ffdd61a <_start-0x229e6> + 80002034: deadbeef jal t4,7ffdd61e <_start-0x229e2> + +0000000080002038 <tdat8>: + 80002038: deadbeef jal t4,7ffdd622 <_start-0x229de> + 8000203c: deadbeef jal t4,7ffdd626 <_start-0x229da> + +0000000080002040 <tdat9>: + 80002040: deadbeef jal t4,7ffdd62a <_start-0x229d6> + 80002044: deadbeef jal t4,7ffdd62e <_start-0x229d2> + +0000000080002048 <tdat10>: + 80002048: deadbeef jal t4,7ffdd632 <_start-0x229ce> + 8000204c: deadbeef jal t4,7ffdd636 <_start-0x229ca> diff --git a/test/riscv/tests/rv64ui-p-sd.elf b/test/riscv/tests/rv64ui-p-sd.elf Binary files differnew file mode 100755 index 00000000..f6801dcf --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sd.elf diff --git a/test/riscv/tests/rv64ui-p-sh.dump b/test/riscv/tests/rv64ui-p-sh.dump new file mode 100644 index 00000000..dc11b449 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sh.dump @@ -0,0 +1,480 @@ + +rv64ui-p-sh: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00002097 auipc ra,0x2 + 80000100: f0408093 addi ra,ra,-252 # 80002000 <begin_signature> + 80000104: 0aa00113 li sp,170 + 80000108: 00209023 sh sp,0(ra) + 8000010c: 00009f03 lh t5,0(ra) + 80000110: 0aa00e93 li t4,170 + 80000114: 00200193 li gp,2 + 80000118: 45df1e63 bne t5,t4,80000574 <fail> + +000000008000011c <test_3>: + 8000011c: 00002097 auipc ra,0x2 + 80000120: ee408093 addi ra,ra,-284 # 80002000 <begin_signature> + 80000124: ffffb137 lui sp,0xffffb + 80000128: a001011b addiw sp,sp,-1536 + 8000012c: 00209123 sh sp,2(ra) + 80000130: 00209f03 lh t5,2(ra) + 80000134: ffffbeb7 lui t4,0xffffb + 80000138: a00e8e9b addiw t4,t4,-1536 + 8000013c: 00300193 li gp,3 + 80000140: 43df1a63 bne t5,t4,80000574 <fail> + +0000000080000144 <test_4>: + 80000144: 00002097 auipc ra,0x2 + 80000148: ebc08093 addi ra,ra,-324 # 80002000 <begin_signature> + 8000014c: beef1137 lui sp,0xbeef1 + 80000150: aa01011b addiw sp,sp,-1376 + 80000154: 00209223 sh sp,4(ra) + 80000158: 0040af03 lw t5,4(ra) + 8000015c: beef1eb7 lui t4,0xbeef1 + 80000160: aa0e8e9b addiw t4,t4,-1376 + 80000164: 00400193 li gp,4 + 80000168: 41df1663 bne t5,t4,80000574 <fail> + +000000008000016c <test_5>: + 8000016c: 00002097 auipc ra,0x2 + 80000170: e9408093 addi ra,ra,-364 # 80002000 <begin_signature> + 80000174: ffffa137 lui sp,0xffffa + 80000178: 00a1011b addiw sp,sp,10 + 8000017c: 00209323 sh sp,6(ra) + 80000180: 00609f03 lh t5,6(ra) + 80000184: ffffaeb7 lui t4,0xffffa + 80000188: 00ae8e9b addiw t4,t4,10 + 8000018c: 00500193 li gp,5 + 80000190: 3fdf1263 bne t5,t4,80000574 <fail> + +0000000080000194 <test_6>: + 80000194: 00002097 auipc ra,0x2 + 80000198: e7a08093 addi ra,ra,-390 # 8000200e <tdat8> + 8000019c: 0aa00113 li sp,170 + 800001a0: fe209d23 sh sp,-6(ra) + 800001a4: ffa09f03 lh t5,-6(ra) + 800001a8: 0aa00e93 li t4,170 + 800001ac: 00600193 li gp,6 + 800001b0: 3ddf1263 bne t5,t4,80000574 <fail> + +00000000800001b4 <test_7>: + 800001b4: 00002097 auipc ra,0x2 + 800001b8: e5a08093 addi ra,ra,-422 # 8000200e <tdat8> + 800001bc: ffffb137 lui sp,0xffffb + 800001c0: a001011b addiw sp,sp,-1536 + 800001c4: fe209e23 sh sp,-4(ra) + 800001c8: ffc09f03 lh t5,-4(ra) + 800001cc: ffffbeb7 lui t4,0xffffb + 800001d0: a00e8e9b addiw t4,t4,-1536 + 800001d4: 00700193 li gp,7 + 800001d8: 39df1e63 bne t5,t4,80000574 <fail> + +00000000800001dc <test_8>: + 800001dc: 00002097 auipc ra,0x2 + 800001e0: e3208093 addi ra,ra,-462 # 8000200e <tdat8> + 800001e4: 00001137 lui sp,0x1 + 800001e8: aa01011b addiw sp,sp,-1376 + 800001ec: fe209f23 sh sp,-2(ra) + 800001f0: ffe09f03 lh t5,-2(ra) + 800001f4: 00001eb7 lui t4,0x1 + 800001f8: aa0e8e9b addiw t4,t4,-1376 + 800001fc: 00800193 li gp,8 + 80000200: 37df1a63 bne t5,t4,80000574 <fail> + +0000000080000204 <test_9>: + 80000204: 00002097 auipc ra,0x2 + 80000208: e0a08093 addi ra,ra,-502 # 8000200e <tdat8> + 8000020c: ffffa137 lui sp,0xffffa + 80000210: 00a1011b addiw sp,sp,10 + 80000214: 00209023 sh sp,0(ra) + 80000218: 00009f03 lh t5,0(ra) + 8000021c: ffffaeb7 lui t4,0xffffa + 80000220: 00ae8e9b addiw t4,t4,10 + 80000224: 00900193 li gp,9 + 80000228: 35df1663 bne t5,t4,80000574 <fail> + +000000008000022c <test_10>: + 8000022c: 00002097 auipc ra,0x2 + 80000230: de408093 addi ra,ra,-540 # 80002010 <tdat9> + 80000234: 12345137 lui sp,0x12345 + 80000238: 6781011b addiw sp,sp,1656 + 8000023c: fe008213 addi tp,ra,-32 + 80000240: 02221023 sh sp,32(tp) # 20 <_start-0x7fffffe0> + 80000244: 00009283 lh t0,0(ra) + 80000248: 00005eb7 lui t4,0x5 + 8000024c: 678e8e9b addiw t4,t4,1656 + 80000250: 00a00193 li gp,10 + 80000254: 33d29063 bne t0,t4,80000574 <fail> + +0000000080000258 <test_11>: + 80000258: 00002097 auipc ra,0x2 + 8000025c: db808093 addi ra,ra,-584 # 80002010 <tdat9> + 80000260: 00003137 lui sp,0x3 + 80000264: 0981011b addiw sp,sp,152 + 80000268: ffb08093 addi ra,ra,-5 + 8000026c: 002093a3 sh sp,7(ra) + 80000270: 00002217 auipc tp,0x2 + 80000274: da220213 addi tp,tp,-606 # 80002012 <tdat10> + 80000278: 00021283 lh t0,0(tp) # 0 <_start-0x80000000> + 8000027c: 00003eb7 lui t4,0x3 + 80000280: 098e8e9b addiw t4,t4,152 + 80000284: 00b00193 li gp,11 + 80000288: 2fd29663 bne t0,t4,80000574 <fail> + +000000008000028c <test_12>: + 8000028c: 00c00193 li gp,12 + 80000290: 00000213 li tp,0 + 80000294: ffffd0b7 lui ra,0xffffd + 80000298: cdd0809b addiw ra,ra,-803 + 8000029c: 00002117 auipc sp,0x2 + 800002a0: d6410113 addi sp,sp,-668 # 80002000 <begin_signature> + 800002a4: 00111023 sh ra,0(sp) + 800002a8: 00011f03 lh t5,0(sp) + 800002ac: ffffdeb7 lui t4,0xffffd + 800002b0: cdde8e9b addiw t4,t4,-803 + 800002b4: 2ddf1063 bne t5,t4,80000574 <fail> + 800002b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002bc: 00200293 li t0,2 + 800002c0: fc521ae3 bne tp,t0,80000294 <test_12+0x8> + +00000000800002c4 <test_13>: + 800002c4: 00d00193 li gp,13 + 800002c8: 00000213 li tp,0 + 800002cc: ffffc0b7 lui ra,0xffffc + 800002d0: ccd0809b addiw ra,ra,-819 + 800002d4: 00002117 auipc sp,0x2 + 800002d8: d2c10113 addi sp,sp,-724 # 80002000 <begin_signature> + 800002dc: 00000013 nop + 800002e0: 00111123 sh ra,2(sp) + 800002e4: 00211f03 lh t5,2(sp) + 800002e8: ffffceb7 lui t4,0xffffc + 800002ec: ccde8e9b addiw t4,t4,-819 + 800002f0: 29df1263 bne t5,t4,80000574 <fail> + 800002f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002f8: 00200293 li t0,2 + 800002fc: fc5218e3 bne tp,t0,800002cc <test_13+0x8> + +0000000080000300 <test_14>: + 80000300: 00e00193 li gp,14 + 80000304: 00000213 li tp,0 + 80000308: ffffc0b7 lui ra,0xffffc + 8000030c: bcc0809b addiw ra,ra,-1076 + 80000310: 00002117 auipc sp,0x2 + 80000314: cf010113 addi sp,sp,-784 # 80002000 <begin_signature> + 80000318: 00000013 nop + 8000031c: 00000013 nop + 80000320: 00111223 sh ra,4(sp) + 80000324: 00411f03 lh t5,4(sp) + 80000328: ffffceb7 lui t4,0xffffc + 8000032c: bcce8e9b addiw t4,t4,-1076 + 80000330: 25df1263 bne t5,t4,80000574 <fail> + 80000334: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000338: 00200293 li t0,2 + 8000033c: fc5216e3 bne tp,t0,80000308 <test_14+0x8> + +0000000080000340 <test_15>: + 80000340: 00f00193 li gp,15 + 80000344: 00000213 li tp,0 + 80000348: ffffb0b7 lui ra,0xffffb + 8000034c: bbc0809b addiw ra,ra,-1092 + 80000350: 00000013 nop + 80000354: 00002117 auipc sp,0x2 + 80000358: cac10113 addi sp,sp,-852 # 80002000 <begin_signature> + 8000035c: 00111323 sh ra,6(sp) + 80000360: 00611f03 lh t5,6(sp) + 80000364: ffffbeb7 lui t4,0xffffb + 80000368: bbce8e9b addiw t4,t4,-1092 + 8000036c: 21df1463 bne t5,t4,80000574 <fail> + 80000370: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000374: 00200293 li t0,2 + 80000378: fc5218e3 bne tp,t0,80000348 <test_15+0x8> + +000000008000037c <test_16>: + 8000037c: 01000193 li gp,16 + 80000380: 00000213 li tp,0 + 80000384: ffffb0b7 lui ra,0xffffb + 80000388: abb0809b addiw ra,ra,-1349 + 8000038c: 00000013 nop + 80000390: 00002117 auipc sp,0x2 + 80000394: c7010113 addi sp,sp,-912 # 80002000 <begin_signature> + 80000398: 00000013 nop + 8000039c: 00111423 sh ra,8(sp) + 800003a0: 00811f03 lh t5,8(sp) + 800003a4: ffffbeb7 lui t4,0xffffb + 800003a8: abbe8e9b addiw t4,t4,-1349 + 800003ac: 1ddf1463 bne t5,t4,80000574 <fail> + 800003b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003b4: 00200293 li t0,2 + 800003b8: fc5216e3 bne tp,t0,80000384 <test_16+0x8> + +00000000800003bc <test_17>: + 800003bc: 01100193 li gp,17 + 800003c0: 00000213 li tp,0 + 800003c4: ffffe0b7 lui ra,0xffffe + 800003c8: aab0809b addiw ra,ra,-1365 + 800003cc: 00000013 nop + 800003d0: 00000013 nop + 800003d4: 00002117 auipc sp,0x2 + 800003d8: c2c10113 addi sp,sp,-980 # 80002000 <begin_signature> + 800003dc: 00111523 sh ra,10(sp) + 800003e0: 00a11f03 lh t5,10(sp) + 800003e4: ffffeeb7 lui t4,0xffffe + 800003e8: aabe8e9b addiw t4,t4,-1365 + 800003ec: 19df1463 bne t5,t4,80000574 <fail> + 800003f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003f4: 00200293 li t0,2 + 800003f8: fc5216e3 bne tp,t0,800003c4 <test_17+0x8> + +00000000800003fc <test_18>: + 800003fc: 01200193 li gp,18 + 80000400: 00000213 li tp,0 + 80000404: 00002117 auipc sp,0x2 + 80000408: bfc10113 addi sp,sp,-1028 # 80002000 <begin_signature> + 8000040c: 000020b7 lui ra,0x2 + 80000410: 2330809b addiw ra,ra,563 + 80000414: 00111023 sh ra,0(sp) + 80000418: 00011f03 lh t5,0(sp) + 8000041c: 00002eb7 lui t4,0x2 + 80000420: 233e8e9b addiw t4,t4,563 + 80000424: 15df1863 bne t5,t4,80000574 <fail> + 80000428: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000042c: 00200293 li t0,2 + 80000430: fc521ae3 bne tp,t0,80000404 <test_18+0x8> + +0000000080000434 <test_19>: + 80000434: 01300193 li gp,19 + 80000438: 00000213 li tp,0 + 8000043c: 00002117 auipc sp,0x2 + 80000440: bc410113 addi sp,sp,-1084 # 80002000 <begin_signature> + 80000444: 000010b7 lui ra,0x1 + 80000448: 2230809b addiw ra,ra,547 + 8000044c: 00000013 nop + 80000450: 00111123 sh ra,2(sp) + 80000454: 00211f03 lh t5,2(sp) + 80000458: 00001eb7 lui t4,0x1 + 8000045c: 223e8e9b addiw t4,t4,547 + 80000460: 11df1a63 bne t5,t4,80000574 <fail> + 80000464: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000468: 00200293 li t0,2 + 8000046c: fc5218e3 bne tp,t0,8000043c <test_19+0x8> + +0000000080000470 <test_20>: + 80000470: 01400193 li gp,20 + 80000474: 00000213 li tp,0 + 80000478: 00002117 auipc sp,0x2 + 8000047c: b8810113 addi sp,sp,-1144 # 80002000 <begin_signature> + 80000480: 000010b7 lui ra,0x1 + 80000484: 1220809b addiw ra,ra,290 + 80000488: 00000013 nop + 8000048c: 00000013 nop + 80000490: 00111223 sh ra,4(sp) + 80000494: 00411f03 lh t5,4(sp) + 80000498: 00001eb7 lui t4,0x1 + 8000049c: 122e8e9b addiw t4,t4,290 + 800004a0: 0ddf1a63 bne t5,t4,80000574 <fail> + 800004a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004a8: 00200293 li t0,2 + 800004ac: fc5216e3 bne tp,t0,80000478 <test_20+0x8> + +00000000800004b0 <test_21>: + 800004b0: 01500193 li gp,21 + 800004b4: 00000213 li tp,0 + 800004b8: 00002117 auipc sp,0x2 + 800004bc: b4810113 addi sp,sp,-1208 # 80002000 <begin_signature> + 800004c0: 00000013 nop + 800004c4: 11200093 li ra,274 + 800004c8: 00111323 sh ra,6(sp) + 800004cc: 00611f03 lh t5,6(sp) + 800004d0: 11200e93 li t4,274 + 800004d4: 0bdf1063 bne t5,t4,80000574 <fail> + 800004d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004dc: 00200293 li t0,2 + 800004e0: fc521ce3 bne tp,t0,800004b8 <test_21+0x8> + +00000000800004e4 <test_22>: + 800004e4: 01600193 li gp,22 + 800004e8: 00000213 li tp,0 + 800004ec: 00002117 auipc sp,0x2 + 800004f0: b1410113 addi sp,sp,-1260 # 80002000 <begin_signature> + 800004f4: 00000013 nop + 800004f8: 01100093 li ra,17 + 800004fc: 00000013 nop + 80000500: 00111423 sh ra,8(sp) + 80000504: 00811f03 lh t5,8(sp) + 80000508: 01100e93 li t4,17 + 8000050c: 07df1463 bne t5,t4,80000574 <fail> + 80000510: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000514: 00200293 li t0,2 + 80000518: fc521ae3 bne tp,t0,800004ec <test_22+0x8> + +000000008000051c <test_23>: + 8000051c: 01700193 li gp,23 + 80000520: 00000213 li tp,0 + 80000524: 00002117 auipc sp,0x2 + 80000528: adc10113 addi sp,sp,-1316 # 80002000 <begin_signature> + 8000052c: 00000013 nop + 80000530: 00000013 nop + 80000534: 000030b7 lui ra,0x3 + 80000538: 0010809b addiw ra,ra,1 + 8000053c: 00111523 sh ra,10(sp) + 80000540: 00a11f03 lh t5,10(sp) + 80000544: 00003eb7 lui t4,0x3 + 80000548: 001e8e9b addiw t4,t4,1 + 8000054c: 03df1463 bne t5,t4,80000574 <fail> + 80000550: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000554: 00200293 li t0,2 + 80000558: fc5216e3 bne tp,t0,80000524 <test_23+0x8> + 8000055c: 0000c537 lui a0,0xc + 80000560: eef5051b addiw a0,a0,-273 + 80000564: 00002597 auipc a1,0x2 + 80000568: a9c58593 addi a1,a1,-1380 # 80002000 <begin_signature> + 8000056c: 00a59323 sh a0,6(a1) + 80000570: 00301c63 bne zero,gp,80000588 <pass> + +0000000080000574 <fail>: + 80000574: 0ff0000f fence + 80000578: 00018063 beqz gp,80000578 <fail+0x4> + 8000057c: 00119193 slli gp,gp,0x1 + 80000580: 0011e193 ori gp,gp,1 + 80000584: 00000073 ecall + +0000000080000588 <pass>: + 80000588: 0ff0000f fence + 8000058c: 00100193 li gp,1 + 80000590: 00000073 ecall + 80000594: c0001073 unimp + 80000598: 0000 unimp + 8000059a: 0000 unimp + 8000059c: 0000 unimp + 8000059e: 0000 unimp + 800005a0: 0000 unimp + 800005a2: 0000 unimp + 800005a4: 0000 unimp + 800005a6: 0000 unimp + 800005a8: 0000 unimp + 800005aa: 0000 unimp + 800005ac: 0000 unimp + 800005ae: 0000 unimp + 800005b0: 0000 unimp + 800005b2: 0000 unimp + 800005b4: 0000 unimp + 800005b6: 0000 unimp + 800005b8: 0000 unimp + 800005ba: 0000 unimp + 800005bc: 0000 unimp + 800005be: 0000 unimp + 800005c0: 0000 unimp + 800005c2: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: jal t4,7fffd3ee <_start-0x2c12> + +0000000080002002 <tdat2>: + 80002002: jal t4,7fffd3f0 <_start-0x2c10> + +0000000080002004 <tdat3>: + 80002004: jal t4,7fffd3f2 <_start-0x2c0e> + +0000000080002006 <tdat4>: + 80002006: jal t4,7fffd3f4 <_start-0x2c0c> + +0000000080002008 <tdat5>: + 80002008: jal t4,7fffd3f6 <_start-0x2c0a> + +000000008000200a <tdat6>: + 8000200a: jal t4,7fffd3f8 <_start-0x2c08> + +000000008000200c <tdat7>: + 8000200c: jal t4,7fffd3fa <_start-0x2c06> + +000000008000200e <tdat8>: + 8000200e: jal t4,7fffd3fc <_start-0x2c04> + +0000000080002010 <tdat9>: + 80002010: jal t4,7fffd3fe <_start-0x2c02> + +0000000080002012 <tdat10>: + 80002012: 0000beef jal t4,8000d012 <_end+0xaff2> + 80002016: 0000 unimp + 80002018: 0000 unimp + 8000201a: 0000 unimp + 8000201c: 0000 unimp + 8000201e: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sh.elf b/test/riscv/tests/rv64ui-p-sh.elf Binary files differnew file mode 100755 index 00000000..118eeb3f --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sh.elf diff --git a/test/riscv/tests/rv64ui-p-simple.dump b/test/riscv/tests/rv64ui-p-simple.dump new file mode 100644 index 00000000..7a05fb7e --- /dev/null +++ b/test/riscv/tests/rv64ui-p-simple.dump @@ -0,0 +1,110 @@ + +rv64ui-p-simple: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <reset_vector+0xb0> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + 800000fc: 0ff0000f fence + 80000100: 00100193 li gp,1 + 80000104: 00000073 ecall + 80000108: c0001073 unimp + 8000010c: 0000 unimp + 8000010e: 0000 unimp + 80000110: 0000 unimp + 80000112: 0000 unimp + 80000114: 0000 unimp + 80000116: 0000 unimp + 80000118: 0000 unimp + 8000011a: 0000 unimp + 8000011c: 0000 unimp + 8000011e: 0000 unimp + 80000120: 0000 unimp + 80000122: 0000 unimp + 80000124: 0000 unimp + 80000126: 0000 unimp + 80000128: 0000 unimp + 8000012a: 0000 unimp + 8000012c: 0000 unimp + 8000012e: 0000 unimp + 80000130: 0000 unimp + 80000132: 0000 unimp + 80000134: 0000 unimp + 80000136: 0000 unimp + 80000138: 0000 unimp + 8000013a: 0000 unimp + 8000013c: 0000 unimp + 8000013e: 0000 unimp + 80000140: 0000 unimp + 80000142: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-simple.elf b/test/riscv/tests/rv64ui-p-simple.elf Binary files differnew file mode 100755 index 00000000..541353b3 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-simple.elf diff --git a/test/riscv/tests/rv64ui-p-sll.dump b/test/riscv/tests/rv64ui-p-sll.dump new file mode 100644 index 00000000..c2ac48ff --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sll.dump @@ -0,0 +1,580 @@ + +rv64ui-p-sll: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00100093 li ra,1 + 80000100: 00000113 li sp,0 + 80000104: 00209f33 sll t5,ra,sp + 80000108: 00100e93 li t4,1 + 8000010c: 00200193 li gp,2 + 80000110: 5fdf1c63 bne t5,t4,80000708 <fail> + +0000000080000114 <test_3>: + 80000114: 00100093 li ra,1 + 80000118: 00100113 li sp,1 + 8000011c: 00209f33 sll t5,ra,sp + 80000120: 00200e93 li t4,2 + 80000124: 00300193 li gp,3 + 80000128: 5fdf1063 bne t5,t4,80000708 <fail> + +000000008000012c <test_4>: + 8000012c: 00100093 li ra,1 + 80000130: 00700113 li sp,7 + 80000134: 00209f33 sll t5,ra,sp + 80000138: 08000e93 li t4,128 + 8000013c: 00400193 li gp,4 + 80000140: 5ddf1463 bne t5,t4,80000708 <fail> + +0000000080000144 <test_5>: + 80000144: 00100093 li ra,1 + 80000148: 00e00113 li sp,14 + 8000014c: 00209f33 sll t5,ra,sp + 80000150: 00004eb7 lui t4,0x4 + 80000154: 00500193 li gp,5 + 80000158: 5bdf1863 bne t5,t4,80000708 <fail> + +000000008000015c <test_6>: + 8000015c: 00100093 li ra,1 + 80000160: 01f00113 li sp,31 + 80000164: 00209f33 sll t5,ra,sp + 80000168: 00100e9b addiw t4,zero,1 + 8000016c: 01fe9e93 slli t4,t4,0x1f + 80000170: 00600193 li gp,6 + 80000174: 59df1a63 bne t5,t4,80000708 <fail> + +0000000080000178 <test_7>: + 80000178: fff00093 li ra,-1 + 8000017c: 00000113 li sp,0 + 80000180: 00209f33 sll t5,ra,sp + 80000184: fff00e93 li t4,-1 + 80000188: 00700193 li gp,7 + 8000018c: 57df1e63 bne t5,t4,80000708 <fail> + +0000000080000190 <test_8>: + 80000190: fff00093 li ra,-1 + 80000194: 00100113 li sp,1 + 80000198: 00209f33 sll t5,ra,sp + 8000019c: ffe00e93 li t4,-2 + 800001a0: 00800193 li gp,8 + 800001a4: 57df1263 bne t5,t4,80000708 <fail> + +00000000800001a8 <test_9>: + 800001a8: fff00093 li ra,-1 + 800001ac: 00700113 li sp,7 + 800001b0: 00209f33 sll t5,ra,sp + 800001b4: f8000e93 li t4,-128 + 800001b8: 00900193 li gp,9 + 800001bc: 55df1663 bne t5,t4,80000708 <fail> + +00000000800001c0 <test_10>: + 800001c0: fff00093 li ra,-1 + 800001c4: 00e00113 li sp,14 + 800001c8: 00209f33 sll t5,ra,sp + 800001cc: ffffceb7 lui t4,0xffffc + 800001d0: 00a00193 li gp,10 + 800001d4: 53df1a63 bne t5,t4,80000708 <fail> + +00000000800001d8 <test_11>: + 800001d8: fff00093 li ra,-1 + 800001dc: 01f00113 li sp,31 + 800001e0: 00209f33 sll t5,ra,sp + 800001e4: 80000eb7 lui t4,0x80000 + 800001e8: 00b00193 li gp,11 + 800001ec: 51df1e63 bne t5,t4,80000708 <fail> + +00000000800001f0 <test_12>: + 800001f0: 212120b7 lui ra,0x21212 + 800001f4: 1210809b addiw ra,ra,289 + 800001f8: 00000113 li sp,0 + 800001fc: 00209f33 sll t5,ra,sp + 80000200: 21212eb7 lui t4,0x21212 + 80000204: 121e8e9b addiw t4,t4,289 + 80000208: 00c00193 li gp,12 + 8000020c: 4fdf1e63 bne t5,t4,80000708 <fail> + +0000000080000210 <test_13>: + 80000210: 212120b7 lui ra,0x21212 + 80000214: 1210809b addiw ra,ra,289 + 80000218: 00100113 li sp,1 + 8000021c: 00209f33 sll t5,ra,sp + 80000220: 42424eb7 lui t4,0x42424 + 80000224: 242e8e9b addiw t4,t4,578 + 80000228: 00d00193 li gp,13 + 8000022c: 4ddf1e63 bne t5,t4,80000708 <fail> + +0000000080000230 <test_14>: + 80000230: 212120b7 lui ra,0x21212 + 80000234: 1210809b addiw ra,ra,289 + 80000238: 00700113 li sp,7 + 8000023c: 00209f33 sll t5,ra,sp + 80000240: 01091eb7 lui t4,0x1091 + 80000244: 909e8e9b addiw t4,t4,-1783 + 80000248: 00ce9e93 slli t4,t4,0xc + 8000024c: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> + 80000250: 00e00193 li gp,14 + 80000254: 4bdf1a63 bne t5,t4,80000708 <fail> + +0000000080000258 <test_15>: + 80000258: 212120b7 lui ra,0x21212 + 8000025c: 1210809b addiw ra,ra,289 + 80000260: 00e00113 li sp,14 + 80000264: 00209f33 sll t5,ra,sp + 80000268: 21212eb7 lui t4,0x21212 + 8000026c: 121e8e9b addiw t4,t4,289 + 80000270: 00ee9e93 slli t4,t4,0xe + 80000274: 00f00193 li gp,15 + 80000278: 49df1863 bne t5,t4,80000708 <fail> + +000000008000027c <test_16>: + 8000027c: 212120b7 lui ra,0x21212 + 80000280: 1210809b addiw ra,ra,289 + 80000284: 01f00113 li sp,31 + 80000288: 00209f33 sll t5,ra,sp + 8000028c: 21212eb7 lui t4,0x21212 + 80000290: 121e8e9b addiw t4,t4,289 + 80000294: 01fe9e93 slli t4,t4,0x1f + 80000298: 01000193 li gp,16 + 8000029c: 47df1663 bne t5,t4,80000708 <fail> + +00000000800002a0 <test_17>: + 800002a0: 212120b7 lui ra,0x21212 + 800002a4: 1210809b addiw ra,ra,289 + 800002a8: fc000113 li sp,-64 + 800002ac: 00209f33 sll t5,ra,sp + 800002b0: 21212eb7 lui t4,0x21212 + 800002b4: 121e8e9b addiw t4,t4,289 + 800002b8: 01100193 li gp,17 + 800002bc: 45df1663 bne t5,t4,80000708 <fail> + +00000000800002c0 <test_18>: + 800002c0: 212120b7 lui ra,0x21212 + 800002c4: 1210809b addiw ra,ra,289 + 800002c8: fc100113 li sp,-63 + 800002cc: 00209f33 sll t5,ra,sp + 800002d0: 42424eb7 lui t4,0x42424 + 800002d4: 242e8e9b addiw t4,t4,578 + 800002d8: 01200193 li gp,18 + 800002dc: 43df1663 bne t5,t4,80000708 <fail> + +00000000800002e0 <test_19>: + 800002e0: 212120b7 lui ra,0x21212 + 800002e4: 1210809b addiw ra,ra,289 + 800002e8: fc700113 li sp,-57 + 800002ec: 00209f33 sll t5,ra,sp + 800002f0: 01091eb7 lui t4,0x1091 + 800002f4: 909e8e9b addiw t4,t4,-1783 + 800002f8: 00ce9e93 slli t4,t4,0xc + 800002fc: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> + 80000300: 01300193 li gp,19 + 80000304: 41df1263 bne t5,t4,80000708 <fail> + +0000000080000308 <test_20>: + 80000308: 212120b7 lui ra,0x21212 + 8000030c: 1210809b addiw ra,ra,289 + 80000310: fce00113 li sp,-50 + 80000314: 00209f33 sll t5,ra,sp + 80000318: 21212eb7 lui t4,0x21212 + 8000031c: 121e8e9b addiw t4,t4,289 + 80000320: 00ee9e93 slli t4,t4,0xe + 80000324: 01400193 li gp,20 + 80000328: 3fdf1063 bne t5,t4,80000708 <fail> + +000000008000032c <test_21>: + 8000032c: 212120b7 lui ra,0x21212 + 80000330: 1210809b addiw ra,ra,289 + 80000334: fff00113 li sp,-1 + 80000338: 00209f33 sll t5,ra,sp + 8000033c: fff00e9b addiw t4,zero,-1 + 80000340: 03fe9e93 slli t4,t4,0x3f + 80000344: 01500193 li gp,21 + 80000348: 3ddf1063 bne t5,t4,80000708 <fail> + +000000008000034c <test_50>: + 8000034c: 00100093 li ra,1 + 80000350: 03f00113 li sp,63 + 80000354: 00209f33 sll t5,ra,sp + 80000358: fff00e9b addiw t4,zero,-1 + 8000035c: 03fe9e93 slli t4,t4,0x3f + 80000360: 03200193 li gp,50 + 80000364: 3bdf1263 bne t5,t4,80000708 <fail> + +0000000080000368 <test_51>: + 80000368: fff00093 li ra,-1 + 8000036c: 02700113 li sp,39 + 80000370: 00209f33 sll t5,ra,sp + 80000374: fff00e9b addiw t4,zero,-1 + 80000378: 027e9e93 slli t4,t4,0x27 + 8000037c: 03300193 li gp,51 + 80000380: 39df1463 bne t5,t4,80000708 <fail> + +0000000080000384 <test_52>: + 80000384: 212120b7 lui ra,0x21212 + 80000388: 1210809b addiw ra,ra,289 + 8000038c: 02b00113 li sp,43 + 80000390: 00209f33 sll t5,ra,sp + 80000394: 00012eb7 lui t4,0x12 + 80000398: 121e8e9b addiw t4,t4,289 + 8000039c: 02be9e93 slli t4,t4,0x2b + 800003a0: 03400193 li gp,52 + 800003a4: 37df1263 bne t5,t4,80000708 <fail> + +00000000800003a8 <test_22>: + 800003a8: 00100093 li ra,1 + 800003ac: 00700113 li sp,7 + 800003b0: 002090b3 sll ra,ra,sp + 800003b4: 08000e93 li t4,128 + 800003b8: 01600193 li gp,22 + 800003bc: 35d09663 bne ra,t4,80000708 <fail> + +00000000800003c0 <test_23>: + 800003c0: 00100093 li ra,1 + 800003c4: 00e00113 li sp,14 + 800003c8: 00209133 sll sp,ra,sp + 800003cc: 00004eb7 lui t4,0x4 + 800003d0: 01700193 li gp,23 + 800003d4: 33d11a63 bne sp,t4,80000708 <fail> + +00000000800003d8 <test_24>: + 800003d8: 00300093 li ra,3 + 800003dc: 001090b3 sll ra,ra,ra + 800003e0: 01800e93 li t4,24 + 800003e4: 01800193 li gp,24 + 800003e8: 33d09063 bne ra,t4,80000708 <fail> + +00000000800003ec <test_25>: + 800003ec: 00000213 li tp,0 + 800003f0: 00100093 li ra,1 + 800003f4: 00700113 li sp,7 + 800003f8: 00209f33 sll t5,ra,sp + 800003fc: 000f0313 mv t1,t5 + 80000400: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000404: 00200293 li t0,2 + 80000408: fe5214e3 bne tp,t0,800003f0 <test_25+0x4> + 8000040c: 08000e93 li t4,128 + 80000410: 01900193 li gp,25 + 80000414: 2fd31a63 bne t1,t4,80000708 <fail> + +0000000080000418 <test_26>: + 80000418: 00000213 li tp,0 + 8000041c: 00100093 li ra,1 + 80000420: 00e00113 li sp,14 + 80000424: 00209f33 sll t5,ra,sp + 80000428: 00000013 nop + 8000042c: 000f0313 mv t1,t5 + 80000430: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000434: 00200293 li t0,2 + 80000438: fe5212e3 bne tp,t0,8000041c <test_26+0x4> + 8000043c: 00004eb7 lui t4,0x4 + 80000440: 01a00193 li gp,26 + 80000444: 2dd31263 bne t1,t4,80000708 <fail> + +0000000080000448 <test_27>: + 80000448: 00000213 li tp,0 + 8000044c: 00100093 li ra,1 + 80000450: 01f00113 li sp,31 + 80000454: 00209f33 sll t5,ra,sp + 80000458: 00000013 nop + 8000045c: 00000013 nop + 80000460: 000f0313 mv t1,t5 + 80000464: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000468: 00200293 li t0,2 + 8000046c: fe5210e3 bne tp,t0,8000044c <test_27+0x4> + 80000470: 00100e9b addiw t4,zero,1 + 80000474: 01fe9e93 slli t4,t4,0x1f + 80000478: 01b00193 li gp,27 + 8000047c: 29d31663 bne t1,t4,80000708 <fail> + +0000000080000480 <test_28>: + 80000480: 00000213 li tp,0 + 80000484: 00100093 li ra,1 + 80000488: 00700113 li sp,7 + 8000048c: 00209f33 sll t5,ra,sp + 80000490: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000494: 00200293 li t0,2 + 80000498: fe5216e3 bne tp,t0,80000484 <test_28+0x4> + 8000049c: 08000e93 li t4,128 + 800004a0: 01c00193 li gp,28 + 800004a4: 27df1263 bne t5,t4,80000708 <fail> + +00000000800004a8 <test_29>: + 800004a8: 00000213 li tp,0 + 800004ac: 00100093 li ra,1 + 800004b0: 00e00113 li sp,14 + 800004b4: 00000013 nop + 800004b8: 00209f33 sll t5,ra,sp + 800004bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004c0: 00200293 li t0,2 + 800004c4: fe5214e3 bne tp,t0,800004ac <test_29+0x4> + 800004c8: 00004eb7 lui t4,0x4 + 800004cc: 01d00193 li gp,29 + 800004d0: 23df1c63 bne t5,t4,80000708 <fail> + +00000000800004d4 <test_30>: + 800004d4: 00000213 li tp,0 + 800004d8: 00100093 li ra,1 + 800004dc: 01f00113 li sp,31 + 800004e0: 00000013 nop + 800004e4: 00000013 nop + 800004e8: 00209f33 sll t5,ra,sp + 800004ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004f0: 00200293 li t0,2 + 800004f4: fe5212e3 bne tp,t0,800004d8 <test_30+0x4> + 800004f8: 00100e9b addiw t4,zero,1 + 800004fc: 01fe9e93 slli t4,t4,0x1f + 80000500: 01e00193 li gp,30 + 80000504: 21df1263 bne t5,t4,80000708 <fail> + +0000000080000508 <test_31>: + 80000508: 00000213 li tp,0 + 8000050c: 00100093 li ra,1 + 80000510: 00000013 nop + 80000514: 00700113 li sp,7 + 80000518: 00209f33 sll t5,ra,sp + 8000051c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000520: 00200293 li t0,2 + 80000524: fe5214e3 bne tp,t0,8000050c <test_31+0x4> + 80000528: 08000e93 li t4,128 + 8000052c: 01f00193 li gp,31 + 80000530: 1ddf1c63 bne t5,t4,80000708 <fail> + +0000000080000534 <test_32>: + 80000534: 00000213 li tp,0 + 80000538: 00100093 li ra,1 + 8000053c: 00000013 nop + 80000540: 00e00113 li sp,14 + 80000544: 00000013 nop + 80000548: 00209f33 sll t5,ra,sp + 8000054c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000550: 00200293 li t0,2 + 80000554: fe5212e3 bne tp,t0,80000538 <test_32+0x4> + 80000558: 00004eb7 lui t4,0x4 + 8000055c: 02000193 li gp,32 + 80000560: 1bdf1463 bne t5,t4,80000708 <fail> + +0000000080000564 <test_33>: + 80000564: 00000213 li tp,0 + 80000568: 00100093 li ra,1 + 8000056c: 00000013 nop + 80000570: 00000013 nop + 80000574: 01f00113 li sp,31 + 80000578: 00209f33 sll t5,ra,sp + 8000057c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000580: 00200293 li t0,2 + 80000584: fe5212e3 bne tp,t0,80000568 <test_33+0x4> + 80000588: 00100e9b addiw t4,zero,1 + 8000058c: 01fe9e93 slli t4,t4,0x1f + 80000590: 02100193 li gp,33 + 80000594: 17df1a63 bne t5,t4,80000708 <fail> + +0000000080000598 <test_34>: + 80000598: 00000213 li tp,0 + 8000059c: 00700113 li sp,7 + 800005a0: 00100093 li ra,1 + 800005a4: 00209f33 sll t5,ra,sp + 800005a8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005ac: 00200293 li t0,2 + 800005b0: fe5216e3 bne tp,t0,8000059c <test_34+0x4> + 800005b4: 08000e93 li t4,128 + 800005b8: 02200193 li gp,34 + 800005bc: 15df1663 bne t5,t4,80000708 <fail> + +00000000800005c0 <test_35>: + 800005c0: 00000213 li tp,0 + 800005c4: 00e00113 li sp,14 + 800005c8: 00100093 li ra,1 + 800005cc: 00000013 nop + 800005d0: 00209f33 sll t5,ra,sp + 800005d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005d8: 00200293 li t0,2 + 800005dc: fe5214e3 bne tp,t0,800005c4 <test_35+0x4> + 800005e0: 00004eb7 lui t4,0x4 + 800005e4: 02300193 li gp,35 + 800005e8: 13df1063 bne t5,t4,80000708 <fail> + +00000000800005ec <test_36>: + 800005ec: 00000213 li tp,0 + 800005f0: 01f00113 li sp,31 + 800005f4: 00100093 li ra,1 + 800005f8: 00000013 nop + 800005fc: 00000013 nop + 80000600: 00209f33 sll t5,ra,sp + 80000604: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000608: 00200293 li t0,2 + 8000060c: fe5212e3 bne tp,t0,800005f0 <test_36+0x4> + 80000610: 00100e9b addiw t4,zero,1 + 80000614: 01fe9e93 slli t4,t4,0x1f + 80000618: 02400193 li gp,36 + 8000061c: 0fdf1663 bne t5,t4,80000708 <fail> + +0000000080000620 <test_37>: + 80000620: 00000213 li tp,0 + 80000624: 00700113 li sp,7 + 80000628: 00000013 nop + 8000062c: 00100093 li ra,1 + 80000630: 00209f33 sll t5,ra,sp + 80000634: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000638: 00200293 li t0,2 + 8000063c: fe5214e3 bne tp,t0,80000624 <test_37+0x4> + 80000640: 08000e93 li t4,128 + 80000644: 02500193 li gp,37 + 80000648: 0ddf1063 bne t5,t4,80000708 <fail> + +000000008000064c <test_38>: + 8000064c: 00000213 li tp,0 + 80000650: 00e00113 li sp,14 + 80000654: 00000013 nop + 80000658: 00100093 li ra,1 + 8000065c: 00000013 nop + 80000660: 00209f33 sll t5,ra,sp + 80000664: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000668: 00200293 li t0,2 + 8000066c: fe5212e3 bne tp,t0,80000650 <test_38+0x4> + 80000670: 00004eb7 lui t4,0x4 + 80000674: 02600193 li gp,38 + 80000678: 09df1863 bne t5,t4,80000708 <fail> + +000000008000067c <test_39>: + 8000067c: 00000213 li tp,0 + 80000680: 01f00113 li sp,31 + 80000684: 00000013 nop + 80000688: 00000013 nop + 8000068c: 00100093 li ra,1 + 80000690: 00209f33 sll t5,ra,sp + 80000694: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000698: 00200293 li t0,2 + 8000069c: fe5212e3 bne tp,t0,80000680 <test_39+0x4> + 800006a0: 00100e9b addiw t4,zero,1 + 800006a4: 01fe9e93 slli t4,t4,0x1f + 800006a8: 02700193 li gp,39 + 800006ac: 05df1e63 bne t5,t4,80000708 <fail> + +00000000800006b0 <test_40>: + 800006b0: 00f00093 li ra,15 + 800006b4: 00101133 sll sp,zero,ra + 800006b8: 00000e93 li t4,0 + 800006bc: 02800193 li gp,40 + 800006c0: 05d11463 bne sp,t4,80000708 <fail> + +00000000800006c4 <test_41>: + 800006c4: 02000093 li ra,32 + 800006c8: 00009133 sll sp,ra,zero + 800006cc: 02000e93 li t4,32 + 800006d0: 02900193 li gp,41 + 800006d4: 03d11a63 bne sp,t4,80000708 <fail> + +00000000800006d8 <test_42>: + 800006d8: 000010b3 sll ra,zero,zero + 800006dc: 00000e93 li t4,0 + 800006e0: 02a00193 li gp,42 + 800006e4: 03d09263 bne ra,t4,80000708 <fail> + +00000000800006e8 <test_43>: + 800006e8: 40000093 li ra,1024 + 800006ec: 00001137 lui sp,0x1 + 800006f0: 8001011b addiw sp,sp,-2048 + 800006f4: 00209033 sll zero,ra,sp + 800006f8: 00000e93 li t4,0 + 800006fc: 02b00193 li gp,43 + 80000700: 01d01463 bne zero,t4,80000708 <fail> + 80000704: 00301c63 bne zero,gp,8000071c <pass> + +0000000080000708 <fail>: + 80000708: 0ff0000f fence + 8000070c: 00018063 beqz gp,8000070c <fail+0x4> + 80000710: 00119193 slli gp,gp,0x1 + 80000714: 0011e193 ori gp,gp,1 + 80000718: 00000073 ecall + +000000008000071c <pass>: + 8000071c: 0ff0000f fence + 80000720: 00100193 li gp,1 + 80000724: 00000073 ecall + 80000728: c0001073 unimp + 8000072c: 0000 unimp + 8000072e: 0000 unimp + 80000730: 0000 unimp + 80000732: 0000 unimp + 80000734: 0000 unimp + 80000736: 0000 unimp + 80000738: 0000 unimp + 8000073a: 0000 unimp + 8000073c: 0000 unimp + 8000073e: 0000 unimp + 80000740: 0000 unimp + 80000742: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sll.elf b/test/riscv/tests/rv64ui-p-sll.elf Binary files differnew file mode 100755 index 00000000..ad48a8ea --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sll.elf diff --git a/test/riscv/tests/rv64ui-p-slli.dump b/test/riscv/tests/rv64ui-p-slli.dump new file mode 100644 index 00000000..de783cf8 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-slli.dump @@ -0,0 +1,354 @@ + +rv64ui-p-slli: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00100093 li ra,1 + 80000100: 00009f13 slli t5,ra,0x0 + 80000104: 00100e93 li t4,1 + 80000108: 00200193 li gp,2 + 8000010c: 2fdf1a63 bne t5,t4,80000400 <fail> + +0000000080000110 <test_3>: + 80000110: 00100093 li ra,1 + 80000114: 00109f13 slli t5,ra,0x1 + 80000118: 00200e93 li t4,2 + 8000011c: 00300193 li gp,3 + 80000120: 2fdf1063 bne t5,t4,80000400 <fail> + +0000000080000124 <test_4>: + 80000124: 00100093 li ra,1 + 80000128: 00709f13 slli t5,ra,0x7 + 8000012c: 08000e93 li t4,128 + 80000130: 00400193 li gp,4 + 80000134: 2ddf1663 bne t5,t4,80000400 <fail> + +0000000080000138 <test_5>: + 80000138: 00100093 li ra,1 + 8000013c: 00e09f13 slli t5,ra,0xe + 80000140: 00004eb7 lui t4,0x4 + 80000144: 00500193 li gp,5 + 80000148: 2bdf1c63 bne t5,t4,80000400 <fail> + +000000008000014c <test_6>: + 8000014c: 00100093 li ra,1 + 80000150: 01f09f13 slli t5,ra,0x1f + 80000154: 00100e9b addiw t4,zero,1 + 80000158: 01fe9e93 slli t4,t4,0x1f + 8000015c: 00600193 li gp,6 + 80000160: 2bdf1063 bne t5,t4,80000400 <fail> + +0000000080000164 <test_7>: + 80000164: fff00093 li ra,-1 + 80000168: 00009f13 slli t5,ra,0x0 + 8000016c: fff00e93 li t4,-1 + 80000170: 00700193 li gp,7 + 80000174: 29df1663 bne t5,t4,80000400 <fail> + +0000000080000178 <test_8>: + 80000178: fff00093 li ra,-1 + 8000017c: 00109f13 slli t5,ra,0x1 + 80000180: ffe00e93 li t4,-2 + 80000184: 00800193 li gp,8 + 80000188: 27df1c63 bne t5,t4,80000400 <fail> + +000000008000018c <test_9>: + 8000018c: fff00093 li ra,-1 + 80000190: 00709f13 slli t5,ra,0x7 + 80000194: f8000e93 li t4,-128 + 80000198: 00900193 li gp,9 + 8000019c: 27df1263 bne t5,t4,80000400 <fail> + +00000000800001a0 <test_10>: + 800001a0: fff00093 li ra,-1 + 800001a4: 00e09f13 slli t5,ra,0xe + 800001a8: ffffceb7 lui t4,0xffffc + 800001ac: 00a00193 li gp,10 + 800001b0: 25df1863 bne t5,t4,80000400 <fail> + +00000000800001b4 <test_11>: + 800001b4: fff00093 li ra,-1 + 800001b8: 01f09f13 slli t5,ra,0x1f + 800001bc: 80000eb7 lui t4,0x80000 + 800001c0: 00b00193 li gp,11 + 800001c4: 23df1e63 bne t5,t4,80000400 <fail> + +00000000800001c8 <test_12>: + 800001c8: 212120b7 lui ra,0x21212 + 800001cc: 1210809b addiw ra,ra,289 + 800001d0: 00009f13 slli t5,ra,0x0 + 800001d4: 21212eb7 lui t4,0x21212 + 800001d8: 121e8e9b addiw t4,t4,289 + 800001dc: 00c00193 li gp,12 + 800001e0: 23df1063 bne t5,t4,80000400 <fail> + +00000000800001e4 <test_13>: + 800001e4: 212120b7 lui ra,0x21212 + 800001e8: 1210809b addiw ra,ra,289 + 800001ec: 00109f13 slli t5,ra,0x1 + 800001f0: 42424eb7 lui t4,0x42424 + 800001f4: 242e8e9b addiw t4,t4,578 + 800001f8: 00d00193 li gp,13 + 800001fc: 21df1263 bne t5,t4,80000400 <fail> + +0000000080000200 <test_14>: + 80000200: 212120b7 lui ra,0x21212 + 80000204: 1210809b addiw ra,ra,289 + 80000208: 00709f13 slli t5,ra,0x7 + 8000020c: 01091eb7 lui t4,0x1091 + 80000210: 909e8e9b addiw t4,t4,-1783 + 80000214: 00ce9e93 slli t4,t4,0xc + 80000218: 080e8e93 addi t4,t4,128 # 1091080 <_start-0x7ef6ef80> + 8000021c: 00e00193 li gp,14 + 80000220: 1fdf1063 bne t5,t4,80000400 <fail> + +0000000080000224 <test_15>: + 80000224: 212120b7 lui ra,0x21212 + 80000228: 1210809b addiw ra,ra,289 + 8000022c: 00e09f13 slli t5,ra,0xe + 80000230: 21212eb7 lui t4,0x21212 + 80000234: 121e8e9b addiw t4,t4,289 + 80000238: 00ee9e93 slli t4,t4,0xe + 8000023c: 00f00193 li gp,15 + 80000240: 1ddf1063 bne t5,t4,80000400 <fail> + +0000000080000244 <test_16>: + 80000244: 212120b7 lui ra,0x21212 + 80000248: 1210809b addiw ra,ra,289 + 8000024c: 01f09f13 slli t5,ra,0x1f + 80000250: 21212eb7 lui t4,0x21212 + 80000254: 121e8e9b addiw t4,t4,289 + 80000258: 01fe9e93 slli t4,t4,0x1f + 8000025c: 01000193 li gp,16 + 80000260: 1bdf1063 bne t5,t4,80000400 <fail> + +0000000080000264 <test_50>: + 80000264: 00100093 li ra,1 + 80000268: 03f00113 li sp,63 + 8000026c: 00209f33 sll t5,ra,sp + 80000270: fff00e9b addiw t4,zero,-1 + 80000274: 03fe9e93 slli t4,t4,0x3f + 80000278: 03200193 li gp,50 + 8000027c: 19df1263 bne t5,t4,80000400 <fail> + +0000000080000280 <test_51>: + 80000280: fff00093 li ra,-1 + 80000284: 02700113 li sp,39 + 80000288: 00209f33 sll t5,ra,sp + 8000028c: fff00e9b addiw t4,zero,-1 + 80000290: 027e9e93 slli t4,t4,0x27 + 80000294: 03300193 li gp,51 + 80000298: 17df1463 bne t5,t4,80000400 <fail> + +000000008000029c <test_52>: + 8000029c: 212120b7 lui ra,0x21212 + 800002a0: 1210809b addiw ra,ra,289 + 800002a4: 02b00113 li sp,43 + 800002a8: 00209f33 sll t5,ra,sp + 800002ac: 00012eb7 lui t4,0x12 + 800002b0: 121e8e9b addiw t4,t4,289 + 800002b4: 02be9e93 slli t4,t4,0x2b + 800002b8: 03400193 li gp,52 + 800002bc: 15df1263 bne t5,t4,80000400 <fail> + +00000000800002c0 <test_17>: + 800002c0: 00100093 li ra,1 + 800002c4: 00709093 slli ra,ra,0x7 + 800002c8: 08000e93 li t4,128 + 800002cc: 01100193 li gp,17 + 800002d0: 13d09863 bne ra,t4,80000400 <fail> + +00000000800002d4 <test_18>: + 800002d4: 00000213 li tp,0 + 800002d8: 00100093 li ra,1 + 800002dc: 00709f13 slli t5,ra,0x7 + 800002e0: 000f0313 mv t1,t5 + 800002e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002e8: 00200293 li t0,2 + 800002ec: fe5216e3 bne tp,t0,800002d8 <test_18+0x4> + 800002f0: 08000e93 li t4,128 + 800002f4: 01200193 li gp,18 + 800002f8: 11d31463 bne t1,t4,80000400 <fail> + +00000000800002fc <test_19>: + 800002fc: 00000213 li tp,0 + 80000300: 00100093 li ra,1 + 80000304: 00e09f13 slli t5,ra,0xe + 80000308: 00000013 nop + 8000030c: 000f0313 mv t1,t5 + 80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000314: 00200293 li t0,2 + 80000318: fe5214e3 bne tp,t0,80000300 <test_19+0x4> + 8000031c: 00004eb7 lui t4,0x4 + 80000320: 01300193 li gp,19 + 80000324: 0dd31e63 bne t1,t4,80000400 <fail> + +0000000080000328 <test_20>: + 80000328: 00000213 li tp,0 + 8000032c: 00100093 li ra,1 + 80000330: 01f09f13 slli t5,ra,0x1f + 80000334: 00000013 nop + 80000338: 00000013 nop + 8000033c: 000f0313 mv t1,t5 + 80000340: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000344: 00200293 li t0,2 + 80000348: fe5212e3 bne tp,t0,8000032c <test_20+0x4> + 8000034c: 00100e9b addiw t4,zero,1 + 80000350: 01fe9e93 slli t4,t4,0x1f + 80000354: 01400193 li gp,20 + 80000358: 0bd31463 bne t1,t4,80000400 <fail> + +000000008000035c <test_21>: + 8000035c: 00000213 li tp,0 + 80000360: 00100093 li ra,1 + 80000364: 00709f13 slli t5,ra,0x7 + 80000368: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000036c: 00200293 li t0,2 + 80000370: fe5218e3 bne tp,t0,80000360 <test_21+0x4> + 80000374: 08000e93 li t4,128 + 80000378: 01500193 li gp,21 + 8000037c: 09df1263 bne t5,t4,80000400 <fail> + +0000000080000380 <test_22>: + 80000380: 00000213 li tp,0 + 80000384: 00100093 li ra,1 + 80000388: 00000013 nop + 8000038c: 00e09f13 slli t5,ra,0xe + 80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000394: 00200293 li t0,2 + 80000398: fe5216e3 bne tp,t0,80000384 <test_22+0x4> + 8000039c: 00004eb7 lui t4,0x4 + 800003a0: 01600193 li gp,22 + 800003a4: 05df1e63 bne t5,t4,80000400 <fail> + +00000000800003a8 <test_23>: + 800003a8: 00000213 li tp,0 + 800003ac: 00100093 li ra,1 + 800003b0: 00000013 nop + 800003b4: 00000013 nop + 800003b8: 01f09f13 slli t5,ra,0x1f + 800003bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003c0: 00200293 li t0,2 + 800003c4: fe5214e3 bne tp,t0,800003ac <test_23+0x4> + 800003c8: 00100e9b addiw t4,zero,1 + 800003cc: 01fe9e93 slli t4,t4,0x1f + 800003d0: 01700193 li gp,23 + 800003d4: 03df1663 bne t5,t4,80000400 <fail> + +00000000800003d8 <test_24>: + 800003d8: 01f01093 slli ra,zero,0x1f + 800003dc: 00000e93 li t4,0 + 800003e0: 01800193 li gp,24 + 800003e4: 01d09e63 bne ra,t4,80000400 <fail> + +00000000800003e8 <test_25>: + 800003e8: 02100093 li ra,33 + 800003ec: 01409013 slli zero,ra,0x14 + 800003f0: 00000e93 li t4,0 + 800003f4: 01900193 li gp,25 + 800003f8: 01d01463 bne zero,t4,80000400 <fail> + 800003fc: 00301c63 bne zero,gp,80000414 <pass> + +0000000080000400 <fail>: + 80000400: 0ff0000f fence + 80000404: 00018063 beqz gp,80000404 <fail+0x4> + 80000408: 00119193 slli gp,gp,0x1 + 8000040c: 0011e193 ori gp,gp,1 + 80000410: 00000073 ecall + +0000000080000414 <pass>: + 80000414: 0ff0000f fence + 80000418: 00100193 li gp,1 + 8000041c: 00000073 ecall + 80000420: c0001073 unimp + 80000424: 0000 unimp + 80000426: 0000 unimp + 80000428: 0000 unimp + 8000042a: 0000 unimp + 8000042c: 0000 unimp + 8000042e: 0000 unimp + 80000430: 0000 unimp + 80000432: 0000 unimp + 80000434: 0000 unimp + 80000436: 0000 unimp + 80000438: 0000 unimp + 8000043a: 0000 unimp + 8000043c: 0000 unimp + 8000043e: 0000 unimp + 80000440: 0000 unimp + 80000442: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-slli.elf b/test/riscv/tests/rv64ui-p-slli.elf Binary files differnew file mode 100755 index 00000000..12c898f3 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-slli.elf diff --git a/test/riscv/tests/rv64ui-p-slliw.dump b/test/riscv/tests/rv64ui-p-slliw.dump new file mode 100644 index 00000000..b821b9fc --- /dev/null +++ b/test/riscv/tests/rv64ui-p-slliw.dump @@ -0,0 +1,316 @@ + +rv64ui-p-slliw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00100093 li ra,1 + 80000100: 00009f1b slliw t5,ra,0x0 + 80000104: 00100e93 li t4,1 + 80000108: 00200193 li gp,2 + 8000010c: 27df1a63 bne t5,t4,80000380 <fail> + +0000000080000110 <test_3>: + 80000110: 00100093 li ra,1 + 80000114: 00109f1b slliw t5,ra,0x1 + 80000118: 00200e93 li t4,2 + 8000011c: 00300193 li gp,3 + 80000120: 27df1063 bne t5,t4,80000380 <fail> + +0000000080000124 <test_4>: + 80000124: 00100093 li ra,1 + 80000128: 00709f1b slliw t5,ra,0x7 + 8000012c: 08000e93 li t4,128 + 80000130: 00400193 li gp,4 + 80000134: 25df1663 bne t5,t4,80000380 <fail> + +0000000080000138 <test_5>: + 80000138: 00100093 li ra,1 + 8000013c: 00e09f1b slliw t5,ra,0xe + 80000140: 00004eb7 lui t4,0x4 + 80000144: 00500193 li gp,5 + 80000148: 23df1c63 bne t5,t4,80000380 <fail> + +000000008000014c <test_6>: + 8000014c: 00100093 li ra,1 + 80000150: 01f09f1b slliw t5,ra,0x1f + 80000154: 80000eb7 lui t4,0x80000 + 80000158: 00600193 li gp,6 + 8000015c: 23df1263 bne t5,t4,80000380 <fail> + +0000000080000160 <test_7>: + 80000160: fff00093 li ra,-1 + 80000164: 00009f1b slliw t5,ra,0x0 + 80000168: fff00e93 li t4,-1 + 8000016c: 00700193 li gp,7 + 80000170: 21df1863 bne t5,t4,80000380 <fail> + +0000000080000174 <test_8>: + 80000174: fff00093 li ra,-1 + 80000178: 00109f1b slliw t5,ra,0x1 + 8000017c: ffe00e93 li t4,-2 + 80000180: 00800193 li gp,8 + 80000184: 1fdf1e63 bne t5,t4,80000380 <fail> + +0000000080000188 <test_9>: + 80000188: fff00093 li ra,-1 + 8000018c: 00709f1b slliw t5,ra,0x7 + 80000190: f8000e93 li t4,-128 + 80000194: 00900193 li gp,9 + 80000198: 1fdf1463 bne t5,t4,80000380 <fail> + +000000008000019c <test_10>: + 8000019c: fff00093 li ra,-1 + 800001a0: 00e09f1b slliw t5,ra,0xe + 800001a4: ffffceb7 lui t4,0xffffc + 800001a8: 00a00193 li gp,10 + 800001ac: 1ddf1a63 bne t5,t4,80000380 <fail> + +00000000800001b0 <test_11>: + 800001b0: fff00093 li ra,-1 + 800001b4: 01f09f1b slliw t5,ra,0x1f + 800001b8: 80000eb7 lui t4,0x80000 + 800001bc: 00b00193 li gp,11 + 800001c0: 1ddf1063 bne t5,t4,80000380 <fail> + +00000000800001c4 <test_12>: + 800001c4: 212120b7 lui ra,0x21212 + 800001c8: 1210809b addiw ra,ra,289 + 800001cc: 00009f1b slliw t5,ra,0x0 + 800001d0: 21212eb7 lui t4,0x21212 + 800001d4: 121e8e9b addiw t4,t4,289 + 800001d8: 00c00193 li gp,12 + 800001dc: 1bdf1263 bne t5,t4,80000380 <fail> + +00000000800001e0 <test_13>: + 800001e0: 212120b7 lui ra,0x21212 + 800001e4: 1210809b addiw ra,ra,289 + 800001e8: 00109f1b slliw t5,ra,0x1 + 800001ec: 42424eb7 lui t4,0x42424 + 800001f0: 242e8e9b addiw t4,t4,578 + 800001f4: 00d00193 li gp,13 + 800001f8: 19df1463 bne t5,t4,80000380 <fail> + +00000000800001fc <test_14>: + 800001fc: 212120b7 lui ra,0x21212 + 80000200: 1210809b addiw ra,ra,289 + 80000204: 00709f1b slliw t5,ra,0x7 + 80000208: 90909eb7 lui t4,0x90909 + 8000020c: 080e8e9b addiw t4,t4,128 + 80000210: 00e00193 li gp,14 + 80000214: 17df1663 bne t5,t4,80000380 <fail> + +0000000080000218 <test_15>: + 80000218: 212120b7 lui ra,0x21212 + 8000021c: 1210809b addiw ra,ra,289 + 80000220: 00e09f1b slliw t5,ra,0xe + 80000224: 48484eb7 lui t4,0x48484 + 80000228: 00f00193 li gp,15 + 8000022c: 15df1a63 bne t5,t4,80000380 <fail> + +0000000080000230 <test_16>: + 80000230: 212120b7 lui ra,0x21212 + 80000234: 1210809b addiw ra,ra,289 + 80000238: 01f09f1b slliw t5,ra,0x1f + 8000023c: 80000eb7 lui t4,0x80000 + 80000240: 01000193 li gp,16 + 80000244: 13df1e63 bne t5,t4,80000380 <fail> + +0000000080000248 <test_17>: + 80000248: 00100093 li ra,1 + 8000024c: 0070909b slliw ra,ra,0x7 + 80000250: 08000e93 li t4,128 + 80000254: 01100193 li gp,17 + 80000258: 13d09463 bne ra,t4,80000380 <fail> + +000000008000025c <test_18>: + 8000025c: 00000213 li tp,0 + 80000260: 00100093 li ra,1 + 80000264: 00709f1b slliw t5,ra,0x7 + 80000268: 000f0313 mv t1,t5 + 8000026c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000270: 00200293 li t0,2 + 80000274: fe5216e3 bne tp,t0,80000260 <test_18+0x4> + 80000278: 08000e93 li t4,128 + 8000027c: 01200193 li gp,18 + 80000280: 11d31063 bne t1,t4,80000380 <fail> + +0000000080000284 <test_19>: + 80000284: 00000213 li tp,0 + 80000288: 00100093 li ra,1 + 8000028c: 00e09f1b slliw t5,ra,0xe + 80000290: 00000013 nop + 80000294: 000f0313 mv t1,t5 + 80000298: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000029c: 00200293 li t0,2 + 800002a0: fe5214e3 bne tp,t0,80000288 <test_19+0x4> + 800002a4: 00004eb7 lui t4,0x4 + 800002a8: 01300193 li gp,19 + 800002ac: 0dd31a63 bne t1,t4,80000380 <fail> + +00000000800002b0 <test_20>: + 800002b0: 00000213 li tp,0 + 800002b4: 00100093 li ra,1 + 800002b8: 01f09f1b slliw t5,ra,0x1f + 800002bc: 00000013 nop + 800002c0: 00000013 nop + 800002c4: 000f0313 mv t1,t5 + 800002c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002cc: 00200293 li t0,2 + 800002d0: fe5212e3 bne tp,t0,800002b4 <test_20+0x4> + 800002d4: 80000eb7 lui t4,0x80000 + 800002d8: 01400193 li gp,20 + 800002dc: 0bd31263 bne t1,t4,80000380 <fail> + +00000000800002e0 <test_21>: + 800002e0: 00000213 li tp,0 + 800002e4: 00100093 li ra,1 + 800002e8: 00709f1b slliw t5,ra,0x7 + 800002ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002f0: 00200293 li t0,2 + 800002f4: fe5218e3 bne tp,t0,800002e4 <test_21+0x4> + 800002f8: 08000e93 li t4,128 + 800002fc: 01500193 li gp,21 + 80000300: 09df1063 bne t5,t4,80000380 <fail> + +0000000080000304 <test_22>: + 80000304: 00000213 li tp,0 + 80000308: 00100093 li ra,1 + 8000030c: 00000013 nop + 80000310: 00e09f1b slliw t5,ra,0xe + 80000314: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000318: 00200293 li t0,2 + 8000031c: fe5216e3 bne tp,t0,80000308 <test_22+0x4> + 80000320: 00004eb7 lui t4,0x4 + 80000324: 01600193 li gp,22 + 80000328: 05df1c63 bne t5,t4,80000380 <fail> + +000000008000032c <test_23>: + 8000032c: 00000213 li tp,0 + 80000330: 00100093 li ra,1 + 80000334: 00000013 nop + 80000338: 00000013 nop + 8000033c: 01f09f1b slliw t5,ra,0x1f + 80000340: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000344: 00200293 li t0,2 + 80000348: fe5214e3 bne tp,t0,80000330 <test_23+0x4> + 8000034c: 80000eb7 lui t4,0x80000 + 80000350: 01700193 li gp,23 + 80000354: 03df1663 bne t5,t4,80000380 <fail> + +0000000080000358 <test_24>: + 80000358: 01f0109b slliw ra,zero,0x1f + 8000035c: 00000e93 li t4,0 + 80000360: 01800193 li gp,24 + 80000364: 01d09e63 bne ra,t4,80000380 <fail> + +0000000080000368 <test_25>: + 80000368: 01f00093 li ra,31 + 8000036c: 01c0901b slliw zero,ra,0x1c + 80000370: 00000e93 li t4,0 + 80000374: 01900193 li gp,25 + 80000378: 01d01463 bne zero,t4,80000380 <fail> + 8000037c: 00301c63 bne zero,gp,80000394 <pass> + +0000000080000380 <fail>: + 80000380: 0ff0000f fence + 80000384: 00018063 beqz gp,80000384 <fail+0x4> + 80000388: 00119193 slli gp,gp,0x1 + 8000038c: 0011e193 ori gp,gp,1 + 80000390: 00000073 ecall + +0000000080000394 <pass>: + 80000394: 0ff0000f fence + 80000398: 00100193 li gp,1 + 8000039c: 00000073 ecall + 800003a0: c0001073 unimp + 800003a4: 0000 unimp + 800003a6: 0000 unimp + 800003a8: 0000 unimp + 800003aa: 0000 unimp + 800003ac: 0000 unimp + 800003ae: 0000 unimp + 800003b0: 0000 unimp + 800003b2: 0000 unimp + 800003b4: 0000 unimp + 800003b6: 0000 unimp + 800003b8: 0000 unimp + 800003ba: 0000 unimp + 800003bc: 0000 unimp + 800003be: 0000 unimp + 800003c0: 0000 unimp + 800003c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-slliw.elf b/test/riscv/tests/rv64ui-p-slliw.elf Binary files differnew file mode 100755 index 00000000..b8046e69 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-slliw.elf diff --git a/test/riscv/tests/rv64ui-p-sllw.dump b/test/riscv/tests/rv64ui-p-sllw.dump new file mode 100644 index 00000000..45f030a1 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sllw.dump @@ -0,0 +1,550 @@ + +rv64ui-p-sllw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00100093 li ra,1 + 80000100: 00000113 li sp,0 + 80000104: 00209f3b sllw t5,ra,sp + 80000108: 00100e93 li t4,1 + 8000010c: 00200193 li gp,2 + 80000110: 55df1c63 bne t5,t4,80000668 <fail> + +0000000080000114 <test_3>: + 80000114: 00100093 li ra,1 + 80000118: 00100113 li sp,1 + 8000011c: 00209f3b sllw t5,ra,sp + 80000120: 00200e93 li t4,2 + 80000124: 00300193 li gp,3 + 80000128: 55df1063 bne t5,t4,80000668 <fail> + +000000008000012c <test_4>: + 8000012c: 00100093 li ra,1 + 80000130: 00700113 li sp,7 + 80000134: 00209f3b sllw t5,ra,sp + 80000138: 08000e93 li t4,128 + 8000013c: 00400193 li gp,4 + 80000140: 53df1463 bne t5,t4,80000668 <fail> + +0000000080000144 <test_5>: + 80000144: 00100093 li ra,1 + 80000148: 00e00113 li sp,14 + 8000014c: 00209f3b sllw t5,ra,sp + 80000150: 00004eb7 lui t4,0x4 + 80000154: 00500193 li gp,5 + 80000158: 51df1863 bne t5,t4,80000668 <fail> + +000000008000015c <test_6>: + 8000015c: 00100093 li ra,1 + 80000160: 01f00113 li sp,31 + 80000164: 00209f3b sllw t5,ra,sp + 80000168: 80000eb7 lui t4,0x80000 + 8000016c: 00600193 li gp,6 + 80000170: 4fdf1c63 bne t5,t4,80000668 <fail> + +0000000080000174 <test_7>: + 80000174: fff00093 li ra,-1 + 80000178: 00000113 li sp,0 + 8000017c: 00209f3b sllw t5,ra,sp + 80000180: fff00e93 li t4,-1 + 80000184: 00700193 li gp,7 + 80000188: 4fdf1063 bne t5,t4,80000668 <fail> + +000000008000018c <test_8>: + 8000018c: fff00093 li ra,-1 + 80000190: 00100113 li sp,1 + 80000194: 00209f3b sllw t5,ra,sp + 80000198: ffe00e93 li t4,-2 + 8000019c: 00800193 li gp,8 + 800001a0: 4ddf1463 bne t5,t4,80000668 <fail> + +00000000800001a4 <test_9>: + 800001a4: fff00093 li ra,-1 + 800001a8: 00700113 li sp,7 + 800001ac: 00209f3b sllw t5,ra,sp + 800001b0: f8000e93 li t4,-128 + 800001b4: 00900193 li gp,9 + 800001b8: 4bdf1863 bne t5,t4,80000668 <fail> + +00000000800001bc <test_10>: + 800001bc: fff00093 li ra,-1 + 800001c0: 00e00113 li sp,14 + 800001c4: 00209f3b sllw t5,ra,sp + 800001c8: ffffceb7 lui t4,0xffffc + 800001cc: 00a00193 li gp,10 + 800001d0: 49df1c63 bne t5,t4,80000668 <fail> + +00000000800001d4 <test_11>: + 800001d4: fff00093 li ra,-1 + 800001d8: 01f00113 li sp,31 + 800001dc: 00209f3b sllw t5,ra,sp + 800001e0: 80000eb7 lui t4,0x80000 + 800001e4: 00b00193 li gp,11 + 800001e8: 49df1063 bne t5,t4,80000668 <fail> + +00000000800001ec <test_12>: + 800001ec: 212120b7 lui ra,0x21212 + 800001f0: 1210809b addiw ra,ra,289 + 800001f4: 00000113 li sp,0 + 800001f8: 00209f3b sllw t5,ra,sp + 800001fc: 21212eb7 lui t4,0x21212 + 80000200: 121e8e9b addiw t4,t4,289 + 80000204: 00c00193 li gp,12 + 80000208: 47df1063 bne t5,t4,80000668 <fail> + +000000008000020c <test_13>: + 8000020c: 212120b7 lui ra,0x21212 + 80000210: 1210809b addiw ra,ra,289 + 80000214: 00100113 li sp,1 + 80000218: 00209f3b sllw t5,ra,sp + 8000021c: 42424eb7 lui t4,0x42424 + 80000220: 242e8e9b addiw t4,t4,578 + 80000224: 00d00193 li gp,13 + 80000228: 45df1063 bne t5,t4,80000668 <fail> + +000000008000022c <test_14>: + 8000022c: 212120b7 lui ra,0x21212 + 80000230: 1210809b addiw ra,ra,289 + 80000234: 00700113 li sp,7 + 80000238: 00209f3b sllw t5,ra,sp + 8000023c: 90909eb7 lui t4,0x90909 + 80000240: 080e8e9b addiw t4,t4,128 + 80000244: 00e00193 li gp,14 + 80000248: 43df1063 bne t5,t4,80000668 <fail> + +000000008000024c <test_15>: + 8000024c: 212120b7 lui ra,0x21212 + 80000250: 1210809b addiw ra,ra,289 + 80000254: 00e00113 li sp,14 + 80000258: 00209f3b sllw t5,ra,sp + 8000025c: 48484eb7 lui t4,0x48484 + 80000260: 00f00193 li gp,15 + 80000264: 41df1263 bne t5,t4,80000668 <fail> + +0000000080000268 <test_16>: + 80000268: 212120b7 lui ra,0x21212 + 8000026c: 1210809b addiw ra,ra,289 + 80000270: 01f00113 li sp,31 + 80000274: 00209f3b sllw t5,ra,sp + 80000278: 80000eb7 lui t4,0x80000 + 8000027c: 01000193 li gp,16 + 80000280: 3fdf1463 bne t5,t4,80000668 <fail> + +0000000080000284 <test_17>: + 80000284: 212120b7 lui ra,0x21212 + 80000288: 1210809b addiw ra,ra,289 + 8000028c: fe000113 li sp,-32 + 80000290: 00209f3b sllw t5,ra,sp + 80000294: 21212eb7 lui t4,0x21212 + 80000298: 121e8e9b addiw t4,t4,289 + 8000029c: 01100193 li gp,17 + 800002a0: 3ddf1463 bne t5,t4,80000668 <fail> + +00000000800002a4 <test_18>: + 800002a4: 212120b7 lui ra,0x21212 + 800002a8: 1210809b addiw ra,ra,289 + 800002ac: fe100113 li sp,-31 + 800002b0: 00209f3b sllw t5,ra,sp + 800002b4: 42424eb7 lui t4,0x42424 + 800002b8: 242e8e9b addiw t4,t4,578 + 800002bc: 01200193 li gp,18 + 800002c0: 3bdf1463 bne t5,t4,80000668 <fail> + +00000000800002c4 <test_19>: + 800002c4: 212120b7 lui ra,0x21212 + 800002c8: 1210809b addiw ra,ra,289 + 800002cc: fe700113 li sp,-25 + 800002d0: 00209f3b sllw t5,ra,sp + 800002d4: 90909eb7 lui t4,0x90909 + 800002d8: 080e8e9b addiw t4,t4,128 + 800002dc: 01300193 li gp,19 + 800002e0: 39df1463 bne t5,t4,80000668 <fail> + +00000000800002e4 <test_20>: + 800002e4: 212120b7 lui ra,0x21212 + 800002e8: 1210809b addiw ra,ra,289 + 800002ec: fee00113 li sp,-18 + 800002f0: 00209f3b sllw t5,ra,sp + 800002f4: 48484eb7 lui t4,0x48484 + 800002f8: 01400193 li gp,20 + 800002fc: 37df1663 bne t5,t4,80000668 <fail> + +0000000080000300 <test_21>: + 80000300: 212120b7 lui ra,0x21212 + 80000304: 1210809b addiw ra,ra,289 + 80000308: fff00113 li sp,-1 + 8000030c: 00209f3b sllw t5,ra,sp + 80000310: 80000eb7 lui t4,0x80000 + 80000314: 01500193 li gp,21 + 80000318: 35df1863 bne t5,t4,80000668 <fail> + +000000008000031c <test_22>: + 8000031c: 00100093 li ra,1 + 80000320: 00700113 li sp,7 + 80000324: 002090bb sllw ra,ra,sp + 80000328: 08000e93 li t4,128 + 8000032c: 01600193 li gp,22 + 80000330: 33d09c63 bne ra,t4,80000668 <fail> + +0000000080000334 <test_23>: + 80000334: 00100093 li ra,1 + 80000338: 00e00113 li sp,14 + 8000033c: 0020913b sllw sp,ra,sp + 80000340: 00004eb7 lui t4,0x4 + 80000344: 01700193 li gp,23 + 80000348: 33d11063 bne sp,t4,80000668 <fail> + +000000008000034c <test_24>: + 8000034c: 00300093 li ra,3 + 80000350: 001090bb sllw ra,ra,ra + 80000354: 01800e93 li t4,24 + 80000358: 01800193 li gp,24 + 8000035c: 31d09663 bne ra,t4,80000668 <fail> + +0000000080000360 <test_25>: + 80000360: 00000213 li tp,0 + 80000364: 00100093 li ra,1 + 80000368: 00700113 li sp,7 + 8000036c: 00209f3b sllw t5,ra,sp + 80000370: 000f0313 mv t1,t5 + 80000374: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000378: 00200293 li t0,2 + 8000037c: fe5214e3 bne tp,t0,80000364 <test_25+0x4> + 80000380: 08000e93 li t4,128 + 80000384: 01900193 li gp,25 + 80000388: 2fd31063 bne t1,t4,80000668 <fail> + +000000008000038c <test_26>: + 8000038c: 00000213 li tp,0 + 80000390: 00100093 li ra,1 + 80000394: 00e00113 li sp,14 + 80000398: 00209f3b sllw t5,ra,sp + 8000039c: 00000013 nop + 800003a0: 000f0313 mv t1,t5 + 800003a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003a8: 00200293 li t0,2 + 800003ac: fe5212e3 bne tp,t0,80000390 <test_26+0x4> + 800003b0: 00004eb7 lui t4,0x4 + 800003b4: 01a00193 li gp,26 + 800003b8: 2bd31863 bne t1,t4,80000668 <fail> + +00000000800003bc <test_27>: + 800003bc: 00000213 li tp,0 + 800003c0: 00100093 li ra,1 + 800003c4: 01f00113 li sp,31 + 800003c8: 00209f3b sllw t5,ra,sp + 800003cc: 00000013 nop + 800003d0: 00000013 nop + 800003d4: 000f0313 mv t1,t5 + 800003d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003dc: 00200293 li t0,2 + 800003e0: fe5210e3 bne tp,t0,800003c0 <test_27+0x4> + 800003e4: 80000eb7 lui t4,0x80000 + 800003e8: 01b00193 li gp,27 + 800003ec: 27d31e63 bne t1,t4,80000668 <fail> + +00000000800003f0 <test_28>: + 800003f0: 00000213 li tp,0 + 800003f4: 00100093 li ra,1 + 800003f8: 00700113 li sp,7 + 800003fc: 00209f3b sllw t5,ra,sp + 80000400: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000404: 00200293 li t0,2 + 80000408: fe5216e3 bne tp,t0,800003f4 <test_28+0x4> + 8000040c: 08000e93 li t4,128 + 80000410: 01c00193 li gp,28 + 80000414: 25df1a63 bne t5,t4,80000668 <fail> + +0000000080000418 <test_29>: + 80000418: 00000213 li tp,0 + 8000041c: 00100093 li ra,1 + 80000420: 00e00113 li sp,14 + 80000424: 00000013 nop + 80000428: 00209f3b sllw t5,ra,sp + 8000042c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000430: 00200293 li t0,2 + 80000434: fe5214e3 bne tp,t0,8000041c <test_29+0x4> + 80000438: 00004eb7 lui t4,0x4 + 8000043c: 01d00193 li gp,29 + 80000440: 23df1463 bne t5,t4,80000668 <fail> + +0000000080000444 <test_30>: + 80000444: 00000213 li tp,0 + 80000448: 00100093 li ra,1 + 8000044c: 01f00113 li sp,31 + 80000450: 00000013 nop + 80000454: 00000013 nop + 80000458: 00209f3b sllw t5,ra,sp + 8000045c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000460: 00200293 li t0,2 + 80000464: fe5212e3 bne tp,t0,80000448 <test_30+0x4> + 80000468: 80000eb7 lui t4,0x80000 + 8000046c: 01e00193 li gp,30 + 80000470: 1fdf1c63 bne t5,t4,80000668 <fail> + +0000000080000474 <test_31>: + 80000474: 00000213 li tp,0 + 80000478: 00100093 li ra,1 + 8000047c: 00000013 nop + 80000480: 00700113 li sp,7 + 80000484: 00209f3b sllw t5,ra,sp + 80000488: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000048c: 00200293 li t0,2 + 80000490: fe5214e3 bne tp,t0,80000478 <test_31+0x4> + 80000494: 08000e93 li t4,128 + 80000498: 01f00193 li gp,31 + 8000049c: 1ddf1663 bne t5,t4,80000668 <fail> + +00000000800004a0 <test_32>: + 800004a0: 00000213 li tp,0 + 800004a4: 00100093 li ra,1 + 800004a8: 00000013 nop + 800004ac: 00e00113 li sp,14 + 800004b0: 00000013 nop + 800004b4: 00209f3b sllw t5,ra,sp + 800004b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004bc: 00200293 li t0,2 + 800004c0: fe5212e3 bne tp,t0,800004a4 <test_32+0x4> + 800004c4: 00004eb7 lui t4,0x4 + 800004c8: 02000193 li gp,32 + 800004cc: 19df1e63 bne t5,t4,80000668 <fail> + +00000000800004d0 <test_33>: + 800004d0: 00000213 li tp,0 + 800004d4: 00100093 li ra,1 + 800004d8: 00000013 nop + 800004dc: 00000013 nop + 800004e0: 01f00113 li sp,31 + 800004e4: 00209f3b sllw t5,ra,sp + 800004e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004ec: 00200293 li t0,2 + 800004f0: fe5212e3 bne tp,t0,800004d4 <test_33+0x4> + 800004f4: 80000eb7 lui t4,0x80000 + 800004f8: 02100193 li gp,33 + 800004fc: 17df1663 bne t5,t4,80000668 <fail> + +0000000080000500 <test_34>: + 80000500: 00000213 li tp,0 + 80000504: 00700113 li sp,7 + 80000508: 00100093 li ra,1 + 8000050c: 00209f3b sllw t5,ra,sp + 80000510: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000514: 00200293 li t0,2 + 80000518: fe5216e3 bne tp,t0,80000504 <test_34+0x4> + 8000051c: 08000e93 li t4,128 + 80000520: 02200193 li gp,34 + 80000524: 15df1263 bne t5,t4,80000668 <fail> + +0000000080000528 <test_35>: + 80000528: 00000213 li tp,0 + 8000052c: 00e00113 li sp,14 + 80000530: 00100093 li ra,1 + 80000534: 00000013 nop + 80000538: 00209f3b sllw t5,ra,sp + 8000053c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000540: 00200293 li t0,2 + 80000544: fe5214e3 bne tp,t0,8000052c <test_35+0x4> + 80000548: 00004eb7 lui t4,0x4 + 8000054c: 02300193 li gp,35 + 80000550: 11df1c63 bne t5,t4,80000668 <fail> + +0000000080000554 <test_36>: + 80000554: 00000213 li tp,0 + 80000558: 01f00113 li sp,31 + 8000055c: 00100093 li ra,1 + 80000560: 00000013 nop + 80000564: 00000013 nop + 80000568: 00209f3b sllw t5,ra,sp + 8000056c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000570: 00200293 li t0,2 + 80000574: fe5212e3 bne tp,t0,80000558 <test_36+0x4> + 80000578: 80000eb7 lui t4,0x80000 + 8000057c: 02400193 li gp,36 + 80000580: 0fdf1463 bne t5,t4,80000668 <fail> + +0000000080000584 <test_37>: + 80000584: 00000213 li tp,0 + 80000588: 00700113 li sp,7 + 8000058c: 00000013 nop + 80000590: 00100093 li ra,1 + 80000594: 00209f3b sllw t5,ra,sp + 80000598: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000059c: 00200293 li t0,2 + 800005a0: fe5214e3 bne tp,t0,80000588 <test_37+0x4> + 800005a4: 08000e93 li t4,128 + 800005a8: 02500193 li gp,37 + 800005ac: 0bdf1e63 bne t5,t4,80000668 <fail> + +00000000800005b0 <test_38>: + 800005b0: 00000213 li tp,0 + 800005b4: 00e00113 li sp,14 + 800005b8: 00000013 nop + 800005bc: 00100093 li ra,1 + 800005c0: 00000013 nop + 800005c4: 00209f3b sllw t5,ra,sp + 800005c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005cc: 00200293 li t0,2 + 800005d0: fe5212e3 bne tp,t0,800005b4 <test_38+0x4> + 800005d4: 00004eb7 lui t4,0x4 + 800005d8: 02600193 li gp,38 + 800005dc: 09df1663 bne t5,t4,80000668 <fail> + +00000000800005e0 <test_39>: + 800005e0: 00000213 li tp,0 + 800005e4: 01f00113 li sp,31 + 800005e8: 00000013 nop + 800005ec: 00000013 nop + 800005f0: 00100093 li ra,1 + 800005f4: 00209f3b sllw t5,ra,sp + 800005f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005fc: 00200293 li t0,2 + 80000600: fe5212e3 bne tp,t0,800005e4 <test_39+0x4> + 80000604: 80000eb7 lui t4,0x80000 + 80000608: 02700193 li gp,39 + 8000060c: 05df1e63 bne t5,t4,80000668 <fail> + +0000000080000610 <test_40>: + 80000610: 00f00093 li ra,15 + 80000614: 0010113b sllw sp,zero,ra + 80000618: 00000e93 li t4,0 + 8000061c: 02800193 li gp,40 + 80000620: 05d11463 bne sp,t4,80000668 <fail> + +0000000080000624 <test_41>: + 80000624: 02000093 li ra,32 + 80000628: 0000913b sllw sp,ra,zero + 8000062c: 02000e93 li t4,32 + 80000630: 02900193 li gp,41 + 80000634: 03d11a63 bne sp,t4,80000668 <fail> + +0000000080000638 <test_42>: + 80000638: 000010bb sllw ra,zero,zero + 8000063c: 00000e93 li t4,0 + 80000640: 02a00193 li gp,42 + 80000644: 03d09263 bne ra,t4,80000668 <fail> + +0000000080000648 <test_43>: + 80000648: 40000093 li ra,1024 + 8000064c: 00001137 lui sp,0x1 + 80000650: 8001011b addiw sp,sp,-2048 + 80000654: 0020903b sllw zero,ra,sp + 80000658: 00000e93 li t4,0 + 8000065c: 02b00193 li gp,43 + 80000660: 01d01463 bne zero,t4,80000668 <fail> + 80000664: 00301c63 bne zero,gp,8000067c <pass> + +0000000080000668 <fail>: + 80000668: 0ff0000f fence + 8000066c: 00018063 beqz gp,8000066c <fail+0x4> + 80000670: 00119193 slli gp,gp,0x1 + 80000674: 0011e193 ori gp,gp,1 + 80000678: 00000073 ecall + +000000008000067c <pass>: + 8000067c: 0ff0000f fence + 80000680: 00100193 li gp,1 + 80000684: 00000073 ecall + 80000688: c0001073 unimp + 8000068c: 0000 unimp + 8000068e: 0000 unimp + 80000690: 0000 unimp + 80000692: 0000 unimp + 80000694: 0000 unimp + 80000696: 0000 unimp + 80000698: 0000 unimp + 8000069a: 0000 unimp + 8000069c: 0000 unimp + 8000069e: 0000 unimp + 800006a0: 0000 unimp + 800006a2: 0000 unimp + 800006a4: 0000 unimp + 800006a6: 0000 unimp + 800006a8: 0000 unimp + 800006aa: 0000 unimp + 800006ac: 0000 unimp + 800006ae: 0000 unimp + 800006b0: 0000 unimp + 800006b2: 0000 unimp + 800006b4: 0000 unimp + 800006b6: 0000 unimp + 800006b8: 0000 unimp + 800006ba: 0000 unimp + 800006bc: 0000 unimp + 800006be: 0000 unimp + 800006c0: 0000 unimp + 800006c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sllw.elf b/test/riscv/tests/rv64ui-p-sllw.elf Binary files differnew file mode 100755 index 00000000..b722e66c --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sllw.elf diff --git a/test/riscv/tests/rv64ui-p-slt.dump b/test/riscv/tests/rv64ui-p-slt.dump new file mode 100644 index 00000000..1d5f786e --- /dev/null +++ b/test/riscv/tests/rv64ui-p-slt.dump @@ -0,0 +1,485 @@ + +rv64ui-p-slt: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 00000113 li sp,0 + 80000104: 0020af33 slt t5,ra,sp + 80000108: 00000e93 li t4,0 + 8000010c: 00200193 li gp,2 + 80000110: 4bdf1a63 bne t5,t4,800005c4 <fail> + +0000000080000114 <test_3>: + 80000114: 00100093 li ra,1 + 80000118: 00100113 li sp,1 + 8000011c: 0020af33 slt t5,ra,sp + 80000120: 00000e93 li t4,0 + 80000124: 00300193 li gp,3 + 80000128: 49df1e63 bne t5,t4,800005c4 <fail> + +000000008000012c <test_4>: + 8000012c: 00300093 li ra,3 + 80000130: 00700113 li sp,7 + 80000134: 0020af33 slt t5,ra,sp + 80000138: 00100e93 li t4,1 + 8000013c: 00400193 li gp,4 + 80000140: 49df1263 bne t5,t4,800005c4 <fail> + +0000000080000144 <test_5>: + 80000144: 00700093 li ra,7 + 80000148: 00300113 li sp,3 + 8000014c: 0020af33 slt t5,ra,sp + 80000150: 00000e93 li t4,0 + 80000154: 00500193 li gp,5 + 80000158: 47df1663 bne t5,t4,800005c4 <fail> + +000000008000015c <test_6>: + 8000015c: 00000093 li ra,0 + 80000160: ffff8137 lui sp,0xffff8 + 80000164: 0020af33 slt t5,ra,sp + 80000168: 00000e93 li t4,0 + 8000016c: 00600193 li gp,6 + 80000170: 45df1a63 bne t5,t4,800005c4 <fail> + +0000000080000174 <test_7>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: 00000113 li sp,0 + 8000017c: 0020af33 slt t5,ra,sp + 80000180: 00100e93 li t4,1 + 80000184: 00700193 li gp,7 + 80000188: 43df1e63 bne t5,t4,800005c4 <fail> + +000000008000018c <test_8>: + 8000018c: 800000b7 lui ra,0x80000 + 80000190: ffff8137 lui sp,0xffff8 + 80000194: 0020af33 slt t5,ra,sp + 80000198: 00100e93 li t4,1 + 8000019c: 00800193 li gp,8 + 800001a0: 43df1263 bne t5,t4,800005c4 <fail> + +00000000800001a4 <test_9>: + 800001a4: 00000093 li ra,0 + 800001a8: 00008137 lui sp,0x8 + 800001ac: fff1011b addiw sp,sp,-1 + 800001b0: 0020af33 slt t5,ra,sp + 800001b4: 00100e93 li t4,1 + 800001b8: 00900193 li gp,9 + 800001bc: 41df1463 bne t5,t4,800005c4 <fail> + +00000000800001c0 <test_10>: + 800001c0: 800000b7 lui ra,0x80000 + 800001c4: fff0809b addiw ra,ra,-1 + 800001c8: 00000113 li sp,0 + 800001cc: 0020af33 slt t5,ra,sp + 800001d0: 00000e93 li t4,0 + 800001d4: 00a00193 li gp,10 + 800001d8: 3fdf1663 bne t5,t4,800005c4 <fail> + +00000000800001dc <test_11>: + 800001dc: 800000b7 lui ra,0x80000 + 800001e0: fff0809b addiw ra,ra,-1 + 800001e4: 00008137 lui sp,0x8 + 800001e8: fff1011b addiw sp,sp,-1 + 800001ec: 0020af33 slt t5,ra,sp + 800001f0: 00000e93 li t4,0 + 800001f4: 00b00193 li gp,11 + 800001f8: 3ddf1663 bne t5,t4,800005c4 <fail> + +00000000800001fc <test_12>: + 800001fc: 800000b7 lui ra,0x80000 + 80000200: 00008137 lui sp,0x8 + 80000204: fff1011b addiw sp,sp,-1 + 80000208: 0020af33 slt t5,ra,sp + 8000020c: 00100e93 li t4,1 + 80000210: 00c00193 li gp,12 + 80000214: 3bdf1863 bne t5,t4,800005c4 <fail> + +0000000080000218 <test_13>: + 80000218: 800000b7 lui ra,0x80000 + 8000021c: fff0809b addiw ra,ra,-1 + 80000220: ffff8137 lui sp,0xffff8 + 80000224: 0020af33 slt t5,ra,sp + 80000228: 00000e93 li t4,0 + 8000022c: 00d00193 li gp,13 + 80000230: 39df1a63 bne t5,t4,800005c4 <fail> + +0000000080000234 <test_14>: + 80000234: 00000093 li ra,0 + 80000238: fff00113 li sp,-1 + 8000023c: 0020af33 slt t5,ra,sp + 80000240: 00000e93 li t4,0 + 80000244: 00e00193 li gp,14 + 80000248: 37df1e63 bne t5,t4,800005c4 <fail> + +000000008000024c <test_15>: + 8000024c: fff00093 li ra,-1 + 80000250: 00100113 li sp,1 + 80000254: 0020af33 slt t5,ra,sp + 80000258: 00100e93 li t4,1 + 8000025c: 00f00193 li gp,15 + 80000260: 37df1263 bne t5,t4,800005c4 <fail> + +0000000080000264 <test_16>: + 80000264: fff00093 li ra,-1 + 80000268: fff00113 li sp,-1 + 8000026c: 0020af33 slt t5,ra,sp + 80000270: 00000e93 li t4,0 + 80000274: 01000193 li gp,16 + 80000278: 35df1663 bne t5,t4,800005c4 <fail> + +000000008000027c <test_17>: + 8000027c: 00e00093 li ra,14 + 80000280: 00d00113 li sp,13 + 80000284: 0020a0b3 slt ra,ra,sp + 80000288: 00000e93 li t4,0 + 8000028c: 01100193 li gp,17 + 80000290: 33d09a63 bne ra,t4,800005c4 <fail> + +0000000080000294 <test_18>: + 80000294: 00b00093 li ra,11 + 80000298: 00d00113 li sp,13 + 8000029c: 0020a133 slt sp,ra,sp + 800002a0: 00100e93 li t4,1 + 800002a4: 01200193 li gp,18 + 800002a8: 31d11e63 bne sp,t4,800005c4 <fail> + +00000000800002ac <test_19>: + 800002ac: 00d00093 li ra,13 + 800002b0: 0010a0b3 slt ra,ra,ra + 800002b4: 00000e93 li t4,0 + 800002b8: 01300193 li gp,19 + 800002bc: 31d09463 bne ra,t4,800005c4 <fail> + +00000000800002c0 <test_20>: + 800002c0: 00000213 li tp,0 + 800002c4: 00b00093 li ra,11 + 800002c8: 00d00113 li sp,13 + 800002cc: 0020af33 slt t5,ra,sp + 800002d0: 000f0313 mv t1,t5 + 800002d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002d8: 00200293 li t0,2 + 800002dc: fe5214e3 bne tp,t0,800002c4 <test_20+0x4> + 800002e0: 00100e93 li t4,1 + 800002e4: 01400193 li gp,20 + 800002e8: 2dd31e63 bne t1,t4,800005c4 <fail> + +00000000800002ec <test_21>: + 800002ec: 00000213 li tp,0 + 800002f0: 00e00093 li ra,14 + 800002f4: 00d00113 li sp,13 + 800002f8: 0020af33 slt t5,ra,sp + 800002fc: 00000013 nop + 80000300: 000f0313 mv t1,t5 + 80000304: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000308: 00200293 li t0,2 + 8000030c: fe5212e3 bne tp,t0,800002f0 <test_21+0x4> + 80000310: 00000e93 li t4,0 + 80000314: 01500193 li gp,21 + 80000318: 2bd31663 bne t1,t4,800005c4 <fail> + +000000008000031c <test_22>: + 8000031c: 00000213 li tp,0 + 80000320: 00c00093 li ra,12 + 80000324: 00d00113 li sp,13 + 80000328: 0020af33 slt t5,ra,sp + 8000032c: 00000013 nop + 80000330: 00000013 nop + 80000334: 000f0313 mv t1,t5 + 80000338: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000033c: 00200293 li t0,2 + 80000340: fe5210e3 bne tp,t0,80000320 <test_22+0x4> + 80000344: 00100e93 li t4,1 + 80000348: 01600193 li gp,22 + 8000034c: 27d31c63 bne t1,t4,800005c4 <fail> + +0000000080000350 <test_23>: + 80000350: 00000213 li tp,0 + 80000354: 00e00093 li ra,14 + 80000358: 00d00113 li sp,13 + 8000035c: 0020af33 slt t5,ra,sp + 80000360: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000364: 00200293 li t0,2 + 80000368: fe5216e3 bne tp,t0,80000354 <test_23+0x4> + 8000036c: 00000e93 li t4,0 + 80000370: 01700193 li gp,23 + 80000374: 25df1863 bne t5,t4,800005c4 <fail> + +0000000080000378 <test_24>: + 80000378: 00000213 li tp,0 + 8000037c: 00b00093 li ra,11 + 80000380: 00d00113 li sp,13 + 80000384: 00000013 nop + 80000388: 0020af33 slt t5,ra,sp + 8000038c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000390: 00200293 li t0,2 + 80000394: fe5214e3 bne tp,t0,8000037c <test_24+0x4> + 80000398: 00100e93 li t4,1 + 8000039c: 01800193 li gp,24 + 800003a0: 23df1263 bne t5,t4,800005c4 <fail> + +00000000800003a4 <test_25>: + 800003a4: 00000213 li tp,0 + 800003a8: 00f00093 li ra,15 + 800003ac: 00d00113 li sp,13 + 800003b0: 00000013 nop + 800003b4: 00000013 nop + 800003b8: 0020af33 slt t5,ra,sp + 800003bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003c0: 00200293 li t0,2 + 800003c4: fe5212e3 bne tp,t0,800003a8 <test_25+0x4> + 800003c8: 00000e93 li t4,0 + 800003cc: 01900193 li gp,25 + 800003d0: 1fdf1a63 bne t5,t4,800005c4 <fail> + +00000000800003d4 <test_26>: + 800003d4: 00000213 li tp,0 + 800003d8: 00a00093 li ra,10 + 800003dc: 00000013 nop + 800003e0: 00d00113 li sp,13 + 800003e4: 0020af33 slt t5,ra,sp + 800003e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003ec: 00200293 li t0,2 + 800003f0: fe5214e3 bne tp,t0,800003d8 <test_26+0x4> + 800003f4: 00100e93 li t4,1 + 800003f8: 01a00193 li gp,26 + 800003fc: 1ddf1463 bne t5,t4,800005c4 <fail> + +0000000080000400 <test_27>: + 80000400: 00000213 li tp,0 + 80000404: 01000093 li ra,16 + 80000408: 00000013 nop + 8000040c: 00d00113 li sp,13 + 80000410: 00000013 nop + 80000414: 0020af33 slt t5,ra,sp + 80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000041c: 00200293 li t0,2 + 80000420: fe5212e3 bne tp,t0,80000404 <test_27+0x4> + 80000424: 00000e93 li t4,0 + 80000428: 01b00193 li gp,27 + 8000042c: 19df1c63 bne t5,t4,800005c4 <fail> + +0000000080000430 <test_28>: + 80000430: 00000213 li tp,0 + 80000434: 00900093 li ra,9 + 80000438: 00000013 nop + 8000043c: 00000013 nop + 80000440: 00d00113 li sp,13 + 80000444: 0020af33 slt t5,ra,sp + 80000448: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000044c: 00200293 li t0,2 + 80000450: fe5212e3 bne tp,t0,80000434 <test_28+0x4> + 80000454: 00100e93 li t4,1 + 80000458: 01c00193 li gp,28 + 8000045c: 17df1463 bne t5,t4,800005c4 <fail> + +0000000080000460 <test_29>: + 80000460: 00000213 li tp,0 + 80000464: 00d00113 li sp,13 + 80000468: 01100093 li ra,17 + 8000046c: 0020af33 slt t5,ra,sp + 80000470: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000474: 00200293 li t0,2 + 80000478: fe5216e3 bne tp,t0,80000464 <test_29+0x4> + 8000047c: 00000e93 li t4,0 + 80000480: 01d00193 li gp,29 + 80000484: 15df1063 bne t5,t4,800005c4 <fail> + +0000000080000488 <test_30>: + 80000488: 00000213 li tp,0 + 8000048c: 00d00113 li sp,13 + 80000490: 00800093 li ra,8 + 80000494: 00000013 nop + 80000498: 0020af33 slt t5,ra,sp + 8000049c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004a0: 00200293 li t0,2 + 800004a4: fe5214e3 bne tp,t0,8000048c <test_30+0x4> + 800004a8: 00100e93 li t4,1 + 800004ac: 01e00193 li gp,30 + 800004b0: 11df1a63 bne t5,t4,800005c4 <fail> + +00000000800004b4 <test_31>: + 800004b4: 00000213 li tp,0 + 800004b8: 00d00113 li sp,13 + 800004bc: 01200093 li ra,18 + 800004c0: 00000013 nop + 800004c4: 00000013 nop + 800004c8: 0020af33 slt t5,ra,sp + 800004cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004d0: 00200293 li t0,2 + 800004d4: fe5212e3 bne tp,t0,800004b8 <test_31+0x4> + 800004d8: 00000e93 li t4,0 + 800004dc: 01f00193 li gp,31 + 800004e0: 0fdf1263 bne t5,t4,800005c4 <fail> + +00000000800004e4 <test_32>: + 800004e4: 00000213 li tp,0 + 800004e8: 00d00113 li sp,13 + 800004ec: 00000013 nop + 800004f0: 00700093 li ra,7 + 800004f4: 0020af33 slt t5,ra,sp + 800004f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004fc: 00200293 li t0,2 + 80000500: fe5214e3 bne tp,t0,800004e8 <test_32+0x4> + 80000504: 00100e93 li t4,1 + 80000508: 02000193 li gp,32 + 8000050c: 0bdf1c63 bne t5,t4,800005c4 <fail> + +0000000080000510 <test_33>: + 80000510: 00000213 li tp,0 + 80000514: 00d00113 li sp,13 + 80000518: 00000013 nop + 8000051c: 01300093 li ra,19 + 80000520: 00000013 nop + 80000524: 0020af33 slt t5,ra,sp + 80000528: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000052c: 00200293 li t0,2 + 80000530: fe5212e3 bne tp,t0,80000514 <test_33+0x4> + 80000534: 00000e93 li t4,0 + 80000538: 02100193 li gp,33 + 8000053c: 09df1463 bne t5,t4,800005c4 <fail> + +0000000080000540 <test_34>: + 80000540: 00000213 li tp,0 + 80000544: 00d00113 li sp,13 + 80000548: 00000013 nop + 8000054c: 00000013 nop + 80000550: 00600093 li ra,6 + 80000554: 0020af33 slt t5,ra,sp + 80000558: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000055c: 00200293 li t0,2 + 80000560: fe5212e3 bne tp,t0,80000544 <test_34+0x4> + 80000564: 00100e93 li t4,1 + 80000568: 02200193 li gp,34 + 8000056c: 05df1c63 bne t5,t4,800005c4 <fail> + +0000000080000570 <test_35>: + 80000570: fff00093 li ra,-1 + 80000574: 00102133 sgtz sp,ra + 80000578: 00000e93 li t4,0 + 8000057c: 02300193 li gp,35 + 80000580: 05d11263 bne sp,t4,800005c4 <fail> + +0000000080000584 <test_36>: + 80000584: fff00093 li ra,-1 + 80000588: 0000a133 sltz sp,ra + 8000058c: 00100e93 li t4,1 + 80000590: 02400193 li gp,36 + 80000594: 03d11863 bne sp,t4,800005c4 <fail> + +0000000080000598 <test_37>: + 80000598: 000020b3 sltz ra,zero + 8000059c: 00000e93 li t4,0 + 800005a0: 02500193 li gp,37 + 800005a4: 03d09063 bne ra,t4,800005c4 <fail> + +00000000800005a8 <test_38>: + 800005a8: 01000093 li ra,16 + 800005ac: 01e00113 li sp,30 + 800005b0: 0020a033 slt zero,ra,sp + 800005b4: 00000e93 li t4,0 + 800005b8: 02600193 li gp,38 + 800005bc: 01d01463 bne zero,t4,800005c4 <fail> + 800005c0: 00301c63 bne zero,gp,800005d8 <pass> + +00000000800005c4 <fail>: + 800005c4: 0ff0000f fence + 800005c8: 00018063 beqz gp,800005c8 <fail+0x4> + 800005cc: 00119193 slli gp,gp,0x1 + 800005d0: 0011e193 ori gp,gp,1 + 800005d4: 00000073 ecall + +00000000800005d8 <pass>: + 800005d8: 0ff0000f fence + 800005dc: 00100193 li gp,1 + 800005e0: 00000073 ecall + 800005e4: c0001073 unimp + 800005e8: 0000 unimp + 800005ea: 0000 unimp + 800005ec: 0000 unimp + 800005ee: 0000 unimp + 800005f0: 0000 unimp + 800005f2: 0000 unimp + 800005f4: 0000 unimp + 800005f6: 0000 unimp + 800005f8: 0000 unimp + 800005fa: 0000 unimp + 800005fc: 0000 unimp + 800005fe: 0000 unimp + 80000600: 0000 unimp + 80000602: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-slt.elf b/test/riscv/tests/rv64ui-p-slt.elf Binary files differnew file mode 100755 index 00000000..d5e3ee14 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-slt.elf diff --git a/test/riscv/tests/rv64ui-p-slti.dump b/test/riscv/tests/rv64ui-p-slti.dump new file mode 100644 index 00000000..c9ca449a --- /dev/null +++ b/test/riscv/tests/rv64ui-p-slti.dump @@ -0,0 +1,320 @@ + +rv64ui-p-slti: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 0000af13 slti t5,ra,0 + 80000104: 00000e93 li t4,0 + 80000108: 00200193 li gp,2 + 8000010c: 27df1263 bne t5,t4,80000370 <fail> + +0000000080000110 <test_3>: + 80000110: 00100093 li ra,1 + 80000114: 0010af13 slti t5,ra,1 + 80000118: 00000e93 li t4,0 + 8000011c: 00300193 li gp,3 + 80000120: 25df1863 bne t5,t4,80000370 <fail> + +0000000080000124 <test_4>: + 80000124: 00300093 li ra,3 + 80000128: 0070af13 slti t5,ra,7 + 8000012c: 00100e93 li t4,1 + 80000130: 00400193 li gp,4 + 80000134: 23df1e63 bne t5,t4,80000370 <fail> + +0000000080000138 <test_5>: + 80000138: 00700093 li ra,7 + 8000013c: 0030af13 slti t5,ra,3 + 80000140: 00000e93 li t4,0 + 80000144: 00500193 li gp,5 + 80000148: 23df1463 bne t5,t4,80000370 <fail> + +000000008000014c <test_6>: + 8000014c: 00000093 li ra,0 + 80000150: 8000af13 slti t5,ra,-2048 + 80000154: 00000e93 li t4,0 + 80000158: 00600193 li gp,6 + 8000015c: 21df1a63 bne t5,t4,80000370 <fail> + +0000000080000160 <test_7>: + 80000160: 800000b7 lui ra,0x80000 + 80000164: 0000af13 slti t5,ra,0 + 80000168: 00100e93 li t4,1 + 8000016c: 00700193 li gp,7 + 80000170: 21df1063 bne t5,t4,80000370 <fail> + +0000000080000174 <test_8>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: 8000af13 slti t5,ra,-2048 + 8000017c: 00100e93 li t4,1 + 80000180: 00800193 li gp,8 + 80000184: 1fdf1663 bne t5,t4,80000370 <fail> + +0000000080000188 <test_9>: + 80000188: 00000093 li ra,0 + 8000018c: 7ff0af13 slti t5,ra,2047 + 80000190: 00100e93 li t4,1 + 80000194: 00900193 li gp,9 + 80000198: 1ddf1c63 bne t5,t4,80000370 <fail> + +000000008000019c <test_10>: + 8000019c: 800000b7 lui ra,0x80000 + 800001a0: fff0809b addiw ra,ra,-1 + 800001a4: 0000af13 slti t5,ra,0 + 800001a8: 00000e93 li t4,0 + 800001ac: 00a00193 li gp,10 + 800001b0: 1ddf1063 bne t5,t4,80000370 <fail> + +00000000800001b4 <test_11>: + 800001b4: 800000b7 lui ra,0x80000 + 800001b8: fff0809b addiw ra,ra,-1 + 800001bc: 7ff0af13 slti t5,ra,2047 + 800001c0: 00000e93 li t4,0 + 800001c4: 00b00193 li gp,11 + 800001c8: 1bdf1463 bne t5,t4,80000370 <fail> + +00000000800001cc <test_12>: + 800001cc: 800000b7 lui ra,0x80000 + 800001d0: 7ff0af13 slti t5,ra,2047 + 800001d4: 00100e93 li t4,1 + 800001d8: 00c00193 li gp,12 + 800001dc: 19df1a63 bne t5,t4,80000370 <fail> + +00000000800001e0 <test_13>: + 800001e0: 800000b7 lui ra,0x80000 + 800001e4: fff0809b addiw ra,ra,-1 + 800001e8: 8000af13 slti t5,ra,-2048 + 800001ec: 00000e93 li t4,0 + 800001f0: 00d00193 li gp,13 + 800001f4: 17df1e63 bne t5,t4,80000370 <fail> + +00000000800001f8 <test_14>: + 800001f8: 00000093 li ra,0 + 800001fc: fff0af13 slti t5,ra,-1 + 80000200: 00000e93 li t4,0 + 80000204: 00e00193 li gp,14 + 80000208: 17df1463 bne t5,t4,80000370 <fail> + +000000008000020c <test_15>: + 8000020c: fff00093 li ra,-1 + 80000210: 0010af13 slti t5,ra,1 + 80000214: 00100e93 li t4,1 + 80000218: 00f00193 li gp,15 + 8000021c: 15df1a63 bne t5,t4,80000370 <fail> + +0000000080000220 <test_16>: + 80000220: fff00093 li ra,-1 + 80000224: fff0af13 slti t5,ra,-1 + 80000228: 00000e93 li t4,0 + 8000022c: 01000193 li gp,16 + 80000230: 15df1063 bne t5,t4,80000370 <fail> + +0000000080000234 <test_17>: + 80000234: 00b00093 li ra,11 + 80000238: 00d0a093 slti ra,ra,13 + 8000023c: 00100e93 li t4,1 + 80000240: 01100193 li gp,17 + 80000244: 13d09663 bne ra,t4,80000370 <fail> + +0000000080000248 <test_18>: + 80000248: 00000213 li tp,0 + 8000024c: 00f00093 li ra,15 + 80000250: 00a0af13 slti t5,ra,10 + 80000254: 000f0313 mv t1,t5 + 80000258: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000025c: 00200293 li t0,2 + 80000260: fe5216e3 bne tp,t0,8000024c <test_18+0x4> + 80000264: 00000e93 li t4,0 + 80000268: 01200193 li gp,18 + 8000026c: 11d31263 bne t1,t4,80000370 <fail> + +0000000080000270 <test_19>: + 80000270: 00000213 li tp,0 + 80000274: 00a00093 li ra,10 + 80000278: 0100af13 slti t5,ra,16 + 8000027c: 00000013 nop + 80000280: 000f0313 mv t1,t5 + 80000284: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000288: 00200293 li t0,2 + 8000028c: fe5214e3 bne tp,t0,80000274 <test_19+0x4> + 80000290: 00100e93 li t4,1 + 80000294: 01300193 li gp,19 + 80000298: 0dd31c63 bne t1,t4,80000370 <fail> + +000000008000029c <test_20>: + 8000029c: 00000213 li tp,0 + 800002a0: 01000093 li ra,16 + 800002a4: 0090af13 slti t5,ra,9 + 800002a8: 00000013 nop + 800002ac: 00000013 nop + 800002b0: 000f0313 mv t1,t5 + 800002b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002b8: 00200293 li t0,2 + 800002bc: fe5212e3 bne tp,t0,800002a0 <test_20+0x4> + 800002c0: 00000e93 li t4,0 + 800002c4: 01400193 li gp,20 + 800002c8: 0bd31463 bne t1,t4,80000370 <fail> + +00000000800002cc <test_21>: + 800002cc: 00000213 li tp,0 + 800002d0: 00b00093 li ra,11 + 800002d4: 00f0af13 slti t5,ra,15 + 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002dc: 00200293 li t0,2 + 800002e0: fe5218e3 bne tp,t0,800002d0 <test_21+0x4> + 800002e4: 00100e93 li t4,1 + 800002e8: 01500193 li gp,21 + 800002ec: 09df1263 bne t5,t4,80000370 <fail> + +00000000800002f0 <test_22>: + 800002f0: 00000213 li tp,0 + 800002f4: 01100093 li ra,17 + 800002f8: 00000013 nop + 800002fc: 0080af13 slti t5,ra,8 + 80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000304: 00200293 li t0,2 + 80000308: fe5216e3 bne tp,t0,800002f4 <test_22+0x4> + 8000030c: 00000e93 li t4,0 + 80000310: 01600193 li gp,22 + 80000314: 05df1e63 bne t5,t4,80000370 <fail> + +0000000080000318 <test_23>: + 80000318: 00000213 li tp,0 + 8000031c: 00c00093 li ra,12 + 80000320: 00000013 nop + 80000324: 00000013 nop + 80000328: 00e0af13 slti t5,ra,14 + 8000032c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000330: 00200293 li t0,2 + 80000334: fe5214e3 bne tp,t0,8000031c <test_23+0x4> + 80000338: 00100e93 li t4,1 + 8000033c: 01700193 li gp,23 + 80000340: 03df1863 bne t5,t4,80000370 <fail> + +0000000080000344 <test_24>: + 80000344: fff02093 slti ra,zero,-1 + 80000348: 00000e93 li t4,0 + 8000034c: 01800193 li gp,24 + 80000350: 03d09063 bne ra,t4,80000370 <fail> + +0000000080000354 <test_25>: + 80000354: 00ff00b7 lui ra,0xff0 + 80000358: 0ff0809b addiw ra,ra,255 + 8000035c: fff0a013 slti zero,ra,-1 + 80000360: 00000e93 li t4,0 + 80000364: 01900193 li gp,25 + 80000368: 01d01463 bne zero,t4,80000370 <fail> + 8000036c: 00301c63 bne zero,gp,80000384 <pass> + +0000000080000370 <fail>: + 80000370: 0ff0000f fence + 80000374: 00018063 beqz gp,80000374 <fail+0x4> + 80000378: 00119193 slli gp,gp,0x1 + 8000037c: 0011e193 ori gp,gp,1 + 80000380: 00000073 ecall + +0000000080000384 <pass>: + 80000384: 0ff0000f fence + 80000388: 00100193 li gp,1 + 8000038c: 00000073 ecall + 80000390: c0001073 unimp + 80000394: 0000 unimp + 80000396: 0000 unimp + 80000398: 0000 unimp + 8000039a: 0000 unimp + 8000039c: 0000 unimp + 8000039e: 0000 unimp + 800003a0: 0000 unimp + 800003a2: 0000 unimp + 800003a4: 0000 unimp + 800003a6: 0000 unimp + 800003a8: 0000 unimp + 800003aa: 0000 unimp + 800003ac: 0000 unimp + 800003ae: 0000 unimp + 800003b0: 0000 unimp + 800003b2: 0000 unimp + 800003b4: 0000 unimp + 800003b6: 0000 unimp + 800003b8: 0000 unimp + 800003ba: 0000 unimp + 800003bc: 0000 unimp + 800003be: 0000 unimp + 800003c0: 0000 unimp + 800003c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-slti.elf b/test/riscv/tests/rv64ui-p-slti.elf Binary files differnew file mode 100755 index 00000000..3dbb9dcf --- /dev/null +++ b/test/riscv/tests/rv64ui-p-slti.elf diff --git a/test/riscv/tests/rv64ui-p-sltiu.dump b/test/riscv/tests/rv64ui-p-sltiu.dump new file mode 100644 index 00000000..45fe6ab3 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sltiu.dump @@ -0,0 +1,320 @@ + +rv64ui-p-sltiu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 0000bf13 sltiu t5,ra,0 + 80000104: 00000e93 li t4,0 + 80000108: 00200193 li gp,2 + 8000010c: 27df1263 bne t5,t4,80000370 <fail> + +0000000080000110 <test_3>: + 80000110: 00100093 li ra,1 + 80000114: 0010bf13 seqz t5,ra + 80000118: 00000e93 li t4,0 + 8000011c: 00300193 li gp,3 + 80000120: 25df1863 bne t5,t4,80000370 <fail> + +0000000080000124 <test_4>: + 80000124: 00300093 li ra,3 + 80000128: 0070bf13 sltiu t5,ra,7 + 8000012c: 00100e93 li t4,1 + 80000130: 00400193 li gp,4 + 80000134: 23df1e63 bne t5,t4,80000370 <fail> + +0000000080000138 <test_5>: + 80000138: 00700093 li ra,7 + 8000013c: 0030bf13 sltiu t5,ra,3 + 80000140: 00000e93 li t4,0 + 80000144: 00500193 li gp,5 + 80000148: 23df1463 bne t5,t4,80000370 <fail> + +000000008000014c <test_6>: + 8000014c: 00000093 li ra,0 + 80000150: 8000bf13 sltiu t5,ra,-2048 + 80000154: 00100e93 li t4,1 + 80000158: 00600193 li gp,6 + 8000015c: 21df1a63 bne t5,t4,80000370 <fail> + +0000000080000160 <test_7>: + 80000160: 800000b7 lui ra,0x80000 + 80000164: 0000bf13 sltiu t5,ra,0 + 80000168: 00000e93 li t4,0 + 8000016c: 00700193 li gp,7 + 80000170: 21df1063 bne t5,t4,80000370 <fail> + +0000000080000174 <test_8>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: 8000bf13 sltiu t5,ra,-2048 + 8000017c: 00100e93 li t4,1 + 80000180: 00800193 li gp,8 + 80000184: 1fdf1663 bne t5,t4,80000370 <fail> + +0000000080000188 <test_9>: + 80000188: 00000093 li ra,0 + 8000018c: 7ff0bf13 sltiu t5,ra,2047 + 80000190: 00100e93 li t4,1 + 80000194: 00900193 li gp,9 + 80000198: 1ddf1c63 bne t5,t4,80000370 <fail> + +000000008000019c <test_10>: + 8000019c: 800000b7 lui ra,0x80000 + 800001a0: fff0809b addiw ra,ra,-1 + 800001a4: 0000bf13 sltiu t5,ra,0 + 800001a8: 00000e93 li t4,0 + 800001ac: 00a00193 li gp,10 + 800001b0: 1ddf1063 bne t5,t4,80000370 <fail> + +00000000800001b4 <test_11>: + 800001b4: 800000b7 lui ra,0x80000 + 800001b8: fff0809b addiw ra,ra,-1 + 800001bc: 7ff0bf13 sltiu t5,ra,2047 + 800001c0: 00000e93 li t4,0 + 800001c4: 00b00193 li gp,11 + 800001c8: 1bdf1463 bne t5,t4,80000370 <fail> + +00000000800001cc <test_12>: + 800001cc: 800000b7 lui ra,0x80000 + 800001d0: 7ff0bf13 sltiu t5,ra,2047 + 800001d4: 00000e93 li t4,0 + 800001d8: 00c00193 li gp,12 + 800001dc: 19df1a63 bne t5,t4,80000370 <fail> + +00000000800001e0 <test_13>: + 800001e0: 800000b7 lui ra,0x80000 + 800001e4: fff0809b addiw ra,ra,-1 + 800001e8: 8000bf13 sltiu t5,ra,-2048 + 800001ec: 00100e93 li t4,1 + 800001f0: 00d00193 li gp,13 + 800001f4: 17df1e63 bne t5,t4,80000370 <fail> + +00000000800001f8 <test_14>: + 800001f8: 00000093 li ra,0 + 800001fc: fff0bf13 sltiu t5,ra,-1 + 80000200: 00100e93 li t4,1 + 80000204: 00e00193 li gp,14 + 80000208: 17df1463 bne t5,t4,80000370 <fail> + +000000008000020c <test_15>: + 8000020c: fff00093 li ra,-1 + 80000210: 0010bf13 seqz t5,ra + 80000214: 00000e93 li t4,0 + 80000218: 00f00193 li gp,15 + 8000021c: 15df1a63 bne t5,t4,80000370 <fail> + +0000000080000220 <test_16>: + 80000220: fff00093 li ra,-1 + 80000224: fff0bf13 sltiu t5,ra,-1 + 80000228: 00000e93 li t4,0 + 8000022c: 01000193 li gp,16 + 80000230: 15df1063 bne t5,t4,80000370 <fail> + +0000000080000234 <test_17>: + 80000234: 00b00093 li ra,11 + 80000238: 00d0b093 sltiu ra,ra,13 + 8000023c: 00100e93 li t4,1 + 80000240: 01100193 li gp,17 + 80000244: 13d09663 bne ra,t4,80000370 <fail> + +0000000080000248 <test_18>: + 80000248: 00000213 li tp,0 + 8000024c: 00f00093 li ra,15 + 80000250: 00a0bf13 sltiu t5,ra,10 + 80000254: 000f0313 mv t1,t5 + 80000258: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000025c: 00200293 li t0,2 + 80000260: fe5216e3 bne tp,t0,8000024c <test_18+0x4> + 80000264: 00000e93 li t4,0 + 80000268: 01200193 li gp,18 + 8000026c: 11d31263 bne t1,t4,80000370 <fail> + +0000000080000270 <test_19>: + 80000270: 00000213 li tp,0 + 80000274: 00a00093 li ra,10 + 80000278: 0100bf13 sltiu t5,ra,16 + 8000027c: 00000013 nop + 80000280: 000f0313 mv t1,t5 + 80000284: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000288: 00200293 li t0,2 + 8000028c: fe5214e3 bne tp,t0,80000274 <test_19+0x4> + 80000290: 00100e93 li t4,1 + 80000294: 01300193 li gp,19 + 80000298: 0dd31c63 bne t1,t4,80000370 <fail> + +000000008000029c <test_20>: + 8000029c: 00000213 li tp,0 + 800002a0: 01000093 li ra,16 + 800002a4: 0090bf13 sltiu t5,ra,9 + 800002a8: 00000013 nop + 800002ac: 00000013 nop + 800002b0: 000f0313 mv t1,t5 + 800002b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002b8: 00200293 li t0,2 + 800002bc: fe5212e3 bne tp,t0,800002a0 <test_20+0x4> + 800002c0: 00000e93 li t4,0 + 800002c4: 01400193 li gp,20 + 800002c8: 0bd31463 bne t1,t4,80000370 <fail> + +00000000800002cc <test_21>: + 800002cc: 00000213 li tp,0 + 800002d0: 00b00093 li ra,11 + 800002d4: 00f0bf13 sltiu t5,ra,15 + 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002dc: 00200293 li t0,2 + 800002e0: fe5218e3 bne tp,t0,800002d0 <test_21+0x4> + 800002e4: 00100e93 li t4,1 + 800002e8: 01500193 li gp,21 + 800002ec: 09df1263 bne t5,t4,80000370 <fail> + +00000000800002f0 <test_22>: + 800002f0: 00000213 li tp,0 + 800002f4: 01100093 li ra,17 + 800002f8: 00000013 nop + 800002fc: 0080bf13 sltiu t5,ra,8 + 80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000304: 00200293 li t0,2 + 80000308: fe5216e3 bne tp,t0,800002f4 <test_22+0x4> + 8000030c: 00000e93 li t4,0 + 80000310: 01600193 li gp,22 + 80000314: 05df1e63 bne t5,t4,80000370 <fail> + +0000000080000318 <test_23>: + 80000318: 00000213 li tp,0 + 8000031c: 00c00093 li ra,12 + 80000320: 00000013 nop + 80000324: 00000013 nop + 80000328: 00e0bf13 sltiu t5,ra,14 + 8000032c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000330: 00200293 li t0,2 + 80000334: fe5214e3 bne tp,t0,8000031c <test_23+0x4> + 80000338: 00100e93 li t4,1 + 8000033c: 01700193 li gp,23 + 80000340: 03df1863 bne t5,t4,80000370 <fail> + +0000000080000344 <test_24>: + 80000344: fff03093 sltiu ra,zero,-1 + 80000348: 00100e93 li t4,1 + 8000034c: 01800193 li gp,24 + 80000350: 03d09063 bne ra,t4,80000370 <fail> + +0000000080000354 <test_25>: + 80000354: 00ff00b7 lui ra,0xff0 + 80000358: 0ff0809b addiw ra,ra,255 + 8000035c: fff0b013 sltiu zero,ra,-1 + 80000360: 00000e93 li t4,0 + 80000364: 01900193 li gp,25 + 80000368: 01d01463 bne zero,t4,80000370 <fail> + 8000036c: 00301c63 bne zero,gp,80000384 <pass> + +0000000080000370 <fail>: + 80000370: 0ff0000f fence + 80000374: 00018063 beqz gp,80000374 <fail+0x4> + 80000378: 00119193 slli gp,gp,0x1 + 8000037c: 0011e193 ori gp,gp,1 + 80000380: 00000073 ecall + +0000000080000384 <pass>: + 80000384: 0ff0000f fence + 80000388: 00100193 li gp,1 + 8000038c: 00000073 ecall + 80000390: c0001073 unimp + 80000394: 0000 unimp + 80000396: 0000 unimp + 80000398: 0000 unimp + 8000039a: 0000 unimp + 8000039c: 0000 unimp + 8000039e: 0000 unimp + 800003a0: 0000 unimp + 800003a2: 0000 unimp + 800003a4: 0000 unimp + 800003a6: 0000 unimp + 800003a8: 0000 unimp + 800003aa: 0000 unimp + 800003ac: 0000 unimp + 800003ae: 0000 unimp + 800003b0: 0000 unimp + 800003b2: 0000 unimp + 800003b4: 0000 unimp + 800003b6: 0000 unimp + 800003b8: 0000 unimp + 800003ba: 0000 unimp + 800003bc: 0000 unimp + 800003be: 0000 unimp + 800003c0: 0000 unimp + 800003c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sltiu.elf b/test/riscv/tests/rv64ui-p-sltiu.elf Binary files differnew file mode 100755 index 00000000..9eb7628a --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sltiu.elf diff --git a/test/riscv/tests/rv64ui-p-sltu.dump b/test/riscv/tests/rv64ui-p-sltu.dump new file mode 100644 index 00000000..4b1cd23e --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sltu.dump @@ -0,0 +1,500 @@ + +rv64ui-p-sltu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 00000113 li sp,0 + 80000104: 0020bf33 sltu t5,ra,sp + 80000108: 00000e93 li t4,0 + 8000010c: 00200193 li gp,2 + 80000110: 4fdf1c63 bne t5,t4,80000608 <fail> + +0000000080000114 <test_3>: + 80000114: 00100093 li ra,1 + 80000118: 00100113 li sp,1 + 8000011c: 0020bf33 sltu t5,ra,sp + 80000120: 00000e93 li t4,0 + 80000124: 00300193 li gp,3 + 80000128: 4fdf1063 bne t5,t4,80000608 <fail> + +000000008000012c <test_4>: + 8000012c: 00300093 li ra,3 + 80000130: 00700113 li sp,7 + 80000134: 0020bf33 sltu t5,ra,sp + 80000138: 00100e93 li t4,1 + 8000013c: 00400193 li gp,4 + 80000140: 4ddf1463 bne t5,t4,80000608 <fail> + +0000000080000144 <test_5>: + 80000144: 00700093 li ra,7 + 80000148: 00300113 li sp,3 + 8000014c: 0020bf33 sltu t5,ra,sp + 80000150: 00000e93 li t4,0 + 80000154: 00500193 li gp,5 + 80000158: 4bdf1863 bne t5,t4,80000608 <fail> + +000000008000015c <test_6>: + 8000015c: 00000093 li ra,0 + 80000160: 00020137 lui sp,0x20 + 80000164: fff1011b addiw sp,sp,-1 + 80000168: 00f11113 slli sp,sp,0xf + 8000016c: 0020bf33 sltu t5,ra,sp + 80000170: 00100e93 li t4,1 + 80000174: 00600193 li gp,6 + 80000178: 49df1863 bne t5,t4,80000608 <fail> + +000000008000017c <test_7>: + 8000017c: 0010009b addiw ra,zero,1 + 80000180: 01f09093 slli ra,ra,0x1f + 80000184: 00000113 li sp,0 + 80000188: 0020bf33 sltu t5,ra,sp + 8000018c: 00000e93 li t4,0 + 80000190: 00700193 li gp,7 + 80000194: 47df1a63 bne t5,t4,80000608 <fail> + +0000000080000198 <test_8>: + 80000198: 0010009b addiw ra,zero,1 + 8000019c: 01f09093 slli ra,ra,0x1f + 800001a0: 00020137 lui sp,0x20 + 800001a4: fff1011b addiw sp,sp,-1 + 800001a8: 00f11113 slli sp,sp,0xf + 800001ac: 0020bf33 sltu t5,ra,sp + 800001b0: 00100e93 li t4,1 + 800001b4: 00800193 li gp,8 + 800001b8: 45df1863 bne t5,t4,80000608 <fail> + +00000000800001bc <test_9>: + 800001bc: 00000093 li ra,0 + 800001c0: 00008137 lui sp,0x8 + 800001c4: fff1011b addiw sp,sp,-1 + 800001c8: 0020bf33 sltu t5,ra,sp + 800001cc: 00100e93 li t4,1 + 800001d0: 00900193 li gp,9 + 800001d4: 43df1a63 bne t5,t4,80000608 <fail> + +00000000800001d8 <test_10>: + 800001d8: 800000b7 lui ra,0x80000 + 800001dc: fff0809b addiw ra,ra,-1 + 800001e0: 00000113 li sp,0 + 800001e4: 0020bf33 sltu t5,ra,sp + 800001e8: 00000e93 li t4,0 + 800001ec: 00a00193 li gp,10 + 800001f0: 41df1c63 bne t5,t4,80000608 <fail> + +00000000800001f4 <test_11>: + 800001f4: 800000b7 lui ra,0x80000 + 800001f8: fff0809b addiw ra,ra,-1 + 800001fc: 00008137 lui sp,0x8 + 80000200: fff1011b addiw sp,sp,-1 + 80000204: 0020bf33 sltu t5,ra,sp + 80000208: 00000e93 li t4,0 + 8000020c: 00b00193 li gp,11 + 80000210: 3fdf1c63 bne t5,t4,80000608 <fail> + +0000000080000214 <test_12>: + 80000214: 0010009b addiw ra,zero,1 + 80000218: 01f09093 slli ra,ra,0x1f + 8000021c: 00008137 lui sp,0x8 + 80000220: fff1011b addiw sp,sp,-1 + 80000224: 0020bf33 sltu t5,ra,sp + 80000228: 00000e93 li t4,0 + 8000022c: 00c00193 li gp,12 + 80000230: 3ddf1c63 bne t5,t4,80000608 <fail> + +0000000080000234 <test_13>: + 80000234: 800000b7 lui ra,0x80000 + 80000238: fff0809b addiw ra,ra,-1 + 8000023c: 00020137 lui sp,0x20 + 80000240: fff1011b addiw sp,sp,-1 + 80000244: 00f11113 slli sp,sp,0xf + 80000248: 0020bf33 sltu t5,ra,sp + 8000024c: 00100e93 li t4,1 + 80000250: 00d00193 li gp,13 + 80000254: 3bdf1a63 bne t5,t4,80000608 <fail> + +0000000080000258 <test_14>: + 80000258: 00000093 li ra,0 + 8000025c: 0010011b addiw sp,zero,1 + 80000260: 02011113 slli sp,sp,0x20 + 80000264: fff10113 addi sp,sp,-1 # 1ffff <_start-0x7ffe0001> + 80000268: 0020bf33 sltu t5,ra,sp + 8000026c: 00100e93 li t4,1 + 80000270: 00e00193 li gp,14 + 80000274: 39df1a63 bne t5,t4,80000608 <fail> + +0000000080000278 <test_15>: + 80000278: 0010009b addiw ra,zero,1 + 8000027c: 02009093 slli ra,ra,0x20 + 80000280: fff08093 addi ra,ra,-1 # ffffffff7fffffff <_end+0xfffffffeffffdfff> + 80000284: 00100113 li sp,1 + 80000288: 0020bf33 sltu t5,ra,sp + 8000028c: 00000e93 li t4,0 + 80000290: 00f00193 li gp,15 + 80000294: 37df1a63 bne t5,t4,80000608 <fail> + +0000000080000298 <test_16>: + 80000298: 0010009b addiw ra,zero,1 + 8000029c: 02009093 slli ra,ra,0x20 + 800002a0: fff08093 addi ra,ra,-1 + 800002a4: 0010011b addiw sp,zero,1 + 800002a8: 02011113 slli sp,sp,0x20 + 800002ac: fff10113 addi sp,sp,-1 + 800002b0: 0020bf33 sltu t5,ra,sp + 800002b4: 00000e93 li t4,0 + 800002b8: 01000193 li gp,16 + 800002bc: 35df1663 bne t5,t4,80000608 <fail> + +00000000800002c0 <test_17>: + 800002c0: 00e00093 li ra,14 + 800002c4: 00d00113 li sp,13 + 800002c8: 0020b0b3 sltu ra,ra,sp + 800002cc: 00000e93 li t4,0 + 800002d0: 01100193 li gp,17 + 800002d4: 33d09a63 bne ra,t4,80000608 <fail> + +00000000800002d8 <test_18>: + 800002d8: 00b00093 li ra,11 + 800002dc: 00d00113 li sp,13 + 800002e0: 0020b133 sltu sp,ra,sp + 800002e4: 00100e93 li t4,1 + 800002e8: 01200193 li gp,18 + 800002ec: 31d11e63 bne sp,t4,80000608 <fail> + +00000000800002f0 <test_19>: + 800002f0: 00d00093 li ra,13 + 800002f4: 0010b0b3 sltu ra,ra,ra + 800002f8: 00000e93 li t4,0 + 800002fc: 01300193 li gp,19 + 80000300: 31d09463 bne ra,t4,80000608 <fail> + +0000000080000304 <test_20>: + 80000304: 00000213 li tp,0 + 80000308: 00b00093 li ra,11 + 8000030c: 00d00113 li sp,13 + 80000310: 0020bf33 sltu t5,ra,sp + 80000314: 000f0313 mv t1,t5 + 80000318: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000031c: 00200293 li t0,2 + 80000320: fe5214e3 bne tp,t0,80000308 <test_20+0x4> + 80000324: 00100e93 li t4,1 + 80000328: 01400193 li gp,20 + 8000032c: 2dd31e63 bne t1,t4,80000608 <fail> + +0000000080000330 <test_21>: + 80000330: 00000213 li tp,0 + 80000334: 00e00093 li ra,14 + 80000338: 00d00113 li sp,13 + 8000033c: 0020bf33 sltu t5,ra,sp + 80000340: 00000013 nop + 80000344: 000f0313 mv t1,t5 + 80000348: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000034c: 00200293 li t0,2 + 80000350: fe5212e3 bne tp,t0,80000334 <test_21+0x4> + 80000354: 00000e93 li t4,0 + 80000358: 01500193 li gp,21 + 8000035c: 2bd31663 bne t1,t4,80000608 <fail> + +0000000080000360 <test_22>: + 80000360: 00000213 li tp,0 + 80000364: 00c00093 li ra,12 + 80000368: 00d00113 li sp,13 + 8000036c: 0020bf33 sltu t5,ra,sp + 80000370: 00000013 nop + 80000374: 00000013 nop + 80000378: 000f0313 mv t1,t5 + 8000037c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000380: 00200293 li t0,2 + 80000384: fe5210e3 bne tp,t0,80000364 <test_22+0x4> + 80000388: 00100e93 li t4,1 + 8000038c: 01600193 li gp,22 + 80000390: 27d31c63 bne t1,t4,80000608 <fail> + +0000000080000394 <test_23>: + 80000394: 00000213 li tp,0 + 80000398: 00e00093 li ra,14 + 8000039c: 00d00113 li sp,13 + 800003a0: 0020bf33 sltu t5,ra,sp + 800003a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003a8: 00200293 li t0,2 + 800003ac: fe5216e3 bne tp,t0,80000398 <test_23+0x4> + 800003b0: 00000e93 li t4,0 + 800003b4: 01700193 li gp,23 + 800003b8: 25df1863 bne t5,t4,80000608 <fail> + +00000000800003bc <test_24>: + 800003bc: 00000213 li tp,0 + 800003c0: 00b00093 li ra,11 + 800003c4: 00d00113 li sp,13 + 800003c8: 00000013 nop + 800003cc: 0020bf33 sltu t5,ra,sp + 800003d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003d4: 00200293 li t0,2 + 800003d8: fe5214e3 bne tp,t0,800003c0 <test_24+0x4> + 800003dc: 00100e93 li t4,1 + 800003e0: 01800193 li gp,24 + 800003e4: 23df1263 bne t5,t4,80000608 <fail> + +00000000800003e8 <test_25>: + 800003e8: 00000213 li tp,0 + 800003ec: 00f00093 li ra,15 + 800003f0: 00d00113 li sp,13 + 800003f4: 00000013 nop + 800003f8: 00000013 nop + 800003fc: 0020bf33 sltu t5,ra,sp + 80000400: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000404: 00200293 li t0,2 + 80000408: fe5212e3 bne tp,t0,800003ec <test_25+0x4> + 8000040c: 00000e93 li t4,0 + 80000410: 01900193 li gp,25 + 80000414: 1fdf1a63 bne t5,t4,80000608 <fail> + +0000000080000418 <test_26>: + 80000418: 00000213 li tp,0 + 8000041c: 00a00093 li ra,10 + 80000420: 00000013 nop + 80000424: 00d00113 li sp,13 + 80000428: 0020bf33 sltu t5,ra,sp + 8000042c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000430: 00200293 li t0,2 + 80000434: fe5214e3 bne tp,t0,8000041c <test_26+0x4> + 80000438: 00100e93 li t4,1 + 8000043c: 01a00193 li gp,26 + 80000440: 1ddf1463 bne t5,t4,80000608 <fail> + +0000000080000444 <test_27>: + 80000444: 00000213 li tp,0 + 80000448: 01000093 li ra,16 + 8000044c: 00000013 nop + 80000450: 00d00113 li sp,13 + 80000454: 00000013 nop + 80000458: 0020bf33 sltu t5,ra,sp + 8000045c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000460: 00200293 li t0,2 + 80000464: fe5212e3 bne tp,t0,80000448 <test_27+0x4> + 80000468: 00000e93 li t4,0 + 8000046c: 01b00193 li gp,27 + 80000470: 19df1c63 bne t5,t4,80000608 <fail> + +0000000080000474 <test_28>: + 80000474: 00000213 li tp,0 + 80000478: 00900093 li ra,9 + 8000047c: 00000013 nop + 80000480: 00000013 nop + 80000484: 00d00113 li sp,13 + 80000488: 0020bf33 sltu t5,ra,sp + 8000048c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000490: 00200293 li t0,2 + 80000494: fe5212e3 bne tp,t0,80000478 <test_28+0x4> + 80000498: 00100e93 li t4,1 + 8000049c: 01c00193 li gp,28 + 800004a0: 17df1463 bne t5,t4,80000608 <fail> + +00000000800004a4 <test_29>: + 800004a4: 00000213 li tp,0 + 800004a8: 00d00113 li sp,13 + 800004ac: 01100093 li ra,17 + 800004b0: 0020bf33 sltu t5,ra,sp + 800004b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004b8: 00200293 li t0,2 + 800004bc: fe5216e3 bne tp,t0,800004a8 <test_29+0x4> + 800004c0: 00000e93 li t4,0 + 800004c4: 01d00193 li gp,29 + 800004c8: 15df1063 bne t5,t4,80000608 <fail> + +00000000800004cc <test_30>: + 800004cc: 00000213 li tp,0 + 800004d0: 00d00113 li sp,13 + 800004d4: 00800093 li ra,8 + 800004d8: 00000013 nop + 800004dc: 0020bf33 sltu t5,ra,sp + 800004e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004e4: 00200293 li t0,2 + 800004e8: fe5214e3 bne tp,t0,800004d0 <test_30+0x4> + 800004ec: 00100e93 li t4,1 + 800004f0: 01e00193 li gp,30 + 800004f4: 11df1a63 bne t5,t4,80000608 <fail> + +00000000800004f8 <test_31>: + 800004f8: 00000213 li tp,0 + 800004fc: 00d00113 li sp,13 + 80000500: 01200093 li ra,18 + 80000504: 00000013 nop + 80000508: 00000013 nop + 8000050c: 0020bf33 sltu t5,ra,sp + 80000510: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000514: 00200293 li t0,2 + 80000518: fe5212e3 bne tp,t0,800004fc <test_31+0x4> + 8000051c: 00000e93 li t4,0 + 80000520: 01f00193 li gp,31 + 80000524: 0fdf1263 bne t5,t4,80000608 <fail> + +0000000080000528 <test_32>: + 80000528: 00000213 li tp,0 + 8000052c: 00d00113 li sp,13 + 80000530: 00000013 nop + 80000534: 00700093 li ra,7 + 80000538: 0020bf33 sltu t5,ra,sp + 8000053c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000540: 00200293 li t0,2 + 80000544: fe5214e3 bne tp,t0,8000052c <test_32+0x4> + 80000548: 00100e93 li t4,1 + 8000054c: 02000193 li gp,32 + 80000550: 0bdf1c63 bne t5,t4,80000608 <fail> + +0000000080000554 <test_33>: + 80000554: 00000213 li tp,0 + 80000558: 00d00113 li sp,13 + 8000055c: 00000013 nop + 80000560: 01300093 li ra,19 + 80000564: 00000013 nop + 80000568: 0020bf33 sltu t5,ra,sp + 8000056c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000570: 00200293 li t0,2 + 80000574: fe5212e3 bne tp,t0,80000558 <test_33+0x4> + 80000578: 00000e93 li t4,0 + 8000057c: 02100193 li gp,33 + 80000580: 09df1463 bne t5,t4,80000608 <fail> + +0000000080000584 <test_34>: + 80000584: 00000213 li tp,0 + 80000588: 00d00113 li sp,13 + 8000058c: 00000013 nop + 80000590: 00000013 nop + 80000594: 00600093 li ra,6 + 80000598: 0020bf33 sltu t5,ra,sp + 8000059c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005a0: 00200293 li t0,2 + 800005a4: fe5212e3 bne tp,t0,80000588 <test_34+0x4> + 800005a8: 00100e93 li t4,1 + 800005ac: 02200193 li gp,34 + 800005b0: 05df1c63 bne t5,t4,80000608 <fail> + +00000000800005b4 <test_35>: + 800005b4: fff00093 li ra,-1 + 800005b8: 00103133 snez sp,ra + 800005bc: 00100e93 li t4,1 + 800005c0: 02300193 li gp,35 + 800005c4: 05d11263 bne sp,t4,80000608 <fail> + +00000000800005c8 <test_36>: + 800005c8: fff00093 li ra,-1 + 800005cc: 0000b133 sltu sp,ra,zero + 800005d0: 00000e93 li t4,0 + 800005d4: 02400193 li gp,36 + 800005d8: 03d11863 bne sp,t4,80000608 <fail> + +00000000800005dc <test_37>: + 800005dc: 000030b3 snez ra,zero + 800005e0: 00000e93 li t4,0 + 800005e4: 02500193 li gp,37 + 800005e8: 03d09063 bne ra,t4,80000608 <fail> + +00000000800005ec <test_38>: + 800005ec: 01000093 li ra,16 + 800005f0: 01e00113 li sp,30 + 800005f4: 0020b033 sltu zero,ra,sp + 800005f8: 00000e93 li t4,0 + 800005fc: 02600193 li gp,38 + 80000600: 01d01463 bne zero,t4,80000608 <fail> + 80000604: 00301c63 bne zero,gp,8000061c <pass> + +0000000080000608 <fail>: + 80000608: 0ff0000f fence + 8000060c: 00018063 beqz gp,8000060c <fail+0x4> + 80000610: 00119193 slli gp,gp,0x1 + 80000614: 0011e193 ori gp,gp,1 + 80000618: 00000073 ecall + +000000008000061c <pass>: + 8000061c: 0ff0000f fence + 80000620: 00100193 li gp,1 + 80000624: 00000073 ecall + 80000628: c0001073 unimp + 8000062c: 0000 unimp + 8000062e: 0000 unimp + 80000630: 0000 unimp + 80000632: 0000 unimp + 80000634: 0000 unimp + 80000636: 0000 unimp + 80000638: 0000 unimp + 8000063a: 0000 unimp + 8000063c: 0000 unimp + 8000063e: 0000 unimp + 80000640: 0000 unimp + 80000642: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sltu.elf b/test/riscv/tests/rv64ui-p-sltu.elf Binary files differnew file mode 100755 index 00000000..2c63f0bd --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sltu.elf diff --git a/test/riscv/tests/rv64ui-p-sra.dump b/test/riscv/tests/rv64ui-p-sra.dump new file mode 100644 index 00000000..4b5e4ed5 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sra.dump @@ -0,0 +1,538 @@ + +rv64ui-p-sra: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 800000b7 lui ra,0x80000 + 80000100: 00000113 li sp,0 + 80000104: 4020df33 sra t5,ra,sp + 80000108: 80000eb7 lui t4,0x80000 + 8000010c: 00200193 li gp,2 + 80000110: 59df1463 bne t5,t4,80000698 <fail> + +0000000080000114 <test_3>: + 80000114: 800000b7 lui ra,0x80000 + 80000118: 00100113 li sp,1 + 8000011c: 4020df33 sra t5,ra,sp + 80000120: c0000eb7 lui t4,0xc0000 + 80000124: 00300193 li gp,3 + 80000128: 57df1863 bne t5,t4,80000698 <fail> + +000000008000012c <test_4>: + 8000012c: 800000b7 lui ra,0x80000 + 80000130: 00700113 li sp,7 + 80000134: 4020df33 sra t5,ra,sp + 80000138: ff000eb7 lui t4,0xff000 + 8000013c: 00400193 li gp,4 + 80000140: 55df1c63 bne t5,t4,80000698 <fail> + +0000000080000144 <test_5>: + 80000144: 800000b7 lui ra,0x80000 + 80000148: 00e00113 li sp,14 + 8000014c: 4020df33 sra t5,ra,sp + 80000150: fffe0eb7 lui t4,0xfffe0 + 80000154: 00500193 li gp,5 + 80000158: 55df1063 bne t5,t4,80000698 <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 0010809b addiw ra,ra,1 + 80000164: 01f00113 li sp,31 + 80000168: 4020df33 sra t5,ra,sp + 8000016c: fff00e93 li t4,-1 + 80000170: 00600193 li gp,6 + 80000174: 53df1263 bne t5,t4,80000698 <fail> + +0000000080000178 <test_7>: + 80000178: 800000b7 lui ra,0x80000 + 8000017c: fff0809b addiw ra,ra,-1 + 80000180: 00000113 li sp,0 + 80000184: 4020df33 sra t5,ra,sp + 80000188: 80000eb7 lui t4,0x80000 + 8000018c: fffe8e9b addiw t4,t4,-1 + 80000190: 00700193 li gp,7 + 80000194: 51df1263 bne t5,t4,80000698 <fail> + +0000000080000198 <test_8>: + 80000198: 800000b7 lui ra,0x80000 + 8000019c: fff0809b addiw ra,ra,-1 + 800001a0: 00100113 li sp,1 + 800001a4: 4020df33 sra t5,ra,sp + 800001a8: 40000eb7 lui t4,0x40000 + 800001ac: fffe8e9b addiw t4,t4,-1 + 800001b0: 00800193 li gp,8 + 800001b4: 4fdf1263 bne t5,t4,80000698 <fail> + +00000000800001b8 <test_9>: + 800001b8: 800000b7 lui ra,0x80000 + 800001bc: fff0809b addiw ra,ra,-1 + 800001c0: 00700113 li sp,7 + 800001c4: 4020df33 sra t5,ra,sp + 800001c8: 01000eb7 lui t4,0x1000 + 800001cc: fffe8e9b addiw t4,t4,-1 + 800001d0: 00900193 li gp,9 + 800001d4: 4ddf1263 bne t5,t4,80000698 <fail> + +00000000800001d8 <test_10>: + 800001d8: 800000b7 lui ra,0x80000 + 800001dc: fff0809b addiw ra,ra,-1 + 800001e0: 00e00113 li sp,14 + 800001e4: 4020df33 sra t5,ra,sp + 800001e8: 00020eb7 lui t4,0x20 + 800001ec: fffe8e9b addiw t4,t4,-1 + 800001f0: 00a00193 li gp,10 + 800001f4: 4bdf1263 bne t5,t4,80000698 <fail> + +00000000800001f8 <test_11>: + 800001f8: 800000b7 lui ra,0x80000 + 800001fc: fff0809b addiw ra,ra,-1 + 80000200: 01f00113 li sp,31 + 80000204: 4020df33 sra t5,ra,sp + 80000208: 00000e93 li t4,0 + 8000020c: 00b00193 li gp,11 + 80000210: 49df1463 bne t5,t4,80000698 <fail> + +0000000080000214 <test_12>: + 80000214: 818180b7 lui ra,0x81818 + 80000218: 1810809b addiw ra,ra,385 + 8000021c: 00000113 li sp,0 + 80000220: 4020df33 sra t5,ra,sp + 80000224: 81818eb7 lui t4,0x81818 + 80000228: 181e8e9b addiw t4,t4,385 + 8000022c: 00c00193 li gp,12 + 80000230: 47df1463 bne t5,t4,80000698 <fail> + +0000000080000234 <test_13>: + 80000234: 818180b7 lui ra,0x81818 + 80000238: 1810809b addiw ra,ra,385 + 8000023c: 00100113 li sp,1 + 80000240: 4020df33 sra t5,ra,sp + 80000244: c0c0ceb7 lui t4,0xc0c0c + 80000248: 0c0e8e9b addiw t4,t4,192 + 8000024c: 00d00193 li gp,13 + 80000250: 45df1463 bne t5,t4,80000698 <fail> + +0000000080000254 <test_14>: + 80000254: 818180b7 lui ra,0x81818 + 80000258: 1810809b addiw ra,ra,385 + 8000025c: 00700113 li sp,7 + 80000260: 4020df33 sra t5,ra,sp + 80000264: ff030eb7 lui t4,0xff030 + 80000268: 303e8e9b addiw t4,t4,771 + 8000026c: 00e00193 li gp,14 + 80000270: 43df1463 bne t5,t4,80000698 <fail> + +0000000080000274 <test_15>: + 80000274: 818180b7 lui ra,0x81818 + 80000278: 1810809b addiw ra,ra,385 + 8000027c: 00e00113 li sp,14 + 80000280: 4020df33 sra t5,ra,sp + 80000284: fffe0eb7 lui t4,0xfffe0 + 80000288: 606e8e9b addiw t4,t4,1542 + 8000028c: 00f00193 li gp,15 + 80000290: 41df1463 bne t5,t4,80000698 <fail> + +0000000080000294 <test_16>: + 80000294: 818180b7 lui ra,0x81818 + 80000298: 1810809b addiw ra,ra,385 + 8000029c: 01f00113 li sp,31 + 800002a0: 4020df33 sra t5,ra,sp + 800002a4: fff00e93 li t4,-1 + 800002a8: 01000193 li gp,16 + 800002ac: 3fdf1663 bne t5,t4,80000698 <fail> + +00000000800002b0 <test_17>: + 800002b0: 818180b7 lui ra,0x81818 + 800002b4: 1810809b addiw ra,ra,385 + 800002b8: fc000113 li sp,-64 + 800002bc: 4020df33 sra t5,ra,sp + 800002c0: 81818eb7 lui t4,0x81818 + 800002c4: 181e8e9b addiw t4,t4,385 + 800002c8: 01100193 li gp,17 + 800002cc: 3ddf1663 bne t5,t4,80000698 <fail> + +00000000800002d0 <test_18>: + 800002d0: 818180b7 lui ra,0x81818 + 800002d4: 1810809b addiw ra,ra,385 + 800002d8: fc100113 li sp,-63 + 800002dc: 4020df33 sra t5,ra,sp + 800002e0: c0c0ceb7 lui t4,0xc0c0c + 800002e4: 0c0e8e9b addiw t4,t4,192 + 800002e8: 01200193 li gp,18 + 800002ec: 3bdf1663 bne t5,t4,80000698 <fail> + +00000000800002f0 <test_19>: + 800002f0: 818180b7 lui ra,0x81818 + 800002f4: 1810809b addiw ra,ra,385 + 800002f8: fc700113 li sp,-57 + 800002fc: 4020df33 sra t5,ra,sp + 80000300: ff030eb7 lui t4,0xff030 + 80000304: 303e8e9b addiw t4,t4,771 + 80000308: 01300193 li gp,19 + 8000030c: 39df1663 bne t5,t4,80000698 <fail> + +0000000080000310 <test_20>: + 80000310: 818180b7 lui ra,0x81818 + 80000314: 1810809b addiw ra,ra,385 + 80000318: fce00113 li sp,-50 + 8000031c: 4020df33 sra t5,ra,sp + 80000320: fffe0eb7 lui t4,0xfffe0 + 80000324: 606e8e9b addiw t4,t4,1542 + 80000328: 01400193 li gp,20 + 8000032c: 37df1663 bne t5,t4,80000698 <fail> + +0000000080000330 <test_21>: + 80000330: 818180b7 lui ra,0x81818 + 80000334: 1810809b addiw ra,ra,385 + 80000338: fff00113 li sp,-1 + 8000033c: 4020df33 sra t5,ra,sp + 80000340: fff00e93 li t4,-1 + 80000344: 01500193 li gp,21 + 80000348: 35df1863 bne t5,t4,80000698 <fail> + +000000008000034c <test_22>: + 8000034c: 800000b7 lui ra,0x80000 + 80000350: 00700113 li sp,7 + 80000354: 4020d0b3 sra ra,ra,sp + 80000358: ff000eb7 lui t4,0xff000 + 8000035c: 01600193 li gp,22 + 80000360: 33d09c63 bne ra,t4,80000698 <fail> + +0000000080000364 <test_23>: + 80000364: 800000b7 lui ra,0x80000 + 80000368: 00e00113 li sp,14 + 8000036c: 4020d133 sra sp,ra,sp + 80000370: fffe0eb7 lui t4,0xfffe0 + 80000374: 01700193 li gp,23 + 80000378: 33d11063 bne sp,t4,80000698 <fail> + +000000008000037c <test_24>: + 8000037c: 00700093 li ra,7 + 80000380: 4010d0b3 sra ra,ra,ra + 80000384: 00000e93 li t4,0 + 80000388: 01800193 li gp,24 + 8000038c: 31d09663 bne ra,t4,80000698 <fail> + +0000000080000390 <test_25>: + 80000390: 00000213 li tp,0 + 80000394: 800000b7 lui ra,0x80000 + 80000398: 00700113 li sp,7 + 8000039c: 4020df33 sra t5,ra,sp + 800003a0: 000f0313 mv t1,t5 + 800003a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003a8: 00200293 li t0,2 + 800003ac: fe5214e3 bne tp,t0,80000394 <test_25+0x4> + 800003b0: ff000eb7 lui t4,0xff000 + 800003b4: 01900193 li gp,25 + 800003b8: 2fd31063 bne t1,t4,80000698 <fail> + +00000000800003bc <test_26>: + 800003bc: 00000213 li tp,0 + 800003c0: 800000b7 lui ra,0x80000 + 800003c4: 00e00113 li sp,14 + 800003c8: 4020df33 sra t5,ra,sp + 800003cc: 00000013 nop + 800003d0: 000f0313 mv t1,t5 + 800003d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003d8: 00200293 li t0,2 + 800003dc: fe5212e3 bne tp,t0,800003c0 <test_26+0x4> + 800003e0: fffe0eb7 lui t4,0xfffe0 + 800003e4: 01a00193 li gp,26 + 800003e8: 2bd31863 bne t1,t4,80000698 <fail> + +00000000800003ec <test_27>: + 800003ec: 00000213 li tp,0 + 800003f0: 800000b7 lui ra,0x80000 + 800003f4: 01f00113 li sp,31 + 800003f8: 4020df33 sra t5,ra,sp + 800003fc: 00000013 nop + 80000400: 00000013 nop + 80000404: 000f0313 mv t1,t5 + 80000408: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000040c: 00200293 li t0,2 + 80000410: fe5210e3 bne tp,t0,800003f0 <test_27+0x4> + 80000414: fff00e93 li t4,-1 + 80000418: 01b00193 li gp,27 + 8000041c: 27d31e63 bne t1,t4,80000698 <fail> + +0000000080000420 <test_28>: + 80000420: 00000213 li tp,0 + 80000424: 800000b7 lui ra,0x80000 + 80000428: 00700113 li sp,7 + 8000042c: 4020df33 sra t5,ra,sp + 80000430: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000434: 00200293 li t0,2 + 80000438: fe5216e3 bne tp,t0,80000424 <test_28+0x4> + 8000043c: ff000eb7 lui t4,0xff000 + 80000440: 01c00193 li gp,28 + 80000444: 25df1a63 bne t5,t4,80000698 <fail> + +0000000080000448 <test_29>: + 80000448: 00000213 li tp,0 + 8000044c: 800000b7 lui ra,0x80000 + 80000450: 00e00113 li sp,14 + 80000454: 00000013 nop + 80000458: 4020df33 sra t5,ra,sp + 8000045c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000460: 00200293 li t0,2 + 80000464: fe5214e3 bne tp,t0,8000044c <test_29+0x4> + 80000468: fffe0eb7 lui t4,0xfffe0 + 8000046c: 01d00193 li gp,29 + 80000470: 23df1463 bne t5,t4,80000698 <fail> + +0000000080000474 <test_30>: + 80000474: 00000213 li tp,0 + 80000478: 800000b7 lui ra,0x80000 + 8000047c: 01f00113 li sp,31 + 80000480: 00000013 nop + 80000484: 00000013 nop + 80000488: 4020df33 sra t5,ra,sp + 8000048c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000490: 00200293 li t0,2 + 80000494: fe5212e3 bne tp,t0,80000478 <test_30+0x4> + 80000498: fff00e93 li t4,-1 + 8000049c: 01e00193 li gp,30 + 800004a0: 1fdf1c63 bne t5,t4,80000698 <fail> + +00000000800004a4 <test_31>: + 800004a4: 00000213 li tp,0 + 800004a8: 800000b7 lui ra,0x80000 + 800004ac: 00000013 nop + 800004b0: 00700113 li sp,7 + 800004b4: 4020df33 sra t5,ra,sp + 800004b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004bc: 00200293 li t0,2 + 800004c0: fe5214e3 bne tp,t0,800004a8 <test_31+0x4> + 800004c4: ff000eb7 lui t4,0xff000 + 800004c8: 01f00193 li gp,31 + 800004cc: 1ddf1663 bne t5,t4,80000698 <fail> + +00000000800004d0 <test_32>: + 800004d0: 00000213 li tp,0 + 800004d4: 800000b7 lui ra,0x80000 + 800004d8: 00000013 nop + 800004dc: 00e00113 li sp,14 + 800004e0: 00000013 nop + 800004e4: 4020df33 sra t5,ra,sp + 800004e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004ec: 00200293 li t0,2 + 800004f0: fe5212e3 bne tp,t0,800004d4 <test_32+0x4> + 800004f4: fffe0eb7 lui t4,0xfffe0 + 800004f8: 02000193 li gp,32 + 800004fc: 19df1e63 bne t5,t4,80000698 <fail> + +0000000080000500 <test_33>: + 80000500: 00000213 li tp,0 + 80000504: 800000b7 lui ra,0x80000 + 80000508: 00000013 nop + 8000050c: 00000013 nop + 80000510: 01f00113 li sp,31 + 80000514: 4020df33 sra t5,ra,sp + 80000518: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000051c: 00200293 li t0,2 + 80000520: fe5212e3 bne tp,t0,80000504 <test_33+0x4> + 80000524: fff00e93 li t4,-1 + 80000528: 02100193 li gp,33 + 8000052c: 17df1663 bne t5,t4,80000698 <fail> + +0000000080000530 <test_34>: + 80000530: 00000213 li tp,0 + 80000534: 00700113 li sp,7 + 80000538: 800000b7 lui ra,0x80000 + 8000053c: 4020df33 sra t5,ra,sp + 80000540: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000544: 00200293 li t0,2 + 80000548: fe5216e3 bne tp,t0,80000534 <test_34+0x4> + 8000054c: ff000eb7 lui t4,0xff000 + 80000550: 02200193 li gp,34 + 80000554: 15df1263 bne t5,t4,80000698 <fail> + +0000000080000558 <test_35>: + 80000558: 00000213 li tp,0 + 8000055c: 00e00113 li sp,14 + 80000560: 800000b7 lui ra,0x80000 + 80000564: 00000013 nop + 80000568: 4020df33 sra t5,ra,sp + 8000056c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000570: 00200293 li t0,2 + 80000574: fe5214e3 bne tp,t0,8000055c <test_35+0x4> + 80000578: fffe0eb7 lui t4,0xfffe0 + 8000057c: 02300193 li gp,35 + 80000580: 11df1c63 bne t5,t4,80000698 <fail> + +0000000080000584 <test_36>: + 80000584: 00000213 li tp,0 + 80000588: 01f00113 li sp,31 + 8000058c: 800000b7 lui ra,0x80000 + 80000590: 00000013 nop + 80000594: 00000013 nop + 80000598: 4020df33 sra t5,ra,sp + 8000059c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005a0: 00200293 li t0,2 + 800005a4: fe5212e3 bne tp,t0,80000588 <test_36+0x4> + 800005a8: fff00e93 li t4,-1 + 800005ac: 02400193 li gp,36 + 800005b0: 0fdf1463 bne t5,t4,80000698 <fail> + +00000000800005b4 <test_37>: + 800005b4: 00000213 li tp,0 + 800005b8: 00700113 li sp,7 + 800005bc: 00000013 nop + 800005c0: 800000b7 lui ra,0x80000 + 800005c4: 4020df33 sra t5,ra,sp + 800005c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005cc: 00200293 li t0,2 + 800005d0: fe5214e3 bne tp,t0,800005b8 <test_37+0x4> + 800005d4: ff000eb7 lui t4,0xff000 + 800005d8: 02500193 li gp,37 + 800005dc: 0bdf1e63 bne t5,t4,80000698 <fail> + +00000000800005e0 <test_38>: + 800005e0: 00000213 li tp,0 + 800005e4: 00e00113 li sp,14 + 800005e8: 00000013 nop + 800005ec: 800000b7 lui ra,0x80000 + 800005f0: 00000013 nop + 800005f4: 4020df33 sra t5,ra,sp + 800005f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005fc: 00200293 li t0,2 + 80000600: fe5212e3 bne tp,t0,800005e4 <test_38+0x4> + 80000604: fffe0eb7 lui t4,0xfffe0 + 80000608: 02600193 li gp,38 + 8000060c: 09df1663 bne t5,t4,80000698 <fail> + +0000000080000610 <test_39>: + 80000610: 00000213 li tp,0 + 80000614: 01f00113 li sp,31 + 80000618: 00000013 nop + 8000061c: 00000013 nop + 80000620: 800000b7 lui ra,0x80000 + 80000624: 4020df33 sra t5,ra,sp + 80000628: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000062c: 00200293 li t0,2 + 80000630: fe5212e3 bne tp,t0,80000614 <test_39+0x4> + 80000634: fff00e93 li t4,-1 + 80000638: 02700193 li gp,39 + 8000063c: 05df1e63 bne t5,t4,80000698 <fail> + +0000000080000640 <test_40>: + 80000640: 00f00093 li ra,15 + 80000644: 40105133 sra sp,zero,ra + 80000648: 00000e93 li t4,0 + 8000064c: 02800193 li gp,40 + 80000650: 05d11463 bne sp,t4,80000698 <fail> + +0000000080000654 <test_41>: + 80000654: 02000093 li ra,32 + 80000658: 4000d133 sra sp,ra,zero + 8000065c: 02000e93 li t4,32 + 80000660: 02900193 li gp,41 + 80000664: 03d11a63 bne sp,t4,80000698 <fail> + +0000000080000668 <test_42>: + 80000668: 400050b3 sra ra,zero,zero + 8000066c: 00000e93 li t4,0 + 80000670: 02a00193 li gp,42 + 80000674: 03d09263 bne ra,t4,80000698 <fail> + +0000000080000678 <test_43>: + 80000678: 40000093 li ra,1024 + 8000067c: 00001137 lui sp,0x1 + 80000680: 8001011b addiw sp,sp,-2048 + 80000684: 4020d033 sra zero,ra,sp + 80000688: 00000e93 li t4,0 + 8000068c: 02b00193 li gp,43 + 80000690: 01d01463 bne zero,t4,80000698 <fail> + 80000694: 00301c63 bne zero,gp,800006ac <pass> + +0000000080000698 <fail>: + 80000698: 0ff0000f fence + 8000069c: 00018063 beqz gp,8000069c <fail+0x4> + 800006a0: 00119193 slli gp,gp,0x1 + 800006a4: 0011e193 ori gp,gp,1 + 800006a8: 00000073 ecall + +00000000800006ac <pass>: + 800006ac: 0ff0000f fence + 800006b0: 00100193 li gp,1 + 800006b4: 00000073 ecall + 800006b8: c0001073 unimp + 800006bc: 0000 unimp + 800006be: 0000 unimp + 800006c0: 0000 unimp + 800006c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sra.elf b/test/riscv/tests/rv64ui-p-sra.elf Binary files differnew file mode 100755 index 00000000..9ed528bd --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sra.elf diff --git a/test/riscv/tests/rv64ui-p-srai.dump b/test/riscv/tests/rv64ui-p-srai.dump new file mode 100644 index 00000000..e86b0510 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-srai.dump @@ -0,0 +1,333 @@ + +rv64ui-p-srai: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: fff0009b addiw ra,zero,-1 + 80000100: 02709093 slli ra,ra,0x27 + 80000104: 4000df13 srai t5,ra,0x0 + 80000108: fff00e9b addiw t4,zero,-1 + 8000010c: 027e9e93 slli t4,t4,0x27 + 80000110: 00200193 li gp,2 + 80000114: 2bdf1463 bne t5,t4,800003bc <fail> + +0000000080000118 <test_3>: + 80000118: 800000b7 lui ra,0x80000 + 8000011c: 4010df13 srai t5,ra,0x1 + 80000120: c0000eb7 lui t4,0xc0000 + 80000124: 00300193 li gp,3 + 80000128: 29df1a63 bne t5,t4,800003bc <fail> + +000000008000012c <test_4>: + 8000012c: 800000b7 lui ra,0x80000 + 80000130: 4070df13 srai t5,ra,0x7 + 80000134: ff000eb7 lui t4,0xff000 + 80000138: 00400193 li gp,4 + 8000013c: 29df1063 bne t5,t4,800003bc <fail> + +0000000080000140 <test_5>: + 80000140: 800000b7 lui ra,0x80000 + 80000144: 40e0df13 srai t5,ra,0xe + 80000148: fffe0eb7 lui t4,0xfffe0 + 8000014c: 00500193 li gp,5 + 80000150: 27df1663 bne t5,t4,800003bc <fail> + +0000000080000154 <test_6>: + 80000154: 800000b7 lui ra,0x80000 + 80000158: 0010809b addiw ra,ra,1 + 8000015c: 41f0df13 srai t5,ra,0x1f + 80000160: fff00e93 li t4,-1 + 80000164: 00600193 li gp,6 + 80000168: 25df1a63 bne t5,t4,800003bc <fail> + +000000008000016c <test_7>: + 8000016c: 800000b7 lui ra,0x80000 + 80000170: fff0809b addiw ra,ra,-1 + 80000174: 4000df13 srai t5,ra,0x0 + 80000178: 80000eb7 lui t4,0x80000 + 8000017c: fffe8e9b addiw t4,t4,-1 + 80000180: 00700193 li gp,7 + 80000184: 23df1c63 bne t5,t4,800003bc <fail> + +0000000080000188 <test_8>: + 80000188: 800000b7 lui ra,0x80000 + 8000018c: fff0809b addiw ra,ra,-1 + 80000190: 4010df13 srai t5,ra,0x1 + 80000194: 40000eb7 lui t4,0x40000 + 80000198: fffe8e9b addiw t4,t4,-1 + 8000019c: 00800193 li gp,8 + 800001a0: 21df1e63 bne t5,t4,800003bc <fail> + +00000000800001a4 <test_9>: + 800001a4: 800000b7 lui ra,0x80000 + 800001a8: fff0809b addiw ra,ra,-1 + 800001ac: 4070df13 srai t5,ra,0x7 + 800001b0: 01000eb7 lui t4,0x1000 + 800001b4: fffe8e9b addiw t4,t4,-1 + 800001b8: 00900193 li gp,9 + 800001bc: 21df1063 bne t5,t4,800003bc <fail> + +00000000800001c0 <test_10>: + 800001c0: 800000b7 lui ra,0x80000 + 800001c4: fff0809b addiw ra,ra,-1 + 800001c8: 40e0df13 srai t5,ra,0xe + 800001cc: 00020eb7 lui t4,0x20 + 800001d0: fffe8e9b addiw t4,t4,-1 + 800001d4: 00a00193 li gp,10 + 800001d8: 1fdf1263 bne t5,t4,800003bc <fail> + +00000000800001dc <test_11>: + 800001dc: 800000b7 lui ra,0x80000 + 800001e0: fff0809b addiw ra,ra,-1 + 800001e4: 41f0df13 srai t5,ra,0x1f + 800001e8: 00000e93 li t4,0 + 800001ec: 00b00193 li gp,11 + 800001f0: 1ddf1663 bne t5,t4,800003bc <fail> + +00000000800001f4 <test_12>: + 800001f4: 818180b7 lui ra,0x81818 + 800001f8: 1810809b addiw ra,ra,385 + 800001fc: 4000df13 srai t5,ra,0x0 + 80000200: 81818eb7 lui t4,0x81818 + 80000204: 181e8e9b addiw t4,t4,385 + 80000208: 00c00193 li gp,12 + 8000020c: 1bdf1863 bne t5,t4,800003bc <fail> + +0000000080000210 <test_13>: + 80000210: 818180b7 lui ra,0x81818 + 80000214: 1810809b addiw ra,ra,385 + 80000218: 4010df13 srai t5,ra,0x1 + 8000021c: c0c0ceb7 lui t4,0xc0c0c + 80000220: 0c0e8e9b addiw t4,t4,192 + 80000224: 00d00193 li gp,13 + 80000228: 19df1a63 bne t5,t4,800003bc <fail> + +000000008000022c <test_14>: + 8000022c: 818180b7 lui ra,0x81818 + 80000230: 1810809b addiw ra,ra,385 + 80000234: 4070df13 srai t5,ra,0x7 + 80000238: ff030eb7 lui t4,0xff030 + 8000023c: 303e8e9b addiw t4,t4,771 + 80000240: 00e00193 li gp,14 + 80000244: 17df1c63 bne t5,t4,800003bc <fail> + +0000000080000248 <test_15>: + 80000248: 818180b7 lui ra,0x81818 + 8000024c: 1810809b addiw ra,ra,385 + 80000250: 40e0df13 srai t5,ra,0xe + 80000254: fffe0eb7 lui t4,0xfffe0 + 80000258: 606e8e9b addiw t4,t4,1542 + 8000025c: 00f00193 li gp,15 + 80000260: 15df1e63 bne t5,t4,800003bc <fail> + +0000000080000264 <test_16>: + 80000264: 818180b7 lui ra,0x81818 + 80000268: 1810809b addiw ra,ra,385 + 8000026c: 41f0df13 srai t5,ra,0x1f + 80000270: fff00e93 li t4,-1 + 80000274: 01000193 li gp,16 + 80000278: 15df1263 bne t5,t4,800003bc <fail> + +000000008000027c <test_17>: + 8000027c: 800000b7 lui ra,0x80000 + 80000280: 4070d093 srai ra,ra,0x7 + 80000284: ff000eb7 lui t4,0xff000 + 80000288: 01100193 li gp,17 + 8000028c: 13d09863 bne ra,t4,800003bc <fail> + +0000000080000290 <test_18>: + 80000290: 00000213 li tp,0 + 80000294: 800000b7 lui ra,0x80000 + 80000298: 4070df13 srai t5,ra,0x7 + 8000029c: 000f0313 mv t1,t5 + 800002a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a4: 00200293 li t0,2 + 800002a8: fe5216e3 bne tp,t0,80000294 <test_18+0x4> + 800002ac: ff000eb7 lui t4,0xff000 + 800002b0: 01200193 li gp,18 + 800002b4: 11d31463 bne t1,t4,800003bc <fail> + +00000000800002b8 <test_19>: + 800002b8: 00000213 li tp,0 + 800002bc: 800000b7 lui ra,0x80000 + 800002c0: 40e0df13 srai t5,ra,0xe + 800002c4: 00000013 nop + 800002c8: 000f0313 mv t1,t5 + 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002d0: 00200293 li t0,2 + 800002d4: fe5214e3 bne tp,t0,800002bc <test_19+0x4> + 800002d8: fffe0eb7 lui t4,0xfffe0 + 800002dc: 01300193 li gp,19 + 800002e0: 0dd31e63 bne t1,t4,800003bc <fail> + +00000000800002e4 <test_20>: + 800002e4: 00000213 li tp,0 + 800002e8: 800000b7 lui ra,0x80000 + 800002ec: 0010809b addiw ra,ra,1 + 800002f0: 41f0df13 srai t5,ra,0x1f + 800002f4: 00000013 nop + 800002f8: 00000013 nop + 800002fc: 000f0313 mv t1,t5 + 80000300: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000304: 00200293 li t0,2 + 80000308: fe5210e3 bne tp,t0,800002e8 <test_20+0x4> + 8000030c: fff00e93 li t4,-1 + 80000310: 01400193 li gp,20 + 80000314: 0bd31463 bne t1,t4,800003bc <fail> + +0000000080000318 <test_21>: + 80000318: 00000213 li tp,0 + 8000031c: 800000b7 lui ra,0x80000 + 80000320: 4070df13 srai t5,ra,0x7 + 80000324: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000328: 00200293 li t0,2 + 8000032c: fe5218e3 bne tp,t0,8000031c <test_21+0x4> + 80000330: ff000eb7 lui t4,0xff000 + 80000334: 01500193 li gp,21 + 80000338: 09df1263 bne t5,t4,800003bc <fail> + +000000008000033c <test_22>: + 8000033c: 00000213 li tp,0 + 80000340: 800000b7 lui ra,0x80000 + 80000344: 00000013 nop + 80000348: 40e0df13 srai t5,ra,0xe + 8000034c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000350: 00200293 li t0,2 + 80000354: fe5216e3 bne tp,t0,80000340 <test_22+0x4> + 80000358: fffe0eb7 lui t4,0xfffe0 + 8000035c: 01600193 li gp,22 + 80000360: 05df1e63 bne t5,t4,800003bc <fail> + +0000000080000364 <test_23>: + 80000364: 00000213 li tp,0 + 80000368: 800000b7 lui ra,0x80000 + 8000036c: 0010809b addiw ra,ra,1 + 80000370: 00000013 nop + 80000374: 00000013 nop + 80000378: 41f0df13 srai t5,ra,0x1f + 8000037c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000380: 00200293 li t0,2 + 80000384: fe5212e3 bne tp,t0,80000368 <test_23+0x4> + 80000388: fff00e93 li t4,-1 + 8000038c: 01700193 li gp,23 + 80000390: 03df1663 bne t5,t4,800003bc <fail> + +0000000080000394 <test_24>: + 80000394: 40405093 srai ra,zero,0x4 + 80000398: 00000e93 li t4,0 + 8000039c: 01800193 li gp,24 + 800003a0: 01d09e63 bne ra,t4,800003bc <fail> + +00000000800003a4 <test_25>: + 800003a4: 02100093 li ra,33 + 800003a8: 40a0d013 srai zero,ra,0xa + 800003ac: 00000e93 li t4,0 + 800003b0: 01900193 li gp,25 + 800003b4: 01d01463 bne zero,t4,800003bc <fail> + 800003b8: 00301c63 bne zero,gp,800003d0 <pass> + +00000000800003bc <fail>: + 800003bc: 0ff0000f fence + 800003c0: 00018063 beqz gp,800003c0 <fail+0x4> + 800003c4: 00119193 slli gp,gp,0x1 + 800003c8: 0011e193 ori gp,gp,1 + 800003cc: 00000073 ecall + +00000000800003d0 <pass>: + 800003d0: 0ff0000f fence + 800003d4: 00100193 li gp,1 + 800003d8: 00000073 ecall + 800003dc: c0001073 unimp + 800003e0: 0000 unimp + 800003e2: 0000 unimp + 800003e4: 0000 unimp + 800003e6: 0000 unimp + 800003e8: 0000 unimp + 800003ea: 0000 unimp + 800003ec: 0000 unimp + 800003ee: 0000 unimp + 800003f0: 0000 unimp + 800003f2: 0000 unimp + 800003f4: 0000 unimp + 800003f6: 0000 unimp + 800003f8: 0000 unimp + 800003fa: 0000 unimp + 800003fc: 0000 unimp + 800003fe: 0000 unimp + 80000400: 0000 unimp + 80000402: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-srai.elf b/test/riscv/tests/rv64ui-p-srai.elf Binary files differnew file mode 100755 index 00000000..4ffa0b72 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-srai.elf diff --git a/test/riscv/tests/rv64ui-p-sraiw.dump b/test/riscv/tests/rv64ui-p-sraiw.dump new file mode 100644 index 00000000..c45179f8 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sraiw.dump @@ -0,0 +1,359 @@ + +rv64ui-p-sraiw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 800000b7 lui ra,0x80000 + 80000100: 4000df1b sraiw t5,ra,0x0 + 80000104: 80000eb7 lui t4,0x80000 + 80000108: 00200193 li gp,2 + 8000010c: 2ddf1c63 bne t5,t4,800003e4 <fail> + +0000000080000110 <test_3>: + 80000110: 800000b7 lui ra,0x80000 + 80000114: 4010df1b sraiw t5,ra,0x1 + 80000118: c0000eb7 lui t4,0xc0000 + 8000011c: 00300193 li gp,3 + 80000120: 2ddf1263 bne t5,t4,800003e4 <fail> + +0000000080000124 <test_4>: + 80000124: 800000b7 lui ra,0x80000 + 80000128: 4070df1b sraiw t5,ra,0x7 + 8000012c: ff000eb7 lui t4,0xff000 + 80000130: 00400193 li gp,4 + 80000134: 2bdf1863 bne t5,t4,800003e4 <fail> + +0000000080000138 <test_5>: + 80000138: 800000b7 lui ra,0x80000 + 8000013c: 40e0df1b sraiw t5,ra,0xe + 80000140: fffe0eb7 lui t4,0xfffe0 + 80000144: 00500193 li gp,5 + 80000148: 29df1e63 bne t5,t4,800003e4 <fail> + +000000008000014c <test_6>: + 8000014c: 800000b7 lui ra,0x80000 + 80000150: 0010809b addiw ra,ra,1 + 80000154: 41f0df1b sraiw t5,ra,0x1f + 80000158: fff00e93 li t4,-1 + 8000015c: 00600193 li gp,6 + 80000160: 29df1263 bne t5,t4,800003e4 <fail> + +0000000080000164 <test_7>: + 80000164: 800000b7 lui ra,0x80000 + 80000168: fff0809b addiw ra,ra,-1 + 8000016c: 4000df1b sraiw t5,ra,0x0 + 80000170: 80000eb7 lui t4,0x80000 + 80000174: fffe8e9b addiw t4,t4,-1 + 80000178: 00700193 li gp,7 + 8000017c: 27df1463 bne t5,t4,800003e4 <fail> + +0000000080000180 <test_8>: + 80000180: 800000b7 lui ra,0x80000 + 80000184: fff0809b addiw ra,ra,-1 + 80000188: 4010df1b sraiw t5,ra,0x1 + 8000018c: 40000eb7 lui t4,0x40000 + 80000190: fffe8e9b addiw t4,t4,-1 + 80000194: 00800193 li gp,8 + 80000198: 25df1663 bne t5,t4,800003e4 <fail> + +000000008000019c <test_9>: + 8000019c: 800000b7 lui ra,0x80000 + 800001a0: fff0809b addiw ra,ra,-1 + 800001a4: 4070df1b sraiw t5,ra,0x7 + 800001a8: 01000eb7 lui t4,0x1000 + 800001ac: fffe8e9b addiw t4,t4,-1 + 800001b0: 00900193 li gp,9 + 800001b4: 23df1863 bne t5,t4,800003e4 <fail> + +00000000800001b8 <test_10>: + 800001b8: 800000b7 lui ra,0x80000 + 800001bc: fff0809b addiw ra,ra,-1 + 800001c0: 40e0df1b sraiw t5,ra,0xe + 800001c4: 00020eb7 lui t4,0x20 + 800001c8: fffe8e9b addiw t4,t4,-1 + 800001cc: 00a00193 li gp,10 + 800001d0: 21df1a63 bne t5,t4,800003e4 <fail> + +00000000800001d4 <test_11>: + 800001d4: 800000b7 lui ra,0x80000 + 800001d8: fff0809b addiw ra,ra,-1 + 800001dc: 41f0df1b sraiw t5,ra,0x1f + 800001e0: 00000e93 li t4,0 + 800001e4: 00b00193 li gp,11 + 800001e8: 1fdf1e63 bne t5,t4,800003e4 <fail> + +00000000800001ec <test_12>: + 800001ec: 818180b7 lui ra,0x81818 + 800001f0: 1810809b addiw ra,ra,385 + 800001f4: 4000df1b sraiw t5,ra,0x0 + 800001f8: 81818eb7 lui t4,0x81818 + 800001fc: 181e8e9b addiw t4,t4,385 + 80000200: 00c00193 li gp,12 + 80000204: 1fdf1063 bne t5,t4,800003e4 <fail> + +0000000080000208 <test_13>: + 80000208: 818180b7 lui ra,0x81818 + 8000020c: 1810809b addiw ra,ra,385 + 80000210: 4010df1b sraiw t5,ra,0x1 + 80000214: c0c0ceb7 lui t4,0xc0c0c + 80000218: 0c0e8e9b addiw t4,t4,192 + 8000021c: 00d00193 li gp,13 + 80000220: 1ddf1263 bne t5,t4,800003e4 <fail> + +0000000080000224 <test_14>: + 80000224: 818180b7 lui ra,0x81818 + 80000228: 1810809b addiw ra,ra,385 + 8000022c: 4070df1b sraiw t5,ra,0x7 + 80000230: ff030eb7 lui t4,0xff030 + 80000234: 303e8e9b addiw t4,t4,771 + 80000238: 00e00193 li gp,14 + 8000023c: 1bdf1463 bne t5,t4,800003e4 <fail> + +0000000080000240 <test_15>: + 80000240: 818180b7 lui ra,0x81818 + 80000244: 1810809b addiw ra,ra,385 + 80000248: 40e0df1b sraiw t5,ra,0xe + 8000024c: fffe0eb7 lui t4,0xfffe0 + 80000250: 606e8e9b addiw t4,t4,1542 + 80000254: 00f00193 li gp,15 + 80000258: 19df1663 bne t5,t4,800003e4 <fail> + +000000008000025c <test_16>: + 8000025c: 818180b7 lui ra,0x81818 + 80000260: 1810809b addiw ra,ra,385 + 80000264: 41f0df1b sraiw t5,ra,0x1f + 80000268: fff00e93 li t4,-1 + 8000026c: 01000193 li gp,16 + 80000270: 17df1a63 bne t5,t4,800003e4 <fail> + +0000000080000274 <test_17>: + 80000274: 800000b7 lui ra,0x80000 + 80000278: 4070d09b sraiw ra,ra,0x7 + 8000027c: ff000eb7 lui t4,0xff000 + 80000280: 01100193 li gp,17 + 80000284: 17d09063 bne ra,t4,800003e4 <fail> + +0000000080000288 <test_18>: + 80000288: 00000213 li tp,0 + 8000028c: 800000b7 lui ra,0x80000 + 80000290: 4070df1b sraiw t5,ra,0x7 + 80000294: 000f0313 mv t1,t5 + 80000298: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000029c: 00200293 li t0,2 + 800002a0: fe5216e3 bne tp,t0,8000028c <test_18+0x4> + 800002a4: ff000eb7 lui t4,0xff000 + 800002a8: 01200193 li gp,18 + 800002ac: 13d31c63 bne t1,t4,800003e4 <fail> + +00000000800002b0 <test_19>: + 800002b0: 00000213 li tp,0 + 800002b4: 800000b7 lui ra,0x80000 + 800002b8: 40e0df1b sraiw t5,ra,0xe + 800002bc: 00000013 nop + 800002c0: 000f0313 mv t1,t5 + 800002c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002c8: 00200293 li t0,2 + 800002cc: fe5214e3 bne tp,t0,800002b4 <test_19+0x4> + 800002d0: fffe0eb7 lui t4,0xfffe0 + 800002d4: 01300193 li gp,19 + 800002d8: 11d31663 bne t1,t4,800003e4 <fail> + +00000000800002dc <test_20>: + 800002dc: 00000213 li tp,0 + 800002e0: 800000b7 lui ra,0x80000 + 800002e4: 0010809b addiw ra,ra,1 + 800002e8: 41f0df1b sraiw t5,ra,0x1f + 800002ec: 00000013 nop + 800002f0: 00000013 nop + 800002f4: 000f0313 mv t1,t5 + 800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002fc: 00200293 li t0,2 + 80000300: fe5210e3 bne tp,t0,800002e0 <test_20+0x4> + 80000304: fff00e93 li t4,-1 + 80000308: 01400193 li gp,20 + 8000030c: 0dd31c63 bne t1,t4,800003e4 <fail> + +0000000080000310 <test_21>: + 80000310: 00000213 li tp,0 + 80000314: 800000b7 lui ra,0x80000 + 80000318: 4070df1b sraiw t5,ra,0x7 + 8000031c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000320: 00200293 li t0,2 + 80000324: fe5218e3 bne tp,t0,80000314 <test_21+0x4> + 80000328: ff000eb7 lui t4,0xff000 + 8000032c: 01500193 li gp,21 + 80000330: 0bdf1a63 bne t5,t4,800003e4 <fail> + +0000000080000334 <test_22>: + 80000334: 00000213 li tp,0 + 80000338: 800000b7 lui ra,0x80000 + 8000033c: 00000013 nop + 80000340: 40e0df1b sraiw t5,ra,0xe + 80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000348: 00200293 li t0,2 + 8000034c: fe5216e3 bne tp,t0,80000338 <test_22+0x4> + 80000350: fffe0eb7 lui t4,0xfffe0 + 80000354: 01600193 li gp,22 + 80000358: 09df1663 bne t5,t4,800003e4 <fail> + +000000008000035c <test_23>: + 8000035c: 00000213 li tp,0 + 80000360: 800000b7 lui ra,0x80000 + 80000364: 0010809b addiw ra,ra,1 + 80000368: 00000013 nop + 8000036c: 00000013 nop + 80000370: 41f0df1b sraiw t5,ra,0x1f + 80000374: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000378: 00200293 li t0,2 + 8000037c: fe5212e3 bne tp,t0,80000360 <test_23+0x4> + 80000380: fff00e93 li t4,-1 + 80000384: 01700193 li gp,23 + 80000388: 05df1e63 bne t5,t4,800003e4 <fail> + +000000008000038c <test_24>: + 8000038c: 41f0509b sraiw ra,zero,0x1f + 80000390: 00000e93 li t4,0 + 80000394: 01800193 li gp,24 + 80000398: 05d09663 bne ra,t4,800003e4 <fail> + +000000008000039c <test_25>: + 8000039c: 01f00093 li ra,31 + 800003a0: 41c0d01b sraiw zero,ra,0x1c + 800003a4: 00000e93 li t4,0 + 800003a8: 01900193 li gp,25 + 800003ac: 03d01c63 bne zero,t4,800003e4 <fail> + +00000000800003b0 <test_26>: + 800003b0: 0070009b addiw ra,zero,7 + 800003b4: 03509093 slli ra,ra,0x35 + 800003b8: 41c0df1b sraiw t5,ra,0x1c + 800003bc: 00000e93 li t4,0 + 800003c0: 01a00193 li gp,26 + 800003c4: 03df1063 bne t5,t4,800003e4 <fail> + +00000000800003c8 <test_27>: + 800003c8: 00f0009b addiw ra,zero,15 + 800003cc: 01c09093 slli ra,ra,0x1c + 800003d0: 4040df1b sraiw t5,ra,0x4 + 800003d4: ff000eb7 lui t4,0xff000 + 800003d8: 01b00193 li gp,27 + 800003dc: 01df1463 bne t5,t4,800003e4 <fail> + 800003e0: 00301c63 bne zero,gp,800003f8 <pass> + +00000000800003e4 <fail>: + 800003e4: 0ff0000f fence + 800003e8: 00018063 beqz gp,800003e8 <fail+0x4> + 800003ec: 00119193 slli gp,gp,0x1 + 800003f0: 0011e193 ori gp,gp,1 + 800003f4: 00000073 ecall + +00000000800003f8 <pass>: + 800003f8: 0ff0000f fence + 800003fc: 00100193 li gp,1 + 80000400: 00000073 ecall + 80000404: c0001073 unimp + 80000408: 0000 unimp + 8000040a: 0000 unimp + 8000040c: 0000 unimp + 8000040e: 0000 unimp + 80000410: 0000 unimp + 80000412: 0000 unimp + 80000414: 0000 unimp + 80000416: 0000 unimp + 80000418: 0000 unimp + 8000041a: 0000 unimp + 8000041c: 0000 unimp + 8000041e: 0000 unimp + 80000420: 0000 unimp + 80000422: 0000 unimp + 80000424: 0000 unimp + 80000426: 0000 unimp + 80000428: 0000 unimp + 8000042a: 0000 unimp + 8000042c: 0000 unimp + 8000042e: 0000 unimp + 80000430: 0000 unimp + 80000432: 0000 unimp + 80000434: 0000 unimp + 80000436: 0000 unimp + 80000438: 0000 unimp + 8000043a: 0000 unimp + 8000043c: 0000 unimp + 8000043e: 0000 unimp + 80000440: 0000 unimp + 80000442: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sraiw.elf b/test/riscv/tests/rv64ui-p-sraiw.elf Binary files differnew file mode 100755 index 00000000..34dfe773 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sraiw.elf diff --git a/test/riscv/tests/rv64ui-p-sraw.dump b/test/riscv/tests/rv64ui-p-sraw.dump new file mode 100644 index 00000000..dc65ff46 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sraw.dump @@ -0,0 +1,538 @@ + +rv64ui-p-sraw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 800000b7 lui ra,0x80000 + 80000100: 00000113 li sp,0 + 80000104: 4020df3b sraw t5,ra,sp + 80000108: 80000eb7 lui t4,0x80000 + 8000010c: 00200193 li gp,2 + 80000110: 59df1463 bne t5,t4,80000698 <fail> + +0000000080000114 <test_3>: + 80000114: 800000b7 lui ra,0x80000 + 80000118: 00100113 li sp,1 + 8000011c: 4020df3b sraw t5,ra,sp + 80000120: c0000eb7 lui t4,0xc0000 + 80000124: 00300193 li gp,3 + 80000128: 57df1863 bne t5,t4,80000698 <fail> + +000000008000012c <test_4>: + 8000012c: 800000b7 lui ra,0x80000 + 80000130: 00700113 li sp,7 + 80000134: 4020df3b sraw t5,ra,sp + 80000138: ff000eb7 lui t4,0xff000 + 8000013c: 00400193 li gp,4 + 80000140: 55df1c63 bne t5,t4,80000698 <fail> + +0000000080000144 <test_5>: + 80000144: 800000b7 lui ra,0x80000 + 80000148: 00e00113 li sp,14 + 8000014c: 4020df3b sraw t5,ra,sp + 80000150: fffe0eb7 lui t4,0xfffe0 + 80000154: 00500193 li gp,5 + 80000158: 55df1063 bne t5,t4,80000698 <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 0010809b addiw ra,ra,1 + 80000164: 01f00113 li sp,31 + 80000168: 4020df3b sraw t5,ra,sp + 8000016c: fff00e93 li t4,-1 + 80000170: 00600193 li gp,6 + 80000174: 53df1263 bne t5,t4,80000698 <fail> + +0000000080000178 <test_7>: + 80000178: 800000b7 lui ra,0x80000 + 8000017c: fff0809b addiw ra,ra,-1 + 80000180: 00000113 li sp,0 + 80000184: 4020df3b sraw t5,ra,sp + 80000188: 80000eb7 lui t4,0x80000 + 8000018c: fffe8e9b addiw t4,t4,-1 + 80000190: 00700193 li gp,7 + 80000194: 51df1263 bne t5,t4,80000698 <fail> + +0000000080000198 <test_8>: + 80000198: 800000b7 lui ra,0x80000 + 8000019c: fff0809b addiw ra,ra,-1 + 800001a0: 00100113 li sp,1 + 800001a4: 4020df3b sraw t5,ra,sp + 800001a8: 40000eb7 lui t4,0x40000 + 800001ac: fffe8e9b addiw t4,t4,-1 + 800001b0: 00800193 li gp,8 + 800001b4: 4fdf1263 bne t5,t4,80000698 <fail> + +00000000800001b8 <test_9>: + 800001b8: 800000b7 lui ra,0x80000 + 800001bc: fff0809b addiw ra,ra,-1 + 800001c0: 00700113 li sp,7 + 800001c4: 4020df3b sraw t5,ra,sp + 800001c8: 01000eb7 lui t4,0x1000 + 800001cc: fffe8e9b addiw t4,t4,-1 + 800001d0: 00900193 li gp,9 + 800001d4: 4ddf1263 bne t5,t4,80000698 <fail> + +00000000800001d8 <test_10>: + 800001d8: 800000b7 lui ra,0x80000 + 800001dc: fff0809b addiw ra,ra,-1 + 800001e0: 00e00113 li sp,14 + 800001e4: 4020df3b sraw t5,ra,sp + 800001e8: 00020eb7 lui t4,0x20 + 800001ec: fffe8e9b addiw t4,t4,-1 + 800001f0: 00a00193 li gp,10 + 800001f4: 4bdf1263 bne t5,t4,80000698 <fail> + +00000000800001f8 <test_11>: + 800001f8: 800000b7 lui ra,0x80000 + 800001fc: fff0809b addiw ra,ra,-1 + 80000200: 01f00113 li sp,31 + 80000204: 4020df3b sraw t5,ra,sp + 80000208: 00000e93 li t4,0 + 8000020c: 00b00193 li gp,11 + 80000210: 49df1463 bne t5,t4,80000698 <fail> + +0000000080000214 <test_12>: + 80000214: 818180b7 lui ra,0x81818 + 80000218: 1810809b addiw ra,ra,385 + 8000021c: 00000113 li sp,0 + 80000220: 4020df3b sraw t5,ra,sp + 80000224: 81818eb7 lui t4,0x81818 + 80000228: 181e8e9b addiw t4,t4,385 + 8000022c: 00c00193 li gp,12 + 80000230: 47df1463 bne t5,t4,80000698 <fail> + +0000000080000234 <test_13>: + 80000234: 818180b7 lui ra,0x81818 + 80000238: 1810809b addiw ra,ra,385 + 8000023c: 00100113 li sp,1 + 80000240: 4020df3b sraw t5,ra,sp + 80000244: c0c0ceb7 lui t4,0xc0c0c + 80000248: 0c0e8e9b addiw t4,t4,192 + 8000024c: 00d00193 li gp,13 + 80000250: 45df1463 bne t5,t4,80000698 <fail> + +0000000080000254 <test_14>: + 80000254: 818180b7 lui ra,0x81818 + 80000258: 1810809b addiw ra,ra,385 + 8000025c: 00700113 li sp,7 + 80000260: 4020df3b sraw t5,ra,sp + 80000264: ff030eb7 lui t4,0xff030 + 80000268: 303e8e9b addiw t4,t4,771 + 8000026c: 00e00193 li gp,14 + 80000270: 43df1463 bne t5,t4,80000698 <fail> + +0000000080000274 <test_15>: + 80000274: 818180b7 lui ra,0x81818 + 80000278: 1810809b addiw ra,ra,385 + 8000027c: 00e00113 li sp,14 + 80000280: 4020df3b sraw t5,ra,sp + 80000284: fffe0eb7 lui t4,0xfffe0 + 80000288: 606e8e9b addiw t4,t4,1542 + 8000028c: 00f00193 li gp,15 + 80000290: 41df1463 bne t5,t4,80000698 <fail> + +0000000080000294 <test_16>: + 80000294: 818180b7 lui ra,0x81818 + 80000298: 1810809b addiw ra,ra,385 + 8000029c: 01f00113 li sp,31 + 800002a0: 4020df3b sraw t5,ra,sp + 800002a4: fff00e93 li t4,-1 + 800002a8: 01000193 li gp,16 + 800002ac: 3fdf1663 bne t5,t4,80000698 <fail> + +00000000800002b0 <test_17>: + 800002b0: 818180b7 lui ra,0x81818 + 800002b4: 1810809b addiw ra,ra,385 + 800002b8: fe000113 li sp,-32 + 800002bc: 4020df3b sraw t5,ra,sp + 800002c0: 81818eb7 lui t4,0x81818 + 800002c4: 181e8e9b addiw t4,t4,385 + 800002c8: 01100193 li gp,17 + 800002cc: 3ddf1663 bne t5,t4,80000698 <fail> + +00000000800002d0 <test_18>: + 800002d0: 818180b7 lui ra,0x81818 + 800002d4: 1810809b addiw ra,ra,385 + 800002d8: fe100113 li sp,-31 + 800002dc: 4020df3b sraw t5,ra,sp + 800002e0: c0c0ceb7 lui t4,0xc0c0c + 800002e4: 0c0e8e9b addiw t4,t4,192 + 800002e8: 01200193 li gp,18 + 800002ec: 3bdf1663 bne t5,t4,80000698 <fail> + +00000000800002f0 <test_19>: + 800002f0: 818180b7 lui ra,0x81818 + 800002f4: 1810809b addiw ra,ra,385 + 800002f8: fe700113 li sp,-25 + 800002fc: 4020df3b sraw t5,ra,sp + 80000300: ff030eb7 lui t4,0xff030 + 80000304: 303e8e9b addiw t4,t4,771 + 80000308: 01300193 li gp,19 + 8000030c: 39df1663 bne t5,t4,80000698 <fail> + +0000000080000310 <test_20>: + 80000310: 818180b7 lui ra,0x81818 + 80000314: 1810809b addiw ra,ra,385 + 80000318: fee00113 li sp,-18 + 8000031c: 4020df3b sraw t5,ra,sp + 80000320: fffe0eb7 lui t4,0xfffe0 + 80000324: 606e8e9b addiw t4,t4,1542 + 80000328: 01400193 li gp,20 + 8000032c: 37df1663 bne t5,t4,80000698 <fail> + +0000000080000330 <test_21>: + 80000330: 818180b7 lui ra,0x81818 + 80000334: 1810809b addiw ra,ra,385 + 80000338: fff00113 li sp,-1 + 8000033c: 4020df3b sraw t5,ra,sp + 80000340: fff00e93 li t4,-1 + 80000344: 01500193 li gp,21 + 80000348: 35df1863 bne t5,t4,80000698 <fail> + +000000008000034c <test_22>: + 8000034c: 800000b7 lui ra,0x80000 + 80000350: 00700113 li sp,7 + 80000354: 4020d0bb sraw ra,ra,sp + 80000358: ff000eb7 lui t4,0xff000 + 8000035c: 01600193 li gp,22 + 80000360: 33d09c63 bne ra,t4,80000698 <fail> + +0000000080000364 <test_23>: + 80000364: 800000b7 lui ra,0x80000 + 80000368: 00e00113 li sp,14 + 8000036c: 4020d13b sraw sp,ra,sp + 80000370: fffe0eb7 lui t4,0xfffe0 + 80000374: 01700193 li gp,23 + 80000378: 33d11063 bne sp,t4,80000698 <fail> + +000000008000037c <test_24>: + 8000037c: 00700093 li ra,7 + 80000380: 4010d0bb sraw ra,ra,ra + 80000384: 00000e93 li t4,0 + 80000388: 01800193 li gp,24 + 8000038c: 31d09663 bne ra,t4,80000698 <fail> + +0000000080000390 <test_25>: + 80000390: 00000213 li tp,0 + 80000394: 800000b7 lui ra,0x80000 + 80000398: 00700113 li sp,7 + 8000039c: 4020df3b sraw t5,ra,sp + 800003a0: 000f0313 mv t1,t5 + 800003a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003a8: 00200293 li t0,2 + 800003ac: fe5214e3 bne tp,t0,80000394 <test_25+0x4> + 800003b0: ff000eb7 lui t4,0xff000 + 800003b4: 01900193 li gp,25 + 800003b8: 2fd31063 bne t1,t4,80000698 <fail> + +00000000800003bc <test_26>: + 800003bc: 00000213 li tp,0 + 800003c0: 800000b7 lui ra,0x80000 + 800003c4: 00e00113 li sp,14 + 800003c8: 4020df3b sraw t5,ra,sp + 800003cc: 00000013 nop + 800003d0: 000f0313 mv t1,t5 + 800003d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003d8: 00200293 li t0,2 + 800003dc: fe5212e3 bne tp,t0,800003c0 <test_26+0x4> + 800003e0: fffe0eb7 lui t4,0xfffe0 + 800003e4: 01a00193 li gp,26 + 800003e8: 2bd31863 bne t1,t4,80000698 <fail> + +00000000800003ec <test_27>: + 800003ec: 00000213 li tp,0 + 800003f0: 800000b7 lui ra,0x80000 + 800003f4: 01f00113 li sp,31 + 800003f8: 4020df3b sraw t5,ra,sp + 800003fc: 00000013 nop + 80000400: 00000013 nop + 80000404: 000f0313 mv t1,t5 + 80000408: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000040c: 00200293 li t0,2 + 80000410: fe5210e3 bne tp,t0,800003f0 <test_27+0x4> + 80000414: fff00e93 li t4,-1 + 80000418: 01b00193 li gp,27 + 8000041c: 27d31e63 bne t1,t4,80000698 <fail> + +0000000080000420 <test_28>: + 80000420: 00000213 li tp,0 + 80000424: 800000b7 lui ra,0x80000 + 80000428: 00700113 li sp,7 + 8000042c: 4020df3b sraw t5,ra,sp + 80000430: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000434: 00200293 li t0,2 + 80000438: fe5216e3 bne tp,t0,80000424 <test_28+0x4> + 8000043c: ff000eb7 lui t4,0xff000 + 80000440: 01c00193 li gp,28 + 80000444: 25df1a63 bne t5,t4,80000698 <fail> + +0000000080000448 <test_29>: + 80000448: 00000213 li tp,0 + 8000044c: 800000b7 lui ra,0x80000 + 80000450: 00e00113 li sp,14 + 80000454: 00000013 nop + 80000458: 4020df3b sraw t5,ra,sp + 8000045c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000460: 00200293 li t0,2 + 80000464: fe5214e3 bne tp,t0,8000044c <test_29+0x4> + 80000468: fffe0eb7 lui t4,0xfffe0 + 8000046c: 01d00193 li gp,29 + 80000470: 23df1463 bne t5,t4,80000698 <fail> + +0000000080000474 <test_30>: + 80000474: 00000213 li tp,0 + 80000478: 800000b7 lui ra,0x80000 + 8000047c: 01f00113 li sp,31 + 80000480: 00000013 nop + 80000484: 00000013 nop + 80000488: 4020df3b sraw t5,ra,sp + 8000048c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000490: 00200293 li t0,2 + 80000494: fe5212e3 bne tp,t0,80000478 <test_30+0x4> + 80000498: fff00e93 li t4,-1 + 8000049c: 01e00193 li gp,30 + 800004a0: 1fdf1c63 bne t5,t4,80000698 <fail> + +00000000800004a4 <test_31>: + 800004a4: 00000213 li tp,0 + 800004a8: 800000b7 lui ra,0x80000 + 800004ac: 00000013 nop + 800004b0: 00700113 li sp,7 + 800004b4: 4020df3b sraw t5,ra,sp + 800004b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004bc: 00200293 li t0,2 + 800004c0: fe5214e3 bne tp,t0,800004a8 <test_31+0x4> + 800004c4: ff000eb7 lui t4,0xff000 + 800004c8: 01f00193 li gp,31 + 800004cc: 1ddf1663 bne t5,t4,80000698 <fail> + +00000000800004d0 <test_32>: + 800004d0: 00000213 li tp,0 + 800004d4: 800000b7 lui ra,0x80000 + 800004d8: 00000013 nop + 800004dc: 00e00113 li sp,14 + 800004e0: 00000013 nop + 800004e4: 4020df3b sraw t5,ra,sp + 800004e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004ec: 00200293 li t0,2 + 800004f0: fe5212e3 bne tp,t0,800004d4 <test_32+0x4> + 800004f4: fffe0eb7 lui t4,0xfffe0 + 800004f8: 02000193 li gp,32 + 800004fc: 19df1e63 bne t5,t4,80000698 <fail> + +0000000080000500 <test_33>: + 80000500: 00000213 li tp,0 + 80000504: 800000b7 lui ra,0x80000 + 80000508: 00000013 nop + 8000050c: 00000013 nop + 80000510: 01f00113 li sp,31 + 80000514: 4020df3b sraw t5,ra,sp + 80000518: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000051c: 00200293 li t0,2 + 80000520: fe5212e3 bne tp,t0,80000504 <test_33+0x4> + 80000524: fff00e93 li t4,-1 + 80000528: 02100193 li gp,33 + 8000052c: 17df1663 bne t5,t4,80000698 <fail> + +0000000080000530 <test_34>: + 80000530: 00000213 li tp,0 + 80000534: 00700113 li sp,7 + 80000538: 800000b7 lui ra,0x80000 + 8000053c: 4020df3b sraw t5,ra,sp + 80000540: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000544: 00200293 li t0,2 + 80000548: fe5216e3 bne tp,t0,80000534 <test_34+0x4> + 8000054c: ff000eb7 lui t4,0xff000 + 80000550: 02200193 li gp,34 + 80000554: 15df1263 bne t5,t4,80000698 <fail> + +0000000080000558 <test_35>: + 80000558: 00000213 li tp,0 + 8000055c: 00e00113 li sp,14 + 80000560: 800000b7 lui ra,0x80000 + 80000564: 00000013 nop + 80000568: 4020df3b sraw t5,ra,sp + 8000056c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000570: 00200293 li t0,2 + 80000574: fe5214e3 bne tp,t0,8000055c <test_35+0x4> + 80000578: fffe0eb7 lui t4,0xfffe0 + 8000057c: 02300193 li gp,35 + 80000580: 11df1c63 bne t5,t4,80000698 <fail> + +0000000080000584 <test_36>: + 80000584: 00000213 li tp,0 + 80000588: 01f00113 li sp,31 + 8000058c: 800000b7 lui ra,0x80000 + 80000590: 00000013 nop + 80000594: 00000013 nop + 80000598: 4020df3b sraw t5,ra,sp + 8000059c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005a0: 00200293 li t0,2 + 800005a4: fe5212e3 bne tp,t0,80000588 <test_36+0x4> + 800005a8: fff00e93 li t4,-1 + 800005ac: 02400193 li gp,36 + 800005b0: 0fdf1463 bne t5,t4,80000698 <fail> + +00000000800005b4 <test_37>: + 800005b4: 00000213 li tp,0 + 800005b8: 00700113 li sp,7 + 800005bc: 00000013 nop + 800005c0: 800000b7 lui ra,0x80000 + 800005c4: 4020df3b sraw t5,ra,sp + 800005c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005cc: 00200293 li t0,2 + 800005d0: fe5214e3 bne tp,t0,800005b8 <test_37+0x4> + 800005d4: ff000eb7 lui t4,0xff000 + 800005d8: 02500193 li gp,37 + 800005dc: 0bdf1e63 bne t5,t4,80000698 <fail> + +00000000800005e0 <test_38>: + 800005e0: 00000213 li tp,0 + 800005e4: 00e00113 li sp,14 + 800005e8: 00000013 nop + 800005ec: 800000b7 lui ra,0x80000 + 800005f0: 00000013 nop + 800005f4: 4020df3b sraw t5,ra,sp + 800005f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005fc: 00200293 li t0,2 + 80000600: fe5212e3 bne tp,t0,800005e4 <test_38+0x4> + 80000604: fffe0eb7 lui t4,0xfffe0 + 80000608: 02600193 li gp,38 + 8000060c: 09df1663 bne t5,t4,80000698 <fail> + +0000000080000610 <test_39>: + 80000610: 00000213 li tp,0 + 80000614: 01f00113 li sp,31 + 80000618: 00000013 nop + 8000061c: 00000013 nop + 80000620: 800000b7 lui ra,0x80000 + 80000624: 4020df3b sraw t5,ra,sp + 80000628: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000062c: 00200293 li t0,2 + 80000630: fe5212e3 bne tp,t0,80000614 <test_39+0x4> + 80000634: fff00e93 li t4,-1 + 80000638: 02700193 li gp,39 + 8000063c: 05df1e63 bne t5,t4,80000698 <fail> + +0000000080000640 <test_40>: + 80000640: 00f00093 li ra,15 + 80000644: 4010513b sraw sp,zero,ra + 80000648: 00000e93 li t4,0 + 8000064c: 02800193 li gp,40 + 80000650: 05d11463 bne sp,t4,80000698 <fail> + +0000000080000654 <test_41>: + 80000654: 02000093 li ra,32 + 80000658: 4000d13b sraw sp,ra,zero + 8000065c: 02000e93 li t4,32 + 80000660: 02900193 li gp,41 + 80000664: 03d11a63 bne sp,t4,80000698 <fail> + +0000000080000668 <test_42>: + 80000668: 400050bb sraw ra,zero,zero + 8000066c: 00000e93 li t4,0 + 80000670: 02a00193 li gp,42 + 80000674: 03d09263 bne ra,t4,80000698 <fail> + +0000000080000678 <test_43>: + 80000678: 40000093 li ra,1024 + 8000067c: 00001137 lui sp,0x1 + 80000680: 8001011b addiw sp,sp,-2048 + 80000684: 4020d03b sraw zero,ra,sp + 80000688: 00000e93 li t4,0 + 8000068c: 02b00193 li gp,43 + 80000690: 01d01463 bne zero,t4,80000698 <fail> + 80000694: 00301c63 bne zero,gp,800006ac <pass> + +0000000080000698 <fail>: + 80000698: 0ff0000f fence + 8000069c: 00018063 beqz gp,8000069c <fail+0x4> + 800006a0: 00119193 slli gp,gp,0x1 + 800006a4: 0011e193 ori gp,gp,1 + 800006a8: 00000073 ecall + +00000000800006ac <pass>: + 800006ac: 0ff0000f fence + 800006b0: 00100193 li gp,1 + 800006b4: 00000073 ecall + 800006b8: c0001073 unimp + 800006bc: 0000 unimp + 800006be: 0000 unimp + 800006c0: 0000 unimp + 800006c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sraw.elf b/test/riscv/tests/rv64ui-p-sraw.elf Binary files differnew file mode 100755 index 00000000..ec7baca6 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sraw.elf diff --git a/test/riscv/tests/rv64ui-p-srl.dump b/test/riscv/tests/rv64ui-p-srl.dump new file mode 100644 index 00000000..314069ff --- /dev/null +++ b/test/riscv/tests/rv64ui-p-srl.dump @@ -0,0 +1,575 @@ + +rv64ui-p-srl: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 800000b7 lui ra,0x80000 + 80000100: 00000113 li sp,0 + 80000104: 0020df33 srl t5,ra,sp + 80000108: 80000eb7 lui t4,0x80000 + 8000010c: 00200193 li gp,2 + 80000110: 5fdf1a63 bne t5,t4,80000704 <fail> + +0000000080000114 <test_3>: + 80000114: 800000b7 lui ra,0x80000 + 80000118: 00100113 li sp,1 + 8000011c: 0020df33 srl t5,ra,sp + 80000120: 00100e9b addiw t4,zero,1 + 80000124: 021e9e93 slli t4,t4,0x21 + 80000128: fffe8e93 addi t4,t4,-1 # ffffffff7fffffff <_end+0xfffffffeffffdfff> + 8000012c: 01ee9e93 slli t4,t4,0x1e + 80000130: 00300193 li gp,3 + 80000134: 5ddf1863 bne t5,t4,80000704 <fail> + +0000000080000138 <test_4>: + 80000138: 800000b7 lui ra,0x80000 + 8000013c: 00700113 li sp,7 + 80000140: 0020df33 srl t5,ra,sp + 80000144: 00100e9b addiw t4,zero,1 + 80000148: 021e9e93 slli t4,t4,0x21 + 8000014c: fffe8e93 addi t4,t4,-1 + 80000150: 018e9e93 slli t4,t4,0x18 + 80000154: 00400193 li gp,4 + 80000158: 5bdf1663 bne t5,t4,80000704 <fail> + +000000008000015c <test_5>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 00e00113 li sp,14 + 80000164: 0020df33 srl t5,ra,sp + 80000168: 00100e9b addiw t4,zero,1 + 8000016c: 021e9e93 slli t4,t4,0x21 + 80000170: fffe8e93 addi t4,t4,-1 + 80000174: 011e9e93 slli t4,t4,0x11 + 80000178: 00500193 li gp,5 + 8000017c: 59df1463 bne t5,t4,80000704 <fail> + +0000000080000180 <test_6>: + 80000180: 800000b7 lui ra,0x80000 + 80000184: 0010809b addiw ra,ra,1 + 80000188: 01f00113 li sp,31 + 8000018c: 0020df33 srl t5,ra,sp + 80000190: 00100e9b addiw t4,zero,1 + 80000194: 021e9e93 slli t4,t4,0x21 + 80000198: fffe8e93 addi t4,t4,-1 + 8000019c: 00600193 li gp,6 + 800001a0: 57df1263 bne t5,t4,80000704 <fail> + +00000000800001a4 <test_7>: + 800001a4: fff00093 li ra,-1 + 800001a8: 00000113 li sp,0 + 800001ac: 0020df33 srl t5,ra,sp + 800001b0: fff00e93 li t4,-1 + 800001b4: 00700193 li gp,7 + 800001b8: 55df1663 bne t5,t4,80000704 <fail> + +00000000800001bc <test_8>: + 800001bc: fff00093 li ra,-1 + 800001c0: 00100113 li sp,1 + 800001c4: 0020df33 srl t5,ra,sp + 800001c8: fff00e9b addiw t4,zero,-1 + 800001cc: 03fe9e93 slli t4,t4,0x3f + 800001d0: fffe8e93 addi t4,t4,-1 + 800001d4: 00800193 li gp,8 + 800001d8: 53df1663 bne t5,t4,80000704 <fail> + +00000000800001dc <test_9>: + 800001dc: fff00093 li ra,-1 + 800001e0: 00700113 li sp,7 + 800001e4: 0020df33 srl t5,ra,sp + 800001e8: 00100e9b addiw t4,zero,1 + 800001ec: 039e9e93 slli t4,t4,0x39 + 800001f0: fffe8e93 addi t4,t4,-1 + 800001f4: 00900193 li gp,9 + 800001f8: 51df1663 bne t5,t4,80000704 <fail> + +00000000800001fc <test_10>: + 800001fc: fff00093 li ra,-1 + 80000200: 00e00113 li sp,14 + 80000204: 0020df33 srl t5,ra,sp + 80000208: 00100e9b addiw t4,zero,1 + 8000020c: 032e9e93 slli t4,t4,0x32 + 80000210: fffe8e93 addi t4,t4,-1 + 80000214: 00a00193 li gp,10 + 80000218: 4fdf1663 bne t5,t4,80000704 <fail> + +000000008000021c <test_11>: + 8000021c: fff00093 li ra,-1 + 80000220: 01f00113 li sp,31 + 80000224: 0020df33 srl t5,ra,sp + 80000228: 00100e9b addiw t4,zero,1 + 8000022c: 021e9e93 slli t4,t4,0x21 + 80000230: fffe8e93 addi t4,t4,-1 + 80000234: 00b00193 li gp,11 + 80000238: 4ddf1663 bne t5,t4,80000704 <fail> + +000000008000023c <test_12>: + 8000023c: 212120b7 lui ra,0x21212 + 80000240: 1210809b addiw ra,ra,289 + 80000244: 00000113 li sp,0 + 80000248: 0020df33 srl t5,ra,sp + 8000024c: 21212eb7 lui t4,0x21212 + 80000250: 121e8e9b addiw t4,t4,289 + 80000254: 00c00193 li gp,12 + 80000258: 4bdf1663 bne t5,t4,80000704 <fail> + +000000008000025c <test_13>: + 8000025c: 212120b7 lui ra,0x21212 + 80000260: 1210809b addiw ra,ra,289 + 80000264: 00100113 li sp,1 + 80000268: 0020df33 srl t5,ra,sp + 8000026c: 10909eb7 lui t4,0x10909 + 80000270: 090e8e9b addiw t4,t4,144 + 80000274: 00d00193 li gp,13 + 80000278: 49df1663 bne t5,t4,80000704 <fail> + +000000008000027c <test_14>: + 8000027c: 212120b7 lui ra,0x21212 + 80000280: 1210809b addiw ra,ra,289 + 80000284: 00700113 li sp,7 + 80000288: 0020df33 srl t5,ra,sp + 8000028c: 00424eb7 lui t4,0x424 + 80000290: 242e8e9b addiw t4,t4,578 + 80000294: 00e00193 li gp,14 + 80000298: 47df1663 bne t5,t4,80000704 <fail> + +000000008000029c <test_15>: + 8000029c: 212120b7 lui ra,0x21212 + 800002a0: 1210809b addiw ra,ra,289 + 800002a4: 00e00113 li sp,14 + 800002a8: 0020df33 srl t5,ra,sp + 800002ac: 00008eb7 lui t4,0x8 + 800002b0: 484e8e9b addiw t4,t4,1156 + 800002b4: 00f00193 li gp,15 + 800002b8: 45df1663 bne t5,t4,80000704 <fail> + +00000000800002bc <test_16>: + 800002bc: 212120b7 lui ra,0x21212 + 800002c0: 1210809b addiw ra,ra,289 + 800002c4: 01f00113 li sp,31 + 800002c8: 0020df33 srl t5,ra,sp + 800002cc: 00000e93 li t4,0 + 800002d0: 01000193 li gp,16 + 800002d4: 43df1863 bne t5,t4,80000704 <fail> + +00000000800002d8 <test_17>: + 800002d8: 212120b7 lui ra,0x21212 + 800002dc: 1210809b addiw ra,ra,289 + 800002e0: fc000113 li sp,-64 + 800002e4: 0020df33 srl t5,ra,sp + 800002e8: 21212eb7 lui t4,0x21212 + 800002ec: 121e8e9b addiw t4,t4,289 + 800002f0: 01100193 li gp,17 + 800002f4: 41df1863 bne t5,t4,80000704 <fail> + +00000000800002f8 <test_18>: + 800002f8: 212120b7 lui ra,0x21212 + 800002fc: 1210809b addiw ra,ra,289 + 80000300: fc100113 li sp,-63 + 80000304: 0020df33 srl t5,ra,sp + 80000308: 10909eb7 lui t4,0x10909 + 8000030c: 090e8e9b addiw t4,t4,144 + 80000310: 01200193 li gp,18 + 80000314: 3fdf1863 bne t5,t4,80000704 <fail> + +0000000080000318 <test_19>: + 80000318: 212120b7 lui ra,0x21212 + 8000031c: 1210809b addiw ra,ra,289 + 80000320: fc700113 li sp,-57 + 80000324: 0020df33 srl t5,ra,sp + 80000328: 00424eb7 lui t4,0x424 + 8000032c: 242e8e9b addiw t4,t4,578 + 80000330: 01300193 li gp,19 + 80000334: 3ddf1863 bne t5,t4,80000704 <fail> + +0000000080000338 <test_20>: + 80000338: 212120b7 lui ra,0x21212 + 8000033c: 1210809b addiw ra,ra,289 + 80000340: fce00113 li sp,-50 + 80000344: 0020df33 srl t5,ra,sp + 80000348: 00008eb7 lui t4,0x8 + 8000034c: 484e8e9b addiw t4,t4,1156 + 80000350: 01400193 li gp,20 + 80000354: 3bdf1863 bne t5,t4,80000704 <fail> + +0000000080000358 <test_21>: + 80000358: 212120b7 lui ra,0x21212 + 8000035c: 1210809b addiw ra,ra,289 + 80000360: fff00113 li sp,-1 + 80000364: 0020df33 srl t5,ra,sp + 80000368: 00000e93 li t4,0 + 8000036c: 01500193 li gp,21 + 80000370: 39df1a63 bne t5,t4,80000704 <fail> + +0000000080000374 <test_22>: + 80000374: 0010009b addiw ra,zero,1 + 80000378: 01f09093 slli ra,ra,0x1f + 8000037c: 00700113 li sp,7 + 80000380: 0020d0b3 srl ra,ra,sp + 80000384: 01000eb7 lui t4,0x1000 + 80000388: 01600193 li gp,22 + 8000038c: 37d09c63 bne ra,t4,80000704 <fail> + +0000000080000390 <test_23>: + 80000390: 0010009b addiw ra,zero,1 + 80000394: 01f09093 slli ra,ra,0x1f + 80000398: 00e00113 li sp,14 + 8000039c: 0020d133 srl sp,ra,sp + 800003a0: 00020eb7 lui t4,0x20 + 800003a4: 01700193 li gp,23 + 800003a8: 35d11e63 bne sp,t4,80000704 <fail> + +00000000800003ac <test_24>: + 800003ac: 00700093 li ra,7 + 800003b0: 0010d0b3 srl ra,ra,ra + 800003b4: 00000e93 li t4,0 + 800003b8: 01800193 li gp,24 + 800003bc: 35d09463 bne ra,t4,80000704 <fail> + +00000000800003c0 <test_25>: + 800003c0: 00000213 li tp,0 + 800003c4: 0010009b addiw ra,zero,1 + 800003c8: 01f09093 slli ra,ra,0x1f + 800003cc: 00700113 li sp,7 + 800003d0: 0020df33 srl t5,ra,sp + 800003d4: 000f0313 mv t1,t5 + 800003d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003dc: 00200293 li t0,2 + 800003e0: fe5212e3 bne tp,t0,800003c4 <test_25+0x4> + 800003e4: 01000eb7 lui t4,0x1000 + 800003e8: 01900193 li gp,25 + 800003ec: 31d31c63 bne t1,t4,80000704 <fail> + +00000000800003f0 <test_26>: + 800003f0: 00000213 li tp,0 + 800003f4: 0010009b addiw ra,zero,1 + 800003f8: 01f09093 slli ra,ra,0x1f + 800003fc: 00e00113 li sp,14 + 80000400: 0020df33 srl t5,ra,sp + 80000404: 00000013 nop + 80000408: 000f0313 mv t1,t5 + 8000040c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000410: 00200293 li t0,2 + 80000414: fe5210e3 bne tp,t0,800003f4 <test_26+0x4> + 80000418: 00020eb7 lui t4,0x20 + 8000041c: 01a00193 li gp,26 + 80000420: 2fd31263 bne t1,t4,80000704 <fail> + +0000000080000424 <test_27>: + 80000424: 00000213 li tp,0 + 80000428: 0010009b addiw ra,zero,1 + 8000042c: 01f09093 slli ra,ra,0x1f + 80000430: 01f00113 li sp,31 + 80000434: 0020df33 srl t5,ra,sp + 80000438: 00000013 nop + 8000043c: 00000013 nop + 80000440: 000f0313 mv t1,t5 + 80000444: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000448: 00200293 li t0,2 + 8000044c: fc521ee3 bne tp,t0,80000428 <test_27+0x4> + 80000450: 00100e93 li t4,1 + 80000454: 01b00193 li gp,27 + 80000458: 2bd31663 bne t1,t4,80000704 <fail> + +000000008000045c <test_28>: + 8000045c: 00000213 li tp,0 + 80000460: 0010009b addiw ra,zero,1 + 80000464: 01f09093 slli ra,ra,0x1f + 80000468: 00700113 li sp,7 + 8000046c: 0020df33 srl t5,ra,sp + 80000470: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000474: 00200293 li t0,2 + 80000478: fe5214e3 bne tp,t0,80000460 <test_28+0x4> + 8000047c: 01000eb7 lui t4,0x1000 + 80000480: 01c00193 li gp,28 + 80000484: 29df1063 bne t5,t4,80000704 <fail> + +0000000080000488 <test_29>: + 80000488: 00000213 li tp,0 + 8000048c: 0010009b addiw ra,zero,1 + 80000490: 01f09093 slli ra,ra,0x1f + 80000494: 00e00113 li sp,14 + 80000498: 00000013 nop + 8000049c: 0020df33 srl t5,ra,sp + 800004a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004a4: 00200293 li t0,2 + 800004a8: fe5212e3 bne tp,t0,8000048c <test_29+0x4> + 800004ac: 00020eb7 lui t4,0x20 + 800004b0: 01d00193 li gp,29 + 800004b4: 25df1863 bne t5,t4,80000704 <fail> + +00000000800004b8 <test_30>: + 800004b8: 00000213 li tp,0 + 800004bc: 0010009b addiw ra,zero,1 + 800004c0: 01f09093 slli ra,ra,0x1f + 800004c4: 01f00113 li sp,31 + 800004c8: 00000013 nop + 800004cc: 00000013 nop + 800004d0: 0020df33 srl t5,ra,sp + 800004d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004d8: 00200293 li t0,2 + 800004dc: fe5210e3 bne tp,t0,800004bc <test_30+0x4> + 800004e0: 00100e93 li t4,1 + 800004e4: 01e00193 li gp,30 + 800004e8: 21df1e63 bne t5,t4,80000704 <fail> + +00000000800004ec <test_31>: + 800004ec: 00000213 li tp,0 + 800004f0: 0010009b addiw ra,zero,1 + 800004f4: 01f09093 slli ra,ra,0x1f + 800004f8: 00000013 nop + 800004fc: 00700113 li sp,7 + 80000500: 0020df33 srl t5,ra,sp + 80000504: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000508: 00200293 li t0,2 + 8000050c: fe5212e3 bne tp,t0,800004f0 <test_31+0x4> + 80000510: 01000eb7 lui t4,0x1000 + 80000514: 01f00193 li gp,31 + 80000518: 1fdf1663 bne t5,t4,80000704 <fail> + +000000008000051c <test_32>: + 8000051c: 00000213 li tp,0 + 80000520: 0010009b addiw ra,zero,1 + 80000524: 01f09093 slli ra,ra,0x1f + 80000528: 00000013 nop + 8000052c: 00e00113 li sp,14 + 80000530: 00000013 nop + 80000534: 0020df33 srl t5,ra,sp + 80000538: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000053c: 00200293 li t0,2 + 80000540: fe5210e3 bne tp,t0,80000520 <test_32+0x4> + 80000544: 00020eb7 lui t4,0x20 + 80000548: 02000193 li gp,32 + 8000054c: 1bdf1c63 bne t5,t4,80000704 <fail> + +0000000080000550 <test_33>: + 80000550: 00000213 li tp,0 + 80000554: 0010009b addiw ra,zero,1 + 80000558: 01f09093 slli ra,ra,0x1f + 8000055c: 00000013 nop + 80000560: 00000013 nop + 80000564: 01f00113 li sp,31 + 80000568: 0020df33 srl t5,ra,sp + 8000056c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000570: 00200293 li t0,2 + 80000574: fe5210e3 bne tp,t0,80000554 <test_33+0x4> + 80000578: 00100e93 li t4,1 + 8000057c: 02100193 li gp,33 + 80000580: 19df1263 bne t5,t4,80000704 <fail> + +0000000080000584 <test_34>: + 80000584: 00000213 li tp,0 + 80000588: 00700113 li sp,7 + 8000058c: 0010009b addiw ra,zero,1 + 80000590: 01f09093 slli ra,ra,0x1f + 80000594: 0020df33 srl t5,ra,sp + 80000598: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000059c: 00200293 li t0,2 + 800005a0: fe5214e3 bne tp,t0,80000588 <test_34+0x4> + 800005a4: 01000eb7 lui t4,0x1000 + 800005a8: 02200193 li gp,34 + 800005ac: 15df1c63 bne t5,t4,80000704 <fail> + +00000000800005b0 <test_35>: + 800005b0: 00000213 li tp,0 + 800005b4: 00e00113 li sp,14 + 800005b8: 0010009b addiw ra,zero,1 + 800005bc: 01f09093 slli ra,ra,0x1f + 800005c0: 00000013 nop + 800005c4: 0020df33 srl t5,ra,sp + 800005c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005cc: 00200293 li t0,2 + 800005d0: fe5212e3 bne tp,t0,800005b4 <test_35+0x4> + 800005d4: 00020eb7 lui t4,0x20 + 800005d8: 02300193 li gp,35 + 800005dc: 13df1463 bne t5,t4,80000704 <fail> + +00000000800005e0 <test_36>: + 800005e0: 00000213 li tp,0 + 800005e4: 01f00113 li sp,31 + 800005e8: 0010009b addiw ra,zero,1 + 800005ec: 01f09093 slli ra,ra,0x1f + 800005f0: 00000013 nop + 800005f4: 00000013 nop + 800005f8: 0020df33 srl t5,ra,sp + 800005fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000600: 00200293 li t0,2 + 80000604: fe5210e3 bne tp,t0,800005e4 <test_36+0x4> + 80000608: 00100e93 li t4,1 + 8000060c: 02400193 li gp,36 + 80000610: 0fdf1a63 bne t5,t4,80000704 <fail> + +0000000080000614 <test_37>: + 80000614: 00000213 li tp,0 + 80000618: 00700113 li sp,7 + 8000061c: 00000013 nop + 80000620: 0010009b addiw ra,zero,1 + 80000624: 01f09093 slli ra,ra,0x1f + 80000628: 0020df33 srl t5,ra,sp + 8000062c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000630: 00200293 li t0,2 + 80000634: fe5212e3 bne tp,t0,80000618 <test_37+0x4> + 80000638: 01000eb7 lui t4,0x1000 + 8000063c: 02500193 li gp,37 + 80000640: 0ddf1263 bne t5,t4,80000704 <fail> + +0000000080000644 <test_38>: + 80000644: 00000213 li tp,0 + 80000648: 00e00113 li sp,14 + 8000064c: 00000013 nop + 80000650: 0010009b addiw ra,zero,1 + 80000654: 01f09093 slli ra,ra,0x1f + 80000658: 00000013 nop + 8000065c: 0020df33 srl t5,ra,sp + 80000660: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000664: 00200293 li t0,2 + 80000668: fe5210e3 bne tp,t0,80000648 <test_38+0x4> + 8000066c: 00020eb7 lui t4,0x20 + 80000670: 02600193 li gp,38 + 80000674: 09df1863 bne t5,t4,80000704 <fail> + +0000000080000678 <test_39>: + 80000678: 00000213 li tp,0 + 8000067c: 01f00113 li sp,31 + 80000680: 00000013 nop + 80000684: 00000013 nop + 80000688: 0010009b addiw ra,zero,1 + 8000068c: 01f09093 slli ra,ra,0x1f + 80000690: 0020df33 srl t5,ra,sp + 80000694: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000698: 00200293 li t0,2 + 8000069c: fe5210e3 bne tp,t0,8000067c <test_39+0x4> + 800006a0: 00100e93 li t4,1 + 800006a4: 02700193 li gp,39 + 800006a8: 05df1e63 bne t5,t4,80000704 <fail> + +00000000800006ac <test_40>: + 800006ac: 00f00093 li ra,15 + 800006b0: 00105133 srl sp,zero,ra + 800006b4: 00000e93 li t4,0 + 800006b8: 02800193 li gp,40 + 800006bc: 05d11463 bne sp,t4,80000704 <fail> + +00000000800006c0 <test_41>: + 800006c0: 02000093 li ra,32 + 800006c4: 0000d133 srl sp,ra,zero + 800006c8: 02000e93 li t4,32 + 800006cc: 02900193 li gp,41 + 800006d0: 03d11a63 bne sp,t4,80000704 <fail> + +00000000800006d4 <test_42>: + 800006d4: 000050b3 srl ra,zero,zero + 800006d8: 00000e93 li t4,0 + 800006dc: 02a00193 li gp,42 + 800006e0: 03d09263 bne ra,t4,80000704 <fail> + +00000000800006e4 <test_43>: + 800006e4: 40000093 li ra,1024 + 800006e8: 00001137 lui sp,0x1 + 800006ec: 8001011b addiw sp,sp,-2048 + 800006f0: 0020d033 srl zero,ra,sp + 800006f4: 00000e93 li t4,0 + 800006f8: 02b00193 li gp,43 + 800006fc: 01d01463 bne zero,t4,80000704 <fail> + 80000700: 00301c63 bne zero,gp,80000718 <pass> + +0000000080000704 <fail>: + 80000704: 0ff0000f fence + 80000708: 00018063 beqz gp,80000708 <fail+0x4> + 8000070c: 00119193 slli gp,gp,0x1 + 80000710: 0011e193 ori gp,gp,1 + 80000714: 00000073 ecall + +0000000080000718 <pass>: + 80000718: 0ff0000f fence + 8000071c: 00100193 li gp,1 + 80000720: 00000073 ecall + 80000724: c0001073 unimp + 80000728: 0000 unimp + 8000072a: 0000 unimp + 8000072c: 0000 unimp + 8000072e: 0000 unimp + 80000730: 0000 unimp + 80000732: 0000 unimp + 80000734: 0000 unimp + 80000736: 0000 unimp + 80000738: 0000 unimp + 8000073a: 0000 unimp + 8000073c: 0000 unimp + 8000073e: 0000 unimp + 80000740: 0000 unimp + 80000742: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-srl.elf b/test/riscv/tests/rv64ui-p-srl.elf Binary files differnew file mode 100755 index 00000000..2da2e0ba --- /dev/null +++ b/test/riscv/tests/rv64ui-p-srl.elf diff --git a/test/riscv/tests/rv64ui-p-srli.dump b/test/riscv/tests/rv64ui-p-srli.dump new file mode 100644 index 00000000..bcb2df7a --- /dev/null +++ b/test/riscv/tests/rv64ui-p-srli.dump @@ -0,0 +1,350 @@ + +rv64ui-p-srli: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 800000b7 lui ra,0x80000 + 80000100: 0000df13 srli t5,ra,0x0 + 80000104: 80000eb7 lui t4,0x80000 + 80000108: 00200193 li gp,2 + 8000010c: 2fdf1663 bne t5,t4,800003f8 <fail> + +0000000080000110 <test_3>: + 80000110: 800000b7 lui ra,0x80000 + 80000114: 0010df13 srli t5,ra,0x1 + 80000118: 00100e9b addiw t4,zero,1 + 8000011c: 021e9e93 slli t4,t4,0x21 + 80000120: fffe8e93 addi t4,t4,-1 # ffffffff7fffffff <_end+0xfffffffeffffdfff> + 80000124: 01ee9e93 slli t4,t4,0x1e + 80000128: 00300193 li gp,3 + 8000012c: 2ddf1663 bne t5,t4,800003f8 <fail> + +0000000080000130 <test_4>: + 80000130: 800000b7 lui ra,0x80000 + 80000134: 0070df13 srli t5,ra,0x7 + 80000138: 00100e9b addiw t4,zero,1 + 8000013c: 021e9e93 slli t4,t4,0x21 + 80000140: fffe8e93 addi t4,t4,-1 + 80000144: 018e9e93 slli t4,t4,0x18 + 80000148: 00400193 li gp,4 + 8000014c: 2bdf1663 bne t5,t4,800003f8 <fail> + +0000000080000150 <test_5>: + 80000150: 800000b7 lui ra,0x80000 + 80000154: 00e0df13 srli t5,ra,0xe + 80000158: 00100e9b addiw t4,zero,1 + 8000015c: 021e9e93 slli t4,t4,0x21 + 80000160: fffe8e93 addi t4,t4,-1 + 80000164: 011e9e93 slli t4,t4,0x11 + 80000168: 00500193 li gp,5 + 8000016c: 29df1663 bne t5,t4,800003f8 <fail> + +0000000080000170 <test_6>: + 80000170: 800000b7 lui ra,0x80000 + 80000174: 0010809b addiw ra,ra,1 + 80000178: 01f0df13 srli t5,ra,0x1f + 8000017c: 00100e9b addiw t4,zero,1 + 80000180: 021e9e93 slli t4,t4,0x21 + 80000184: fffe8e93 addi t4,t4,-1 + 80000188: 00600193 li gp,6 + 8000018c: 27df1663 bne t5,t4,800003f8 <fail> + +0000000080000190 <test_7>: + 80000190: fff00093 li ra,-1 + 80000194: 0000df13 srli t5,ra,0x0 + 80000198: fff00e93 li t4,-1 + 8000019c: 00700193 li gp,7 + 800001a0: 25df1c63 bne t5,t4,800003f8 <fail> + +00000000800001a4 <test_8>: + 800001a4: fff00093 li ra,-1 + 800001a8: 0010df13 srli t5,ra,0x1 + 800001ac: fff00e9b addiw t4,zero,-1 + 800001b0: 03fe9e93 slli t4,t4,0x3f + 800001b4: fffe8e93 addi t4,t4,-1 + 800001b8: 00800193 li gp,8 + 800001bc: 23df1e63 bne t5,t4,800003f8 <fail> + +00000000800001c0 <test_9>: + 800001c0: fff00093 li ra,-1 + 800001c4: 0070df13 srli t5,ra,0x7 + 800001c8: 00100e9b addiw t4,zero,1 + 800001cc: 039e9e93 slli t4,t4,0x39 + 800001d0: fffe8e93 addi t4,t4,-1 + 800001d4: 00900193 li gp,9 + 800001d8: 23df1063 bne t5,t4,800003f8 <fail> + +00000000800001dc <test_10>: + 800001dc: fff00093 li ra,-1 + 800001e0: 00e0df13 srli t5,ra,0xe + 800001e4: 00100e9b addiw t4,zero,1 + 800001e8: 032e9e93 slli t4,t4,0x32 + 800001ec: fffe8e93 addi t4,t4,-1 + 800001f0: 00a00193 li gp,10 + 800001f4: 21df1263 bne t5,t4,800003f8 <fail> + +00000000800001f8 <test_11>: + 800001f8: fff00093 li ra,-1 + 800001fc: 01f0df13 srli t5,ra,0x1f + 80000200: 00100e9b addiw t4,zero,1 + 80000204: 021e9e93 slli t4,t4,0x21 + 80000208: fffe8e93 addi t4,t4,-1 + 8000020c: 00b00193 li gp,11 + 80000210: 1fdf1463 bne t5,t4,800003f8 <fail> + +0000000080000214 <test_12>: + 80000214: 212120b7 lui ra,0x21212 + 80000218: 1210809b addiw ra,ra,289 + 8000021c: 0000df13 srli t5,ra,0x0 + 80000220: 21212eb7 lui t4,0x21212 + 80000224: 121e8e9b addiw t4,t4,289 + 80000228: 00c00193 li gp,12 + 8000022c: 1ddf1663 bne t5,t4,800003f8 <fail> + +0000000080000230 <test_13>: + 80000230: 212120b7 lui ra,0x21212 + 80000234: 1210809b addiw ra,ra,289 + 80000238: 0010df13 srli t5,ra,0x1 + 8000023c: 10909eb7 lui t4,0x10909 + 80000240: 090e8e9b addiw t4,t4,144 + 80000244: 00d00193 li gp,13 + 80000248: 1bdf1863 bne t5,t4,800003f8 <fail> + +000000008000024c <test_14>: + 8000024c: 212120b7 lui ra,0x21212 + 80000250: 1210809b addiw ra,ra,289 + 80000254: 0070df13 srli t5,ra,0x7 + 80000258: 00424eb7 lui t4,0x424 + 8000025c: 242e8e9b addiw t4,t4,578 + 80000260: 00e00193 li gp,14 + 80000264: 19df1a63 bne t5,t4,800003f8 <fail> + +0000000080000268 <test_15>: + 80000268: 212120b7 lui ra,0x21212 + 8000026c: 1210809b addiw ra,ra,289 + 80000270: 00e0df13 srli t5,ra,0xe + 80000274: 00008eb7 lui t4,0x8 + 80000278: 484e8e9b addiw t4,t4,1156 + 8000027c: 00f00193 li gp,15 + 80000280: 17df1c63 bne t5,t4,800003f8 <fail> + +0000000080000284 <test_16>: + 80000284: 212120b7 lui ra,0x21212 + 80000288: 1210809b addiw ra,ra,289 + 8000028c: 01f0df13 srli t5,ra,0x1f + 80000290: 00000e93 li t4,0 + 80000294: 01000193 li gp,16 + 80000298: 17df1063 bne t5,t4,800003f8 <fail> + +000000008000029c <test_17>: + 8000029c: 0010009b addiw ra,zero,1 + 800002a0: 01f09093 slli ra,ra,0x1f + 800002a4: 0070d093 srli ra,ra,0x7 + 800002a8: 01000eb7 lui t4,0x1000 + 800002ac: 01100193 li gp,17 + 800002b0: 15d09463 bne ra,t4,800003f8 <fail> + +00000000800002b4 <test_18>: + 800002b4: 00000213 li tp,0 + 800002b8: 0010009b addiw ra,zero,1 + 800002bc: 01f09093 slli ra,ra,0x1f + 800002c0: 0070df13 srli t5,ra,0x7 + 800002c4: 000f0313 mv t1,t5 + 800002c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002cc: 00200293 li t0,2 + 800002d0: fe5214e3 bne tp,t0,800002b8 <test_18+0x4> + 800002d4: 01000eb7 lui t4,0x1000 + 800002d8: 01200193 li gp,18 + 800002dc: 11d31e63 bne t1,t4,800003f8 <fail> + +00000000800002e0 <test_19>: + 800002e0: 00000213 li tp,0 + 800002e4: 0010009b addiw ra,zero,1 + 800002e8: 01f09093 slli ra,ra,0x1f + 800002ec: 00e0df13 srli t5,ra,0xe + 800002f0: 00000013 nop + 800002f4: 000f0313 mv t1,t5 + 800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002fc: 00200293 li t0,2 + 80000300: fe5212e3 bne tp,t0,800002e4 <test_19+0x4> + 80000304: 00020eb7 lui t4,0x20 + 80000308: 01300193 li gp,19 + 8000030c: 0fd31663 bne t1,t4,800003f8 <fail> + +0000000080000310 <test_20>: + 80000310: 00000213 li tp,0 + 80000314: 0010009b addiw ra,zero,1 + 80000318: 01f09093 slli ra,ra,0x1f + 8000031c: 00108093 addi ra,ra,1 # 21212001 <_start-0x5ededfff> + 80000320: 01f0df13 srli t5,ra,0x1f + 80000324: 00000013 nop + 80000328: 00000013 nop + 8000032c: 000f0313 mv t1,t5 + 80000330: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000334: 00200293 li t0,2 + 80000338: fc521ee3 bne tp,t0,80000314 <test_20+0x4> + 8000033c: 00100e93 li t4,1 + 80000340: 01400193 li gp,20 + 80000344: 0bd31a63 bne t1,t4,800003f8 <fail> + +0000000080000348 <test_21>: + 80000348: 00000213 li tp,0 + 8000034c: 0010009b addiw ra,zero,1 + 80000350: 01f09093 slli ra,ra,0x1f + 80000354: 0070df13 srli t5,ra,0x7 + 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000035c: 00200293 li t0,2 + 80000360: fe5216e3 bne tp,t0,8000034c <test_21+0x4> + 80000364: 01000eb7 lui t4,0x1000 + 80000368: 01500193 li gp,21 + 8000036c: 09df1663 bne t5,t4,800003f8 <fail> + +0000000080000370 <test_22>: + 80000370: 00000213 li tp,0 + 80000374: 0010009b addiw ra,zero,1 + 80000378: 01f09093 slli ra,ra,0x1f + 8000037c: 00000013 nop + 80000380: 00e0df13 srli t5,ra,0xe + 80000384: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000388: 00200293 li t0,2 + 8000038c: fe5214e3 bne tp,t0,80000374 <test_22+0x4> + 80000390: 00020eb7 lui t4,0x20 + 80000394: 01600193 li gp,22 + 80000398: 07df1063 bne t5,t4,800003f8 <fail> + +000000008000039c <test_23>: + 8000039c: 00000213 li tp,0 + 800003a0: 0010009b addiw ra,zero,1 + 800003a4: 01f09093 slli ra,ra,0x1f + 800003a8: 00108093 addi ra,ra,1 + 800003ac: 00000013 nop + 800003b0: 00000013 nop + 800003b4: 01f0df13 srli t5,ra,0x1f + 800003b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003bc: 00200293 li t0,2 + 800003c0: fe5210e3 bne tp,t0,800003a0 <test_23+0x4> + 800003c4: 00100e93 li t4,1 + 800003c8: 01700193 li gp,23 + 800003cc: 03df1663 bne t5,t4,800003f8 <fail> + +00000000800003d0 <test_24>: + 800003d0: 00405093 srli ra,zero,0x4 + 800003d4: 00000e93 li t4,0 + 800003d8: 01800193 li gp,24 + 800003dc: 01d09e63 bne ra,t4,800003f8 <fail> + +00000000800003e0 <test_25>: + 800003e0: 02100093 li ra,33 + 800003e4: 00a0d013 srli zero,ra,0xa + 800003e8: 00000e93 li t4,0 + 800003ec: 01900193 li gp,25 + 800003f0: 01d01463 bne zero,t4,800003f8 <fail> + 800003f4: 00301c63 bne zero,gp,8000040c <pass> + +00000000800003f8 <fail>: + 800003f8: 0ff0000f fence + 800003fc: 00018063 beqz gp,800003fc <fail+0x4> + 80000400: 00119193 slli gp,gp,0x1 + 80000404: 0011e193 ori gp,gp,1 + 80000408: 00000073 ecall + +000000008000040c <pass>: + 8000040c: 0ff0000f fence + 80000410: 00100193 li gp,1 + 80000414: 00000073 ecall + 80000418: c0001073 unimp + 8000041c: 0000 unimp + 8000041e: 0000 unimp + 80000420: 0000 unimp + 80000422: 0000 unimp + 80000424: 0000 unimp + 80000426: 0000 unimp + 80000428: 0000 unimp + 8000042a: 0000 unimp + 8000042c: 0000 unimp + 8000042e: 0000 unimp + 80000430: 0000 unimp + 80000432: 0000 unimp + 80000434: 0000 unimp + 80000436: 0000 unimp + 80000438: 0000 unimp + 8000043a: 0000 unimp + 8000043c: 0000 unimp + 8000043e: 0000 unimp + 80000440: 0000 unimp + 80000442: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-srli.elf b/test/riscv/tests/rv64ui-p-srli.elf Binary files differnew file mode 100755 index 00000000..73d7db18 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-srli.elf diff --git a/test/riscv/tests/rv64ui-p-srliw.dump b/test/riscv/tests/rv64ui-p-srliw.dump new file mode 100644 index 00000000..99581fb6 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-srliw.dump @@ -0,0 +1,309 @@ + +rv64ui-p-srliw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 800000b7 lui ra,0x80000 + 80000100: 0000df1b srliw t5,ra,0x0 + 80000104: 80000eb7 lui t4,0x80000 + 80000108: 00200193 li gp,2 + 8000010c: 29df1863 bne t5,t4,8000039c <fail> + +0000000080000110 <test_3>: + 80000110: 800000b7 lui ra,0x80000 + 80000114: 0010df1b srliw t5,ra,0x1 + 80000118: 40000eb7 lui t4,0x40000 + 8000011c: 00300193 li gp,3 + 80000120: 27df1e63 bne t5,t4,8000039c <fail> + +0000000080000124 <test_4>: + 80000124: 800000b7 lui ra,0x80000 + 80000128: 0070df1b srliw t5,ra,0x7 + 8000012c: 01000eb7 lui t4,0x1000 + 80000130: 00400193 li gp,4 + 80000134: 27df1463 bne t5,t4,8000039c <fail> + +0000000080000138 <test_5>: + 80000138: 800000b7 lui ra,0x80000 + 8000013c: 00e0df1b srliw t5,ra,0xe + 80000140: 00020eb7 lui t4,0x20 + 80000144: 00500193 li gp,5 + 80000148: 25df1a63 bne t5,t4,8000039c <fail> + +000000008000014c <test_6>: + 8000014c: 800000b7 lui ra,0x80000 + 80000150: 0010809b addiw ra,ra,1 + 80000154: 01f0df1b srliw t5,ra,0x1f + 80000158: 00100e93 li t4,1 + 8000015c: 00600193 li gp,6 + 80000160: 23df1e63 bne t5,t4,8000039c <fail> + +0000000080000164 <test_7>: + 80000164: fff00093 li ra,-1 + 80000168: 0000df1b srliw t5,ra,0x0 + 8000016c: fff00e93 li t4,-1 + 80000170: 00700193 li gp,7 + 80000174: 23df1463 bne t5,t4,8000039c <fail> + +0000000080000178 <test_8>: + 80000178: fff00093 li ra,-1 + 8000017c: 0010df1b srliw t5,ra,0x1 + 80000180: 80000eb7 lui t4,0x80000 + 80000184: fffe8e9b addiw t4,t4,-1 + 80000188: 00800193 li gp,8 + 8000018c: 21df1863 bne t5,t4,8000039c <fail> + +0000000080000190 <test_9>: + 80000190: fff00093 li ra,-1 + 80000194: 0070df1b srliw t5,ra,0x7 + 80000198: 02000eb7 lui t4,0x2000 + 8000019c: fffe8e9b addiw t4,t4,-1 + 800001a0: 00900193 li gp,9 + 800001a4: 1fdf1c63 bne t5,t4,8000039c <fail> + +00000000800001a8 <test_10>: + 800001a8: fff00093 li ra,-1 + 800001ac: 00e0df1b srliw t5,ra,0xe + 800001b0: 00040eb7 lui t4,0x40 + 800001b4: fffe8e9b addiw t4,t4,-1 + 800001b8: 00a00193 li gp,10 + 800001bc: 1fdf1063 bne t5,t4,8000039c <fail> + +00000000800001c0 <test_11>: + 800001c0: fff00093 li ra,-1 + 800001c4: 01f0df1b srliw t5,ra,0x1f + 800001c8: 00100e93 li t4,1 + 800001cc: 00b00193 li gp,11 + 800001d0: 1ddf1663 bne t5,t4,8000039c <fail> + +00000000800001d4 <test_12>: + 800001d4: 212120b7 lui ra,0x21212 + 800001d8: 1210809b addiw ra,ra,289 + 800001dc: 0000df1b srliw t5,ra,0x0 + 800001e0: 21212eb7 lui t4,0x21212 + 800001e4: 121e8e9b addiw t4,t4,289 + 800001e8: 00c00193 li gp,12 + 800001ec: 1bdf1863 bne t5,t4,8000039c <fail> + +00000000800001f0 <test_13>: + 800001f0: 212120b7 lui ra,0x21212 + 800001f4: 1210809b addiw ra,ra,289 + 800001f8: 0010df1b srliw t5,ra,0x1 + 800001fc: 10909eb7 lui t4,0x10909 + 80000200: 090e8e9b addiw t4,t4,144 + 80000204: 00d00193 li gp,13 + 80000208: 19df1a63 bne t5,t4,8000039c <fail> + +000000008000020c <test_14>: + 8000020c: 212120b7 lui ra,0x21212 + 80000210: 1210809b addiw ra,ra,289 + 80000214: 0070df1b srliw t5,ra,0x7 + 80000218: 00424eb7 lui t4,0x424 + 8000021c: 242e8e9b addiw t4,t4,578 + 80000220: 00e00193 li gp,14 + 80000224: 17df1c63 bne t5,t4,8000039c <fail> + +0000000080000228 <test_15>: + 80000228: 212120b7 lui ra,0x21212 + 8000022c: 1210809b addiw ra,ra,289 + 80000230: 00e0df1b srliw t5,ra,0xe + 80000234: 00008eb7 lui t4,0x8 + 80000238: 484e8e9b addiw t4,t4,1156 + 8000023c: 00f00193 li gp,15 + 80000240: 15df1e63 bne t5,t4,8000039c <fail> + +0000000080000244 <test_16>: + 80000244: 212120b7 lui ra,0x21212 + 80000248: 1210809b addiw ra,ra,289 + 8000024c: 01f0df1b srliw t5,ra,0x1f + 80000250: 00000e93 li t4,0 + 80000254: 01000193 li gp,16 + 80000258: 15df1263 bne t5,t4,8000039c <fail> + +000000008000025c <test_17>: + 8000025c: 800000b7 lui ra,0x80000 + 80000260: 0070d09b srliw ra,ra,0x7 + 80000264: 01000eb7 lui t4,0x1000 + 80000268: 01100193 li gp,17 + 8000026c: 13d09863 bne ra,t4,8000039c <fail> + +0000000080000270 <test_18>: + 80000270: 00000213 li tp,0 + 80000274: 800000b7 lui ra,0x80000 + 80000278: 0070df1b srliw t5,ra,0x7 + 8000027c: 000f0313 mv t1,t5 + 80000280: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000284: 00200293 li t0,2 + 80000288: fe5216e3 bne tp,t0,80000274 <test_18+0x4> + 8000028c: 01000eb7 lui t4,0x1000 + 80000290: 01200193 li gp,18 + 80000294: 11d31463 bne t1,t4,8000039c <fail> + +0000000080000298 <test_19>: + 80000298: 00000213 li tp,0 + 8000029c: 800000b7 lui ra,0x80000 + 800002a0: 00e0df1b srliw t5,ra,0xe + 800002a4: 00000013 nop + 800002a8: 000f0313 mv t1,t5 + 800002ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002b0: 00200293 li t0,2 + 800002b4: fe5214e3 bne tp,t0,8000029c <test_19+0x4> + 800002b8: 00020eb7 lui t4,0x20 + 800002bc: 01300193 li gp,19 + 800002c0: 0dd31e63 bne t1,t4,8000039c <fail> + +00000000800002c4 <test_20>: + 800002c4: 00000213 li tp,0 + 800002c8: 800000b7 lui ra,0x80000 + 800002cc: 0010809b addiw ra,ra,1 + 800002d0: 01f0df1b srliw t5,ra,0x1f + 800002d4: 00000013 nop + 800002d8: 00000013 nop + 800002dc: 000f0313 mv t1,t5 + 800002e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002e4: 00200293 li t0,2 + 800002e8: fe5210e3 bne tp,t0,800002c8 <test_20+0x4> + 800002ec: 00100e93 li t4,1 + 800002f0: 01400193 li gp,20 + 800002f4: 0bd31463 bne t1,t4,8000039c <fail> + +00000000800002f8 <test_21>: + 800002f8: 00000213 li tp,0 + 800002fc: 800000b7 lui ra,0x80000 + 80000300: 0070df1b srliw t5,ra,0x7 + 80000304: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000308: 00200293 li t0,2 + 8000030c: fe5218e3 bne tp,t0,800002fc <test_21+0x4> + 80000310: 01000eb7 lui t4,0x1000 + 80000314: 01500193 li gp,21 + 80000318: 09df1263 bne t5,t4,8000039c <fail> + +000000008000031c <test_22>: + 8000031c: 00000213 li tp,0 + 80000320: 800000b7 lui ra,0x80000 + 80000324: 00000013 nop + 80000328: 00e0df1b srliw t5,ra,0xe + 8000032c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000330: 00200293 li t0,2 + 80000334: fe5216e3 bne tp,t0,80000320 <test_22+0x4> + 80000338: 00020eb7 lui t4,0x20 + 8000033c: 01600193 li gp,22 + 80000340: 05df1e63 bne t5,t4,8000039c <fail> + +0000000080000344 <test_23>: + 80000344: 00000213 li tp,0 + 80000348: 800000b7 lui ra,0x80000 + 8000034c: 0010809b addiw ra,ra,1 + 80000350: 00000013 nop + 80000354: 00000013 nop + 80000358: 01f0df1b srliw t5,ra,0x1f + 8000035c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000360: 00200293 li t0,2 + 80000364: fe5212e3 bne tp,t0,80000348 <test_23+0x4> + 80000368: 00100e93 li t4,1 + 8000036c: 01700193 li gp,23 + 80000370: 03df1663 bne t5,t4,8000039c <fail> + +0000000080000374 <test_24>: + 80000374: 01f0509b srliw ra,zero,0x1f + 80000378: 00000e93 li t4,0 + 8000037c: 01800193 li gp,24 + 80000380: 01d09e63 bne ra,t4,8000039c <fail> + +0000000080000384 <test_25>: + 80000384: 01f00093 li ra,31 + 80000388: 01c0d01b srliw zero,ra,0x1c + 8000038c: 00000e93 li t4,0 + 80000390: 01900193 li gp,25 + 80000394: 01d01463 bne zero,t4,8000039c <fail> + 80000398: 00301c63 bne zero,gp,800003b0 <pass> + +000000008000039c <fail>: + 8000039c: 0ff0000f fence + 800003a0: 00018063 beqz gp,800003a0 <fail+0x4> + 800003a4: 00119193 slli gp,gp,0x1 + 800003a8: 0011e193 ori gp,gp,1 + 800003ac: 00000073 ecall + +00000000800003b0 <pass>: + 800003b0: 0ff0000f fence + 800003b4: 00100193 li gp,1 + 800003b8: 00000073 ecall + 800003bc: c0001073 unimp + 800003c0: 0000 unimp + 800003c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-srliw.elf b/test/riscv/tests/rv64ui-p-srliw.elf Binary files differnew file mode 100755 index 00000000..2dc12254 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-srliw.elf diff --git a/test/riscv/tests/rv64ui-p-srlw.dump b/test/riscv/tests/rv64ui-p-srlw.dump new file mode 100644 index 00000000..cf3f8377 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-srlw.dump @@ -0,0 +1,544 @@ + +rv64ui-p-srlw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 800000b7 lui ra,0x80000 + 80000100: 00000113 li sp,0 + 80000104: 0020df3b srlw t5,ra,sp + 80000108: 80000eb7 lui t4,0x80000 + 8000010c: 00200193 li gp,2 + 80000110: 57df1863 bne t5,t4,80000680 <fail> + +0000000080000114 <test_3>: + 80000114: 800000b7 lui ra,0x80000 + 80000118: 00100113 li sp,1 + 8000011c: 0020df3b srlw t5,ra,sp + 80000120: 40000eb7 lui t4,0x40000 + 80000124: 00300193 li gp,3 + 80000128: 55df1c63 bne t5,t4,80000680 <fail> + +000000008000012c <test_4>: + 8000012c: 800000b7 lui ra,0x80000 + 80000130: 00700113 li sp,7 + 80000134: 0020df3b srlw t5,ra,sp + 80000138: 01000eb7 lui t4,0x1000 + 8000013c: 00400193 li gp,4 + 80000140: 55df1063 bne t5,t4,80000680 <fail> + +0000000080000144 <test_5>: + 80000144: 800000b7 lui ra,0x80000 + 80000148: 00e00113 li sp,14 + 8000014c: 0020df3b srlw t5,ra,sp + 80000150: 00020eb7 lui t4,0x20 + 80000154: 00500193 li gp,5 + 80000158: 53df1463 bne t5,t4,80000680 <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 0010809b addiw ra,ra,1 + 80000164: 01f00113 li sp,31 + 80000168: 0020df3b srlw t5,ra,sp + 8000016c: 00100e93 li t4,1 + 80000170: 00600193 li gp,6 + 80000174: 51df1663 bne t5,t4,80000680 <fail> + +0000000080000178 <test_7>: + 80000178: fff00093 li ra,-1 + 8000017c: 00000113 li sp,0 + 80000180: 0020df3b srlw t5,ra,sp + 80000184: fff00e93 li t4,-1 + 80000188: 00700193 li gp,7 + 8000018c: 4fdf1a63 bne t5,t4,80000680 <fail> + +0000000080000190 <test_8>: + 80000190: fff00093 li ra,-1 + 80000194: 00100113 li sp,1 + 80000198: 0020df3b srlw t5,ra,sp + 8000019c: 80000eb7 lui t4,0x80000 + 800001a0: fffe8e9b addiw t4,t4,-1 + 800001a4: 00800193 li gp,8 + 800001a8: 4ddf1c63 bne t5,t4,80000680 <fail> + +00000000800001ac <test_9>: + 800001ac: fff00093 li ra,-1 + 800001b0: 00700113 li sp,7 + 800001b4: 0020df3b srlw t5,ra,sp + 800001b8: 02000eb7 lui t4,0x2000 + 800001bc: fffe8e9b addiw t4,t4,-1 + 800001c0: 00900193 li gp,9 + 800001c4: 4bdf1e63 bne t5,t4,80000680 <fail> + +00000000800001c8 <test_10>: + 800001c8: fff00093 li ra,-1 + 800001cc: 00e00113 li sp,14 + 800001d0: 0020df3b srlw t5,ra,sp + 800001d4: 00040eb7 lui t4,0x40 + 800001d8: fffe8e9b addiw t4,t4,-1 + 800001dc: 00a00193 li gp,10 + 800001e0: 4bdf1063 bne t5,t4,80000680 <fail> + +00000000800001e4 <test_11>: + 800001e4: fff00093 li ra,-1 + 800001e8: 01f00113 li sp,31 + 800001ec: 0020df3b srlw t5,ra,sp + 800001f0: 00100e93 li t4,1 + 800001f4: 00b00193 li gp,11 + 800001f8: 49df1463 bne t5,t4,80000680 <fail> + +00000000800001fc <test_12>: + 800001fc: 212120b7 lui ra,0x21212 + 80000200: 1210809b addiw ra,ra,289 + 80000204: 00000113 li sp,0 + 80000208: 0020df3b srlw t5,ra,sp + 8000020c: 21212eb7 lui t4,0x21212 + 80000210: 121e8e9b addiw t4,t4,289 + 80000214: 00c00193 li gp,12 + 80000218: 47df1463 bne t5,t4,80000680 <fail> + +000000008000021c <test_13>: + 8000021c: 212120b7 lui ra,0x21212 + 80000220: 1210809b addiw ra,ra,289 + 80000224: 00100113 li sp,1 + 80000228: 0020df3b srlw t5,ra,sp + 8000022c: 10909eb7 lui t4,0x10909 + 80000230: 090e8e9b addiw t4,t4,144 + 80000234: 00d00193 li gp,13 + 80000238: 45df1463 bne t5,t4,80000680 <fail> + +000000008000023c <test_14>: + 8000023c: 212120b7 lui ra,0x21212 + 80000240: 1210809b addiw ra,ra,289 + 80000244: 00700113 li sp,7 + 80000248: 0020df3b srlw t5,ra,sp + 8000024c: 00424eb7 lui t4,0x424 + 80000250: 242e8e9b addiw t4,t4,578 + 80000254: 00e00193 li gp,14 + 80000258: 43df1463 bne t5,t4,80000680 <fail> + +000000008000025c <test_15>: + 8000025c: 212120b7 lui ra,0x21212 + 80000260: 1210809b addiw ra,ra,289 + 80000264: 00e00113 li sp,14 + 80000268: 0020df3b srlw t5,ra,sp + 8000026c: 00008eb7 lui t4,0x8 + 80000270: 484e8e9b addiw t4,t4,1156 + 80000274: 00f00193 li gp,15 + 80000278: 41df1463 bne t5,t4,80000680 <fail> + +000000008000027c <test_16>: + 8000027c: 212120b7 lui ra,0x21212 + 80000280: 1210809b addiw ra,ra,289 + 80000284: 01f00113 li sp,31 + 80000288: 0020df3b srlw t5,ra,sp + 8000028c: 00000e93 li t4,0 + 80000290: 01000193 li gp,16 + 80000294: 3fdf1663 bne t5,t4,80000680 <fail> + +0000000080000298 <test_17>: + 80000298: 212120b7 lui ra,0x21212 + 8000029c: 1210809b addiw ra,ra,289 + 800002a0: fe000113 li sp,-32 + 800002a4: 0020df3b srlw t5,ra,sp + 800002a8: 21212eb7 lui t4,0x21212 + 800002ac: 121e8e9b addiw t4,t4,289 + 800002b0: 01100193 li gp,17 + 800002b4: 3ddf1663 bne t5,t4,80000680 <fail> + +00000000800002b8 <test_18>: + 800002b8: 212120b7 lui ra,0x21212 + 800002bc: 1210809b addiw ra,ra,289 + 800002c0: fe100113 li sp,-31 + 800002c4: 0020df3b srlw t5,ra,sp + 800002c8: 10909eb7 lui t4,0x10909 + 800002cc: 090e8e9b addiw t4,t4,144 + 800002d0: 01200193 li gp,18 + 800002d4: 3bdf1663 bne t5,t4,80000680 <fail> + +00000000800002d8 <test_19>: + 800002d8: 212120b7 lui ra,0x21212 + 800002dc: 1210809b addiw ra,ra,289 + 800002e0: fe700113 li sp,-25 + 800002e4: 0020df3b srlw t5,ra,sp + 800002e8: 00424eb7 lui t4,0x424 + 800002ec: 242e8e9b addiw t4,t4,578 + 800002f0: 01300193 li gp,19 + 800002f4: 39df1663 bne t5,t4,80000680 <fail> + +00000000800002f8 <test_20>: + 800002f8: 212120b7 lui ra,0x21212 + 800002fc: 1210809b addiw ra,ra,289 + 80000300: fee00113 li sp,-18 + 80000304: 0020df3b srlw t5,ra,sp + 80000308: 00008eb7 lui t4,0x8 + 8000030c: 484e8e9b addiw t4,t4,1156 + 80000310: 01400193 li gp,20 + 80000314: 37df1663 bne t5,t4,80000680 <fail> + +0000000080000318 <test_21>: + 80000318: 212120b7 lui ra,0x21212 + 8000031c: 1210809b addiw ra,ra,289 + 80000320: fff00113 li sp,-1 + 80000324: 0020df3b srlw t5,ra,sp + 80000328: 00000e93 li t4,0 + 8000032c: 01500193 li gp,21 + 80000330: 35df1863 bne t5,t4,80000680 <fail> + +0000000080000334 <test_22>: + 80000334: 800000b7 lui ra,0x80000 + 80000338: 00700113 li sp,7 + 8000033c: 0020d0bb srlw ra,ra,sp + 80000340: 01000eb7 lui t4,0x1000 + 80000344: 01600193 li gp,22 + 80000348: 33d09c63 bne ra,t4,80000680 <fail> + +000000008000034c <test_23>: + 8000034c: 800000b7 lui ra,0x80000 + 80000350: 00e00113 li sp,14 + 80000354: 0020d13b srlw sp,ra,sp + 80000358: 00020eb7 lui t4,0x20 + 8000035c: 01700193 li gp,23 + 80000360: 33d11063 bne sp,t4,80000680 <fail> + +0000000080000364 <test_24>: + 80000364: 00700093 li ra,7 + 80000368: 0010d0bb srlw ra,ra,ra + 8000036c: 00000e93 li t4,0 + 80000370: 01800193 li gp,24 + 80000374: 31d09663 bne ra,t4,80000680 <fail> + +0000000080000378 <test_25>: + 80000378: 00000213 li tp,0 + 8000037c: 800000b7 lui ra,0x80000 + 80000380: 00700113 li sp,7 + 80000384: 0020df3b srlw t5,ra,sp + 80000388: 000f0313 mv t1,t5 + 8000038c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000390: 00200293 li t0,2 + 80000394: fe5214e3 bne tp,t0,8000037c <test_25+0x4> + 80000398: 01000eb7 lui t4,0x1000 + 8000039c: 01900193 li gp,25 + 800003a0: 2fd31063 bne t1,t4,80000680 <fail> + +00000000800003a4 <test_26>: + 800003a4: 00000213 li tp,0 + 800003a8: 800000b7 lui ra,0x80000 + 800003ac: 00e00113 li sp,14 + 800003b0: 0020df3b srlw t5,ra,sp + 800003b4: 00000013 nop + 800003b8: 000f0313 mv t1,t5 + 800003bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003c0: 00200293 li t0,2 + 800003c4: fe5212e3 bne tp,t0,800003a8 <test_26+0x4> + 800003c8: 00020eb7 lui t4,0x20 + 800003cc: 01a00193 li gp,26 + 800003d0: 2bd31863 bne t1,t4,80000680 <fail> + +00000000800003d4 <test_27>: + 800003d4: 00000213 li tp,0 + 800003d8: 800000b7 lui ra,0x80000 + 800003dc: 01f00113 li sp,31 + 800003e0: 0020df3b srlw t5,ra,sp + 800003e4: 00000013 nop + 800003e8: 00000013 nop + 800003ec: 000f0313 mv t1,t5 + 800003f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003f4: 00200293 li t0,2 + 800003f8: fe5210e3 bne tp,t0,800003d8 <test_27+0x4> + 800003fc: 00100e93 li t4,1 + 80000400: 01b00193 li gp,27 + 80000404: 27d31e63 bne t1,t4,80000680 <fail> + +0000000080000408 <test_28>: + 80000408: 00000213 li tp,0 + 8000040c: 800000b7 lui ra,0x80000 + 80000410: 00700113 li sp,7 + 80000414: 0020df3b srlw t5,ra,sp + 80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000041c: 00200293 li t0,2 + 80000420: fe5216e3 bne tp,t0,8000040c <test_28+0x4> + 80000424: 01000eb7 lui t4,0x1000 + 80000428: 01c00193 li gp,28 + 8000042c: 25df1a63 bne t5,t4,80000680 <fail> + +0000000080000430 <test_29>: + 80000430: 00000213 li tp,0 + 80000434: 800000b7 lui ra,0x80000 + 80000438: 00e00113 li sp,14 + 8000043c: 00000013 nop + 80000440: 0020df3b srlw t5,ra,sp + 80000444: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000448: 00200293 li t0,2 + 8000044c: fe5214e3 bne tp,t0,80000434 <test_29+0x4> + 80000450: 00020eb7 lui t4,0x20 + 80000454: 01d00193 li gp,29 + 80000458: 23df1463 bne t5,t4,80000680 <fail> + +000000008000045c <test_30>: + 8000045c: 00000213 li tp,0 + 80000460: 800000b7 lui ra,0x80000 + 80000464: 01f00113 li sp,31 + 80000468: 00000013 nop + 8000046c: 00000013 nop + 80000470: 0020df3b srlw t5,ra,sp + 80000474: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000478: 00200293 li t0,2 + 8000047c: fe5212e3 bne tp,t0,80000460 <test_30+0x4> + 80000480: 00100e93 li t4,1 + 80000484: 01e00193 li gp,30 + 80000488: 1fdf1c63 bne t5,t4,80000680 <fail> + +000000008000048c <test_31>: + 8000048c: 00000213 li tp,0 + 80000490: 800000b7 lui ra,0x80000 + 80000494: 00000013 nop + 80000498: 00700113 li sp,7 + 8000049c: 0020df3b srlw t5,ra,sp + 800004a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004a4: 00200293 li t0,2 + 800004a8: fe5214e3 bne tp,t0,80000490 <test_31+0x4> + 800004ac: 01000eb7 lui t4,0x1000 + 800004b0: 01f00193 li gp,31 + 800004b4: 1ddf1663 bne t5,t4,80000680 <fail> + +00000000800004b8 <test_32>: + 800004b8: 00000213 li tp,0 + 800004bc: 800000b7 lui ra,0x80000 + 800004c0: 00000013 nop + 800004c4: 00e00113 li sp,14 + 800004c8: 00000013 nop + 800004cc: 0020df3b srlw t5,ra,sp + 800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004d4: 00200293 li t0,2 + 800004d8: fe5212e3 bne tp,t0,800004bc <test_32+0x4> + 800004dc: 00020eb7 lui t4,0x20 + 800004e0: 02000193 li gp,32 + 800004e4: 19df1e63 bne t5,t4,80000680 <fail> + +00000000800004e8 <test_33>: + 800004e8: 00000213 li tp,0 + 800004ec: 800000b7 lui ra,0x80000 + 800004f0: 00000013 nop + 800004f4: 00000013 nop + 800004f8: 01f00113 li sp,31 + 800004fc: 0020df3b srlw t5,ra,sp + 80000500: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000504: 00200293 li t0,2 + 80000508: fe5212e3 bne tp,t0,800004ec <test_33+0x4> + 8000050c: 00100e93 li t4,1 + 80000510: 02100193 li gp,33 + 80000514: 17df1663 bne t5,t4,80000680 <fail> + +0000000080000518 <test_34>: + 80000518: 00000213 li tp,0 + 8000051c: 00700113 li sp,7 + 80000520: 800000b7 lui ra,0x80000 + 80000524: 0020df3b srlw t5,ra,sp + 80000528: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000052c: 00200293 li t0,2 + 80000530: fe5216e3 bne tp,t0,8000051c <test_34+0x4> + 80000534: 01000eb7 lui t4,0x1000 + 80000538: 02200193 li gp,34 + 8000053c: 15df1263 bne t5,t4,80000680 <fail> + +0000000080000540 <test_35>: + 80000540: 00000213 li tp,0 + 80000544: 00e00113 li sp,14 + 80000548: 800000b7 lui ra,0x80000 + 8000054c: 00000013 nop + 80000550: 0020df3b srlw t5,ra,sp + 80000554: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000558: 00200293 li t0,2 + 8000055c: fe5214e3 bne tp,t0,80000544 <test_35+0x4> + 80000560: 00020eb7 lui t4,0x20 + 80000564: 02300193 li gp,35 + 80000568: 11df1c63 bne t5,t4,80000680 <fail> + +000000008000056c <test_36>: + 8000056c: 00000213 li tp,0 + 80000570: 01f00113 li sp,31 + 80000574: 800000b7 lui ra,0x80000 + 80000578: 00000013 nop + 8000057c: 00000013 nop + 80000580: 0020df3b srlw t5,ra,sp + 80000584: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000588: 00200293 li t0,2 + 8000058c: fe5212e3 bne tp,t0,80000570 <test_36+0x4> + 80000590: 00100e93 li t4,1 + 80000594: 02400193 li gp,36 + 80000598: 0fdf1463 bne t5,t4,80000680 <fail> + +000000008000059c <test_37>: + 8000059c: 00000213 li tp,0 + 800005a0: 00700113 li sp,7 + 800005a4: 00000013 nop + 800005a8: 800000b7 lui ra,0x80000 + 800005ac: 0020df3b srlw t5,ra,sp + 800005b0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005b4: 00200293 li t0,2 + 800005b8: fe5214e3 bne tp,t0,800005a0 <test_37+0x4> + 800005bc: 01000eb7 lui t4,0x1000 + 800005c0: 02500193 li gp,37 + 800005c4: 0bdf1e63 bne t5,t4,80000680 <fail> + +00000000800005c8 <test_38>: + 800005c8: 00000213 li tp,0 + 800005cc: 00e00113 li sp,14 + 800005d0: 00000013 nop + 800005d4: 800000b7 lui ra,0x80000 + 800005d8: 00000013 nop + 800005dc: 0020df3b srlw t5,ra,sp + 800005e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005e4: 00200293 li t0,2 + 800005e8: fe5212e3 bne tp,t0,800005cc <test_38+0x4> + 800005ec: 00020eb7 lui t4,0x20 + 800005f0: 02600193 li gp,38 + 800005f4: 09df1663 bne t5,t4,80000680 <fail> + +00000000800005f8 <test_39>: + 800005f8: 00000213 li tp,0 + 800005fc: 01f00113 li sp,31 + 80000600: 00000013 nop + 80000604: 00000013 nop + 80000608: 800000b7 lui ra,0x80000 + 8000060c: 0020df3b srlw t5,ra,sp + 80000610: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000614: 00200293 li t0,2 + 80000618: fe5212e3 bne tp,t0,800005fc <test_39+0x4> + 8000061c: 00100e93 li t4,1 + 80000620: 02700193 li gp,39 + 80000624: 05df1e63 bne t5,t4,80000680 <fail> + +0000000080000628 <test_40>: + 80000628: 00f00093 li ra,15 + 8000062c: 0010513b srlw sp,zero,ra + 80000630: 00000e93 li t4,0 + 80000634: 02800193 li gp,40 + 80000638: 05d11463 bne sp,t4,80000680 <fail> + +000000008000063c <test_41>: + 8000063c: 02000093 li ra,32 + 80000640: 0000d13b srlw sp,ra,zero + 80000644: 02000e93 li t4,32 + 80000648: 02900193 li gp,41 + 8000064c: 03d11a63 bne sp,t4,80000680 <fail> + +0000000080000650 <test_42>: + 80000650: 000050bb srlw ra,zero,zero + 80000654: 00000e93 li t4,0 + 80000658: 02a00193 li gp,42 + 8000065c: 03d09263 bne ra,t4,80000680 <fail> + +0000000080000660 <test_43>: + 80000660: 40000093 li ra,1024 + 80000664: 00001137 lui sp,0x1 + 80000668: 8001011b addiw sp,sp,-2048 + 8000066c: 0020d03b srlw zero,ra,sp + 80000670: 00000e93 li t4,0 + 80000674: 02b00193 li gp,43 + 80000678: 01d01463 bne zero,t4,80000680 <fail> + 8000067c: 00301c63 bne zero,gp,80000694 <pass> + +0000000080000680 <fail>: + 80000680: 0ff0000f fence + 80000684: 00018063 beqz gp,80000684 <fail+0x4> + 80000688: 00119193 slli gp,gp,0x1 + 8000068c: 0011e193 ori gp,gp,1 + 80000690: 00000073 ecall + +0000000080000694 <pass>: + 80000694: 0ff0000f fence + 80000698: 00100193 li gp,1 + 8000069c: 00000073 ecall + 800006a0: c0001073 unimp + 800006a4: 0000 unimp + 800006a6: 0000 unimp + 800006a8: 0000 unimp + 800006aa: 0000 unimp + 800006ac: 0000 unimp + 800006ae: 0000 unimp + 800006b0: 0000 unimp + 800006b2: 0000 unimp + 800006b4: 0000 unimp + 800006b6: 0000 unimp + 800006b8: 0000 unimp + 800006ba: 0000 unimp + 800006bc: 0000 unimp + 800006be: 0000 unimp + 800006c0: 0000 unimp + 800006c2: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-srlw.elf b/test/riscv/tests/rv64ui-p-srlw.elf Binary files differnew file mode 100755 index 00000000..04a9c213 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-srlw.elf diff --git a/test/riscv/tests/rv64ui-p-sub.dump b/test/riscv/tests/rv64ui-p-sub.dump new file mode 100644 index 00000000..34bda7b8 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sub.dump @@ -0,0 +1,481 @@ + +rv64ui-p-sub: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 00000113 li sp,0 + 80000104: 40208f33 sub t5,ra,sp + 80000108: 00000e93 li t4,0 + 8000010c: 00200193 li gp,2 + 80000110: 4bdf1e63 bne t5,t4,800005cc <fail> + +0000000080000114 <test_3>: + 80000114: 00100093 li ra,1 + 80000118: 00100113 li sp,1 + 8000011c: 40208f33 sub t5,ra,sp + 80000120: 00000e93 li t4,0 + 80000124: 00300193 li gp,3 + 80000128: 4bdf1263 bne t5,t4,800005cc <fail> + +000000008000012c <test_4>: + 8000012c: 00300093 li ra,3 + 80000130: 00700113 li sp,7 + 80000134: 40208f33 sub t5,ra,sp + 80000138: ffc00e93 li t4,-4 + 8000013c: 00400193 li gp,4 + 80000140: 49df1663 bne t5,t4,800005cc <fail> + +0000000080000144 <test_5>: + 80000144: 00000093 li ra,0 + 80000148: ffff8137 lui sp,0xffff8 + 8000014c: 40208f33 sub t5,ra,sp + 80000150: 00008eb7 lui t4,0x8 + 80000154: 00500193 li gp,5 + 80000158: 47df1a63 bne t5,t4,800005cc <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 00000113 li sp,0 + 80000164: 40208f33 sub t5,ra,sp + 80000168: 80000eb7 lui t4,0x80000 + 8000016c: 00600193 li gp,6 + 80000170: 45df1e63 bne t5,t4,800005cc <fail> + +0000000080000174 <test_7>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: ffff8137 lui sp,0xffff8 + 8000017c: 40208f33 sub t5,ra,sp + 80000180: 80008eb7 lui t4,0x80008 + 80000184: 00700193 li gp,7 + 80000188: 45df1263 bne t5,t4,800005cc <fail> + +000000008000018c <test_8>: + 8000018c: 00000093 li ra,0 + 80000190: 00008137 lui sp,0x8 + 80000194: fff1011b addiw sp,sp,-1 + 80000198: 40208f33 sub t5,ra,sp + 8000019c: ffff8eb7 lui t4,0xffff8 + 800001a0: 001e8e9b addiw t4,t4,1 + 800001a4: 00800193 li gp,8 + 800001a8: 43df1263 bne t5,t4,800005cc <fail> + +00000000800001ac <test_9>: + 800001ac: 800000b7 lui ra,0x80000 + 800001b0: fff0809b addiw ra,ra,-1 + 800001b4: 00000113 li sp,0 + 800001b8: 40208f33 sub t5,ra,sp + 800001bc: 80000eb7 lui t4,0x80000 + 800001c0: fffe8e9b addiw t4,t4,-1 + 800001c4: 00900193 li gp,9 + 800001c8: 41df1263 bne t5,t4,800005cc <fail> + +00000000800001cc <test_10>: + 800001cc: 800000b7 lui ra,0x80000 + 800001d0: fff0809b addiw ra,ra,-1 + 800001d4: 00008137 lui sp,0x8 + 800001d8: fff1011b addiw sp,sp,-1 + 800001dc: 40208f33 sub t5,ra,sp + 800001e0: 7fff8eb7 lui t4,0x7fff8 + 800001e4: 00a00193 li gp,10 + 800001e8: 3fdf1263 bne t5,t4,800005cc <fail> + +00000000800001ec <test_11>: + 800001ec: 800000b7 lui ra,0x80000 + 800001f0: 00008137 lui sp,0x8 + 800001f4: fff1011b addiw sp,sp,-1 + 800001f8: 40208f33 sub t5,ra,sp + 800001fc: ffff0eb7 lui t4,0xffff0 + 80000200: fffe8e9b addiw t4,t4,-1 + 80000204: 00fe9e93 slli t4,t4,0xf + 80000208: 001e8e93 addi t4,t4,1 # ffffffffffff0001 <_end+0xffffffff7ffee001> + 8000020c: 00b00193 li gp,11 + 80000210: 3bdf1e63 bne t5,t4,800005cc <fail> + +0000000080000214 <test_12>: + 80000214: 800000b7 lui ra,0x80000 + 80000218: fff0809b addiw ra,ra,-1 + 8000021c: ffff8137 lui sp,0xffff8 + 80000220: 40208f33 sub t5,ra,sp + 80000224: 00010eb7 lui t4,0x10 + 80000228: 001e8e9b addiw t4,t4,1 + 8000022c: 00fe9e93 slli t4,t4,0xf + 80000230: fffe8e93 addi t4,t4,-1 # ffff <_start-0x7fff0001> + 80000234: 00c00193 li gp,12 + 80000238: 39df1a63 bne t5,t4,800005cc <fail> + +000000008000023c <test_13>: + 8000023c: 00000093 li ra,0 + 80000240: fff00113 li sp,-1 + 80000244: 40208f33 sub t5,ra,sp + 80000248: 00100e93 li t4,1 + 8000024c: 00d00193 li gp,13 + 80000250: 37df1e63 bne t5,t4,800005cc <fail> + +0000000080000254 <test_14>: + 80000254: fff00093 li ra,-1 + 80000258: 00100113 li sp,1 + 8000025c: 40208f33 sub t5,ra,sp + 80000260: ffe00e93 li t4,-2 + 80000264: 00e00193 li gp,14 + 80000268: 37df1263 bne t5,t4,800005cc <fail> + +000000008000026c <test_15>: + 8000026c: fff00093 li ra,-1 + 80000270: fff00113 li sp,-1 + 80000274: 40208f33 sub t5,ra,sp + 80000278: 00000e93 li t4,0 + 8000027c: 00f00193 li gp,15 + 80000280: 35df1663 bne t5,t4,800005cc <fail> + +0000000080000284 <test_16>: + 80000284: 00d00093 li ra,13 + 80000288: 00b00113 li sp,11 + 8000028c: 402080b3 sub ra,ra,sp + 80000290: 00200e93 li t4,2 + 80000294: 01000193 li gp,16 + 80000298: 33d09a63 bne ra,t4,800005cc <fail> + +000000008000029c <test_17>: + 8000029c: 00e00093 li ra,14 + 800002a0: 00b00113 li sp,11 + 800002a4: 40208133 sub sp,ra,sp + 800002a8: 00300e93 li t4,3 + 800002ac: 01100193 li gp,17 + 800002b0: 31d11e63 bne sp,t4,800005cc <fail> + +00000000800002b4 <test_18>: + 800002b4: 00d00093 li ra,13 + 800002b8: 401080b3 sub ra,ra,ra + 800002bc: 00000e93 li t4,0 + 800002c0: 01200193 li gp,18 + 800002c4: 31d09463 bne ra,t4,800005cc <fail> + +00000000800002c8 <test_19>: + 800002c8: 00000213 li tp,0 + 800002cc: 00d00093 li ra,13 + 800002d0: 00b00113 li sp,11 + 800002d4: 40208f33 sub t5,ra,sp + 800002d8: 000f0313 mv t1,t5 + 800002dc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002e0: 00200293 li t0,2 + 800002e4: fe5214e3 bne tp,t0,800002cc <test_19+0x4> + 800002e8: 00200e93 li t4,2 + 800002ec: 01300193 li gp,19 + 800002f0: 2dd31e63 bne t1,t4,800005cc <fail> + +00000000800002f4 <test_20>: + 800002f4: 00000213 li tp,0 + 800002f8: 00e00093 li ra,14 + 800002fc: 00b00113 li sp,11 + 80000300: 40208f33 sub t5,ra,sp + 80000304: 00000013 nop + 80000308: 000f0313 mv t1,t5 + 8000030c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000310: 00200293 li t0,2 + 80000314: fe5212e3 bne tp,t0,800002f8 <test_20+0x4> + 80000318: 00300e93 li t4,3 + 8000031c: 01400193 li gp,20 + 80000320: 2bd31663 bne t1,t4,800005cc <fail> + +0000000080000324 <test_21>: + 80000324: 00000213 li tp,0 + 80000328: 00f00093 li ra,15 + 8000032c: 00b00113 li sp,11 + 80000330: 40208f33 sub t5,ra,sp + 80000334: 00000013 nop + 80000338: 00000013 nop + 8000033c: 000f0313 mv t1,t5 + 80000340: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000344: 00200293 li t0,2 + 80000348: fe5210e3 bne tp,t0,80000328 <test_21+0x4> + 8000034c: 00400e93 li t4,4 + 80000350: 01500193 li gp,21 + 80000354: 27d31c63 bne t1,t4,800005cc <fail> + +0000000080000358 <test_22>: + 80000358: 00000213 li tp,0 + 8000035c: 00d00093 li ra,13 + 80000360: 00b00113 li sp,11 + 80000364: 40208f33 sub t5,ra,sp + 80000368: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000036c: 00200293 li t0,2 + 80000370: fe5216e3 bne tp,t0,8000035c <test_22+0x4> + 80000374: 00200e93 li t4,2 + 80000378: 01600193 li gp,22 + 8000037c: 25df1863 bne t5,t4,800005cc <fail> + +0000000080000380 <test_23>: + 80000380: 00000213 li tp,0 + 80000384: 00e00093 li ra,14 + 80000388: 00b00113 li sp,11 + 8000038c: 00000013 nop + 80000390: 40208f33 sub t5,ra,sp + 80000394: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000398: 00200293 li t0,2 + 8000039c: fe5214e3 bne tp,t0,80000384 <test_23+0x4> + 800003a0: 00300e93 li t4,3 + 800003a4: 01700193 li gp,23 + 800003a8: 23df1263 bne t5,t4,800005cc <fail> + +00000000800003ac <test_24>: + 800003ac: 00000213 li tp,0 + 800003b0: 00f00093 li ra,15 + 800003b4: 00b00113 li sp,11 + 800003b8: 00000013 nop + 800003bc: 00000013 nop + 800003c0: 40208f33 sub t5,ra,sp + 800003c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003c8: 00200293 li t0,2 + 800003cc: fe5212e3 bne tp,t0,800003b0 <test_24+0x4> + 800003d0: 00400e93 li t4,4 + 800003d4: 01800193 li gp,24 + 800003d8: 1fdf1a63 bne t5,t4,800005cc <fail> + +00000000800003dc <test_25>: + 800003dc: 00000213 li tp,0 + 800003e0: 00d00093 li ra,13 + 800003e4: 00000013 nop + 800003e8: 00b00113 li sp,11 + 800003ec: 40208f33 sub t5,ra,sp + 800003f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003f4: 00200293 li t0,2 + 800003f8: fe5214e3 bne tp,t0,800003e0 <test_25+0x4> + 800003fc: 00200e93 li t4,2 + 80000400: 01900193 li gp,25 + 80000404: 1ddf1463 bne t5,t4,800005cc <fail> + +0000000080000408 <test_26>: + 80000408: 00000213 li tp,0 + 8000040c: 00e00093 li ra,14 + 80000410: 00000013 nop + 80000414: 00b00113 li sp,11 + 80000418: 00000013 nop + 8000041c: 40208f33 sub t5,ra,sp + 80000420: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000424: 00200293 li t0,2 + 80000428: fe5212e3 bne tp,t0,8000040c <test_26+0x4> + 8000042c: 00300e93 li t4,3 + 80000430: 01a00193 li gp,26 + 80000434: 19df1c63 bne t5,t4,800005cc <fail> + +0000000080000438 <test_27>: + 80000438: 00000213 li tp,0 + 8000043c: 00f00093 li ra,15 + 80000440: 00000013 nop + 80000444: 00000013 nop + 80000448: 00b00113 li sp,11 + 8000044c: 40208f33 sub t5,ra,sp + 80000450: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000454: 00200293 li t0,2 + 80000458: fe5212e3 bne tp,t0,8000043c <test_27+0x4> + 8000045c: 00400e93 li t4,4 + 80000460: 01b00193 li gp,27 + 80000464: 17df1463 bne t5,t4,800005cc <fail> + +0000000080000468 <test_28>: + 80000468: 00000213 li tp,0 + 8000046c: 00b00113 li sp,11 + 80000470: 00d00093 li ra,13 + 80000474: 40208f33 sub t5,ra,sp + 80000478: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000047c: 00200293 li t0,2 + 80000480: fe5216e3 bne tp,t0,8000046c <test_28+0x4> + 80000484: 00200e93 li t4,2 + 80000488: 01c00193 li gp,28 + 8000048c: 15df1063 bne t5,t4,800005cc <fail> + +0000000080000490 <test_29>: + 80000490: 00000213 li tp,0 + 80000494: 00b00113 li sp,11 + 80000498: 00e00093 li ra,14 + 8000049c: 00000013 nop + 800004a0: 40208f33 sub t5,ra,sp + 800004a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004a8: 00200293 li t0,2 + 800004ac: fe5214e3 bne tp,t0,80000494 <test_29+0x4> + 800004b0: 00300e93 li t4,3 + 800004b4: 01d00193 li gp,29 + 800004b8: 11df1a63 bne t5,t4,800005cc <fail> + +00000000800004bc <test_30>: + 800004bc: 00000213 li tp,0 + 800004c0: 00b00113 li sp,11 + 800004c4: 00f00093 li ra,15 + 800004c8: 00000013 nop + 800004cc: 00000013 nop + 800004d0: 40208f33 sub t5,ra,sp + 800004d4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004d8: 00200293 li t0,2 + 800004dc: fe5212e3 bne tp,t0,800004c0 <test_30+0x4> + 800004e0: 00400e93 li t4,4 + 800004e4: 01e00193 li gp,30 + 800004e8: 0fdf1263 bne t5,t4,800005cc <fail> + +00000000800004ec <test_31>: + 800004ec: 00000213 li tp,0 + 800004f0: 00b00113 li sp,11 + 800004f4: 00000013 nop + 800004f8: 00d00093 li ra,13 + 800004fc: 40208f33 sub t5,ra,sp + 80000500: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000504: 00200293 li t0,2 + 80000508: fe5214e3 bne tp,t0,800004f0 <test_31+0x4> + 8000050c: 00200e93 li t4,2 + 80000510: 01f00193 li gp,31 + 80000514: 0bdf1c63 bne t5,t4,800005cc <fail> + +0000000080000518 <test_32>: + 80000518: 00000213 li tp,0 + 8000051c: 00b00113 li sp,11 + 80000520: 00000013 nop + 80000524: 00e00093 li ra,14 + 80000528: 00000013 nop + 8000052c: 40208f33 sub t5,ra,sp + 80000530: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000534: 00200293 li t0,2 + 80000538: fe5212e3 bne tp,t0,8000051c <test_32+0x4> + 8000053c: 00300e93 li t4,3 + 80000540: 02000193 li gp,32 + 80000544: 09df1463 bne t5,t4,800005cc <fail> + +0000000080000548 <test_33>: + 80000548: 00000213 li tp,0 + 8000054c: 00b00113 li sp,11 + 80000550: 00000013 nop + 80000554: 00000013 nop + 80000558: 00f00093 li ra,15 + 8000055c: 40208f33 sub t5,ra,sp + 80000560: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000564: 00200293 li t0,2 + 80000568: fe5212e3 bne tp,t0,8000054c <test_33+0x4> + 8000056c: 00400e93 li t4,4 + 80000570: 02100193 li gp,33 + 80000574: 05df1c63 bne t5,t4,800005cc <fail> + +0000000080000578 <test_34>: + 80000578: ff100093 li ra,-15 + 8000057c: 40100133 neg sp,ra + 80000580: 00f00e93 li t4,15 + 80000584: 02200193 li gp,34 + 80000588: 05d11263 bne sp,t4,800005cc <fail> + +000000008000058c <test_35>: + 8000058c: 02000093 li ra,32 + 80000590: 40008133 sub sp,ra,zero + 80000594: 02000e93 li t4,32 + 80000598: 02300193 li gp,35 + 8000059c: 03d11863 bne sp,t4,800005cc <fail> + +00000000800005a0 <test_36>: + 800005a0: 400000b3 neg ra,zero + 800005a4: 00000e93 li t4,0 + 800005a8: 02400193 li gp,36 + 800005ac: 03d09063 bne ra,t4,800005cc <fail> + +00000000800005b0 <test_37>: + 800005b0: 01000093 li ra,16 + 800005b4: 01e00113 li sp,30 + 800005b8: 40208033 sub zero,ra,sp + 800005bc: 00000e93 li t4,0 + 800005c0: 02500193 li gp,37 + 800005c4: 01d01463 bne zero,t4,800005cc <fail> + 800005c8: 00301c63 bne zero,gp,800005e0 <pass> + +00000000800005cc <fail>: + 800005cc: 0ff0000f fence + 800005d0: 00018063 beqz gp,800005d0 <fail+0x4> + 800005d4: 00119193 slli gp,gp,0x1 + 800005d8: 0011e193 ori gp,gp,1 + 800005dc: 00000073 ecall + +00000000800005e0 <pass>: + 800005e0: 0ff0000f fence + 800005e4: 00100193 li gp,1 + 800005e8: 00000073 ecall + 800005ec: c0001073 unimp + 800005f0: 0000 unimp + 800005f2: 0000 unimp + 800005f4: 0000 unimp + 800005f6: 0000 unimp + 800005f8: 0000 unimp + 800005fa: 0000 unimp + 800005fc: 0000 unimp + 800005fe: 0000 unimp + 80000600: 0000 unimp + 80000602: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sub.elf b/test/riscv/tests/rv64ui-p-sub.elf Binary files differnew file mode 100755 index 00000000..04699b73 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sub.elf diff --git a/test/riscv/tests/rv64ui-p-subw.dump b/test/riscv/tests/rv64ui-p-subw.dump new file mode 100644 index 00000000..0a29bbfb --- /dev/null +++ b/test/riscv/tests/rv64ui-p-subw.dump @@ -0,0 +1,485 @@ + +rv64ui-p-subw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 00000113 li sp,0 + 80000104: 40208f3b subw t5,ra,sp + 80000108: 00000e93 li t4,0 + 8000010c: 00200193 li gp,2 + 80000110: 4bdf1663 bne t5,t4,800005bc <fail> + +0000000080000114 <test_3>: + 80000114: 00100093 li ra,1 + 80000118: 00100113 li sp,1 + 8000011c: 40208f3b subw t5,ra,sp + 80000120: 00000e93 li t4,0 + 80000124: 00300193 li gp,3 + 80000128: 49df1a63 bne t5,t4,800005bc <fail> + +000000008000012c <test_4>: + 8000012c: 00300093 li ra,3 + 80000130: 00700113 li sp,7 + 80000134: 40208f3b subw t5,ra,sp + 80000138: ffc00e93 li t4,-4 + 8000013c: 00400193 li gp,4 + 80000140: 47df1e63 bne t5,t4,800005bc <fail> + +0000000080000144 <test_5>: + 80000144: 00000093 li ra,0 + 80000148: ffff8137 lui sp,0xffff8 + 8000014c: 40208f3b subw t5,ra,sp + 80000150: 00008eb7 lui t4,0x8 + 80000154: 00500193 li gp,5 + 80000158: 47df1263 bne t5,t4,800005bc <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 00000113 li sp,0 + 80000164: 40208f3b subw t5,ra,sp + 80000168: 80000eb7 lui t4,0x80000 + 8000016c: 00600193 li gp,6 + 80000170: 45df1663 bne t5,t4,800005bc <fail> + +0000000080000174 <test_7>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: ffff8137 lui sp,0xffff8 + 8000017c: 40208f3b subw t5,ra,sp + 80000180: 80008eb7 lui t4,0x80008 + 80000184: 00700193 li gp,7 + 80000188: 43df1a63 bne t5,t4,800005bc <fail> + +000000008000018c <test_8>: + 8000018c: 00000093 li ra,0 + 80000190: 00008137 lui sp,0x8 + 80000194: fff1011b addiw sp,sp,-1 + 80000198: 40208f3b subw t5,ra,sp + 8000019c: ffff8eb7 lui t4,0xffff8 + 800001a0: 001e8e9b addiw t4,t4,1 + 800001a4: 00800193 li gp,8 + 800001a8: 41df1a63 bne t5,t4,800005bc <fail> + +00000000800001ac <test_9>: + 800001ac: 800000b7 lui ra,0x80000 + 800001b0: fff0809b addiw ra,ra,-1 + 800001b4: 00000113 li sp,0 + 800001b8: 40208f3b subw t5,ra,sp + 800001bc: 80000eb7 lui t4,0x80000 + 800001c0: fffe8e9b addiw t4,t4,-1 + 800001c4: 00900193 li gp,9 + 800001c8: 3fdf1a63 bne t5,t4,800005bc <fail> + +00000000800001cc <test_10>: + 800001cc: 800000b7 lui ra,0x80000 + 800001d0: fff0809b addiw ra,ra,-1 + 800001d4: 00008137 lui sp,0x8 + 800001d8: fff1011b addiw sp,sp,-1 + 800001dc: 40208f3b subw t5,ra,sp + 800001e0: 7fff8eb7 lui t4,0x7fff8 + 800001e4: 00a00193 li gp,10 + 800001e8: 3ddf1a63 bne t5,t4,800005bc <fail> + +00000000800001ec <test_11>: + 800001ec: 800000b7 lui ra,0x80000 + 800001f0: 00008137 lui sp,0x8 + 800001f4: fff1011b addiw sp,sp,-1 + 800001f8: 40208f3b subw t5,ra,sp + 800001fc: 7fff8eb7 lui t4,0x7fff8 + 80000200: 001e8e9b addiw t4,t4,1 + 80000204: 00b00193 li gp,11 + 80000208: 3bdf1a63 bne t5,t4,800005bc <fail> + +000000008000020c <test_12>: + 8000020c: 800000b7 lui ra,0x80000 + 80000210: fff0809b addiw ra,ra,-1 + 80000214: ffff8137 lui sp,0xffff8 + 80000218: 40208f3b subw t5,ra,sp + 8000021c: 80008eb7 lui t4,0x80008 + 80000220: fffe8e9b addiw t4,t4,-1 + 80000224: 00c00193 li gp,12 + 80000228: 39df1a63 bne t5,t4,800005bc <fail> + +000000008000022c <test_13>: + 8000022c: 00000093 li ra,0 + 80000230: fff00113 li sp,-1 + 80000234: 40208f3b subw t5,ra,sp + 80000238: 00100e93 li t4,1 + 8000023c: 00d00193 li gp,13 + 80000240: 37df1e63 bne t5,t4,800005bc <fail> + +0000000080000244 <test_14>: + 80000244: fff00093 li ra,-1 + 80000248: 00100113 li sp,1 + 8000024c: 40208f3b subw t5,ra,sp + 80000250: ffe00e93 li t4,-2 + 80000254: 00e00193 li gp,14 + 80000258: 37df1263 bne t5,t4,800005bc <fail> + +000000008000025c <test_15>: + 8000025c: fff00093 li ra,-1 + 80000260: fff00113 li sp,-1 + 80000264: 40208f3b subw t5,ra,sp + 80000268: 00000e93 li t4,0 + 8000026c: 00f00193 li gp,15 + 80000270: 35df1663 bne t5,t4,800005bc <fail> + +0000000080000274 <test_16>: + 80000274: 00d00093 li ra,13 + 80000278: 00b00113 li sp,11 + 8000027c: 402080bb subw ra,ra,sp + 80000280: 00200e93 li t4,2 + 80000284: 01000193 li gp,16 + 80000288: 33d09a63 bne ra,t4,800005bc <fail> + +000000008000028c <test_17>: + 8000028c: 00e00093 li ra,14 + 80000290: 00b00113 li sp,11 + 80000294: 4020813b subw sp,ra,sp + 80000298: 00300e93 li t4,3 + 8000029c: 01100193 li gp,17 + 800002a0: 31d11e63 bne sp,t4,800005bc <fail> + +00000000800002a4 <test_18>: + 800002a4: 00d00093 li ra,13 + 800002a8: 401080bb subw ra,ra,ra + 800002ac: 00000e93 li t4,0 + 800002b0: 01200193 li gp,18 + 800002b4: 31d09463 bne ra,t4,800005bc <fail> + +00000000800002b8 <test_19>: + 800002b8: 00000213 li tp,0 + 800002bc: 00d00093 li ra,13 + 800002c0: 00b00113 li sp,11 + 800002c4: 40208f3b subw t5,ra,sp + 800002c8: 000f0313 mv t1,t5 + 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002d0: 00200293 li t0,2 + 800002d4: fe5214e3 bne tp,t0,800002bc <test_19+0x4> + 800002d8: 00200e93 li t4,2 + 800002dc: 01300193 li gp,19 + 800002e0: 2dd31e63 bne t1,t4,800005bc <fail> + +00000000800002e4 <test_20>: + 800002e4: 00000213 li tp,0 + 800002e8: 00e00093 li ra,14 + 800002ec: 00b00113 li sp,11 + 800002f0: 40208f3b subw t5,ra,sp + 800002f4: 00000013 nop + 800002f8: 000f0313 mv t1,t5 + 800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000300: 00200293 li t0,2 + 80000304: fe5212e3 bne tp,t0,800002e8 <test_20+0x4> + 80000308: 00300e93 li t4,3 + 8000030c: 01400193 li gp,20 + 80000310: 2bd31663 bne t1,t4,800005bc <fail> + +0000000080000314 <test_21>: + 80000314: 00000213 li tp,0 + 80000318: 00f00093 li ra,15 + 8000031c: 00b00113 li sp,11 + 80000320: 40208f3b subw t5,ra,sp + 80000324: 00000013 nop + 80000328: 00000013 nop + 8000032c: 000f0313 mv t1,t5 + 80000330: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000334: 00200293 li t0,2 + 80000338: fe5210e3 bne tp,t0,80000318 <test_21+0x4> + 8000033c: 00400e93 li t4,4 + 80000340: 01500193 li gp,21 + 80000344: 27d31c63 bne t1,t4,800005bc <fail> + +0000000080000348 <test_22>: + 80000348: 00000213 li tp,0 + 8000034c: 00d00093 li ra,13 + 80000350: 00b00113 li sp,11 + 80000354: 40208f3b subw t5,ra,sp + 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000035c: 00200293 li t0,2 + 80000360: fe5216e3 bne tp,t0,8000034c <test_22+0x4> + 80000364: 00200e93 li t4,2 + 80000368: 01600193 li gp,22 + 8000036c: 25df1863 bne t5,t4,800005bc <fail> + +0000000080000370 <test_23>: + 80000370: 00000213 li tp,0 + 80000374: 00e00093 li ra,14 + 80000378: 00b00113 li sp,11 + 8000037c: 00000013 nop + 80000380: 40208f3b subw t5,ra,sp + 80000384: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000388: 00200293 li t0,2 + 8000038c: fe5214e3 bne tp,t0,80000374 <test_23+0x4> + 80000390: 00300e93 li t4,3 + 80000394: 01700193 li gp,23 + 80000398: 23df1263 bne t5,t4,800005bc <fail> + +000000008000039c <test_24>: + 8000039c: 00000213 li tp,0 + 800003a0: 00f00093 li ra,15 + 800003a4: 00b00113 li sp,11 + 800003a8: 00000013 nop + 800003ac: 00000013 nop + 800003b0: 40208f3b subw t5,ra,sp + 800003b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003b8: 00200293 li t0,2 + 800003bc: fe5212e3 bne tp,t0,800003a0 <test_24+0x4> + 800003c0: 00400e93 li t4,4 + 800003c4: 01800193 li gp,24 + 800003c8: 1fdf1a63 bne t5,t4,800005bc <fail> + +00000000800003cc <test_25>: + 800003cc: 00000213 li tp,0 + 800003d0: 00d00093 li ra,13 + 800003d4: 00000013 nop + 800003d8: 00b00113 li sp,11 + 800003dc: 40208f3b subw t5,ra,sp + 800003e0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003e4: 00200293 li t0,2 + 800003e8: fe5214e3 bne tp,t0,800003d0 <test_25+0x4> + 800003ec: 00200e93 li t4,2 + 800003f0: 01900193 li gp,25 + 800003f4: 1ddf1463 bne t5,t4,800005bc <fail> + +00000000800003f8 <test_26>: + 800003f8: 00000213 li tp,0 + 800003fc: 00e00093 li ra,14 + 80000400: 00000013 nop + 80000404: 00b00113 li sp,11 + 80000408: 00000013 nop + 8000040c: 40208f3b subw t5,ra,sp + 80000410: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000414: 00200293 li t0,2 + 80000418: fe5212e3 bne tp,t0,800003fc <test_26+0x4> + 8000041c: 00300e93 li t4,3 + 80000420: 01a00193 li gp,26 + 80000424: 19df1c63 bne t5,t4,800005bc <fail> + +0000000080000428 <test_27>: + 80000428: 00000213 li tp,0 + 8000042c: 00f00093 li ra,15 + 80000430: 00000013 nop + 80000434: 00000013 nop + 80000438: 00b00113 li sp,11 + 8000043c: 40208f3b subw t5,ra,sp + 80000440: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000444: 00200293 li t0,2 + 80000448: fe5212e3 bne tp,t0,8000042c <test_27+0x4> + 8000044c: 00400e93 li t4,4 + 80000450: 01b00193 li gp,27 + 80000454: 17df1463 bne t5,t4,800005bc <fail> + +0000000080000458 <test_28>: + 80000458: 00000213 li tp,0 + 8000045c: 00b00113 li sp,11 + 80000460: 00d00093 li ra,13 + 80000464: 40208f3b subw t5,ra,sp + 80000468: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000046c: 00200293 li t0,2 + 80000470: fe5216e3 bne tp,t0,8000045c <test_28+0x4> + 80000474: 00200e93 li t4,2 + 80000478: 01c00193 li gp,28 + 8000047c: 15df1063 bne t5,t4,800005bc <fail> + +0000000080000480 <test_29>: + 80000480: 00000213 li tp,0 + 80000484: 00b00113 li sp,11 + 80000488: 00e00093 li ra,14 + 8000048c: 00000013 nop + 80000490: 40208f3b subw t5,ra,sp + 80000494: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000498: 00200293 li t0,2 + 8000049c: fe5214e3 bne tp,t0,80000484 <test_29+0x4> + 800004a0: 00300e93 li t4,3 + 800004a4: 01d00193 li gp,29 + 800004a8: 11df1a63 bne t5,t4,800005bc <fail> + +00000000800004ac <test_30>: + 800004ac: 00000213 li tp,0 + 800004b0: 00b00113 li sp,11 + 800004b4: 00f00093 li ra,15 + 800004b8: 00000013 nop + 800004bc: 00000013 nop + 800004c0: 40208f3b subw t5,ra,sp + 800004c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004c8: 00200293 li t0,2 + 800004cc: fe5212e3 bne tp,t0,800004b0 <test_30+0x4> + 800004d0: 00400e93 li t4,4 + 800004d4: 01e00193 li gp,30 + 800004d8: 0fdf1263 bne t5,t4,800005bc <fail> + +00000000800004dc <test_31>: + 800004dc: 00000213 li tp,0 + 800004e0: 00b00113 li sp,11 + 800004e4: 00000013 nop + 800004e8: 00d00093 li ra,13 + 800004ec: 40208f3b subw t5,ra,sp + 800004f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004f4: 00200293 li t0,2 + 800004f8: fe5214e3 bne tp,t0,800004e0 <test_31+0x4> + 800004fc: 00200e93 li t4,2 + 80000500: 01f00193 li gp,31 + 80000504: 0bdf1c63 bne t5,t4,800005bc <fail> + +0000000080000508 <test_32>: + 80000508: 00000213 li tp,0 + 8000050c: 00b00113 li sp,11 + 80000510: 00000013 nop + 80000514: 00e00093 li ra,14 + 80000518: 00000013 nop + 8000051c: 40208f3b subw t5,ra,sp + 80000520: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000524: 00200293 li t0,2 + 80000528: fe5212e3 bne tp,t0,8000050c <test_32+0x4> + 8000052c: 00300e93 li t4,3 + 80000530: 02000193 li gp,32 + 80000534: 09df1463 bne t5,t4,800005bc <fail> + +0000000080000538 <test_33>: + 80000538: 00000213 li tp,0 + 8000053c: 00b00113 li sp,11 + 80000540: 00000013 nop + 80000544: 00000013 nop + 80000548: 00f00093 li ra,15 + 8000054c: 40208f3b subw t5,ra,sp + 80000550: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000554: 00200293 li t0,2 + 80000558: fe5212e3 bne tp,t0,8000053c <test_33+0x4> + 8000055c: 00400e93 li t4,4 + 80000560: 02100193 li gp,33 + 80000564: 05df1c63 bne t5,t4,800005bc <fail> + +0000000080000568 <test_34>: + 80000568: ff100093 li ra,-15 + 8000056c: 4010013b negw sp,ra + 80000570: 00f00e93 li t4,15 + 80000574: 02200193 li gp,34 + 80000578: 05d11263 bne sp,t4,800005bc <fail> + +000000008000057c <test_35>: + 8000057c: 02000093 li ra,32 + 80000580: 4000813b subw sp,ra,zero + 80000584: 02000e93 li t4,32 + 80000588: 02300193 li gp,35 + 8000058c: 03d11863 bne sp,t4,800005bc <fail> + +0000000080000590 <test_36>: + 80000590: 400000bb negw ra,zero + 80000594: 00000e93 li t4,0 + 80000598: 02400193 li gp,36 + 8000059c: 03d09063 bne ra,t4,800005bc <fail> + +00000000800005a0 <test_37>: + 800005a0: 01000093 li ra,16 + 800005a4: 01e00113 li sp,30 + 800005a8: 4020803b subw zero,ra,sp + 800005ac: 00000e93 li t4,0 + 800005b0: 02500193 li gp,37 + 800005b4: 01d01463 bne zero,t4,800005bc <fail> + 800005b8: 00301c63 bne zero,gp,800005d0 <pass> + +00000000800005bc <fail>: + 800005bc: 0ff0000f fence + 800005c0: 00018063 beqz gp,800005c0 <fail+0x4> + 800005c4: 00119193 slli gp,gp,0x1 + 800005c8: 0011e193 ori gp,gp,1 + 800005cc: 00000073 ecall + +00000000800005d0 <pass>: + 800005d0: 0ff0000f fence + 800005d4: 00100193 li gp,1 + 800005d8: 00000073 ecall + 800005dc: c0001073 unimp + 800005e0: 0000 unimp + 800005e2: 0000 unimp + 800005e4: 0000 unimp + 800005e6: 0000 unimp + 800005e8: 0000 unimp + 800005ea: 0000 unimp + 800005ec: 0000 unimp + 800005ee: 0000 unimp + 800005f0: 0000 unimp + 800005f2: 0000 unimp + 800005f4: 0000 unimp + 800005f6: 0000 unimp + 800005f8: 0000 unimp + 800005fa: 0000 unimp + 800005fc: 0000 unimp + 800005fe: 0000 unimp + 80000600: 0000 unimp + 80000602: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-subw.elf b/test/riscv/tests/rv64ui-p-subw.elf Binary files differnew file mode 100755 index 00000000..569998ee --- /dev/null +++ b/test/riscv/tests/rv64ui-p-subw.elf diff --git a/test/riscv/tests/rv64ui-p-sw.dump b/test/riscv/tests/rv64ui-p-sw.dump new file mode 100644 index 00000000..a80b9958 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sw.dump @@ -0,0 +1,476 @@ + +rv64ui-p-sw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00002097 auipc ra,0x2 + 80000100: f0408093 addi ra,ra,-252 # 80002000 <begin_signature> + 80000104: 00aa0137 lui sp,0xaa0 + 80000108: 0aa1011b addiw sp,sp,170 + 8000010c: 0020a023 sw sp,0(ra) + 80000110: 0000af03 lw t5,0(ra) + 80000114: 00aa0eb7 lui t4,0xaa0 + 80000118: 0aae8e9b addiw t4,t4,170 + 8000011c: 00200193 li gp,2 + 80000120: 47df1063 bne t5,t4,80000580 <fail> + +0000000080000124 <test_3>: + 80000124: 00002097 auipc ra,0x2 + 80000128: edc08093 addi ra,ra,-292 # 80002000 <begin_signature> + 8000012c: aa00b137 lui sp,0xaa00b + 80000130: a001011b addiw sp,sp,-1536 + 80000134: 0020a223 sw sp,4(ra) + 80000138: 0040af03 lw t5,4(ra) + 8000013c: aa00beb7 lui t4,0xaa00b + 80000140: a00e8e9b addiw t4,t4,-1536 + 80000144: 00300193 li gp,3 + 80000148: 43df1c63 bne t5,t4,80000580 <fail> + +000000008000014c <test_4>: + 8000014c: 00002097 auipc ra,0x2 + 80000150: eb408093 addi ra,ra,-332 # 80002000 <begin_signature> + 80000154: 0aa01137 lui sp,0xaa01 + 80000158: aa01011b addiw sp,sp,-1376 + 8000015c: 0020a423 sw sp,8(ra) + 80000160: 0080af03 lw t5,8(ra) + 80000164: 0aa01eb7 lui t4,0xaa01 + 80000168: aa0e8e9b addiw t4,t4,-1376 + 8000016c: 00400193 li gp,4 + 80000170: 41df1863 bne t5,t4,80000580 <fail> + +0000000080000174 <test_5>: + 80000174: 00002097 auipc ra,0x2 + 80000178: e8c08093 addi ra,ra,-372 # 80002000 <begin_signature> + 8000017c: a00aa137 lui sp,0xa00aa + 80000180: 00a1011b addiw sp,sp,10 + 80000184: 0020a623 sw sp,12(ra) + 80000188: 00c0af03 lw t5,12(ra) + 8000018c: a00aaeb7 lui t4,0xa00aa + 80000190: 00ae8e9b addiw t4,t4,10 + 80000194: 00500193 li gp,5 + 80000198: 3fdf1463 bne t5,t4,80000580 <fail> + +000000008000019c <test_6>: + 8000019c: 00002097 auipc ra,0x2 + 800001a0: e8008093 addi ra,ra,-384 # 8000201c <tdat8> + 800001a4: 00aa0137 lui sp,0xaa0 + 800001a8: 0aa1011b addiw sp,sp,170 + 800001ac: fe20aa23 sw sp,-12(ra) + 800001b0: ff40af03 lw t5,-12(ra) + 800001b4: 00aa0eb7 lui t4,0xaa0 + 800001b8: 0aae8e9b addiw t4,t4,170 + 800001bc: 00600193 li gp,6 + 800001c0: 3ddf1063 bne t5,t4,80000580 <fail> + +00000000800001c4 <test_7>: + 800001c4: 00002097 auipc ra,0x2 + 800001c8: e5808093 addi ra,ra,-424 # 8000201c <tdat8> + 800001cc: aa00b137 lui sp,0xaa00b + 800001d0: a001011b addiw sp,sp,-1536 + 800001d4: fe20ac23 sw sp,-8(ra) + 800001d8: ff80af03 lw t5,-8(ra) + 800001dc: aa00beb7 lui t4,0xaa00b + 800001e0: a00e8e9b addiw t4,t4,-1536 + 800001e4: 00700193 li gp,7 + 800001e8: 39df1c63 bne t5,t4,80000580 <fail> + +00000000800001ec <test_8>: + 800001ec: 00002097 auipc ra,0x2 + 800001f0: e3008093 addi ra,ra,-464 # 8000201c <tdat8> + 800001f4: 0aa01137 lui sp,0xaa01 + 800001f8: aa01011b addiw sp,sp,-1376 + 800001fc: fe20ae23 sw sp,-4(ra) + 80000200: ffc0af03 lw t5,-4(ra) + 80000204: 0aa01eb7 lui t4,0xaa01 + 80000208: aa0e8e9b addiw t4,t4,-1376 + 8000020c: 00800193 li gp,8 + 80000210: 37df1863 bne t5,t4,80000580 <fail> + +0000000080000214 <test_9>: + 80000214: 00002097 auipc ra,0x2 + 80000218: e0808093 addi ra,ra,-504 # 8000201c <tdat8> + 8000021c: a00aa137 lui sp,0xa00aa + 80000220: 00a1011b addiw sp,sp,10 + 80000224: 0020a023 sw sp,0(ra) + 80000228: 0000af03 lw t5,0(ra) + 8000022c: a00aaeb7 lui t4,0xa00aa + 80000230: 00ae8e9b addiw t4,t4,10 + 80000234: 00900193 li gp,9 + 80000238: 35df1463 bne t5,t4,80000580 <fail> + +000000008000023c <test_10>: + 8000023c: 00002097 auipc ra,0x2 + 80000240: de408093 addi ra,ra,-540 # 80002020 <tdat9> + 80000244: 12345137 lui sp,0x12345 + 80000248: 6781011b addiw sp,sp,1656 + 8000024c: fe008213 addi tp,ra,-32 + 80000250: 02222023 sw sp,32(tp) # 20 <_start-0x7fffffe0> + 80000254: 0000a283 lw t0,0(ra) + 80000258: 12345eb7 lui t4,0x12345 + 8000025c: 678e8e9b addiw t4,t4,1656 + 80000260: 00a00193 li gp,10 + 80000264: 31d29e63 bne t0,t4,80000580 <fail> + +0000000080000268 <test_11>: + 80000268: 00002097 auipc ra,0x2 + 8000026c: db808093 addi ra,ra,-584 # 80002020 <tdat9> + 80000270: 58213137 lui sp,0x58213 + 80000274: 0981011b addiw sp,sp,152 + 80000278: ffd08093 addi ra,ra,-3 + 8000027c: 0020a3a3 sw sp,7(ra) + 80000280: 00002217 auipc tp,0x2 + 80000284: da420213 addi tp,tp,-604 # 80002024 <tdat10> + 80000288: 00022283 lw t0,0(tp) # 0 <_start-0x80000000> + 8000028c: 58213eb7 lui t4,0x58213 + 80000290: 098e8e9b addiw t4,t4,152 + 80000294: 00b00193 li gp,11 + 80000298: 2fd29463 bne t0,t4,80000580 <fail> + +000000008000029c <test_12>: + 8000029c: 00c00193 li gp,12 + 800002a0: 00000213 li tp,0 + 800002a4: aabbd0b7 lui ra,0xaabbd + 800002a8: cdd0809b addiw ra,ra,-803 + 800002ac: 00002117 auipc sp,0x2 + 800002b0: d5410113 addi sp,sp,-684 # 80002000 <begin_signature> + 800002b4: 00112023 sw ra,0(sp) + 800002b8: 00012f03 lw t5,0(sp) + 800002bc: aabbdeb7 lui t4,0xaabbd + 800002c0: cdde8e9b addiw t4,t4,-803 + 800002c4: 2bdf1e63 bne t5,t4,80000580 <fail> + 800002c8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002cc: 00200293 li t0,2 + 800002d0: fc521ae3 bne tp,t0,800002a4 <test_12+0x8> + +00000000800002d4 <test_13>: + 800002d4: 00d00193 li gp,13 + 800002d8: 00000213 li tp,0 + 800002dc: daabc0b7 lui ra,0xdaabc + 800002e0: ccd0809b addiw ra,ra,-819 + 800002e4: 00002117 auipc sp,0x2 + 800002e8: d1c10113 addi sp,sp,-740 # 80002000 <begin_signature> + 800002ec: 00000013 nop + 800002f0: 00112223 sw ra,4(sp) + 800002f4: 00412f03 lw t5,4(sp) + 800002f8: daabceb7 lui t4,0xdaabc + 800002fc: ccde8e9b addiw t4,t4,-819 + 80000300: 29df1063 bne t5,t4,80000580 <fail> + 80000304: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000308: 00200293 li t0,2 + 8000030c: fc5218e3 bne tp,t0,800002dc <test_13+0x8> + +0000000080000310 <test_14>: + 80000310: 00e00193 li gp,14 + 80000314: 00000213 li tp,0 + 80000318: ddaac0b7 lui ra,0xddaac + 8000031c: bcc0809b addiw ra,ra,-1076 + 80000320: 00002117 auipc sp,0x2 + 80000324: ce010113 addi sp,sp,-800 # 80002000 <begin_signature> + 80000328: 00000013 nop + 8000032c: 00000013 nop + 80000330: 00112423 sw ra,8(sp) + 80000334: 00812f03 lw t5,8(sp) + 80000338: ddaaceb7 lui t4,0xddaac + 8000033c: bcce8e9b addiw t4,t4,-1076 + 80000340: 25df1063 bne t5,t4,80000580 <fail> + 80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000348: 00200293 li t0,2 + 8000034c: fc5216e3 bne tp,t0,80000318 <test_14+0x8> + +0000000080000350 <test_15>: + 80000350: 00f00193 li gp,15 + 80000354: 00000213 li tp,0 + 80000358: cddab0b7 lui ra,0xcddab + 8000035c: bbc0809b addiw ra,ra,-1092 + 80000360: 00000013 nop + 80000364: 00002117 auipc sp,0x2 + 80000368: c9c10113 addi sp,sp,-868 # 80002000 <begin_signature> + 8000036c: 00112623 sw ra,12(sp) + 80000370: 00c12f03 lw t5,12(sp) + 80000374: cddabeb7 lui t4,0xcddab + 80000378: bbce8e9b addiw t4,t4,-1092 + 8000037c: 21df1263 bne t5,t4,80000580 <fail> + 80000380: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000384: 00200293 li t0,2 + 80000388: fc5218e3 bne tp,t0,80000358 <test_15+0x8> + +000000008000038c <test_16>: + 8000038c: 01000193 li gp,16 + 80000390: 00000213 li tp,0 + 80000394: ccddb0b7 lui ra,0xccddb + 80000398: abb0809b addiw ra,ra,-1349 + 8000039c: 00000013 nop + 800003a0: 00002117 auipc sp,0x2 + 800003a4: c6010113 addi sp,sp,-928 # 80002000 <begin_signature> + 800003a8: 00000013 nop + 800003ac: 00112823 sw ra,16(sp) + 800003b0: 01012f03 lw t5,16(sp) + 800003b4: ccddbeb7 lui t4,0xccddb + 800003b8: abbe8e9b addiw t4,t4,-1349 + 800003bc: 1ddf1263 bne t5,t4,80000580 <fail> + 800003c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003c4: 00200293 li t0,2 + 800003c8: fc5216e3 bne tp,t0,80000394 <test_16+0x8> + +00000000800003cc <test_17>: + 800003cc: 01100193 li gp,17 + 800003d0: 00000213 li tp,0 + 800003d4: bccde0b7 lui ra,0xbccde + 800003d8: aab0809b addiw ra,ra,-1365 + 800003dc: 00000013 nop + 800003e0: 00000013 nop + 800003e4: 00002117 auipc sp,0x2 + 800003e8: c1c10113 addi sp,sp,-996 # 80002000 <begin_signature> + 800003ec: 00112a23 sw ra,20(sp) + 800003f0: 01412f03 lw t5,20(sp) + 800003f4: bccdeeb7 lui t4,0xbccde + 800003f8: aabe8e9b addiw t4,t4,-1365 + 800003fc: 19df1263 bne t5,t4,80000580 <fail> + 80000400: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000404: 00200293 li t0,2 + 80000408: fc5216e3 bne tp,t0,800003d4 <test_17+0x8> + +000000008000040c <test_18>: + 8000040c: 01200193 li gp,18 + 80000410: 00000213 li tp,0 + 80000414: 00002117 auipc sp,0x2 + 80000418: bec10113 addi sp,sp,-1044 # 80002000 <begin_signature> + 8000041c: 001120b7 lui ra,0x112 + 80000420: 2330809b addiw ra,ra,563 + 80000424: 00112023 sw ra,0(sp) + 80000428: 00012f03 lw t5,0(sp) + 8000042c: 00112eb7 lui t4,0x112 + 80000430: 233e8e9b addiw t4,t4,563 + 80000434: 15df1663 bne t5,t4,80000580 <fail> + 80000438: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000043c: 00200293 li t0,2 + 80000440: fc521ae3 bne tp,t0,80000414 <test_18+0x8> + +0000000080000444 <test_19>: + 80000444: 01300193 li gp,19 + 80000448: 00000213 li tp,0 + 8000044c: 00002117 auipc sp,0x2 + 80000450: bb410113 addi sp,sp,-1100 # 80002000 <begin_signature> + 80000454: 300110b7 lui ra,0x30011 + 80000458: 2230809b addiw ra,ra,547 + 8000045c: 00000013 nop + 80000460: 00112223 sw ra,4(sp) + 80000464: 00412f03 lw t5,4(sp) + 80000468: 30011eb7 lui t4,0x30011 + 8000046c: 223e8e9b addiw t4,t4,547 + 80000470: 11df1863 bne t5,t4,80000580 <fail> + 80000474: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000478: 00200293 li t0,2 + 8000047c: fc5218e3 bne tp,t0,8000044c <test_19+0x8> + +0000000080000480 <test_20>: + 80000480: 01400193 li gp,20 + 80000484: 00000213 li tp,0 + 80000488: 00002117 auipc sp,0x2 + 8000048c: b7810113 addi sp,sp,-1160 # 80002000 <begin_signature> + 80000490: 330010b7 lui ra,0x33001 + 80000494: 1220809b addiw ra,ra,290 + 80000498: 00000013 nop + 8000049c: 00000013 nop + 800004a0: 00112423 sw ra,8(sp) + 800004a4: 00812f03 lw t5,8(sp) + 800004a8: 33001eb7 lui t4,0x33001 + 800004ac: 122e8e9b addiw t4,t4,290 + 800004b0: 0ddf1863 bne t5,t4,80000580 <fail> + 800004b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004b8: 00200293 li t0,2 + 800004bc: fc5216e3 bne tp,t0,80000488 <test_20+0x8> + +00000000800004c0 <test_21>: + 800004c0: 01500193 li gp,21 + 800004c4: 00000213 li tp,0 + 800004c8: 00002117 auipc sp,0x2 + 800004cc: b3810113 addi sp,sp,-1224 # 80002000 <begin_signature> + 800004d0: 00000013 nop + 800004d4: 233000b7 lui ra,0x23300 + 800004d8: 1120809b addiw ra,ra,274 + 800004dc: 00112623 sw ra,12(sp) + 800004e0: 00c12f03 lw t5,12(sp) + 800004e4: 23300eb7 lui t4,0x23300 + 800004e8: 112e8e9b addiw t4,t4,274 + 800004ec: 09df1a63 bne t5,t4,80000580 <fail> + 800004f0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004f4: 00200293 li t0,2 + 800004f8: fc5218e3 bne tp,t0,800004c8 <test_21+0x8> + +00000000800004fc <test_22>: + 800004fc: 01600193 li gp,22 + 80000500: 00000213 li tp,0 + 80000504: 00002117 auipc sp,0x2 + 80000508: afc10113 addi sp,sp,-1284 # 80002000 <begin_signature> + 8000050c: 00000013 nop + 80000510: 223300b7 lui ra,0x22330 + 80000514: 0110809b addiw ra,ra,17 + 80000518: 00000013 nop + 8000051c: 00112823 sw ra,16(sp) + 80000520: 01012f03 lw t5,16(sp) + 80000524: 22330eb7 lui t4,0x22330 + 80000528: 011e8e9b addiw t4,t4,17 + 8000052c: 05df1a63 bne t5,t4,80000580 <fail> + 80000530: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000534: 00200293 li t0,2 + 80000538: fc5216e3 bne tp,t0,80000504 <test_22+0x8> + +000000008000053c <test_23>: + 8000053c: 01700193 li gp,23 + 80000540: 00000213 li tp,0 + 80000544: 00002117 auipc sp,0x2 + 80000548: abc10113 addi sp,sp,-1348 # 80002000 <begin_signature> + 8000054c: 00000013 nop + 80000550: 00000013 nop + 80000554: 122330b7 lui ra,0x12233 + 80000558: 0010809b addiw ra,ra,1 + 8000055c: 00112a23 sw ra,20(sp) + 80000560: 01412f03 lw t5,20(sp) + 80000564: 12233eb7 lui t4,0x12233 + 80000568: 001e8e9b addiw t4,t4,1 + 8000056c: 01df1a63 bne t5,t4,80000580 <fail> + 80000570: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000574: 00200293 li t0,2 + 80000578: fc5216e3 bne tp,t0,80000544 <test_23+0x8> + 8000057c: 00301c63 bne zero,gp,80000594 <pass> + +0000000080000580 <fail>: + 80000580: 0ff0000f fence + 80000584: 00018063 beqz gp,80000584 <fail+0x4> + 80000588: 00119193 slli gp,gp,0x1 + 8000058c: 0011e193 ori gp,gp,1 + 80000590: 00000073 ecall + +0000000080000594 <pass>: + 80000594: 0ff0000f fence + 80000598: 00100193 li gp,1 + 8000059c: 00000073 ecall + 800005a0: c0001073 unimp + 800005a4: 0000 unimp + 800005a6: 0000 unimp + 800005a8: 0000 unimp + 800005aa: 0000 unimp + 800005ac: 0000 unimp + 800005ae: 0000 unimp + 800005b0: 0000 unimp + 800005b2: 0000 unimp + 800005b4: 0000 unimp + 800005b6: 0000 unimp + 800005b8: 0000 unimp + 800005ba: 0000 unimp + 800005bc: 0000 unimp + 800005be: 0000 unimp + 800005c0: 0000 unimp + 800005c2: 0000 unimp + +Disassembly of section .data: + +0000000080002000 <begin_signature>: + 80002000: deadbeef jal t4,7ffdd5ea <_start-0x22a16> + +0000000080002004 <tdat2>: + 80002004: deadbeef jal t4,7ffdd5ee <_start-0x22a12> + +0000000080002008 <tdat3>: + 80002008: deadbeef jal t4,7ffdd5f2 <_start-0x22a0e> + +000000008000200c <tdat4>: + 8000200c: deadbeef jal t4,7ffdd5f6 <_start-0x22a0a> + +0000000080002010 <tdat5>: + 80002010: deadbeef jal t4,7ffdd5fa <_start-0x22a06> + +0000000080002014 <tdat6>: + 80002014: deadbeef jal t4,7ffdd5fe <_start-0x22a02> + +0000000080002018 <tdat7>: + 80002018: deadbeef jal t4,7ffdd602 <_start-0x229fe> + +000000008000201c <tdat8>: + 8000201c: deadbeef jal t4,7ffdd606 <_start-0x229fa> + +0000000080002020 <tdat9>: + 80002020: deadbeef jal t4,7ffdd60a <_start-0x229f6> + +0000000080002024 <tdat10>: + 80002024: deadbeef jal t4,7ffdd60e <_start-0x229f2> + 80002028: 0000 unimp + 8000202a: 0000 unimp + 8000202c: 0000 unimp + 8000202e: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-sw.elf b/test/riscv/tests/rv64ui-p-sw.elf Binary files differnew file mode 100755 index 00000000..0b7daaa8 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-sw.elf diff --git a/test/riscv/tests/rv64ui-p-xor.dump b/test/riscv/tests/rv64ui-p-xor.dump new file mode 100644 index 00000000..2f6d21b3 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-xor.dump @@ -0,0 +1,527 @@ + +rv64ui-p-xor: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 000100b7 lui ra,0x10 + 80000100: f010809b addiw ra,ra,-255 + 80000104: 01009093 slli ra,ra,0x10 + 80000108: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 8000010c: 0f0f1137 lui sp,0xf0f1 + 80000110: f0f1011b addiw sp,sp,-241 + 80000114: 0020cf33 xor t5,ra,sp + 80000118: 000f0eb7 lui t4,0xf0 + 8000011c: 0ffe8e9b addiw t4,t4,255 + 80000120: 00ce9e93 slli t4,t4,0xc + 80000124: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80000128: 00200193 li gp,2 + 8000012c: 59df1c63 bne t5,t4,800006c4 <fail> + +0000000080000130 <test_3>: + 80000130: 0ff010b7 lui ra,0xff01 + 80000134: ff00809b addiw ra,ra,-16 + 80000138: 000f1137 lui sp,0xf1 + 8000013c: f0f1011b addiw sp,sp,-241 + 80000140: 00c11113 slli sp,sp,0xc + 80000144: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80000148: 0020cf33 xor t5,ra,sp + 8000014c: 00010eb7 lui t4,0x10 + 80000150: f01e8e9b addiw t4,t4,-255 + 80000154: 010e9e93 slli t4,t4,0x10 + 80000158: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 8000015c: 00300193 li gp,3 + 80000160: 57df1263 bne t5,t4,800006c4 <fail> + +0000000080000164 <test_4>: + 80000164: 00ff00b7 lui ra,0xff0 + 80000168: 0ff0809b addiw ra,ra,255 + 8000016c: 0f0f1137 lui sp,0xf0f1 + 80000170: f0f1011b addiw sp,sp,-241 + 80000174: 0020cf33 xor t5,ra,sp + 80000178: 0ff01eb7 lui t4,0xff01 + 8000017c: ff0e8e9b addiw t4,t4,-16 + 80000180: 00400193 li gp,4 + 80000184: 55df1063 bne t5,t4,800006c4 <fail> + +0000000080000188 <test_5>: + 80000188: 000f00b7 lui ra,0xf0 + 8000018c: 0ff0809b addiw ra,ra,255 + 80000190: 00c09093 slli ra,ra,0xc + 80000194: 00f08093 addi ra,ra,15 # f000f <_start-0x7ff0fff1> + 80000198: 000f1137 lui sp,0xf1 + 8000019c: f0f1011b addiw sp,sp,-241 + 800001a0: 00c11113 slli sp,sp,0xc + 800001a4: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 800001a8: 0020cf33 xor t5,ra,sp + 800001ac: 00ff0eb7 lui t4,0xff0 + 800001b0: 0ffe8e9b addiw t4,t4,255 + 800001b4: 00500193 li gp,5 + 800001b8: 51df1663 bne t5,t4,800006c4 <fail> + +00000000800001bc <test_6>: + 800001bc: 000100b7 lui ra,0x10 + 800001c0: f010809b addiw ra,ra,-255 + 800001c4: 01009093 slli ra,ra,0x10 + 800001c8: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 800001cc: 0f0f1137 lui sp,0xf0f1 + 800001d0: f0f1011b addiw sp,sp,-241 + 800001d4: 0020c0b3 xor ra,ra,sp + 800001d8: 000f0eb7 lui t4,0xf0 + 800001dc: 0ffe8e9b addiw t4,t4,255 + 800001e0: 00ce9e93 slli t4,t4,0xc + 800001e4: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 800001e8: 00600193 li gp,6 + 800001ec: 4dd09c63 bne ra,t4,800006c4 <fail> + +00000000800001f0 <test_7>: + 800001f0: 000100b7 lui ra,0x10 + 800001f4: f010809b addiw ra,ra,-255 + 800001f8: 01009093 slli ra,ra,0x10 + 800001fc: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000200: 0f0f1137 lui sp,0xf0f1 + 80000204: f0f1011b addiw sp,sp,-241 + 80000208: 0020c133 xor sp,ra,sp + 8000020c: 000f0eb7 lui t4,0xf0 + 80000210: 0ffe8e9b addiw t4,t4,255 + 80000214: 00ce9e93 slli t4,t4,0xc + 80000218: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 8000021c: 00700193 li gp,7 + 80000220: 4bd11263 bne sp,t4,800006c4 <fail> + +0000000080000224 <test_8>: + 80000224: 000100b7 lui ra,0x10 + 80000228: f010809b addiw ra,ra,-255 + 8000022c: 01009093 slli ra,ra,0x10 + 80000230: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000234: 0010c0b3 xor ra,ra,ra + 80000238: 00000e93 li t4,0 + 8000023c: 00800193 li gp,8 + 80000240: 49d09263 bne ra,t4,800006c4 <fail> + +0000000080000244 <test_9>: + 80000244: 00000213 li tp,0 + 80000248: 000100b7 lui ra,0x10 + 8000024c: f010809b addiw ra,ra,-255 + 80000250: 01009093 slli ra,ra,0x10 + 80000254: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000258: 0f0f1137 lui sp,0xf0f1 + 8000025c: f0f1011b addiw sp,sp,-241 + 80000260: 0020cf33 xor t5,ra,sp + 80000264: 000f0313 mv t1,t5 + 80000268: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000026c: 00200293 li t0,2 + 80000270: fc521ce3 bne tp,t0,80000248 <test_9+0x4> + 80000274: 000f0eb7 lui t4,0xf0 + 80000278: 0ffe8e9b addiw t4,t4,255 + 8000027c: 00ce9e93 slli t4,t4,0xc + 80000280: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80000284: 00900193 li gp,9 + 80000288: 43d31e63 bne t1,t4,800006c4 <fail> + +000000008000028c <test_10>: + 8000028c: 00000213 li tp,0 + 80000290: 0ff010b7 lui ra,0xff01 + 80000294: ff00809b addiw ra,ra,-16 + 80000298: 000f1137 lui sp,0xf1 + 8000029c: f0f1011b addiw sp,sp,-241 + 800002a0: 00c11113 slli sp,sp,0xc + 800002a4: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 800002a8: 0020cf33 xor t5,ra,sp + 800002ac: 00000013 nop + 800002b0: 000f0313 mv t1,t5 + 800002b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002b8: 00200293 li t0,2 + 800002bc: fc521ae3 bne tp,t0,80000290 <test_10+0x4> + 800002c0: 00010eb7 lui t4,0x10 + 800002c4: f01e8e9b addiw t4,t4,-255 + 800002c8: 010e9e93 slli t4,t4,0x10 + 800002cc: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 800002d0: 00a00193 li gp,10 + 800002d4: 3fd31863 bne t1,t4,800006c4 <fail> + +00000000800002d8 <test_11>: + 800002d8: 00000213 li tp,0 + 800002dc: 00ff00b7 lui ra,0xff0 + 800002e0: 0ff0809b addiw ra,ra,255 + 800002e4: 0f0f1137 lui sp,0xf0f1 + 800002e8: f0f1011b addiw sp,sp,-241 + 800002ec: 0020cf33 xor t5,ra,sp + 800002f0: 00000013 nop + 800002f4: 00000013 nop + 800002f8: 000f0313 mv t1,t5 + 800002fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000300: 00200293 li t0,2 + 80000304: fc521ce3 bne tp,t0,800002dc <test_11+0x4> + 80000308: 0ff01eb7 lui t4,0xff01 + 8000030c: ff0e8e9b addiw t4,t4,-16 + 80000310: 00b00193 li gp,11 + 80000314: 3bd31863 bne t1,t4,800006c4 <fail> + +0000000080000318 <test_12>: + 80000318: 00000213 li tp,0 + 8000031c: 000100b7 lui ra,0x10 + 80000320: f010809b addiw ra,ra,-255 + 80000324: 01009093 slli ra,ra,0x10 + 80000328: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 8000032c: 0f0f1137 lui sp,0xf0f1 + 80000330: f0f1011b addiw sp,sp,-241 + 80000334: 0020cf33 xor t5,ra,sp + 80000338: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000033c: 00200293 li t0,2 + 80000340: fc521ee3 bne tp,t0,8000031c <test_12+0x4> + 80000344: 000f0eb7 lui t4,0xf0 + 80000348: 0ffe8e9b addiw t4,t4,255 + 8000034c: 00ce9e93 slli t4,t4,0xc + 80000350: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80000354: 00c00193 li gp,12 + 80000358: 37df1663 bne t5,t4,800006c4 <fail> + +000000008000035c <test_13>: + 8000035c: 00000213 li tp,0 + 80000360: 0ff010b7 lui ra,0xff01 + 80000364: ff00809b addiw ra,ra,-16 + 80000368: 000f1137 lui sp,0xf1 + 8000036c: f0f1011b addiw sp,sp,-241 + 80000370: 00c11113 slli sp,sp,0xc + 80000374: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80000378: 00000013 nop + 8000037c: 0020cf33 xor t5,ra,sp + 80000380: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000384: 00200293 li t0,2 + 80000388: fc521ce3 bne tp,t0,80000360 <test_13+0x4> + 8000038c: 00010eb7 lui t4,0x10 + 80000390: f01e8e9b addiw t4,t4,-255 + 80000394: 010e9e93 slli t4,t4,0x10 + 80000398: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 8000039c: 00d00193 li gp,13 + 800003a0: 33df1263 bne t5,t4,800006c4 <fail> + +00000000800003a4 <test_14>: + 800003a4: 00000213 li tp,0 + 800003a8: 00ff00b7 lui ra,0xff0 + 800003ac: 0ff0809b addiw ra,ra,255 + 800003b0: 0f0f1137 lui sp,0xf0f1 + 800003b4: f0f1011b addiw sp,sp,-241 + 800003b8: 00000013 nop + 800003bc: 00000013 nop + 800003c0: 0020cf33 xor t5,ra,sp + 800003c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003c8: 00200293 li t0,2 + 800003cc: fc521ee3 bne tp,t0,800003a8 <test_14+0x4> + 800003d0: 0ff01eb7 lui t4,0xff01 + 800003d4: ff0e8e9b addiw t4,t4,-16 + 800003d8: 00e00193 li gp,14 + 800003dc: 2fdf1463 bne t5,t4,800006c4 <fail> + +00000000800003e0 <test_15>: + 800003e0: 00000213 li tp,0 + 800003e4: 000100b7 lui ra,0x10 + 800003e8: f010809b addiw ra,ra,-255 + 800003ec: 01009093 slli ra,ra,0x10 + 800003f0: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 800003f4: 00000013 nop + 800003f8: 0f0f1137 lui sp,0xf0f1 + 800003fc: f0f1011b addiw sp,sp,-241 + 80000400: 0020cf33 xor t5,ra,sp + 80000404: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000408: 00200293 li t0,2 + 8000040c: fc521ce3 bne tp,t0,800003e4 <test_15+0x4> + 80000410: 000f0eb7 lui t4,0xf0 + 80000414: 0ffe8e9b addiw t4,t4,255 + 80000418: 00ce9e93 slli t4,t4,0xc + 8000041c: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 80000420: 00f00193 li gp,15 + 80000424: 2bdf1063 bne t5,t4,800006c4 <fail> + +0000000080000428 <test_16>: + 80000428: 00000213 li tp,0 + 8000042c: 0ff010b7 lui ra,0xff01 + 80000430: ff00809b addiw ra,ra,-16 + 80000434: 00000013 nop + 80000438: 000f1137 lui sp,0xf1 + 8000043c: f0f1011b addiw sp,sp,-241 + 80000440: 00c11113 slli sp,sp,0xc + 80000444: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80000448: 00000013 nop + 8000044c: 0020cf33 xor t5,ra,sp + 80000450: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000454: 00200293 li t0,2 + 80000458: fc521ae3 bne tp,t0,8000042c <test_16+0x4> + 8000045c: 00010eb7 lui t4,0x10 + 80000460: f01e8e9b addiw t4,t4,-255 + 80000464: 010e9e93 slli t4,t4,0x10 + 80000468: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 8000046c: 01000193 li gp,16 + 80000470: 25df1a63 bne t5,t4,800006c4 <fail> + +0000000080000474 <test_17>: + 80000474: 00000213 li tp,0 + 80000478: 00ff00b7 lui ra,0xff0 + 8000047c: 0ff0809b addiw ra,ra,255 + 80000480: 00000013 nop + 80000484: 00000013 nop + 80000488: 0f0f1137 lui sp,0xf0f1 + 8000048c: f0f1011b addiw sp,sp,-241 + 80000490: 0020cf33 xor t5,ra,sp + 80000494: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000498: 00200293 li t0,2 + 8000049c: fc521ee3 bne tp,t0,80000478 <test_17+0x4> + 800004a0: 0ff01eb7 lui t4,0xff01 + 800004a4: ff0e8e9b addiw t4,t4,-16 + 800004a8: 01100193 li gp,17 + 800004ac: 21df1c63 bne t5,t4,800006c4 <fail> + +00000000800004b0 <test_18>: + 800004b0: 00000213 li tp,0 + 800004b4: 0f0f1137 lui sp,0xf0f1 + 800004b8: f0f1011b addiw sp,sp,-241 + 800004bc: 000100b7 lui ra,0x10 + 800004c0: f010809b addiw ra,ra,-255 + 800004c4: 01009093 slli ra,ra,0x10 + 800004c8: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 800004cc: 0020cf33 xor t5,ra,sp + 800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004d4: 00200293 li t0,2 + 800004d8: fc521ee3 bne tp,t0,800004b4 <test_18+0x4> + 800004dc: 000f0eb7 lui t4,0xf0 + 800004e0: 0ffe8e9b addiw t4,t4,255 + 800004e4: 00ce9e93 slli t4,t4,0xc + 800004e8: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 800004ec: 01200193 li gp,18 + 800004f0: 1ddf1a63 bne t5,t4,800006c4 <fail> + +00000000800004f4 <test_19>: + 800004f4: 00000213 li tp,0 + 800004f8: 000f1137 lui sp,0xf1 + 800004fc: f0f1011b addiw sp,sp,-241 + 80000500: 00c11113 slli sp,sp,0xc + 80000504: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 80000508: 0ff010b7 lui ra,0xff01 + 8000050c: ff00809b addiw ra,ra,-16 + 80000510: 00000013 nop + 80000514: 0020cf33 xor t5,ra,sp + 80000518: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000051c: 00200293 li t0,2 + 80000520: fc521ce3 bne tp,t0,800004f8 <test_19+0x4> + 80000524: 00010eb7 lui t4,0x10 + 80000528: f01e8e9b addiw t4,t4,-255 + 8000052c: 010e9e93 slli t4,t4,0x10 + 80000530: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80000534: 01300193 li gp,19 + 80000538: 19df1663 bne t5,t4,800006c4 <fail> + +000000008000053c <test_20>: + 8000053c: 00000213 li tp,0 + 80000540: 0f0f1137 lui sp,0xf0f1 + 80000544: f0f1011b addiw sp,sp,-241 + 80000548: 00ff00b7 lui ra,0xff0 + 8000054c: 0ff0809b addiw ra,ra,255 + 80000550: 00000013 nop + 80000554: 00000013 nop + 80000558: 0020cf33 xor t5,ra,sp + 8000055c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000560: 00200293 li t0,2 + 80000564: fc521ee3 bne tp,t0,80000540 <test_20+0x4> + 80000568: 0ff01eb7 lui t4,0xff01 + 8000056c: ff0e8e9b addiw t4,t4,-16 + 80000570: 01400193 li gp,20 + 80000574: 15df1863 bne t5,t4,800006c4 <fail> + +0000000080000578 <test_21>: + 80000578: 00000213 li tp,0 + 8000057c: 0f0f1137 lui sp,0xf0f1 + 80000580: f0f1011b addiw sp,sp,-241 + 80000584: 00000013 nop + 80000588: 000100b7 lui ra,0x10 + 8000058c: f010809b addiw ra,ra,-255 + 80000590: 01009093 slli ra,ra,0x10 + 80000594: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000598: 0020cf33 xor t5,ra,sp + 8000059c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005a0: 00200293 li t0,2 + 800005a4: fc521ce3 bne tp,t0,8000057c <test_21+0x4> + 800005a8: 000f0eb7 lui t4,0xf0 + 800005ac: 0ffe8e9b addiw t4,t4,255 + 800005b0: 00ce9e93 slli t4,t4,0xc + 800005b4: 00fe8e93 addi t4,t4,15 # f000f <_start-0x7ff0fff1> + 800005b8: 01500193 li gp,21 + 800005bc: 11df1463 bne t5,t4,800006c4 <fail> + +00000000800005c0 <test_22>: + 800005c0: 00000213 li tp,0 + 800005c4: 000f1137 lui sp,0xf1 + 800005c8: f0f1011b addiw sp,sp,-241 + 800005cc: 00c11113 slli sp,sp,0xc + 800005d0: 0f010113 addi sp,sp,240 # f10f0 <_start-0x7ff0ef10> + 800005d4: 00000013 nop + 800005d8: 0ff010b7 lui ra,0xff01 + 800005dc: ff00809b addiw ra,ra,-16 + 800005e0: 00000013 nop + 800005e4: 0020cf33 xor t5,ra,sp + 800005e8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800005ec: 00200293 li t0,2 + 800005f0: fc521ae3 bne tp,t0,800005c4 <test_22+0x4> + 800005f4: 00010eb7 lui t4,0x10 + 800005f8: f01e8e9b addiw t4,t4,-255 + 800005fc: 010e9e93 slli t4,t4,0x10 + 80000600: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 80000604: 01600193 li gp,22 + 80000608: 0bdf1e63 bne t5,t4,800006c4 <fail> + +000000008000060c <test_23>: + 8000060c: 00000213 li tp,0 + 80000610: 0f0f1137 lui sp,0xf0f1 + 80000614: f0f1011b addiw sp,sp,-241 + 80000618: 00000013 nop + 8000061c: 00000013 nop + 80000620: 00ff00b7 lui ra,0xff0 + 80000624: 0ff0809b addiw ra,ra,255 + 80000628: 0020cf33 xor t5,ra,sp + 8000062c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000630: 00200293 li t0,2 + 80000634: fc521ee3 bne tp,t0,80000610 <test_23+0x4> + 80000638: 0ff01eb7 lui t4,0xff01 + 8000063c: ff0e8e9b addiw t4,t4,-16 + 80000640: 01700193 li gp,23 + 80000644: 09df1063 bne t5,t4,800006c4 <fail> + +0000000080000648 <test_24>: + 80000648: 000100b7 lui ra,0x10 + 8000064c: f010809b addiw ra,ra,-255 + 80000650: 01009093 slli ra,ra,0x10 + 80000654: f0008093 addi ra,ra,-256 # ff00 <_start-0x7fff0100> + 80000658: 00104133 xor sp,zero,ra + 8000065c: 00010eb7 lui t4,0x10 + 80000660: f01e8e9b addiw t4,t4,-255 + 80000664: 010e9e93 slli t4,t4,0x10 + 80000668: f00e8e93 addi t4,t4,-256 # ff00 <_start-0x7fff0100> + 8000066c: 01800193 li gp,24 + 80000670: 05d11a63 bne sp,t4,800006c4 <fail> + +0000000080000674 <test_25>: + 80000674: 00ff00b7 lui ra,0xff0 + 80000678: 0ff0809b addiw ra,ra,255 + 8000067c: 0000c133 xor sp,ra,zero + 80000680: 00ff0eb7 lui t4,0xff0 + 80000684: 0ffe8e9b addiw t4,t4,255 + 80000688: 01900193 li gp,25 + 8000068c: 03d11c63 bne sp,t4,800006c4 <fail> + +0000000080000690 <test_26>: + 80000690: 000040b3 xor ra,zero,zero + 80000694: 00000e93 li t4,0 + 80000698: 01a00193 li gp,26 + 8000069c: 03d09463 bne ra,t4,800006c4 <fail> + +00000000800006a0 <test_27>: + 800006a0: 111110b7 lui ra,0x11111 + 800006a4: 1110809b addiw ra,ra,273 + 800006a8: 22222137 lui sp,0x22222 + 800006ac: 2221011b addiw sp,sp,546 + 800006b0: 0020c033 xor zero,ra,sp + 800006b4: 00000e93 li t4,0 + 800006b8: 01b00193 li gp,27 + 800006bc: 01d01463 bne zero,t4,800006c4 <fail> + 800006c0: 00301c63 bne zero,gp,800006d8 <pass> + +00000000800006c4 <fail>: + 800006c4: 0ff0000f fence + 800006c8: 00018063 beqz gp,800006c8 <fail+0x4> + 800006cc: 00119193 slli gp,gp,0x1 + 800006d0: 0011e193 ori gp,gp,1 + 800006d4: 00000073 ecall + +00000000800006d8 <pass>: + 800006d8: 0ff0000f fence + 800006dc: 00100193 li gp,1 + 800006e0: 00000073 ecall + 800006e4: c0001073 unimp + 800006e8: 0000 unimp + 800006ea: 0000 unimp + 800006ec: 0000 unimp + 800006ee: 0000 unimp + 800006f0: 0000 unimp + 800006f2: 0000 unimp + 800006f4: 0000 unimp + 800006f6: 0000 unimp + 800006f8: 0000 unimp + 800006fa: 0000 unimp + 800006fc: 0000 unimp + 800006fe: 0000 unimp + 80000700: 0000 unimp + 80000702: 0000 unimp diff --git a/test/riscv/tests/rv64ui-p-xor.elf b/test/riscv/tests/rv64ui-p-xor.elf Binary files differnew file mode 100755 index 00000000..e610fc9c --- /dev/null +++ b/test/riscv/tests/rv64ui-p-xor.elf diff --git a/test/riscv/tests/rv64ui-p-xori.dump b/test/riscv/tests/rv64ui-p-xori.dump new file mode 100644 index 00000000..12f6997d --- /dev/null +++ b/test/riscv/tests/rv64ui-p-xori.dump @@ -0,0 +1,238 @@ + +rv64ui-p-xori: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00ff10b7 lui ra,0xff1 + 80000100: f000809b addiw ra,ra,-256 + 80000104: f0f0cf13 xori t5,ra,-241 + 80000108: ff00feb7 lui t4,0xff00f + 8000010c: 00fe8e9b addiw t4,t4,15 + 80000110: 00200193 li gp,2 + 80000114: 1ddf1663 bne t5,t4,800002e0 <fail> + +0000000080000118 <test_3>: + 80000118: 0ff010b7 lui ra,0xff01 + 8000011c: ff00809b addiw ra,ra,-16 + 80000120: 0f00cf13 xori t5,ra,240 + 80000124: 0ff01eb7 lui t4,0xff01 + 80000128: f00e8e9b addiw t4,t4,-256 + 8000012c: 00300193 li gp,3 + 80000130: 1bdf1863 bne t5,t4,800002e0 <fail> + +0000000080000134 <test_4>: + 80000134: 00ff10b7 lui ra,0xff1 + 80000138: 8ff0809b addiw ra,ra,-1793 + 8000013c: 70f0cf13 xori t5,ra,1807 + 80000140: 00ff1eb7 lui t4,0xff1 + 80000144: ff0e8e9b addiw t4,t4,-16 + 80000148: 00400193 li gp,4 + 8000014c: 19df1a63 bne t5,t4,800002e0 <fail> + +0000000080000150 <test_5>: + 80000150: f00ff0b7 lui ra,0xf00ff + 80000154: 00f0809b addiw ra,ra,15 + 80000158: 0f00cf13 xori t5,ra,240 + 8000015c: f00ffeb7 lui t4,0xf00ff + 80000160: 0ffe8e9b addiw t4,t4,255 + 80000164: 00500193 li gp,5 + 80000168: 17df1c63 bne t5,t4,800002e0 <fail> + +000000008000016c <test_6>: + 8000016c: ff00f0b7 lui ra,0xff00f + 80000170: 7000809b addiw ra,ra,1792 + 80000174: 70f0c093 xori ra,ra,1807 + 80000178: ff00feb7 lui t4,0xff00f + 8000017c: 00fe8e9b addiw t4,t4,15 + 80000180: 00600193 li gp,6 + 80000184: 15d09e63 bne ra,t4,800002e0 <fail> + +0000000080000188 <test_7>: + 80000188: 00000213 li tp,0 + 8000018c: 0ff010b7 lui ra,0xff01 + 80000190: ff00809b addiw ra,ra,-16 + 80000194: 0f00cf13 xori t5,ra,240 + 80000198: 000f0313 mv t1,t5 + 8000019c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800001a0: 00200293 li t0,2 + 800001a4: fe5214e3 bne tp,t0,8000018c <test_7+0x4> + 800001a8: 0ff01eb7 lui t4,0xff01 + 800001ac: f00e8e9b addiw t4,t4,-256 + 800001b0: 00700193 li gp,7 + 800001b4: 13d31663 bne t1,t4,800002e0 <fail> + +00000000800001b8 <test_8>: + 800001b8: 00000213 li tp,0 + 800001bc: 00ff10b7 lui ra,0xff1 + 800001c0: 8ff0809b addiw ra,ra,-1793 + 800001c4: 70f0cf13 xori t5,ra,1807 + 800001c8: 00000013 nop + 800001cc: 000f0313 mv t1,t5 + 800001d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800001d4: 00200293 li t0,2 + 800001d8: fe5212e3 bne tp,t0,800001bc <test_8+0x4> + 800001dc: 00ff1eb7 lui t4,0xff1 + 800001e0: ff0e8e9b addiw t4,t4,-16 + 800001e4: 00800193 li gp,8 + 800001e8: 0fd31c63 bne t1,t4,800002e0 <fail> + +00000000800001ec <test_9>: + 800001ec: 00000213 li tp,0 + 800001f0: f00ff0b7 lui ra,0xf00ff + 800001f4: 00f0809b addiw ra,ra,15 + 800001f8: 0f00cf13 xori t5,ra,240 + 800001fc: 00000013 nop + 80000200: 00000013 nop + 80000204: 000f0313 mv t1,t5 + 80000208: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000020c: 00200293 li t0,2 + 80000210: fe5210e3 bne tp,t0,800001f0 <test_9+0x4> + 80000214: f00ffeb7 lui t4,0xf00ff + 80000218: 0ffe8e9b addiw t4,t4,255 + 8000021c: 00900193 li gp,9 + 80000220: 0dd31063 bne t1,t4,800002e0 <fail> + +0000000080000224 <test_10>: + 80000224: 00000213 li tp,0 + 80000228: 0ff010b7 lui ra,0xff01 + 8000022c: ff00809b addiw ra,ra,-16 + 80000230: 0f00cf13 xori t5,ra,240 + 80000234: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000238: 00200293 li t0,2 + 8000023c: fe5216e3 bne tp,t0,80000228 <test_10+0x4> + 80000240: 0ff01eb7 lui t4,0xff01 + 80000244: f00e8e9b addiw t4,t4,-256 + 80000248: 00a00193 li gp,10 + 8000024c: 09df1a63 bne t5,t4,800002e0 <fail> + +0000000080000250 <test_11>: + 80000250: 00000213 li tp,0 + 80000254: 00ff10b7 lui ra,0xff1 + 80000258: fff0809b addiw ra,ra,-1 + 8000025c: 00000013 nop + 80000260: 00f0cf13 xori t5,ra,15 + 80000264: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000268: 00200293 li t0,2 + 8000026c: fe5214e3 bne tp,t0,80000254 <test_11+0x4> + 80000270: 00ff1eb7 lui t4,0xff1 + 80000274: ff0e8e9b addiw t4,t4,-16 + 80000278: 00b00193 li gp,11 + 8000027c: 07df1263 bne t5,t4,800002e0 <fail> + +0000000080000280 <test_12>: + 80000280: 00000213 li tp,0 + 80000284: f00ff0b7 lui ra,0xf00ff + 80000288: 00f0809b addiw ra,ra,15 + 8000028c: 00000013 nop + 80000290: 00000013 nop + 80000294: 0f00cf13 xori t5,ra,240 + 80000298: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000029c: 00200293 li t0,2 + 800002a0: fe5212e3 bne tp,t0,80000284 <test_12+0x4> + 800002a4: f00ffeb7 lui t4,0xf00ff + 800002a8: 0ffe8e9b addiw t4,t4,255 + 800002ac: 00c00193 li gp,12 + 800002b0: 03df1863 bne t5,t4,800002e0 <fail> + +00000000800002b4 <test_13>: + 800002b4: 0f004093 xori ra,zero,240 + 800002b8: 0f000e93 li t4,240 + 800002bc: 00d00193 li gp,13 + 800002c0: 03d09063 bne ra,t4,800002e0 <fail> + +00000000800002c4 <test_14>: + 800002c4: 00ff00b7 lui ra,0xff0 + 800002c8: 0ff0809b addiw ra,ra,255 + 800002cc: 70f0c013 xori zero,ra,1807 + 800002d0: 00000e93 li t4,0 + 800002d4: 00e00193 li gp,14 + 800002d8: 01d01463 bne zero,t4,800002e0 <fail> + 800002dc: 00301c63 bne zero,gp,800002f4 <pass> + +00000000800002e0 <fail>: + 800002e0: 0ff0000f fence + 800002e4: 00018063 beqz gp,800002e4 <fail+0x4> + 800002e8: 00119193 slli gp,gp,0x1 + 800002ec: 0011e193 ori gp,gp,1 + 800002f0: 00000073 ecall + +00000000800002f4 <pass>: + 800002f4: 0ff0000f fence + 800002f8: 00100193 li gp,1 + 800002fc: 00000073 ecall + 80000300: c0001073 unimp diff --git a/test/riscv/tests/rv64ui-p-xori.elf b/test/riscv/tests/rv64ui-p-xori.elf Binary files differnew file mode 100755 index 00000000..4e8f1fd3 --- /dev/null +++ b/test/riscv/tests/rv64ui-p-xori.elf diff --git a/test/riscv/tests/rv64um-p-div.dump b/test/riscv/tests/rv64um-p-div.dump new file mode 100644 index 00000000..b117c5cd --- /dev/null +++ b/test/riscv/tests/rv64um-p-div.dump @@ -0,0 +1,195 @@ + +rv64um-p-div: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 01400093 li ra,20 + 80000100: 00600113 li sp,6 + 80000104: 0220cf33 div t5,ra,sp + 80000108: 00300e93 li t4,3 + 8000010c: 00200193 li gp,2 + 80000110: 0ddf1e63 bne t5,t4,800001ec <fail> + +0000000080000114 <test_3>: + 80000114: fec00093 li ra,-20 + 80000118: 00600113 li sp,6 + 8000011c: 0220cf33 div t5,ra,sp + 80000120: ffd00e93 li t4,-3 + 80000124: 00300193 li gp,3 + 80000128: 0ddf1263 bne t5,t4,800001ec <fail> + +000000008000012c <test_4>: + 8000012c: 01400093 li ra,20 + 80000130: ffa00113 li sp,-6 + 80000134: 0220cf33 div t5,ra,sp + 80000138: ffd00e93 li t4,-3 + 8000013c: 00400193 li gp,4 + 80000140: 0bdf1663 bne t5,t4,800001ec <fail> + +0000000080000144 <test_5>: + 80000144: fec00093 li ra,-20 + 80000148: ffa00113 li sp,-6 + 8000014c: 0220cf33 div t5,ra,sp + 80000150: 00300e93 li t4,3 + 80000154: 00500193 li gp,5 + 80000158: 09df1a63 bne t5,t4,800001ec <fail> + +000000008000015c <test_6>: + 8000015c: fff0009b addiw ra,zero,-1 + 80000160: 03f09093 slli ra,ra,0x3f + 80000164: 00100113 li sp,1 + 80000168: 0220cf33 div t5,ra,sp + 8000016c: fff00e9b addiw t4,zero,-1 + 80000170: 03fe9e93 slli t4,t4,0x3f + 80000174: 00600193 li gp,6 + 80000178: 07df1a63 bne t5,t4,800001ec <fail> + +000000008000017c <test_7>: + 8000017c: fff0009b addiw ra,zero,-1 + 80000180: 03f09093 slli ra,ra,0x3f + 80000184: fff00113 li sp,-1 + 80000188: 0220cf33 div t5,ra,sp + 8000018c: fff00e9b addiw t4,zero,-1 + 80000190: 03fe9e93 slli t4,t4,0x3f + 80000194: 00700193 li gp,7 + 80000198: 05df1a63 bne t5,t4,800001ec <fail> + +000000008000019c <test_8>: + 8000019c: fff0009b addiw ra,zero,-1 + 800001a0: 03f09093 slli ra,ra,0x3f + 800001a4: 00000113 li sp,0 + 800001a8: 0220cf33 div t5,ra,sp + 800001ac: fff00e93 li t4,-1 + 800001b0: 00800193 li gp,8 + 800001b4: 03df1c63 bne t5,t4,800001ec <fail> + +00000000800001b8 <test_9>: + 800001b8: 00100093 li ra,1 + 800001bc: 00000113 li sp,0 + 800001c0: 0220cf33 div t5,ra,sp + 800001c4: fff00e93 li t4,-1 + 800001c8: 00900193 li gp,9 + 800001cc: 03df1063 bne t5,t4,800001ec <fail> + +00000000800001d0 <test_10>: + 800001d0: 00000093 li ra,0 + 800001d4: 00000113 li sp,0 + 800001d8: 0220cf33 div t5,ra,sp + 800001dc: fff00e93 li t4,-1 + 800001e0: 00a00193 li gp,10 + 800001e4: 01df1463 bne t5,t4,800001ec <fail> + 800001e8: 00301c63 bne zero,gp,80000200 <pass> + +00000000800001ec <fail>: + 800001ec: 0ff0000f fence + 800001f0: 00018063 beqz gp,800001f0 <fail+0x4> + 800001f4: 00119193 slli gp,gp,0x1 + 800001f8: 0011e193 ori gp,gp,1 + 800001fc: 00000073 ecall + +0000000080000200 <pass>: + 80000200: 0ff0000f fence + 80000204: 00100193 li gp,1 + 80000208: 00000073 ecall + 8000020c: c0001073 unimp + 80000210: 0000 unimp + 80000212: 0000 unimp + 80000214: 0000 unimp + 80000216: 0000 unimp + 80000218: 0000 unimp + 8000021a: 0000 unimp + 8000021c: 0000 unimp + 8000021e: 0000 unimp + 80000220: 0000 unimp + 80000222: 0000 unimp + 80000224: 0000 unimp + 80000226: 0000 unimp + 80000228: 0000 unimp + 8000022a: 0000 unimp + 8000022c: 0000 unimp + 8000022e: 0000 unimp + 80000230: 0000 unimp + 80000232: 0000 unimp + 80000234: 0000 unimp + 80000236: 0000 unimp + 80000238: 0000 unimp + 8000023a: 0000 unimp + 8000023c: 0000 unimp + 8000023e: 0000 unimp + 80000240: 0000 unimp + 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-div.elf b/test/riscv/tests/rv64um-p-div.elf Binary files differnew file mode 100755 index 00000000..f8df5452 --- /dev/null +++ b/test/riscv/tests/rv64um-p-div.elf diff --git a/test/riscv/tests/rv64um-p-divu.dump b/test/riscv/tests/rv64um-p-divu.dump new file mode 100644 index 00000000..f987025d --- /dev/null +++ b/test/riscv/tests/rv64um-p-divu.dump @@ -0,0 +1,189 @@ + +rv64um-p-divu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 01400093 li ra,20 + 80000100: 00600113 li sp,6 + 80000104: 0220df33 divu t5,ra,sp + 80000108: 00300e93 li t4,3 + 8000010c: 00200193 li gp,2 + 80000110: 0fdf1a63 bne t5,t4,80000204 <fail> + +0000000080000114 <test_3>: + 80000114: fec00093 li ra,-20 + 80000118: 00600113 li sp,6 + 8000011c: 0220df33 divu t5,ra,sp + 80000120: 02aabeb7 lui t4,0x2aab + 80000124: aabe8e9b addiw t4,t4,-1365 + 80000128: 00ce9e93 slli t4,t4,0xc + 8000012c: aabe8e93 addi t4,t4,-1365 # 2aaaaab <_start-0x7d555555> + 80000130: 00ce9e93 slli t4,t4,0xc + 80000134: aabe8e93 addi t4,t4,-1365 + 80000138: 00ce9e93 slli t4,t4,0xc + 8000013c: aa7e8e93 addi t4,t4,-1369 + 80000140: 00300193 li gp,3 + 80000144: 0ddf1063 bne t5,t4,80000204 <fail> + +0000000080000148 <test_4>: + 80000148: 01400093 li ra,20 + 8000014c: ffa00113 li sp,-6 + 80000150: 0220df33 divu t5,ra,sp + 80000154: 00000e93 li t4,0 + 80000158: 00400193 li gp,4 + 8000015c: 0bdf1463 bne t5,t4,80000204 <fail> + +0000000080000160 <test_5>: + 80000160: fec00093 li ra,-20 + 80000164: ffa00113 li sp,-6 + 80000168: 0220df33 divu t5,ra,sp + 8000016c: 00000e93 li t4,0 + 80000170: 00500193 li gp,5 + 80000174: 09df1863 bne t5,t4,80000204 <fail> + +0000000080000178 <test_6>: + 80000178: fff0009b addiw ra,zero,-1 + 8000017c: 03f09093 slli ra,ra,0x3f + 80000180: 00100113 li sp,1 + 80000184: 0220df33 divu t5,ra,sp + 80000188: fff00e9b addiw t4,zero,-1 + 8000018c: 03fe9e93 slli t4,t4,0x3f + 80000190: 00600193 li gp,6 + 80000194: 07df1863 bne t5,t4,80000204 <fail> + +0000000080000198 <test_7>: + 80000198: fff0009b addiw ra,zero,-1 + 8000019c: 03f09093 slli ra,ra,0x3f + 800001a0: fff00113 li sp,-1 + 800001a4: 0220df33 divu t5,ra,sp + 800001a8: 00000e93 li t4,0 + 800001ac: 00700193 li gp,7 + 800001b0: 05df1a63 bne t5,t4,80000204 <fail> + +00000000800001b4 <test_8>: + 800001b4: fff0009b addiw ra,zero,-1 + 800001b8: 03f09093 slli ra,ra,0x3f + 800001bc: 00000113 li sp,0 + 800001c0: 0220df33 divu t5,ra,sp + 800001c4: fff00e93 li t4,-1 + 800001c8: 00800193 li gp,8 + 800001cc: 03df1c63 bne t5,t4,80000204 <fail> + +00000000800001d0 <test_9>: + 800001d0: 00100093 li ra,1 + 800001d4: 00000113 li sp,0 + 800001d8: 0220df33 divu t5,ra,sp + 800001dc: fff00e93 li t4,-1 + 800001e0: 00900193 li gp,9 + 800001e4: 03df1063 bne t5,t4,80000204 <fail> + +00000000800001e8 <test_10>: + 800001e8: 00000093 li ra,0 + 800001ec: 00000113 li sp,0 + 800001f0: 0220df33 divu t5,ra,sp + 800001f4: fff00e93 li t4,-1 + 800001f8: 00a00193 li gp,10 + 800001fc: 01df1463 bne t5,t4,80000204 <fail> + 80000200: 00301c63 bne zero,gp,80000218 <pass> + +0000000080000204 <fail>: + 80000204: 0ff0000f fence + 80000208: 00018063 beqz gp,80000208 <fail+0x4> + 8000020c: 00119193 slli gp,gp,0x1 + 80000210: 0011e193 ori gp,gp,1 + 80000214: 00000073 ecall + +0000000080000218 <pass>: + 80000218: 0ff0000f fence + 8000021c: 00100193 li gp,1 + 80000220: 00000073 ecall + 80000224: c0001073 unimp + 80000228: 0000 unimp + 8000022a: 0000 unimp + 8000022c: 0000 unimp + 8000022e: 0000 unimp + 80000230: 0000 unimp + 80000232: 0000 unimp + 80000234: 0000 unimp + 80000236: 0000 unimp + 80000238: 0000 unimp + 8000023a: 0000 unimp + 8000023c: 0000 unimp + 8000023e: 0000 unimp + 80000240: 0000 unimp + 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-divu.elf b/test/riscv/tests/rv64um-p-divu.elf Binary files differnew file mode 100755 index 00000000..d02748e3 --- /dev/null +++ b/test/riscv/tests/rv64um-p-divu.elf diff --git a/test/riscv/tests/rv64um-p-divuw.dump b/test/riscv/tests/rv64um-p-divuw.dump new file mode 100644 index 00000000..576f2638 --- /dev/null +++ b/test/riscv/tests/rv64um-p-divuw.dump @@ -0,0 +1,197 @@ + +rv64um-p-divuw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 01400093 li ra,20 + 80000100: 00600113 li sp,6 + 80000104: 0220df3b divuw t5,ra,sp + 80000108: 00300e93 li t4,3 + 8000010c: 00200193 li gp,2 + 80000110: 0ddf1a63 bne t5,t4,800001e4 <fail> + +0000000080000114 <test_3>: + 80000114: 0010009b addiw ra,zero,1 + 80000118: 02009093 slli ra,ra,0x20 + 8000011c: fec08093 addi ra,ra,-20 + 80000120: 00600113 li sp,6 + 80000124: 0220df3b divuw t5,ra,sp + 80000128: 2aaabeb7 lui t4,0x2aaab + 8000012c: aa7e8e9b addiw t4,t4,-1369 + 80000130: 00300193 li gp,3 + 80000134: 0bdf1863 bne t5,t4,800001e4 <fail> + +0000000080000138 <test_4>: + 80000138: 01400093 li ra,20 + 8000013c: ffa00113 li sp,-6 + 80000140: 0220df3b divuw t5,ra,sp + 80000144: 00000e93 li t4,0 + 80000148: 00400193 li gp,4 + 8000014c: 09df1c63 bne t5,t4,800001e4 <fail> + +0000000080000150 <test_5>: + 80000150: fec00093 li ra,-20 + 80000154: ffa00113 li sp,-6 + 80000158: 0220df3b divuw t5,ra,sp + 8000015c: 00000e93 li t4,0 + 80000160: 00500193 li gp,5 + 80000164: 09df1063 bne t5,t4,800001e4 <fail> + +0000000080000168 <test_6>: + 80000168: 800000b7 lui ra,0x80000 + 8000016c: 00100113 li sp,1 + 80000170: 0220df3b divuw t5,ra,sp + 80000174: 80000eb7 lui t4,0x80000 + 80000178: 00600193 li gp,6 + 8000017c: 07df1463 bne t5,t4,800001e4 <fail> + +0000000080000180 <test_7>: + 80000180: 800000b7 lui ra,0x80000 + 80000184: fff00113 li sp,-1 + 80000188: 0220df3b divuw t5,ra,sp + 8000018c: 00000e93 li t4,0 + 80000190: 00700193 li gp,7 + 80000194: 05df1863 bne t5,t4,800001e4 <fail> + +0000000080000198 <test_8>: + 80000198: 800000b7 lui ra,0x80000 + 8000019c: 00000113 li sp,0 + 800001a0: 0220df3b divuw t5,ra,sp + 800001a4: fff00e93 li t4,-1 + 800001a8: 00800193 li gp,8 + 800001ac: 03df1c63 bne t5,t4,800001e4 <fail> + +00000000800001b0 <test_9>: + 800001b0: 00100093 li ra,1 + 800001b4: 00000113 li sp,0 + 800001b8: 0220df3b divuw t5,ra,sp + 800001bc: fff00e93 li t4,-1 + 800001c0: 00900193 li gp,9 + 800001c4: 03df1063 bne t5,t4,800001e4 <fail> + +00000000800001c8 <test_10>: + 800001c8: 00000093 li ra,0 + 800001cc: 00000113 li sp,0 + 800001d0: 0220df3b divuw t5,ra,sp + 800001d4: fff00e93 li t4,-1 + 800001d8: 00a00193 li gp,10 + 800001dc: 01df1463 bne t5,t4,800001e4 <fail> + 800001e0: 00301c63 bne zero,gp,800001f8 <pass> + +00000000800001e4 <fail>: + 800001e4: 0ff0000f fence + 800001e8: 00018063 beqz gp,800001e8 <fail+0x4> + 800001ec: 00119193 slli gp,gp,0x1 + 800001f0: 0011e193 ori gp,gp,1 + 800001f4: 00000073 ecall + +00000000800001f8 <pass>: + 800001f8: 0ff0000f fence + 800001fc: 00100193 li gp,1 + 80000200: 00000073 ecall + 80000204: c0001073 unimp + 80000208: 0000 unimp + 8000020a: 0000 unimp + 8000020c: 0000 unimp + 8000020e: 0000 unimp + 80000210: 0000 unimp + 80000212: 0000 unimp + 80000214: 0000 unimp + 80000216: 0000 unimp + 80000218: 0000 unimp + 8000021a: 0000 unimp + 8000021c: 0000 unimp + 8000021e: 0000 unimp + 80000220: 0000 unimp + 80000222: 0000 unimp + 80000224: 0000 unimp + 80000226: 0000 unimp + 80000228: 0000 unimp + 8000022a: 0000 unimp + 8000022c: 0000 unimp + 8000022e: 0000 unimp + 80000230: 0000 unimp + 80000232: 0000 unimp + 80000234: 0000 unimp + 80000236: 0000 unimp + 80000238: 0000 unimp + 8000023a: 0000 unimp + 8000023c: 0000 unimp + 8000023e: 0000 unimp + 80000240: 0000 unimp + 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-divuw.elf b/test/riscv/tests/rv64um-p-divuw.elf Binary files differnew file mode 100755 index 00000000..b0da149b --- /dev/null +++ b/test/riscv/tests/rv64um-p-divuw.elf diff --git a/test/riscv/tests/rv64um-p-divw.dump b/test/riscv/tests/rv64um-p-divw.dump new file mode 100644 index 00000000..2d331a94 --- /dev/null +++ b/test/riscv/tests/rv64um-p-divw.dump @@ -0,0 +1,168 @@ + +rv64um-p-divw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 01400093 li ra,20 + 80000100: 00600113 li sp,6 + 80000104: 0220cf3b divw t5,ra,sp + 80000108: 00300e93 li t4,3 + 8000010c: 00200193 li gp,2 + 80000110: 0ddf1463 bne t5,t4,800001d8 <fail> + +0000000080000114 <test_3>: + 80000114: fec00093 li ra,-20 + 80000118: 00600113 li sp,6 + 8000011c: 0220cf3b divw t5,ra,sp + 80000120: ffd00e93 li t4,-3 + 80000124: 00300193 li gp,3 + 80000128: 0bdf1863 bne t5,t4,800001d8 <fail> + +000000008000012c <test_4>: + 8000012c: 01400093 li ra,20 + 80000130: ffa00113 li sp,-6 + 80000134: 0220cf3b divw t5,ra,sp + 80000138: ffd00e93 li t4,-3 + 8000013c: 00400193 li gp,4 + 80000140: 09df1c63 bne t5,t4,800001d8 <fail> + +0000000080000144 <test_5>: + 80000144: fec00093 li ra,-20 + 80000148: ffa00113 li sp,-6 + 8000014c: 0220cf3b divw t5,ra,sp + 80000150: 00300e93 li t4,3 + 80000154: 00500193 li gp,5 + 80000158: 09df1063 bne t5,t4,800001d8 <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 00100113 li sp,1 + 80000164: 0220cf3b divw t5,ra,sp + 80000168: 80000eb7 lui t4,0x80000 + 8000016c: 00600193 li gp,6 + 80000170: 07df1463 bne t5,t4,800001d8 <fail> + +0000000080000174 <test_7>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: fff00113 li sp,-1 + 8000017c: 0220cf3b divw t5,ra,sp + 80000180: 80000eb7 lui t4,0x80000 + 80000184: 00700193 li gp,7 + 80000188: 05df1863 bne t5,t4,800001d8 <fail> + +000000008000018c <test_8>: + 8000018c: 800000b7 lui ra,0x80000 + 80000190: 00000113 li sp,0 + 80000194: 0220cf3b divw t5,ra,sp + 80000198: fff00e93 li t4,-1 + 8000019c: 00800193 li gp,8 + 800001a0: 03df1c63 bne t5,t4,800001d8 <fail> + +00000000800001a4 <test_9>: + 800001a4: 00100093 li ra,1 + 800001a8: 00000113 li sp,0 + 800001ac: 0220cf3b divw t5,ra,sp + 800001b0: fff00e93 li t4,-1 + 800001b4: 00900193 li gp,9 + 800001b8: 03df1063 bne t5,t4,800001d8 <fail> + +00000000800001bc <test_10>: + 800001bc: 00000093 li ra,0 + 800001c0: 00000113 li sp,0 + 800001c4: 0220cf3b divw t5,ra,sp + 800001c8: fff00e93 li t4,-1 + 800001cc: 00a00193 li gp,10 + 800001d0: 01df1463 bne t5,t4,800001d8 <fail> + 800001d4: 00301c63 bne zero,gp,800001ec <pass> + +00000000800001d8 <fail>: + 800001d8: 0ff0000f fence + 800001dc: 00018063 beqz gp,800001dc <fail+0x4> + 800001e0: 00119193 slli gp,gp,0x1 + 800001e4: 0011e193 ori gp,gp,1 + 800001e8: 00000073 ecall + +00000000800001ec <pass>: + 800001ec: 0ff0000f fence + 800001f0: 00100193 li gp,1 + 800001f4: 00000073 ecall + 800001f8: c0001073 unimp + 800001fc: 0000 unimp + 800001fe: 0000 unimp + 80000200: 0000 unimp + 80000202: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-divw.elf b/test/riscv/tests/rv64um-p-divw.elf Binary files differnew file mode 100755 index 00000000..eb2e0f58 --- /dev/null +++ b/test/riscv/tests/rv64um-p-divw.elf diff --git a/test/riscv/tests/rv64um-p-mul.dump b/test/riscv/tests/rv64um-p-mul.dump new file mode 100644 index 00000000..b546f6c9 --- /dev/null +++ b/test/riscv/tests/rv64um-p-mul.dump @@ -0,0 +1,474 @@ + +rv64um-p-mul: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_32> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_32>: + 800000fc: 000080b7 lui ra,0x8 + 80000100: e000809b addiw ra,ra,-512 + 80000104: 06db7137 lui sp,0x6db7 + 80000108: db71011b addiw sp,sp,-585 + 8000010c: 00c11113 slli sp,sp,0xc + 80000110: db710113 addi sp,sp,-585 # 6db6db7 <_start-0x79249249> + 80000114: 00c11113 slli sp,sp,0xc + 80000118: db710113 addi sp,sp,-585 + 8000011c: 00c11113 slli sp,sp,0xc + 80000120: db710113 addi sp,sp,-585 + 80000124: 02208f33 mul t5,ra,sp + 80000128: 00001eb7 lui t4,0x1 + 8000012c: 200e8e9b addiw t4,t4,512 + 80000130: 02000193 li gp,32 + 80000134: 49df1a63 bne t5,t4,800005c8 <fail> + +0000000080000138 <test_33>: + 80000138: 000080b7 lui ra,0x8 + 8000013c: fc00809b addiw ra,ra,-64 + 80000140: 06db7137 lui sp,0x6db7 + 80000144: db71011b addiw sp,sp,-585 + 80000148: 00c11113 slli sp,sp,0xc + 8000014c: db710113 addi sp,sp,-585 # 6db6db7 <_start-0x79249249> + 80000150: 00c11113 slli sp,sp,0xc + 80000154: db710113 addi sp,sp,-585 + 80000158: 00c11113 slli sp,sp,0xc + 8000015c: db710113 addi sp,sp,-585 + 80000160: 02208f33 mul t5,ra,sp + 80000164: 00001eb7 lui t4,0x1 + 80000168: 240e8e9b addiw t4,t4,576 + 8000016c: 02100193 li gp,33 + 80000170: 45df1c63 bne t5,t4,800005c8 <fail> + +0000000080000174 <test_2>: + 80000174: 00000093 li ra,0 + 80000178: 00000113 li sp,0 + 8000017c: 02208f33 mul t5,ra,sp + 80000180: 00000e93 li t4,0 + 80000184: 00200193 li gp,2 + 80000188: 45df1063 bne t5,t4,800005c8 <fail> + +000000008000018c <test_3>: + 8000018c: 00100093 li ra,1 + 80000190: 00100113 li sp,1 + 80000194: 02208f33 mul t5,ra,sp + 80000198: 00100e93 li t4,1 + 8000019c: 00300193 li gp,3 + 800001a0: 43df1463 bne t5,t4,800005c8 <fail> + +00000000800001a4 <test_4>: + 800001a4: 00300093 li ra,3 + 800001a8: 00700113 li sp,7 + 800001ac: 02208f33 mul t5,ra,sp + 800001b0: 01500e93 li t4,21 + 800001b4: 00400193 li gp,4 + 800001b8: 41df1863 bne t5,t4,800005c8 <fail> + +00000000800001bc <test_5>: + 800001bc: 00000093 li ra,0 + 800001c0: ffff8137 lui sp,0xffff8 + 800001c4: 02208f33 mul t5,ra,sp + 800001c8: 00000e93 li t4,0 + 800001cc: 00500193 li gp,5 + 800001d0: 3fdf1c63 bne t5,t4,800005c8 <fail> + +00000000800001d4 <test_6>: + 800001d4: 800000b7 lui ra,0x80000 + 800001d8: 00000113 li sp,0 + 800001dc: 02208f33 mul t5,ra,sp + 800001e0: 00000e93 li t4,0 + 800001e4: 00600193 li gp,6 + 800001e8: 3fdf1063 bne t5,t4,800005c8 <fail> + +00000000800001ec <test_7>: + 800001ec: 800000b7 lui ra,0x80000 + 800001f0: ffff8137 lui sp,0xffff8 + 800001f4: 02208f33 mul t5,ra,sp + 800001f8: 00100e9b addiw t4,zero,1 + 800001fc: 02ee9e93 slli t4,t4,0x2e + 80000200: 00700193 li gp,7 + 80000204: 3ddf1263 bne t5,t4,800005c8 <fail> + +0000000080000208 <test_30>: + 80000208: faaab0b7 lui ra,0xfaaab + 8000020c: aab0809b addiw ra,ra,-1365 + 80000210: 00c09093 slli ra,ra,0xc + 80000214: aab08093 addi ra,ra,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa8aab> + 80000218: 00c09093 slli ra,ra,0xc + 8000021c: aab08093 addi ra,ra,-1365 + 80000220: 00c09093 slli ra,ra,0xc + 80000224: aab08093 addi ra,ra,-1365 + 80000228: 00030137 lui sp,0x30 + 8000022c: e7d1011b addiw sp,sp,-387 + 80000230: 02208f33 mul t5,ra,sp + 80000234: 00010eb7 lui t4,0x10 + 80000238: f7fe8e9b addiw t4,t4,-129 + 8000023c: 01e00193 li gp,30 + 80000240: 39df1463 bne t5,t4,800005c8 <fail> + +0000000080000244 <test_31>: + 80000244: 000300b7 lui ra,0x30 + 80000248: e7d0809b addiw ra,ra,-387 + 8000024c: faaab137 lui sp,0xfaaab + 80000250: aab1011b addiw sp,sp,-1365 + 80000254: 00c11113 slli sp,sp,0xc + 80000258: aab10113 addi sp,sp,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa8aab> + 8000025c: 00c11113 slli sp,sp,0xc + 80000260: aab10113 addi sp,sp,-1365 + 80000264: 00c11113 slli sp,sp,0xc + 80000268: aab10113 addi sp,sp,-1365 + 8000026c: 02208f33 mul t5,ra,sp + 80000270: 00010eb7 lui t4,0x10 + 80000274: f7fe8e9b addiw t4,t4,-129 + 80000278: 01f00193 li gp,31 + 8000027c: 35df1663 bne t5,t4,800005c8 <fail> + +0000000080000280 <test_8>: + 80000280: 00d00093 li ra,13 + 80000284: 00b00113 li sp,11 + 80000288: 022080b3 mul ra,ra,sp + 8000028c: 08f00e93 li t4,143 + 80000290: 00800193 li gp,8 + 80000294: 33d09a63 bne ra,t4,800005c8 <fail> + +0000000080000298 <test_9>: + 80000298: 00e00093 li ra,14 + 8000029c: 00b00113 li sp,11 + 800002a0: 02208133 mul sp,ra,sp + 800002a4: 09a00e93 li t4,154 + 800002a8: 00900193 li gp,9 + 800002ac: 31d11e63 bne sp,t4,800005c8 <fail> + +00000000800002b0 <test_10>: + 800002b0: 00d00093 li ra,13 + 800002b4: 021080b3 mul ra,ra,ra + 800002b8: 0a900e93 li t4,169 + 800002bc: 00a00193 li gp,10 + 800002c0: 31d09463 bne ra,t4,800005c8 <fail> + +00000000800002c4 <test_11>: + 800002c4: 00000213 li tp,0 + 800002c8: 00d00093 li ra,13 + 800002cc: 00b00113 li sp,11 + 800002d0: 02208f33 mul t5,ra,sp + 800002d4: 000f0313 mv t1,t5 + 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002dc: 00200293 li t0,2 + 800002e0: fe5214e3 bne tp,t0,800002c8 <test_11+0x4> + 800002e4: 08f00e93 li t4,143 + 800002e8: 00b00193 li gp,11 + 800002ec: 2dd31e63 bne t1,t4,800005c8 <fail> + +00000000800002f0 <test_12>: + 800002f0: 00000213 li tp,0 + 800002f4: 00e00093 li ra,14 + 800002f8: 00b00113 li sp,11 + 800002fc: 02208f33 mul t5,ra,sp + 80000300: 00000013 nop + 80000304: 000f0313 mv t1,t5 + 80000308: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000030c: 00200293 li t0,2 + 80000310: fe5212e3 bne tp,t0,800002f4 <test_12+0x4> + 80000314: 09a00e93 li t4,154 + 80000318: 00c00193 li gp,12 + 8000031c: 2bd31663 bne t1,t4,800005c8 <fail> + +0000000080000320 <test_13>: + 80000320: 00000213 li tp,0 + 80000324: 00f00093 li ra,15 + 80000328: 00b00113 li sp,11 + 8000032c: 02208f33 mul t5,ra,sp + 80000330: 00000013 nop + 80000334: 00000013 nop + 80000338: 000f0313 mv t1,t5 + 8000033c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000340: 00200293 li t0,2 + 80000344: fe5210e3 bne tp,t0,80000324 <test_13+0x4> + 80000348: 0a500e93 li t4,165 + 8000034c: 00d00193 li gp,13 + 80000350: 27d31c63 bne t1,t4,800005c8 <fail> + +0000000080000354 <test_14>: + 80000354: 00000213 li tp,0 + 80000358: 00d00093 li ra,13 + 8000035c: 00b00113 li sp,11 + 80000360: 02208f33 mul t5,ra,sp + 80000364: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000368: 00200293 li t0,2 + 8000036c: fe5216e3 bne tp,t0,80000358 <test_14+0x4> + 80000370: 08f00e93 li t4,143 + 80000374: 00e00193 li gp,14 + 80000378: 25df1863 bne t5,t4,800005c8 <fail> + +000000008000037c <test_15>: + 8000037c: 00000213 li tp,0 + 80000380: 00e00093 li ra,14 + 80000384: 00b00113 li sp,11 + 80000388: 00000013 nop + 8000038c: 02208f33 mul t5,ra,sp + 80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000394: 00200293 li t0,2 + 80000398: fe5214e3 bne tp,t0,80000380 <test_15+0x4> + 8000039c: 09a00e93 li t4,154 + 800003a0: 00f00193 li gp,15 + 800003a4: 23df1263 bne t5,t4,800005c8 <fail> + +00000000800003a8 <test_16>: + 800003a8: 00000213 li tp,0 + 800003ac: 00f00093 li ra,15 + 800003b0: 00b00113 li sp,11 + 800003b4: 00000013 nop + 800003b8: 00000013 nop + 800003bc: 02208f33 mul t5,ra,sp + 800003c0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003c4: 00200293 li t0,2 + 800003c8: fe5212e3 bne tp,t0,800003ac <test_16+0x4> + 800003cc: 0a500e93 li t4,165 + 800003d0: 01000193 li gp,16 + 800003d4: 1fdf1a63 bne t5,t4,800005c8 <fail> + +00000000800003d8 <test_17>: + 800003d8: 00000213 li tp,0 + 800003dc: 00d00093 li ra,13 + 800003e0: 00000013 nop + 800003e4: 00b00113 li sp,11 + 800003e8: 02208f33 mul t5,ra,sp + 800003ec: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003f0: 00200293 li t0,2 + 800003f4: fe5214e3 bne tp,t0,800003dc <test_17+0x4> + 800003f8: 08f00e93 li t4,143 + 800003fc: 01100193 li gp,17 + 80000400: 1ddf1463 bne t5,t4,800005c8 <fail> + +0000000080000404 <test_18>: + 80000404: 00000213 li tp,0 + 80000408: 00e00093 li ra,14 + 8000040c: 00000013 nop + 80000410: 00b00113 li sp,11 + 80000414: 00000013 nop + 80000418: 02208f33 mul t5,ra,sp + 8000041c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000420: 00200293 li t0,2 + 80000424: fe5212e3 bne tp,t0,80000408 <test_18+0x4> + 80000428: 09a00e93 li t4,154 + 8000042c: 01200193 li gp,18 + 80000430: 19df1c63 bne t5,t4,800005c8 <fail> + +0000000080000434 <test_19>: + 80000434: 00000213 li tp,0 + 80000438: 00f00093 li ra,15 + 8000043c: 00000013 nop + 80000440: 00000013 nop + 80000444: 00b00113 li sp,11 + 80000448: 02208f33 mul t5,ra,sp + 8000044c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000450: 00200293 li t0,2 + 80000454: fe5212e3 bne tp,t0,80000438 <test_19+0x4> + 80000458: 0a500e93 li t4,165 + 8000045c: 01300193 li gp,19 + 80000460: 17df1463 bne t5,t4,800005c8 <fail> + +0000000080000464 <test_20>: + 80000464: 00000213 li tp,0 + 80000468: 00b00113 li sp,11 + 8000046c: 00d00093 li ra,13 + 80000470: 02208f33 mul t5,ra,sp + 80000474: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000478: 00200293 li t0,2 + 8000047c: fe5216e3 bne tp,t0,80000468 <test_20+0x4> + 80000480: 08f00e93 li t4,143 + 80000484: 01400193 li gp,20 + 80000488: 15df1063 bne t5,t4,800005c8 <fail> + +000000008000048c <test_21>: + 8000048c: 00000213 li tp,0 + 80000490: 00b00113 li sp,11 + 80000494: 00e00093 li ra,14 + 80000498: 00000013 nop + 8000049c: 02208f33 mul t5,ra,sp + 800004a0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004a4: 00200293 li t0,2 + 800004a8: fe5214e3 bne tp,t0,80000490 <test_21+0x4> + 800004ac: 09a00e93 li t4,154 + 800004b0: 01500193 li gp,21 + 800004b4: 11df1a63 bne t5,t4,800005c8 <fail> + +00000000800004b8 <test_22>: + 800004b8: 00000213 li tp,0 + 800004bc: 00b00113 li sp,11 + 800004c0: 00f00093 li ra,15 + 800004c4: 00000013 nop + 800004c8: 00000013 nop + 800004cc: 02208f33 mul t5,ra,sp + 800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004d4: 00200293 li t0,2 + 800004d8: fe5212e3 bne tp,t0,800004bc <test_22+0x4> + 800004dc: 0a500e93 li t4,165 + 800004e0: 01600193 li gp,22 + 800004e4: 0fdf1263 bne t5,t4,800005c8 <fail> + +00000000800004e8 <test_23>: + 800004e8: 00000213 li tp,0 + 800004ec: 00b00113 li sp,11 + 800004f0: 00000013 nop + 800004f4: 00d00093 li ra,13 + 800004f8: 02208f33 mul t5,ra,sp + 800004fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000500: 00200293 li t0,2 + 80000504: fe5214e3 bne tp,t0,800004ec <test_23+0x4> + 80000508: 08f00e93 li t4,143 + 8000050c: 01700193 li gp,23 + 80000510: 0bdf1c63 bne t5,t4,800005c8 <fail> + +0000000080000514 <test_24>: + 80000514: 00000213 li tp,0 + 80000518: 00b00113 li sp,11 + 8000051c: 00000013 nop + 80000520: 00e00093 li ra,14 + 80000524: 00000013 nop + 80000528: 02208f33 mul t5,ra,sp + 8000052c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000530: 00200293 li t0,2 + 80000534: fe5212e3 bne tp,t0,80000518 <test_24+0x4> + 80000538: 09a00e93 li t4,154 + 8000053c: 01800193 li gp,24 + 80000540: 09df1463 bne t5,t4,800005c8 <fail> + +0000000080000544 <test_25>: + 80000544: 00000213 li tp,0 + 80000548: 00b00113 li sp,11 + 8000054c: 00000013 nop + 80000550: 00000013 nop + 80000554: 00f00093 li ra,15 + 80000558: 02208f33 mul t5,ra,sp + 8000055c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000560: 00200293 li t0,2 + 80000564: fe5212e3 bne tp,t0,80000548 <test_25+0x4> + 80000568: 0a500e93 li t4,165 + 8000056c: 01900193 li gp,25 + 80000570: 05df1c63 bne t5,t4,800005c8 <fail> + +0000000080000574 <test_26>: + 80000574: 01f00093 li ra,31 + 80000578: 02100133 mul sp,zero,ra + 8000057c: 00000e93 li t4,0 + 80000580: 01a00193 li gp,26 + 80000584: 05d11263 bne sp,t4,800005c8 <fail> + +0000000080000588 <test_27>: + 80000588: 02000093 li ra,32 + 8000058c: 02008133 mul sp,ra,zero + 80000590: 00000e93 li t4,0 + 80000594: 01b00193 li gp,27 + 80000598: 03d11863 bne sp,t4,800005c8 <fail> + +000000008000059c <test_28>: + 8000059c: 020000b3 mul ra,zero,zero + 800005a0: 00000e93 li t4,0 + 800005a4: 01c00193 li gp,28 + 800005a8: 03d09063 bne ra,t4,800005c8 <fail> + +00000000800005ac <test_29>: + 800005ac: 02100093 li ra,33 + 800005b0: 02200113 li sp,34 + 800005b4: 02208033 mul zero,ra,sp + 800005b8: 00000e93 li t4,0 + 800005bc: 01d00193 li gp,29 + 800005c0: 01d01463 bne zero,t4,800005c8 <fail> + 800005c4: 00301c63 bne zero,gp,800005dc <pass> + +00000000800005c8 <fail>: + 800005c8: 0ff0000f fence + 800005cc: 00018063 beqz gp,800005cc <fail+0x4> + 800005d0: 00119193 slli gp,gp,0x1 + 800005d4: 0011e193 ori gp,gp,1 + 800005d8: 00000073 ecall + +00000000800005dc <pass>: + 800005dc: 0ff0000f fence + 800005e0: 00100193 li gp,1 + 800005e4: 00000073 ecall + 800005e8: c0001073 unimp + 800005ec: 0000 unimp + 800005ee: 0000 unimp + 800005f0: 0000 unimp + 800005f2: 0000 unimp + 800005f4: 0000 unimp + 800005f6: 0000 unimp + 800005f8: 0000 unimp + 800005fa: 0000 unimp + 800005fc: 0000 unimp + 800005fe: 0000 unimp + 80000600: 0000 unimp + 80000602: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-mul.elf b/test/riscv/tests/rv64um-p-mul.elf Binary files differnew file mode 100755 index 00000000..7107505a --- /dev/null +++ b/test/riscv/tests/rv64um-p-mul.elf diff --git a/test/riscv/tests/rv64um-p-mulh.dump b/test/riscv/tests/rv64um-p-mulh.dump new file mode 100644 index 00000000..59475e6d --- /dev/null +++ b/test/riscv/tests/rv64um-p-mulh.dump @@ -0,0 +1,456 @@ + +rv64um-p-mulh: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 00000113 li sp,0 + 80000104: 02209f33 mulh t5,ra,sp + 80000108: 00000e93 li t4,0 + 8000010c: 00200193 li gp,2 + 80000110: 47df1063 bne t5,t4,80000570 <fail> + +0000000080000114 <test_3>: + 80000114: 00100093 li ra,1 + 80000118: 00100113 li sp,1 + 8000011c: 02209f33 mulh t5,ra,sp + 80000120: 00000e93 li t4,0 + 80000124: 00300193 li gp,3 + 80000128: 45df1463 bne t5,t4,80000570 <fail> + +000000008000012c <test_4>: + 8000012c: 00300093 li ra,3 + 80000130: 00700113 li sp,7 + 80000134: 02209f33 mulh t5,ra,sp + 80000138: 00000e93 li t4,0 + 8000013c: 00400193 li gp,4 + 80000140: 43df1863 bne t5,t4,80000570 <fail> + +0000000080000144 <test_5>: + 80000144: 00000093 li ra,0 + 80000148: ffff8137 lui sp,0xffff8 + 8000014c: 02209f33 mulh t5,ra,sp + 80000150: 00000e93 li t4,0 + 80000154: 00500193 li gp,5 + 80000158: 41df1c63 bne t5,t4,80000570 <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 00000113 li sp,0 + 80000164: 02209f33 mulh t5,ra,sp + 80000168: 00000e93 li t4,0 + 8000016c: 00600193 li gp,6 + 80000170: 41df1063 bne t5,t4,80000570 <fail> + +0000000080000174 <test_7>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: ffff8137 lui sp,0xffff8 + 8000017c: 02209f33 mulh t5,ra,sp + 80000180: 00000e93 li t4,0 + 80000184: 00700193 li gp,7 + 80000188: 3fdf1463 bne t5,t4,80000570 <fail> + +000000008000018c <test_8>: + 8000018c: 00d0009b addiw ra,zero,13 + 80000190: 02009093 slli ra,ra,0x20 + 80000194: 00b0011b addiw sp,zero,11 + 80000198: 02011113 slli sp,sp,0x20 + 8000019c: 022090b3 mulh ra,ra,sp + 800001a0: 08f00e93 li t4,143 + 800001a4: 00800193 li gp,8 + 800001a8: 3dd09463 bne ra,t4,80000570 <fail> + +00000000800001ac <test_9>: + 800001ac: 0070009b addiw ra,zero,7 + 800001b0: 02109093 slli ra,ra,0x21 + 800001b4: 00b0011b addiw sp,zero,11 + 800001b8: 02011113 slli sp,sp,0x20 + 800001bc: 02209133 mulh sp,ra,sp + 800001c0: 09a00e93 li t4,154 + 800001c4: 00900193 li gp,9 + 800001c8: 3bd11463 bne sp,t4,80000570 <fail> + +00000000800001cc <test_10>: + 800001cc: 00d0009b addiw ra,zero,13 + 800001d0: 02009093 slli ra,ra,0x20 + 800001d4: 021090b3 mulh ra,ra,ra + 800001d8: 0a900e93 li t4,169 + 800001dc: 00a00193 li gp,10 + 800001e0: 39d09863 bne ra,t4,80000570 <fail> + +00000000800001e4 <test_11>: + 800001e4: 00000213 li tp,0 + 800001e8: 00d0009b addiw ra,zero,13 + 800001ec: 02009093 slli ra,ra,0x20 + 800001f0: 00b0011b addiw sp,zero,11 + 800001f4: 02011113 slli sp,sp,0x20 + 800001f8: 02209f33 mulh t5,ra,sp + 800001fc: 000f0313 mv t1,t5 + 80000200: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000204: 00200293 li t0,2 + 80000208: fe5210e3 bne tp,t0,800001e8 <test_11+0x4> + 8000020c: 08f00e93 li t4,143 + 80000210: 00b00193 li gp,11 + 80000214: 35d31e63 bne t1,t4,80000570 <fail> + +0000000080000218 <test_12>: + 80000218: 00000213 li tp,0 + 8000021c: 0070009b addiw ra,zero,7 + 80000220: 02109093 slli ra,ra,0x21 + 80000224: 00b0011b addiw sp,zero,11 + 80000228: 02011113 slli sp,sp,0x20 + 8000022c: 02209f33 mulh t5,ra,sp + 80000230: 00000013 nop + 80000234: 000f0313 mv t1,t5 + 80000238: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000023c: 00200293 li t0,2 + 80000240: fc521ee3 bne tp,t0,8000021c <test_12+0x4> + 80000244: 09a00e93 li t4,154 + 80000248: 00c00193 li gp,12 + 8000024c: 33d31263 bne t1,t4,80000570 <fail> + +0000000080000250 <test_13>: + 80000250: 00000213 li tp,0 + 80000254: 00f0009b addiw ra,zero,15 + 80000258: 02009093 slli ra,ra,0x20 + 8000025c: 00b0011b addiw sp,zero,11 + 80000260: 02011113 slli sp,sp,0x20 + 80000264: 02209f33 mulh t5,ra,sp + 80000268: 00000013 nop + 8000026c: 00000013 nop + 80000270: 000f0313 mv t1,t5 + 80000274: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000278: 00200293 li t0,2 + 8000027c: fc521ce3 bne tp,t0,80000254 <test_13+0x4> + 80000280: 0a500e93 li t4,165 + 80000284: 00d00193 li gp,13 + 80000288: 2fd31463 bne t1,t4,80000570 <fail> + +000000008000028c <test_14>: + 8000028c: 00000213 li tp,0 + 80000290: 00d0009b addiw ra,zero,13 + 80000294: 02009093 slli ra,ra,0x20 + 80000298: 00b0011b addiw sp,zero,11 + 8000029c: 02011113 slli sp,sp,0x20 + 800002a0: 02209f33 mulh t5,ra,sp + 800002a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a8: 00200293 li t0,2 + 800002ac: fe5212e3 bne tp,t0,80000290 <test_14+0x4> + 800002b0: 08f00e93 li t4,143 + 800002b4: 00e00193 li gp,14 + 800002b8: 2bdf1c63 bne t5,t4,80000570 <fail> + +00000000800002bc <test_15>: + 800002bc: 00000213 li tp,0 + 800002c0: 0070009b addiw ra,zero,7 + 800002c4: 02109093 slli ra,ra,0x21 + 800002c8: 00b0011b addiw sp,zero,11 + 800002cc: 02011113 slli sp,sp,0x20 + 800002d0: 00000013 nop + 800002d4: 02209f33 mulh t5,ra,sp + 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002dc: 00200293 li t0,2 + 800002e0: fe5210e3 bne tp,t0,800002c0 <test_15+0x4> + 800002e4: 09a00e93 li t4,154 + 800002e8: 00f00193 li gp,15 + 800002ec: 29df1263 bne t5,t4,80000570 <fail> + +00000000800002f0 <test_16>: + 800002f0: 00000213 li tp,0 + 800002f4: 00f0009b addiw ra,zero,15 + 800002f8: 02009093 slli ra,ra,0x20 + 800002fc: 00b0011b addiw sp,zero,11 + 80000300: 02011113 slli sp,sp,0x20 + 80000304: 00000013 nop + 80000308: 00000013 nop + 8000030c: 02209f33 mulh t5,ra,sp + 80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000314: 00200293 li t0,2 + 80000318: fc521ee3 bne tp,t0,800002f4 <test_16+0x4> + 8000031c: 0a500e93 li t4,165 + 80000320: 01000193 li gp,16 + 80000324: 25df1663 bne t5,t4,80000570 <fail> + +0000000080000328 <test_17>: + 80000328: 00000213 li tp,0 + 8000032c: 00d0009b addiw ra,zero,13 + 80000330: 02009093 slli ra,ra,0x20 + 80000334: 00000013 nop + 80000338: 00b0011b addiw sp,zero,11 + 8000033c: 02011113 slli sp,sp,0x20 + 80000340: 02209f33 mulh t5,ra,sp + 80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000348: 00200293 li t0,2 + 8000034c: fe5210e3 bne tp,t0,8000032c <test_17+0x4> + 80000350: 08f00e93 li t4,143 + 80000354: 01100193 li gp,17 + 80000358: 21df1c63 bne t5,t4,80000570 <fail> + +000000008000035c <test_18>: + 8000035c: 00000213 li tp,0 + 80000360: 0070009b addiw ra,zero,7 + 80000364: 02109093 slli ra,ra,0x21 + 80000368: 00000013 nop + 8000036c: 00b0011b addiw sp,zero,11 + 80000370: 02011113 slli sp,sp,0x20 + 80000374: 00000013 nop + 80000378: 02209f33 mulh t5,ra,sp + 8000037c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000380: 00200293 li t0,2 + 80000384: fc521ee3 bne tp,t0,80000360 <test_18+0x4> + 80000388: 09a00e93 li t4,154 + 8000038c: 01200193 li gp,18 + 80000390: 1fdf1063 bne t5,t4,80000570 <fail> + +0000000080000394 <test_19>: + 80000394: 00000213 li tp,0 + 80000398: 00f0009b addiw ra,zero,15 + 8000039c: 02009093 slli ra,ra,0x20 + 800003a0: 00000013 nop + 800003a4: 00000013 nop + 800003a8: 00b0011b addiw sp,zero,11 + 800003ac: 02011113 slli sp,sp,0x20 + 800003b0: 02209f33 mulh t5,ra,sp + 800003b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003b8: 00200293 li t0,2 + 800003bc: fc521ee3 bne tp,t0,80000398 <test_19+0x4> + 800003c0: 0a500e93 li t4,165 + 800003c4: 01300193 li gp,19 + 800003c8: 1bdf1463 bne t5,t4,80000570 <fail> + +00000000800003cc <test_20>: + 800003cc: 00000213 li tp,0 + 800003d0: 00b0011b addiw sp,zero,11 + 800003d4: 02011113 slli sp,sp,0x20 + 800003d8: 00d0009b addiw ra,zero,13 + 800003dc: 02009093 slli ra,ra,0x20 + 800003e0: 02209f33 mulh t5,ra,sp + 800003e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003e8: 00200293 li t0,2 + 800003ec: fe5212e3 bne tp,t0,800003d0 <test_20+0x4> + 800003f0: 08f00e93 li t4,143 + 800003f4: 01400193 li gp,20 + 800003f8: 17df1c63 bne t5,t4,80000570 <fail> + +00000000800003fc <test_21>: + 800003fc: 00000213 li tp,0 + 80000400: 00b0011b addiw sp,zero,11 + 80000404: 02011113 slli sp,sp,0x20 + 80000408: 0070009b addiw ra,zero,7 + 8000040c: 02109093 slli ra,ra,0x21 + 80000410: 00000013 nop + 80000414: 02209f33 mulh t5,ra,sp + 80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000041c: 00200293 li t0,2 + 80000420: fe5210e3 bne tp,t0,80000400 <test_21+0x4> + 80000424: 09a00e93 li t4,154 + 80000428: 01500193 li gp,21 + 8000042c: 15df1263 bne t5,t4,80000570 <fail> + +0000000080000430 <test_22>: + 80000430: 00000213 li tp,0 + 80000434: 00b0011b addiw sp,zero,11 + 80000438: 02011113 slli sp,sp,0x20 + 8000043c: 00f0009b addiw ra,zero,15 + 80000440: 02009093 slli ra,ra,0x20 + 80000444: 00000013 nop + 80000448: 00000013 nop + 8000044c: 02209f33 mulh t5,ra,sp + 80000450: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000454: 00200293 li t0,2 + 80000458: fc521ee3 bne tp,t0,80000434 <test_22+0x4> + 8000045c: 0a500e93 li t4,165 + 80000460: 01600193 li gp,22 + 80000464: 11df1663 bne t5,t4,80000570 <fail> + +0000000080000468 <test_23>: + 80000468: 00000213 li tp,0 + 8000046c: 00b0011b addiw sp,zero,11 + 80000470: 02011113 slli sp,sp,0x20 + 80000474: 00000013 nop + 80000478: 00d0009b addiw ra,zero,13 + 8000047c: 02009093 slli ra,ra,0x20 + 80000480: 02209f33 mulh t5,ra,sp + 80000484: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000488: 00200293 li t0,2 + 8000048c: fe5210e3 bne tp,t0,8000046c <test_23+0x4> + 80000490: 08f00e93 li t4,143 + 80000494: 01700193 li gp,23 + 80000498: 0ddf1c63 bne t5,t4,80000570 <fail> + +000000008000049c <test_24>: + 8000049c: 00000213 li tp,0 + 800004a0: 00b0011b addiw sp,zero,11 + 800004a4: 02011113 slli sp,sp,0x20 + 800004a8: 00000013 nop + 800004ac: 0070009b addiw ra,zero,7 + 800004b0: 02109093 slli ra,ra,0x21 + 800004b4: 00000013 nop + 800004b8: 02209f33 mulh t5,ra,sp + 800004bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004c0: 00200293 li t0,2 + 800004c4: fc521ee3 bne tp,t0,800004a0 <test_24+0x4> + 800004c8: 09a00e93 li t4,154 + 800004cc: 01800193 li gp,24 + 800004d0: 0bdf1063 bne t5,t4,80000570 <fail> + +00000000800004d4 <test_25>: + 800004d4: 00000213 li tp,0 + 800004d8: 00b0011b addiw sp,zero,11 + 800004dc: 02011113 slli sp,sp,0x20 + 800004e0: 00000013 nop + 800004e4: 00000013 nop + 800004e8: 00f0009b addiw ra,zero,15 + 800004ec: 02009093 slli ra,ra,0x20 + 800004f0: 02209f33 mulh t5,ra,sp + 800004f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004f8: 00200293 li t0,2 + 800004fc: fc521ee3 bne tp,t0,800004d8 <test_25+0x4> + 80000500: 0a500e93 li t4,165 + 80000504: 01900193 li gp,25 + 80000508: 07df1463 bne t5,t4,80000570 <fail> + +000000008000050c <test_26>: + 8000050c: 01f0009b addiw ra,zero,31 + 80000510: 02009093 slli ra,ra,0x20 + 80000514: 02101133 mulh sp,zero,ra + 80000518: 00000e93 li t4,0 + 8000051c: 01a00193 li gp,26 + 80000520: 05d11863 bne sp,t4,80000570 <fail> + +0000000080000524 <test_27>: + 80000524: 0010009b addiw ra,zero,1 + 80000528: 02509093 slli ra,ra,0x25 + 8000052c: 02009133 mulh sp,ra,zero + 80000530: 00000e93 li t4,0 + 80000534: 01b00193 li gp,27 + 80000538: 03d11c63 bne sp,t4,80000570 <fail> + +000000008000053c <test_28>: + 8000053c: 020010b3 mulh ra,zero,zero + 80000540: 00000e93 li t4,0 + 80000544: 01c00193 li gp,28 + 80000548: 03d09463 bne ra,t4,80000570 <fail> + +000000008000054c <test_29>: + 8000054c: 0210009b addiw ra,zero,33 + 80000550: 02009093 slli ra,ra,0x20 + 80000554: 0110011b addiw sp,zero,17 + 80000558: 02111113 slli sp,sp,0x21 + 8000055c: 02209033 mulh zero,ra,sp + 80000560: 00000e93 li t4,0 + 80000564: 01d00193 li gp,29 + 80000568: 01d01463 bne zero,t4,80000570 <fail> + 8000056c: 00301c63 bne zero,gp,80000584 <pass> + +0000000080000570 <fail>: + 80000570: 0ff0000f fence + 80000574: 00018063 beqz gp,80000574 <fail+0x4> + 80000578: 00119193 slli gp,gp,0x1 + 8000057c: 0011e193 ori gp,gp,1 + 80000580: 00000073 ecall + +0000000080000584 <pass>: + 80000584: 0ff0000f fence + 80000588: 00100193 li gp,1 + 8000058c: 00000073 ecall + 80000590: c0001073 unimp + 80000594: 0000 unimp + 80000596: 0000 unimp + 80000598: 0000 unimp + 8000059a: 0000 unimp + 8000059c: 0000 unimp + 8000059e: 0000 unimp + 800005a0: 0000 unimp + 800005a2: 0000 unimp + 800005a4: 0000 unimp + 800005a6: 0000 unimp + 800005a8: 0000 unimp + 800005aa: 0000 unimp + 800005ac: 0000 unimp + 800005ae: 0000 unimp + 800005b0: 0000 unimp + 800005b2: 0000 unimp + 800005b4: 0000 unimp + 800005b6: 0000 unimp + 800005b8: 0000 unimp + 800005ba: 0000 unimp + 800005bc: 0000 unimp + 800005be: 0000 unimp + 800005c0: 0000 unimp + 800005c2: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-mulh.elf b/test/riscv/tests/rv64um-p-mulh.elf Binary files differnew file mode 100755 index 00000000..f44264b4 --- /dev/null +++ b/test/riscv/tests/rv64um-p-mulh.elf diff --git a/test/riscv/tests/rv64um-p-mulhsu.dump b/test/riscv/tests/rv64um-p-mulhsu.dump new file mode 100644 index 00000000..56d5b6da --- /dev/null +++ b/test/riscv/tests/rv64um-p-mulhsu.dump @@ -0,0 +1,456 @@ + +rv64um-p-mulhsu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 00000113 li sp,0 + 80000104: 0220af33 mulhsu t5,ra,sp + 80000108: 00000e93 li t4,0 + 8000010c: 00200193 li gp,2 + 80000110: 47df1063 bne t5,t4,80000570 <fail> + +0000000080000114 <test_3>: + 80000114: 00100093 li ra,1 + 80000118: 00100113 li sp,1 + 8000011c: 0220af33 mulhsu t5,ra,sp + 80000120: 00000e93 li t4,0 + 80000124: 00300193 li gp,3 + 80000128: 45df1463 bne t5,t4,80000570 <fail> + +000000008000012c <test_4>: + 8000012c: 00300093 li ra,3 + 80000130: 00700113 li sp,7 + 80000134: 0220af33 mulhsu t5,ra,sp + 80000138: 00000e93 li t4,0 + 8000013c: 00400193 li gp,4 + 80000140: 43df1863 bne t5,t4,80000570 <fail> + +0000000080000144 <test_5>: + 80000144: 00000093 li ra,0 + 80000148: ffff8137 lui sp,0xffff8 + 8000014c: 0220af33 mulhsu t5,ra,sp + 80000150: 00000e93 li t4,0 + 80000154: 00500193 li gp,5 + 80000158: 41df1c63 bne t5,t4,80000570 <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 00000113 li sp,0 + 80000164: 0220af33 mulhsu t5,ra,sp + 80000168: 00000e93 li t4,0 + 8000016c: 00600193 li gp,6 + 80000170: 41df1063 bne t5,t4,80000570 <fail> + +0000000080000174 <test_7>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: ffff8137 lui sp,0xffff8 + 8000017c: 0220af33 mulhsu t5,ra,sp + 80000180: 80000eb7 lui t4,0x80000 + 80000184: 00700193 li gp,7 + 80000188: 3fdf1463 bne t5,t4,80000570 <fail> + +000000008000018c <test_8>: + 8000018c: 00d0009b addiw ra,zero,13 + 80000190: 02009093 slli ra,ra,0x20 + 80000194: 00b0011b addiw sp,zero,11 + 80000198: 02011113 slli sp,sp,0x20 + 8000019c: 0220a0b3 mulhsu ra,ra,sp + 800001a0: 08f00e93 li t4,143 + 800001a4: 00800193 li gp,8 + 800001a8: 3dd09463 bne ra,t4,80000570 <fail> + +00000000800001ac <test_9>: + 800001ac: 0070009b addiw ra,zero,7 + 800001b0: 02109093 slli ra,ra,0x21 + 800001b4: 00b0011b addiw sp,zero,11 + 800001b8: 02011113 slli sp,sp,0x20 + 800001bc: 0220a133 mulhsu sp,ra,sp + 800001c0: 09a00e93 li t4,154 + 800001c4: 00900193 li gp,9 + 800001c8: 3bd11463 bne sp,t4,80000570 <fail> + +00000000800001cc <test_10>: + 800001cc: 00d0009b addiw ra,zero,13 + 800001d0: 02009093 slli ra,ra,0x20 + 800001d4: 0210a0b3 mulhsu ra,ra,ra + 800001d8: 0a900e93 li t4,169 + 800001dc: 00a00193 li gp,10 + 800001e0: 39d09863 bne ra,t4,80000570 <fail> + +00000000800001e4 <test_11>: + 800001e4: 00000213 li tp,0 + 800001e8: 00d0009b addiw ra,zero,13 + 800001ec: 02009093 slli ra,ra,0x20 + 800001f0: 00b0011b addiw sp,zero,11 + 800001f4: 02011113 slli sp,sp,0x20 + 800001f8: 0220af33 mulhsu t5,ra,sp + 800001fc: 000f0313 mv t1,t5 + 80000200: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000204: 00200293 li t0,2 + 80000208: fe5210e3 bne tp,t0,800001e8 <test_11+0x4> + 8000020c: 08f00e93 li t4,143 + 80000210: 00b00193 li gp,11 + 80000214: 35d31e63 bne t1,t4,80000570 <fail> + +0000000080000218 <test_12>: + 80000218: 00000213 li tp,0 + 8000021c: 0070009b addiw ra,zero,7 + 80000220: 02109093 slli ra,ra,0x21 + 80000224: 00b0011b addiw sp,zero,11 + 80000228: 02011113 slli sp,sp,0x20 + 8000022c: 0220af33 mulhsu t5,ra,sp + 80000230: 00000013 nop + 80000234: 000f0313 mv t1,t5 + 80000238: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000023c: 00200293 li t0,2 + 80000240: fc521ee3 bne tp,t0,8000021c <test_12+0x4> + 80000244: 09a00e93 li t4,154 + 80000248: 00c00193 li gp,12 + 8000024c: 33d31263 bne t1,t4,80000570 <fail> + +0000000080000250 <test_13>: + 80000250: 00000213 li tp,0 + 80000254: 00f0009b addiw ra,zero,15 + 80000258: 02009093 slli ra,ra,0x20 + 8000025c: 00b0011b addiw sp,zero,11 + 80000260: 02011113 slli sp,sp,0x20 + 80000264: 0220af33 mulhsu t5,ra,sp + 80000268: 00000013 nop + 8000026c: 00000013 nop + 80000270: 000f0313 mv t1,t5 + 80000274: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000278: 00200293 li t0,2 + 8000027c: fc521ce3 bne tp,t0,80000254 <test_13+0x4> + 80000280: 0a500e93 li t4,165 + 80000284: 00d00193 li gp,13 + 80000288: 2fd31463 bne t1,t4,80000570 <fail> + +000000008000028c <test_14>: + 8000028c: 00000213 li tp,0 + 80000290: 00d0009b addiw ra,zero,13 + 80000294: 02009093 slli ra,ra,0x20 + 80000298: 00b0011b addiw sp,zero,11 + 8000029c: 02011113 slli sp,sp,0x20 + 800002a0: 0220af33 mulhsu t5,ra,sp + 800002a4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a8: 00200293 li t0,2 + 800002ac: fe5212e3 bne tp,t0,80000290 <test_14+0x4> + 800002b0: 08f00e93 li t4,143 + 800002b4: 00e00193 li gp,14 + 800002b8: 2bdf1c63 bne t5,t4,80000570 <fail> + +00000000800002bc <test_15>: + 800002bc: 00000213 li tp,0 + 800002c0: 0070009b addiw ra,zero,7 + 800002c4: 02109093 slli ra,ra,0x21 + 800002c8: 00b0011b addiw sp,zero,11 + 800002cc: 02011113 slli sp,sp,0x20 + 800002d0: 00000013 nop + 800002d4: 0220af33 mulhsu t5,ra,sp + 800002d8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002dc: 00200293 li t0,2 + 800002e0: fe5210e3 bne tp,t0,800002c0 <test_15+0x4> + 800002e4: 09a00e93 li t4,154 + 800002e8: 00f00193 li gp,15 + 800002ec: 29df1263 bne t5,t4,80000570 <fail> + +00000000800002f0 <test_16>: + 800002f0: 00000213 li tp,0 + 800002f4: 00f0009b addiw ra,zero,15 + 800002f8: 02009093 slli ra,ra,0x20 + 800002fc: 00b0011b addiw sp,zero,11 + 80000300: 02011113 slli sp,sp,0x20 + 80000304: 00000013 nop + 80000308: 00000013 nop + 8000030c: 0220af33 mulhsu t5,ra,sp + 80000310: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000314: 00200293 li t0,2 + 80000318: fc521ee3 bne tp,t0,800002f4 <test_16+0x4> + 8000031c: 0a500e93 li t4,165 + 80000320: 01000193 li gp,16 + 80000324: 25df1663 bne t5,t4,80000570 <fail> + +0000000080000328 <test_17>: + 80000328: 00000213 li tp,0 + 8000032c: 00d0009b addiw ra,zero,13 + 80000330: 02009093 slli ra,ra,0x20 + 80000334: 00000013 nop + 80000338: 00b0011b addiw sp,zero,11 + 8000033c: 02011113 slli sp,sp,0x20 + 80000340: 0220af33 mulhsu t5,ra,sp + 80000344: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000348: 00200293 li t0,2 + 8000034c: fe5210e3 bne tp,t0,8000032c <test_17+0x4> + 80000350: 08f00e93 li t4,143 + 80000354: 01100193 li gp,17 + 80000358: 21df1c63 bne t5,t4,80000570 <fail> + +000000008000035c <test_18>: + 8000035c: 00000213 li tp,0 + 80000360: 0070009b addiw ra,zero,7 + 80000364: 02109093 slli ra,ra,0x21 + 80000368: 00000013 nop + 8000036c: 00b0011b addiw sp,zero,11 + 80000370: 02011113 slli sp,sp,0x20 + 80000374: 00000013 nop + 80000378: 0220af33 mulhsu t5,ra,sp + 8000037c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000380: 00200293 li t0,2 + 80000384: fc521ee3 bne tp,t0,80000360 <test_18+0x4> + 80000388: 09a00e93 li t4,154 + 8000038c: 01200193 li gp,18 + 80000390: 1fdf1063 bne t5,t4,80000570 <fail> + +0000000080000394 <test_19>: + 80000394: 00000213 li tp,0 + 80000398: 00f0009b addiw ra,zero,15 + 8000039c: 02009093 slli ra,ra,0x20 + 800003a0: 00000013 nop + 800003a4: 00000013 nop + 800003a8: 00b0011b addiw sp,zero,11 + 800003ac: 02011113 slli sp,sp,0x20 + 800003b0: 0220af33 mulhsu t5,ra,sp + 800003b4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003b8: 00200293 li t0,2 + 800003bc: fc521ee3 bne tp,t0,80000398 <test_19+0x4> + 800003c0: 0a500e93 li t4,165 + 800003c4: 01300193 li gp,19 + 800003c8: 1bdf1463 bne t5,t4,80000570 <fail> + +00000000800003cc <test_20>: + 800003cc: 00000213 li tp,0 + 800003d0: 00b0011b addiw sp,zero,11 + 800003d4: 02011113 slli sp,sp,0x20 + 800003d8: 00d0009b addiw ra,zero,13 + 800003dc: 02009093 slli ra,ra,0x20 + 800003e0: 0220af33 mulhsu t5,ra,sp + 800003e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003e8: 00200293 li t0,2 + 800003ec: fe5212e3 bne tp,t0,800003d0 <test_20+0x4> + 800003f0: 08f00e93 li t4,143 + 800003f4: 01400193 li gp,20 + 800003f8: 17df1c63 bne t5,t4,80000570 <fail> + +00000000800003fc <test_21>: + 800003fc: 00000213 li tp,0 + 80000400: 00b0011b addiw sp,zero,11 + 80000404: 02011113 slli sp,sp,0x20 + 80000408: 0070009b addiw ra,zero,7 + 8000040c: 02109093 slli ra,ra,0x21 + 80000410: 00000013 nop + 80000414: 0220af33 mulhsu t5,ra,sp + 80000418: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000041c: 00200293 li t0,2 + 80000420: fe5210e3 bne tp,t0,80000400 <test_21+0x4> + 80000424: 09a00e93 li t4,154 + 80000428: 01500193 li gp,21 + 8000042c: 15df1263 bne t5,t4,80000570 <fail> + +0000000080000430 <test_22>: + 80000430: 00000213 li tp,0 + 80000434: 00b0011b addiw sp,zero,11 + 80000438: 02011113 slli sp,sp,0x20 + 8000043c: 00f0009b addiw ra,zero,15 + 80000440: 02009093 slli ra,ra,0x20 + 80000444: 00000013 nop + 80000448: 00000013 nop + 8000044c: 0220af33 mulhsu t5,ra,sp + 80000450: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000454: 00200293 li t0,2 + 80000458: fc521ee3 bne tp,t0,80000434 <test_22+0x4> + 8000045c: 0a500e93 li t4,165 + 80000460: 01600193 li gp,22 + 80000464: 11df1663 bne t5,t4,80000570 <fail> + +0000000080000468 <test_23>: + 80000468: 00000213 li tp,0 + 8000046c: 00b0011b addiw sp,zero,11 + 80000470: 02011113 slli sp,sp,0x20 + 80000474: 00000013 nop + 80000478: 00d0009b addiw ra,zero,13 + 8000047c: 02009093 slli ra,ra,0x20 + 80000480: 0220af33 mulhsu t5,ra,sp + 80000484: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000488: 00200293 li t0,2 + 8000048c: fe5210e3 bne tp,t0,8000046c <test_23+0x4> + 80000490: 08f00e93 li t4,143 + 80000494: 01700193 li gp,23 + 80000498: 0ddf1c63 bne t5,t4,80000570 <fail> + +000000008000049c <test_24>: + 8000049c: 00000213 li tp,0 + 800004a0: 00b0011b addiw sp,zero,11 + 800004a4: 02011113 slli sp,sp,0x20 + 800004a8: 00000013 nop + 800004ac: 0070009b addiw ra,zero,7 + 800004b0: 02109093 slli ra,ra,0x21 + 800004b4: 00000013 nop + 800004b8: 0220af33 mulhsu t5,ra,sp + 800004bc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004c0: 00200293 li t0,2 + 800004c4: fc521ee3 bne tp,t0,800004a0 <test_24+0x4> + 800004c8: 09a00e93 li t4,154 + 800004cc: 01800193 li gp,24 + 800004d0: 0bdf1063 bne t5,t4,80000570 <fail> + +00000000800004d4 <test_25>: + 800004d4: 00000213 li tp,0 + 800004d8: 00b0011b addiw sp,zero,11 + 800004dc: 02011113 slli sp,sp,0x20 + 800004e0: 00000013 nop + 800004e4: 00000013 nop + 800004e8: 00f0009b addiw ra,zero,15 + 800004ec: 02009093 slli ra,ra,0x20 + 800004f0: 0220af33 mulhsu t5,ra,sp + 800004f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004f8: 00200293 li t0,2 + 800004fc: fc521ee3 bne tp,t0,800004d8 <test_25+0x4> + 80000500: 0a500e93 li t4,165 + 80000504: 01900193 li gp,25 + 80000508: 07df1463 bne t5,t4,80000570 <fail> + +000000008000050c <test_26>: + 8000050c: 01f0009b addiw ra,zero,31 + 80000510: 02009093 slli ra,ra,0x20 + 80000514: 02102133 mulhsu sp,zero,ra + 80000518: 00000e93 li t4,0 + 8000051c: 01a00193 li gp,26 + 80000520: 05d11863 bne sp,t4,80000570 <fail> + +0000000080000524 <test_27>: + 80000524: 0010009b addiw ra,zero,1 + 80000528: 02509093 slli ra,ra,0x25 + 8000052c: 0200a133 mulhsu sp,ra,zero + 80000530: 00000e93 li t4,0 + 80000534: 01b00193 li gp,27 + 80000538: 03d11c63 bne sp,t4,80000570 <fail> + +000000008000053c <test_28>: + 8000053c: 020020b3 mulhsu ra,zero,zero + 80000540: 00000e93 li t4,0 + 80000544: 01c00193 li gp,28 + 80000548: 03d09463 bne ra,t4,80000570 <fail> + +000000008000054c <test_29>: + 8000054c: 0210009b addiw ra,zero,33 + 80000550: 02009093 slli ra,ra,0x20 + 80000554: 0110011b addiw sp,zero,17 + 80000558: 02111113 slli sp,sp,0x21 + 8000055c: 0220a033 mulhsu zero,ra,sp + 80000560: 00000e93 li t4,0 + 80000564: 01d00193 li gp,29 + 80000568: 01d01463 bne zero,t4,80000570 <fail> + 8000056c: 00301c63 bne zero,gp,80000584 <pass> + +0000000080000570 <fail>: + 80000570: 0ff0000f fence + 80000574: 00018063 beqz gp,80000574 <fail+0x4> + 80000578: 00119193 slli gp,gp,0x1 + 8000057c: 0011e193 ori gp,gp,1 + 80000580: 00000073 ecall + +0000000080000584 <pass>: + 80000584: 0ff0000f fence + 80000588: 00100193 li gp,1 + 8000058c: 00000073 ecall + 80000590: c0001073 unimp + 80000594: 0000 unimp + 80000596: 0000 unimp + 80000598: 0000 unimp + 8000059a: 0000 unimp + 8000059c: 0000 unimp + 8000059e: 0000 unimp + 800005a0: 0000 unimp + 800005a2: 0000 unimp + 800005a4: 0000 unimp + 800005a6: 0000 unimp + 800005a8: 0000 unimp + 800005aa: 0000 unimp + 800005ac: 0000 unimp + 800005ae: 0000 unimp + 800005b0: 0000 unimp + 800005b2: 0000 unimp + 800005b4: 0000 unimp + 800005b6: 0000 unimp + 800005b8: 0000 unimp + 800005ba: 0000 unimp + 800005bc: 0000 unimp + 800005be: 0000 unimp + 800005c0: 0000 unimp + 800005c2: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-mulhsu.elf b/test/riscv/tests/rv64um-p-mulhsu.elf Binary files differnew file mode 100755 index 00000000..93efb0b3 --- /dev/null +++ b/test/riscv/tests/rv64um-p-mulhsu.elf diff --git a/test/riscv/tests/rv64um-p-mulhu.dump b/test/riscv/tests/rv64um-p-mulhu.dump new file mode 100644 index 00000000..82860e14 --- /dev/null +++ b/test/riscv/tests/rv64um-p-mulhu.dump @@ -0,0 +1,492 @@ + +rv64um-p-mulhu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 00000113 li sp,0 + 80000104: 0220bf33 mulhu t5,ra,sp + 80000108: 00000e93 li t4,0 + 8000010c: 00200193 li gp,2 + 80000110: 4fdf1063 bne t5,t4,800005f0 <fail> + +0000000080000114 <test_3>: + 80000114: 00100093 li ra,1 + 80000118: 00100113 li sp,1 + 8000011c: 0220bf33 mulhu t5,ra,sp + 80000120: 00000e93 li t4,0 + 80000124: 00300193 li gp,3 + 80000128: 4ddf1463 bne t5,t4,800005f0 <fail> + +000000008000012c <test_4>: + 8000012c: 00300093 li ra,3 + 80000130: 00700113 li sp,7 + 80000134: 0220bf33 mulhu t5,ra,sp + 80000138: 00000e93 li t4,0 + 8000013c: 00400193 li gp,4 + 80000140: 4bdf1863 bne t5,t4,800005f0 <fail> + +0000000080000144 <test_5>: + 80000144: 00000093 li ra,0 + 80000148: ffff8137 lui sp,0xffff8 + 8000014c: 0220bf33 mulhu t5,ra,sp + 80000150: 00000e93 li t4,0 + 80000154: 00500193 li gp,5 + 80000158: 49df1c63 bne t5,t4,800005f0 <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 00000113 li sp,0 + 80000164: 0220bf33 mulhu t5,ra,sp + 80000168: 00000e93 li t4,0 + 8000016c: 00600193 li gp,6 + 80000170: 49df1063 bne t5,t4,800005f0 <fail> + +0000000080000174 <test_7>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: ffff8137 lui sp,0xffff8 + 8000017c: 0220bf33 mulhu t5,ra,sp + 80000180: ffff0eb7 lui t4,0xffff0 + 80000184: fffe8e9b addiw t4,t4,-1 + 80000188: 00fe9e93 slli t4,t4,0xf + 8000018c: 00700193 li gp,7 + 80000190: 47df1063 bne t5,t4,800005f0 <fail> + +0000000080000194 <test_30>: + 80000194: faaab0b7 lui ra,0xfaaab + 80000198: aab0809b addiw ra,ra,-1365 + 8000019c: 00c09093 slli ra,ra,0xc + 800001a0: aab08093 addi ra,ra,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa8aab> + 800001a4: 00c09093 slli ra,ra,0xc + 800001a8: aab08093 addi ra,ra,-1365 + 800001ac: 00c09093 slli ra,ra,0xc + 800001b0: aab08093 addi ra,ra,-1365 + 800001b4: 00030137 lui sp,0x30 + 800001b8: e7d1011b addiw sp,sp,-387 + 800001bc: 0220bf33 mulhu t5,ra,sp + 800001c0: 00020eb7 lui t4,0x20 + 800001c4: efee8e9b addiw t4,t4,-258 + 800001c8: 01e00193 li gp,30 + 800001cc: 43df1263 bne t5,t4,800005f0 <fail> + +00000000800001d0 <test_31>: + 800001d0: 000300b7 lui ra,0x30 + 800001d4: e7d0809b addiw ra,ra,-387 + 800001d8: faaab137 lui sp,0xfaaab + 800001dc: aab1011b addiw sp,sp,-1365 + 800001e0: 00c11113 slli sp,sp,0xc + 800001e4: aab10113 addi sp,sp,-1365 # fffffffffaaaaaab <_end+0xffffffff7aaa8aab> + 800001e8: 00c11113 slli sp,sp,0xc + 800001ec: aab10113 addi sp,sp,-1365 + 800001f0: 00c11113 slli sp,sp,0xc + 800001f4: aab10113 addi sp,sp,-1365 + 800001f8: 0220bf33 mulhu t5,ra,sp + 800001fc: 00020eb7 lui t4,0x20 + 80000200: efee8e9b addiw t4,t4,-258 + 80000204: 01f00193 li gp,31 + 80000208: 3fdf1463 bne t5,t4,800005f0 <fail> + +000000008000020c <test_8>: + 8000020c: 00d0009b addiw ra,zero,13 + 80000210: 02009093 slli ra,ra,0x20 + 80000214: 00b0011b addiw sp,zero,11 + 80000218: 02011113 slli sp,sp,0x20 + 8000021c: 0220b0b3 mulhu ra,ra,sp + 80000220: 08f00e93 li t4,143 + 80000224: 00800193 li gp,8 + 80000228: 3dd09463 bne ra,t4,800005f0 <fail> + +000000008000022c <test_9>: + 8000022c: 0070009b addiw ra,zero,7 + 80000230: 02109093 slli ra,ra,0x21 + 80000234: 00b0011b addiw sp,zero,11 + 80000238: 02011113 slli sp,sp,0x20 + 8000023c: 0220b133 mulhu sp,ra,sp + 80000240: 09a00e93 li t4,154 + 80000244: 00900193 li gp,9 + 80000248: 3bd11463 bne sp,t4,800005f0 <fail> + +000000008000024c <test_10>: + 8000024c: 00d0009b addiw ra,zero,13 + 80000250: 02009093 slli ra,ra,0x20 + 80000254: 0210b0b3 mulhu ra,ra,ra + 80000258: 0a900e93 li t4,169 + 8000025c: 00a00193 li gp,10 + 80000260: 39d09863 bne ra,t4,800005f0 <fail> + +0000000080000264 <test_11>: + 80000264: 00000213 li tp,0 + 80000268: 00d0009b addiw ra,zero,13 + 8000026c: 02009093 slli ra,ra,0x20 + 80000270: 00b0011b addiw sp,zero,11 + 80000274: 02011113 slli sp,sp,0x20 + 80000278: 0220bf33 mulhu t5,ra,sp + 8000027c: 000f0313 mv t1,t5 + 80000280: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000284: 00200293 li t0,2 + 80000288: fe5210e3 bne tp,t0,80000268 <test_11+0x4> + 8000028c: 08f00e93 li t4,143 + 80000290: 00b00193 li gp,11 + 80000294: 35d31e63 bne t1,t4,800005f0 <fail> + +0000000080000298 <test_12>: + 80000298: 00000213 li tp,0 + 8000029c: 0070009b addiw ra,zero,7 + 800002a0: 02109093 slli ra,ra,0x21 + 800002a4: 00b0011b addiw sp,zero,11 + 800002a8: 02011113 slli sp,sp,0x20 + 800002ac: 0220bf33 mulhu t5,ra,sp + 800002b0: 00000013 nop + 800002b4: 000f0313 mv t1,t5 + 800002b8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002bc: 00200293 li t0,2 + 800002c0: fc521ee3 bne tp,t0,8000029c <test_12+0x4> + 800002c4: 09a00e93 li t4,154 + 800002c8: 00c00193 li gp,12 + 800002cc: 33d31263 bne t1,t4,800005f0 <fail> + +00000000800002d0 <test_13>: + 800002d0: 00000213 li tp,0 + 800002d4: 00f0009b addiw ra,zero,15 + 800002d8: 02009093 slli ra,ra,0x20 + 800002dc: 00b0011b addiw sp,zero,11 + 800002e0: 02011113 slli sp,sp,0x20 + 800002e4: 0220bf33 mulhu t5,ra,sp + 800002e8: 00000013 nop + 800002ec: 00000013 nop + 800002f0: 000f0313 mv t1,t5 + 800002f4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002f8: 00200293 li t0,2 + 800002fc: fc521ce3 bne tp,t0,800002d4 <test_13+0x4> + 80000300: 0a500e93 li t4,165 + 80000304: 00d00193 li gp,13 + 80000308: 2fd31463 bne t1,t4,800005f0 <fail> + +000000008000030c <test_14>: + 8000030c: 00000213 li tp,0 + 80000310: 00d0009b addiw ra,zero,13 + 80000314: 02009093 slli ra,ra,0x20 + 80000318: 00b0011b addiw sp,zero,11 + 8000031c: 02011113 slli sp,sp,0x20 + 80000320: 0220bf33 mulhu t5,ra,sp + 80000324: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000328: 00200293 li t0,2 + 8000032c: fe5212e3 bne tp,t0,80000310 <test_14+0x4> + 80000330: 08f00e93 li t4,143 + 80000334: 00e00193 li gp,14 + 80000338: 2bdf1c63 bne t5,t4,800005f0 <fail> + +000000008000033c <test_15>: + 8000033c: 00000213 li tp,0 + 80000340: 0070009b addiw ra,zero,7 + 80000344: 02109093 slli ra,ra,0x21 + 80000348: 00b0011b addiw sp,zero,11 + 8000034c: 02011113 slli sp,sp,0x20 + 80000350: 00000013 nop + 80000354: 0220bf33 mulhu t5,ra,sp + 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000035c: 00200293 li t0,2 + 80000360: fe5210e3 bne tp,t0,80000340 <test_15+0x4> + 80000364: 09a00e93 li t4,154 + 80000368: 00f00193 li gp,15 + 8000036c: 29df1263 bne t5,t4,800005f0 <fail> + +0000000080000370 <test_16>: + 80000370: 00000213 li tp,0 + 80000374: 00f0009b addiw ra,zero,15 + 80000378: 02009093 slli ra,ra,0x20 + 8000037c: 00b0011b addiw sp,zero,11 + 80000380: 02011113 slli sp,sp,0x20 + 80000384: 00000013 nop + 80000388: 00000013 nop + 8000038c: 0220bf33 mulhu t5,ra,sp + 80000390: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000394: 00200293 li t0,2 + 80000398: fc521ee3 bne tp,t0,80000374 <test_16+0x4> + 8000039c: 0a500e93 li t4,165 + 800003a0: 01000193 li gp,16 + 800003a4: 25df1663 bne t5,t4,800005f0 <fail> + +00000000800003a8 <test_17>: + 800003a8: 00000213 li tp,0 + 800003ac: 00d0009b addiw ra,zero,13 + 800003b0: 02009093 slli ra,ra,0x20 + 800003b4: 00000013 nop + 800003b8: 00b0011b addiw sp,zero,11 + 800003bc: 02011113 slli sp,sp,0x20 + 800003c0: 0220bf33 mulhu t5,ra,sp + 800003c4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003c8: 00200293 li t0,2 + 800003cc: fe5210e3 bne tp,t0,800003ac <test_17+0x4> + 800003d0: 08f00e93 li t4,143 + 800003d4: 01100193 li gp,17 + 800003d8: 21df1c63 bne t5,t4,800005f0 <fail> + +00000000800003dc <test_18>: + 800003dc: 00000213 li tp,0 + 800003e0: 0070009b addiw ra,zero,7 + 800003e4: 02109093 slli ra,ra,0x21 + 800003e8: 00000013 nop + 800003ec: 00b0011b addiw sp,zero,11 + 800003f0: 02011113 slli sp,sp,0x20 + 800003f4: 00000013 nop + 800003f8: 0220bf33 mulhu t5,ra,sp + 800003fc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000400: 00200293 li t0,2 + 80000404: fc521ee3 bne tp,t0,800003e0 <test_18+0x4> + 80000408: 09a00e93 li t4,154 + 8000040c: 01200193 li gp,18 + 80000410: 1fdf1063 bne t5,t4,800005f0 <fail> + +0000000080000414 <test_19>: + 80000414: 00000213 li tp,0 + 80000418: 00f0009b addiw ra,zero,15 + 8000041c: 02009093 slli ra,ra,0x20 + 80000420: 00000013 nop + 80000424: 00000013 nop + 80000428: 00b0011b addiw sp,zero,11 + 8000042c: 02011113 slli sp,sp,0x20 + 80000430: 0220bf33 mulhu t5,ra,sp + 80000434: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000438: 00200293 li t0,2 + 8000043c: fc521ee3 bne tp,t0,80000418 <test_19+0x4> + 80000440: 0a500e93 li t4,165 + 80000444: 01300193 li gp,19 + 80000448: 1bdf1463 bne t5,t4,800005f0 <fail> + +000000008000044c <test_20>: + 8000044c: 00000213 li tp,0 + 80000450: 00b0011b addiw sp,zero,11 + 80000454: 02011113 slli sp,sp,0x20 + 80000458: 00d0009b addiw ra,zero,13 + 8000045c: 02009093 slli ra,ra,0x20 + 80000460: 0220bf33 mulhu t5,ra,sp + 80000464: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000468: 00200293 li t0,2 + 8000046c: fe5212e3 bne tp,t0,80000450 <test_20+0x4> + 80000470: 08f00e93 li t4,143 + 80000474: 01400193 li gp,20 + 80000478: 17df1c63 bne t5,t4,800005f0 <fail> + +000000008000047c <test_21>: + 8000047c: 00000213 li tp,0 + 80000480: 00b0011b addiw sp,zero,11 + 80000484: 02011113 slli sp,sp,0x20 + 80000488: 0070009b addiw ra,zero,7 + 8000048c: 02109093 slli ra,ra,0x21 + 80000490: 00000013 nop + 80000494: 0220bf33 mulhu t5,ra,sp + 80000498: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000049c: 00200293 li t0,2 + 800004a0: fe5210e3 bne tp,t0,80000480 <test_21+0x4> + 800004a4: 09a00e93 li t4,154 + 800004a8: 01500193 li gp,21 + 800004ac: 15df1263 bne t5,t4,800005f0 <fail> + +00000000800004b0 <test_22>: + 800004b0: 00000213 li tp,0 + 800004b4: 00b0011b addiw sp,zero,11 + 800004b8: 02011113 slli sp,sp,0x20 + 800004bc: 00f0009b addiw ra,zero,15 + 800004c0: 02009093 slli ra,ra,0x20 + 800004c4: 00000013 nop + 800004c8: 00000013 nop + 800004cc: 0220bf33 mulhu t5,ra,sp + 800004d0: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800004d4: 00200293 li t0,2 + 800004d8: fc521ee3 bne tp,t0,800004b4 <test_22+0x4> + 800004dc: 0a500e93 li t4,165 + 800004e0: 01600193 li gp,22 + 800004e4: 11df1663 bne t5,t4,800005f0 <fail> + +00000000800004e8 <test_23>: + 800004e8: 00000213 li tp,0 + 800004ec: 00b0011b addiw sp,zero,11 + 800004f0: 02011113 slli sp,sp,0x20 + 800004f4: 00000013 nop + 800004f8: 00d0009b addiw ra,zero,13 + 800004fc: 02009093 slli ra,ra,0x20 + 80000500: 0220bf33 mulhu t5,ra,sp + 80000504: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000508: 00200293 li t0,2 + 8000050c: fe5210e3 bne tp,t0,800004ec <test_23+0x4> + 80000510: 08f00e93 li t4,143 + 80000514: 01700193 li gp,23 + 80000518: 0ddf1c63 bne t5,t4,800005f0 <fail> + +000000008000051c <test_24>: + 8000051c: 00000213 li tp,0 + 80000520: 00b0011b addiw sp,zero,11 + 80000524: 02011113 slli sp,sp,0x20 + 80000528: 00000013 nop + 8000052c: 0070009b addiw ra,zero,7 + 80000530: 02109093 slli ra,ra,0x21 + 80000534: 00000013 nop + 80000538: 0220bf33 mulhu t5,ra,sp + 8000053c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000540: 00200293 li t0,2 + 80000544: fc521ee3 bne tp,t0,80000520 <test_24+0x4> + 80000548: 09a00e93 li t4,154 + 8000054c: 01800193 li gp,24 + 80000550: 0bdf1063 bne t5,t4,800005f0 <fail> + +0000000080000554 <test_25>: + 80000554: 00000213 li tp,0 + 80000558: 00b0011b addiw sp,zero,11 + 8000055c: 02011113 slli sp,sp,0x20 + 80000560: 00000013 nop + 80000564: 00000013 nop + 80000568: 00f0009b addiw ra,zero,15 + 8000056c: 02009093 slli ra,ra,0x20 + 80000570: 0220bf33 mulhu t5,ra,sp + 80000574: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000578: 00200293 li t0,2 + 8000057c: fc521ee3 bne tp,t0,80000558 <test_25+0x4> + 80000580: 0a500e93 li t4,165 + 80000584: 01900193 li gp,25 + 80000588: 07df1463 bne t5,t4,800005f0 <fail> + +000000008000058c <test_26>: + 8000058c: 01f0009b addiw ra,zero,31 + 80000590: 02009093 slli ra,ra,0x20 + 80000594: 02103133 mulhu sp,zero,ra + 80000598: 00000e93 li t4,0 + 8000059c: 01a00193 li gp,26 + 800005a0: 05d11863 bne sp,t4,800005f0 <fail> + +00000000800005a4 <test_27>: + 800005a4: 0010009b addiw ra,zero,1 + 800005a8: 02509093 slli ra,ra,0x25 + 800005ac: 0200b133 mulhu sp,ra,zero + 800005b0: 00000e93 li t4,0 + 800005b4: 01b00193 li gp,27 + 800005b8: 03d11c63 bne sp,t4,800005f0 <fail> + +00000000800005bc <test_28>: + 800005bc: 020030b3 mulhu ra,zero,zero + 800005c0: 00000e93 li t4,0 + 800005c4: 01c00193 li gp,28 + 800005c8: 03d09463 bne ra,t4,800005f0 <fail> + +00000000800005cc <test_29>: + 800005cc: 0210009b addiw ra,zero,33 + 800005d0: 02009093 slli ra,ra,0x20 + 800005d4: 0110011b addiw sp,zero,17 + 800005d8: 02111113 slli sp,sp,0x21 + 800005dc: 0220b033 mulhu zero,ra,sp + 800005e0: 00000e93 li t4,0 + 800005e4: 01d00193 li gp,29 + 800005e8: 01d01463 bne zero,t4,800005f0 <fail> + 800005ec: 00301c63 bne zero,gp,80000604 <pass> + +00000000800005f0 <fail>: + 800005f0: 0ff0000f fence + 800005f4: 00018063 beqz gp,800005f4 <fail+0x4> + 800005f8: 00119193 slli gp,gp,0x1 + 800005fc: 0011e193 ori gp,gp,1 + 80000600: 00000073 ecall + +0000000080000604 <pass>: + 80000604: 0ff0000f fence + 80000608: 00100193 li gp,1 + 8000060c: 00000073 ecall + 80000610: c0001073 unimp + 80000614: 0000 unimp + 80000616: 0000 unimp + 80000618: 0000 unimp + 8000061a: 0000 unimp + 8000061c: 0000 unimp + 8000061e: 0000 unimp + 80000620: 0000 unimp + 80000622: 0000 unimp + 80000624: 0000 unimp + 80000626: 0000 unimp + 80000628: 0000 unimp + 8000062a: 0000 unimp + 8000062c: 0000 unimp + 8000062e: 0000 unimp + 80000630: 0000 unimp + 80000632: 0000 unimp + 80000634: 0000 unimp + 80000636: 0000 unimp + 80000638: 0000 unimp + 8000063a: 0000 unimp + 8000063c: 0000 unimp + 8000063e: 0000 unimp + 80000640: 0000 unimp + 80000642: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-mulhu.elf b/test/riscv/tests/rv64um-p-mulhu.elf Binary files differnew file mode 100755 index 00000000..f2b74120 --- /dev/null +++ b/test/riscv/tests/rv64um-p-mulhu.elf diff --git a/test/riscv/tests/rv64um-p-mulw.dump b/test/riscv/tests/rv64um-p-mulw.dump new file mode 100644 index 00000000..c9c2d8de --- /dev/null +++ b/test/riscv/tests/rv64um-p-mulw.dump @@ -0,0 +1,399 @@ + +rv64um-p-mulw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 00000093 li ra,0 + 80000100: 00000113 li sp,0 + 80000104: 02208f3b mulw t5,ra,sp + 80000108: 00000e93 li t4,0 + 8000010c: 00200193 li gp,2 + 80000110: 3ddf1263 bne t5,t4,800004d4 <fail> + +0000000080000114 <test_3>: + 80000114: 00100093 li ra,1 + 80000118: 00100113 li sp,1 + 8000011c: 02208f3b mulw t5,ra,sp + 80000120: 00100e93 li t4,1 + 80000124: 00300193 li gp,3 + 80000128: 3bdf1663 bne t5,t4,800004d4 <fail> + +000000008000012c <test_4>: + 8000012c: 00300093 li ra,3 + 80000130: 00700113 li sp,7 + 80000134: 02208f3b mulw t5,ra,sp + 80000138: 01500e93 li t4,21 + 8000013c: 00400193 li gp,4 + 80000140: 39df1a63 bne t5,t4,800004d4 <fail> + +0000000080000144 <test_5>: + 80000144: 00000093 li ra,0 + 80000148: ffff8137 lui sp,0xffff8 + 8000014c: 02208f3b mulw t5,ra,sp + 80000150: 00000e93 li t4,0 + 80000154: 00500193 li gp,5 + 80000158: 37df1e63 bne t5,t4,800004d4 <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 00000113 li sp,0 + 80000164: 02208f3b mulw t5,ra,sp + 80000168: 00000e93 li t4,0 + 8000016c: 00600193 li gp,6 + 80000170: 37df1263 bne t5,t4,800004d4 <fail> + +0000000080000174 <test_7>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: ffff8137 lui sp,0xffff8 + 8000017c: 02208f3b mulw t5,ra,sp + 80000180: 00000e93 li t4,0 + 80000184: 00700193 li gp,7 + 80000188: 35df1663 bne t5,t4,800004d4 <fail> + +000000008000018c <test_8>: + 8000018c: 00d00093 li ra,13 + 80000190: 00b00113 li sp,11 + 80000194: 022080bb mulw ra,ra,sp + 80000198: 08f00e93 li t4,143 + 8000019c: 00800193 li gp,8 + 800001a0: 33d09a63 bne ra,t4,800004d4 <fail> + +00000000800001a4 <test_9>: + 800001a4: 00e00093 li ra,14 + 800001a8: 00b00113 li sp,11 + 800001ac: 0220813b mulw sp,ra,sp + 800001b0: 09a00e93 li t4,154 + 800001b4: 00900193 li gp,9 + 800001b8: 31d11e63 bne sp,t4,800004d4 <fail> + +00000000800001bc <test_10>: + 800001bc: 00d00093 li ra,13 + 800001c0: 021080bb mulw ra,ra,ra + 800001c4: 0a900e93 li t4,169 + 800001c8: 00a00193 li gp,10 + 800001cc: 31d09463 bne ra,t4,800004d4 <fail> + +00000000800001d0 <test_11>: + 800001d0: 00000213 li tp,0 + 800001d4: 00d00093 li ra,13 + 800001d8: 00b00113 li sp,11 + 800001dc: 02208f3b mulw t5,ra,sp + 800001e0: 000f0313 mv t1,t5 + 800001e4: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800001e8: 00200293 li t0,2 + 800001ec: fe5214e3 bne tp,t0,800001d4 <test_11+0x4> + 800001f0: 08f00e93 li t4,143 + 800001f4: 00b00193 li gp,11 + 800001f8: 2dd31e63 bne t1,t4,800004d4 <fail> + +00000000800001fc <test_12>: + 800001fc: 00000213 li tp,0 + 80000200: 00e00093 li ra,14 + 80000204: 00b00113 li sp,11 + 80000208: 02208f3b mulw t5,ra,sp + 8000020c: 00000013 nop + 80000210: 000f0313 mv t1,t5 + 80000214: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000218: 00200293 li t0,2 + 8000021c: fe5212e3 bne tp,t0,80000200 <test_12+0x4> + 80000220: 09a00e93 li t4,154 + 80000224: 00c00193 li gp,12 + 80000228: 2bd31663 bne t1,t4,800004d4 <fail> + +000000008000022c <test_13>: + 8000022c: 00000213 li tp,0 + 80000230: 00f00093 li ra,15 + 80000234: 00b00113 li sp,11 + 80000238: 02208f3b mulw t5,ra,sp + 8000023c: 00000013 nop + 80000240: 00000013 nop + 80000244: 000f0313 mv t1,t5 + 80000248: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000024c: 00200293 li t0,2 + 80000250: fe5210e3 bne tp,t0,80000230 <test_13+0x4> + 80000254: 0a500e93 li t4,165 + 80000258: 00d00193 li gp,13 + 8000025c: 27d31c63 bne t1,t4,800004d4 <fail> + +0000000080000260 <test_14>: + 80000260: 00000213 li tp,0 + 80000264: 00d00093 li ra,13 + 80000268: 00b00113 li sp,11 + 8000026c: 02208f3b mulw t5,ra,sp + 80000270: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000274: 00200293 li t0,2 + 80000278: fe5216e3 bne tp,t0,80000264 <test_14+0x4> + 8000027c: 08f00e93 li t4,143 + 80000280: 00e00193 li gp,14 + 80000284: 25df1863 bne t5,t4,800004d4 <fail> + +0000000080000288 <test_15>: + 80000288: 00000213 li tp,0 + 8000028c: 00e00093 li ra,14 + 80000290: 00b00113 li sp,11 + 80000294: 00000013 nop + 80000298: 02208f3b mulw t5,ra,sp + 8000029c: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002a0: 00200293 li t0,2 + 800002a4: fe5214e3 bne tp,t0,8000028c <test_15+0x4> + 800002a8: 09a00e93 li t4,154 + 800002ac: 00f00193 li gp,15 + 800002b0: 23df1263 bne t5,t4,800004d4 <fail> + +00000000800002b4 <test_16>: + 800002b4: 00000213 li tp,0 + 800002b8: 00f00093 li ra,15 + 800002bc: 00b00113 li sp,11 + 800002c0: 00000013 nop + 800002c4: 00000013 nop + 800002c8: 02208f3b mulw t5,ra,sp + 800002cc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002d0: 00200293 li t0,2 + 800002d4: fe5212e3 bne tp,t0,800002b8 <test_16+0x4> + 800002d8: 0a500e93 li t4,165 + 800002dc: 01000193 li gp,16 + 800002e0: 1fdf1a63 bne t5,t4,800004d4 <fail> + +00000000800002e4 <test_17>: + 800002e4: 00000213 li tp,0 + 800002e8: 00d00093 li ra,13 + 800002ec: 00000013 nop + 800002f0: 00b00113 li sp,11 + 800002f4: 02208f3b mulw t5,ra,sp + 800002f8: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800002fc: 00200293 li t0,2 + 80000300: fe5214e3 bne tp,t0,800002e8 <test_17+0x4> + 80000304: 08f00e93 li t4,143 + 80000308: 01100193 li gp,17 + 8000030c: 1ddf1463 bne t5,t4,800004d4 <fail> + +0000000080000310 <test_18>: + 80000310: 00000213 li tp,0 + 80000314: 00e00093 li ra,14 + 80000318: 00000013 nop + 8000031c: 00b00113 li sp,11 + 80000320: 00000013 nop + 80000324: 02208f3b mulw t5,ra,sp + 80000328: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000032c: 00200293 li t0,2 + 80000330: fe5212e3 bne tp,t0,80000314 <test_18+0x4> + 80000334: 09a00e93 li t4,154 + 80000338: 01200193 li gp,18 + 8000033c: 19df1c63 bne t5,t4,800004d4 <fail> + +0000000080000340 <test_19>: + 80000340: 00000213 li tp,0 + 80000344: 00f00093 li ra,15 + 80000348: 00000013 nop + 8000034c: 00000013 nop + 80000350: 00b00113 li sp,11 + 80000354: 02208f3b mulw t5,ra,sp + 80000358: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000035c: 00200293 li t0,2 + 80000360: fe5212e3 bne tp,t0,80000344 <test_19+0x4> + 80000364: 0a500e93 li t4,165 + 80000368: 01300193 li gp,19 + 8000036c: 17df1463 bne t5,t4,800004d4 <fail> + +0000000080000370 <test_20>: + 80000370: 00000213 li tp,0 + 80000374: 00b00113 li sp,11 + 80000378: 00d00093 li ra,13 + 8000037c: 02208f3b mulw t5,ra,sp + 80000380: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 80000384: 00200293 li t0,2 + 80000388: fe5216e3 bne tp,t0,80000374 <test_20+0x4> + 8000038c: 08f00e93 li t4,143 + 80000390: 01400193 li gp,20 + 80000394: 15df1063 bne t5,t4,800004d4 <fail> + +0000000080000398 <test_21>: + 80000398: 00000213 li tp,0 + 8000039c: 00b00113 li sp,11 + 800003a0: 00e00093 li ra,14 + 800003a4: 00000013 nop + 800003a8: 02208f3b mulw t5,ra,sp + 800003ac: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003b0: 00200293 li t0,2 + 800003b4: fe5214e3 bne tp,t0,8000039c <test_21+0x4> + 800003b8: 09a00e93 li t4,154 + 800003bc: 01500193 li gp,21 + 800003c0: 11df1a63 bne t5,t4,800004d4 <fail> + +00000000800003c4 <test_22>: + 800003c4: 00000213 li tp,0 + 800003c8: 00b00113 li sp,11 + 800003cc: 00f00093 li ra,15 + 800003d0: 00000013 nop + 800003d4: 00000013 nop + 800003d8: 02208f3b mulw t5,ra,sp + 800003dc: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 800003e0: 00200293 li t0,2 + 800003e4: fe5212e3 bne tp,t0,800003c8 <test_22+0x4> + 800003e8: 0a500e93 li t4,165 + 800003ec: 01600193 li gp,22 + 800003f0: 0fdf1263 bne t5,t4,800004d4 <fail> + +00000000800003f4 <test_23>: + 800003f4: 00000213 li tp,0 + 800003f8: 00b00113 li sp,11 + 800003fc: 00000013 nop + 80000400: 00d00093 li ra,13 + 80000404: 02208f3b mulw t5,ra,sp + 80000408: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000040c: 00200293 li t0,2 + 80000410: fe5214e3 bne tp,t0,800003f8 <test_23+0x4> + 80000414: 08f00e93 li t4,143 + 80000418: 01700193 li gp,23 + 8000041c: 0bdf1c63 bne t5,t4,800004d4 <fail> + +0000000080000420 <test_24>: + 80000420: 00000213 li tp,0 + 80000424: 00b00113 li sp,11 + 80000428: 00000013 nop + 8000042c: 00e00093 li ra,14 + 80000430: 00000013 nop + 80000434: 02208f3b mulw t5,ra,sp + 80000438: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000043c: 00200293 li t0,2 + 80000440: fe5212e3 bne tp,t0,80000424 <test_24+0x4> + 80000444: 09a00e93 li t4,154 + 80000448: 01800193 li gp,24 + 8000044c: 09df1463 bne t5,t4,800004d4 <fail> + +0000000080000450 <test_25>: + 80000450: 00000213 li tp,0 + 80000454: 00b00113 li sp,11 + 80000458: 00000013 nop + 8000045c: 00000013 nop + 80000460: 00f00093 li ra,15 + 80000464: 02208f3b mulw t5,ra,sp + 80000468: 00120213 addi tp,tp,1 # 1 <_start-0x7fffffff> + 8000046c: 00200293 li t0,2 + 80000470: fe5212e3 bne tp,t0,80000454 <test_25+0x4> + 80000474: 0a500e93 li t4,165 + 80000478: 01900193 li gp,25 + 8000047c: 05df1c63 bne t5,t4,800004d4 <fail> + +0000000080000480 <test_26>: + 80000480: 01f00093 li ra,31 + 80000484: 0210013b mulw sp,zero,ra + 80000488: 00000e93 li t4,0 + 8000048c: 01a00193 li gp,26 + 80000490: 05d11263 bne sp,t4,800004d4 <fail> + +0000000080000494 <test_27>: + 80000494: 02000093 li ra,32 + 80000498: 0200813b mulw sp,ra,zero + 8000049c: 00000e93 li t4,0 + 800004a0: 01b00193 li gp,27 + 800004a4: 03d11863 bne sp,t4,800004d4 <fail> + +00000000800004a8 <test_28>: + 800004a8: 020000bb mulw ra,zero,zero + 800004ac: 00000e93 li t4,0 + 800004b0: 01c00193 li gp,28 + 800004b4: 03d09063 bne ra,t4,800004d4 <fail> + +00000000800004b8 <test_29>: + 800004b8: 02100093 li ra,33 + 800004bc: 02200113 li sp,34 + 800004c0: 0220803b mulw zero,ra,sp + 800004c4: 00000e93 li t4,0 + 800004c8: 01d00193 li gp,29 + 800004cc: 01d01463 bne zero,t4,800004d4 <fail> + 800004d0: 00301c63 bne zero,gp,800004e8 <pass> + +00000000800004d4 <fail>: + 800004d4: 0ff0000f fence + 800004d8: 00018063 beqz gp,800004d8 <fail+0x4> + 800004dc: 00119193 slli gp,gp,0x1 + 800004e0: 0011e193 ori gp,gp,1 + 800004e4: 00000073 ecall + +00000000800004e8 <pass>: + 800004e8: 0ff0000f fence + 800004ec: 00100193 li gp,1 + 800004f0: 00000073 ecall + 800004f4: c0001073 unimp + 800004f8: 0000 unimp + 800004fa: 0000 unimp + 800004fc: 0000 unimp + 800004fe: 0000 unimp + 80000500: 0000 unimp + 80000502: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-mulw.elf b/test/riscv/tests/rv64um-p-mulw.elf Binary files differnew file mode 100755 index 00000000..7b1242fd --- /dev/null +++ b/test/riscv/tests/rv64um-p-mulw.elf diff --git a/test/riscv/tests/rv64um-p-rem.dump b/test/riscv/tests/rv64um-p-rem.dump new file mode 100644 index 00000000..a3676862 --- /dev/null +++ b/test/riscv/tests/rv64um-p-rem.dump @@ -0,0 +1,196 @@ + +rv64um-p-rem: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 01400093 li ra,20 + 80000100: 00600113 li sp,6 + 80000104: 0220ef33 rem t5,ra,sp + 80000108: 00200e93 li t4,2 + 8000010c: 00200193 li gp,2 + 80000110: 0ddf1c63 bne t5,t4,800001e8 <fail> + +0000000080000114 <test_3>: + 80000114: fec00093 li ra,-20 + 80000118: 00600113 li sp,6 + 8000011c: 0220ef33 rem t5,ra,sp + 80000120: ffe00e93 li t4,-2 + 80000124: 00300193 li gp,3 + 80000128: 0ddf1063 bne t5,t4,800001e8 <fail> + +000000008000012c <test_4>: + 8000012c: 01400093 li ra,20 + 80000130: ffa00113 li sp,-6 + 80000134: 0220ef33 rem t5,ra,sp + 80000138: 00200e93 li t4,2 + 8000013c: 00400193 li gp,4 + 80000140: 0bdf1463 bne t5,t4,800001e8 <fail> + +0000000080000144 <test_5>: + 80000144: fec00093 li ra,-20 + 80000148: ffa00113 li sp,-6 + 8000014c: 0220ef33 rem t5,ra,sp + 80000150: ffe00e93 li t4,-2 + 80000154: 00500193 li gp,5 + 80000158: 09df1863 bne t5,t4,800001e8 <fail> + +000000008000015c <test_6>: + 8000015c: fff0009b addiw ra,zero,-1 + 80000160: 03f09093 slli ra,ra,0x3f + 80000164: 00100113 li sp,1 + 80000168: 0220ef33 rem t5,ra,sp + 8000016c: 00000e93 li t4,0 + 80000170: 00600193 li gp,6 + 80000174: 07df1a63 bne t5,t4,800001e8 <fail> + +0000000080000178 <test_7>: + 80000178: fff0009b addiw ra,zero,-1 + 8000017c: 03f09093 slli ra,ra,0x3f + 80000180: fff00113 li sp,-1 + 80000184: 0220ef33 rem t5,ra,sp + 80000188: 00000e93 li t4,0 + 8000018c: 00700193 li gp,7 + 80000190: 05df1c63 bne t5,t4,800001e8 <fail> + +0000000080000194 <test_8>: + 80000194: fff0009b addiw ra,zero,-1 + 80000198: 03f09093 slli ra,ra,0x3f + 8000019c: 00000113 li sp,0 + 800001a0: 0220ef33 rem t5,ra,sp + 800001a4: fff00e9b addiw t4,zero,-1 + 800001a8: 03fe9e93 slli t4,t4,0x3f + 800001ac: 00800193 li gp,8 + 800001b0: 03df1c63 bne t5,t4,800001e8 <fail> + +00000000800001b4 <test_9>: + 800001b4: 00100093 li ra,1 + 800001b8: 00000113 li sp,0 + 800001bc: 0220ef33 rem t5,ra,sp + 800001c0: 00100e93 li t4,1 + 800001c4: 00900193 li gp,9 + 800001c8: 03df1063 bne t5,t4,800001e8 <fail> + +00000000800001cc <test_10>: + 800001cc: 00000093 li ra,0 + 800001d0: 00000113 li sp,0 + 800001d4: 0220ef33 rem t5,ra,sp + 800001d8: 00000e93 li t4,0 + 800001dc: 00a00193 li gp,10 + 800001e0: 01df1463 bne t5,t4,800001e8 <fail> + 800001e4: 00301c63 bne zero,gp,800001fc <pass> + +00000000800001e8 <fail>: + 800001e8: 0ff0000f fence + 800001ec: 00018063 beqz gp,800001ec <fail+0x4> + 800001f0: 00119193 slli gp,gp,0x1 + 800001f4: 0011e193 ori gp,gp,1 + 800001f8: 00000073 ecall + +00000000800001fc <pass>: + 800001fc: 0ff0000f fence + 80000200: 00100193 li gp,1 + 80000204: 00000073 ecall + 80000208: c0001073 unimp + 8000020c: 0000 unimp + 8000020e: 0000 unimp + 80000210: 0000 unimp + 80000212: 0000 unimp + 80000214: 0000 unimp + 80000216: 0000 unimp + 80000218: 0000 unimp + 8000021a: 0000 unimp + 8000021c: 0000 unimp + 8000021e: 0000 unimp + 80000220: 0000 unimp + 80000222: 0000 unimp + 80000224: 0000 unimp + 80000226: 0000 unimp + 80000228: 0000 unimp + 8000022a: 0000 unimp + 8000022c: 0000 unimp + 8000022e: 0000 unimp + 80000230: 0000 unimp + 80000232: 0000 unimp + 80000234: 0000 unimp + 80000236: 0000 unimp + 80000238: 0000 unimp + 8000023a: 0000 unimp + 8000023c: 0000 unimp + 8000023e: 0000 unimp + 80000240: 0000 unimp + 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-rem.elf b/test/riscv/tests/rv64um-p-rem.elf Binary files differnew file mode 100755 index 00000000..55cc62b8 --- /dev/null +++ b/test/riscv/tests/rv64um-p-rem.elf diff --git a/test/riscv/tests/rv64um-p-remu.dump b/test/riscv/tests/rv64um-p-remu.dump new file mode 100644 index 00000000..f33af39a --- /dev/null +++ b/test/riscv/tests/rv64um-p-remu.dump @@ -0,0 +1,195 @@ + +rv64um-p-remu: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 01400093 li ra,20 + 80000100: 00600113 li sp,6 + 80000104: 0220ff33 remu t5,ra,sp + 80000108: 00200e93 li t4,2 + 8000010c: 00200193 li gp,2 + 80000110: 0ddf1e63 bne t5,t4,800001ec <fail> + +0000000080000114 <test_3>: + 80000114: fec00093 li ra,-20 + 80000118: 00600113 li sp,6 + 8000011c: 0220ff33 remu t5,ra,sp + 80000120: 00200e93 li t4,2 + 80000124: 00300193 li gp,3 + 80000128: 0ddf1263 bne t5,t4,800001ec <fail> + +000000008000012c <test_4>: + 8000012c: 01400093 li ra,20 + 80000130: ffa00113 li sp,-6 + 80000134: 0220ff33 remu t5,ra,sp + 80000138: 01400e93 li t4,20 + 8000013c: 00400193 li gp,4 + 80000140: 0bdf1663 bne t5,t4,800001ec <fail> + +0000000080000144 <test_5>: + 80000144: fec00093 li ra,-20 + 80000148: ffa00113 li sp,-6 + 8000014c: 0220ff33 remu t5,ra,sp + 80000150: fec00e93 li t4,-20 + 80000154: 00500193 li gp,5 + 80000158: 09df1a63 bne t5,t4,800001ec <fail> + +000000008000015c <test_6>: + 8000015c: fff0009b addiw ra,zero,-1 + 80000160: 03f09093 slli ra,ra,0x3f + 80000164: 00100113 li sp,1 + 80000168: 0220ff33 remu t5,ra,sp + 8000016c: 00000e93 li t4,0 + 80000170: 00600193 li gp,6 + 80000174: 07df1c63 bne t5,t4,800001ec <fail> + +0000000080000178 <test_7>: + 80000178: fff0009b addiw ra,zero,-1 + 8000017c: 03f09093 slli ra,ra,0x3f + 80000180: fff00113 li sp,-1 + 80000184: 0220ff33 remu t5,ra,sp + 80000188: fff00e9b addiw t4,zero,-1 + 8000018c: 03fe9e93 slli t4,t4,0x3f + 80000190: 00700193 li gp,7 + 80000194: 05df1c63 bne t5,t4,800001ec <fail> + +0000000080000198 <test_8>: + 80000198: fff0009b addiw ra,zero,-1 + 8000019c: 03f09093 slli ra,ra,0x3f + 800001a0: 00000113 li sp,0 + 800001a4: 0220ff33 remu t5,ra,sp + 800001a8: fff00e9b addiw t4,zero,-1 + 800001ac: 03fe9e93 slli t4,t4,0x3f + 800001b0: 00800193 li gp,8 + 800001b4: 03df1c63 bne t5,t4,800001ec <fail> + +00000000800001b8 <test_9>: + 800001b8: 00100093 li ra,1 + 800001bc: 00000113 li sp,0 + 800001c0: 0220ff33 remu t5,ra,sp + 800001c4: 00100e93 li t4,1 + 800001c8: 00900193 li gp,9 + 800001cc: 03df1063 bne t5,t4,800001ec <fail> + +00000000800001d0 <test_10>: + 800001d0: 00000093 li ra,0 + 800001d4: 00000113 li sp,0 + 800001d8: 0220ff33 remu t5,ra,sp + 800001dc: 00000e93 li t4,0 + 800001e0: 00a00193 li gp,10 + 800001e4: 01df1463 bne t5,t4,800001ec <fail> + 800001e8: 00301c63 bne zero,gp,80000200 <pass> + +00000000800001ec <fail>: + 800001ec: 0ff0000f fence + 800001f0: 00018063 beqz gp,800001f0 <fail+0x4> + 800001f4: 00119193 slli gp,gp,0x1 + 800001f8: 0011e193 ori gp,gp,1 + 800001fc: 00000073 ecall + +0000000080000200 <pass>: + 80000200: 0ff0000f fence + 80000204: 00100193 li gp,1 + 80000208: 00000073 ecall + 8000020c: c0001073 unimp + 80000210: 0000 unimp + 80000212: 0000 unimp + 80000214: 0000 unimp + 80000216: 0000 unimp + 80000218: 0000 unimp + 8000021a: 0000 unimp + 8000021c: 0000 unimp + 8000021e: 0000 unimp + 80000220: 0000 unimp + 80000222: 0000 unimp + 80000224: 0000 unimp + 80000226: 0000 unimp + 80000228: 0000 unimp + 8000022a: 0000 unimp + 8000022c: 0000 unimp + 8000022e: 0000 unimp + 80000230: 0000 unimp + 80000232: 0000 unimp + 80000234: 0000 unimp + 80000236: 0000 unimp + 80000238: 0000 unimp + 8000023a: 0000 unimp + 8000023c: 0000 unimp + 8000023e: 0000 unimp + 80000240: 0000 unimp + 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-remu.elf b/test/riscv/tests/rv64um-p-remu.elf Binary files differnew file mode 100755 index 00000000..ba6c64ac --- /dev/null +++ b/test/riscv/tests/rv64um-p-remu.elf diff --git a/test/riscv/tests/rv64um-p-remuw.dump b/test/riscv/tests/rv64um-p-remuw.dump new file mode 100644 index 00000000..43ddd98a --- /dev/null +++ b/test/riscv/tests/rv64um-p-remuw.dump @@ -0,0 +1,168 @@ + +rv64um-p-remuw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 01400093 li ra,20 + 80000100: 00600113 li sp,6 + 80000104: 0220ff3b remuw t5,ra,sp + 80000108: 00200e93 li t4,2 + 8000010c: 00200193 li gp,2 + 80000110: 0ddf1463 bne t5,t4,800001d8 <fail> + +0000000080000114 <test_3>: + 80000114: fec00093 li ra,-20 + 80000118: 00600113 li sp,6 + 8000011c: 0220ff3b remuw t5,ra,sp + 80000120: 00200e93 li t4,2 + 80000124: 00300193 li gp,3 + 80000128: 0bdf1863 bne t5,t4,800001d8 <fail> + +000000008000012c <test_4>: + 8000012c: 01400093 li ra,20 + 80000130: ffa00113 li sp,-6 + 80000134: 0220ff3b remuw t5,ra,sp + 80000138: 01400e93 li t4,20 + 8000013c: 00400193 li gp,4 + 80000140: 09df1c63 bne t5,t4,800001d8 <fail> + +0000000080000144 <test_5>: + 80000144: fec00093 li ra,-20 + 80000148: ffa00113 li sp,-6 + 8000014c: 0220ff3b remuw t5,ra,sp + 80000150: fec00e93 li t4,-20 + 80000154: 00500193 li gp,5 + 80000158: 09df1063 bne t5,t4,800001d8 <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 00100113 li sp,1 + 80000164: 0220ff3b remuw t5,ra,sp + 80000168: 00000e93 li t4,0 + 8000016c: 00600193 li gp,6 + 80000170: 07df1463 bne t5,t4,800001d8 <fail> + +0000000080000174 <test_7>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: fff00113 li sp,-1 + 8000017c: 0220ff3b remuw t5,ra,sp + 80000180: 80000eb7 lui t4,0x80000 + 80000184: 00700193 li gp,7 + 80000188: 05df1863 bne t5,t4,800001d8 <fail> + +000000008000018c <test_8>: + 8000018c: 800000b7 lui ra,0x80000 + 80000190: 00000113 li sp,0 + 80000194: 0220ff3b remuw t5,ra,sp + 80000198: 80000eb7 lui t4,0x80000 + 8000019c: 00800193 li gp,8 + 800001a0: 03df1c63 bne t5,t4,800001d8 <fail> + +00000000800001a4 <test_9>: + 800001a4: 00100093 li ra,1 + 800001a8: 00000113 li sp,0 + 800001ac: 0220ff3b remuw t5,ra,sp + 800001b0: 00100e93 li t4,1 + 800001b4: 00900193 li gp,9 + 800001b8: 03df1063 bne t5,t4,800001d8 <fail> + +00000000800001bc <test_10>: + 800001bc: 00000093 li ra,0 + 800001c0: 00000113 li sp,0 + 800001c4: 0220ff3b remuw t5,ra,sp + 800001c8: 00000e93 li t4,0 + 800001cc: 00a00193 li gp,10 + 800001d0: 01df1463 bne t5,t4,800001d8 <fail> + 800001d4: 00301c63 bne zero,gp,800001ec <pass> + +00000000800001d8 <fail>: + 800001d8: 0ff0000f fence + 800001dc: 00018063 beqz gp,800001dc <fail+0x4> + 800001e0: 00119193 slli gp,gp,0x1 + 800001e4: 0011e193 ori gp,gp,1 + 800001e8: 00000073 ecall + +00000000800001ec <pass>: + 800001ec: 0ff0000f fence + 800001f0: 00100193 li gp,1 + 800001f4: 00000073 ecall + 800001f8: c0001073 unimp + 800001fc: 0000 unimp + 800001fe: 0000 unimp + 80000200: 0000 unimp + 80000202: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-remuw.elf b/test/riscv/tests/rv64um-p-remuw.elf Binary files differnew file mode 100755 index 00000000..86cf837c --- /dev/null +++ b/test/riscv/tests/rv64um-p-remuw.elf diff --git a/test/riscv/tests/rv64um-p-remw.dump b/test/riscv/tests/rv64um-p-remw.dump new file mode 100644 index 00000000..48fcac9f --- /dev/null +++ b/test/riscv/tests/rv64um-p-remw.dump @@ -0,0 +1,196 @@ + +rv64um-p-remw: file format elf64-littleriscv + + +Disassembly of section .text.init: + +0000000080000000 <_start>: + 80000000: 04c0006f j 8000004c <reset_vector> + +0000000080000004 <trap_vector>: + 80000004: 34202f73 csrr t5,mcause + 80000008: 00800f93 li t6,8 + 8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost> + 80000010: 00900f93 li t6,9 + 80000014: 03ff0663 beq t5,t6,80000040 <write_tohost> + 80000018: 00b00f93 li t6,11 + 8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost> + 80000020: 80000f17 auipc t5,0x80000 + 80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000> + 80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c> + 8000002c: 000f0067 jr t5 + 80000030: 34202f73 csrr t5,mcause + 80000034: 000f5463 bgez t5,8000003c <handle_exception> + 80000038: 0040006f j 8000003c <handle_exception> + +000000008000003c <handle_exception>: + 8000003c: 5391e193 ori gp,gp,1337 + +0000000080000040 <write_tohost>: + 80000040: 00001f17 auipc t5,0x1 + 80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost> + 80000048: ff9ff06f j 80000040 <write_tohost> + +000000008000004c <reset_vector>: + 8000004c: f1402573 csrr a0,mhartid + 80000050: 00051063 bnez a0,80000050 <reset_vector+0x4> + 80000054: 00000297 auipc t0,0x0 + 80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18> + 8000005c: 30529073 csrw mtvec,t0 + 80000060: 18005073 csrwi satp,0 + 80000064: 00000297 auipc t0,0x0 + 80000068: 01c28293 addi t0,t0,28 # 80000080 <reset_vector+0x34> + 8000006c: 30529073 csrw mtvec,t0 + 80000070: fff00293 li t0,-1 + 80000074: 3b029073 csrw pmpaddr0,t0 + 80000078: 01f00293 li t0,31 + 8000007c: 3a029073 csrw pmpcfg0,t0 + 80000080: 00000297 auipc t0,0x0 + 80000084: 01828293 addi t0,t0,24 # 80000098 <reset_vector+0x4c> + 80000088: 30529073 csrw mtvec,t0 + 8000008c: 30205073 csrwi medeleg,0 + 80000090: 30305073 csrwi mideleg,0 + 80000094: 30405073 csrwi mie,0 + 80000098: 00000193 li gp,0 + 8000009c: 00000297 auipc t0,0x0 + 800000a0: f6828293 addi t0,t0,-152 # 80000004 <trap_vector> + 800000a4: 30529073 csrw mtvec,t0 + 800000a8: 00100513 li a0,1 + 800000ac: 01f51513 slli a0,a0,0x1f + 800000b0: 00055863 bgez a0,800000c0 <reset_vector+0x74> + 800000b4: 0ff0000f fence + 800000b8: 00100193 li gp,1 + 800000bc: 00000073 ecall + 800000c0: 80000297 auipc t0,0x80000 + 800000c4: f4028293 addi t0,t0,-192 # 0 <_start-0x80000000> + 800000c8: 00028e63 beqz t0,800000e4 <reset_vector+0x98> + 800000cc: 10529073 csrw stvec,t0 + 800000d0: 0000b2b7 lui t0,0xb + 800000d4: 1092829b addiw t0,t0,265 + 800000d8: 30229073 csrw medeleg,t0 + 800000dc: 30202373 csrr t1,medeleg + 800000e0: f4629ee3 bne t0,t1,8000003c <handle_exception> + 800000e4: 30005073 csrwi mstatus,0 + 800000e8: 00000297 auipc t0,0x0 + 800000ec: 01428293 addi t0,t0,20 # 800000fc <test_2> + 800000f0: 34129073 csrw mepc,t0 + 800000f4: f1402573 csrr a0,mhartid + 800000f8: 30200073 mret + +00000000800000fc <test_2>: + 800000fc: 01400093 li ra,20 + 80000100: 00600113 li sp,6 + 80000104: 0220ef3b remw t5,ra,sp + 80000108: 00200e93 li t4,2 + 8000010c: 00200193 li gp,2 + 80000110: 0fdf1063 bne t5,t4,800001f0 <fail> + +0000000080000114 <test_3>: + 80000114: fec00093 li ra,-20 + 80000118: 00600113 li sp,6 + 8000011c: 0220ef3b remw t5,ra,sp + 80000120: ffe00e93 li t4,-2 + 80000124: 00300193 li gp,3 + 80000128: 0ddf1463 bne t5,t4,800001f0 <fail> + +000000008000012c <test_4>: + 8000012c: 01400093 li ra,20 + 80000130: ffa00113 li sp,-6 + 80000134: 0220ef3b remw t5,ra,sp + 80000138: 00200e93 li t4,2 + 8000013c: 00400193 li gp,4 + 80000140: 0bdf1863 bne t5,t4,800001f0 <fail> + +0000000080000144 <test_5>: + 80000144: fec00093 li ra,-20 + 80000148: ffa00113 li sp,-6 + 8000014c: 0220ef3b remw t5,ra,sp + 80000150: ffe00e93 li t4,-2 + 80000154: 00500193 li gp,5 + 80000158: 09df1c63 bne t5,t4,800001f0 <fail> + +000000008000015c <test_6>: + 8000015c: 800000b7 lui ra,0x80000 + 80000160: 00100113 li sp,1 + 80000164: 0220ef3b remw t5,ra,sp + 80000168: 00000e93 li t4,0 + 8000016c: 00600193 li gp,6 + 80000170: 09df1063 bne t5,t4,800001f0 <fail> + +0000000080000174 <test_7>: + 80000174: 800000b7 lui ra,0x80000 + 80000178: fff00113 li sp,-1 + 8000017c: 0220ef3b remw t5,ra,sp + 80000180: 00000e93 li t4,0 + 80000184: 00700193 li gp,7 + 80000188: 07df1463 bne t5,t4,800001f0 <fail> + +000000008000018c <test_8>: + 8000018c: 800000b7 lui ra,0x80000 + 80000190: 00000113 li sp,0 + 80000194: 0220ef3b remw t5,ra,sp + 80000198: 80000eb7 lui t4,0x80000 + 8000019c: 00800193 li gp,8 + 800001a0: 05df1863 bne t5,t4,800001f0 <fail> + +00000000800001a4 <test_9>: + 800001a4: 00100093 li ra,1 + 800001a8: 00000113 li sp,0 + 800001ac: 0220ef3b remw t5,ra,sp + 800001b0: 00100e93 li t4,1 + 800001b4: 00900193 li gp,9 + 800001b8: 03df1c63 bne t5,t4,800001f0 <fail> + +00000000800001bc <test_10>: + 800001bc: 00000093 li ra,0 + 800001c0: 00000113 li sp,0 + 800001c4: 0220ef3b remw t5,ra,sp + 800001c8: 00000e93 li t4,0 + 800001cc: 00a00193 li gp,10 + 800001d0: 03df1063 bne t5,t4,800001f0 <fail> + +00000000800001d4 <test_11>: + 800001d4: 89700093 li ra,-1897 + 800001d8: 00000113 li sp,0 + 800001dc: 0220ef3b remw t5,ra,sp + 800001e0: 89700e93 li t4,-1897 + 800001e4: 00b00193 li gp,11 + 800001e8: 01df1463 bne t5,t4,800001f0 <fail> + 800001ec: 00301c63 bne zero,gp,80000204 <pass> + +00000000800001f0 <fail>: + 800001f0: 0ff0000f fence + 800001f4: 00018063 beqz gp,800001f4 <fail+0x4> + 800001f8: 00119193 slli gp,gp,0x1 + 800001fc: 0011e193 ori gp,gp,1 + 80000200: 00000073 ecall + +0000000080000204 <pass>: + 80000204: 0ff0000f fence + 80000208: 00100193 li gp,1 + 8000020c: 00000073 ecall + 80000210: c0001073 unimp + 80000214: 0000 unimp + 80000216: 0000 unimp + 80000218: 0000 unimp + 8000021a: 0000 unimp + 8000021c: 0000 unimp + 8000021e: 0000 unimp + 80000220: 0000 unimp + 80000222: 0000 unimp + 80000224: 0000 unimp + 80000226: 0000 unimp + 80000228: 0000 unimp + 8000022a: 0000 unimp + 8000022c: 0000 unimp + 8000022e: 0000 unimp + 80000230: 0000 unimp + 80000232: 0000 unimp + 80000234: 0000 unimp + 80000236: 0000 unimp + 80000238: 0000 unimp + 8000023a: 0000 unimp + 8000023c: 0000 unimp + 8000023e: 0000 unimp + 80000240: 0000 unimp + 80000242: 0000 unimp diff --git a/test/riscv/tests/rv64um-p-remw.elf b/test/riscv/tests/rv64um-p-remw.elf Binary files differnew file mode 100755 index 00000000..4ef57f28 --- /dev/null +++ b/test/riscv/tests/rv64um-p-remw.elf diff --git a/test/typecheck/pass/arm_types.sail b/test/typecheck/pass/arm_types.sail index 83cc8687..af0bcba9 100644 --- a/test/typecheck/pass/arm_types.sail +++ b/test/typecheck/pass/arm_types.sail @@ -1,3 +1,5 @@ +$include <flow.sail> + enum boolean = {FALSE, TRUE} enum signal = {LOW, HIGH} diff --git a/test/typecheck/pass/decode_patterns.sail b/test/typecheck/pass/decode_patterns.sail new file mode 100644 index 00000000..d8b17f5b --- /dev/null +++ b/test/typecheck/pass/decode_patterns.sail @@ -0,0 +1,47 @@ +$include <flow.sail> + +default Order dec + +type bits ('n : Int) = vector('n, dec, bit) + +val eq_anything = "eq" : forall ('a : Type). ('a, 'a) -> bool + +overload operator == = {eq_anything} + +val vector_subrange = {ocaml: "subrange", lem: "subrange_vec_dec"} : forall ('n : Int) ('m : Int) ('o : Int), 'o <= 'm <= 'n. + (bits('n), atom('m), atom('o)) -> bits('m - ('o - 1)) + +val vector_access = {ocaml: "access", lem: "access_vec_dec"} : forall ('n : Int) ('m : Int), 0 <= 'm < 'n. + (bits('n), atom('m)) -> bit + +val decode : vector(16, dec, bit) -> unit + +scattered function decode + +function clause decode 0x00 @ 0b000 @ _ : bits(1) @ 0x0 as op_code = + if op_code[5 .. 5] == 0b0 then { + () + } else { + () + } + +function clause decode 0x00 @ 0b001 @ [b : bit] @ 0x0 = + if b == bitone then { + () + } else { + () + } + +end decode + +val decode2 : vector(16, dec, bit) -> unit + +function decode2 x = + match x { + 0x00 @ 0b000 @ [b : bit] @ 0x0 => + if b == bitone then { + () + } else { + () + } + } diff --git a/test/typecheck/pass/exist_tlb.sail b/test/typecheck/pass/exist_tlb.sail index f1b79b3d..de15edf8 100644 --- a/test/typecheck/pass/exist_tlb.sail +++ b/test/typecheck/pass/exist_tlb.sail @@ -1,3 +1,5 @@ +$include <flow.sail> + val extz : forall ('n : Int) ('m : Int) ('ord : Order). vector('n, 'ord, bit) -> vector('m, 'ord, bit) diff --git a/test/typecheck/pass/function_namespace.sail b/test/typecheck/pass/function_namespace.sail new file mode 100644 index 00000000..1e79f051 --- /dev/null +++ b/test/typecheck/pass/function_namespace.sail @@ -0,0 +1,11 @@ + +val test : bool -> unit + +function test _ = () + +val main: unit -> unit + +function main _ = { + let test2 = true; + test(test2) +} diff --git a/test/typecheck/pass/function_namespace/v1.expect b/test/typecheck/pass/function_namespace/v1.expect new file mode 100644 index 00000000..d01c3adb --- /dev/null +++ b/test/typecheck/pass/function_namespace/v1.expect @@ -0,0 +1,5 @@ +Type error at file "function_namespace/v1.sail", line 9, character 7 to line 9, character 10 + + let [41mtest[49m = true; + +Local variable test is already bound as a function name diff --git a/test/typecheck/pass/function_namespace/v1.sail b/test/typecheck/pass/function_namespace/v1.sail new file mode 100644 index 00000000..a72dcc11 --- /dev/null +++ b/test/typecheck/pass/function_namespace/v1.sail @@ -0,0 +1,11 @@ + +val test : bool -> unit + +function test _ = () + +val main: unit -> unit + +function main _ = { + let test = true; + test(test) +} diff --git a/test/typecheck/pass/global_type_var.sail b/test/typecheck/pass/global_type_var.sail new file mode 100644 index 00000000..215907b4 --- /dev/null +++ b/test/typecheck/pass/global_type_var.sail @@ -0,0 +1,21 @@ +$include <flow.sail> + +overload operator == = {eq_atom} + +let (size as 'size) : {|32, 64|} = 32 + +val zeros : forall 'n. atom('n) -> vector ('n, dec, bit) + +val test : atom('size) -> unit + +function test x = + if x == 32 then { + () + } else { + let y : atom(64) = size in + () + } + +val test2 : unit -> atom('size) + +function test2 () = size diff --git a/test/typecheck/pass/global_type_var/v1.expect b/test/typecheck/pass/global_type_var/v1.expect new file mode 100644 index 00000000..67355f59 --- /dev/null +++ b/test/typecheck/pass/global_type_var/v1.expect @@ -0,0 +1,6 @@ +Type error at file "global_type_var/v1.sail", line 23, character 14 to line 23, character 15 + +let _ = test([41m32[49m) + +Tried performing type coercion on 32 +Failed because atom<32> is not a subtype of atom<'size> in context ('size = 32 | 'size = 64) diff --git a/test/typecheck/pass/global_type_var/v1.sail b/test/typecheck/pass/global_type_var/v1.sail new file mode 100644 index 00000000..f2b2f89a --- /dev/null +++ b/test/typecheck/pass/global_type_var/v1.sail @@ -0,0 +1,23 @@ +$include <flow.sail> + +overload operator == = {eq_atom} + +let (size as 'size) : {|32, 64|} = 32 + +val zeros : forall 'n. atom('n) -> vector ('n, dec, bit) + +val test : atom('size) -> unit + +function test x = + if x == 32 then { + () + } else { + let y : atom(64) = size in + () + } + +val test2 : unit -> atom('size) + +function test2 () = size + +let _ = test(32)
\ No newline at end of file diff --git a/test/typecheck/pass/global_type_var/v2.expect b/test/typecheck/pass/global_type_var/v2.expect new file mode 100644 index 00000000..fb31fbed --- /dev/null +++ b/test/typecheck/pass/global_type_var/v2.expect @@ -0,0 +1,6 @@ +Type error at file "global_type_var/v2.sail", line 23, character 14 to line 23, character 15 + +let _ = test([41m64[49m) + +Tried performing type coercion on 64 +Failed because atom<64> is not a subtype of atom<'size> in context ('size = 32 | 'size = 64) diff --git a/test/typecheck/pass/global_type_var/v2.sail b/test/typecheck/pass/global_type_var/v2.sail new file mode 100644 index 00000000..e8340978 --- /dev/null +++ b/test/typecheck/pass/global_type_var/v2.sail @@ -0,0 +1,23 @@ +$include <flow.sail> + +overload operator == = {eq_atom} + +let (size as 'size) : {|32, 64|} = 32 + +val zeros : forall 'n. atom('n) -> vector ('n, dec, bit) + +val test : atom('size) -> unit + +function test x = + if x == 32 then { + () + } else { + let y : atom(64) = size in + () + } + +val test2 : unit -> atom('size) + +function test2 () = size + +let _ = test(64)
\ No newline at end of file diff --git a/test/typecheck/pass/global_type_var/v3.expect b/test/typecheck/pass/global_type_var/v3.expect new file mode 100644 index 00000000..a01f3eec --- /dev/null +++ b/test/typecheck/pass/global_type_var/v3.expect @@ -0,0 +1,5 @@ +Type error at file "global_type_var/v3.sail", line 9, character 19 to line 9, character 23 + +val test : forall [41m'size[49m. atom('size) -> unit + +Kind identifier 'size is already bound diff --git a/test/typecheck/pass/global_type_var/v3.sail b/test/typecheck/pass/global_type_var/v3.sail new file mode 100644 index 00000000..274490ff --- /dev/null +++ b/test/typecheck/pass/global_type_var/v3.sail @@ -0,0 +1,21 @@ +$include <flow.sail> + +overload operator == = {eq_atom} + +let (size as 'size) : {|32, 64|} = 32 + +val zeros : forall 'n. atom('n) -> vector ('n, dec, bit) + +val test : forall 'size. atom('size) -> unit + +function test x = + if x == 32 then { + () + } else { + let y : atom(64) = size in + () + } + +val test2 : unit -> atom('size) + +function test2 () = size diff --git a/test/typecheck/pass/simple_record_access.sail b/test/typecheck/pass/simple_record_access.sail index b1eab652..a6e34c8b 100644 --- a/test/typecheck/pass/simple_record_access.sail +++ b/test/typecheck/pass/simple_record_access.sail @@ -1,3 +1,5 @@ +$include <flow.sail> + enum signal = {LOW, HIGH} type Bit32 = vector(32, inc, bit) |
