diff options
| -rw-r--r-- | riscv/main.sail | 2 | ||||
| -rw-r--r-- | riscv/riscv.sail | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/riscv/main.sail b/riscv/main.sail index 43820e25..8accaf5b 100644 --- a/riscv/main.sail +++ b/riscv/main.sail @@ -43,6 +43,8 @@ function main () = { print(assembly(assembly("ldu.aq zero, zero, 0x0"))); print_bits("assembled lui zero, 0x0: ", encdec(assembly("lui zero, 0x0"))); print_bits("assembled jal zero, 0x123456 : ", encdec(assembly("jal zero, 0x123456"))); + print(assembly(assembly("beq zero, zero, 0x124"))); + print_bits("assembled beq zero, zero, 0x124 : ", encdec(assembly("beq zero, zero, 0x124"))); /*PC = __GetSlice_int(64, elf_entry(), 0); try { init_sys (); diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 6ede17b1..84f0f279 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -149,7 +149,7 @@ mapping btype_mnemonic = { RISCV_BGEU <-> "bgeu" } -mapping clause assembly = BTYPE(imm, rs2, rs1, op) <-> btype_mnemonic(op) ^^ spaces() ^^ reg_name(rs1) ^^ operand_sep() ^^ reg_name(rs2) ^^ operand_sep() ^^ hex_bits_13(imm) +mapping clause assembly = BTYPE(imm, rs2, rs1, op) <-> btype_mnemonic(op) ^^ spaces() ^^ reg_name(rs1) ^^ operand_sep() ^^ reg_name(rs2) ^^ operand_sep() ^^ hex_bits_13(imm) /* ****************************************************************** */ |