diff options
| -rw-r--r-- | cheri/cheri_prelude.sail | 4 | ||||
| -rw-r--r-- | mips/mips_wrappers.sail | 5 |
2 files changed, 7 insertions, 2 deletions
diff --git a/cheri/cheri_prelude.sail b/cheri/cheri_prelude.sail index 8fa3b180..7853caad 100644 --- a/cheri/cheri_prelude.sail +++ b/cheri/cheri_prelude.sail @@ -412,7 +412,9 @@ function (bit[64]) TranslateAddress ((bit[64]) vAddr, (MemAccessType) accessType let (bit[64]) base = x[127..64] in let (bit[64]) length = x[63..0] in let (bit[64]) absPC = (base + vAddr) in - if ((unsigned(vAddr) + 4) > unsigned(length)) then + if (absPC[1..0] != 0b00) then (* bad PC alignment *) + exit (SignalExceptionBadAddr(AdEL, absPC)) + else if ((unsigned(vAddr) + 4) > unsigned(length)) then exit (raise_c2_exception_noreg(CapEx_LengthViolation)) (* XXX take exception properly *) else TLBTranslate(absPC, accessType) diff --git a/mips/mips_wrappers.sail b/mips/mips_wrappers.sail index 8fe1b4d4..25b8936b 100644 --- a/mips/mips_wrappers.sail +++ b/mips/mips_wrappers.sail @@ -6,7 +6,10 @@ function bit[64] addrWrapper((bit[64]) addr, (MemAccessType) accessType, (WordTy addr function (bit[64]) TranslateAddress ((bit[64]) vAddr, (MemAccessType) accessType) = - TLBTranslate(vAddr, accessType) + if (vAddr[1..0] != 0b00) then (* bad PC alignment *) + exit (SignalExceptionBadAddr(AdEL, vAddr)) + else + TLBTranslate(vAddr, accessType) function unit SignalException ((Exception) ex) = SignalExceptionMIPS(ex) |