diff options
38 files changed, 30186 insertions, 11483 deletions
diff --git a/snapshots/isabelle/aarch64/Aarch64.thy b/snapshots/isabelle/aarch64/Aarch64.thy index a117b761..c63ed15e 100644 --- a/snapshots/isabelle/aarch64/Aarch64.thy +++ b/snapshots/isabelle/aarch64/Aarch64.thy @@ -5,25 +5,25 @@ theory "Aarch64" imports Main "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" - "Sail_operators_mwords" - "Prompt_monad" - "Prompt" - "State" + "/tmp/sail/src/lem_interp/Sail2_instr_kinds" + "/tmp/sail/src/gen_lib/Sail2_values" + "/tmp/sail/src/gen_lib/Sail2_operators_mwords" + "/tmp/sail/src/gen_lib/Sail2_prompt_monad" + "/tmp/sail/src/gen_lib/Sail2_prompt" + "/tmp/sail/src/gen_lib/Sail2_string" "Aarch64_types" - "Aarch64_extras" + "/tmp/sail/aarch64/mono/Aarch64_extras" begin (*Generated by Sail from aarch64.*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) -(*open import State*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) (*open import Aarch64_types*) (*open import Aarch64_extras*) @@ -60,7 +60,7 @@ definition neq_bool :: " bool \<Rightarrow> bool \<Rightarrow> bool " where definition GetSlice_int :: "('n::len)itself \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where " GetSlice_int n m o1 = ( (let n = (size_itself_int n) in - (get_slice_int0 n m o1 :: ( 'n::len)Word.word)))" + (get_slice_int n m o1 :: ( 'n::len)Word.word)))" (*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*) @@ -74,19 +74,11 @@ fun cast_unit_vec0 :: " bitU \<Rightarrow>(1)Word.word " where |" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))" -(*val DecStr : ii -> string*) +(*val BoolStr : bool -> string*) -(*val HexStr : ii -> string*) +definition BoolStr :: " bool \<Rightarrow> string " where + " BoolStr b = ( if b then (''true'') else (''false''))" -(*val __TraceMemoryWrite : forall 'm 'p8_times_n_ . integer -> bits 'm -> bits 'p8_times_n_ -> unit*) - -(*val __InitRAM : forall 'm. Size 'm => integer -> ii -> mword 'm -> mword ty8 -> unit*) - -definition InitRAM :: " int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> unit " where - " InitRAM g__615 g__616 g__617 g__618 = ( () )" - - -(*val __TraceMemoryRead : forall 'm 'p8_times_n_ . integer -> bits 'm -> bits 'p8_times_n_ -> unit*) (*val ex_nat : ii -> integer*) @@ -118,13 +110,48 @@ definition break :: " unit \<Rightarrow> unit " where definition undefined_exception :: " unit \<Rightarrow>((register_value),(exception),(exception))monad " where " undefined_exception _ = ( - (undefined_unit () \<then> - undefined_string () ) \<bind> (\<lambda> (w__0 :: string) . - undefined_string () \<bind> (\<lambda> (w__1 :: string) . - (undefined_unit () \<then> - undefined_unit () ) \<then> + undefined_string () \<bind> (\<lambda> (u_0 :: string) . + undefined_unit () \<bind> (\<lambda> (u_1 :: unit) . internal_pick - [Error_Undefined () ,Error_See w__0,Error_Implementation_Defined w__1,Error_ReservedEncoding () ,Error_ExceptionTaken () ])))" + [Error_Undefined u_1,Error_See u_0,Error_Implementation_Defined u_0,Error_ReservedEncoding u_1,Error_ExceptionTaken u_1])))" + + +(*val __GetVerbosity : unit -> M (bits ty64)*) + +(*val get_cycle_count : unit -> M ii*) + +(*val __InitRAM : forall 'm. Size 'm => integer -> ii -> mword 'm -> mword ty8 -> unit*) + +definition InitRAM :: " int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> unit " where + " InitRAM g__302 g__303 g__304 g__305 = ( () )" + + +(*val __ReadRAM : forall 'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => itself 'm -> integer -> mword 'm -> mword 'm -> M (mword 'p8_times_n_)*) + +definition ReadRAM :: "('m::len)itself \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow>('m::len)Word.word \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where + " ReadRAM addr_length bytes hex_ram addr = ( + (let addr_length = (size_itself_int addr_length) in + (read_ram addr_length bytes hex_ram addr :: (( 'p8_times_n_::len)Word.word) M)))" + + +(*val __TraceMemoryWrite : forall 'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => integer -> mword 'm -> mword 'p8_times_n_ -> unit*) + +(*val __WriteRAM : forall 'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => itself 'm -> integer -> mword 'm -> mword 'm -> mword 'p8_times_n_ -> M unit*) + +definition WriteRAM :: "('m::len)itself \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow>('m::len)Word.word \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " WriteRAM addr_length bytes hex_ram addr data = ( + (let addr_length = (size_itself_int addr_length) in + write_ram addr_length bytes hex_ram addr data))" + + +definition TraceMemoryWrite :: " int \<Rightarrow>('m::len)Word.word \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow> unit " where + " TraceMemoryWrite bytes addr data = ( () )" + + +(*val __TraceMemoryRead : forall 'm 'p8_times_n_ . Size 'm, Size 'p8_times_n_ => integer -> mword 'm -> mword 'p8_times_n_ -> unit*) + +definition TraceMemoryRead :: " int \<Rightarrow>('m::len)Word.word \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow> unit " where + " TraceMemoryRead bytes addr data = ( () )" (*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) @@ -151,14 +178,17 @@ definition slice_mask :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow definition is_zero_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where " is_zero_subrange xs i j = ( - (((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0] :: 1 Word.word) :: ( 'n::len)Word.word))))" + (((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0] :: 1 Word.word) :: ( 'n::len)Word.word))))" (*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) definition is_ones_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where " is_ones_subrange xs i j = ( - (let (m :: 'n bits) = ((slice_mask ((int (size xs))) j ((j - i)) :: ( 'n::len)Word.word)) in + (let (m :: 'n bits) = + ((slice_mask ((int (size xs))) j ((((j - i)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) in (((and_vec xs m :: ( 'n::len)Word.word)) = m)))" @@ -190,12 +220,15 @@ definition subrange_subrange_eq :: "('n::len)Word.word \<Rightarrow> int \<Righ " subrange_subrange_eq xs i j ys i' j' = ( (let xs = ((shiftr - ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + ((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) j :: ( 'n::len)Word.word)) in (let ys = ((shiftr - ((and_vec ys ((slice_mask ((int (size xs))) j' ((i' - j')) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) - j' + ((and_vec ys + ((slice_mask ((int (size xs))) j' ((((i' - j')) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) j' :: ( 'n::len)Word.word)) in (xs = ys))))" @@ -206,16 +239,18 @@ definition subrange_subrange_concat :: " int \<Rightarrow>('n::len)Word.word \< " subrange_subrange_concat (s__tv :: int) xs i j ys i' j' = ( (let xs = ((shiftr - ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + ((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) j :: ( 'n::len)Word.word)) in (let ys = ((shiftr - ((and_vec ys ((slice_mask ((int (size ys))) j' ((i' - j')) :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) - j' + ((and_vec ys + ((slice_mask ((int (size ys))) j' ((((i' - j')) + (( 1 :: int)::ii))) :: ( 'm::len)Word.word)) + :: ( 'm::len)Word.word)) j' :: ( 'm::len)Word.word)) in (or_vec - ((sub_vec_int ((shiftl ((extzv s__tv xs :: ( 's::len)Word.word)) i' :: ( 's::len)Word.word)) - ((j' - (( 1 :: int)::ii))) + ((shiftl ((extzv s__tv xs :: ( 's::len)Word.word)) ((((i' - j')) + (( 1 :: int)::ii))) :: ( 's::len)Word.word)) ((extzv s__tv ys :: ( 's::len)Word.word)) :: ( 's::len)Word.word))))" @@ -226,7 +261,9 @@ definition place_subrange :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow " place_subrange (m__tv :: int) xs i j shift = ( (let xs = ((shiftr - ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + ((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) j :: ( 'n::len)Word.word)) in (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" @@ -277,7 +314,9 @@ definition unsigned_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightar " unsigned_subrange xs i j = ( (let xs = ((shiftr - ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i + ((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in Word.uint xs))" @@ -294,8 +333,8 @@ definition zext_ones :: " int \<Rightarrow> int \<Rightarrow>('n::len)Word.word definition boolean_of_num :: " int \<Rightarrow> boolean " where " boolean_of_num arg0 = ( - (let l__595 = arg0 in - if (((l__595 = (( 0 :: int)::ii)))) then FALSE + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then FALSE else TRUE))" @@ -316,8 +355,8 @@ definition undefined_boolean :: " unit \<Rightarrow>((register_value),(boolean) definition signal_of_num :: " int \<Rightarrow> signal " where " signal_of_num arg0 = ( - (let l__594 = arg0 in - if (((l__594 = (( 0 :: int)::ii)))) then LOW + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then LOW else HIGH))" @@ -338,15 +377,15 @@ definition undefined_signal :: " unit \<Rightarrow>((register_value),(signal),( definition RetCode_of_num :: " int \<Rightarrow> RetCode " where " RetCode_of_num arg0 = ( - (let l__586 = arg0 in - if (((l__586 = (( 0 :: int)::ii)))) then RC_OK - else if (((l__586 = (( 1 :: int)::ii)))) then RC_UNDEFINED - else if (((l__586 = (( 2 :: int)::ii)))) then RC_UNPREDICTABLE - else if (((l__586 = (( 3 :: int)::ii)))) then RC_SEE - else if (((l__586 = (( 4 :: int)::ii)))) then RC_IMPLEMENTATION_DEFINED - else if (((l__586 = (( 5 :: int)::ii)))) then RC_SUBARCHITECTURE_DEFINED - else if (((l__586 = (( 6 :: int)::ii)))) then RC_EXCEPTION_TAKEN - else if (((l__586 = (( 7 :: int)::ii)))) then RC_ASSERT_FAILED + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then RC_OK + else if (((p00 = (( 1 :: int)::ii)))) then RC_UNDEFINED + else if (((p00 = (( 2 :: int)::ii)))) then RC_UNPREDICTABLE + else if (((p00 = (( 3 :: int)::ii)))) then RC_SEE + else if (((p00 = (( 4 :: int)::ii)))) then RC_IMPLEMENTATION_DEFINED + else if (((p00 = (( 5 :: int)::ii)))) then RC_SUBARCHITECTURE_DEFINED + else if (((p00 = (( 6 :: int)::ii)))) then RC_EXCEPTION_TAKEN + else if (((p00 = (( 7 :: int)::ii)))) then RC_ASSERT_FAILED else RC_UNMATCHED_CASE))" @@ -376,11 +415,11 @@ definition undefined___RetCode :: " unit \<Rightarrow>((register_value),(RetCod definition FPConvOp_of_num :: " int \<Rightarrow> FPConvOp " where " FPConvOp_of_num arg0 = ( - (let l__582 = arg0 in - if (((l__582 = (( 0 :: int)::ii)))) then FPConvOp_CVT_FtoI - else if (((l__582 = (( 1 :: int)::ii)))) then FPConvOp_CVT_ItoF - else if (((l__582 = (( 2 :: int)::ii)))) then FPConvOp_MOV_FtoI - else if (((l__582 = (( 3 :: int)::ii)))) then FPConvOp_MOV_ItoF + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then FPConvOp_CVT_FtoI + else if (((p00 = (( 1 :: int)::ii)))) then FPConvOp_CVT_ItoF + else if (((p00 = (( 2 :: int)::ii)))) then FPConvOp_MOV_FtoI + else if (((p00 = (( 3 :: int)::ii)))) then FPConvOp_MOV_ItoF else FPConvOp_CVT_FtoI_JS))" @@ -406,35 +445,35 @@ definition undefined_FPConvOp :: " unit \<Rightarrow>((register_value),(FPConvO definition Exception_of_num :: " int \<Rightarrow> Exception " where " Exception_of_num arg0 = ( - (let l__554 = arg0 in - if (((l__554 = (( 0 :: int)::ii)))) then Exception_Uncategorized - else if (((l__554 = (( 1 :: int)::ii)))) then Exception_WFxTrap - else if (((l__554 = (( 2 :: int)::ii)))) then Exception_CP15RTTrap - else if (((l__554 = (( 3 :: int)::ii)))) then Exception_CP15RRTTrap - else if (((l__554 = (( 4 :: int)::ii)))) then Exception_CP14RTTrap - else if (((l__554 = (( 5 :: int)::ii)))) then Exception_CP14DTTrap - else if (((l__554 = (( 6 :: int)::ii)))) then Exception_AdvSIMDFPAccessTrap - else if (((l__554 = (( 7 :: int)::ii)))) then Exception_FPIDTrap - else if (((l__554 = (( 8 :: int)::ii)))) then Exception_PACTrap - else if (((l__554 = (( 9 :: int)::ii)))) then Exception_CP14RRTTrap - else if (((l__554 = (( 10 :: int)::ii)))) then Exception_IllegalState - else if (((l__554 = (( 11 :: int)::ii)))) then Exception_SupervisorCall - else if (((l__554 = (( 12 :: int)::ii)))) then Exception_HypervisorCall - else if (((l__554 = (( 13 :: int)::ii)))) then Exception_MonitorCall - else if (((l__554 = (( 14 :: int)::ii)))) then Exception_SystemRegisterTrap - else if (((l__554 = (( 15 :: int)::ii)))) then Exception_ERetTrap - else if (((l__554 = (( 16 :: int)::ii)))) then Exception_InstructionAbort - else if (((l__554 = (( 17 :: int)::ii)))) then Exception_PCAlignment - else if (((l__554 = (( 18 :: int)::ii)))) then Exception_DataAbort - else if (((l__554 = (( 19 :: int)::ii)))) then Exception_SPAlignment - else if (((l__554 = (( 20 :: int)::ii)))) then Exception_FPTrappedException - else if (((l__554 = (( 21 :: int)::ii)))) then Exception_SError - else if (((l__554 = (( 22 :: int)::ii)))) then Exception_Breakpoint - else if (((l__554 = (( 23 :: int)::ii)))) then Exception_SoftwareStep - else if (((l__554 = (( 24 :: int)::ii)))) then Exception_Watchpoint - else if (((l__554 = (( 25 :: int)::ii)))) then Exception_SoftwareBreakpoint - else if (((l__554 = (( 26 :: int)::ii)))) then Exception_VectorCatch - else if (((l__554 = (( 27 :: int)::ii)))) then Exception_IRQ + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Exception_Uncategorized + else if (((p00 = (( 1 :: int)::ii)))) then Exception_WFxTrap + else if (((p00 = (( 2 :: int)::ii)))) then Exception_CP15RTTrap + else if (((p00 = (( 3 :: int)::ii)))) then Exception_CP15RRTTrap + else if (((p00 = (( 4 :: int)::ii)))) then Exception_CP14RTTrap + else if (((p00 = (( 5 :: int)::ii)))) then Exception_CP14DTTrap + else if (((p00 = (( 6 :: int)::ii)))) then Exception_AdvSIMDFPAccessTrap + else if (((p00 = (( 7 :: int)::ii)))) then Exception_FPIDTrap + else if (((p00 = (( 8 :: int)::ii)))) then Exception_PACTrap + else if (((p00 = (( 9 :: int)::ii)))) then Exception_CP14RRTTrap + else if (((p00 = (( 10 :: int)::ii)))) then Exception_IllegalState + else if (((p00 = (( 11 :: int)::ii)))) then Exception_SupervisorCall + else if (((p00 = (( 12 :: int)::ii)))) then Exception_HypervisorCall + else if (((p00 = (( 13 :: int)::ii)))) then Exception_MonitorCall + else if (((p00 = (( 14 :: int)::ii)))) then Exception_SystemRegisterTrap + else if (((p00 = (( 15 :: int)::ii)))) then Exception_ERetTrap + else if (((p00 = (( 16 :: int)::ii)))) then Exception_InstructionAbort + else if (((p00 = (( 17 :: int)::ii)))) then Exception_PCAlignment + else if (((p00 = (( 18 :: int)::ii)))) then Exception_DataAbort + else if (((p00 = (( 19 :: int)::ii)))) then Exception_SPAlignment + else if (((p00 = (( 20 :: int)::ii)))) then Exception_FPTrappedException + else if (((p00 = (( 21 :: int)::ii)))) then Exception_SError + else if (((p00 = (( 22 :: int)::ii)))) then Exception_Breakpoint + else if (((p00 = (( 23 :: int)::ii)))) then Exception_SoftwareStep + else if (((p00 = (( 24 :: int)::ii)))) then Exception_Watchpoint + else if (((p00 = (( 25 :: int)::ii)))) then Exception_SoftwareBreakpoint + else if (((p00 = (( 26 :: int)::ii)))) then Exception_VectorCatch + else if (((p00 = (( 27 :: int)::ii)))) then Exception_IRQ else Exception_FIQ))" @@ -484,10 +523,10 @@ definition undefined_Exception :: " unit \<Rightarrow>((register_value),(Except definition ArchVersion_of_num :: " int \<Rightarrow> ArchVersion " where " ArchVersion_of_num arg0 = ( - (let l__551 = arg0 in - if (((l__551 = (( 0 :: int)::ii)))) then ARMv8p0 - else if (((l__551 = (( 1 :: int)::ii)))) then ARMv8p1 - else if (((l__551 = (( 2 :: int)::ii)))) then ARMv8p2 + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then ARMv8p0 + else if (((p00 = (( 1 :: int)::ii)))) then ARMv8p1 + else if (((p00 = (( 2 :: int)::ii)))) then ARMv8p2 else ARMv8p3))" @@ -510,51 +549,51 @@ definition undefined_ArchVersion :: " unit \<Rightarrow>((register_value),(Arch definition Unpredictable_of_num :: " int \<Rightarrow> Unpredictable " where " Unpredictable_of_num arg0 = ( - (let l__507 = arg0 in - if (((l__507 = (( 0 :: int)::ii)))) then Unpredictable_WBOVERLAPLD - else if (((l__507 = (( 1 :: int)::ii)))) then Unpredictable_WBOVERLAPST - else if (((l__507 = (( 2 :: int)::ii)))) then Unpredictable_LDPOVERLAP - else if (((l__507 = (( 3 :: int)::ii)))) then Unpredictable_BASEOVERLAP - else if (((l__507 = (( 4 :: int)::ii)))) then Unpredictable_DATAOVERLAP - else if (((l__507 = (( 5 :: int)::ii)))) then Unpredictable_DEVPAGE2 - else if (((l__507 = (( 6 :: int)::ii)))) then Unpredictable_INSTRDEVICE - else if (((l__507 = (( 7 :: int)::ii)))) then Unpredictable_RESCPACR - else if (((l__507 = (( 8 :: int)::ii)))) then Unpredictable_RESMAIR - else if (((l__507 = (( 9 :: int)::ii)))) then Unpredictable_RESTEXCB - else if (((l__507 = (( 10 :: int)::ii)))) then Unpredictable_RESPRRR - else if (((l__507 = (( 11 :: int)::ii)))) then Unpredictable_RESDACR - else if (((l__507 = (( 12 :: int)::ii)))) then Unpredictable_RESVTCRS - else if (((l__507 = (( 13 :: int)::ii)))) then Unpredictable_RESTnSZ - else if (((l__507 = (( 14 :: int)::ii)))) then Unpredictable_OORTnSZ - else if (((l__507 = (( 15 :: int)::ii)))) then Unpredictable_LARGEIPA - else if (((l__507 = (( 16 :: int)::ii)))) then Unpredictable_ESRCONDPASS - else if (((l__507 = (( 17 :: int)::ii)))) then Unpredictable_ILZEROIT - else if (((l__507 = (( 18 :: int)::ii)))) then Unpredictable_ILZEROT - else if (((l__507 = (( 19 :: int)::ii)))) then Unpredictable_BPVECTORCATCHPRI - else if (((l__507 = (( 20 :: int)::ii)))) then Unpredictable_VCMATCHHALF - else if (((l__507 = (( 21 :: int)::ii)))) then Unpredictable_VCMATCHDAPA - else if (((l__507 = (( 22 :: int)::ii)))) then Unpredictable_WPMASKANDBAS - else if (((l__507 = (( 23 :: int)::ii)))) then Unpredictable_WPBASCONTIGUOUS - else if (((l__507 = (( 24 :: int)::ii)))) then Unpredictable_RESWPMASK - else if (((l__507 = (( 25 :: int)::ii)))) then Unpredictable_WPMASKEDBITS - else if (((l__507 = (( 26 :: int)::ii)))) then Unpredictable_RESBPWPCTRL - else if (((l__507 = (( 27 :: int)::ii)))) then Unpredictable_BPNOTIMPL - else if (((l__507 = (( 28 :: int)::ii)))) then Unpredictable_RESBPTYPE - else if (((l__507 = (( 29 :: int)::ii)))) then Unpredictable_BPNOTCTXCMP - else if (((l__507 = (( 30 :: int)::ii)))) then Unpredictable_BPMATCHHALF - else if (((l__507 = (( 31 :: int)::ii)))) then Unpredictable_BPMISMATCHHALF - else if (((l__507 = (( 32 :: int)::ii)))) then Unpredictable_RESTARTALIGNPC - else if (((l__507 = (( 33 :: int)::ii)))) then Unpredictable_RESTARTZEROUPPERPC - else if (((l__507 = (( 34 :: int)::ii)))) then Unpredictable_ZEROUPPER - else if (((l__507 = (( 35 :: int)::ii)))) then Unpredictable_ERETZEROUPPERPC - else if (((l__507 = (( 36 :: int)::ii)))) then Unpredictable_A32FORCEALIGNPC - else if (((l__507 = (( 37 :: int)::ii)))) then Unpredictable_SMD - else if (((l__507 = (( 38 :: int)::ii)))) then Unpredictable_AFUPDATE - else if (((l__507 = (( 39 :: int)::ii)))) then Unpredictable_IESBinDebug - else if (((l__507 = (( 40 :: int)::ii)))) then Unpredictable_ZEROPMSEVFR - else if (((l__507 = (( 41 :: int)::ii)))) then Unpredictable_NOOPTYPES - else if (((l__507 = (( 42 :: int)::ii)))) then Unpredictable_ZEROMINLATENCY - else if (((l__507 = (( 43 :: int)::ii)))) then Unpredictable_CLEARERRITEZERO + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Unpredictable_WBOVERLAPLD + else if (((p00 = (( 1 :: int)::ii)))) then Unpredictable_WBOVERLAPST + else if (((p00 = (( 2 :: int)::ii)))) then Unpredictable_LDPOVERLAP + else if (((p00 = (( 3 :: int)::ii)))) then Unpredictable_BASEOVERLAP + else if (((p00 = (( 4 :: int)::ii)))) then Unpredictable_DATAOVERLAP + else if (((p00 = (( 5 :: int)::ii)))) then Unpredictable_DEVPAGE2 + else if (((p00 = (( 6 :: int)::ii)))) then Unpredictable_INSTRDEVICE + else if (((p00 = (( 7 :: int)::ii)))) then Unpredictable_RESCPACR + else if (((p00 = (( 8 :: int)::ii)))) then Unpredictable_RESMAIR + else if (((p00 = (( 9 :: int)::ii)))) then Unpredictable_RESTEXCB + else if (((p00 = (( 10 :: int)::ii)))) then Unpredictable_RESPRRR + else if (((p00 = (( 11 :: int)::ii)))) then Unpredictable_RESDACR + else if (((p00 = (( 12 :: int)::ii)))) then Unpredictable_RESVTCRS + else if (((p00 = (( 13 :: int)::ii)))) then Unpredictable_RESTnSZ + else if (((p00 = (( 14 :: int)::ii)))) then Unpredictable_OORTnSZ + else if (((p00 = (( 15 :: int)::ii)))) then Unpredictable_LARGEIPA + else if (((p00 = (( 16 :: int)::ii)))) then Unpredictable_ESRCONDPASS + else if (((p00 = (( 17 :: int)::ii)))) then Unpredictable_ILZEROIT + else if (((p00 = (( 18 :: int)::ii)))) then Unpredictable_ILZEROT + else if (((p00 = (( 19 :: int)::ii)))) then Unpredictable_BPVECTORCATCHPRI + else if (((p00 = (( 20 :: int)::ii)))) then Unpredictable_VCMATCHHALF + else if (((p00 = (( 21 :: int)::ii)))) then Unpredictable_VCMATCHDAPA + else if (((p00 = (( 22 :: int)::ii)))) then Unpredictable_WPMASKANDBAS + else if (((p00 = (( 23 :: int)::ii)))) then Unpredictable_WPBASCONTIGUOUS + else if (((p00 = (( 24 :: int)::ii)))) then Unpredictable_RESWPMASK + else if (((p00 = (( 25 :: int)::ii)))) then Unpredictable_WPMASKEDBITS + else if (((p00 = (( 26 :: int)::ii)))) then Unpredictable_RESBPWPCTRL + else if (((p00 = (( 27 :: int)::ii)))) then Unpredictable_BPNOTIMPL + else if (((p00 = (( 28 :: int)::ii)))) then Unpredictable_RESBPTYPE + else if (((p00 = (( 29 :: int)::ii)))) then Unpredictable_BPNOTCTXCMP + else if (((p00 = (( 30 :: int)::ii)))) then Unpredictable_BPMATCHHALF + else if (((p00 = (( 31 :: int)::ii)))) then Unpredictable_BPMISMATCHHALF + else if (((p00 = (( 32 :: int)::ii)))) then Unpredictable_RESTARTALIGNPC + else if (((p00 = (( 33 :: int)::ii)))) then Unpredictable_RESTARTZEROUPPERPC + else if (((p00 = (( 34 :: int)::ii)))) then Unpredictable_ZEROUPPER + else if (((p00 = (( 35 :: int)::ii)))) then Unpredictable_ERETZEROUPPERPC + else if (((p00 = (( 36 :: int)::ii)))) then Unpredictable_A32FORCEALIGNPC + else if (((p00 = (( 37 :: int)::ii)))) then Unpredictable_SMD + else if (((p00 = (( 38 :: int)::ii)))) then Unpredictable_AFUPDATE + else if (((p00 = (( 39 :: int)::ii)))) then Unpredictable_IESBinDebug + else if (((p00 = (( 40 :: int)::ii)))) then Unpredictable_ZEROPMSEVFR + else if (((p00 = (( 41 :: int)::ii)))) then Unpredictable_NOOPTYPES + else if (((p00 = (( 42 :: int)::ii)))) then Unpredictable_ZEROMINLATENCY + else if (((p00 = (( 43 :: int)::ii)))) then Unpredictable_CLEARERRITEZERO else Unpredictable_TBD))" @@ -620,21 +659,21 @@ definition undefined_Unpredictable :: " unit \<Rightarrow>((register_value),(Un definition Constraint_of_num :: " int \<Rightarrow> Constraint " where " Constraint_of_num arg0 = ( - (let l__493 = arg0 in - if (((l__493 = (( 0 :: int)::ii)))) then Constraint_NONE - else if (((l__493 = (( 1 :: int)::ii)))) then Constraint_UNKNOWN - else if (((l__493 = (( 2 :: int)::ii)))) then Constraint_UNDEF - else if (((l__493 = (( 3 :: int)::ii)))) then Constraint_UNDEFEL0 - else if (((l__493 = (( 4 :: int)::ii)))) then Constraint_NOP - else if (((l__493 = (( 5 :: int)::ii)))) then Constraint_TRUE - else if (((l__493 = (( 6 :: int)::ii)))) then Constraint_FALSE - else if (((l__493 = (( 7 :: int)::ii)))) then Constraint_DISABLED - else if (((l__493 = (( 8 :: int)::ii)))) then Constraint_UNCOND - else if (((l__493 = (( 9 :: int)::ii)))) then Constraint_COND - else if (((l__493 = (( 10 :: int)::ii)))) then Constraint_ADDITIONAL_DECODE - else if (((l__493 = (( 11 :: int)::ii)))) then Constraint_WBSUPPRESS - else if (((l__493 = (( 12 :: int)::ii)))) then Constraint_FAULT - else if (((l__493 = (( 13 :: int)::ii)))) then Constraint_FORCE + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Constraint_NONE + else if (((p00 = (( 1 :: int)::ii)))) then Constraint_UNKNOWN + else if (((p00 = (( 2 :: int)::ii)))) then Constraint_UNDEF + else if (((p00 = (( 3 :: int)::ii)))) then Constraint_UNDEFEL0 + else if (((p00 = (( 4 :: int)::ii)))) then Constraint_NOP + else if (((p00 = (( 5 :: int)::ii)))) then Constraint_TRUE + else if (((p00 = (( 6 :: int)::ii)))) then Constraint_FALSE + else if (((p00 = (( 7 :: int)::ii)))) then Constraint_DISABLED + else if (((p00 = (( 8 :: int)::ii)))) then Constraint_UNCOND + else if (((p00 = (( 9 :: int)::ii)))) then Constraint_COND + else if (((p00 = (( 10 :: int)::ii)))) then Constraint_ADDITIONAL_DECODE + else if (((p00 = (( 11 :: int)::ii)))) then Constraint_WBSUPPRESS + else if (((p00 = (( 12 :: int)::ii)))) then Constraint_FAULT + else if (((p00 = (( 13 :: int)::ii)))) then Constraint_FORCE else Constraint_FORCENOSLCHECK))" @@ -670,9 +709,9 @@ definition undefined_Constraint :: " unit \<Rightarrow>((register_value),(Const definition InstrSet_of_num :: " int \<Rightarrow> InstrSet " where " InstrSet_of_num arg0 = ( - (let l__491 = arg0 in - if (((l__491 = (( 0 :: int)::ii)))) then InstrSet_A64 - else if (((l__491 = (( 1 :: int)::ii)))) then InstrSet_A32 + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then InstrSet_A64 + else if (((p00 = (( 1 :: int)::ii)))) then InstrSet_A32 else InstrSet_T32))" @@ -744,13 +783,13 @@ definition undefined_ProcState :: " unit \<Rightarrow>((register_value),(ProcSt definition BranchType_of_num :: " int \<Rightarrow> BranchType " where " BranchType_of_num arg0 = ( - (let l__485 = arg0 in - if (((l__485 = (( 0 :: int)::ii)))) then BranchType_CALL - else if (((l__485 = (( 1 :: int)::ii)))) then BranchType_ERET - else if (((l__485 = (( 2 :: int)::ii)))) then BranchType_DBGEXIT - else if (((l__485 = (( 3 :: int)::ii)))) then BranchType_RET - else if (((l__485 = (( 4 :: int)::ii)))) then BranchType_JMP - else if (((l__485 = (( 5 :: int)::ii)))) then BranchType_EXCEPTION + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then BranchType_CALL + else if (((p00 = (( 1 :: int)::ii)))) then BranchType_ERET + else if (((p00 = (( 2 :: int)::ii)))) then BranchType_DBGEXIT + else if (((p00 = (( 3 :: int)::ii)))) then BranchType_RET + else if (((p00 = (( 4 :: int)::ii)))) then BranchType_JMP + else if (((p00 = (( 5 :: int)::ii)))) then BranchType_EXCEPTION else BranchType_UNKNOWN))" @@ -794,25 +833,25 @@ definition undefined_ExceptionRecord :: " unit \<Rightarrow>((register_value),( definition Fault_of_num :: " int \<Rightarrow> Fault " where " Fault_of_num arg0 = ( - (let l__467 = arg0 in - if (((l__467 = (( 0 :: int)::ii)))) then Fault_None - else if (((l__467 = (( 1 :: int)::ii)))) then Fault_AccessFlag - else if (((l__467 = (( 2 :: int)::ii)))) then Fault_Alignment - else if (((l__467 = (( 3 :: int)::ii)))) then Fault_Background - else if (((l__467 = (( 4 :: int)::ii)))) then Fault_Domain - else if (((l__467 = (( 5 :: int)::ii)))) then Fault_Permission - else if (((l__467 = (( 6 :: int)::ii)))) then Fault_Translation - else if (((l__467 = (( 7 :: int)::ii)))) then Fault_AddressSize - else if (((l__467 = (( 8 :: int)::ii)))) then Fault_SyncExternal - else if (((l__467 = (( 9 :: int)::ii)))) then Fault_SyncExternalOnWalk - else if (((l__467 = (( 10 :: int)::ii)))) then Fault_SyncParity - else if (((l__467 = (( 11 :: int)::ii)))) then Fault_SyncParityOnWalk - else if (((l__467 = (( 12 :: int)::ii)))) then Fault_AsyncParity - else if (((l__467 = (( 13 :: int)::ii)))) then Fault_AsyncExternal - else if (((l__467 = (( 14 :: int)::ii)))) then Fault_Debug - else if (((l__467 = (( 15 :: int)::ii)))) then Fault_TLBConflict - else if (((l__467 = (( 16 :: int)::ii)))) then Fault_Lockdown - else if (((l__467 = (( 17 :: int)::ii)))) then Fault_Exclusive + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Fault_None + else if (((p00 = (( 1 :: int)::ii)))) then Fault_AccessFlag + else if (((p00 = (( 2 :: int)::ii)))) then Fault_Alignment + else if (((p00 = (( 3 :: int)::ii)))) then Fault_Background + else if (((p00 = (( 4 :: int)::ii)))) then Fault_Domain + else if (((p00 = (( 5 :: int)::ii)))) then Fault_Permission + else if (((p00 = (( 6 :: int)::ii)))) then Fault_Translation + else if (((p00 = (( 7 :: int)::ii)))) then Fault_AddressSize + else if (((p00 = (( 8 :: int)::ii)))) then Fault_SyncExternal + else if (((p00 = (( 9 :: int)::ii)))) then Fault_SyncExternalOnWalk + else if (((p00 = (( 10 :: int)::ii)))) then Fault_SyncParity + else if (((p00 = (( 11 :: int)::ii)))) then Fault_SyncParityOnWalk + else if (((p00 = (( 12 :: int)::ii)))) then Fault_AsyncParity + else if (((p00 = (( 13 :: int)::ii)))) then Fault_AsyncExternal + else if (((p00 = (( 14 :: int)::ii)))) then Fault_Debug + else if (((p00 = (( 15 :: int)::ii)))) then Fault_TLBConflict + else if (((p00 = (( 16 :: int)::ii)))) then Fault_Lockdown + else if (((p00 = (( 17 :: int)::ii)))) then Fault_Exclusive else Fault_ICacheMaint))" @@ -852,22 +891,22 @@ definition undefined_Fault :: " unit \<Rightarrow>((register_value),(Fault),(ex definition AccType_of_num :: " int \<Rightarrow> AccType " where " AccType_of_num arg0 = ( - (let l__452 = arg0 in - if (((l__452 = (( 0 :: int)::ii)))) then AccType_NORMAL - else if (((l__452 = (( 1 :: int)::ii)))) then AccType_VEC - else if (((l__452 = (( 2 :: int)::ii)))) then AccType_STREAM - else if (((l__452 = (( 3 :: int)::ii)))) then AccType_VECSTREAM - else if (((l__452 = (( 4 :: int)::ii)))) then AccType_ATOMIC - else if (((l__452 = (( 5 :: int)::ii)))) then AccType_ATOMICRW - else if (((l__452 = (( 6 :: int)::ii)))) then AccType_ORDERED - else if (((l__452 = (( 7 :: int)::ii)))) then AccType_ORDEREDRW - else if (((l__452 = (( 8 :: int)::ii)))) then AccType_LIMITEDORDERED - else if (((l__452 = (( 9 :: int)::ii)))) then AccType_UNPRIV - else if (((l__452 = (( 10 :: int)::ii)))) then AccType_IFETCH - else if (((l__452 = (( 11 :: int)::ii)))) then AccType_PTW - else if (((l__452 = (( 12 :: int)::ii)))) then AccType_DC - else if (((l__452 = (( 13 :: int)::ii)))) then AccType_IC - else if (((l__452 = (( 14 :: int)::ii)))) then AccType_DCZVA + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then AccType_NORMAL + else if (((p00 = (( 1 :: int)::ii)))) then AccType_VEC + else if (((p00 = (( 2 :: int)::ii)))) then AccType_STREAM + else if (((p00 = (( 3 :: int)::ii)))) then AccType_VECSTREAM + else if (((p00 = (( 4 :: int)::ii)))) then AccType_ATOMIC + else if (((p00 = (( 5 :: int)::ii)))) then AccType_ATOMICRW + else if (((p00 = (( 6 :: int)::ii)))) then AccType_ORDERED + else if (((p00 = (( 7 :: int)::ii)))) then AccType_ORDEREDRW + else if (((p00 = (( 8 :: int)::ii)))) then AccType_LIMITEDORDERED + else if (((p00 = (( 9 :: int)::ii)))) then AccType_UNPRIV + else if (((p00 = (( 10 :: int)::ii)))) then AccType_IFETCH + else if (((p00 = (( 11 :: int)::ii)))) then AccType_PTW + else if (((p00 = (( 12 :: int)::ii)))) then AccType_DC + else if (((p00 = (( 13 :: int)::ii)))) then AccType_IC + else if (((p00 = (( 14 :: int)::ii)))) then AccType_DCZVA else AccType_AT))" @@ -932,10 +971,10 @@ definition undefined_FaultRecord :: " unit \<Rightarrow>((register_value),(Faul definition MBReqDomain_of_num :: " int \<Rightarrow> MBReqDomain " where " MBReqDomain_of_num arg0 = ( - (let l__449 = arg0 in - if (((l__449 = (( 0 :: int)::ii)))) then MBReqDomain_Nonshareable - else if (((l__449 = (( 1 :: int)::ii)))) then MBReqDomain_InnerShareable - else if (((l__449 = (( 2 :: int)::ii)))) then MBReqDomain_OuterShareable + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then MBReqDomain_Nonshareable + else if (((p00 = (( 1 :: int)::ii)))) then MBReqDomain_InnerShareable + else if (((p00 = (( 2 :: int)::ii)))) then MBReqDomain_OuterShareable else MBReqDomain_FullSystem))" @@ -960,9 +999,9 @@ definition undefined_MBReqDomain :: " unit \<Rightarrow>((register_value),(MBRe definition MBReqTypes_of_num :: " int \<Rightarrow> MBReqTypes " where " MBReqTypes_of_num arg0 = ( - (let l__447 = arg0 in - if (((l__447 = (( 0 :: int)::ii)))) then MBReqTypes_Reads - else if (((l__447 = (( 1 :: int)::ii)))) then MBReqTypes_Writes + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then MBReqTypes_Reads + else if (((p00 = (( 1 :: int)::ii)))) then MBReqTypes_Writes else MBReqTypes_All))" @@ -984,8 +1023,8 @@ definition undefined_MBReqTypes :: " unit \<Rightarrow>((register_value),(MBReq definition MemType_of_num :: " int \<Rightarrow> MemType " where " MemType_of_num arg0 = ( - (let l__446 = arg0 in - if (((l__446 = (( 0 :: int)::ii)))) then MemType_Normal + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then MemType_Normal else MemType_Device))" @@ -1006,10 +1045,10 @@ definition undefined_MemType :: " unit \<Rightarrow>((register_value),(MemType) definition DeviceType_of_num :: " int \<Rightarrow> DeviceType " where " DeviceType_of_num arg0 = ( - (let l__443 = arg0 in - if (((l__443 = (( 0 :: int)::ii)))) then DeviceType_GRE - else if (((l__443 = (( 1 :: int)::ii)))) then DeviceType_nGRE - else if (((l__443 = (( 2 :: int)::ii)))) then DeviceType_nGnRE + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then DeviceType_GRE + else if (((p00 = (( 1 :: int)::ii)))) then DeviceType_nGRE + else if (((p00 = (( 2 :: int)::ii)))) then DeviceType_nGnRE else DeviceType_nGnRnE))" @@ -1099,15 +1138,15 @@ definition undefined_DescriptorUpdate :: " unit \<Rightarrow>((register_value), definition MemAtomicOp_of_num :: " int \<Rightarrow> MemAtomicOp " where " MemAtomicOp_of_num arg0 = ( - (let l__435 = arg0 in - if (((l__435 = (( 0 :: int)::ii)))) then MemAtomicOp_ADD - else if (((l__435 = (( 1 :: int)::ii)))) then MemAtomicOp_BIC - else if (((l__435 = (( 2 :: int)::ii)))) then MemAtomicOp_EOR - else if (((l__435 = (( 3 :: int)::ii)))) then MemAtomicOp_ORR - else if (((l__435 = (( 4 :: int)::ii)))) then MemAtomicOp_SMAX - else if (((l__435 = (( 5 :: int)::ii)))) then MemAtomicOp_SMIN - else if (((l__435 = (( 6 :: int)::ii)))) then MemAtomicOp_UMAX - else if (((l__435 = (( 7 :: int)::ii)))) then MemAtomicOp_UMIN + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then MemAtomicOp_ADD + else if (((p00 = (( 1 :: int)::ii)))) then MemAtomicOp_BIC + else if (((p00 = (( 2 :: int)::ii)))) then MemAtomicOp_EOR + else if (((p00 = (( 3 :: int)::ii)))) then MemAtomicOp_ORR + else if (((p00 = (( 4 :: int)::ii)))) then MemAtomicOp_SMAX + else if (((p00 = (( 5 :: int)::ii)))) then MemAtomicOp_SMIN + else if (((p00 = (( 6 :: int)::ii)))) then MemAtomicOp_UMAX + else if (((p00 = (( 7 :: int)::ii)))) then MemAtomicOp_UMIN else MemAtomicOp_SWP))" @@ -1137,11 +1176,11 @@ definition undefined_MemAtomicOp :: " unit \<Rightarrow>((register_value),(MemA definition FPType_of_num :: " int \<Rightarrow> FPType " where " FPType_of_num arg0 = ( - (let l__431 = arg0 in - if (((l__431 = (( 0 :: int)::ii)))) then FPType_Nonzero - else if (((l__431 = (( 1 :: int)::ii)))) then FPType_Zero - else if (((l__431 = (( 2 :: int)::ii)))) then FPType_Infinity - else if (((l__431 = (( 3 :: int)::ii)))) then FPType_QNaN + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then FPType_Nonzero + else if (((p00 = (( 1 :: int)::ii)))) then FPType_Zero + else if (((p00 = (( 2 :: int)::ii)))) then FPType_Infinity + else if (((p00 = (( 3 :: int)::ii)))) then FPType_QNaN else FPType_SNaN))" @@ -1166,12 +1205,12 @@ definition undefined_FPType :: " unit \<Rightarrow>((register_value),(FPType),( definition FPExc_of_num :: " int \<Rightarrow> FPExc " where " FPExc_of_num arg0 = ( - (let l__426 = arg0 in - if (((l__426 = (( 0 :: int)::ii)))) then FPExc_InvalidOp - else if (((l__426 = (( 1 :: int)::ii)))) then FPExc_DivideByZero - else if (((l__426 = (( 2 :: int)::ii)))) then FPExc_Overflow - else if (((l__426 = (( 3 :: int)::ii)))) then FPExc_Underflow - else if (((l__426 = (( 4 :: int)::ii)))) then FPExc_Inexact + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then FPExc_InvalidOp + else if (((p00 = (( 1 :: int)::ii)))) then FPExc_DivideByZero + else if (((p00 = (( 2 :: int)::ii)))) then FPExc_Overflow + else if (((p00 = (( 3 :: int)::ii)))) then FPExc_Underflow + else if (((p00 = (( 4 :: int)::ii)))) then FPExc_Inexact else FPExc_InputDenorm))" @@ -1198,12 +1237,12 @@ definition undefined_FPExc :: " unit \<Rightarrow>((register_value),(FPExc),(ex definition FPRounding_of_num :: " int \<Rightarrow> FPRounding " where " FPRounding_of_num arg0 = ( - (let l__421 = arg0 in - if (((l__421 = (( 0 :: int)::ii)))) then FPRounding_TIEEVEN - else if (((l__421 = (( 1 :: int)::ii)))) then FPRounding_POSINF - else if (((l__421 = (( 2 :: int)::ii)))) then FPRounding_NEGINF - else if (((l__421 = (( 3 :: int)::ii)))) then FPRounding_ZERO - else if (((l__421 = (( 4 :: int)::ii)))) then FPRounding_TIEAWAY + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then FPRounding_TIEEVEN + else if (((p00 = (( 1 :: int)::ii)))) then FPRounding_POSINF + else if (((p00 = (( 2 :: int)::ii)))) then FPRounding_NEGINF + else if (((p00 = (( 3 :: int)::ii)))) then FPRounding_ZERO + else if (((p00 = (( 4 :: int)::ii)))) then FPRounding_TIEAWAY else FPRounding_ODD))" @@ -1230,11 +1269,11 @@ definition undefined_FPRounding :: " unit \<Rightarrow>((register_value),(FPRou definition SysRegAccess_of_num :: " int \<Rightarrow> SysRegAccess " where " SysRegAccess_of_num arg0 = ( - (let l__417 = arg0 in - if (((l__417 = (( 0 :: int)::ii)))) then SysRegAccess_OK - else if (((l__417 = (( 1 :: int)::ii)))) then SysRegAccess_UNDEFINED - else if (((l__417 = (( 2 :: int)::ii)))) then SysRegAccess_TrapToEL1 - else if (((l__417 = (( 3 :: int)::ii)))) then SysRegAccess_TrapToEL2 + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then SysRegAccess_OK + else if (((p00 = (( 1 :: int)::ii)))) then SysRegAccess_UNDEFINED + else if (((p00 = (( 2 :: int)::ii)))) then SysRegAccess_TrapToEL1 + else if (((p00 = (( 3 :: int)::ii)))) then SysRegAccess_TrapToEL2 else SysRegAccess_TrapToEL3))" @@ -1260,11 +1299,11 @@ definition undefined_SysRegAccess :: " unit \<Rightarrow>((register_value),(Sys definition SRType_of_num :: " int \<Rightarrow> SRType " where " SRType_of_num arg0 = ( - (let l__413 = arg0 in - if (((l__413 = (( 0 :: int)::ii)))) then SRType_LSL - else if (((l__413 = (( 1 :: int)::ii)))) then SRType_LSR - else if (((l__413 = (( 2 :: int)::ii)))) then SRType_ASR - else if (((l__413 = (( 3 :: int)::ii)))) then SRType_ROR + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then SRType_LSL + else if (((p00 = (( 1 :: int)::ii)))) then SRType_LSR + else if (((p00 = (( 2 :: int)::ii)))) then SRType_ASR + else if (((p00 = (( 3 :: int)::ii)))) then SRType_ROR else SRType_RRX))" @@ -1288,10 +1327,10 @@ definition undefined_SRType :: " unit \<Rightarrow>((register_value),(SRType),( definition ShiftType_of_num :: " int \<Rightarrow> ShiftType " where " ShiftType_of_num arg0 = ( - (let l__410 = arg0 in - if (((l__410 = (( 0 :: int)::ii)))) then ShiftType_LSL - else if (((l__410 = (( 1 :: int)::ii)))) then ShiftType_LSR - else if (((l__410 = (( 2 :: int)::ii)))) then ShiftType_ASR + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then ShiftType_LSL + else if (((p00 = (( 1 :: int)::ii)))) then ShiftType_LSR + else if (((p00 = (( 2 :: int)::ii)))) then ShiftType_ASR else ShiftType_ROR))" @@ -1314,9 +1353,9 @@ definition undefined_ShiftType :: " unit \<Rightarrow>((register_value),(ShiftT definition PrefetchHint_of_num :: " int \<Rightarrow> PrefetchHint " where " PrefetchHint_of_num arg0 = ( - (let l__408 = arg0 in - if (((l__408 = (( 0 :: int)::ii)))) then Prefetch_READ - else if (((l__408 = (( 1 :: int)::ii)))) then Prefetch_WRITE + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Prefetch_READ + else if (((p00 = (( 1 :: int)::ii)))) then Prefetch_WRITE else Prefetch_EXEC))" @@ -1338,11 +1377,11 @@ definition undefined_PrefetchHint :: " unit \<Rightarrow>((register_value),(Pre definition InterruptID_of_num :: " int \<Rightarrow> InterruptID " where " InterruptID_of_num arg0 = ( - (let l__404 = arg0 in - if (((l__404 = (( 0 :: int)::ii)))) then InterruptID_PMUIRQ - else if (((l__404 = (( 1 :: int)::ii)))) then InterruptID_COMMIRQ - else if (((l__404 = (( 2 :: int)::ii)))) then InterruptID_CTIIRQ - else if (((l__404 = (( 3 :: int)::ii)))) then InterruptID_COMMRX + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then InterruptID_PMUIRQ + else if (((p00 = (( 1 :: int)::ii)))) then InterruptID_COMMIRQ + else if (((p00 = (( 2 :: int)::ii)))) then InterruptID_CTIIRQ + else if (((p00 = (( 3 :: int)::ii)))) then InterruptID_COMMRX else InterruptID_COMMTX))" @@ -1368,14 +1407,14 @@ definition undefined_InterruptID :: " unit \<Rightarrow>((register_value),(Inte definition CrossTriggerOut_of_num :: " int \<Rightarrow> CrossTriggerOut " where " CrossTriggerOut_of_num arg0 = ( - (let l__397 = arg0 in - if (((l__397 = (( 0 :: int)::ii)))) then CrossTriggerOut_DebugRequest - else if (((l__397 = (( 1 :: int)::ii)))) then CrossTriggerOut_RestartRequest - else if (((l__397 = (( 2 :: int)::ii)))) then CrossTriggerOut_IRQ - else if (((l__397 = (( 3 :: int)::ii)))) then CrossTriggerOut_RSVD3 - else if (((l__397 = (( 4 :: int)::ii)))) then CrossTriggerOut_TraceExtIn0 - else if (((l__397 = (( 5 :: int)::ii)))) then CrossTriggerOut_TraceExtIn1 - else if (((l__397 = (( 6 :: int)::ii)))) then CrossTriggerOut_TraceExtIn2 + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then CrossTriggerOut_DebugRequest + else if (((p00 = (( 1 :: int)::ii)))) then CrossTriggerOut_RestartRequest + else if (((p00 = (( 2 :: int)::ii)))) then CrossTriggerOut_IRQ + else if (((p00 = (( 3 :: int)::ii)))) then CrossTriggerOut_RSVD3 + else if (((p00 = (( 4 :: int)::ii)))) then CrossTriggerOut_TraceExtIn0 + else if (((p00 = (( 5 :: int)::ii)))) then CrossTriggerOut_TraceExtIn1 + else if (((p00 = (( 6 :: int)::ii)))) then CrossTriggerOut_TraceExtIn2 else CrossTriggerOut_TraceExtIn3))" @@ -1404,14 +1443,14 @@ definition undefined_CrossTriggerOut :: " unit \<Rightarrow>((register_value),( definition CrossTriggerIn_of_num :: " int \<Rightarrow> CrossTriggerIn " where " CrossTriggerIn_of_num arg0 = ( - (let l__390 = arg0 in - if (((l__390 = (( 0 :: int)::ii)))) then CrossTriggerIn_CrossHalt - else if (((l__390 = (( 1 :: int)::ii)))) then CrossTriggerIn_PMUOverflow - else if (((l__390 = (( 2 :: int)::ii)))) then CrossTriggerIn_RSVD2 - else if (((l__390 = (( 3 :: int)::ii)))) then CrossTriggerIn_RSVD3 - else if (((l__390 = (( 4 :: int)::ii)))) then CrossTriggerIn_TraceExtOut0 - else if (((l__390 = (( 5 :: int)::ii)))) then CrossTriggerIn_TraceExtOut1 - else if (((l__390 = (( 6 :: int)::ii)))) then CrossTriggerIn_TraceExtOut2 + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then CrossTriggerIn_CrossHalt + else if (((p00 = (( 1 :: int)::ii)))) then CrossTriggerIn_PMUOverflow + else if (((p00 = (( 2 :: int)::ii)))) then CrossTriggerIn_RSVD2 + else if (((p00 = (( 3 :: int)::ii)))) then CrossTriggerIn_RSVD3 + else if (((p00 = (( 4 :: int)::ii)))) then CrossTriggerIn_TraceExtOut0 + else if (((p00 = (( 5 :: int)::ii)))) then CrossTriggerIn_TraceExtOut1 + else if (((p00 = (( 6 :: int)::ii)))) then CrossTriggerIn_TraceExtOut2 else CrossTriggerIn_TraceExtOut3))" @@ -1440,9 +1479,9 @@ definition undefined_CrossTriggerIn :: " unit \<Rightarrow>((register_value),(C definition MemBarrierOp_of_num :: " int \<Rightarrow> MemBarrierOp " where " MemBarrierOp_of_num arg0 = ( - (let l__388 = arg0 in - if (((l__388 = (( 0 :: int)::ii)))) then MemBarrierOp_DSB - else if (((l__388 = (( 1 :: int)::ii)))) then MemBarrierOp_DMB + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then MemBarrierOp_DSB + else if (((p00 = (( 1 :: int)::ii)))) then MemBarrierOp_DMB else MemBarrierOp_ISB))" @@ -1518,10 +1557,10 @@ definition undefined_TLBRecord :: " unit \<Rightarrow>((register_value),(TLBRec definition ImmediateOp_of_num :: " int \<Rightarrow> ImmediateOp " where " ImmediateOp_of_num arg0 = ( - (let l__385 = arg0 in - if (((l__385 = (( 0 :: int)::ii)))) then ImmediateOp_MOVI - else if (((l__385 = (( 1 :: int)::ii)))) then ImmediateOp_MVNI - else if (((l__385 = (( 2 :: int)::ii)))) then ImmediateOp_ORR + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then ImmediateOp_MOVI + else if (((p00 = (( 1 :: int)::ii)))) then ImmediateOp_MVNI + else if (((p00 = (( 2 :: int)::ii)))) then ImmediateOp_ORR else ImmediateOp_BIC))" @@ -1545,9 +1584,9 @@ definition undefined_ImmediateOp :: " unit \<Rightarrow>((register_value),(Imme definition MoveWideOp_of_num :: " int \<Rightarrow> MoveWideOp " where " MoveWideOp_of_num arg0 = ( - (let l__383 = arg0 in - if (((l__383 = (( 0 :: int)::ii)))) then MoveWideOp_N - else if (((l__383 = (( 1 :: int)::ii)))) then MoveWideOp_Z + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then MoveWideOp_N + else if (((p00 = (( 1 :: int)::ii)))) then MoveWideOp_Z else MoveWideOp_K))" @@ -1569,9 +1608,9 @@ definition undefined_MoveWideOp :: " unit \<Rightarrow>((register_value),(MoveW definition SystemAccessType_of_num :: " int \<Rightarrow> SystemAccessType " where " SystemAccessType_of_num arg0 = ( - (let l__381 = arg0 in - if (((l__381 = (( 0 :: int)::ii)))) then SystemAccessType_RT - else if (((l__381 = (( 1 :: int)::ii)))) then SystemAccessType_RRT + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then SystemAccessType_RT + else if (((p00 = (( 1 :: int)::ii)))) then SystemAccessType_RRT else SystemAccessType_DT))" @@ -1594,10 +1633,10 @@ definition undefined_SystemAccessType :: " unit \<Rightarrow>((register_value), definition VBitOp_of_num :: " int \<Rightarrow> VBitOp " where " VBitOp_of_num arg0 = ( - (let l__378 = arg0 in - if (((l__378 = (( 0 :: int)::ii)))) then VBitOp_VBIF - else if (((l__378 = (( 1 :: int)::ii)))) then VBitOp_VBIT - else if (((l__378 = (( 2 :: int)::ii)))) then VBitOp_VBSL + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then VBitOp_VBIF + else if (((p00 = (( 1 :: int)::ii)))) then VBitOp_VBIT + else if (((p00 = (( 2 :: int)::ii)))) then VBitOp_VBSL else VBitOp_VEOR))" @@ -1620,9 +1659,9 @@ definition undefined_VBitOp :: " unit \<Rightarrow>((register_value),(VBitOp),( definition TimeStamp_of_num :: " int \<Rightarrow> TimeStamp " where " TimeStamp_of_num arg0 = ( - (let l__376 = arg0 in - if (((l__376 = (( 0 :: int)::ii)))) then TimeStamp_None - else if (((l__376 = (( 1 :: int)::ii)))) then TimeStamp_Virtual + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then TimeStamp_None + else if (((p00 = (( 1 :: int)::ii)))) then TimeStamp_Virtual else TimeStamp_Physical))" @@ -1644,10 +1683,10 @@ definition undefined_TimeStamp :: " unit \<Rightarrow>((register_value),(TimeSt definition PrivilegeLevel_of_num :: " int \<Rightarrow> PrivilegeLevel " where " PrivilegeLevel_of_num arg0 = ( - (let l__373 = arg0 in - if (((l__373 = (( 0 :: int)::ii)))) then PL3 - else if (((l__373 = (( 1 :: int)::ii)))) then PL2 - else if (((l__373 = (( 2 :: int)::ii)))) then PL1 + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then PL3 + else if (((p00 = (( 1 :: int)::ii)))) then PL2 + else if (((p00 = (( 2 :: int)::ii)))) then PL1 else PL0))" @@ -1680,11 +1719,11 @@ definition undefined_AArch32_SErrorSyndrome :: " unit \<Rightarrow>((register_v definition SystemOp_of_num :: " int \<Rightarrow> SystemOp " where " SystemOp_of_num arg0 = ( - (let l__369 = arg0 in - if (((l__369 = (( 0 :: int)::ii)))) then Sys_AT - else if (((l__369 = (( 1 :: int)::ii)))) then Sys_DC - else if (((l__369 = (( 2 :: int)::ii)))) then Sys_IC - else if (((l__369 = (( 3 :: int)::ii)))) then Sys_TLBI + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Sys_AT + else if (((p00 = (( 1 :: int)::ii)))) then Sys_DC + else if (((p00 = (( 2 :: int)::ii)))) then Sys_IC + else if (((p00 = (( 3 :: int)::ii)))) then Sys_TLBI else Sys_SYS))" @@ -1730,12 +1769,12 @@ definition undefined_PCSample :: " unit \<Rightarrow>((register_value),(PCSampl definition ReduceOp_of_num :: " int \<Rightarrow> ReduceOp " where " ReduceOp_of_num arg0 = ( - (let l__364 = arg0 in - if (((l__364 = (( 0 :: int)::ii)))) then ReduceOp_FMINNUM - else if (((l__364 = (( 1 :: int)::ii)))) then ReduceOp_FMAXNUM - else if (((l__364 = (( 2 :: int)::ii)))) then ReduceOp_FMIN - else if (((l__364 = (( 3 :: int)::ii)))) then ReduceOp_FMAX - else if (((l__364 = (( 4 :: int)::ii)))) then ReduceOp_FADD + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then ReduceOp_FMINNUM + else if (((p00 = (( 1 :: int)::ii)))) then ReduceOp_FMAXNUM + else if (((p00 = (( 2 :: int)::ii)))) then ReduceOp_FMIN + else if (((p00 = (( 3 :: int)::ii)))) then ReduceOp_FMAX + else if (((p00 = (( 4 :: int)::ii)))) then ReduceOp_FADD else ReduceOp_ADD))" @@ -1762,9 +1801,9 @@ definition undefined_ReduceOp :: " unit \<Rightarrow>((register_value),(ReduceO definition LogicalOp_of_num :: " int \<Rightarrow> LogicalOp " where " LogicalOp_of_num arg0 = ( - (let l__362 = arg0 in - if (((l__362 = (( 0 :: int)::ii)))) then LogicalOp_AND - else if (((l__362 = (( 1 :: int)::ii)))) then LogicalOp_EOR + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then LogicalOp_AND + else if (((p00 = (( 1 :: int)::ii)))) then LogicalOp_EOR else LogicalOp_ORR))" @@ -1786,14 +1825,14 @@ definition undefined_LogicalOp :: " unit \<Rightarrow>((register_value),(Logica definition ExtendType_of_num :: " int \<Rightarrow> ExtendType " where " ExtendType_of_num arg0 = ( - (let l__355 = arg0 in - if (((l__355 = (( 0 :: int)::ii)))) then ExtendType_SXTB - else if (((l__355 = (( 1 :: int)::ii)))) then ExtendType_SXTH - else if (((l__355 = (( 2 :: int)::ii)))) then ExtendType_SXTW - else if (((l__355 = (( 3 :: int)::ii)))) then ExtendType_SXTX - else if (((l__355 = (( 4 :: int)::ii)))) then ExtendType_UXTB - else if (((l__355 = (( 5 :: int)::ii)))) then ExtendType_UXTH - else if (((l__355 = (( 6 :: int)::ii)))) then ExtendType_UXTW + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then ExtendType_SXTB + else if (((p00 = (( 1 :: int)::ii)))) then ExtendType_SXTH + else if (((p00 = (( 2 :: int)::ii)))) then ExtendType_SXTW + else if (((p00 = (( 3 :: int)::ii)))) then ExtendType_SXTX + else if (((p00 = (( 4 :: int)::ii)))) then ExtendType_UXTB + else if (((p00 = (( 5 :: int)::ii)))) then ExtendType_UXTH + else if (((p00 = (( 6 :: int)::ii)))) then ExtendType_UXTW else ExtendType_UXTX))" @@ -1822,14 +1861,14 @@ definition undefined_ExtendType :: " unit \<Rightarrow>((register_value),(Exten definition SystemHintOp_of_num :: " int \<Rightarrow> SystemHintOp " where " SystemHintOp_of_num arg0 = ( - (let l__348 = arg0 in - if (((l__348 = (( 0 :: int)::ii)))) then SystemHintOp_NOP - else if (((l__348 = (( 1 :: int)::ii)))) then SystemHintOp_YIELD - else if (((l__348 = (( 2 :: int)::ii)))) then SystemHintOp_WFE - else if (((l__348 = (( 3 :: int)::ii)))) then SystemHintOp_WFI - else if (((l__348 = (( 4 :: int)::ii)))) then SystemHintOp_SEV - else if (((l__348 = (( 5 :: int)::ii)))) then SystemHintOp_SEVL - else if (((l__348 = (( 6 :: int)::ii)))) then SystemHintOp_ESB + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then SystemHintOp_NOP + else if (((p00 = (( 1 :: int)::ii)))) then SystemHintOp_YIELD + else if (((p00 = (( 2 :: int)::ii)))) then SystemHintOp_WFE + else if (((p00 = (( 3 :: int)::ii)))) then SystemHintOp_WFI + else if (((p00 = (( 4 :: int)::ii)))) then SystemHintOp_SEV + else if (((p00 = (( 5 :: int)::ii)))) then SystemHintOp_SEVL + else if (((p00 = (( 6 :: int)::ii)))) then SystemHintOp_ESB else SystemHintOp_PSB))" @@ -1858,9 +1897,9 @@ definition undefined_SystemHintOp :: " unit \<Rightarrow>((register_value),(Sys definition MemOp_of_num :: " int \<Rightarrow> MemOp " where " MemOp_of_num arg0 = ( - (let l__346 = arg0 in - if (((l__346 = (( 0 :: int)::ii)))) then MemOp_LOAD - else if (((l__346 = (( 1 :: int)::ii)))) then MemOp_STORE + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then MemOp_LOAD + else if (((p00 = (( 1 :: int)::ii)))) then MemOp_STORE else MemOp_PREFETCH))" @@ -1882,11 +1921,11 @@ definition undefined_MemOp :: " unit \<Rightarrow>((register_value),(MemOp),(ex definition OpType_of_num :: " int \<Rightarrow> OpType " where " OpType_of_num arg0 = ( - (let l__342 = arg0 in - if (((l__342 = (( 0 :: int)::ii)))) then OpType_Load - else if (((l__342 = (( 1 :: int)::ii)))) then OpType_Store - else if (((l__342 = (( 2 :: int)::ii)))) then OpType_LoadAtomic - else if (((l__342 = (( 3 :: int)::ii)))) then OpType_Branch + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then OpType_Load + else if (((p00 = (( 1 :: int)::ii)))) then OpType_Store + else if (((p00 = (( 2 :: int)::ii)))) then OpType_LoadAtomic + else if (((p00 = (( 3 :: int)::ii)))) then OpType_Branch else OpType_Other))" @@ -1911,10 +1950,10 @@ definition undefined_OpType :: " unit \<Rightarrow>((register_value),(OpType),( definition FPUnaryOp_of_num :: " int \<Rightarrow> FPUnaryOp " where " FPUnaryOp_of_num arg0 = ( - (let l__339 = arg0 in - if (((l__339 = (( 0 :: int)::ii)))) then FPUnaryOp_ABS - else if (((l__339 = (( 1 :: int)::ii)))) then FPUnaryOp_MOV - else if (((l__339 = (( 2 :: int)::ii)))) then FPUnaryOp_NEG + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then FPUnaryOp_ABS + else if (((p00 = (( 1 :: int)::ii)))) then FPUnaryOp_MOV + else if (((p00 = (( 2 :: int)::ii)))) then FPUnaryOp_NEG else FPUnaryOp_SQRT))" @@ -1938,11 +1977,11 @@ definition undefined_FPUnaryOp :: " unit \<Rightarrow>((register_value),(FPUnar definition CompareOp_of_num :: " int \<Rightarrow> CompareOp " where " CompareOp_of_num arg0 = ( - (let l__335 = arg0 in - if (((l__335 = (( 0 :: int)::ii)))) then CompareOp_GT - else if (((l__335 = (( 1 :: int)::ii)))) then CompareOp_GE - else if (((l__335 = (( 2 :: int)::ii)))) then CompareOp_EQ - else if (((l__335 = (( 3 :: int)::ii)))) then CompareOp_LE + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then CompareOp_GT + else if (((p00 = (( 1 :: int)::ii)))) then CompareOp_GE + else if (((p00 = (( 2 :: int)::ii)))) then CompareOp_EQ + else if (((p00 = (( 3 :: int)::ii)))) then CompareOp_LE else CompareOp_LT))" @@ -1967,11 +2006,11 @@ definition undefined_CompareOp :: " unit \<Rightarrow>((register_value),(Compar definition PSTATEField_of_num :: " int \<Rightarrow> PSTATEField " where " PSTATEField_of_num arg0 = ( - (let l__331 = arg0 in - if (((l__331 = (( 0 :: int)::ii)))) then PSTATEField_DAIFSet - else if (((l__331 = (( 1 :: int)::ii)))) then PSTATEField_DAIFClr - else if (((l__331 = (( 2 :: int)::ii)))) then PSTATEField_PAN - else if (((l__331 = (( 3 :: int)::ii)))) then PSTATEField_UAO + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then PSTATEField_DAIFSet + else if (((p00 = (( 1 :: int)::ii)))) then PSTATEField_DAIFClr + else if (((p00 = (( 2 :: int)::ii)))) then PSTATEField_PAN + else if (((p00 = (( 3 :: int)::ii)))) then PSTATEField_UAO else PSTATEField_SP))" @@ -1997,10 +2036,10 @@ definition undefined_PSTATEField :: " unit \<Rightarrow>((register_value),(PSTA definition FPMaxMinOp_of_num :: " int \<Rightarrow> FPMaxMinOp " where " FPMaxMinOp_of_num arg0 = ( - (let l__328 = arg0 in - if (((l__328 = (( 0 :: int)::ii)))) then FPMaxMinOp_MAX - else if (((l__328 = (( 1 :: int)::ii)))) then FPMaxMinOp_MIN - else if (((l__328 = (( 2 :: int)::ii)))) then FPMaxMinOp_MAXNUM + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then FPMaxMinOp_MAX + else if (((p00 = (( 1 :: int)::ii)))) then FPMaxMinOp_MIN + else if (((p00 = (( 2 :: int)::ii)))) then FPMaxMinOp_MAXNUM else FPMaxMinOp_MINNUM))" @@ -2024,9 +2063,9 @@ definition undefined_FPMaxMinOp :: " unit \<Rightarrow>((register_value),(FPMax definition CountOp_of_num :: " int \<Rightarrow> CountOp " where " CountOp_of_num arg0 = ( - (let l__326 = arg0 in - if (((l__326 = (( 0 :: int)::ii)))) then CountOp_CLZ - else if (((l__326 = (( 1 :: int)::ii)))) then CountOp_CLS + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then CountOp_CLZ + else if (((p00 = (( 1 :: int)::ii)))) then CountOp_CLS else CountOp_CNT))" @@ -2048,9 +2087,9 @@ definition undefined_CountOp :: " unit \<Rightarrow>((register_value),(CountOp) definition VFPNegMul_of_num :: " int \<Rightarrow> VFPNegMul " where " VFPNegMul_of_num arg0 = ( - (let l__324 = arg0 in - if (((l__324 = (( 0 :: int)::ii)))) then VFPNegMul_VNMLA - else if (((l__324 = (( 1 :: int)::ii)))) then VFPNegMul_VNMLS + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then VFPNegMul_VNMLA + else if (((p00 = (( 1 :: int)::ii)))) then VFPNegMul_VNMLS else VFPNegMul_VNMUL))" @@ -2072,9 +2111,9 @@ definition undefined_VFPNegMul :: " unit \<Rightarrow>((register_value),(VFPNeg definition VBitOps_of_num :: " int \<Rightarrow> VBitOps " where " VBitOps_of_num arg0 = ( - (let l__322 = arg0 in - if (((l__322 = (( 0 :: int)::ii)))) then VBitOps_VBIF - else if (((l__322 = (( 1 :: int)::ii)))) then VBitOps_VBIT + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then VBitOps_VBIF + else if (((p00 = (( 1 :: int)::ii)))) then VBitOps_VBIT else VBitOps_VBSL))" @@ -2096,9 +2135,9 @@ definition undefined_VBitOps :: " unit \<Rightarrow>((register_value),(VBitOps) definition VCGEtype_of_num :: " int \<Rightarrow> VCGEtype " where " VCGEtype_of_num arg0 = ( - (let l__320 = arg0 in - if (((l__320 = (( 0 :: int)::ii)))) then VCGEtype_signed - else if (((l__320 = (( 1 :: int)::ii)))) then VCGEtype_unsigned + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then VCGEtype_signed + else if (((p00 = (( 1 :: int)::ii)))) then VCGEtype_unsigned else VCGEtype_fp))" @@ -2120,9 +2159,9 @@ definition undefined_VCGEtype :: " unit \<Rightarrow>((register_value),(VCGEtyp definition VCGTtype_of_num :: " int \<Rightarrow> VCGTtype " where " VCGTtype_of_num arg0 = ( - (let l__318 = arg0 in - if (((l__318 = (( 0 :: int)::ii)))) then VCGTtype_signed - else if (((l__318 = (( 1 :: int)::ii)))) then VCGTtype_unsigned + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then VCGTtype_signed + else if (((p00 = (( 1 :: int)::ii)))) then VCGTtype_unsigned else VCGTtype_fp))" @@ -2144,10 +2183,10 @@ definition undefined_VCGTtype :: " unit \<Rightarrow>((register_value),(VCGTtyp definition InstrEnc_of_num :: " int \<Rightarrow> InstrEnc " where " InstrEnc_of_num arg0 = ( - (let l__315 = arg0 in - if (((l__315 = (( 0 :: int)::ii)))) then A64 - else if (((l__315 = (( 1 :: int)::ii)))) then A32 - else if (((l__315 = (( 2 :: int)::ii)))) then T16 + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then A64 + else if (((p00 = (( 1 :: int)::ii)))) then A32 + else if (((p00 = (( 2 :: int)::ii)))) then T16 else T32))" @@ -2203,7 +2242,7 @@ definition UndefinedFault :: " unit \<Rightarrow>((register_value),(unit),(exce definition ThisInstrAddr :: " int \<Rightarrow> unit \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " ThisInstrAddr (N__tv :: int) _ = ( (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . - return ((slice0 w__0 (( 0 :: int)::ii) N__tv :: ( 'N::len)Word.word))))" + return ((slice w__0 (( 0 :: int)::ii) N__tv :: ( 'N::len)Word.word))))" (*val ThisInstr : unit -> M (mword ty32)*) @@ -2266,52 +2305,52 @@ definition PACCellShuffle :: "(64)Word.word \<Rightarrow>((register_value),((64 " PACCellShuffle indata = ( (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (outdata :: 64 bits) . (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice0 indata (( 52 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice indata (( 52 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice0 indata (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice indata (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice0 indata (( 44 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice indata (( 44 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice0 indata (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice indata (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice0 indata (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice indata (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice0 indata (( 48 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice indata (( 48 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice0 indata (( 4 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice indata (( 4 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice0 indata (( 40 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice indata (( 40 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice0 indata (( 32 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice indata (( 32 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice0 indata (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice indata (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice0 indata (( 56 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice indata (( 56 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) ((slice0 indata (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) ((slice indata (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice0 indata (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice indata (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice0 indata (( 36 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice indata (( 36 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice0 indata (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice indata (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) ((slice0 indata (( 60 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) ((slice indata (( 60 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in return outdata))))))))))))))))))" @@ -2322,52 +2361,52 @@ definition PACCellInvShuffle :: "(64)Word.word \<Rightarrow>((register_value),( " PACCellInvShuffle indata = ( (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (outdata :: 64 bits) . (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice0 indata (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice indata (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice0 indata (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice indata (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice0 indata (( 48 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice indata (( 48 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice0 indata (( 36 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice indata (( 36 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice0 indata (( 56 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice indata (( 56 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice0 indata (( 44 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice indata (( 44 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice0 indata (( 4 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice indata (( 4 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice0 indata (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice indata (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice0 indata (( 32 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice indata (( 32 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice0 indata (( 52 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice indata (( 52 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice0 indata (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice indata (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) ((slice0 indata (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) ((slice indata (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice0 indata (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice indata (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice0 indata (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice indata (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice0 indata (( 40 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice indata (( 40 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) ((slice0 indata (( 60 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) ((slice indata (( 60 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in return outdata))))))))))))))))))" @@ -2584,7 +2623,7 @@ definition FPDecodeRounding :: "(2)Word.word \<Rightarrow> FPRounding " where (*val FPRoundingMode : mword ty32 -> FPRounding*) definition FPRoundingMode :: "(32)Word.word \<Rightarrow> FPRounding " where - " FPRoundingMode fpcr = ( FPDecodeRounding ((slice0 fpcr (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)))" + " FPRoundingMode fpcr = ( FPDecodeRounding ((slice fpcr (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)))" (*val __UNKNOWN_FPConvOp : unit -> FPConvOp*) @@ -2725,21 +2764,21 @@ definition TweakCellRot :: "(4)Word.word \<Rightarrow>((register_value),((4)Wor " TweakCellRot incell_name = ( (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (outcell :: 4 bits) . (let (outcell :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 3 :: int)::ii) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 3 :: int)::ii) ((xor_vec (vec_of_bits [access_vec_dec incell_name (( 0 :: int)::ii)] :: 1 Word.word) (vec_of_bits [access_vec_dec incell_name (( 1 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) :: 4 Word.word)) in (let (outcell :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 2 :: int)::ii) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 2 :: int)::ii) (vec_of_bits [access_vec_dec incell_name (( 3 :: int)::ii)] :: 1 Word.word) :: 4 Word.word)) in (let (outcell :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 1 :: int)::ii) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 1 :: int)::ii) (vec_of_bits [access_vec_dec incell_name (( 2 :: int)::ii)] :: 1 Word.word) :: 4 Word.word)) in (let (outcell :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 0 :: int)::ii) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 0 :: int)::ii) (vec_of_bits [access_vec_dec incell_name (( 1 :: int)::ii)] :: 1 Word.word) :: 4 Word.word)) in return outcell))))))" @@ -2751,53 +2790,53 @@ definition TweakShuffle :: "(64)Word.word \<Rightarrow>((register_value),((64)W " TweakShuffle indata = ( (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (outdata :: 64 bits) . (let (outdata :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice0 indata (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) ((slice indata (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice0 indata (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice indata (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in - (TweakCellRot ((slice0 indata (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__0 :: + (TweakCellRot ((slice indata (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__0 :: 4 Word.word) . - (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) w__0 :: 64 Word.word)) in + (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) w__0 :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice0 indata (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice indata (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in - (TweakCellRot ((slice0 indata (( 44 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 :: + (TweakCellRot ((slice indata (( 44 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 :: 4 Word.word) . - (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) w__1 :: 64 Word.word)) in + (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) w__1 :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice0 indata (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice indata (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice0 indata (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) ((slice indata (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in - (TweakCellRot ((slice0 indata (( 32 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__2 :: + (TweakCellRot ((slice indata (( 32 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__2 :: 4 Word.word) . - (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) w__2 :: 64 Word.word)) in + (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) w__2 :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice0 indata (( 48 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) ((slice indata (( 48 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice0 indata (( 52 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) ((slice indata (( 52 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice0 indata (( 56 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) ((slice indata (( 56 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in - (TweakCellRot ((slice0 indata (( 60 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__3 :: + (TweakCellRot ((slice indata (( 60 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__3 :: 4 Word.word) . - (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) w__3 :: 64 Word.word)) in - (TweakCellRot ((slice0 indata (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: + (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) w__3 :: 64 Word.word)) in + (TweakCellRot ((slice indata (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: 4 Word.word) . - (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) w__4 :: 64 Word.word)) in + (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) w__4 :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice0 indata (( 4 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice indata (( 4 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in - (TweakCellRot ((slice0 indata (( 40 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__5 :: + (TweakCellRot ((slice indata (( 40 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__5 :: 4 Word.word) . - (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) w__5 :: 64 Word.word)) in - (TweakCellRot ((slice0 indata (( 36 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__6 :: + (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) w__5 :: 64 Word.word)) in + (TweakCellRot ((slice indata (( 36 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__6 :: 4 Word.word) . - (let (outdata :: 64 bits) = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) w__6 :: 64 Word.word)) in + (let (outdata :: 64 bits) = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) w__6 :: 64 Word.word)) in return outdata)))))))))))))))))))))))))" @@ -2807,19 +2846,19 @@ definition TweakCellInvRot :: "(4)Word.word \<Rightarrow>((register_value),((4) " TweakCellInvRot incell_name = ( (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (outcell :: 4 bits) . (let (outcell :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 3 :: int)::ii) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 3 :: int)::ii) (vec_of_bits [access_vec_dec incell_name (( 2 :: int)::ii)] :: 1 Word.word) :: 4 Word.word)) in (let (outcell :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 2 :: int)::ii) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 2 :: int)::ii) (vec_of_bits [access_vec_dec incell_name (( 1 :: int)::ii)] :: 1 Word.word) :: 4 Word.word)) in (let (outcell :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 1 :: int)::ii) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 1 :: int)::ii) (vec_of_bits [access_vec_dec incell_name (( 0 :: int)::ii)] :: 1 Word.word) :: 4 Word.word)) in (let (outcell :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 0 :: int)::ii) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) outcell (( 0 :: int)::ii) ((xor_vec (vec_of_bits [access_vec_dec incell_name (( 0 :: int)::ii)] :: 1 Word.word) (vec_of_bits [access_vec_dec incell_name (( 3 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) @@ -2832,54 +2871,54 @@ definition TweakCellInvRot :: "(4)Word.word \<Rightarrow>((register_value),((4) definition TweakInvShuffle :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where " TweakInvShuffle indata = ( (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (outdata :: 64 bits) . - (TweakCellInvRot ((slice0 indata (( 48 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__0 :: + (TweakCellInvRot ((slice indata (( 48 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__0 :: 4 Word.word) . - (let (outdata :: 64 bits) = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) w__0 :: 64 Word.word)) in + (let (outdata :: 64 bits) = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 0 :: int)::ii) w__0 :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice0 indata (( 52 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 4 :: int)::ii) ((slice indata (( 52 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice0 indata (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 8 :: int)::ii) ((slice indata (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice0 indata (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 12 :: int)::ii) ((slice indata (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice0 indata (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 16 :: int)::ii) ((slice indata (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice0 indata (( 4 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 20 :: int)::ii) ((slice indata (( 4 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in - (TweakCellInvRot ((slice0 indata (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 :: + (TweakCellInvRot ((slice indata (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 :: 4 Word.word) . - (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) w__1 :: 64 Word.word)) in + (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 24 :: int)::ii) w__1 :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice0 indata (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 28 :: int)::ii) ((slice indata (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in - (TweakCellInvRot ((slice0 indata (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__2 :: + (TweakCellInvRot ((slice indata (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__2 :: 4 Word.word) . - (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) w__2 :: 64 Word.word)) in - (TweakCellInvRot ((slice0 indata (( 60 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__3 :: + (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 32 :: int)::ii) w__2 :: 64 Word.word)) in + (TweakCellInvRot ((slice indata (( 60 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__3 :: 4 Word.word) . - (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) w__3 :: 64 Word.word)) in - (TweakCellInvRot ((slice0 indata (( 56 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: + (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 36 :: int)::ii) w__3 :: 64 Word.word)) in + (TweakCellInvRot ((slice indata (( 56 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: 4 Word.word) . - (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) w__4 :: 64 Word.word)) in - (TweakCellInvRot ((slice0 indata (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__5 :: + (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 40 :: int)::ii) w__4 :: 64 Word.word)) in + (TweakCellInvRot ((slice indata (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__5 :: 4 Word.word) . - (let outdata = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) w__5 :: 64 Word.word)) in + (let outdata = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 44 :: int)::ii) w__5 :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice0 indata (( 32 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 48 :: int)::ii) ((slice indata (( 32 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice0 indata (( 36 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 52 :: int)::ii) ((slice indata (( 36 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let outdata = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice0 indata (( 40 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 56 :: int)::ii) ((slice indata (( 40 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in - (TweakCellInvRot ((slice0 indata (( 44 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__6 :: + (TweakCellInvRot ((slice indata (( 44 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__6 :: 4 Word.word) . - (let (outdata :: 64 bits) = ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) w__6 :: 64 Word.word)) in + (let (outdata :: 64 bits) = ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) outdata (( 60 :: int)::ii) w__6 :: 64 Word.word)) in return outdata)))))))))))))))))))))))))" @@ -3197,7 +3236,7 @@ definition AArch64_SysRegWrite :: " int \<Rightarrow> int \<Rightarrow> int \<R definition AArch64_SysRegRead :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where " AArch64_SysRegRead arg0 arg1 arg2 arg3 arg4 = ( - (let g__614 = (arg0, arg1, arg2, arg3, arg4) in + (let g__301 = (arg0, arg1, arg2, arg3, arg4) in assert_exp False (''Tried to read system register'') \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)))" @@ -3220,13 +3259,13 @@ definition AArch64_ReportDeferredSError :: "(25)Word.word \<Rightarrow>((regist " AArch64_ReportDeferredSError syndrome = ( (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (target :: 64 bits) . (let (target :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) target (( 31 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) in + ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) target (( 31 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) in (let (target :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) target (( 24 :: int)::ii) + ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) target (( 24 :: int)::ii) (vec_of_bits [access_vec_dec syndrome (( 24 :: int)::ii)] :: 1 Word.word) :: 64 Word.word)) in (let (target :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 24 :: int)::ii) target (( 0 :: int)::ii) ((slice0 syndrome (( 0 :: int)::ii) (( 24 :: int)::ii) :: 24 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 24 :: int)::ii) target (( 0 :: int)::ii) ((slice syndrome (( 0 :: int)::ii) (( 24 :: int)::ii) :: 24 Word.word)) :: 64 Word.word)) in return target)))))" @@ -3382,23 +3421,23 @@ definition aget_SP :: " int \<Rightarrow> unit \<Rightarrow>((register_value),( read_reg PSTATE_ref) \<bind> (\<lambda> (w__0 :: ProcState) . if ((((ProcState_SP w__0) = (vec_of_bits [B0] :: 1 Word.word)))) then (read_reg SP_EL0_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . - return ((slice0 w__1 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) + return ((slice w__1 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) else read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . - (let p__613 = ((ProcState_EL w__2)) in - (let pat0 = p__613 in + (let p__300 = ((ProcState_EL w__2)) in + (let pat0 = p__300 in if (((pat0 = EL0))) then (read_reg SP_EL0_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . - return ((slice0 w__3 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) + return ((slice w__3 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) else if (((pat0 = EL1))) then (read_reg SP_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 bits) . - return ((slice0 w__4 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) + return ((slice w__4 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) else if (((pat0 = EL2))) then (read_reg SP_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . - return ((slice0 w__5 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) + return ((slice w__5 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) else (read_reg SP_EL3_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 bits) . - return ((slice0 w__6 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))))))))" + return ((slice w__6 (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))))))))" (*val __IMPDEF_integer : string -> ii*) @@ -3473,7 +3512,7 @@ definition RoundTowardsZero :: " real \<Rightarrow> int " where definition Restarting :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where " Restarting _ = ( (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . - return (((((slice0 w__0 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word))))))" + return (((((slice w__0 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word))))))" (*val PtrHasUpperAndLowerAddRanges : unit -> M bool*) @@ -3770,12 +3809,12 @@ definition aget_Vpart :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow (if (((part = (( 0 :: int)::ii)))) then (assert_exp ((((((width__tv = (( 8 :: int)::ii)))) \<or> ((((((width__tv = (( 16 :: int)::ii)))) \<or> ((((((width__tv = (( 32 :: int)::ii)))) \<or> (((width__tv = (( 64 :: int)::ii))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))'') \<then> read_reg V_ref) \<bind> (\<lambda> (w__0 :: ( 128 bits) list) . - return ((slice0 ((access_list_dec w__0 n :: 128 Word.word)) (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) + return ((slice ((access_list_dec w__0 n :: 128 Word.word)) (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) else (assert_exp (((width__tv = (( 64 :: int)::ii)))) (''(width == 64)'') \<then> read_reg V_ref) \<bind> (\<lambda> (w__1 :: ( 128 bits) list) . return ((Word.ucast - ((slice0 ((access_list_dec w__1 n :: 128 Word.word)) (( 64 :: int)::ii) (( 64 :: int)::ii) :: ( 'width::len)Word.word)) + ((slice ((access_list_dec w__1 n :: 128 Word.word)) (( 64 :: int)::ii) (( 64 :: int)::ii) :: ( 'width::len)Word.word)) :: ( 'width::len)Word.word)))))" @@ -3786,7 +3825,7 @@ definition aget_V :: " int \<Rightarrow> int \<Rightarrow>((register_value),((' ((assert_exp (((((n \<ge> (( 0 :: int)::ii))) \<and> ((n \<le> (( 31 :: int)::ii)))))) (''((n >= 0) && (n <= 31))'') \<then> assert_exp ((((((width__tv = (( 8 :: int)::ii)))) \<or> ((((((width__tv = (( 16 :: int)::ii)))) \<or> ((((((width__tv = (( 32 :: int)::ii)))) \<or> ((((((width__tv = (( 64 :: int)::ii)))) \<or> (((width__tv = (( 128 :: int)::ii)))))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || ((width == 64) || (width == 128)))))'')) \<then> read_reg V_ref) \<bind> (\<lambda> (w__0 :: ( 128 bits) list) . - return ((slice0 ((access_list_dec w__0 n :: 128 Word.word)) (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))))" + return ((slice ((access_list_dec w__0 n :: 128 Word.word)) (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))))" (*val LookUpRIndex : ii -> mword ty5 -> M ii*) @@ -3795,19 +3834,18 @@ definition LookUpRIndex :: " int \<Rightarrow>(5)Word.word \<Rightarrow>((regis " LookUpRIndex n mode = ( (assert_exp (((((n \<ge> (( 0 :: int)::ii))) \<and> ((n \<le> (( 14 :: int)::ii)))))) (''((n >= 0) && (n <= 14))'') \<then> undefined_int () ) \<bind> (\<lambda> (result :: ii) . - (let l__308 = n in - if (((l__308 = (( 8 :: int)::ii)))) then RBankSelect mode (( 8 :: int)::ii) (( 24 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) - else if (((l__308 = (( 9 :: int)::ii)))) then - RBankSelect mode (( 9 :: int)::ii) (( 25 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) - else if (((l__308 = (( 10 :: int)::ii)))) then + (let p00 = n in + if (((p00 = (( 8 :: int)::ii)))) then RBankSelect mode (( 8 :: int)::ii) (( 24 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) (( 8 :: int)::ii) + else if (((p00 = (( 9 :: int)::ii)))) then RBankSelect mode (( 9 :: int)::ii) (( 25 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) (( 9 :: int)::ii) + else if (((p00 = (( 10 :: int)::ii)))) then RBankSelect mode (( 10 :: int)::ii) (( 26 :: int)::ii) (( 10 :: int)::ii) (( 10 :: int)::ii) (( 10 :: int)::ii) (( 10 :: int)::ii) (( 10 :: int)::ii) - else if (((l__308 = (( 11 :: int)::ii)))) then + else if (((p00 = (( 11 :: int)::ii)))) then RBankSelect mode (( 11 :: int)::ii) (( 27 :: int)::ii) (( 11 :: int)::ii) (( 11 :: int)::ii) (( 11 :: int)::ii) (( 11 :: int)::ii) (( 11 :: int)::ii) - else if (((l__308 = (( 12 :: int)::ii)))) then + else if (((p00 = (( 12 :: int)::ii)))) then RBankSelect mode (( 12 :: int)::ii) (( 28 :: int)::ii) (( 12 :: int)::ii) (( 12 :: int)::ii) (( 12 :: int)::ii) (( 12 :: int)::ii) (( 12 :: int)::ii) - else if (((l__308 = (( 13 :: int)::ii)))) then + else if (((p00 = (( 13 :: int)::ii)))) then RBankSelect mode (( 13 :: int)::ii) (( 29 :: int)::ii) (( 17 :: int)::ii) (( 19 :: int)::ii) (( 21 :: int)::ii) (( 23 :: int)::ii) (( 15 :: int)::ii) - else if (((l__308 = (( 14 :: int)::ii)))) then + else if (((p00 = (( 14 :: int)::ii)))) then RBankSelect mode (( 14 :: int)::ii) (( 30 :: int)::ii) (( 16 :: int)::ii) (( 18 :: int)::ii) (( 20 :: int)::ii) (( 22 :: int)::ii) (( 14 :: int)::ii) else return n)))" @@ -3851,7 +3889,7 @@ definition BitReverse :: "('N::len)Word.word \<Rightarrow>((register_value),((' (let (result :: 'N bits) = (foreach (index_list (( 0 :: int)::ii) ((((int (size data))) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result (\<lambda> i result . - (set_slice0 ((int (size data))) (( 1 :: int)::ii) result + (set_slice ((int (size data))) (( 1 :: int)::ii) result ((((((int (size data))) - i)) - (( 1 :: int)::ii))) (vec_of_bits [access_vec_dec data i] :: 1 Word.word) :: ( 'N::len)Word.word))) in @@ -3864,7 +3902,7 @@ definition NextInstrAddr :: " int \<Rightarrow> unit \<Rightarrow>((register_va " NextInstrAddr (N__tv :: int) _ = ( (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . ThisInstrLength () \<bind> (\<lambda> (w__1 :: ii) . - return ((slice0 ((add_vec_int w__0 ((((ex_int w__1)) div (( 8 :: int)::ii))) :: 64 Word.word)) (( 0 :: int)::ii) + return ((slice ((add_vec_int w__0 ((((ex_int w__1)) div (( 8 :: int)::ii))) :: 64 Word.word)) (( 0 :: int)::ii) N__tv :: ( 'N::len)Word.word)))))" @@ -3950,12 +3988,12 @@ definition RotCell :: "(4)Word.word \<Rightarrow> int \<Rightarrow>((register_v (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (tmp :: 8 bits) . (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (outcell :: 4 bits) . (let (tmp :: 8 bits) = - ((set_slice0 (( 8 :: int)::ii) (( 8 :: int)::ii) tmp (( 0 :: int)::ii) - ((concat_vec ((slice0 incell_name (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) - ((slice0 incell_name (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 8 :: int)::ii) (( 8 :: int)::ii) tmp (( 0 :: int)::ii) + ((concat_vec ((slice incell_name (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((slice incell_name (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 8 Word.word)) :: 8 Word.word)) in - (let (outcell :: 4 bits) = ((slice0 tmp (((( 4 :: int)::ii) - amount)) (( 4 :: int)::ii) :: 4 Word.word)) in + (let (outcell :: 4 bits) = ((slice tmp (((( 4 :: int)::ii) - amount)) (( 4 :: int)::ii) :: 4 Word.word)) in return outcell)))))" @@ -3963,8 +4001,8 @@ definition RotCell :: "(4)Word.word \<Rightarrow> int \<Rightarrow>((register_v definition FPNeg :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " FPNeg op1 = ( - (let l__305 = (int (size op1)) in - if (((l__305 = (( 16 :: int)::ii)))) then + (let p00 = (int (size op1)) in + if (((p00 = (( 16 :: int)::ii)))) then (let (op1 :: 16 Word.word) = ((Word.ucast op1 :: 16 Word.word)) in assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> return ((Word.ucast @@ -3973,10 +4011,10 @@ definition FPNeg :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le (vec_of_bits [access_vec_dec op1 (((( 16 :: int)::ii) - (( 1 :: int)::ii)))] :: 1 Word.word) :: 1 Word.word)) - ((slice0 op1 (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii))) :: 15 Word.word)) + ((slice op1 (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii))) :: 15 Word.word)) :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word))) - else if (((l__305 = (( 32 :: int)::ii)))) then + else if (((p00 = (( 32 :: int)::ii)))) then (let (op1 :: 32 Word.word) = ((Word.ucast op1 :: 32 Word.word)) in assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> return ((Word.ucast @@ -3985,10 +4023,10 @@ definition FPNeg :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le (vec_of_bits [access_vec_dec op1 (((( 32 :: int)::ii) - (( 1 :: int)::ii)))] :: 1 Word.word) :: 1 Word.word)) - ((slice0 op1 (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii))) :: 31 Word.word)) + ((slice op1 (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii))) :: 31 Word.word)) :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word))) - else if (((l__305 = (( 64 :: int)::ii)))) then + else if (((p00 = (( 64 :: int)::ii)))) then (let (op1 :: 64 Word.word) = ((Word.ucast op1 :: 64 Word.word)) in assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> return ((Word.ucast @@ -3997,7 +4035,7 @@ definition FPNeg :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le (vec_of_bits [access_vec_dec op1 (((( 64 :: int)::ii) - (( 1 :: int)::ii)))] :: 1 Word.word) :: 1 Word.word)) - ((slice0 op1 (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii))) :: 63 Word.word)) + ((slice op1 (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii))) :: 63 Word.word)) :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word))) else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> exit0 () ))" @@ -4007,29 +4045,29 @@ definition FPNeg :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le definition FPAbs :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " FPAbs op1 = ( - (let l__302 = (int (size op1)) in - if (((l__302 = (( 16 :: int)::ii)))) then + (let p00 = (int (size op1)) in + if (((p00 = (( 16 :: int)::ii)))) then (let (op1 :: 16 Word.word) = ((Word.ucast op1 :: 16 Word.word)) in assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> return ((Word.ucast ((concat_vec (vec_of_bits [B0] :: 1 Word.word) - ((slice0 op1 (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii))) :: 15 Word.word)) + ((slice op1 (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii))) :: 15 Word.word)) :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word))) - else if (((l__302 = (( 32 :: int)::ii)))) then + else if (((p00 = (( 32 :: int)::ii)))) then (let (op1 :: 32 Word.word) = ((Word.ucast op1 :: 32 Word.word)) in assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> return ((Word.ucast ((concat_vec (vec_of_bits [B0] :: 1 Word.word) - ((slice0 op1 (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii))) :: 31 Word.word)) + ((slice op1 (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii))) :: 31 Word.word)) :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word))) - else if (((l__302 = (( 64 :: int)::ii)))) then + else if (((p00 = (( 64 :: int)::ii)))) then (let (op1 :: 64 Word.word) = ((Word.ucast op1 :: 64 Word.word)) in assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> return ((Word.ucast ((concat_vec (vec_of_bits [B0] :: 1 Word.word) - ((slice0 op1 (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii))) :: 63 Word.word)) + ((slice op1 (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii))) :: 63 Word.word)) :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word))) else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> exit0 () ))" @@ -4114,23 +4152,6 @@ definition EncodeLDFSC :: " Fault \<Rightarrow> int \<Rightarrow>((register_val )))" -(*val BigEndianReverse : forall 'width . Size 'width => mword 'width -> M (mword 'width)*) - -definition BigEndianReverse :: "('width::len)Word.word \<Rightarrow>((register_value),(('width::len)Word.word),(exception))monad " where - " BigEndianReverse value_name = ( - assert_exp ((((((((int (size value_name))) = (( 8 :: int)::ii)))) \<or> ((((((((int (size value_name))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size value_name))) = (( 32 :: int)::ii)))) \<or> ((((((((int (size value_name))) = (( 64 :: int)::ii)))) \<or> (((((int (size value_name))) = (( 128 :: int)::ii)))))))))))))))) ('''') \<then> - ((let (result :: 'width bits) = - ((replicate_bits (vec_of_bits [B0] :: 1 Word.word) ((int (size value_name))) :: ( 'width::len)Word.word)) in - (let (result :: 'width bits) = - (foreach (index_list (( 0 :: int)::ii) ((((int (size result))) - (( 1 :: int)::ii))) (( 8 :: int)::ii)) result - (\<lambda> i result . - (update_subrange_vec_dec result ((i + (( 7 :: int)::ii))) i - ((subrange_vec_dec value_name - ((((((int (size result))) - i)) - (( 1 :: int)::ii))) - ((((((int (size result))) - i)) - (( 8 :: int)::ii))) - :: 8 Word.word)) - :: ( 'width::len)Word.word))) in - return result))))" (*val AArch32_ReportHypEntry : ExceptionRecord -> M unit*) @@ -4156,25 +4177,25 @@ definition AArch32_ReportHypEntry :: " ExceptionRecord \<Rightarrow>((register_ :: 7 Word.word)) iss :: 32 Word.word)) \<then> (if ((((((typ1 = Exception_InstructionAbort))) \<or> (((typ1 = Exception_PCAlignment)))))) then - (write_reg HIFAR_ref ((slice0(ExceptionRecord_vaddress exception) (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \<then> + (write_reg HIFAR_ref ((slice(ExceptionRecord_vaddress exception) (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \<then> (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__0 :: 32 bits) . write_reg HDFAR_ref w__0) else if (((typ1 = Exception_DataAbort))) then (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . write_reg HIFAR_ref w__1 \<then> - write_reg HDFAR_ref ((slice0(ExceptionRecord_vaddress exception) (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))) + write_reg HDFAR_ref ((slice(ExceptionRecord_vaddress exception) (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))) else return () )) \<then> (if(ExceptionRecord_ipavalid exception) then (read_reg HPFAR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . write_reg HPFAR_ref - ((set_slice0 (( 32 :: int)::ii) (( 28 :: int)::ii) w__2 (( 4 :: int)::ii) - ((slice0(ExceptionRecord_ipaddress exception) (( 12 :: int)::ii) (( 28 :: int)::ii) :: 28 Word.word)) + ((set_slice (( 32 :: int)::ii) (( 28 :: int)::ii) w__2 (( 4 :: int)::ii) + ((slice(ExceptionRecord_ipaddress exception) (( 12 :: int)::ii) (( 28 :: int)::ii) :: 28 Word.word)) :: 32 Word.word))) else (read_reg HPFAR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . (undefined_bitvector (( 28 :: int)::ii) :: ( 28 Word.word) M) \<bind> (\<lambda> (w__4 :: 28 Word.word) . - write_reg HPFAR_ref ((set_slice0 (( 32 :: int)::ii) (( 28 :: int)::ii) w__3 (( 4 :: int)::ii) w__4 :: 32 Word.word)))))))))))))))" + write_reg HPFAR_ref ((set_slice (( 32 :: int)::ii) (( 28 :: int)::ii) w__3 (( 4 :: int)::ii) w__4 :: 32 Word.word)))))))))))))))" (*val aset_Elem__0 : forall 'N 'size . Size 'N, Size 'size => mword 'N -> ii -> itself 'size -> mword 'size -> M (mword 'N)*) @@ -4187,7 +4208,7 @@ definition aset_Elem__0 :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>( (let vector_name = vector_name__arg in assert_exp (((((e \<ge> (( 0 :: int)::ii))) \<and> ((((((e + (( 1 :: int)::ii))) * size1)) \<le> ((int (size vector_name)))))))) (''((e >= 0) && (((e + 1) * size) <= N))'') \<then> ((let (vector_name :: ( 'N::len)Word.word) = - ((set_slice0 ((int (size vector_name))) size1 vector_name ((e * size1)) value_name + ((set_slice ((int (size vector_name))) size1 vector_name ((e * size1)) value_name :: ( 'N::len)Word.word)) in return vector_name)))))" @@ -4207,7 +4228,7 @@ definition aget_Elem__0 :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>( " aget_Elem__0 vector_name e size1 = ( (let size1 = (size_itself_int size1) in assert_exp (((((e \<ge> (( 0 :: int)::ii))) \<and> ((((((e + (( 1 :: int)::ii))) * size1)) \<le> ((int (size vector_name)))))))) (''((e >= 0) && (((e + 1) * size) <= N))'') \<then> - return ((slice0 vector_name ((e * size1)) size1 :: ( 'size::len)Word.word))))" + return ((slice vector_name ((e * size1)) size1 :: ( 'size::len)Word.word))))" definition aget_Elem__1 :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('size::len)Word.word),(exception))monad " where @@ -4286,7 +4307,8 @@ definition SatQ :: " int \<Rightarrow>('N::len)itself \<Rightarrow> bool \<Righ definition Replicate :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " Replicate (N__tv :: int) x = ( assert_exp (((((N__tv mod ((int (size x))))) = (( 0 :: int)::ii)))) (''((N MOD M) == 0)'') \<then> - return ((replicate_bits x ((N__tv div ((int (size x))))) :: ( 'N::len)Word.word)))" + ((let O1 = (N__tv div ((int (size x)))) in + assert_exp True ('''') \<then> return ((replicate_bits x ((N__tv div ((int (size x))))) :: ( 'N::len)Word.word)))))" (*val Zeros__0 : forall 'N . Size 'N => itself 'N -> mword 'N*) @@ -4382,8 +4404,8 @@ definition aset_SP :: "('width::len)Word.word \<Rightarrow>((register_value),(u write_reg SP_EL0_ref w__1) else read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . - (let p__612 = ((ProcState_EL w__2)) in - (let pat0 = p__612 in + (let p__299 = ((ProcState_EL w__2)) in + (let pat0 = p__299 in if (((pat0 = EL0))) then (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . write_reg SP_EL0_ref w__3) @@ -4439,7 +4461,7 @@ definition Poly32Mod2 :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Right (or_vec data ((sub_vec_int ((shiftl poly' i :: ( 'N::len)Word.word)) (( 32 :: int)::ii) :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word) else data)) in - return ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)))))))" + return ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)))))))" (*val LSL_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*) @@ -4474,7 +4496,7 @@ definition LSL :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>((register definition AArch32_ITAdvance :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " AArch32_ITAdvance _ = ( read_reg PSTATE_ref \<bind> (\<lambda> (w__0 :: ProcState) . - if (((((slice0(ProcState_IT w__0) (( 0 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then + if (((((slice(ProcState_IT w__0) (( 0 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then read_reg PSTATE_ref \<bind> (\<lambda> (w__1 :: ProcState) . write_reg PSTATE_ref @@ -4483,9 +4505,9 @@ definition AArch32_ITAdvance :: " unit \<Rightarrow>((register_value),(unit),(e read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . (let (tmp_2760 :: 8 bits) = ((ProcState_IT w__2)) in read_reg PSTATE_ref \<bind> (\<lambda> (w__3 :: ProcState) . - (LSL ((slice0(ProcState_IT w__3) (( 0 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) (( 1 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__4 :: + (LSL ((slice(ProcState_IT w__3) (( 0 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) (( 1 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__4 :: 5 Word.word) . - (let tmp_2760 = ((set_slice0 (( 8 :: int)::ii) (( 5 :: int)::ii) tmp_2760 (( 0 :: int)::ii) w__4 :: 8 Word.word)) in + (let tmp_2760 = ((set_slice (( 8 :: int)::ii) (( 5 :: int)::ii) tmp_2760 (( 0 :: int)::ii) w__4 :: 8 Word.word)) in read_reg PSTATE_ref \<bind> (\<lambda> (w__5 :: ProcState) . write_reg PSTATE_ref (w__5 (| ProcState_IT := tmp_2760 |))))))))))" @@ -4608,22 +4630,22 @@ definition GetPSRFromPSTATE :: " unit \<Rightarrow>((register_value),((32)Word. definition FPZero :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " FPZero (N__tv :: int) sign = ( - (let l__299 = N__tv in - if (((l__299 = (( 16 :: int)::ii)))) then + (let p00 = N__tv in + if (((p00 = (( 16 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in (let (exp :: 5 bits) = ((Zeros__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) in (let (frac :: 10 bits) = ((Zeros__0 ((make_the_value F :: 10 itself)) :: 10 Word.word)) in return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word)))))) - else if (((l__299 = (( 32 :: int)::ii)))) then + else if (((p00 = (( 32 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in (let (exp :: 8 bits) = ((Zeros__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) in (let (frac :: 23 bits) = ((Zeros__0 ((make_the_value F :: 23 itself)) :: 23 Word.word)) in return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word)))))) - else if (((l__299 = (( 64 :: int)::ii)))) then + else if (((p00 = (( 64 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in (let (exp :: 11 bits) = ((Zeros__0 ((make_the_value (( 11 :: int)::ii) :: 11 itself)) :: 11 Word.word)) in @@ -4698,8 +4720,8 @@ definition AArch32_PhysicalSErrorSyndrome :: " unit \<Rightarrow>((register_val definition VFPExpandImm :: " int \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " VFPExpandImm (N__tv :: int) imm8 = ( - (let l__296 = N__tv in - if (((l__296 = (( 16 :: int)::ii)))) then + (let p00 = N__tv in + if (((p00 = (( 16 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 :: int)::ii)] :: 1 Word.word)) in @@ -4718,7 +4740,7 @@ definition VFPExpandImm :: " int \<Rightarrow>(8)Word.word \<Rightarrow>((regis :: 10 Word.word)) in return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word))))))) - else if (((l__296 = (( 32 :: int)::ii)))) then + else if (((p00 = (( 32 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 :: int)::ii)] :: 1 Word.word)) in @@ -4737,7 +4759,7 @@ definition VFPExpandImm :: " int \<Rightarrow>(8)Word.word \<Rightarrow>((regis :: 23 Word.word)) in return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word))))))) - else if (((l__296 = (( 64 :: int)::ii)))) then + else if (((p00 = (( 64 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 :: int)::ii)] :: 1 Word.word)) in @@ -4842,8 +4864,8 @@ definition IsOnes :: "('N::len)Word.word \<Rightarrow> bool " where definition FPMaxNormal :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " FPMaxNormal (N__tv :: int) sign = ( - (let l__293 = N__tv in - if (((l__293 = (( 16 :: int)::ii)))) then + (let p00 = N__tv in + if (((p00 = (( 16 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in (let (exp :: 5 bits) = @@ -4854,7 +4876,7 @@ definition FPMaxNormal :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((regist (let (frac :: 10 bits) = ((Ones__0 ((make_the_value F :: 10 itself)) :: 10 Word.word)) in return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word)))))) - else if (((l__293 = (( 32 :: int)::ii)))) then + else if (((p00 = (( 32 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in (let (exp :: 8 bits) = @@ -4865,7 +4887,7 @@ definition FPMaxNormal :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((regist (let (frac :: 23 bits) = ((Ones__0 ((make_the_value F :: 23 itself)) :: 23 Word.word)) in return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word)))))) - else if (((l__293 = (( 64 :: int)::ii)))) then + else if (((p00 = (( 64 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in (let (exp :: 11 bits) = @@ -4883,22 +4905,22 @@ definition FPMaxNormal :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((regist definition FPInfinity :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " FPInfinity (N__tv :: int) sign = ( - (let l__290 = N__tv in - if (((l__290 = (( 16 :: int)::ii)))) then + (let p00 = N__tv in + if (((p00 = (( 16 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in (let (exp :: 5 bits) = ((Ones__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) in (let (frac :: 10 bits) = ((Zeros__0 ((make_the_value F :: 10 itself)) :: 10 Word.word)) in return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word)))))) - else if (((l__290 = (( 32 :: int)::ii)))) then + else if (((p00 = (( 32 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in (let (exp :: 8 bits) = ((Ones__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) in (let (frac :: 23 bits) = ((Zeros__0 ((make_the_value F :: 23 itself)) :: 23 Word.word)) in return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word)))))) - else if (((l__290 = (( 64 :: int)::ii)))) then + else if (((p00 = (( 64 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in (let (exp :: 11 bits) = ((Ones__0 ((make_the_value (( 11 :: int)::ii) :: 11 itself)) :: 11 Word.word)) in @@ -4912,8 +4934,8 @@ definition FPInfinity :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((registe definition FPDefaultNaN :: " int \<Rightarrow> unit \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " FPDefaultNaN (N__tv :: int) _ = ( - (let l__287 = N__tv in - if (((l__287 = (( 16 :: int)::ii)))) then + (let p00 = N__tv in + if (((p00 = (( 16 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in (let (sign :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in @@ -4926,7 +4948,7 @@ definition FPDefaultNaN :: " int \<Rightarrow> unit \<Rightarrow>((register_val ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word))))))) - else if (((l__287 = (( 32 :: int)::ii)))) then + else if (((p00 = (( 32 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in (let (sign :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in @@ -4939,7 +4961,7 @@ definition FPDefaultNaN :: " int \<Rightarrow> unit \<Rightarrow>((register_val ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) :: ( 'N::len)Word.word))))))) - else if (((l__287 = (( 64 :: int)::ii)))) then + else if (((p00 = (( 64 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in (let (sign :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in @@ -4965,40 +4987,40 @@ definition FPConvertNaN :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow>( (undefined_bitvector (( 51 :: int)::ii) :: ( 51 Word.word) M) \<bind> (\<lambda> (frac :: 51 bits) . (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec op1 ((((int (size op1))) - (( 1 :: int)::ii)))] :: 1 Word.word)) in - (let l__281 = (int (size op1)) in + (let p00 = (int (size op1)) in (let (frac :: 51 bits) = - (if (((l__281 = (( 64 :: int)::ii)))) then + (if (((p00 = (( 64 :: int)::ii)))) then (let (op1 :: 64 Word.word) = ((Word.ucast op1 :: 64 Word.word)) in - (slice0 op1 (( 0 :: int)::ii) (( 51 :: int)::ii) :: 51 Word.word)) - else if (((l__281 = (( 32 :: int)::ii)))) then + (slice op1 (( 0 :: int)::ii) (( 51 :: int)::ii) :: 51 Word.word)) + else if (((p00 = (( 32 :: int)::ii)))) then (let (op1 :: 32 Word.word) = ((Word.ucast op1 :: 32 Word.word)) in - (concat_vec ((slice0 op1 (( 0 :: int)::ii) (( 22 :: int)::ii) :: 22 Word.word)) + (concat_vec ((slice op1 (( 0 :: int)::ii) (( 22 :: int)::ii) :: 22 Word.word)) ((Zeros__0 ((make_the_value (( 29 :: int)::ii) :: 29 itself)) :: 29 Word.word)) :: 51 Word.word)) else (let (op1 :: 16 Word.word) = ((Word.ucast op1 :: 16 Word.word)) in - (concat_vec ((slice0 op1 (( 0 :: int)::ii) (( 9 :: int)::ii) :: 9 Word.word)) + (concat_vec ((slice op1 (( 0 :: int)::ii) (( 9 :: int)::ii) :: 9 Word.word)) ((Zeros__0 ((make_the_value (( 42 :: int)::ii) :: 42 itself)) :: 42 Word.word)) :: 51 Word.word))) in - (let l__284 = (int (size result)) in + (let p00 = (int (size result)) in (let (result :: 'M bits) = - (if (((l__284 = (( 64 :: int)::ii)))) then + (if (((p00 = (( 64 :: int)::ii)))) then (concat_vec ((concat_vec sign ((Ones__0 ((make_the_value (((( 64 :: int)::ii) - (( 52 :: int)::ii))) )) :: 12 Word.word)) :: 13 Word.word)) frac :: ( 'M::len)Word.word) - else if (((l__284 = (( 32 :: int)::ii)))) then + else if (((p00 = (( 32 :: int)::ii)))) then (concat_vec ((concat_vec sign ((Ones__0 ((make_the_value (((( 32 :: int)::ii) - (( 23 :: int)::ii))) )) :: 9 Word.word)) - :: 10 Word.word)) ((slice0 frac (( 29 :: int)::ii) (( 22 :: int)::ii) :: 22 Word.word)) + :: 10 Word.word)) ((slice frac (( 29 :: int)::ii) (( 22 :: int)::ii) :: 22 Word.word)) :: ( 'M::len)Word.word) else (concat_vec ((concat_vec sign - ((Ones__0 ((make_the_value ((l__284 - (( 10 :: int)::ii))) )) :: 6 Word.word)) - :: 7 Word.word)) ((slice0 frac (( 42 :: int)::ii) (( 9 :: int)::ii) :: 9 Word.word)) + ((Ones__0 ((make_the_value ((p00 - (( 10 :: int)::ii))) )) :: 6 Word.word)) + :: 7 Word.word)) ((slice frac (( 42 :: int)::ii) (( 9 :: int)::ii) :: 9 Word.word)) :: ( 'M::len)Word.word)) in return result))))))))" @@ -5014,7 +5036,7 @@ definition ExcVectorBase :: " unit \<Rightarrow>((register_value),((32)Word.wor :: 32 Word.word)) else (read_reg VBAR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . - return ((concat_vec ((slice0 w__1 (( 5 :: int)::ii) (( 27 :: int)::ii) :: 27 Word.word)) + return ((concat_vec ((slice w__1 (( 5 :: int)::ii) (( 27 :: int)::ii) :: 27 Word.word)) ((Zeros__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) :: 32 Word.word)))))" @@ -5027,69 +5049,69 @@ definition PACSub :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.wo (let (Toutput :: 64 bits) = (foreach (index_list (( 0 :: int)::ii) (( 15 :: int)::ii) (( 1 :: int)::ii)) Toutput (\<lambda> i Toutput . - (let b__0 = ((slice0 Tinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) in + (let b__0 = ((slice Tinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) in if (((b__0 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word) :: 64 Word.word) else - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word) :: 64 Word.word)))) in return Toutput)))" @@ -5104,78 +5126,80 @@ definition PACMult :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.w (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (t2 :: 4 bits) . (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (t3 :: 4 bits) . (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (Soutput :: 64 bits) . - (foreachM (index_list (( 0 :: int)::ii) (( 3 :: int)::ii) (( 1 :: int)::ii)) Soutput - (\<lambda> i Soutput . - (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (foreachM (index_list (( 0 :: int)::ii) (( 3 :: int)::ii) (( 1 :: int)::ii)) (Soutput, t0, t1, t2, t3) + (\<lambda> i varstup . (let (Soutput, t0, t1, t2, t3) = varstup in + (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) (( 1 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__0 :: 4 Word.word) . - (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) (( 2 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 :: 4 Word.word) . - (let t0 = ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t0 (( 0 :: int)::ii) ((xor_vec w__0 w__1 :: 4 Word.word)) :: 4 Word.word)) in - (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) (( 1 :: int)::ii) + (let t0 = ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t0 (( 0 :: int)::ii) ((xor_vec w__0 w__1 :: 4 Word.word)) :: 4 Word.word)) in + (RotCell ((slice Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) (( 1 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__2 :: 4 Word.word) . (let t0 = - ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t0 (( 0 :: int)::ii) - ((xor_vec ((slice0 t0 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) w__2 :: 4 Word.word)) + ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t0 (( 0 :: int)::ii) + ((xor_vec ((slice t0 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) w__2 :: 4 Word.word)) :: 4 Word.word)) in - (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) (( 1 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__3 :: 4 Word.word) . - (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) (( 1 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: 4 Word.word) . - (let t1 = ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t1 (( 0 :: int)::ii) ((xor_vec w__3 w__4 :: 4 Word.word)) :: 4 Word.word)) in - (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) (( 2 :: int)::ii) + (let t1 = ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t1 (( 0 :: int)::ii) ((xor_vec w__3 w__4 :: 4 Word.word)) :: 4 Word.word)) in + (RotCell ((slice Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) (( 2 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__5 :: 4 Word.word) . (let t1 = - ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t1 (( 0 :: int)::ii) - ((xor_vec ((slice0 t1 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) w__5 :: 4 Word.word)) + ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t1 (( 0 :: int)::ii) + ((xor_vec ((slice t1 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) w__5 :: 4 Word.word)) :: 4 Word.word)) in - (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) (( 2 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__6 :: 4 Word.word) . - (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) (( 1 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__7 :: 4 Word.word) . - (let t2 = ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t2 (( 0 :: int)::ii) ((xor_vec w__6 w__7 :: 4 Word.word)) :: 4 Word.word)) in - (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) (( 1 :: int)::ii) + (let t2 = ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t2 (( 0 :: int)::ii) ((xor_vec w__6 w__7 :: 4 Word.word)) :: 4 Word.word)) in + (RotCell ((slice Sinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) (( 1 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__8 :: 4 Word.word) . (let t2 = - ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t2 (( 0 :: int)::ii) - ((xor_vec ((slice0 t2 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) w__8 :: 4 Word.word)) + ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t2 (( 0 :: int)::ii) + ((xor_vec ((slice t2 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) w__8 :: 4 Word.word)) :: 4 Word.word)) in - (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) (( 1 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__9 :: 4 Word.word) . - (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) (( 2 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__10 :: 4 Word.word) . - (let t3 = ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t3 (( 0 :: int)::ii) ((xor_vec w__9 w__10 :: 4 Word.word)) :: 4 Word.word)) in - (RotCell ((slice0 Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) + (let t3 = ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t3 (( 0 :: int)::ii) ((xor_vec w__9 w__10 :: 4 Word.word)) :: 4 Word.word)) in + (RotCell ((slice Sinput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) (( 4 :: int)::ii) :: 4 Word.word)) (( 1 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__11 :: 4 Word.word) . (let (t3 :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 4 :: int)::ii) t3 (( 0 :: int)::ii) - ((xor_vec ((slice0 t3 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) w__11 :: 4 Word.word)) + ((set_slice (( 4 :: int)::ii) (( 4 :: int)::ii) t3 (( 0 :: int)::ii) + ((xor_vec ((slice t3 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) w__11 :: 4 Word.word)) :: 4 Word.word)) in (let (Soutput :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * i)) - ((slice0 t3 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * i)) + ((slice t3 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (Soutput :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) - ((slice0 t2 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 4 :: int)::ii))))) + ((slice t2 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (Soutput :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) - ((slice0 t1 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 8 :: int)::ii))))) + ((slice t1 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in (let (Soutput :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) - ((slice0 t0 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Soutput (((( 4 :: int)::ii) * ((i + (( 12 :: int)::ii))))) + ((slice t0 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) :: 64 Word.word)) in - return Soutput))))))))))))))))))))))))))))))))" + return (Soutput, t0, t1, t2, t3)))))))))))))))))))))))))))) \<bind> (\<lambda> varstup . (let ((Soutput :: 64 bits), (t0 :: 4 + bits), (t1 :: 4 bits), (t2 :: 4 bits), (t3 :: 4 bits)) = varstup in + return Soutput))))))))" (*val PACInvSub : mword ty64 -> M (mword ty64)*) @@ -5186,69 +5210,69 @@ definition PACInvSub :: "(64)Word.word \<Rightarrow>((register_value),((64)Word (let (Toutput :: 64 bits) = (foreach (index_list (( 0 :: int)::ii) (( 15 :: int)::ii) (( 1 :: int)::ii)) Toutput (\<lambda> i Toutput . - (let b__0 = ((slice0 Tinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) in + (let b__0 = ((slice Tinput (((( 4 :: int)::ii) * i)) (( 4 :: int)::ii) :: 4 Word.word)) in if (((b__0 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word) :: 64 Word.word) else if (((b__0 = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word) :: 64 Word.word) else - (set_slice0 (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) + (set_slice (( 64 :: int)::ii) (( 4 :: int)::ii) Toutput (((( 4 :: int)::ii) * i)) (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word) :: 64 Word.word)))) in return Toutput)))" @@ -5281,7 +5305,7 @@ definition ComputePAC :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow ((let modk0 = ((concat_vec ((concat_vec (vec_of_bits [access_vec_dec key0 (( 0 :: int)::ii)] :: 1 Word.word) - ((slice0 key0 (( 2 :: int)::ii) (( 62 :: int)::ii) :: 62 Word.word)) + ((slice key0 (( 2 :: int)::ii) (( 62 :: int)::ii) :: 62 Word.word)) :: 63 Word.word)) ((xor_vec (vec_of_bits [access_vec_dec key0 (( 63 :: int)::ii)] :: 1 Word.word) (vec_of_bits [access_vec_dec key0 (( 1 :: int)::ii)] :: 1 Word.word) @@ -5302,7 +5326,7 @@ definition ComputePAC :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow else return workingval) \<bind> (\<lambda> (workingval :: 64 bits) . (PACSub workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 bits) . (let workingval = w__13 in - (TweakShuffle ((slice0 runningmod (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64 + (TweakShuffle ((slice runningmod (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64 bits) . (let (runningmod :: 64 bits) = w__14 in return (roundkey, runningmod, workingval))))))))))))) \<bind> (\<lambda> varstup . (let ((roundkey :: 64 bits), (runningmod :: 64 @@ -5330,8 +5354,8 @@ definition ComputePAC :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow (let workingval = w__23 in (let workingval = ((xor_vec workingval key0 :: 64 Word.word)) in (let workingval = ((xor_vec workingval runningmod :: 64 Word.word)) in - (foreachM (index_list (( 0 :: int)::ii) (( 4 :: int)::ii) (( 1 :: int)::ii)) workingval - (\<lambda> i workingval . + (foreachM (index_list (( 0 :: int)::ii) (( 4 :: int)::ii) (( 1 :: int)::ii)) (roundkey, runningmod, workingval) + (\<lambda> i varstup . (let (roundkey, runningmod, workingval) = varstup in (PACInvSub workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__24 :: 64 bits) . (let workingval = w__24 in (if ((i < (( 4 :: int)::ii))) then @@ -5339,7 +5363,7 @@ definition ComputePAC :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow (let workingval = w__25 in (PACCellInvShuffle workingval :: ( 64 Word.word) M))) else return workingval) \<bind> (\<lambda> (workingval :: 64 bits) . - (TweakInvShuffle ((slice0 runningmod (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__27 :: 64 + (TweakInvShuffle ((slice runningmod (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__27 :: 64 bits) . (let runningmod = w__27 in (let roundkey = ((xor_vec key1 runningmod :: 64 Word.word)) in @@ -5349,9 +5373,10 @@ definition ComputePAC :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow :: 64 Word.word)) in (let (workingval :: 64 bits) = ((xor_vec workingval roundkey :: 64 Word.word)) in (let (workingval :: 64 bits) = ((xor_vec workingval Alpha :: 64 Word.word)) in - return workingval)))))))))))) \<bind> (\<lambda> (workingval :: 64 bits) . + return (roundkey, runningmod, workingval)))))))))))))) \<bind> (\<lambda> varstup . (let ((roundkey :: 64 bits), (runningmod :: 64 + bits), (workingval :: 64 bits)) = varstup in (let (workingval :: 64 bits) = ((xor_vec workingval modk0 :: 64 Word.word)) in - return workingval)))))))))))))))))))))))))))))))))))))))))))))))" + return workingval))))))))))))))))))))))))))))))))))))))))))))))))" (*val Align__0 : ii -> ii -> ii*) @@ -5378,12 +5403,12 @@ definition aset__Mem :: " AddressDescriptor \<Rightarrow> int \<Rightarrow> Acc (hex_slice (''0x13000000'') (( 52 :: int)::ii) (( 0 :: int)::ii) :: ( 52 Word.word) M)) \<bind> (\<lambda> (w__0 :: 52 Word.word) . if (((address = w__0))) then if (((((Word.uint value_name)) = (( 4 :: int)::ii)))) then - (let (_ :: unit) = (prerr_endline ([(CHR ''P''), (CHR ''r''), (CHR ''o''), (CHR ''g''), (CHR ''r''), (CHR ''a''), (CHR ''m''), (CHR '' ''), (CHR ''e''), (CHR ''x''), (CHR ''i''), (CHR ''t''), (CHR ''e''), (CHR ''d''), (CHR '' ''), (CHR ''b''), (CHR ''y''), (CHR '' ''), (CHR ''w''), (CHR ''r''), (CHR ''i''), (CHR ''t''), (CHR ''i''), (CHR ''n''), (CHR ''g''), (CHR '' ''), (CHR ''^''), (CHR ''D''), (CHR '' ''), (CHR ''t''), (CHR ''o''), (CHR '' ''), (CHR ''T''), (CHR ''U''), (CHR ''B''), (CHR ''E''), (char_of_nat 10)])) in + (let (_ :: unit) = (prerr ([(CHR ''P''), (CHR ''r''), (CHR ''o''), (CHR ''g''), (CHR ''r''), (CHR ''a''), (CHR ''m''), (CHR '' ''), (CHR ''e''), (CHR ''x''), (CHR ''i''), (CHR ''t''), (CHR ''e''), (CHR ''d''), (CHR '' ''), (CHR ''b''), (CHR ''y''), (CHR '' ''), (CHR ''w''), (CHR ''r''), (CHR ''i''), (CHR ''t''), (CHR ''i''), (CHR ''n''), (CHR ''g''), (CHR '' ''), (CHR ''^''), (CHR ''D''), (CHR '' ''), (CHR ''t''), (CHR ''o''), (CHR '' ''), (CHR ''T''), (CHR ''U''), (CHR ''B''), (CHR ''E''), (char_of_nat 10)])) in exit0 () ) - else return ((putchar ((Word.uint ((slice0 value_name (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)))))) + else return ((putchar ((Word.uint ((slice value_name (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)))))) else (read_reg Memory_ref :: ( 52 Word.word) M) \<bind> (\<lambda> (w__1 :: 52 Word.word) . - write_ram (( 52 :: int)::ii) size1 w__1 address value_name)))))" + WriteRAM ((make_the_value (( 52 :: int)::ii) :: 52 itself)) size1 w__1 address value_name)))))" (*val aget__Mem : forall 'p8_times_size_ . Size 'p8_times_size_ => AddressDescriptor -> integer -> AccessDescriptor -> M (mword 'p8_times_size_)*) @@ -5394,7 +5419,8 @@ definition aget__Mem :: " AddressDescriptor \<Rightarrow> int \<Rightarrow> Acc ((let (address :: 52 bits) = ((FullAddress_physicaladdress (AddressDescriptor_paddress desc))) in (assert_exp (((address = ((Align__1 address size1 :: 52 Word.word))))) (''(address == Align(address, size))'') \<then> (read_reg Memory_ref :: ( 52 Word.word) M)) \<bind> (\<lambda> (w__0 :: 52 Word.word) . - (read_ram (( 52 :: int)::ii) size1 w__0 address :: (( 'p8_times_size_::len)Word.word) M)))))" + (ReadRAM ((make_the_value (( 52 :: int)::ii) :: 52 itself)) size1 w__0 address + :: (( 'p8_times_size_::len)Word.word) M)))))" (*val aset_X : forall 'width . Size 'width => ii -> mword 'width -> M unit*) @@ -5418,7 +5444,7 @@ definition aarch64_integer_arithmetic_address_pcrel :: " int \<Rightarrow>(64)W (aget_PC () :: ( 64 Word.word) M) \<bind> (\<lambda> (base :: 64 bits) . (let (base :: 64 bits) = (if page then - (set_slice0 (( 64 :: int)::ii) (( 12 :: int)::ii) base (( 0 :: int)::ii) + (set_slice (( 64 :: int)::ii) (( 12 :: int)::ii) base (( 0 :: int)::ii) ((Zeros__0 ((make_the_value (( 12 :: int)::ii) :: 12 itself)) :: 12 Word.word)) :: 64 Word.word) else base) in @@ -5484,7 +5510,7 @@ definition aget_X :: " int \<Rightarrow> int \<Rightarrow>((register_value),((' assert_exp ((((((width__tv = (( 8 :: int)::ii)))) \<or> ((((((width__tv = (( 16 :: int)::ii)))) \<or> ((((((width__tv = (( 32 :: int)::ii)))) \<or> (((width__tv = (( 64 :: int)::ii))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))'')) \<then> (if (((n \<noteq> (( 31 :: int)::ii)))) then read_reg R_ref \<bind> (\<lambda> (w__0 :: ( 64 bits) list) . - return ((slice0 ((access_list_dec w__0 n :: 64 Word.word)) (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) + return ((slice ((access_list_dec w__0 n :: 64 Word.word)) (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) else return ((Zeros__0 ((make_the_value width__tv :: ( 'width::len)itself)) :: ( 'width::len)Word.word))))" @@ -5517,8 +5543,8 @@ definition aarch64_system_register_system :: " bool \<Rightarrow> int \<Rightar (*val aarch64_integer_insext_insert_movewide : ii -> ii -> mword ty16 -> MoveWideOp -> ii -> M unit*) definition aarch64_integer_insext_insert_movewide :: " int \<Rightarrow> int \<Rightarrow>(16)Word.word \<Rightarrow> MoveWideOp \<Rightarrow> int \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_insext_insert_movewide d l__276 imm opcode pos = ( - if (((l__276 = (( 8 :: int)::ii)))) then + " aarch64_integer_insext_insert_movewide d l__267 imm opcode pos = ( + if (((l__267 = (( 8 :: int)::ii)))) then (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5527,12 +5553,12 @@ definition aarch64_integer_insext_insert_movewide :: " int \<Rightarrow> int \< else (let (result :: 8 bits) = ((Zeros__1 (( 8 :: int)::ii) () :: 8 Word.word)) in return result)) \<bind> (\<lambda> (result :: 8 bits) . - (let result = ((set_slice0 (( 8 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 8 Word.word)) in + (let result = ((set_slice (( 8 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 8 Word.word)) in (let (result :: 8 bits) = (if (((opcode = MoveWideOp_N))) then (not_vec result :: 8 Word.word) else result) in aset_X d result))))) - else if (((l__276 = (( 16 :: int)::ii)))) then + else if (((l__267 = (( 16 :: int)::ii)))) then (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5541,12 +5567,12 @@ definition aarch64_integer_insext_insert_movewide :: " int \<Rightarrow> int \< else (let (result :: 16 bits) = ((Zeros__1 (( 16 :: int)::ii) () :: 16 Word.word)) in return result)) \<bind> (\<lambda> (result :: 16 bits) . - (let result = ((set_slice0 (( 16 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 16 Word.word)) in + (let result = ((set_slice (( 16 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 16 Word.word)) in (let (result :: 16 bits) = (if (((opcode = MoveWideOp_N))) then (not_vec result :: 16 Word.word) else result) in aset_X d result))))) - else if (((l__276 = (( 32 :: int)::ii)))) then + else if (((l__267 = (( 32 :: int)::ii)))) then (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5555,12 +5581,12 @@ definition aarch64_integer_insext_insert_movewide :: " int \<Rightarrow> int \< else (let (result :: 32 bits) = ((Zeros__1 (( 32 :: int)::ii) () :: 32 Word.word)) in return result)) \<bind> (\<lambda> (result :: 32 bits) . - (let result = ((set_slice0 (( 32 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 32 Word.word)) in + (let result = ((set_slice (( 32 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 32 Word.word)) in (let (result :: 32 bits) = (if (((opcode = MoveWideOp_N))) then (not_vec result :: 32 Word.word) else result) in aset_X d result))))) - else if (((l__276 = (( 64 :: int)::ii)))) then + else if (((l__267 = (( 64 :: int)::ii)))) then (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5569,12 +5595,12 @@ definition aarch64_integer_insext_insert_movewide :: " int \<Rightarrow> int \< else (let (result :: 64 bits) = ((Zeros__1 (( 64 :: int)::ii) () :: 64 Word.word)) in return result)) \<bind> (\<lambda> (result :: 64 bits) . - (let result = ((set_slice0 (( 64 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 64 Word.word)) in + (let result = ((set_slice (( 64 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 64 Word.word)) in (let (result :: 64 bits) = (if (((opcode = MoveWideOp_N))) then (not_vec result :: 64 Word.word) else result) in aset_X d result))))) - else if (((l__276 = (( 128 :: int)::ii)))) then + else if (((l__267 = (( 128 :: int)::ii)))) then (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5583,21 +5609,21 @@ definition aarch64_integer_insext_insert_movewide :: " int \<Rightarrow> int \< else (let (result :: 128 bits) = ((Zeros__1 (( 128 :: int)::ii) () :: 128 Word.word)) in return result)) \<bind> (\<lambda> (result :: 128 bits) . - (let result = ((set_slice0 (( 128 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 128 Word.word)) in + (let result = ((set_slice (( 128 :: int)::ii) (( 16 :: int)::ii) result pos imm :: 128 Word.word)) in (let (result :: 128 bits) = (if (((opcode = MoveWideOp_N))) then (not_vec result :: 128 Word.word) else result) in aset_X d result))))) else - (let dbytes = (ex_int ((l__276 div (( 8 :: int)::ii)))) in + (let dbytes = (ex_int ((l__267 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint'')))" (*val aarch64_integer_insext_extract_immediate : ii -> ii -> ii -> ii -> ii -> M unit*) definition aarch64_integer_insext_extract_immediate :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_insext_extract_immediate d l__271 lsb1 m n = ( - if (((l__271 = (( 8 :: int)::ii)))) then + " aarch64_integer_insext_extract_immediate d l__262 lsb1 m n = ( + if (((l__262 = (( 8 :: int)::ii)))) then (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5605,9 +5631,9 @@ definition aarch64_integer_insext_extract_immediate :: " int \<Rightarrow> int (aget_X (( 8 :: int)::ii) n :: ( 8 Word.word) M) \<bind> (\<lambda> (operand1 :: 8 bits) . (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \<bind> (\<lambda> (operand2 :: 8 bits) . (let (concat1 :: 16 bits) = ((concat_vec operand1 operand2 :: 16 Word.word)) in - (let result = ((slice0 concat1 lsb1 (( 8 :: int)::ii) :: 8 Word.word)) in + (let result = ((slice concat1 lsb1 (( 8 :: int)::ii) :: 8 Word.word)) in aset_X d result)))))) - else if (((l__271 = (( 16 :: int)::ii)))) then + else if (((l__262 = (( 16 :: int)::ii)))) then (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5615,9 +5641,9 @@ definition aarch64_integer_insext_extract_immediate :: " int \<Rightarrow> int (aget_X (( 16 :: int)::ii) n :: ( 16 Word.word) M) \<bind> (\<lambda> (operand1 :: 16 bits) . (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \<bind> (\<lambda> (operand2 :: 16 bits) . (let (concat1 :: 32 bits) = ((concat_vec operand1 operand2 :: 32 Word.word)) in - (let result = ((slice0 concat1 lsb1 (( 16 :: int)::ii) :: 16 Word.word)) in + (let result = ((slice concat1 lsb1 (( 16 :: int)::ii) :: 16 Word.word)) in aset_X d result)))))) - else if (((l__271 = (( 32 :: int)::ii)))) then + else if (((l__262 = (( 32 :: int)::ii)))) then (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5625,9 +5651,9 @@ definition aarch64_integer_insext_extract_immediate :: " int \<Rightarrow> int (aget_X (( 32 :: int)::ii) n :: ( 32 Word.word) M) \<bind> (\<lambda> (operand1 :: 32 bits) . (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \<bind> (\<lambda> (operand2 :: 32 bits) . (let (concat1 :: 64 bits) = ((concat_vec operand1 operand2 :: 64 Word.word)) in - (let result = ((slice0 concat1 lsb1 (( 32 :: int)::ii) :: 32 Word.word)) in + (let result = ((slice concat1 lsb1 (( 32 :: int)::ii) :: 32 Word.word)) in aset_X d result)))))) - else if (((l__271 = (( 64 :: int)::ii)))) then + else if (((l__262 = (( 64 :: int)::ii)))) then (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5635,9 +5661,9 @@ definition aarch64_integer_insext_extract_immediate :: " int \<Rightarrow> int (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M) \<bind> (\<lambda> (operand1 :: 64 bits) . (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \<bind> (\<lambda> (operand2 :: 64 bits) . (let (concat1 :: 128 bits) = ((concat_vec operand1 operand2 :: 128 Word.word)) in - (let result = ((slice0 concat1 lsb1 (( 64 :: int)::ii) :: 64 Word.word)) in + (let result = ((slice concat1 lsb1 (( 64 :: int)::ii) :: 64 Word.word)) in aset_X d result)))))) - else if (((l__271 = (( 128 :: int)::ii)))) then + else if (((l__262 = (( 128 :: int)::ii)))) then (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5645,18 +5671,18 @@ definition aarch64_integer_insext_extract_immediate :: " int \<Rightarrow> int (aget_X (( 128 :: int)::ii) n :: ( 128 Word.word) M) \<bind> (\<lambda> (operand1 :: 128 bits) . (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \<bind> (\<lambda> (operand2 :: 128 bits) . (let (concat1 :: 256 bits) = ((concat_vec operand1 operand2 :: 256 Word.word)) in - (let result = ((slice0 concat1 lsb1 (( 128 :: int)::ii) :: 128 Word.word)) in + (let result = ((slice concat1 lsb1 (( 128 :: int)::ii) :: 128 Word.word)) in aset_X d result)))))) else - (let dbytes = (ex_int ((l__271 div (( 8 :: int)::ii)))) in + (let dbytes = (ex_int ((l__262 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint'')))" (*val aarch64_integer_arithmetic_rev : ii -> ii -> ii -> ii -> M unit*) definition aarch64_integer_arithmetic_rev :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_arithmetic_rev container_size d l__266 n = ( - if (((l__266 = (( 8 :: int)::ii)))) then + " aarch64_integer_arithmetic_rev container_size d l__257 n = ( + if (((l__257 = (( 8 :: int)::ii)))) then (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5666,23 +5692,29 @@ definition aarch64_integer_arithmetic_rev :: " int \<Rightarrow> int \<Rightarr (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in (let (index1 :: ii) = ((( 0 :: int)::ii)) in undefined_int () \<bind> (\<lambda> (rev_index :: ii) . - (let (result :: 8 bits) = - (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result - (\<lambda> c result . + (let ((index1 :: ii), (result :: 8 bits), (rev_index :: ii)) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1, + result, + rev_index) + (\<lambda> c varstup . (let (index1, result, rev_index) = varstup in (let (rev_index :: ii) = (((ex_int index1)) + ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in - (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result - (\<lambda> e result . - (let (result :: 8 bits) = - ((set_slice0 (( 8 :: int)::ii) (( 8 :: int)::ii) result rev_index - ((slice0 operand index1 (( 8 :: int)::ii) :: 8 Word.word)) - :: 8 Word.word)) in - (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in - (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in - result)))))))) in + (let ((index1 :: ii), (result :: 8 bits), (rev_index :: ii)) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1, + result, + rev_index) + (\<lambda> e varstup . (let (index1, result, rev_index) = varstup in + (let (result :: 8 bits) = + ((set_slice (( 8 :: int)::ii) (( 8 :: int)::ii) result rev_index + ((slice operand index1 (( 8 :: int)::ii) :: 8 Word.word)) + :: 8 Word.word)) in + (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in + (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in + (index1, result, rev_index))))))) in + (index1, result, rev_index)))))) in aset_X d result)))))))) - else if (((l__266 = (( 16 :: int)::ii)))) then + else if (((l__257 = (( 16 :: int)::ii)))) then (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5692,23 +5724,29 @@ definition aarch64_integer_arithmetic_rev :: " int \<Rightarrow> int \<Rightarr (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in (let (index1 :: ii) = ((( 0 :: int)::ii)) in undefined_int () \<bind> (\<lambda> (rev_index :: ii) . - (let (result :: 16 bits) = - (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result - (\<lambda> c result . + (let ((index1 :: ii), (result :: 16 bits), (rev_index :: ii)) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1, + result, + rev_index) + (\<lambda> c varstup . (let (index1, result, rev_index) = varstup in (let (rev_index :: ii) = (((ex_int index1)) + ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in - (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result - (\<lambda> e result . - (let (result :: 16 bits) = - ((set_slice0 (( 16 :: int)::ii) (( 8 :: int)::ii) result rev_index - ((slice0 operand index1 (( 8 :: int)::ii) :: 8 Word.word)) - :: 16 Word.word)) in - (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in - (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in - result)))))))) in + (let ((index1 :: ii), (result :: 16 bits), (rev_index :: ii)) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1, + result, + rev_index) + (\<lambda> e varstup . (let (index1, result, rev_index) = varstup in + (let (result :: 16 bits) = + ((set_slice (( 16 :: int)::ii) (( 8 :: int)::ii) result rev_index + ((slice operand index1 (( 8 :: int)::ii) :: 8 Word.word)) + :: 16 Word.word)) in + (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in + (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in + (index1, result, rev_index))))))) in + (index1, result, rev_index)))))) in aset_X d result)))))))) - else if (((l__266 = (( 32 :: int)::ii)))) then + else if (((l__257 = (( 32 :: int)::ii)))) then (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5718,23 +5756,29 @@ definition aarch64_integer_arithmetic_rev :: " int \<Rightarrow> int \<Rightarr (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in (let (index1 :: ii) = ((( 0 :: int)::ii)) in undefined_int () \<bind> (\<lambda> (rev_index :: ii) . - (let (result :: 32 bits) = - (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result - (\<lambda> c result . + (let ((index1 :: ii), (result :: 32 bits), (rev_index :: ii)) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1, + result, + rev_index) + (\<lambda> c varstup . (let (index1, result, rev_index) = varstup in (let (rev_index :: ii) = (((ex_int index1)) + ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in - (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result - (\<lambda> e result . - (let (result :: 32 bits) = - ((set_slice0 (( 32 :: int)::ii) (( 8 :: int)::ii) result rev_index - ((slice0 operand index1 (( 8 :: int)::ii) :: 8 Word.word)) - :: 32 Word.word)) in - (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in - (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in - result)))))))) in + (let ((index1 :: ii), (result :: 32 bits), (rev_index :: ii)) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1, + result, + rev_index) + (\<lambda> e varstup . (let (index1, result, rev_index) = varstup in + (let (result :: 32 bits) = + ((set_slice (( 32 :: int)::ii) (( 8 :: int)::ii) result rev_index + ((slice operand index1 (( 8 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word)) in + (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in + (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in + (index1, result, rev_index))))))) in + (index1, result, rev_index)))))) in aset_X d result)))))))) - else if (((l__266 = (( 64 :: int)::ii)))) then + else if (((l__257 = (( 64 :: int)::ii)))) then (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5744,23 +5788,29 @@ definition aarch64_integer_arithmetic_rev :: " int \<Rightarrow> int \<Rightarr (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in (let (index1 :: ii) = ((( 0 :: int)::ii)) in undefined_int () \<bind> (\<lambda> (rev_index :: ii) . - (let (result :: 64 bits) = - (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result - (\<lambda> c result . + (let ((index1 :: ii), (result :: 64 bits), (rev_index :: ii)) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1, + result, + rev_index) + (\<lambda> c varstup . (let (index1, result, rev_index) = varstup in (let (rev_index :: ii) = (((ex_int index1)) + ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in - (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result - (\<lambda> e result . - (let (result :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 8 :: int)::ii) result rev_index - ((slice0 operand index1 (( 8 :: int)::ii) :: 8 Word.word)) - :: 64 Word.word)) in - (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in - (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in - result)))))))) in + (let ((index1 :: ii), (result :: 64 bits), (rev_index :: ii)) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1, + result, + rev_index) + (\<lambda> e varstup . (let (index1, result, rev_index) = varstup in + (let (result :: 64 bits) = + ((set_slice (( 64 :: int)::ii) (( 8 :: int)::ii) result rev_index + ((slice operand index1 (( 8 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word)) in + (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in + (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in + (index1, result, rev_index))))))) in + (index1, result, rev_index)))))) in aset_X d result)))))))) - else if (((l__266 = (( 128 :: int)::ii)))) then + else if (((l__257 = (( 128 :: int)::ii)))) then (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5770,32 +5820,38 @@ definition aarch64_integer_arithmetic_rev :: " int \<Rightarrow> int \<Rightarr (let (elements_per_container :: ii) = (container_size div (( 8 :: int)::ii)) in (let (index1 :: ii) = ((( 0 :: int)::ii)) in undefined_int () \<bind> (\<lambda> (rev_index :: ii) . - (let (result :: 128 bits) = - (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result - (\<lambda> c result . + (let ((index1 :: ii), (result :: 128 bits), (rev_index :: ii)) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int containers)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1, + result, + rev_index) + (\<lambda> c varstup . (let (index1, result, rev_index) = varstup in (let (rev_index :: ii) = (((ex_int index1)) + ((((((ex_int elements_per_container)) - (( 1 :: int)::ii))) * (( 8 :: int)::ii)))) in - (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result - (\<lambda> e result . - (let (result :: 128 bits) = - ((set_slice0 (( 128 :: int)::ii) (( 8 :: int)::ii) result rev_index - ((slice0 operand index1 (( 8 :: int)::ii) :: 8 Word.word)) - :: 128 Word.word)) in - (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in - (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in - result)))))))) in + (let ((index1 :: ii), (result :: 128 bits), (rev_index :: ii)) = + (foreach (index_list (( 0 :: int)::ii) ((((ex_int elements_per_container)) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (index1, + result, + rev_index) + (\<lambda> e varstup . (let (index1, result, rev_index) = varstup in + (let (result :: 128 bits) = + ((set_slice (( 128 :: int)::ii) (( 8 :: int)::ii) result rev_index + ((slice operand index1 (( 8 :: int)::ii) :: 8 Word.word)) + :: 128 Word.word)) in + (let (index1 :: ii) = (((ex_int index1)) + (( 8 :: int)::ii)) in + (let (rev_index :: ii) = (((ex_int rev_index)) - (( 8 :: int)::ii)) in + (index1, result, rev_index))))))) in + (index1, result, rev_index)))))) in aset_X d result)))))))) else - (let dbytes = (ex_int ((l__266 div (( 8 :: int)::ii)))) in + (let dbytes = (ex_int ((l__257 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint'')))" (*val aarch64_integer_arithmetic_rbit : ii -> ii -> ii -> M unit*) definition aarch64_integer_arithmetic_rbit :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_arithmetic_rbit d l__261 n = ( - if (((l__261 = (( 8 :: int)::ii)))) then + " aarch64_integer_arithmetic_rbit d l__252 n = ( + if (((l__252 = (( 8 :: int)::ii)))) then (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5804,11 +5860,11 @@ definition aarch64_integer_arithmetic_rbit :: " int \<Rightarrow> int \<Rightar (let (result :: 8 bits) = (foreach (index_list (( 0 :: int)::ii) (((( 8 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result (\<lambda> i result . - (set_slice0 (( 8 :: int)::ii) (( 1 :: int)::ii) result (((((( 8 :: int)::ii) - (( 1 :: int)::ii))) - i)) + (set_slice (( 8 :: int)::ii) (( 1 :: int)::ii) result (((((( 8 :: int)::ii) - (( 1 :: int)::ii))) - i)) (vec_of_bits [access_vec_dec operand i] :: 1 Word.word) :: 8 Word.word))) in aset_X d result)))) - else if (((l__261 = (( 16 :: int)::ii)))) then + else if (((l__252 = (( 16 :: int)::ii)))) then (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5817,11 +5873,11 @@ definition aarch64_integer_arithmetic_rbit :: " int \<Rightarrow> int \<Rightar (let (result :: 16 bits) = (foreach (index_list (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result (\<lambda> i result . - (set_slice0 (( 16 :: int)::ii) (( 1 :: int)::ii) result (((((( 16 :: int)::ii) - (( 1 :: int)::ii))) - i)) + (set_slice (( 16 :: int)::ii) (( 1 :: int)::ii) result (((((( 16 :: int)::ii) - (( 1 :: int)::ii))) - i)) (vec_of_bits [access_vec_dec operand i] :: 1 Word.word) :: 16 Word.word))) in aset_X d result)))) - else if (((l__261 = (( 32 :: int)::ii)))) then + else if (((l__252 = (( 32 :: int)::ii)))) then (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5830,11 +5886,11 @@ definition aarch64_integer_arithmetic_rbit :: " int \<Rightarrow> int \<Rightar (let (result :: 32 bits) = (foreach (index_list (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result (\<lambda> i result . - (set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) result (((((( 32 :: int)::ii) - (( 1 :: int)::ii))) - i)) + (set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) result (((((( 32 :: int)::ii) - (( 1 :: int)::ii))) - i)) (vec_of_bits [access_vec_dec operand i] :: 1 Word.word) :: 32 Word.word))) in aset_X d result)))) - else if (((l__261 = (( 64 :: int)::ii)))) then + else if (((l__252 = (( 64 :: int)::ii)))) then (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5843,11 +5899,11 @@ definition aarch64_integer_arithmetic_rbit :: " int \<Rightarrow> int \<Rightar (let (result :: 64 bits) = (foreach (index_list (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result (\<lambda> i result . - (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) result (((((( 64 :: int)::ii) - (( 1 :: int)::ii))) - i)) + (set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) result (((((( 64 :: int)::ii) - (( 1 :: int)::ii))) - i)) (vec_of_bits [access_vec_dec operand i] :: 1 Word.word) :: 64 Word.word))) in aset_X d result)))) - else if (((l__261 = (( 128 :: int)::ii)))) then + else if (((l__252 = (( 128 :: int)::ii)))) then (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5856,12 +5912,12 @@ definition aarch64_integer_arithmetic_rbit :: " int \<Rightarrow> int \<Rightar (let (result :: 128 bits) = (foreach (index_list (( 0 :: int)::ii) (((( 128 :: int)::ii) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result (\<lambda> i result . - (set_slice0 (( 128 :: int)::ii) (( 1 :: int)::ii) result (((((( 128 :: int)::ii) - (( 1 :: int)::ii))) - i)) + (set_slice (( 128 :: int)::ii) (( 1 :: int)::ii) result (((((( 128 :: int)::ii) - (( 1 :: int)::ii))) - i)) (vec_of_bits [access_vec_dec operand i] :: 1 Word.word) :: 128 Word.word))) in aset_X d result)))) else - (let dbytes = (ex_int ((l__261 div (( 8 :: int)::ii)))) in + (let dbytes = (ex_int ((l__252 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint'')))" @@ -5881,8 +5937,8 @@ definition integer_arithmetic_rbit_decode :: "(1)Word.word \<Rightarrow>(1)Word (*val aarch64_integer_arithmetic_mul_widening_64128hi : ii -> ii -> ii -> ii -> bool -> M unit*) definition aarch64_integer_arithmetic_mul_widening_64128hi :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_arithmetic_mul_widening_64128hi d l__256 m n unsigned = ( - if (((l__256 = (( 8 :: int)::ii)))) then + " aarch64_integer_arithmetic_mul_widening_64128hi d l__247 m n unsigned = ( + if (((l__247 = (( 8 :: int)::ii)))) then (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5892,7 +5948,7 @@ definition aarch64_integer_arithmetic_mul_widening_64128hi :: " int \<Rightarro (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 64 :: int)::ii) :: 64 Word.word)))))) - else if (((l__256 = (( 16 :: int)::ii)))) then + else if (((l__247 = (( 16 :: int)::ii)))) then (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5902,7 +5958,7 @@ definition aarch64_integer_arithmetic_mul_widening_64128hi :: " int \<Rightarro (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 64 :: int)::ii) :: 64 Word.word)))))) - else if (((l__256 = (( 32 :: int)::ii)))) then + else if (((l__247 = (( 32 :: int)::ii)))) then (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5912,7 +5968,7 @@ definition aarch64_integer_arithmetic_mul_widening_64128hi :: " int \<Rightarro (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 64 :: int)::ii) :: 64 Word.word)))))) - else if (((l__256 = (( 64 :: int)::ii)))) then + else if (((l__247 = (( 64 :: int)::ii)))) then (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5922,7 +5978,7 @@ definition aarch64_integer_arithmetic_mul_widening_64128hi :: " int \<Rightarro (((ex_int ((asl_Int operand1 unsigned)))) * ((ex_int ((asl_Int operand2 unsigned))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 64 :: int)::ii) :: 64 Word.word)))))) - else if (((l__256 = (( 128 :: int)::ii)))) then + else if (((l__247 = (( 128 :: int)::ii)))) then (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -5933,7 +5989,7 @@ definition aarch64_integer_arithmetic_mul_widening_64128hi :: " int \<Rightarro aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 64 :: int)::ii) :: 64 Word.word)))))) else - (let dbytes = (ex_int ((l__256 div (( 8 :: int)::ii)))) in + (let dbytes = (ex_int ((l__247 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint'')))" @@ -5955,8 +6011,8 @@ definition integer_arithmetic_mul_widening_64128hi_decode :: "(1)Word.word \<Ri (*val aarch64_integer_arithmetic_mul_widening_3264 : ii -> ii -> ii -> ii -> ii -> ii -> bool -> bool -> M unit*) definition aarch64_integer_arithmetic_mul_widening_3264 :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_arithmetic_mul_widening_3264 a d l__229 l__230 m n sub_op unsigned = ( - if ((((((l__229 = (( 8 :: int)::ii)))) \<and> (((l__230 = (( 32 :: int)::ii))))))) then + " aarch64_integer_arithmetic_mul_widening_3264 a d l__220 l__221 m n sub_op unsigned = ( + if ((((((l__220 = (( 8 :: int)::ii)))) \<and> (((l__221 = (( 32 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -5976,7 +6032,7 @@ definition aarch64_integer_arithmetic_mul_widening_3264 :: " int \<Rightarrow> ((ex_int ((asl_Int operand2 unsigned))))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if ((((((l__229 = (( 8 :: int)::ii)))) \<and> (((l__230 = (( 64 :: int)::ii))))))) then + else if ((((((l__220 = (( 8 :: int)::ii)))) \<and> (((l__221 = (( 64 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -5996,8 +6052,8 @@ definition aarch64_integer_arithmetic_mul_widening_3264 :: " int \<Rightarrow> ((ex_int ((asl_Int operand2 unsigned))))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if (((l__229 = (( 8 :: int)::ii)))) then assert_exp True (''destsize constraint'') - else if ((((((l__229 = (( 16 :: int)::ii)))) \<and> (((l__230 = (( 32 :: int)::ii))))))) then + else if (((l__220 = (( 8 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__220 = (( 16 :: int)::ii)))) \<and> (((l__221 = (( 32 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6017,7 +6073,7 @@ definition aarch64_integer_arithmetic_mul_widening_3264 :: " int \<Rightarrow> ((ex_int ((asl_Int operand2 unsigned))))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if ((((((l__229 = (( 16 :: int)::ii)))) \<and> (((l__230 = (( 64 :: int)::ii))))))) then + else if ((((((l__220 = (( 16 :: int)::ii)))) \<and> (((l__221 = (( 64 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6037,8 +6093,8 @@ definition aarch64_integer_arithmetic_mul_widening_3264 :: " int \<Rightarrow> ((ex_int ((asl_Int operand2 unsigned))))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if (((l__229 = (( 16 :: int)::ii)))) then assert_exp True (''destsize constraint'') - else if ((((((l__229 = (( 32 :: int)::ii)))) \<and> (((l__230 = (( 32 :: int)::ii))))))) then + else if (((l__220 = (( 16 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__220 = (( 32 :: int)::ii)))) \<and> (((l__221 = (( 32 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6058,7 +6114,7 @@ definition aarch64_integer_arithmetic_mul_widening_3264 :: " int \<Rightarrow> ((ex_int ((asl_Int operand2 unsigned))))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if ((((((l__229 = (( 32 :: int)::ii)))) \<and> (((l__230 = (( 64 :: int)::ii))))))) then + else if ((((((l__220 = (( 32 :: int)::ii)))) \<and> (((l__221 = (( 64 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6078,8 +6134,8 @@ definition aarch64_integer_arithmetic_mul_widening_3264 :: " int \<Rightarrow> ((ex_int ((asl_Int operand2 unsigned))))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if (((l__229 = (( 32 :: int)::ii)))) then assert_exp True (''destsize constraint'') - else if ((((((l__229 = (( 64 :: int)::ii)))) \<and> (((l__230 = (( 32 :: int)::ii))))))) then + else if (((l__220 = (( 32 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__220 = (( 64 :: int)::ii)))) \<and> (((l__221 = (( 32 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6099,7 +6155,7 @@ definition aarch64_integer_arithmetic_mul_widening_3264 :: " int \<Rightarrow> ((ex_int ((asl_Int operand2 unsigned))))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if ((((((l__229 = (( 64 :: int)::ii)))) \<and> (((l__230 = (( 64 :: int)::ii))))))) then + else if ((((((l__220 = (( 64 :: int)::ii)))) \<and> (((l__221 = (( 64 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6119,8 +6175,8 @@ definition aarch64_integer_arithmetic_mul_widening_3264 :: " int \<Rightarrow> ((ex_int ((asl_Int operand2 unsigned))))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if (((l__229 = (( 64 :: int)::ii)))) then assert_exp True (''destsize constraint'') - else if ((((((l__229 = (( 128 :: int)::ii)))) \<and> (((l__230 = (( 32 :: int)::ii))))))) then + else if (((l__220 = (( 64 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__220 = (( 128 :: int)::ii)))) \<and> (((l__221 = (( 32 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6140,7 +6196,7 @@ definition aarch64_integer_arithmetic_mul_widening_3264 :: " int \<Rightarrow> ((ex_int ((asl_Int operand2 unsigned))))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if ((((((l__229 = (( 128 :: int)::ii)))) \<and> (((l__230 = (( 64 :: int)::ii))))))) then + else if ((((((l__220 = (( 128 :: int)::ii)))) \<and> (((l__221 = (( 64 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6160,14 +6216,14 @@ definition aarch64_integer_arithmetic_mul_widening_3264 :: " int \<Rightarrow> ((ex_int ((asl_Int operand2 unsigned))))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if (((l__229 = (( 128 :: int)::ii)))) then assert_exp True (''destsize constraint'') - else if (((l__230 = (( 32 :: int)::ii)))) then + else if (((l__220 = (( 128 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if (((l__221 = (( 32 :: int)::ii)))) then assert_exp True (''destsize constraint'') \<then> - ((let dbytes = (ex_int ((l__229 div (( 8 :: int)::ii)))) in + ((let dbytes = (ex_int ((l__220 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint''))) - else if (((l__230 = (( 64 :: int)::ii)))) then + else if (((l__221 = (( 64 :: int)::ii)))) then assert_exp True (''destsize constraint'') \<then> - ((let dbytes = (ex_int ((l__229 div (( 8 :: int)::ii)))) in + ((let dbytes = (ex_int ((l__220 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint''))) else assert_exp True (''destsize constraint''))" @@ -6191,8 +6247,8 @@ definition integer_arithmetic_mul_widening_3264_decode :: "(1)Word.word \<Right (*val aarch64_integer_arithmetic_mul_uniform_addsub : ii -> ii -> ii -> ii -> ii -> ii -> bool -> M unit*) definition aarch64_integer_arithmetic_mul_uniform_addsub :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_arithmetic_mul_uniform_addsub a d l__202 l__203 m n sub_op = ( - if ((((((l__202 = (( 8 :: int)::ii)))) \<and> (((l__203 = (( 32 :: int)::ii))))))) then + " aarch64_integer_arithmetic_mul_uniform_addsub a d l__193 l__194 m n sub_op = ( + if ((((((l__193 = (( 8 :: int)::ii)))) \<and> (((l__194 = (( 32 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6207,7 +6263,7 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub :: " int \<Rightarrow> else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in aset_X d ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word))))))))) - else if ((((((l__202 = (( 8 :: int)::ii)))) \<and> (((l__203 = (( 64 :: int)::ii))))))) then + else if ((((((l__193 = (( 8 :: int)::ii)))) \<and> (((l__194 = (( 64 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6222,8 +6278,8 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub :: " int \<Rightarrow> else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if (((l__202 = (( 8 :: int)::ii)))) then assert_exp True (''destsize constraint'') - else if ((((((l__202 = (( 16 :: int)::ii)))) \<and> (((l__203 = (( 32 :: int)::ii))))))) then + else if (((l__193 = (( 8 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__193 = (( 16 :: int)::ii)))) \<and> (((l__194 = (( 32 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6238,7 +6294,7 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub :: " int \<Rightarrow> else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in aset_X d ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word))))))))) - else if ((((((l__202 = (( 16 :: int)::ii)))) \<and> (((l__203 = (( 64 :: int)::ii))))))) then + else if ((((((l__193 = (( 16 :: int)::ii)))) \<and> (((l__194 = (( 64 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6253,8 +6309,8 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub :: " int \<Rightarrow> else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if (((l__202 = (( 16 :: int)::ii)))) then assert_exp True (''destsize constraint'') - else if ((((((l__202 = (( 32 :: int)::ii)))) \<and> (((l__203 = (( 32 :: int)::ii))))))) then + else if (((l__193 = (( 16 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__193 = (( 32 :: int)::ii)))) \<and> (((l__194 = (( 32 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6269,7 +6325,7 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub :: " int \<Rightarrow> else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in aset_X d ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word))))))))) - else if ((((((l__202 = (( 32 :: int)::ii)))) \<and> (((l__203 = (( 64 :: int)::ii))))))) then + else if ((((((l__193 = (( 32 :: int)::ii)))) \<and> (((l__194 = (( 64 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6284,8 +6340,8 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub :: " int \<Rightarrow> else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if (((l__202 = (( 32 :: int)::ii)))) then assert_exp True (''destsize constraint'') - else if ((((((l__202 = (( 64 :: int)::ii)))) \<and> (((l__203 = (( 32 :: int)::ii))))))) then + else if (((l__193 = (( 32 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__193 = (( 64 :: int)::ii)))) \<and> (((l__194 = (( 32 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6300,7 +6356,7 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub :: " int \<Rightarrow> else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in aset_X d ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word))))))))) - else if ((((((l__202 = (( 64 :: int)::ii)))) \<and> (((l__203 = (( 64 :: int)::ii))))))) then + else if ((((((l__193 = (( 64 :: int)::ii)))) \<and> (((l__194 = (( 64 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6315,8 +6371,8 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub :: " int \<Rightarrow> else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if (((l__202 = (( 64 :: int)::ii)))) then assert_exp True (''destsize constraint'') - else if ((((((l__202 = (( 128 :: int)::ii)))) \<and> (((l__203 = (( 32 :: int)::ii))))))) then + else if (((l__193 = (( 64 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if ((((((l__193 = (( 128 :: int)::ii)))) \<and> (((l__194 = (( 32 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6331,7 +6387,7 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub :: " int \<Rightarrow> else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in aset_X d ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word))))))))) - else if ((((((l__202 = (( 128 :: int)::ii)))) \<and> (((l__203 = (( 64 :: int)::ii))))))) then + else if ((((((l__193 = (( 128 :: int)::ii)))) \<and> (((l__194 = (( 64 :: int)::ii))))))) then assert_exp True (''destsize constraint'') \<then> ((let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> @@ -6346,14 +6402,14 @@ definition aarch64_integer_arithmetic_mul_uniform_addsub :: " int \<Rightarrow> else ((Word.uint operand3)) + ((((Word.uint operand1)) * ((Word.uint operand2))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))))) - else if (((l__202 = (( 128 :: int)::ii)))) then assert_exp True (''destsize constraint'') - else if (((l__203 = (( 32 :: int)::ii)))) then + else if (((l__193 = (( 128 :: int)::ii)))) then assert_exp True (''destsize constraint'') + else if (((l__194 = (( 32 :: int)::ii)))) then assert_exp True (''destsize constraint'') \<then> - ((let dbytes = (ex_int ((l__202 div (( 8 :: int)::ii)))) in + ((let dbytes = (ex_int ((l__193 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint''))) - else if (((l__203 = (( 64 :: int)::ii)))) then + else if (((l__194 = (( 64 :: int)::ii)))) then assert_exp True (''destsize constraint'') \<then> - ((let dbytes = (ex_int ((l__202 div (( 8 :: int)::ii)))) in + ((let dbytes = (ex_int ((l__193 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint''))) else assert_exp True (''destsize constraint''))" @@ -6378,8 +6434,8 @@ definition integer_arithmetic_mul_uniform_addsub_decode :: "(1)Word.word \<Righ (*val aarch64_integer_arithmetic_div : ii -> ii -> ii -> ii -> bool -> M unit*) definition aarch64_integer_arithmetic_div :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_arithmetic_div d l__197 m n unsigned = ( - if (((l__197 = (( 8 :: int)::ii)))) then + " aarch64_integer_arithmetic_div d l__188 m n unsigned = ( + if (((l__188 = (( 8 :: int)::ii)))) then (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6393,7 +6449,7 @@ definition aarch64_integer_arithmetic_div :: " int \<Rightarrow> int \<Rightarr (((((real_of_int ((asl_Int operand1 unsigned))))) div (((real_of_int ((asl_Int operand2 unsigned)))))))) in aset_X d ((GetSlice_int ((make_the_value (( 8 :: int)::ii) :: 8 itself)) result (( 0 :: int)::ii) :: 8 Word.word))))))) - else if (((l__197 = (( 16 :: int)::ii)))) then + else if (((l__188 = (( 16 :: int)::ii)))) then (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6408,7 +6464,7 @@ definition aarch64_integer_arithmetic_div :: " int \<Rightarrow> int \<Rightarr (((real_of_int ((asl_Int operand2 unsigned)))))))) in aset_X d ((GetSlice_int ((make_the_value (( 16 :: int)::ii) :: 16 itself)) result (( 0 :: int)::ii) :: 16 Word.word))))))) - else if (((l__197 = (( 32 :: int)::ii)))) then + else if (((l__188 = (( 32 :: int)::ii)))) then (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6423,7 +6479,7 @@ definition aarch64_integer_arithmetic_div :: " int \<Rightarrow> int \<Rightarr (((real_of_int ((asl_Int operand2 unsigned)))))))) in aset_X d ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word))))))) - else if (((l__197 = (( 64 :: int)::ii)))) then + else if (((l__188 = (( 64 :: int)::ii)))) then (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6438,7 +6494,7 @@ definition aarch64_integer_arithmetic_div :: " int \<Rightarrow> int \<Rightarr (((real_of_int ((asl_Int operand2 unsigned)))))))) in aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word))))))) - else if (((l__197 = (( 128 :: int)::ii)))) then + else if (((l__188 = (( 128 :: int)::ii)))) then (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6454,7 +6510,7 @@ definition aarch64_integer_arithmetic_div :: " int \<Rightarrow> int \<Rightarr aset_X d ((GetSlice_int ((make_the_value (( 128 :: int)::ii) :: 128 itself)) result (( 0 :: int)::ii) :: 128 Word.word))))))) else - (let dbytes = (ex_int ((l__197 div (( 8 :: int)::ii)))) in + (let dbytes = (ex_int ((l__188 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint'')))" @@ -6476,8 +6532,8 @@ definition integer_arithmetic_div_decode :: "(1)Word.word \<Rightarrow>(1)Word. (*val aarch64_integer_arithmetic_cnt : ii -> ii -> ii -> CountOp -> M unit*) definition aarch64_integer_arithmetic_cnt :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> CountOp \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_arithmetic_cnt d l__192 n opcode = ( - if (((l__192 = (( 8 :: int)::ii)))) then + " aarch64_integer_arithmetic_cnt d l__183 n opcode = ( + if (((l__183 = (( 8 :: int)::ii)))) then (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6486,7 +6542,7 @@ definition aarch64_integer_arithmetic_cnt :: " int \<Rightarrow> int \<Rightarr (if (((opcode = CountOp_CLZ))) then CountLeadingZeroBits operand1 else CountLeadingSignBits operand1) \<bind> (\<lambda> (result :: ii) . aset_X d ((GetSlice_int ((make_the_value (( 8 :: int)::ii) :: 8 itself)) result (( 0 :: int)::ii) :: 8 Word.word)))))) - else if (((l__192 = (( 16 :: int)::ii)))) then + else if (((l__183 = (( 16 :: int)::ii)))) then (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6496,7 +6552,7 @@ definition aarch64_integer_arithmetic_cnt :: " int \<Rightarrow> int \<Rightarr else CountLeadingSignBits operand1) \<bind> (\<lambda> (result :: ii) . aset_X d ((GetSlice_int ((make_the_value (( 16 :: int)::ii) :: 16 itself)) result (( 0 :: int)::ii) :: 16 Word.word)))))) - else if (((l__192 = (( 32 :: int)::ii)))) then + else if (((l__183 = (( 32 :: int)::ii)))) then (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6506,7 +6562,7 @@ definition aarch64_integer_arithmetic_cnt :: " int \<Rightarrow> int \<Rightarr else CountLeadingSignBits operand1) \<bind> (\<lambda> (result :: ii) . aset_X d ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word)))))) - else if (((l__192 = (( 64 :: int)::ii)))) then + else if (((l__183 = (( 64 :: int)::ii)))) then (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6516,7 +6572,7 @@ definition aarch64_integer_arithmetic_cnt :: " int \<Rightarrow> int \<Rightarr else CountLeadingSignBits operand1) \<bind> (\<lambda> (result :: ii) . aset_X d ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) result (( 0 :: int)::ii) :: 64 Word.word)))))) - else if (((l__192 = (( 128 :: int)::ii)))) then + else if (((l__183 = (( 128 :: int)::ii)))) then (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6527,7 +6583,7 @@ definition aarch64_integer_arithmetic_cnt :: " int \<Rightarrow> int \<Rightarr aset_X d ((GetSlice_int ((make_the_value (( 128 :: int)::ii) :: 128 itself)) result (( 0 :: int)::ii) :: 128 Word.word)))))) else - (let dbytes = (ex_int ((l__192 div (( 8 :: int)::ii)))) in + (let dbytes = (ex_int ((l__183 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint'')))" @@ -6550,8 +6606,8 @@ definition integer_arithmetic_cnt_decode :: "(1)Word.word \<Rightarrow>(1)Word. (*val aarch64_integer_arithmetic_addsub_carry : ii -> ii -> ii -> ii -> bool -> bool -> M unit*) definition aarch64_integer_arithmetic_addsub_carry :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_arithmetic_addsub_carry d l__187 m n setflags sub_op = ( - if (((l__187 = (( 8 :: int)::ii)))) then + " aarch64_integer_arithmetic_addsub_carry d l__178 m n setflags sub_op = ( + if (((l__178 = (( 8 :: int)::ii)))) then (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6581,7 +6637,7 @@ definition aarch64_integer_arithmetic_addsub_carry :: " int \<Rightarrow> int \ write_reg PSTATE_ref (w__4 (| ProcState_V := tup__3 |))))))) else return () ) \<then> aset_X d result)))))))))) - else if (((l__187 = (( 16 :: int)::ii)))) then + else if (((l__178 = (( 16 :: int)::ii)))) then (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6611,7 +6667,7 @@ definition aarch64_integer_arithmetic_addsub_carry :: " int \<Rightarrow> int \ write_reg PSTATE_ref (w__9 (| ProcState_V := tup__3 |))))))) else return () ) \<then> aset_X d result)))))))))) - else if (((l__187 = (( 32 :: int)::ii)))) then + else if (((l__178 = (( 32 :: int)::ii)))) then (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6641,7 +6697,7 @@ definition aarch64_integer_arithmetic_addsub_carry :: " int \<Rightarrow> int \ write_reg PSTATE_ref (w__14 (| ProcState_V := tup__3 |))))))) else return () ) \<then> aset_X d result)))))))))) - else if (((l__187 = (( 64 :: int)::ii)))) then + else if (((l__178 = (( 64 :: int)::ii)))) then (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6671,7 +6727,7 @@ definition aarch64_integer_arithmetic_addsub_carry :: " int \<Rightarrow> int \ write_reg PSTATE_ref (w__19 (| ProcState_V := tup__3 |))))))) else return () ) \<then> aset_X d result)))))))))) - else if (((l__187 = (( 128 :: int)::ii)))) then + else if (((l__178 = (( 128 :: int)::ii)))) then (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6702,7 +6758,7 @@ definition aarch64_integer_arithmetic_addsub_carry :: " int \<Rightarrow> int \ else return () ) \<then> aset_X d result)))))))))) else - (let dbytes = (ex_int ((l__187 div (( 8 :: int)::ii)))) in + (let dbytes = (ex_int ((l__178 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint'')))" @@ -6859,8 +6915,8 @@ definition ShiftReg :: " int \<Rightarrow> int \<Rightarrow> ShiftType \<Righta (*val aarch64_integer_shift_variable : ii -> ii -> ii -> ii -> ShiftType -> M unit*) definition aarch64_integer_shift_variable :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> ShiftType \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_shift_variable d l__182 m n shift_type = ( - if (((l__182 = (( 8 :: int)::ii)))) then + " aarch64_integer_shift_variable d l__173 m n shift_type = ( + if (((l__173 = (( 8 :: int)::ii)))) then (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6870,7 +6926,7 @@ definition aarch64_integer_shift_variable :: " int \<Rightarrow> int \<Rightarr bits) . (let result = w__0 in aset_X d result))))) - else if (((l__182 = (( 16 :: int)::ii)))) then + else if (((l__173 = (( 16 :: int)::ii)))) then (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6880,7 +6936,7 @@ definition aarch64_integer_shift_variable :: " int \<Rightarrow> int \<Rightarr bits) . (let result = w__1 in aset_X d result))))) - else if (((l__182 = (( 32 :: int)::ii)))) then + else if (((l__173 = (( 32 :: int)::ii)))) then (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6890,7 +6946,7 @@ definition aarch64_integer_shift_variable :: " int \<Rightarrow> int \<Rightarr bits) . (let result = w__2 in aset_X d result))))) - else if (((l__182 = (( 64 :: int)::ii)))) then + else if (((l__173 = (( 64 :: int)::ii)))) then (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6900,7 +6956,7 @@ definition aarch64_integer_shift_variable :: " int \<Rightarrow> int \<Rightarr bits) . (let result = w__3 in aset_X d result))))) - else if (((l__182 = (( 128 :: int)::ii)))) then + else if (((l__173 = (( 128 :: int)::ii)))) then (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6911,7 +6967,7 @@ definition aarch64_integer_shift_variable :: " int \<Rightarrow> int \<Rightarr (let result = w__4 in aset_X d result))))) else - (let dbytes = (ex_int ((l__182 div (( 8 :: int)::ii)))) in + (let dbytes = (ex_int ((l__173 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint'')))" @@ -6933,8 +6989,8 @@ definition integer_shift_variable_decode :: "(1)Word.word \<Rightarrow>(1)Word. (*val aarch64_integer_logical_shiftedreg : ii -> ii -> bool -> ii -> ii -> LogicalOp -> bool -> ii -> ShiftType -> M unit*) definition aarch64_integer_logical_shiftedreg :: " int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> int \<Rightarrow> int \<Rightarrow> LogicalOp \<Rightarrow> bool \<Rightarrow> int \<Rightarrow> ShiftType \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_logical_shiftedreg d l__177 invert m n op1 setflags shift_amount shift_type = ( - if (((l__177 = (( 8 :: int)::ii)))) then + " aarch64_integer_logical_shiftedreg d l__168 invert m n op1 setflags shift_amount shift_type = ( + if (((l__168 = (( 8 :: int)::ii)))) then (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -6971,7 +7027,7 @@ definition aarch64_integer_logical_shiftedreg :: " int \<Rightarrow> int \<Righ write_reg PSTATE_ref (w__3 (| ProcState_V := tup__3 |)))))))) else return () ) \<then> aset_X d result)))))) - else if (((l__177 = (( 16 :: int)::ii)))) then + else if (((l__168 = (( 16 :: int)::ii)))) then (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7008,7 +7064,7 @@ definition aarch64_integer_logical_shiftedreg :: " int \<Rightarrow> int \<Righ write_reg PSTATE_ref (w__7 (| ProcState_V := tup__3 |)))))))) else return () ) \<then> aset_X d result)))))) - else if (((l__177 = (( 32 :: int)::ii)))) then + else if (((l__168 = (( 32 :: int)::ii)))) then (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7045,7 +7101,7 @@ definition aarch64_integer_logical_shiftedreg :: " int \<Rightarrow> int \<Righ write_reg PSTATE_ref (w__11 (| ProcState_V := tup__3 |)))))))) else return () ) \<then> aset_X d result)))))) - else if (((l__177 = (( 64 :: int)::ii)))) then + else if (((l__168 = (( 64 :: int)::ii)))) then (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7082,7 +7138,7 @@ definition aarch64_integer_logical_shiftedreg :: " int \<Rightarrow> int \<Righ write_reg PSTATE_ref (w__15 (| ProcState_V := tup__3 |)))))))) else return () ) \<then> aset_X d result)))))) - else if (((l__177 = (( 128 :: int)::ii)))) then + else if (((l__168 = (( 128 :: int)::ii)))) then (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7120,15 +7176,15 @@ definition aarch64_integer_logical_shiftedreg :: " int \<Rightarrow> int \<Righ else return () ) \<then> aset_X d result)))))) else - (let dbytes = (ex_int ((l__177 div (( 8 :: int)::ii)))) in + (let dbytes = (ex_int ((l__168 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint'')))" (*val aarch64_integer_arithmetic_addsub_shiftedreg : ii -> ii -> ii -> ii -> bool -> ii -> ShiftType -> bool -> M unit*) definition aarch64_integer_arithmetic_addsub_shiftedreg :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> int \<Rightarrow> ShiftType \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_arithmetic_addsub_shiftedreg d l__172 m n setflags shift_amount shift_type sub_op = ( - if (((l__172 = (( 8 :: int)::ii)))) then + " aarch64_integer_arithmetic_addsub_shiftedreg d l__163 m n setflags shift_amount shift_type sub_op = ( + if (((l__163 = (( 8 :: int)::ii)))) then (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7164,7 +7220,7 @@ definition aarch64_integer_arithmetic_addsub_shiftedreg :: " int \<Rightarrow> write_reg PSTATE_ref (w__3 (| ProcState_V := tup__3 |))))))) else return () ) \<then> aset_X d result)))))))))) - else if (((l__172 = (( 16 :: int)::ii)))) then + else if (((l__163 = (( 16 :: int)::ii)))) then (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7200,7 +7256,7 @@ definition aarch64_integer_arithmetic_addsub_shiftedreg :: " int \<Rightarrow> write_reg PSTATE_ref (w__7 (| ProcState_V := tup__3 |))))))) else return () ) \<then> aset_X d result)))))))))) - else if (((l__172 = (( 32 :: int)::ii)))) then + else if (((l__163 = (( 32 :: int)::ii)))) then (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7236,7 +7292,7 @@ definition aarch64_integer_arithmetic_addsub_shiftedreg :: " int \<Rightarrow> write_reg PSTATE_ref (w__11 (| ProcState_V := tup__3 |))))))) else return () ) \<then> aset_X d result)))))))))) - else if (((l__172 = (( 64 :: int)::ii)))) then + else if (((l__163 = (( 64 :: int)::ii)))) then (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7272,7 +7328,7 @@ definition aarch64_integer_arithmetic_addsub_shiftedreg :: " int \<Rightarrow> write_reg PSTATE_ref (w__15 (| ProcState_V := tup__3 |))))))) else return () ) \<then> aset_X d result)))))))))) - else if (((l__172 = (( 128 :: int)::ii)))) then + else if (((l__163 = (( 128 :: int)::ii)))) then (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7309,7 +7365,7 @@ definition aarch64_integer_arithmetic_addsub_shiftedreg :: " int \<Rightarrow> else return () ) \<then> aset_X d result)))))))))) else - (let dbytes = (ex_int ((l__172 div (( 8 :: int)::ii)))) in + (let dbytes = (ex_int ((l__163 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint'')))" @@ -7320,13 +7376,13 @@ definition Prefetch :: "(64)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(( undefined_PrefetchHint () \<bind> (\<lambda> (hint :: PrefetchHint) . undefined_int () \<bind> (\<lambda> (target :: ii) . undefined_bool () \<bind> (\<lambda> (stream :: bool) . - (let b__0 = ((slice0 prfop (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let b__0 = ((slice prfop (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in (let (hint :: PrefetchHint) = (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then Prefetch_READ else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Prefetch_EXEC else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then Prefetch_WRITE else hint) in - (let (target :: ii) = (Word.uint ((slice0 prfop (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) in + (let (target :: ii) = (Word.uint ((slice prfop (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) in (let (stream :: bool) = ((vec_of_bits [access_vec_dec prfop (( 0 :: int)::ii)] :: 1 Word.word) \<noteq> (vec_of_bits [B0] :: 1 Word.word)) in (let (_ :: unit) = (Hint_Prefetch address hint target stream) in @@ -7555,8 +7611,8 @@ definition aarch64_integer_arithmetic_addsub_immediate :: " int \<Rightarrow>(' (*val aarch64_integer_arithmetic_addsub_extendedreg : ii -> ii -> ExtendType -> ii -> ii -> bool -> ii -> bool -> M unit*) definition aarch64_integer_arithmetic_addsub_extendedreg :: " int \<Rightarrow> int \<Rightarrow> ExtendType \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where - " aarch64_integer_arithmetic_addsub_extendedreg d l__167 extend_type m n setflags shift sub_op = ( - if (((l__167 = (( 8 :: int)::ii)))) then + " aarch64_integer_arithmetic_addsub_extendedreg d l__158 extend_type m n setflags shift sub_op = ( + if (((l__158 = (( 8 :: int)::ii)))) then (let dbytes = (ex_int (((( 8 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7594,7 +7650,7 @@ definition aarch64_integer_arithmetic_addsub_extendedreg :: " int \<Rightarrow> else return () ) \<then> (if ((((((d = (( 31 :: int)::ii)))) \<and> ((\<not> setflags))))) then aset_SP result else aset_X d result))))))))))) - else if (((l__167 = (( 16 :: int)::ii)))) then + else if (((l__158 = (( 16 :: int)::ii)))) then (let dbytes = (ex_int (((( 16 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7632,7 +7688,7 @@ definition aarch64_integer_arithmetic_addsub_extendedreg :: " int \<Rightarrow> else return () ) \<then> (if ((((((d = (( 31 :: int)::ii)))) \<and> ((\<not> setflags))))) then aset_SP result else aset_X d result))))))))))) - else if (((l__167 = (( 32 :: int)::ii)))) then + else if (((l__158 = (( 32 :: int)::ii)))) then (let dbytes = (ex_int (((( 32 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7670,7 +7726,7 @@ definition aarch64_integer_arithmetic_addsub_extendedreg :: " int \<Rightarrow> else return () ) \<then> (if ((((((d = (( 31 :: int)::ii)))) \<and> ((\<not> setflags))))) then aset_SP result else aset_X d result))))))))))) - else if (((l__167 = (( 64 :: int)::ii)))) then + else if (((l__158 = (( 64 :: int)::ii)))) then (let dbytes = (ex_int (((( 64 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7708,7 +7764,7 @@ definition aarch64_integer_arithmetic_addsub_extendedreg :: " int \<Rightarrow> else return () ) \<then> (if ((((((d = (( 31 :: int)::ii)))) \<and> ((\<not> setflags))))) then aset_SP result else aset_X d result))))))))))) - else if (((l__167 = (( 128 :: int)::ii)))) then + else if (((l__158 = (( 128 :: int)::ii)))) then (let dbytes = (ex_int (((( 128 :: int)::ii) div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> @@ -7747,7 +7803,7 @@ definition aarch64_integer_arithmetic_addsub_extendedreg :: " int \<Rightarrow> (if ((((((d = (( 31 :: int)::ii)))) \<and> ((\<not> setflags))))) then aset_SP result else aset_X d result))))))))))) else - (let dbytes = (ex_int ((l__167 div (( 8 :: int)::ii)))) in + (let dbytes = (ex_int ((l__158 div (( 8 :: int)::ii)))) in assert_exp True (''datasize constraint'')))" @@ -7882,52 +7938,52 @@ definition CalculateBottomPACBit :: "(64)Word.word \<Rightarrow>(1)Word.word \< if w__1 then (if (((top_bit = (vec_of_bits [B1] :: 1 Word.word)))) then (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . - return ((Word.uint ((slice0 w__2 (( 16 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) + return ((Word.uint ((slice w__2 (( 16 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) else (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . - return ((Word.uint ((slice0 w__3 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)))))) \<bind> (\<lambda> (w__4 :: ii) . + return ((Word.uint ((slice w__3 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)))))) \<bind> (\<lambda> (w__4 :: ii) . (let tsz_field = w__4 in (if (((top_bit = (vec_of_bits [B1] :: 1 Word.word)))) then (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . - return (((((slice0 w__5 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))) + return (((((slice w__5 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))) else (read_reg TCR_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 bits) . - return (((((slice0 w__6 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))) \<bind> (\<lambda> (w__7 :: bool) . + return (((((slice w__6 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))) \<bind> (\<lambda> (w__7 :: bool) . (let (using64k :: bool) = w__7 in return (tsz_field, using64k))))) else (assert_exp ((HaveEL EL2)) (''HaveEL(EL2)'') \<then> (if (((top_bit = (vec_of_bits [B1] :: 1 Word.word)))) then (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 :: 64 bits) . - return ((Word.uint ((slice0 w__8 (( 16 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) + return ((Word.uint ((slice w__8 (( 16 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) else (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 bits) . - return ((Word.uint ((slice0 w__9 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))))) \<bind> (\<lambda> (w__10 :: ii) . + return ((Word.uint ((slice w__9 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))))) \<bind> (\<lambda> (w__10 :: ii) . (let tsz_field = w__10 in (if (((top_bit = (vec_of_bits [B1] :: 1 Word.word)))) then (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . - return (((((slice0 w__11 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))) + return (((((slice w__11 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))) else (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 :: 64 bits) . - return (((((slice0 w__12 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))) \<bind> (\<lambda> (w__13 :: bool) . + return (((((slice w__12 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))) \<bind> (\<lambda> (w__13 :: bool) . (let (using64k :: bool) = w__13 in return (tsz_field, using64k)))))) else read_reg PSTATE_ref \<bind> (\<lambda> (w__14 :: ProcState) . (if ((((ProcState_EL w__14) = EL2))) then (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: 64 bits) . - return ((Word.uint ((slice0 w__15 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) + return ((Word.uint ((slice w__15 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) else (read_reg TCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 bits) . - return ((Word.uint ((slice0 w__16 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)))))) \<bind> (\<lambda> (w__17 :: ii) . + return ((Word.uint ((slice w__16 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)))))) \<bind> (\<lambda> (w__17 :: ii) . (let tsz_field = w__17 in read_reg PSTATE_ref \<bind> (\<lambda> (w__18 :: ProcState) . (if ((((ProcState_EL w__18) = EL2))) then (read_reg TCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 bits) . - return (((((slice0 w__19 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))) + return (((((slice w__19 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))) else (read_reg TCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . - return (((((slice0 w__20 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . + return (((((slice w__20 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . (let (using64k :: bool) = w__21 in return (tsz_field, using64k)))))))) \<bind> (\<lambda> varstup . (let ((tsz_field :: ii), (using64k :: bool)) = varstup in (let (max_limit_tsz_field :: ii) = ((( 39 :: int)::ii)) in @@ -8071,8 +8127,8 @@ definition aset_SPSR :: "(32)Word.word \<Rightarrow>((register_value),(unit),(e UsingAArch32 () \<bind> (\<lambda> (w__0 :: bool) . if w__0 then read_reg PSTATE_ref \<bind> (\<lambda> (w__1 :: ProcState) . - (let p__611 = ((ProcState_M w__1)) in - (let pat0 = p__611 in + (let p__298 = ((ProcState_M w__1)) in + (let pat0 = p__298 in if (((pat0 = M32_FIQ))) then write_reg SPSR_fiq_ref value_name else if (((pat0 = M32_IRQ))) then write_reg SPSR_irq_ref value_name else if (((pat0 = M32_Svc))) then write_reg SPSR_svc_ref value_name @@ -8083,8 +8139,8 @@ definition aset_SPSR :: "(32)Word.word \<Rightarrow>((register_value),(unit),(e else Unreachable () ))) else read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . - (let p__610 = ((ProcState_EL w__2)) in - (let pat0 = p__610 in + (let p__297 = ((ProcState_EL w__2)) in + (let pat0 = p__297 in if (((pat0 = EL1))) then write_reg SPSR_EL1_ref value_name else if (((pat0 = EL2))) then write_reg SPSR_EL2_ref value_name else if (((pat0 = EL3))) then write_reg SPSR_EL3_ref value_name @@ -8099,8 +8155,8 @@ definition aget_SPSR :: " unit \<Rightarrow>((register_value),((32)Word.word),( UsingAArch32 () \<bind> (\<lambda> (w__0 :: bool) . if w__0 then read_reg PSTATE_ref \<bind> (\<lambda> (w__1 :: ProcState) . - (let p__609 = ((ProcState_M w__1)) in - (let pat0 = p__609 in + (let p__296 = ((ProcState_M w__1)) in + (let pat0 = p__296 in if (((pat0 = M32_FIQ))) then (read_reg SPSR_fiq_ref :: ( 32 Word.word) M) else if (((pat0 = M32_IRQ))) then (read_reg SPSR_irq_ref :: ( 32 Word.word) M) else if (((pat0 = M32_Svc))) then (read_reg SPSR_svc_ref :: ( 32 Word.word) M) @@ -8111,8 +8167,8 @@ definition aget_SPSR :: " unit \<Rightarrow>((register_value),((32)Word.word),( else Unreachable () \<then> return result))) else read_reg PSTATE_ref \<bind> (\<lambda> (w__9 :: ProcState) . - (let p__608 = ((ProcState_EL w__9)) in - (let pat0 = p__608 in + (let p__295 = ((ProcState_EL w__9)) in + (let pat0 = p__295 in if (((pat0 = EL1))) then (read_reg SPSR_EL1_ref :: ( 32 Word.word) M) else if (((pat0 = EL2))) then (read_reg SPSR_EL2_ref :: ( 32 Word.word) M) else if (((pat0 = EL3))) then (read_reg SPSR_EL3_ref :: ( 32 Word.word) M) @@ -8160,20 +8216,20 @@ definition FPProcessException :: " FPExc \<Rightarrow>(32)Word.word \<Rightarro (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . write_reg FPSCR_ref - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__1 cumul (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__1 cumul (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) else (read_reg FPSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . write_reg FPSR_ref - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 cumul (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))))))))" + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 cumul (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))))))))" (*val FPRoundBase : forall 'N . Size 'N => integer -> real -> mword ty32 -> FPRounding -> M (mword 'N)*) definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \<Rightarrow> FPRounding \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " FPRoundBase (N__tv :: int) op1 fpcr rounding = ( - (let l__164 = N__tv in - if (((l__164 = (( 16 :: int)::ii)))) then + (let p00 = N__tv in + if (((p00 = (( 16 :: int)::ii)))) then (((assert_exp True ('''') \<then> assert_exp (((op1 \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) ('''')) \<then> assert_exp (((rounding \<noteq> FPRounding_TIEAWAY))) ('''')) \<then> @@ -8217,12 +8273,12 @@ definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \ (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . write_reg FPSCR_ref - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__1 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__1 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) else (read_reg FPSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . write_reg FPSR_ref - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)))) \<then> + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)))) \<then> (FPZero (( 16 :: int)::ii) sign :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (w__3 :: ( 'N::len)Word.word) . return ((Word.ucast w__3 :: ( 'N::len)Word.word)))) else @@ -8288,7 +8344,7 @@ definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \ else (biased_exp, int_mant)) in (let (int_mant :: ii) = (if ((((((error \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) \<and> (((rounding = FPRounding_ODD)))))) then - set_slice_int0 (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + set_slice_int (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) else int_mant) in (if (((False \<or> ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then if ((((ex_int biased_exp)) \<ge> ((((pow2 (( 5 :: int)::ii))) - (( 1 :: int)::ii))))) then @@ -8336,7 +8392,7 @@ definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \ (if (((error \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) then FPProcessException FPExc_Inexact fpcr else return () ) \<then> return ((Word.ucast result :: ( 'N::len)Word.word)))))))))))))))))))))))))) - else if (((l__164 = (( 32 :: int)::ii)))) then + else if (((p00 = (( 32 :: int)::ii)))) then (((assert_exp True ('''') \<then> assert_exp (((op1 \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) ('''')) \<then> assert_exp (((rounding \<noteq> FPRounding_TIEAWAY))) ('''')) \<then> @@ -8380,12 +8436,12 @@ definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \ (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 Word.word) . write_reg FPSCR_ref - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__9 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__9 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) else (read_reg FPSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . write_reg FPSR_ref - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__10 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)))) \<then> + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__10 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)))) \<then> (FPZero (( 32 :: int)::ii) sign :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (w__11 :: ( 'N::len)Word.word) . return ((Word.ucast w__11 :: ( 'N::len)Word.word)))) else @@ -8451,38 +8507,15 @@ definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \ else (biased_exp, int_mant)) in (let (int_mant :: ii) = (if ((((((error \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) \<and> (((rounding = FPRounding_ODD)))))) then - set_slice_int0 (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + set_slice_int (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) else int_mant) in - (if (((True \<or> ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then - if ((((ex_int biased_exp)) \<ge> ((((pow2 (( 8 :: int)::ii))) - (( 1 :: int)::ii))))) then - (if overflow_to_inf then (FPInfinity (( 32 :: int)::ii) sign :: ( 32 Word.word) M) - else (FPMaxNormal (( 32 :: int)::ii) sign :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__14 :: 32 Word.word) . - (let result = w__14 in - FPProcessException FPExc_Overflow fpcr \<then> - ((let (error :: real) = (realFromFrac(( 10 :: int))(( 10 :: int))) in - return (error, result))))) - else - (let (result :: 32 bits) = - ((concat_vec - ((concat_vec sign - ((GetSlice_int - ((make_the_value (((((( 32 :: int)::ii) - (( 23 :: int)::ii))) - (( 1 :: int)::ii))) - :: 8 itself)) biased_exp (( 0 :: int)::ii) - :: 8 Word.word)) - :: 9 Word.word)) - ((GetSlice_int ((make_the_value (( 23 :: int)::ii) :: 23 itself)) int_mant (( 0 :: int)::ii) - :: 23 Word.word)) - :: 32 Word.word)) in - return (error, result)) - else if ((((ex_int biased_exp)) \<ge> ((pow2 (( 8 :: int)::ii))))) then - (let result = - ((concat_vec sign - ((Ones__0 ((make_the_value (((( 32 :: int)::ii) - (( 1 :: int)::ii))) :: 31 itself)) - :: 31 Word.word)) - :: 32 Word.word)) in - FPProcessException FPExc_InvalidOp fpcr \<then> - ((let (error :: real) = (realFromFrac(( 0 :: int))(( 10 :: int))) in - return (error, result)))) + (if ((((ex_int biased_exp)) \<ge> ((((pow2 (( 8 :: int)::ii))) - (( 1 :: int)::ii))))) then + (if overflow_to_inf then (FPInfinity (( 32 :: int)::ii) sign :: ( 32 Word.word) M) + else (FPMaxNormal (( 32 :: int)::ii) sign :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__14 :: 32 Word.word) . + (let result = w__14 in + FPProcessException FPExc_Overflow fpcr \<then> + ((let (error :: real) = (realFromFrac(( 10 :: int))(( 10 :: int))) in + return (error, result))))) else (let (result :: 32 bits) = ((concat_vec @@ -8499,7 +8532,7 @@ definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \ (if (((error \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) then FPProcessException FPExc_Inexact fpcr else return () ) \<then> return ((Word.ucast result :: ( 'N::len)Word.word)))))))))))))))))))))))))) - else if (((l__164 = (( 64 :: int)::ii)))) then + else if (((p00 = (( 64 :: int)::ii)))) then (((assert_exp True ('''') \<then> assert_exp (((op1 \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) ('''')) \<then> assert_exp (((rounding \<noteq> FPRounding_TIEAWAY))) ('''')) \<then> @@ -8543,12 +8576,12 @@ definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \ (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__17 :: 32 Word.word) . write_reg FPSCR_ref - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__17 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__17 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) else (read_reg FPSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 Word.word) . write_reg FPSR_ref - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__18 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)))) \<then> + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__18 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)))) \<then> (FPZero (( 64 :: int)::ii) sign :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (w__19 :: ( 'N::len)Word.word) . return ((Word.ucast w__19 :: ( 'N::len)Word.word)))) else @@ -8614,38 +8647,15 @@ definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \ else (biased_exp, int_mant)) in (let (int_mant :: ii) = (if ((((((error \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) \<and> (((rounding = FPRounding_ODD)))))) then - set_slice_int0 (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + set_slice_int (( 1 :: int)::ii) int_mant (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) else int_mant) in - (if (((True \<or> ((((vec_of_bits [access_vec_dec fpcr (( 26 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then - if ((((ex_int biased_exp)) \<ge> ((((pow2 (( 11 :: int)::ii))) - (( 1 :: int)::ii))))) then - (if overflow_to_inf then (FPInfinity (( 64 :: int)::ii) sign :: ( 64 Word.word) M) - else (FPMaxNormal (( 64 :: int)::ii) sign :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__22 :: 64 Word.word) . - (let result = w__22 in - FPProcessException FPExc_Overflow fpcr \<then> - ((let (error :: real) = (realFromFrac(( 10 :: int))(( 10 :: int))) in - return (error, result))))) - else - (let (result :: 64 bits) = - ((concat_vec - ((concat_vec sign - ((GetSlice_int - ((make_the_value (((((( 64 :: int)::ii) - (( 52 :: int)::ii))) - (( 1 :: int)::ii))) - :: 11 itself)) biased_exp (( 0 :: int)::ii) - :: 11 Word.word)) - :: 12 Word.word)) - ((GetSlice_int ((make_the_value (( 52 :: int)::ii) :: 52 itself)) int_mant (( 0 :: int)::ii) - :: 52 Word.word)) - :: 64 Word.word)) in - return (error, result)) - else if ((((ex_int biased_exp)) \<ge> ((pow2 (( 11 :: int)::ii))))) then - (let result = - ((concat_vec sign - ((Ones__0 ((make_the_value (((( 64 :: int)::ii) - (( 1 :: int)::ii))) :: 63 itself)) - :: 63 Word.word)) - :: 64 Word.word)) in - FPProcessException FPExc_InvalidOp fpcr \<then> - ((let (error :: real) = (realFromFrac(( 0 :: int))(( 10 :: int))) in - return (error, result)))) + (if ((((ex_int biased_exp)) \<ge> ((((pow2 (( 11 :: int)::ii))) - (( 1 :: int)::ii))))) then + (if overflow_to_inf then (FPInfinity (( 64 :: int)::ii) sign :: ( 64 Word.word) M) + else (FPMaxNormal (( 64 :: int)::ii) sign :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__22 :: 64 Word.word) . + (let result = w__22 in + FPProcessException FPExc_Overflow fpcr \<then> + ((let (error :: real) = (realFromFrac(( 10 :: int))(( 10 :: int))) in + return (error, result))))) else (let (result :: 64 bits) = ((concat_vec @@ -8670,7 +8680,7 @@ definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \ definition FPRoundCV :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \<Rightarrow> FPRounding \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " FPRoundCV (N__tv :: int) op1 fpcr__arg rounding = ( (let fpcr = fpcr__arg in - (let fpcr = ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 19 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) in + (let fpcr = ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 19 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) in (FPRoundBase N__tv op1 fpcr rounding :: (( 'N::len)Word.word) M))))" @@ -8681,7 +8691,7 @@ definition FPRoundCV :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \<R definition FPRound__0 :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \<Rightarrow> FPRounding \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " FPRound__0 (N__tv :: int) op1 fpcr__arg rounding = ( (let fpcr = fpcr__arg in - (let fpcr = ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 26 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) in + (let fpcr = ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 26 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) in (FPRoundBase N__tv op1 fpcr rounding :: (( 'N::len)Word.word) M))))" @@ -8714,12 +8724,12 @@ definition FPProcessNaN :: " FPType \<Rightarrow>('N::len)Word.word \<Rightarro ((assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size op1))) = (( 32 :: int)::ii)))) \<or> (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> assert_exp ((((((typ1 = FPType_QNaN))) \<or> (((typ1 = FPType_SNaN)))))) (''((type == FPType_QNaN) || (type == FPType_SNaN))'')) \<then> undefined_int () ) \<bind> (\<lambda> (topfrac :: ii) . - (let l__161 = (int (size op1)) in + (let p00 = (int (size op1)) in (let (topfrac :: ii) = - (if (((l__161 = (( 16 :: int)::ii)))) then + (if (((p00 = (( 16 :: int)::ii)))) then (let (op1 :: 16 Word.word) = ((Word.ucast op1 :: 16 Word.word)) in (( 9 :: int)::ii)) - else if (((l__161 = (( 32 :: int)::ii)))) then + else if (((p00 = (( 32 :: int)::ii)))) then (let (op1 :: 32 Word.word) = ((Word.ucast op1 :: 32 Word.word)) in (( 22 :: int)::ii)) else @@ -8728,7 +8738,7 @@ definition FPProcessNaN :: " FPType \<Rightarrow>('N::len)Word.word \<Rightarro (let (result :: 'N bits) = op1 in (if (((typ1 = FPType_SNaN))) then (let result = - ((set_slice0 ((int (size op1))) (( 1 :: int)::ii) result topfrac (vec_of_bits [B1] :: 1 Word.word) :: ( 'N::len)Word.word)) in + ((set_slice ((int (size op1))) (( 1 :: int)::ii) result topfrac (vec_of_bits [B1] :: 1 Word.word) :: ( 'N::len)Word.word)) in FPProcessException FPExc_InvalidOp fpcr \<then> return result) else return result) \<bind> (\<lambda> (result :: 'N bits) . if ((((vec_of_bits [access_vec_dec fpcr (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then @@ -8835,13 +8845,13 @@ definition AArch32_ExecutingLSMInstr :: " unit \<Rightarrow>((register_value),( CurrentInstrSet () \<bind> (\<lambda> (instr_set :: InstrSet) . assert_exp ((((((instr_set = InstrSet_A32))) \<or> (((instr_set = InstrSet_T32)))))) (''((instr_set == InstrSet_A32) || (instr_set == InstrSet_T32))'') \<then> (if (((instr_set = InstrSet_A32))) then - return ((((((((slice0 instr (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) \<noteq> (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word)))) \<and> (((((slice0 instr (( 25 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word))))))) + return ((((((((slice instr (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) \<noteq> (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word)))) \<and> (((((slice instr (( 25 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word))))))) else ThisInstrLength () \<bind> (\<lambda> (w__0 :: ii) . return (if (((((ex_int w__0)) = (( 16 :: int)::ii)))) then - (((slice0 instr (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word)) + (((slice instr (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word)) else - ((((((slice0 instr (( 25 :: int)::ii) (( 7 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0,B0] :: 7 Word.word)))) \<and> ((((vec_of_bits [access_vec_dec instr (( 22 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))))))))" + ((((((slice instr (( 25 :: int)::ii) (( 7 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0,B0] :: 7 Word.word)))) \<and> ((((vec_of_bits [access_vec_dec instr (( 22 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))))))))" (*val AArch32_ExecutingCP10or11Instr : unit -> M bool*) @@ -8852,13 +8862,13 @@ definition AArch32_ExecutingCP10or11Instr :: " unit \<Rightarrow>((register_val CurrentInstrSet () \<bind> (\<lambda> (instr_set :: InstrSet) . assert_exp ((((((instr_set = InstrSet_A32))) \<or> (((instr_set = InstrSet_T32)))))) (''((instr_set == InstrSet_A32) || (instr_set == InstrSet_T32))'') \<then> return (if (((instr_set = InstrSet_A32))) then - (((((((((slice0 instr (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) \<or> (((((slice0 instr (( 25 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) \<and> (((((and_vec ((slice0 instr (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + (((((((((slice instr (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) \<or> (((((slice instr (( 25 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) \<and> (((((and_vec ((slice instr (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) :: 4 Word.word)) = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word))))) else - (((((((((and_vec ((slice0 instr (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + (((((((((and_vec ((slice instr (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) - :: 4 Word.word)) = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) \<and> ((((((((slice0 instr (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) \<or> (((((slice0 instr (( 25 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))))))))) \<and> (((((and_vec ((slice0 instr (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + :: 4 Word.word)) = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) \<and> ((((((((slice instr (( 24 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word)))) \<or> (((((slice instr (( 25 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))))))))) \<and> (((((and_vec ((slice instr (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) :: 4 Word.word)) = (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word)))))))))" @@ -8875,7 +8885,7 @@ definition AArch32_ReportDeferredSError :: "(2)Word.word \<Rightarrow>(1)Word.w " AArch32_ReportDeferredSError AET ExT = ( (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (target :: 32 bits) . (let (target :: 32 bits) = - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) target (( 31 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)) in + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) target (( 31 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)) in (let (syndrome :: 16 bits) = ((Zeros__0 ((make_the_value (( 16 :: int)::ii) :: 16 itself)) :: 16 Word.word)) in read_reg PSTATE_ref \<bind> (\<lambda> (w__0 :: ProcState) . (if ((((ProcState_EL w__0) = EL2))) then @@ -8982,9 +8992,9 @@ definition Halted :: " unit \<Rightarrow>((register_value),(bool),(exception))m " Halted _ = ( or_boolM ((read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . - return (((((slice0 w__0 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))))) + return (((((slice w__0 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))))) ((read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . - return (((((slice0 w__1 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word)))))) \<bind> (\<lambda> (w__2 :: bool) . + return (((((slice w__1 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word)))))) \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2))))" @@ -9004,8 +9014,8 @@ definition FPUnpackBase :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rig (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (sign :: 1 bits) . (if (((((int (size fpval))) = (( 16 :: int)::ii)))) then (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec fpval (( 15 :: int)::ii)] :: 1 Word.word)) in - (let (exp16 :: 5 bits) = ((slice0 fpval (( 10 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in - (let (frac16 :: 10 bits) = ((slice0 fpval (( 0 :: int)::ii) (( 10 :: int)::ii) :: 10 Word.word)) in + (let (exp16 :: 5 bits) = ((slice fpval (( 10 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in + (let (frac16 :: 10 bits) = ((slice fpval (( 0 :: int)::ii) (( 10 :: int)::ii) :: 10 Word.word)) in (let ((typ1 :: FPType), (value_name :: real)) = (if ((IsZero exp16)) then (let ((typ1 :: FPType), (value_name :: real)) = @@ -9050,8 +9060,8 @@ definition FPUnpackBase :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rig return (sign, typ1, value_name))))) else if (((((int (size fpval))) = (( 32 :: int)::ii)))) then (let sign = ((vec_of_bits [access_vec_dec fpval (( 31 :: int)::ii)] :: 1 Word.word)) in - (let exp32 = ((slice0 fpval (( 23 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) in - (let frac32 = ((slice0 fpval (( 0 :: int)::ii) (( 23 :: int)::ii) :: 23 Word.word)) in + (let exp32 = ((slice fpval (( 23 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) in + (let frac32 = ((slice fpval (( 0 :: int)::ii) (( 23 :: int)::ii) :: 23 Word.word)) in (if ((IsZero exp32)) then if (((((IsZero frac32)) \<or> ((((vec_of_bits [access_vec_dec fpcr (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then (let typ1 = FPType_Zero in @@ -9095,8 +9105,8 @@ definition FPUnpackBase :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rig return (sign, typ1, value_name)))))) else (let sign = ((vec_of_bits [access_vec_dec fpval (( 63 :: int)::ii)] :: 1 Word.word)) in - (let exp64 = ((slice0 fpval (( 52 :: int)::ii) (( 11 :: int)::ii) :: 11 Word.word)) in - (let frac64 = ((slice0 fpval (( 0 :: int)::ii) (( 52 :: int)::ii) :: 52 Word.word)) in + (let exp64 = ((slice fpval (( 52 :: int)::ii) (( 11 :: int)::ii) :: 11 Word.word)) in + (let frac64 = ((slice fpval (( 0 :: int)::ii) (( 52 :: int)::ii) :: 52 Word.word)) in (if ((IsZero exp64)) then if (((((IsZero frac64)) \<or> ((((vec_of_bits [access_vec_dec fpcr (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then (let typ1 = FPType_Zero in @@ -9150,7 +9160,7 @@ definition FPUnpackBase :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rig definition FPUnpackCV :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(FPType*(1)Word.word*real),(exception))monad " where " FPUnpackCV fpval fpcr__arg = ( (let fpcr = fpcr__arg in - (let fpcr = ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 19 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) in + (let fpcr = ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 19 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) in undefined_real () \<bind> (\<lambda> (value_name :: real) . (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (sign :: 1 bits) . undefined_FPType () \<bind> (\<lambda> (fp_type :: FPType) . @@ -9167,8 +9177,8 @@ definition FPUnpackCV :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Right definition FPConvert__0 :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow>(32)Word.word \<Rightarrow> FPRounding \<Rightarrow>((register_value),(('M::len)Word.word),(exception))monad " where " FPConvert__0 (M__tv :: int) op1 fpcr rounding = ( - (let l__158 = M__tv in - if (((l__158 = (( 16 :: int)::ii)))) then + (let p00 = M__tv in + if (((p00 = (( 16 :: int)::ii)))) then ((assert_exp True ('''') \<then> assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size op1))) = (( 32 :: int)::ii)))) \<or> (((((int (size op1))) = (( 64 :: int)::ii)))))))))) ('''')) \<then> (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (result :: 16 bits) . @@ -9202,7 +9212,7 @@ definition FPConvert__0 :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow>( else (FPRoundCV (( 16 :: int)::ii) value_name fpcr rounding :: ( 16 Word.word) M)) \<bind> (\<lambda> (result :: 16 bits) . return ((Word.ucast result :: ( 'M::len)Word.word))))))))))))) - else if (((l__158 = (( 32 :: int)::ii)))) then + else if (((p00 = (( 32 :: int)::ii)))) then ((assert_exp True ('''') \<then> assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size op1))) = (( 32 :: int)::ii)))) \<or> (((((int (size op1))) = (( 64 :: int)::ii)))))))))) ('''')) \<then> (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (result :: 32 bits) . @@ -9236,7 +9246,7 @@ definition FPConvert__0 :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow>( else (FPRoundCV (( 32 :: int)::ii) value_name fpcr rounding :: ( 32 Word.word) M)) \<bind> (\<lambda> (result :: 32 bits) . return ((Word.ucast result :: ( 'M::len)Word.word))))))))))))) - else if (((l__158 = (( 64 :: int)::ii)))) then + else if (((p00 = (( 64 :: int)::ii)))) then ((assert_exp True ('''') \<then> assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size op1))) = (( 32 :: int)::ii)))) \<or> (((((int (size op1))) = (( 64 :: int)::ii)))))))))) ('''')) \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (result :: 64 bits) . @@ -9283,7 +9293,7 @@ definition FPConvert__1 :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow>( definition FPUnpack :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(FPType*(1)Word.word*real),(exception))monad " where " FPUnpack fpval fpcr__arg = ( (let fpcr = fpcr__arg in - (let fpcr = ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 26 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) in + (let fpcr = ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) fpcr (( 26 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) in undefined_real () \<bind> (\<lambda> (value_name :: real) . (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (sign :: 1 bits) . undefined_FPType () \<bind> (\<lambda> (fp_type :: FPType) . @@ -9369,7 +9379,7 @@ definition FPToFixedJS :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow>(3 (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) . write_reg FPSCR_ref - ((set_slice0 (( 32 :: int)::ii) (( 4 :: int)::ii) w__4 (( 28 :: int)::ii) + ((set_slice (( 32 :: int)::ii) (( 4 :: int)::ii) w__4 (( 28 :: int)::ii) ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) Z :: 2 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) :: 4 Word.word)) @@ -10008,11 +10018,11 @@ definition ExternalDebugInterruptsDisabled :: "(2)Word.word \<Rightarrow>((regi if (((pat0 = EL3))) then and_boolM ((read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . - return (((((slice0 w__0 (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))) ((ExternalSecureInvasiveDebugEnabled () )) + return (((((slice w__0 (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))) ((ExternalSecureInvasiveDebugEnabled () )) else if (((pat0 = EL2))) then and_boolM ((read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 bits) . - return (((((and_vec ((slice0 w__3 (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + return (((((and_vec ((slice w__3 (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) (vec_of_bits [B1,B0] :: 2 Word.word) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))) ((ExternalInvasiveDebugEnabled () )) @@ -10021,14 +10031,14 @@ definition ExternalDebugInterruptsDisabled :: "(2)Word.word \<Rightarrow>((regi if w__6 then and_boolM ((read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . - return (((((and_vec ((slice0 w__7 (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + return (((((and_vec ((slice w__7 (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) (vec_of_bits [B1,B0] :: 2 Word.word) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))))) ((ExternalSecureInvasiveDebugEnabled () )) else and_boolM ((read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . - return (((((slice0 w__10 (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) \<noteq> (vec_of_bits [B0,B0] :: 2 Word.word)))))) ((ExternalInvasiveDebugEnabled () ))))))" + return (((((slice w__10 (( 22 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) \<noteq> (vec_of_bits [B0,B0] :: 2 Word.word)))))) ((ExternalInvasiveDebugEnabled () ))))))" (*val ELStateUsingAArch32K : mword ty2 -> bool -> M (bool * bool)*) @@ -10115,44 +10125,44 @@ definition UpdateEDSCRFields :: " unit \<Rightarrow>((register_value),(unit),(e (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . (write_reg EDSCR_ref - ((set_slice0 (( 32 :: int)::ii) (( 2 :: int)::ii) w__1 (( 8 :: int)::ii) (vec_of_bits [B0,B0] :: 2 Word.word) :: 32 Word.word)) \<then> + ((set_slice (( 32 :: int)::ii) (( 2 :: int)::ii) w__1 (( 8 :: int)::ii) (vec_of_bits [B0,B0] :: 2 Word.word) :: 32 Word.word)) \<then> (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 :: 32 Word.word) . (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__3 :: 1 Word.word) . - (write_reg EDSCR_ref ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 (( 18 :: int)::ii) w__3 :: 32 Word.word)) \<then> + (write_reg EDSCR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 (( 18 :: int)::ii) w__3 :: 32 Word.word)) \<then> (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__4 :: 32 Word.word) . write_reg EDSCR_ref - ((set_slice0 (( 32 :: int)::ii) (( 4 :: int)::ii) w__4 (( 10 :: int)::ii) (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word) + ((set_slice (( 32 :: int)::ii) (( 4 :: int)::ii) w__4 (( 10 :: int)::ii) (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word) :: 32 Word.word)))))) else (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 Word.word) . read_reg PSTATE_ref \<bind> (\<lambda> (w__6 :: ProcState) . - (write_reg EDSCR_ref ((set_slice0 (( 32 :: int)::ii) (( 2 :: int)::ii) w__5 (( 8 :: int)::ii)(ProcState_EL w__6) :: 32 Word.word)) \<then> + (write_reg EDSCR_ref ((set_slice (( 32 :: int)::ii) (( 2 :: int)::ii) w__5 (( 8 :: int)::ii)(ProcState_EL w__6) :: 32 Word.word)) \<then> (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__7 :: 32 Word.word) . IsSecure () \<bind> (\<lambda> (w__8 :: bool) . (write_reg EDSCR_ref - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__7 (( 18 :: int)::ii) + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__7 (( 18 :: int)::ii) (if w__8 then (vec_of_bits [B0] :: 1 Word.word) else (vec_of_bits [B1] :: 1 Word.word)) :: 32 Word.word)) \<then> (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \<bind> (\<lambda> (RW :: 4 bits) . ELUsingAArch32 EL1 \<bind> (\<lambda> (w__9 :: bool) . (let (RW :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 1 :: int)::ii) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 1 :: int)::ii) (if w__9 then (vec_of_bits [B0] :: 1 Word.word) else (vec_of_bits [B1] :: 1 Word.word)) :: 4 Word.word)) in read_reg PSTATE_ref \<bind> (\<lambda> (w__10 :: ProcState) . (if ((((ProcState_EL w__10) \<noteq> EL0))) then (let (RW :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)] :: 1 Word.word) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)] :: 1 Word.word) :: 4 Word.word)) in return RW) else UsingAArch32 () \<bind> (\<lambda> (w__11 :: bool) . (let (RW :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) (if w__11 then (vec_of_bits [B0] :: 1 Word.word) else (vec_of_bits [B1] :: 1 Word.word)) :: 4 Word.word)) in @@ -10163,45 +10173,45 @@ definition UpdateEDSCRFields :: " unit \<Rightarrow>((register_value),(unit),(e return ((((vec_of_bits [access_vec_dec w__12 (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) \<bind> (\<lambda> (w__14 :: bool) . (if w__14 then (let (RW :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 2 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)] :: 1 Word.word) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 2 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)] :: 1 Word.word) :: 4 Word.word)) in return RW) else ELUsingAArch32 EL2 \<bind> (\<lambda> (w__15 :: bool) . (let (RW :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 2 :: int)::ii) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 2 :: int)::ii) (if w__15 then (vec_of_bits [B0] :: 1 Word.word) else (vec_of_bits [B1] :: 1 Word.word)) :: 4 Word.word)) in return RW))) \<bind> (\<lambda> (RW :: 4 bits) . (if ((\<not> ((HaveEL EL3)))) then (let (RW :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 3 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 2 :: int)::ii)] :: 1 Word.word) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 3 :: int)::ii) (vec_of_bits [access_vec_dec RW (( 2 :: int)::ii)] :: 1 Word.word) :: 4 Word.word)) in return RW) else ELUsingAArch32 EL3 \<bind> (\<lambda> (w__16 :: bool) . (let (RW :: 4 bits) = - ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 3 :: int)::ii) + ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 3 :: int)::ii) (if w__16 then (vec_of_bits [B0] :: 1 Word.word) else (vec_of_bits [B1] :: 1 Word.word)) :: 4 Word.word)) in return RW))) \<bind> (\<lambda> (RW :: 4 bits) . (if ((((vec_of_bits [access_vec_dec RW (( 3 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then (undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M) \<bind> (\<lambda> (w__17 :: 3 Word.word) . - (let (RW :: 4 bits) = ((set_slice0 (( 4 :: int)::ii) (( 3 :: int)::ii) RW (( 0 :: int)::ii) w__17 :: 4 Word.word)) in + (let (RW :: 4 bits) = ((set_slice (( 4 :: int)::ii) (( 3 :: int)::ii) RW (( 0 :: int)::ii) w__17 :: 4 Word.word)) in return RW)) else if ((((vec_of_bits [access_vec_dec RW (( 2 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__18 :: 2 Word.word) . - (let (RW :: 4 bits) = ((set_slice0 (( 4 :: int)::ii) (( 2 :: int)::ii) RW (( 0 :: int)::ii) w__18 :: 4 Word.word)) in + (let (RW :: 4 bits) = ((set_slice (( 4 :: int)::ii) (( 2 :: int)::ii) RW (( 0 :: int)::ii) w__18 :: 4 Word.word)) in return RW)) else if ((((vec_of_bits [access_vec_dec RW (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__19 :: 1 Word.word) . - (let (RW :: 4 bits) = ((set_slice0 (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) w__19 :: 4 Word.word)) in + (let (RW :: 4 bits) = ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) w__19 :: 4 Word.word)) in return RW)) else return RW) \<bind> (\<lambda> (RW :: 4 bits) . (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 Word.word) . - write_reg EDSCR_ref ((set_slice0 (( 32 :: int)::ii) (( 4 :: int)::ii) w__20 (( 10 :: int)::ii) RW :: 32 Word.word))))))))))))))))))" + write_reg EDSCR_ref ((set_slice (( 32 :: int)::ii) (( 4 :: int)::ii) w__20 (( 10 :: int)::ii) RW :: 32 Word.word))))))))))))))))))" (*val Halt : mword ty6 -> M unit*) @@ -10370,9 +10380,9 @@ definition S2ConvertAttrsHints :: "(2)Word.word \<Rightarrow> AccType \<Rightar definition S2AttrDecode :: "(2)Word.word \<Rightarrow>(4)Word.word \<Rightarrow> AccType \<Rightarrow>((register_value),(MemoryAttributes),(exception))monad " where " S2AttrDecode SH attr acctype = ( undefined_MemoryAttributes () \<bind> (\<lambda> (memattrs :: MemoryAttributes) . - (if (((((slice0 attr (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (if (((((slice attr (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) then (let (memattrs :: MemoryAttributes) = ((memattrs (| MemoryAttributes_typ := MemType_Device |))) in - (let b__0 = ((slice0 attr (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let b__0 = ((slice attr (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in (let (memattrs :: MemoryAttributes) = (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then (memattrs (| MemoryAttributes_device := DeviceType_nGnRnE |)) @@ -10382,13 +10392,13 @@ definition S2AttrDecode :: "(2)Word.word \<Rightarrow>(4)Word.word \<Rightarrow (memattrs (| MemoryAttributes_device := DeviceType_nGRE |)) else (memattrs (| MemoryAttributes_device := DeviceType_GRE |))) in return memattrs))) - else if (((((slice0 attr (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) \<noteq> (vec_of_bits [B0,B0] :: 2 Word.word)))) + else if (((((slice attr (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) \<noteq> (vec_of_bits [B0,B0] :: 2 Word.word)))) then (let memattrs = ((memattrs (| MemoryAttributes_typ := MemType_Normal |))) in - S2ConvertAttrsHints ((slice0 attr (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) acctype \<bind> (\<lambda> (w__0 :: + S2ConvertAttrsHints ((slice attr (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) acctype \<bind> (\<lambda> (w__0 :: MemAttrHints) . (let memattrs = ((memattrs (| MemoryAttributes_outer := w__0 |))) in - S2ConvertAttrsHints ((slice0 attr (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) acctype \<bind> (\<lambda> (w__1 :: + S2ConvertAttrsHints ((slice attr (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) acctype \<bind> (\<lambda> (w__1 :: MemAttrHints) . (let (memattrs :: MemoryAttributes) = ((memattrs (| MemoryAttributes_inner := w__1 |))) in (let (memattrs :: MemoryAttributes) = @@ -10661,25 +10671,25 @@ definition LongConvertAttrsHints :: "(4)Word.word \<Rightarrow> AccType \<Right (if w__0 then (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_NC |))) in (result (| MemAttrHints_hints := MemHint_No |))) - else if (((((slice0 attrfield (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + else if (((((slice attrfield (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) then (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_WT |))) in (let (result :: MemAttrHints) = - ((result (| MemAttrHints_hints := ((slice0 attrfield (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|))) in + ((result (| MemAttrHints_hints := ((slice attrfield (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|))) in (result (| MemAttrHints_transient := True |)))) - else if (((((slice0 attrfield (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then + else if (((((slice attrfield (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := MemAttr_NC |))) in (let (result :: MemAttrHints) = ((result (| MemAttrHints_hints := MemHint_No |))) in (result (| MemAttrHints_transient := False |)))) - else if (((((slice0 attrfield (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + else if (((((slice attrfield (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) then (let (result :: MemAttrHints) = - ((result (| MemAttrHints_attrs := ((slice0 attrfield (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|))) in + ((result (| MemAttrHints_attrs := ((slice attrfield (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|))) in (let (result :: MemAttrHints) = ((result (| MemAttrHints_hints := MemAttr_WB |))) in (result (| MemAttrHints_transient := True |)))) else (let (result :: MemAttrHints) = - ((result (| MemAttrHints_attrs := ((slice0 attrfield (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|))) in + ((result (| MemAttrHints_attrs := ((slice attrfield (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|))) in (let (result :: MemAttrHints) = - ((result (| MemAttrHints_hints := ((slice0 attrfield (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|))) in + ((result (| MemAttrHints_hints := ((slice attrfield (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|))) in (result (| MemAttrHints_transient := False |))))) in return result))))" @@ -10804,11 +10814,11 @@ definition AArch64_CheckAndUpdateDescriptor_SecondStage :: " DescriptorUpdate \ (let desc = w__1 in (let (desc :: 64 bits) = (if hw_update_AF then - (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 10 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word) + (set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 10 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word) else desc) in (let (desc :: 64 bits) = (if hw_update_AP then - (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word) + (set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word) else desc) in aset__Mem descaddr2 (( 8 :: int)::ii) accdesc desc))))))) else return () ) \<then> @@ -10902,10 +10912,10 @@ definition ZeroExtend_slice_append :: " int \<Rightarrow>('n::len)Word.word \<R " ZeroExtend_slice_append (o__tv :: int) xs i l ys = ( assert_exp True ('''') \<then> ((let xs = ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) in - (ZeroExtend__1 o__tv ((shiftr xs i :: ( 'n::len)Word.word)) :: (( 'o::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'o::len)Word.word) . - (let (xs :: 'o bits) = ((shiftl w__0 ((int (size ys))) :: ( 'o::len)Word.word)) in - (ZeroExtend__1 ((int (size xs))) ys :: (( 'o::len)Word.word) M) \<bind> (\<lambda> (ys :: 'o bits) . - return ((or_vec xs ys :: ( 'o::len)Word.word))))))))" + (let (xs :: 'o bits) = + ((shiftl ((extzv o__tv ((shiftr xs i :: ( 'n::len)Word.word)) :: ( 'o::len)Word.word)) ((int (size ys))) :: ( 'o::len)Word.word)) in + (let (ys :: 'o bits) = ((extzv ((int (size xs))) ys :: ( 'o::len)Word.word)) in + return ((or_vec xs ys :: ( 'o::len)Word.word)))))))" definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightarrow>(64)Word.word \<Rightarrow> AccType \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> int \<Rightarrow>((register_value),(TLBRecord),(exception))monad " where @@ -10951,13 +10961,13 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar liftR ((ZeroExtend__1 (( 64 :: int)::ii) ipaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__6 :: 64 bits) . (let inputaddr = w__6 in liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__7 :: 32 bits) . - (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__7 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice w__7 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__8 :: 32 bits) . (let largegrain = - (((slice0 w__8 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + (((slice w__8 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__9 :: 32 bits) . (let midgrain = - (((slice0 w__9 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in + (((slice w__9 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in (let inputsize_max = (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii) else (( 48 :: int)::ii)) in (if ((((ex_int inputsize)) > ((ex_int inputsize_max)))) then (let c = (ConstrainUnpredictable Unpredictable_RESTnSZ) in @@ -10973,7 +10983,7 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar return inputsize))) else return inputsize) \<bind> (\<lambda> (inputsize :: ii) . liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__10 :: 32 bits) . - (let ps = ((slice0 w__10 (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let ps = ((slice w__10 (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in and_boolM (return (((((((ex_int inputsize)) \<ge> ((ex_int inputsize_min)))) \<and> ((((ex_int inputsize)) \<le> ((ex_int inputsize_max)))))))) (liftR ((IsZero_slice inputaddr inputsize @@ -10986,9 +10996,9 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__14 :: 32 bits) . liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__15 :: 32 bits) . liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__16 :: 32 bits) . - liftR (WalkAttrDecode ((slice0 w__14 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__15 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__16 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) True) \<bind> (\<lambda> (w__17 :: MemoryAttributes) . + liftR (WalkAttrDecode ((slice w__14 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__15 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__16 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) True) \<bind> (\<lambda> (w__17 :: MemoryAttributes) . (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__17 |))) in liftR ((read_reg SCTLR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__18 :: 32 bits) . (let reversedescriptors = @@ -11004,7 +11014,7 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar return ((((vec_of_bits [access_vec_dec w__21 (( 22 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \<bind> (\<lambda> (w__22 :: bool) . (let update_AP = w__22 in liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__23 :: 32 bits) . - (let startlevel = (Word.uint ((slice0 w__23 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) in + (let startlevel = (Word.uint ((slice w__23 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) in (let ((firstblocklevel :: ii), (grainsize :: ii), (level :: ii)) = (if largegrain then (let (grainsize :: ii) = ((( 16 :: int)::ii)) in @@ -11117,7 +11127,7 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar (let z = (if ((baselowerbound < (( 6 :: int)::ii))) then (( 6 :: int)::ii) else baselowerbound) in liftR (assert_exp True ('''')) \<then> ((let (baseaddress :: 52 bits) = - ((concat_vec ((slice0 baseregister (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((concat_vec ((slice baseregister (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) ((slice_zeros_concat ((((((- z)) + (( 48 :: int)::ii))) + z)) baseregister z ((((- z)) + (( 48 :: int)::ii))) z :: 48 Word.word)) @@ -11148,10 +11158,39 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar liftR (undefined_bool () ) \<bind> (\<lambda> (hwupdatewalk :: bool) . liftR (undefined_AddressDescriptor () ) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . liftR (undefined_int () ) \<bind> (\<lambda> (addrselectbottom :: ii) . - (untilM (addrselectbottom, desc, descaddr, level, result) - (\<lambda> varstup . (let (addrselectbottom, desc, descaddr, level, result) = varstup in + (untilM (accdesc, + addrselectbottom, + addrselecttop, + baseaddress, + blocktranslate, + desc, + descaddr, + descaddr2, + level, + result) + (\<lambda> varstup . + (let (accdesc, + addrselectbottom, + addrselecttop, + baseaddress, + blocktranslate, + desc, + descaddr, + descaddr2, + level, + result) = varstup in return blocktranslate)) - (\<lambda> varstup . (let (addrselectbottom, desc, descaddr, level, result) = varstup in + (\<lambda> varstup . + (let (accdesc, + addrselectbottom, + addrselecttop, + baseaddress, + blocktranslate, + desc, + descaddr, + descaddr2, + level, + result) = varstup in (let addrselectbottom = ((((((( 3 :: int)::ii) - ((ex_int level)))) * ((ex_int stride)))) + @@ -11180,21 +11219,22 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar (let desc = w__36 in (if reversedescriptors then liftR ((BigEndianReverse desc :: ( 64 Word.word) M)) else return desc) \<bind> (\<lambda> (desc :: 64 bits) . - (if (((((((vec_of_bits [access_vec_dec desc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) \<or> ((((((((slice0 desc (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((ex_int level)) = (( 3 :: int)::ii)))))))))) + (if (((((((vec_of_bits [access_vec_dec desc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) \<or> ((((((((slice desc (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((ex_int level)) = (( 3 :: int)::ii)))))))))) then (let (tmp_240 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in liftR (AArch64_TranslationFault ipaddress level acctype iswrite True s2fs1walk) \<bind> (\<lambda> (w__38 :: FaultRecord) . (let tmp_240 = ((tmp_240 (| AddressDescriptor_fault := w__38 |))) in (let result = ((result (| TLBRecord_addrdesc := tmp_240 |))) in - (early_return result :: (unit, TLBRecord) MR) \<then> return (level, result))))) - else if ((((((((slice0 desc (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<or> (((((ex_int level)) = (( 3 :: int)::ii))))))) + (early_return result :: (unit, TLBRecord) MR) \<then> + return (addrselecttop, baseaddress, blocktranslate, level, result))))) + else if ((((((((slice desc (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<or> (((((ex_int level)) = (( 3 :: int)::ii))))))) then (let (blocktranslate :: bool) = True in - return (level, result)) + return (addrselecttop, baseaddress, blocktranslate, level, result)) else or_boolM - (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))))))) + (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))))))) (and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii)))) (liftR (IsZero_slice desc outputsize ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \<bind> (\<lambda> (w__39 :: @@ -11206,32 +11246,41 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar FaultRecord) . (let tmp_250 = ((tmp_250 (| AddressDescriptor_fault := w__42 |))) in (let result = ((result (| TLBRecord_addrdesc := tmp_250 |))) in - (early_return result :: (unit, TLBRecord) MR) \<then> return (level, result))))) + (early_return result :: (unit, TLBRecord) MR) \<then> + return (addrselecttop, baseaddress, blocktranslate, level, result))))) else (let gsz = grainsize in liftR (assert_exp True ('''')) \<then> - ((let (_ :: unit) = + ((let (baseaddress :: 52 bits) = (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then - (let (baseaddress :: 52 bits) = - ((concat_vec ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) - ((slice_zeros_concat - ((((((- gsz)) + (( 48 :: int)::ii))) + gsz)) desc - gsz ((((- gsz)) + (( 48 :: int)::ii))) gsz - :: 48 Word.word)) - :: 52 Word.word)) in - () ) + (concat_vec ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((slice_zeros_concat + ((((((- gsz)) + (( 48 :: int)::ii))) + gsz)) desc + gsz ((((- gsz)) + (( 48 :: int)::ii))) gsz + :: 48 Word.word)) + :: 52 Word.word) else - (let (baseaddress :: 52 bits) = - ((place_slice (( 52 :: int)::ii) desc gsz ((((- gsz)) + (( 48 :: int)::ii))) - gsz - :: 52 Word.word)) in - () )) in + (place_slice (( 52 :: int)::ii) desc gsz ((((- gsz)) + (( 48 :: int)::ii))) + gsz + :: 52 Word.word)) in (let (level :: ii) = (((ex_int level)) + (( 1 :: int)::ii)) in (let (addrselecttop :: ii) = (((ex_int addrselectbottom)) - (( 1 :: int)::ii)) in (let (blocktranslate :: bool) = False in - return (level, result))))))))) \<bind> (\<lambda> varstup . (let ((level :: ii), (result :: TLBRecord)) = varstup in - return (addrselectbottom, desc, descaddr, level, result)))))))))))))))))))))) \<bind> (\<lambda> varstup . (let ((addrselectbottom :: - ii), (desc :: 64 bits), (descaddr :: AddressDescriptor), (level :: ii), (result :: + return (addrselecttop, baseaddress, blocktranslate, level, result))))))))) \<bind> (\<lambda> varstup . (let ((addrselecttop :: + ii), (baseaddress :: 52 bits), (blocktranslate :: bool), (level :: ii), (result :: + TLBRecord)) = varstup in + return (accdesc, + addrselectbottom, + addrselecttop, + baseaddress, + blocktranslate, + desc, + descaddr, + descaddr2, + level, + result)))))))))))))))))))))) \<bind> (\<lambda> varstup . (let ((accdesc :: AccessDescriptor), (addrselectbottom :: + ii), (addrselecttop :: ii), (baseaddress :: 52 bits), (blocktranslate :: bool), (desc :: 64 + bits), (descaddr :: AddressDescriptor), (descaddr2 :: AddressDescriptor), (level :: ii), (result :: TLBRecord)) = varstup in if ((((ex_int level)) < ((ex_int firstblocklevel)))) then (let (tmp_260 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in @@ -11260,7 +11309,7 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar else return result) else return result) \<bind> (\<lambda> (result :: TLBRecord) . or_boolM - (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))))))) + (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))))))) (and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii)))) (liftR (IsZero_slice desc outputsize ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \<bind> (\<lambda> (w__46 :: @@ -11280,7 +11329,7 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar liftR (assert_exp True ('''')) \<then> ((let (outputaddress :: 52 bits) = (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then - (concat_vec ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + (concat_vec ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) ((slice_slice_concat (( 48 :: int)::ii) desc asb ((((- asb)) + (( 48 :: int)::ii))) inputaddr (( 0 :: int)::ii) asb :: 48 Word.word)) @@ -11308,7 +11357,7 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar (let ((desc :: 64 bits), (result :: TLBRecord)) = (if ((((vec_of_bits [access_vec_dec desc (( 7 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then (let (desc :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) in (let (tmp_320 :: DescriptorUpdate) = ((TLBRecord_descupdate result)) in (let (tmp_320 :: DescriptorUpdate) = @@ -11334,7 +11383,7 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar (let (contiguousbit :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 52 :: int)::ii)] :: 1 Word.word)) in (let (nG :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 11 :: int)::ii)] :: 1 Word.word)) in - (let (sh :: 2 bits) = ((slice0 desc (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let (sh :: 2 bits) = ((slice desc (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in liftR ((undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M)) \<bind> (\<lambda> (ap :: 3 bits) . (let (ap :: 3 bits) = (if apply_nvnv1_effect then @@ -11342,10 +11391,10 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar (vec_of_bits [B0,B1] :: 2 Word.word) :: 3 Word.word) else - (concat_vec ((slice0 desc (( 6 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + (concat_vec ((slice desc (( 6 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) (vec_of_bits [B1] :: 1 Word.word) :: 3 Word.word)) in - (let (memattr :: 4 bits) = ((slice0 desc (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + (let (memattr :: 4 bits) = ((slice desc (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in liftR ((undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \<bind> (\<lambda> (w__51 :: 4 bits) . (let result = ((result (| TLBRecord_domain := w__51 |))) in (let result = ((result (| TLBRecord_level := level |))) in @@ -11358,14 +11407,14 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar ((ex_int grainsize))))))|))) in (let (tmp_480 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in (let tmp_480 = - ((set_slice0 (( 3 :: int)::ii) (( 2 :: int)::ii) tmp_480 (( 1 :: int)::ii) ((slice0 ap (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((set_slice (( 3 :: int)::ii) (( 2 :: int)::ii) tmp_480 (( 1 :: int)::ii) ((slice ap (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) :: 3 Word.word)) in (let (tmp_490 :: Permissions) = ((TLBRecord_perms result)) in (let tmp_490 = ((tmp_490 (| Permissions_ap := tmp_480 |))) in (let result = ((result (| TLBRecord_perms := tmp_490 |))) in (let (tmp_500 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in (let tmp_500 = - ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_500 (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + ((set_slice (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_500 (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 3 Word.word)) in (let (tmp_510 :: Permissions) = ((TLBRecord_perms result)) in (let tmp_510 = ((tmp_510 (| Permissions_ap := tmp_500 |))) in @@ -11429,7 +11478,7 @@ definition AArch64_SecondStageTranslate :: " AddressDescriptor \<Rightarrow>(64 (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \<bind> (\<lambda> (ipaddress :: 52 bits) . if s2_enabled then (let ipaddress = - ((slice0(FullAddress_physicaladdress (AddressDescriptor_paddress S1)) (( 0 :: int)::ii) (( 52 :: int)::ii) :: 52 Word.word)) in + ((slice(FullAddress_physicaladdress (AddressDescriptor_paddress S1)) (( 0 :: int)::ii) (( 52 :: int)::ii) :: 52 Word.word)) in AArch64_TranslationTableWalk_SecondStage ipaddress vaddress acctype iswrite s2fs1walk size1 \<bind> (\<lambda> (w__3 :: TLBRecord) . (let S2 = w__3 in @@ -11603,7 +11652,7 @@ definition SSAdvance :: " unit \<Rightarrow>((register_value),(unit),(exception definition ConditionHolds :: "(4)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " ConditionHolds cond = ( undefined_bool () \<bind> (\<lambda> (result :: bool) . - (let b__0 = ((slice0 cond (( 1 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let b__0 = ((slice cond (( 1 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in (if (((b__0 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then read_reg PSTATE_ref \<bind> (\<lambda> (w__0 :: ProcState) . (let (result :: bool) = ((ProcState_Z w__0) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -12037,31 +12086,31 @@ definition ConditionSyndrome :: " unit \<Rightarrow>((register_value),((5)Word. read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . if ((((ProcState_T w__2) = (vec_of_bits [B0] :: 1 Word.word)))) then (let syndrome = - ((set_slice0 (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 5 Word.word)) in + ((set_slice (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 5 Word.word)) in and_boolM ((ConditionHolds cond)) ((ConstrainUnpredictableBool Unpredictable_ESRCONDPASS)) \<bind> (\<lambda> (w__5 :: bool) . (let (syndrome :: 5 bits) = (if w__5 then - (set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) + (set_slice (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) :: 5 Word.word) - else (set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) cond :: 5 Word.word)) in + else (set_slice (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) cond :: 5 Word.word)) in return syndrome))) else if ((IMPDEF_boolean (''Condition valid for trapped T32''))) then (let (syndrome :: 5 bits) = - ((set_slice0 (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 5 Word.word)) in - (let (syndrome :: 5 bits) = ((set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) cond :: 5 Word.word)) in + ((set_slice (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 5 Word.word)) in + (let (syndrome :: 5 bits) = ((set_slice (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) cond :: 5 Word.word)) in return syndrome)) else (let syndrome = - ((set_slice0 (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 5 Word.word)) in + ((set_slice (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 5 Word.word)) in (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__6 :: 4 Word.word) . - (let (syndrome :: 5 bits) = ((set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) w__6 :: 5 Word.word)) in + (let (syndrome :: 5 bits) = ((set_slice (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) w__6 :: 5 Word.word)) in return syndrome)))))) else (let (syndrome :: 5 bits) = - ((set_slice0 (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 5 Word.word)) in + ((set_slice (( 5 :: int)::ii) (( 1 :: int)::ii) syndrome (( 4 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 5 Word.word)) in (let (syndrome :: 5 bits) = - ((set_slice0 (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) + ((set_slice (( 5 :: int)::ii) (( 4 :: int)::ii) syndrome (( 0 :: int)::ii) (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word) :: 5 Word.word)) in return syndrome))))))" @@ -12081,7 +12130,7 @@ definition BranchToAddr :: "('N::len)Word.word \<Rightarrow> BranchType \<Right and_boolM (return (((((int (size target))) = (( 64 :: int)::ii))))) (UsingAArch32 () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2)))) \<bind> (\<lambda> (w__3 :: bool) . assert_exp w__3 (''((N == 64) && !(UsingAArch32()))'') \<then> - write_reg PC_ref ((slice0 target (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word))))))" + write_reg PC_ref ((slice target (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word))))))" (*val BadMode : mword ty5 -> M bool*) @@ -12231,7 +12280,7 @@ definition ELFromSPSR :: "(32)Word.word \<Rightarrow>((register_value),(bool*(2 undefined_bool () \<bind> (\<lambda> (valid_name :: bool) . (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (el :: 2 bits) . (if ((((vec_of_bits [access_vec_dec spsr (( 4 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then - (let el = ((slice0 spsr (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let el = ((slice spsr (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in (if ((HighestELUsingAArch32 () )) then return False else if ((\<not> ((HaveEL el)))) then return False else if ((((vec_of_bits [access_vec_dec spsr (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then @@ -12249,7 +12298,7 @@ definition ELFromSPSR :: "(32)Word.word \<Rightarrow>((register_value),(bool*(2 (let (valid_name :: bool) = False in return (el, valid_name)) else - (ELFromM32 ((slice0 spsr (( 0 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) :: ((bool * 2 Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (ELFromM32 ((slice spsr (( 0 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) :: ((bool * 2 Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in (let (valid_name :: bool) = tup__0 in (let (el :: 2 bits) = tup__1 in return (el, valid_name)))))) \<bind> (\<lambda> varstup . (let ((el :: 2 bits), (valid_name :: bool)) = varstup in @@ -12580,21 +12629,21 @@ definition AArch64_vESBOperation :: " unit \<Rightarrow>((register_value),(unit ((if w__12 then (read_reg VDFSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . (read_reg VDFSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 bits) . - (AArch32_ReportDeferredSError ((slice0 w__13 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + (AArch32_ReportDeferredSError ((slice w__13 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) (vec_of_bits [access_vec_dec w__14 (( 12 :: int)::ii)] :: 1 Word.word) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . (let (VDISR :: 32 bits) = w__15 in return () )))) else (read_reg VSESR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 bits) . - (AArch64_ReportDeferredSError ((slice0 w__16 (( 0 :: int)::ii) (( 25 :: int)::ii) :: 25 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 + (AArch64_ReportDeferredSError ((slice w__16 (( 0 :: int)::ii) (( 25 :: int)::ii) :: 25 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 bits) . (let (VDISR_EL2 :: 64 bits) = w__17 in return () )))) \<then> (read_reg HCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__18 :: 64 Word.word) . write_reg HCR_EL2_ref - ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) w__18 (( 8 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))) + ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) w__18 (( 8 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))) else return () ))))))))" @@ -12732,6 +12781,9 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word liftR (undefined_AddressDescriptor () ) \<bind> (\<lambda> (descaddr :: AddressDescriptor) . liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (baseregister :: 64 bits) . liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (inputaddr :: 64 bits) . + (let (tmp_170 :: FaultRecord) = ((AddressDescriptor_fault descaddr)) in + (let tmp_170 = ((tmp_170 (| FaultRecord_typ := Fault_None |))) in + (let descaddr = ((descaddr (| AddressDescriptor_fault := tmp_170 |))) in (let (tmp_180 :: MemoryAttributes) = ((AddressDescriptor_memattrs descaddr)) in (let tmp_180 = ((tmp_180 (| MemoryAttributes_typ := MemType_Normal |))) in (let descaddr = ((descaddr (| AddressDescriptor_memattrs := tmp_180 |))) in @@ -12769,12 +12821,12 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (if ((((ProcState_EL w__11) = EL3))) then liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__12 :: 32 bits) . (let largegrain = - (((slice0 w__12 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + (((slice w__12 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__13 :: 32 bits) . (let midgrain = - (((slice0 w__13 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in + (((slice w__13 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__14 :: 32 bits) . - (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__14 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice w__14 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in (let inputsize_max = (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii) else (( 48 :: int)::ii)) in @@ -12792,7 +12844,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word return inputsize))) else return inputsize) \<bind> (\<lambda> (inputsize :: ii) . liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__15 :: 32 bits) . - (let ps = ((slice0 w__15 (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let ps = ((slice w__15 (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in and_boolM (return (((((((ex_int inputsize)) \<ge> ((ex_int inputsize_min)))) \<and> ((((ex_int inputsize)) \<le> ((ex_int inputsize_max)))))))) (liftR ((IsZero_slice inputaddr inputsize @@ -12805,9 +12857,9 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__19 :: 32 bits) . liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__20 :: 32 bits) . liftR ((read_reg TCR_EL3_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__21 :: 32 bits) . - liftR (WalkAttrDecode ((slice0 w__19 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__20 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__21 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__22 :: + liftR (WalkAttrDecode ((slice w__19 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__20 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__21 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__22 :: MemoryAttributes) . (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__22 |))) in liftR ((read_reg SCTLR_EL3_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__23 :: 32 bits) . @@ -12847,13 +12899,13 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (if ((((vec_of_bits [access_vec_dec inputaddr top1] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__31 :: 64 bits) . (let largegrain = - (((slice0 w__31 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + (((slice w__31 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__32 :: 64 bits) . (let midgrain = - (((slice0 w__32 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in + (((slice w__32 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__33 :: 64 bits) . (let inputsize = - ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__33 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + ((( 64 :: int)::ii) - ((Word.uint ((slice w__33 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in (let inputsize_max = (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii) else (( 48 :: int)::ii)) in @@ -12889,9 +12941,9 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__38 :: 64 bits) . liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__39 :: 64 bits) . liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__40 :: 64 bits) . - liftR (WalkAttrDecode ((slice0 w__38 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__39 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__40 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__41 :: + liftR (WalkAttrDecode ((slice w__38 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__39 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__40 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__41 :: MemoryAttributes) . (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__41 |))) in and_boolM (return ((AArch64_HaveHPDExt () ))) @@ -12909,13 +12961,13 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word else liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__44 :: 64 bits) . (let inputsize = - ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__44 (( 16 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + ((( 64 :: int)::ii) - ((Word.uint ((slice w__44 (( 16 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__45 :: 64 bits) . (let largegrain = - (((slice0 w__45 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)) in + (((slice w__45 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)) in liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__46 :: 64 bits) . (let midgrain = - (((slice0 w__46 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + (((slice w__46 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in (let inputsize_max = (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii) else (( 48 :: int)::ii)) in @@ -12951,9 +13003,9 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__51 :: 64 bits) . liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__52 :: 64 bits) . liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__53 :: 64 bits) . - liftR (WalkAttrDecode ((slice0 w__51 (( 28 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__52 (( 26 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__53 (( 24 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__54 :: + liftR (WalkAttrDecode ((slice w__51 (( 28 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__52 (( 26 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__53 (( 24 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__54 :: MemoryAttributes) . (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__54 |))) in and_boolM (return ((AArch64_HaveHPDExt () ))) @@ -12971,7 +13023,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word bits), (descaddr :: AddressDescriptor), (disabled :: bool), (hierattrsdisabled :: bool), (inputsize :: ii), (largegrain :: bool), (midgrain :: bool)) = varstup in liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__57 :: 64 bits) . - (let ps = ((slice0 w__57 (( 32 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let ps = ((slice w__57 (( 32 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in liftR ((read_reg SCTLR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__58 :: 32 bits) . (let reversedescriptors = ((vec_of_bits [access_vec_dec w__58 (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -13004,13 +13056,13 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word if ((((ProcState_EL w__63) = EL2))) then liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__64 :: 64 bits) . (let inputsize = - ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__64 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + ((( 64 :: int)::ii) - ((Word.uint ((slice w__64 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__65 :: 64 bits) . (let largegrain = - (((slice0 w__65 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + (((slice w__65 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__66 :: 64 bits) . (let midgrain = - (((slice0 w__66 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in + (((slice w__66 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in (let inputsize_max = (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii) else (( 48 :: int)::ii)) in @@ -13033,7 +13085,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word return inputsize))) else return inputsize) \<bind> (\<lambda> (inputsize :: ii) . liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__67 :: 64 bits) . - (let ps = ((slice0 w__67 (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let ps = ((slice w__67 (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in and_boolM (return (((((((ex_int inputsize)) \<ge> ((ex_int inputsize_min)))) \<and> ((((ex_int inputsize)) \<le> ((ex_int inputsize_max)))))))) (liftR ((IsZero_slice inputaddr inputsize @@ -13046,9 +13098,9 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__71 :: 64 bits) . liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__72 :: 64 bits) . liftR ((read_reg TCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__73 :: 64 bits) . - liftR (WalkAttrDecode ((slice0 w__71 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__72 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__73 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__74 :: + liftR (WalkAttrDecode ((slice w__71 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__72 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__73 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__74 :: MemoryAttributes) . (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__74 |))) in liftR ((read_reg SCTLR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__75 :: 32 bits) . @@ -13086,13 +13138,13 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (if ((((vec_of_bits [access_vec_dec inputaddr top1] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__82 :: 64 bits) . (let inputsize = - ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__82 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + ((( 64 :: int)::ii) - ((Word.uint ((slice w__82 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__83 :: 64 bits) . (let largegrain = - (((slice0 w__83 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + (((slice w__83 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__84 :: 64 bits) . (let midgrain = - (((slice0 w__84 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in + (((slice w__84 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in (let inputsize_max = (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii) else (( 48 :: int)::ii)) in @@ -13128,9 +13180,9 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__89 :: 64 bits) . liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__90 :: 64 bits) . liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__91 :: 64 bits) . - liftR (WalkAttrDecode ((slice0 w__89 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__90 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__91 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__92 :: + liftR (WalkAttrDecode ((slice w__89 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__90 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__91 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__92 :: MemoryAttributes) . (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__92 |))) in and_boolM (return ((AArch64_HaveHPDExt () ))) @@ -13148,13 +13200,13 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word else liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__95 :: 64 bits) . (let inputsize = - ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__95 (( 16 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + ((( 64 :: int)::ii) - ((Word.uint ((slice w__95 (( 16 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__96 :: 64 bits) . (let largegrain = - (((slice0 w__96 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)) in + (((slice w__96 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)) in liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__97 :: 64 bits) . (let midgrain = - (((slice0 w__97 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + (((slice w__97 (( 30 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in (let inputsize_max = (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii) else (( 48 :: int)::ii)) in @@ -13190,9 +13242,9 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__102 :: 64 bits) . liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__103 :: 64 bits) . liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__104 :: 64 bits) . - liftR (WalkAttrDecode ((slice0 w__102 (( 28 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__103 (( 26 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__104 (( 24 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__105 :: + liftR (WalkAttrDecode ((slice w__102 (( 28 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__103 (( 26 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__104 (( 24 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__105 :: MemoryAttributes) . (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__105 |))) in and_boolM (return ((AArch64_HaveHPDExt () ))) @@ -13210,7 +13262,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word bits), (descaddr :: AddressDescriptor), (disabled :: bool), (hierattrsdisabled :: bool), (inputsize :: ii), (largegrain :: bool), (midgrain :: bool)) = varstup in liftR ((read_reg TCR_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__108 :: 64 bits) . - (let ps = ((slice0 w__108 (( 32 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let ps = ((slice w__108 (( 32 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in liftR ((read_reg SCTLR_EL1_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__109 :: 32 bits) . (let reversedescriptors = ((vec_of_bits [access_vec_dec w__109 (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -13289,13 +13341,13 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word liftR ((ZeroExtend__1 (( 64 :: int)::ii) ipaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__115 :: 64 bits) . (let inputaddr = w__115 in liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__116 :: 32 bits) . - (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice0 w__116 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in + (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice w__116 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__117 :: 32 bits) . (let largegrain = - (((slice0 w__117 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + (((slice w__117 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__118 :: 32 bits) . (let midgrain = - (((slice0 w__118 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in + (((slice w__118 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)) in (let inputsize_max = (if (((((Have52BitVAExt () )) \<and> largegrain))) then (( 52 :: int)::ii) else (( 48 :: int)::ii)) in @@ -13313,7 +13365,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word return inputsize))) else return inputsize) \<bind> (\<lambda> (inputsize :: ii) . liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__119 :: 32 bits) . - (let ps = ((slice0 w__119 (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let ps = ((slice w__119 (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in and_boolM (return (((((((ex_int inputsize)) \<ge> ((ex_int inputsize_min)))) \<and> ((((ex_int inputsize)) \<le> ((ex_int inputsize_max)))))))) (liftR ((IsZero_slice inputaddr inputsize @@ -13326,9 +13378,9 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__123 :: 32 bits) . liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__124 :: 32 bits) . liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__125 :: 32 bits) . - liftR (WalkAttrDecode ((slice0 w__123 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__124 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) - ((slice0 w__125 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__126 :: + liftR (WalkAttrDecode ((slice w__123 (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__124 (( 10 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice w__125 (( 12 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) secondstage) \<bind> (\<lambda> (w__126 :: MemoryAttributes) . (let descaddr = ((descaddr (| AddressDescriptor_memattrs := w__126 |))) in liftR ((read_reg SCTLR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__127 :: 32 bits) . @@ -13345,7 +13397,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word return ((((vec_of_bits [access_vec_dec w__130 (( 22 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \<bind> (\<lambda> (w__131 :: bool) . (let update_AP = w__131 in liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__132 :: 32 bits) . - (let startlevel = (Word.uint ((slice0 w__132 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) in + (let startlevel = (Word.uint ((slice w__132 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) in (let ((firstblocklevel :: ii), (grainsize :: ii), (level :: ii)) = (if largegrain then (let (grainsize :: ii) = ((( 16 :: int)::ii)) in @@ -13479,7 +13531,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (let z = (if ((baselowerbound < (( 6 :: int)::ii))) then (( 6 :: int)::ii) else baselowerbound) in liftR (assert_exp True ('''')) \<then> ((let (baseaddress :: 52 bits) = - ((concat_vec ((slice0 baseregister (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((concat_vec ((slice baseregister (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) ((slice_zeros_concat ((((((- z)) + (( 48 :: int)::ii))) + z)) baseregister z ((((- z)) + (( 48 :: int)::ii))) z :: 48 Word.word)) @@ -13510,20 +13562,32 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word liftR (undefined_bool () ) \<bind> (\<lambda> (hwupdatewalk :: bool) . liftR (undefined_AddressDescriptor () ) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . liftR (undefined_int () ) \<bind> (\<lambda> (addrselectbottom :: ii) . - (untilM (addrselectbottom, + (untilM (accdesc, + addrselectbottom, + addrselecttop, ap_table, + baseaddress, + blocktranslate, desc, descaddr, + descaddr2, + hwupdatewalk, level, ns_table, pxn_table, result, xn_table) (\<lambda> varstup . - (let (addrselectbottom, + (let (accdesc, + addrselectbottom, + addrselecttop, ap_table, + baseaddress, + blocktranslate, desc, descaddr, + descaddr2, + hwupdatewalk, level, ns_table, pxn_table, @@ -13531,10 +13595,16 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word xn_table) = varstup in return blocktranslate)) (\<lambda> varstup . - (let (addrselectbottom, + (let (accdesc, + addrselectbottom, + addrselecttop, ap_table, + baseaddress, + blocktranslate, desc, descaddr, + descaddr2, + hwupdatewalk, level, ns_table, pxn_table, @@ -13562,7 +13632,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word bool) . (if w__144 then (let (descaddr2 :: AddressDescriptor) = descaddr in - return (descaddr2, result)) + return (descaddr2, hwupdatewalk, result)) else (let hwupdatewalk = False in liftR (AArch64_SecondStageWalk descaddr vaddress acctype iswrite (( 8 :: int)::ii) @@ -13575,8 +13645,8 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (let result = ((result (| TLBRecord_addrdesc := tmp_230 |))) in (early_return result :: (unit, TLBRecord) MR) \<then> return result))) else return result) \<bind> (\<lambda> (result :: TLBRecord) . - return (descaddr2, result)))))) \<bind> (\<lambda> varstup . (let ((descaddr2 :: AddressDescriptor), (result :: - TLBRecord)) = varstup in + return (descaddr2, hwupdatewalk, result)))))) \<bind> (\<lambda> varstup . (let ((descaddr2 :: + AddressDescriptor), (hwupdatewalk :: bool), (result :: TLBRecord)) = varstup in liftR ((ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__146 :: 64 bits) . (let descaddr2 = ((descaddr2 (| AddressDescriptor_vaddress := w__146 |))) in liftR (CreateAccessDescriptorPTW acctype secondstage s2fs1walk level) \<bind> (\<lambda> (w__147 :: @@ -13587,7 +13657,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (let desc = w__148 in (if reversedescriptors then liftR ((BigEndianReverse desc :: ( 64 Word.word) M)) else return desc) \<bind> (\<lambda> (desc :: 64 bits) . - (if (((((((vec_of_bits [access_vec_dec desc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) \<or> ((((((((slice0 desc (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((ex_int level)) = (( 3 :: int)::ii)))))))))) + (if (((((((vec_of_bits [access_vec_dec desc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) \<or> ((((((((slice desc (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((ex_int level)) = (( 3 :: int)::ii)))))))))) then (let (tmp_240 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in liftR (AArch64_TranslationFault ipaddress level acctype iswrite secondstage @@ -13595,14 +13665,30 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (let tmp_240 = ((tmp_240 (| AddressDescriptor_fault := w__150 |))) in (let result = ((result (| TLBRecord_addrdesc := tmp_240 |))) in (early_return result :: (unit, TLBRecord) MR) \<then> - return (ap_table, level, ns_table, pxn_table, result, xn_table))))) - else if ((((((((slice0 desc (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<or> (((((ex_int level)) = (( 3 :: int)::ii))))))) + return (addrselecttop, + ap_table, + baseaddress, + blocktranslate, + level, + ns_table, + pxn_table, + result, + xn_table))))) + else if ((((((((slice desc (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<or> (((((ex_int level)) = (( 3 :: int)::ii))))))) then (let (blocktranslate :: bool) = True in - return (ap_table, level, ns_table, pxn_table, result, xn_table)) + return (addrselecttop, + ap_table, + baseaddress, + blocktranslate, + level, + ns_table, + pxn_table, + result, + xn_table)) else or_boolM - (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))))))) + (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))))))) (and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii)))) (liftR (IsZero_slice desc outputsize ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \<bind> (\<lambda> (w__151 :: @@ -13615,26 +13701,30 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (let tmp_250 = ((tmp_250 (| AddressDescriptor_fault := w__154 |))) in (let result = ((result (| TLBRecord_addrdesc := tmp_250 |))) in (early_return result :: (unit, TLBRecord) MR) \<then> - return (ap_table, level, ns_table, pxn_table, result, xn_table))))) + return (addrselecttop, + ap_table, + baseaddress, + blocktranslate, + level, + ns_table, + pxn_table, + result, + xn_table))))) else (let gsz = grainsize in liftR (assert_exp True ('''')) \<then> - ((let (_ :: unit) = + ((let (baseaddress :: 52 bits) = (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then - (let (baseaddress :: 52 bits) = - ((concat_vec ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) - ((slice_zeros_concat - ((((((- gsz)) + (( 48 :: int)::ii))) + gsz)) desc - gsz ((((- gsz)) + (( 48 :: int)::ii))) gsz - :: 48 Word.word)) - :: 52 Word.word)) in - () ) + (concat_vec ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + ((slice_zeros_concat + ((((((- gsz)) + (( 48 :: int)::ii))) + gsz)) desc + gsz ((((- gsz)) + (( 48 :: int)::ii))) gsz + :: 48 Word.word)) + :: 52 Word.word) else - (let (baseaddress :: 52 bits) = - ((place_slice (( 52 :: int)::ii) desc gsz ((((- gsz)) + (( 48 :: int)::ii))) - gsz - :: 52 Word.word)) in - () )) in + (place_slice (( 52 :: int)::ii) desc gsz ((((- gsz)) + (( 48 :: int)::ii))) + gsz + :: 52 Word.word)) in (let (ns_table :: 1 bits) = (if ((\<not> secondstage)) then (or_vec ns_table (vec_of_bits [access_vec_dec desc (( 63 :: int)::ii)] :: 1 Word.word) @@ -13643,7 +13733,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (let ((ap_table :: 2 bits), (pxn_table :: 1 bits), (xn_table :: 1 bits)) = (if (((((\<not> secondstage)) \<and> ((\<not> hierattrsdisabled))))) then (let (ap_table :: 2 bits) = - ((set_slice0 (( 2 :: int)::ii) (( 1 :: int)::ii) ap_table (( 1 :: int)::ii) + ((set_slice (( 2 :: int)::ii) (( 1 :: int)::ii) ap_table (( 1 :: int)::ii) ((or_vec (vec_of_bits [access_vec_dec ap_table (( 1 :: int)::ii)] :: 1 Word.word) (vec_of_bits [access_vec_dec desc (( 62 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) @@ -13670,7 +13760,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (vec_of_bits [access_vec_dec desc (( 59 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) in (let (ap_table :: 2 bits) = - ((set_slice0 (( 2 :: int)::ii) (( 1 :: int)::ii) ap_table (( 0 :: int)::ii) + ((set_slice (( 2 :: int)::ii) (( 1 :: int)::ii) ap_table (( 0 :: int)::ii) ((or_vec (vec_of_bits [access_vec_dec ap_table (( 0 :: int)::ii)] :: 1 Word.word) (vec_of_bits [access_vec_dec desc (( 61 :: int)::ii)] :: 1 Word.word) @@ -13685,20 +13775,36 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (let (level :: ii) = (((ex_int level)) + (( 1 :: int)::ii)) in (let (addrselecttop :: ii) = (((ex_int addrselectbottom)) - (( 1 :: int)::ii)) in (let (blocktranslate :: bool) = False in - return (ap_table, level, ns_table, pxn_table, result, xn_table))))))))))) \<bind> (\<lambda> varstup . (let ((ap_table :: 2 - bits), (level :: ii), (ns_table :: 1 bits), (pxn_table :: 1 bits), (result :: - TLBRecord), (xn_table :: 1 bits)) = varstup in - return (addrselectbottom, + return (addrselecttop, + ap_table, + baseaddress, + blocktranslate, + level, + ns_table, + pxn_table, + result, + xn_table))))))))))) \<bind> (\<lambda> varstup . (let ((addrselecttop :: ii), (ap_table :: 2 + bits), (baseaddress :: 52 bits), (blocktranslate :: bool), (level :: ii), (ns_table :: 1 + bits), (pxn_table :: 1 bits), (result :: TLBRecord), (xn_table :: 1 bits)) = varstup in + return (accdesc, + addrselectbottom, + addrselecttop, ap_table, + baseaddress, + blocktranslate, desc, descaddr, + descaddr2, + hwupdatewalk, level, ns_table, pxn_table, result, - xn_table)))))))))))))))))))))))) \<bind> (\<lambda> varstup . (let ((addrselectbottom :: ii), (ap_table :: 2 - bits), (desc :: 64 bits), (descaddr :: AddressDescriptor), (level :: ii), (ns_table :: 1 - bits), (pxn_table :: 1 bits), (result :: TLBRecord), (xn_table :: 1 bits)) = varstup in + xn_table)))))))))))))))))))))))) \<bind> (\<lambda> varstup . (let ((accdesc :: AccessDescriptor), (addrselectbottom :: + ii), (addrselecttop :: ii), (ap_table :: 2 bits), (baseaddress :: 52 bits), (blocktranslate :: + bool), (desc :: 64 bits), (descaddr :: AddressDescriptor), (descaddr2 :: + AddressDescriptor), (hwupdatewalk :: bool), (level :: ii), (ns_table :: 1 bits), (pxn_table :: 1 + bits), (result :: TLBRecord), (xn_table :: 1 bits)) = varstup in if ((((ex_int level)) < ((ex_int firstblocklevel)))) then (let (tmp_260 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in liftR (AArch64_TranslationFault ipaddress level acctype iswrite secondstage s2fs1walk) \<bind> (\<lambda> (w__155 :: @@ -13726,7 +13832,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word else return result) else return result) \<bind> (\<lambda> (result :: TLBRecord) . or_boolM - (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))))))) + (return ((((((((((ex_int outputsize)) < (( 52 :: int)::ii))) \<and> largegrain))) \<and> ((\<not> ((IsZero ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))))))) (and_boolM (return ((((ex_int outputsize)) < (( 48 :: int)::ii)))) (liftR (IsZero_slice desc outputsize ((((- ((ex_int outputsize)))) + (( 48 :: int)::ii)))) \<bind> (\<lambda> (w__158 :: @@ -13747,7 +13853,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word liftR (assert_exp True ('''')) \<then> ((let (outputaddress :: 52 bits) = (if (((((ex_int outputsize)) = (( 52 :: int)::ii)))) then - (concat_vec ((slice0 desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + (concat_vec ((slice desc (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) ((slice_slice_concat (( 48 :: int)::ii) desc asb ((((- asb)) + (( 48 :: int)::ii))) inputaddr (( 0 :: int)::ii) asb :: 48 Word.word)) @@ -13756,6 +13862,11 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (slice_slice_concat (( 52 :: int)::ii) desc asb ((((- asb)) + (( 48 :: int)::ii))) inputaddr (( 0 :: int)::ii) asb :: 52 Word.word)) in + (let (tmp_330 :: DescriptorUpdate) = ((TLBRecord_descupdate result)) in + (let tmp_330 = ((tmp_330 (| DescriptorUpdate_AF := False |))) in + (let tmp_330 = ((tmp_330 (| DescriptorUpdate_AP := False |))) in + (let tmp_330 = ((tmp_330 (| DescriptorUpdate_descaddr := descaddr |))) in + (let result = ((result (| TLBRecord_descupdate := tmp_330 |))) in (if ((((vec_of_bits [access_vec_dec desc (( 10 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))) then if ((\<not> update_AF)) then (let (tmp_290 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in @@ -13775,7 +13886,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (let ((desc :: 64 bits), (result :: TLBRecord)) = (if (((((\<not> secondstage)) \<and> ((((vec_of_bits [access_vec_dec desc (( 7 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))))) then (let (desc :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) + ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) in (let (tmp_310 :: DescriptorUpdate) = ((TLBRecord_descupdate result)) in (let (tmp_310 :: DescriptorUpdate) = @@ -13786,7 +13897,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (let ((desc :: 64 bits), (result :: TLBRecord)) = (if (((secondstage \<and> ((((vec_of_bits [access_vec_dec desc (( 7 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) then (let (desc :: 64 bits) = - ((set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) in (let (tmp_320 :: DescriptorUpdate) = ((TLBRecord_descupdate result)) in (let (tmp_320 :: DescriptorUpdate) = @@ -13797,9 +13908,6 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (desc, result))) in (desc, result)) else (desc, result)) in - (let (tmp_330 :: DescriptorUpdate) = ((TLBRecord_descupdate result)) in - (let tmp_330 = ((tmp_330 (| DescriptorUpdate_descaddr := descaddr |))) in - (let result = ((result (| TLBRecord_descupdate := tmp_330 |))) in liftR ((undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (xn :: 1 bits) . liftR ((undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (pxn :: 1 bits) . (let ((pxn :: 1 bits), (xn :: 1 bits)) = @@ -13814,7 +13922,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (let (contiguousbit :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 52 :: int)::ii)] :: 1 Word.word)) in (let (nG :: 1 bits) = ((vec_of_bits [access_vec_dec desc (( 11 :: int)::ii)] :: 1 Word.word)) in - (let (sh :: 2 bits) = ((slice0 desc (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let (sh :: 2 bits) = ((slice desc (( 8 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in liftR ((undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M)) \<bind> (\<lambda> (ap :: 3 bits) . (let (ap :: 3 bits) = (if apply_nvnv1_effect then @@ -13822,10 +13930,10 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (vec_of_bits [B0,B1] :: 2 Word.word) :: 3 Word.word) else - (concat_vec ((slice0 desc (( 6 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + (concat_vec ((slice desc (( 6 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) (vec_of_bits [B1] :: 1 Word.word) :: 3 Word.word)) in - (let (memattr :: 4 bits) = ((slice0 desc (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + (let (memattr :: 4 bits) = ((slice desc (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in liftR ((undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \<bind> (\<lambda> (w__163 :: 4 bits) . (let result = ((result (| TLBRecord_domain := w__163 |))) in (let result = ((result (| TLBRecord_level := level |))) in @@ -13843,7 +13951,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (let result = ((result (| TLBRecord_perms := tmp_340 |))) in (let (tmp_350 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in (let tmp_350 = - ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_350 (( 2 :: int)::ii) + ((set_slice (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_350 (( 2 :: int)::ii) ((or_vec (vec_of_bits [access_vec_dec ap (( 2 :: int)::ii)] :: 1 Word.word) (vec_of_bits [access_vec_dec ap_table (( 1 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) @@ -13854,7 +13962,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (if ((\<not> singlepriv)) then (let (tmp_370 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in (let tmp_370 = - ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_370 (( 1 :: int)::ii) + ((set_slice (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_370 (( 1 :: int)::ii) ((and_vec (vec_of_bits [access_vec_dec ap (( 1 :: int)::ii)] :: 1 Word.word) ((not_vec (vec_of_bits [access_vec_dec ap_table (( 0 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) @@ -13876,7 +13984,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word else (let (tmp_400 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in (let (tmp_400 :: 3 bits) = - ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_400 (( 1 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + ((set_slice (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_400 (( 1 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 3 Word.word)) in (let (tmp_410 :: Permissions) = ((TLBRecord_perms result)) in (let (tmp_410 :: Permissions) = ((tmp_410 (| Permissions_ap := tmp_400 |))) in @@ -13890,13 +13998,13 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word return result)))))))))) \<bind> (\<lambda> (result :: TLBRecord) . (let (tmp_430 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in (let tmp_430 = - ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_430 (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + ((set_slice (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_430 (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 3 Word.word)) in (let (tmp_440 :: Permissions) = ((TLBRecord_perms result)) in (let tmp_440 = ((tmp_440 (| Permissions_ap := tmp_430 |))) in (let result = ((result (| TLBRecord_perms := tmp_440 |))) in (let (tmp_450 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in - liftR (AArch64_S1AttrDecode sh ((slice0 memattr (( 0 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) acctype) \<bind> (\<lambda> (w__165 :: + liftR (AArch64_S1AttrDecode sh ((slice memattr (( 0 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) acctype) \<bind> (\<lambda> (w__165 :: MemoryAttributes) . (let (tmp_450 :: AddressDescriptor) = ((tmp_450 (| AddressDescriptor_memattrs := w__165 |))) in @@ -13915,14 +14023,14 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word else (let (tmp_480 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in (let tmp_480 = - ((set_slice0 (( 3 :: int)::ii) (( 2 :: int)::ii) tmp_480 (( 1 :: int)::ii) ((slice0 ap (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((set_slice (( 3 :: int)::ii) (( 2 :: int)::ii) tmp_480 (( 1 :: int)::ii) ((slice ap (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) :: 3 Word.word)) in (let (tmp_490 :: Permissions) = ((TLBRecord_perms result)) in (let tmp_490 = ((tmp_490 (| Permissions_ap := tmp_480 |))) in (let result = ((result (| TLBRecord_perms := tmp_490 |))) in (let (tmp_500 :: 3 bits) = ((Permissions_ap (TLBRecord_perms result))) in (let tmp_500 = - ((set_slice0 (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_500 (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + ((set_slice (( 3 :: int)::ii) (( 1 :: int)::ii) tmp_500 (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 3 Word.word)) in (let (tmp_510 :: Permissions) = ((TLBRecord_perms result)) in (let tmp_510 = ((tmp_510 (| Permissions_ap := tmp_500 |))) in @@ -13973,7 +14081,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (result (| TLBRecord_CnP := ((vec_of_bits [access_vec_dec baseregister (( 0 :: int)::ii)] :: 1 Word.word))|)) else result) in - return result))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + return result)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" (*val IsZero_slice2 : forall 'n . Size 'n => mword 'n -> ii -> ii -> M bool*) @@ -14185,7 +14293,7 @@ definition AArch64_TranslateAddressS1Off :: "(64)Word.word \<Rightarrow> AccTyp (let (tmp_2410 :: FullAddress) = ((AddressDescriptor_paddress (TLBRecord_addrdesc result))) in (let tmp_2410 = ((tmp_2410 (| - FullAddress_physicaladdress := ((slice0 vaddress (( 0 :: int)::ii) (( 52 :: int)::ii) :: 52 Word.word))|))) in + FullAddress_physicaladdress := ((slice vaddress (( 0 :: int)::ii) (( 52 :: int)::ii) :: 52 Word.word))|))) in (let (tmp_2420 :: AddressDescriptor) = ((TLBRecord_addrdesc result)) in (let tmp_2420 = ((tmp_2420 (| AddressDescriptor_paddress := tmp_2410 |))) in (let result = ((result (| TLBRecord_addrdesc := tmp_2420 |))) in @@ -14255,7 +14363,7 @@ definition AArch64_MaybeZeroRegisterUppers :: " unit \<Rightarrow>((register_va read_reg R_ref \<bind> (\<lambda> (w__14 :: ( 64 bits) list) . (let (tmp_30 :: 64 bits) = ((access_list_dec w__14 n :: 64 Word.word)) in (let tmp_30 = - ((set_slice0 (( 64 :: int)::ii) (( 32 :: int)::ii) tmp_30 (( 32 :: int)::ii) ((Zeros__1 (( 32 :: int)::ii) () :: 32 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 32 :: int)::ii) tmp_30 (( 32 :: int)::ii) ((Zeros__1 (( 32 :: int)::ii) () :: 32 Word.word)) :: 64 Word.word)) in read_reg R_ref \<bind> (\<lambda> (w__15 :: ( 64 Word.word) list) . write_reg R_ref ((update_list_dec w__15 n tmp_30 :: ( 64 Word.word) list)))))) @@ -14315,7 +14423,7 @@ definition DCPSInstruction :: "(2)Word.word \<Rightarrow>((register_value),(uni (read_reg SCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 Word.word) . write_reg SCR_ref - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__18 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__18 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) else return () ) \<then> UsingAArch32 () ) \<bind> (\<lambda> (w__19 :: bool) . assert_exp w__19 (''UsingAArch32()'') \<then> @@ -14472,23 +14580,23 @@ definition AArch64_FaultSyndrome :: " bool \<Rightarrow> FaultRecord \<Rightarr ((let (iss :: 25 bits) = ((Zeros__1 (( 25 :: int)::ii) () :: 25 Word.word)) in and_boolM (return ((HaveRASExt () ))) ((IsExternalSyncAbort__1 fault)) \<bind> (\<lambda> (w__1 :: bool) . (let (iss :: 25 bits) = - (if w__1 then (set_slice0 (( 25 :: int)::ii) (( 2 :: int)::ii) iss (( 11 :: int)::ii)(FaultRecord_errortype fault) :: 25 Word.word) + (if w__1 then (set_slice (( 25 :: int)::ii) (( 2 :: int)::ii) iss (( 11 :: int)::ii)(FaultRecord_errortype fault) :: 25 Word.word) else iss) in (if d_side then and_boolM ((IsSecondStage fault)) (return ((\<not>(FaultRecord_s2fs1walk fault)))) \<bind> (\<lambda> (w__3 :: bool) . (if w__3 then (LSInstructionSyndrome () :: ( 11 Word.word) M) \<bind> (\<lambda> (w__4 :: 11 Word.word) . - (let (iss :: 25 bits) = ((set_slice0 (( 25 :: int)::ii) (( 11 :: int)::ii) iss (( 14 :: int)::ii) w__4 :: 25 Word.word)) in + (let (iss :: 25 bits) = ((set_slice (( 25 :: int)::ii) (( 11 :: int)::ii) iss (( 14 :: int)::ii) w__4 :: 25 Word.word)) in return iss)) else return iss) \<bind> (\<lambda> (iss :: 25 bits) . (let (iss :: 25 bits) = (if (((((((FaultRecord_acctype fault) = AccType_DC))) \<or> (((((((FaultRecord_acctype fault) = AccType_IC))) \<or> ((((FaultRecord_acctype fault) = AccType_AT))))))))) then (let (iss :: 25 bits) = - ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 8 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 25 Word.word)) in - (set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 6 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 25 Word.word)) + ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 8 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 25 Word.word)) in + (set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 6 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 25 Word.word)) else - (set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 6 :: int)::ii) + (set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 6 :: int)::ii) (if(FaultRecord_write fault) then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word)) :: 25 Word.word)) in @@ -14496,16 +14604,16 @@ definition AArch64_FaultSyndrome :: " bool \<Rightarrow> FaultRecord \<Rightarr else return iss) \<bind> (\<lambda> (iss :: 25 bits) . IsExternalAbort__1 fault \<bind> (\<lambda> (w__5 :: bool) . (let (iss :: 25 bits) = - (if w__5 then (set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 9 :: int)::ii)(FaultRecord_extflag fault) :: 25 Word.word) + (if w__5 then (set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 9 :: int)::ii)(FaultRecord_extflag fault) :: 25 Word.word) else iss) in (let iss = - ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 7 :: int)::ii) + ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) iss (( 7 :: int)::ii) (if(FaultRecord_s2fs1walk fault) then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word)) :: 25 Word.word)) in (EncodeLDFSC(FaultRecord_typ fault)(FaultRecord_level fault) :: ( 6 Word.word) M) \<bind> (\<lambda> (w__6 :: 6 Word.word) . - (let (iss :: 25 bits) = ((set_slice0 (( 25 :: int)::ii) (( 6 :: int)::ii) iss (( 0 :: int)::ii) w__6 :: 25 Word.word)) in + (let (iss :: 25 bits) = ((set_slice (( 25 :: int)::ii) (( 6 :: int)::ii) iss (( 0 :: int)::ii) w__6 :: 25 Word.word)) in return iss)))))))))))" @@ -14540,11 +14648,11 @@ definition AArch64_ExecutingATS1xPInstr :: " unit \<Rightarrow>((register_value (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (CRn :: 4 bits) . (undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M) \<bind> (\<lambda> (op1 :: 3 bits) . (let (w__0 :: bool) = - (if (((((slice0 instr (( 22 :: int)::ii) (( 10 :: int)::ii) :: 10 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0] :: 10 Word.word)))) then - (let (op1 :: 3 bits) = ((slice0 instr (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in - (let (CRn :: 4 bits) = ((slice0 instr (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in - (let (CRm :: 4 bits) = ((slice0 instr (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in - (let (op2 :: 3 bits) = ((slice0 instr (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (if (((((slice instr (( 22 :: int)::ii) (( 10 :: int)::ii) :: 10 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B1,B0,B1,B0,B0] :: 10 Word.word)))) then + (let (op1 :: 3 bits) = ((slice instr (( 16 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let (CRn :: 4 bits) = ((slice instr (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + (let (CRm :: 4 bits) = ((slice instr (( 8 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + (let (op2 :: 3 bits) = ((slice instr (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in ((((((((((op1 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((CRn = (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word))))))) \<and> (((CRm = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word))))))) \<and> ((((((op2 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<or> (((op2 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))))))))))) else False) in return w__0)))))))" @@ -14692,13 +14800,13 @@ definition AArch64_ReportException :: " ExceptionRecord \<Rightarrow>(2)Word.wo (read_reg HPFAR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . write_reg HPFAR_EL2_ref - ((set_slice0 (( 64 :: int)::ii) (( 40 :: int)::ii) w__1 (( 4 :: int)::ii) - ((slice0(ExceptionRecord_ipaddress exception) (( 12 :: int)::ii) (( 40 :: int)::ii) :: 40 Word.word)) + ((set_slice (( 64 :: int)::ii) (( 40 :: int)::ii) w__1 (( 4 :: int)::ii) + ((slice(ExceptionRecord_ipaddress exception) (( 12 :: int)::ii) (( 40 :: int)::ii) :: 40 Word.word)) :: 64 Word.word))) else (read_reg HPFAR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . (undefined_bitvector (( 40 :: int)::ii) :: ( 40 Word.word) M) \<bind> (\<lambda> (w__3 :: 40 Word.word) . - write_reg HPFAR_EL2_ref ((set_slice0 (( 64 :: int)::ii) (( 40 :: int)::ii) w__2 (( 4 :: int)::ii) w__3 :: 64 Word.word)))) + write_reg HPFAR_EL2_ref ((set_slice (( 64 :: int)::ii) (( 40 :: int)::ii) w__2 (( 4 :: int)::ii) w__3 :: 64 Word.word)))) else return () )))))))))))" @@ -14777,59 +14885,65 @@ definition AArch64_ESBOperation :: " unit \<Rightarrow>((register_value),(unit) definition AArch64_CheckAndUpdateDescriptor :: " DescriptorUpdate \<Rightarrow> FaultRecord \<Rightarrow> bool \<Rightarrow>(64)Word.word \<Rightarrow> AccType \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(FaultRecord),(exception))monad " where " AArch64_CheckAndUpdateDescriptor result fault secondstage vaddress acctype iswrite s2fs1walk hwupdatewalk__arg = ( catch_early_return - ((let hwupdatewalk = hwupdatewalk__arg in - liftR (undefined_bool () ) \<bind> (\<lambda> (hw_update_AF :: bool) . - (let (hw_update_AF :: bool) = - (if(DescriptorUpdate_AF result) then - if ((((FaultRecord_typ fault) = Fault_None))) then True - else if (((((ConstrainUnpredictable Unpredictable_AFUPDATE)) = Constraint_TRUE))) then True - else False - else hw_update_AF) in - liftR (undefined_bool () ) \<bind> (\<lambda> (hw_update_AP :: bool) . - liftR (undefined_bool () ) \<bind> (\<lambda> (write_perm_req :: bool) . - (let (hw_update_AP :: bool) = - (if ((((DescriptorUpdate_AP result) \<and> ((((FaultRecord_typ fault) = Fault_None)))))) then - (let (write_perm_req :: bool) = - ((((iswrite \<or> ((((((acctype = AccType_ATOMICRW))) \<or> (((acctype = AccType_ORDEREDRW))))))))) \<and> ((\<not> s2fs1walk))) in - ((((write_perm_req \<and> ((\<not> ((((((acctype = AccType_AT))) \<or> (((acctype = AccType_DC))))))))))) \<or> hwupdatewalk)) - else False) in - liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (desc :: 64 bits) . - liftR (undefined_AccessDescriptor () ) \<bind> (\<lambda> (accdesc :: AccessDescriptor) . - liftR (undefined_AddressDescriptor () ) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . - (if (((hw_update_AF \<or> hw_update_AP))) then - or_boolM (return secondstage) - (liftR (HasS2Translation () ) \<bind> (\<lambda> (w__0 :: bool) . return ((\<not> w__0)))) \<bind> (\<lambda> (w__1 :: - bool) . - (if w__1 then - (let (descaddr2 :: AddressDescriptor) = ((DescriptorUpdate_descaddr result)) in - return descaddr2) - else - (let hwupdatewalk = True in - liftR (AArch64_SecondStageWalk(DescriptorUpdate_descaddr result) vaddress acctype iswrite - (( 8 :: int)::ii) hwupdatewalk) \<bind> (\<lambda> (w__2 :: AddressDescriptor) . - (let descaddr2 = w__2 in - (if ((IsFault descaddr2)) then - (early_return(AddressDescriptor_fault descaddr2) :: (unit, FaultRecord) MR) - else return () ) \<then> - return descaddr2)))) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . - liftR (CreateAccessDescriptor AccType_ATOMICRW) \<bind> (\<lambda> (w__3 :: AccessDescriptor) . - (let accdesc = w__3 in - liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64 bits) . - (let desc = w__4 in - (let (desc :: 64 bits) = - (if hw_update_AF then - (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 10 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word) - else desc) in - (let (desc :: 64 bits) = - (if hw_update_AP then - (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) - (if secondstage then (vec_of_bits [B1] :: 1 Word.word) - else (vec_of_bits [B0] :: 1 Word.word)) - :: 64 Word.word) - else desc) in - liftR (aset__Mem descaddr2 (( 8 :: int)::ii) accdesc desc))))))))) - else return () ) \<then> - return fault)))))))))))" + (liftR ((aget_SCTLR__1 () :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + (let reversedescriptors = (((access_vec_dec w__0 (( 25 :: int)::ii))) = B1) in + (let hwupdatewalk = hwupdatewalk__arg in + liftR (undefined_bool () ) \<bind> (\<lambda> (hw_update_AF :: bool) . + (let (hw_update_AF :: bool) = + (if(DescriptorUpdate_AF result) then + if ((((FaultRecord_typ fault) = Fault_None))) then True + else if (((((ConstrainUnpredictable Unpredictable_AFUPDATE)) = Constraint_TRUE))) then True + else False + else False) in + liftR (undefined_bool () ) \<bind> (\<lambda> (hw_update_AP :: bool) . + liftR (undefined_bool () ) \<bind> (\<lambda> (write_perm_req :: bool) . + (let (hw_update_AP :: bool) = + (if ((((DescriptorUpdate_AP result) \<and> ((((FaultRecord_typ fault) = Fault_None)))))) then + (let (write_perm_req :: bool) = + ((((iswrite \<or> ((((((acctype = AccType_ATOMICRW))) \<or> (((acctype = AccType_ORDEREDRW))))))))) \<and> ((\<not> s2fs1walk))) in + ((((write_perm_req \<and> ((\<not> ((((((acctype = AccType_AT))) \<or> (((acctype = AccType_DC))))))))))) \<or> hwupdatewalk)) + else False) in + liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (desc :: 64 bits) . + liftR (undefined_AccessDescriptor () ) \<bind> (\<lambda> (accdesc :: AccessDescriptor) . + liftR (undefined_AddressDescriptor () ) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . + (if (((hw_update_AF \<or> hw_update_AP))) then + or_boolM (return secondstage) + (liftR (HasS2Translation () ) \<bind> (\<lambda> (w__1 :: bool) . return ((\<not> w__1)))) \<bind> (\<lambda> (w__2 :: + bool) . + (if w__2 then + (let (descaddr2 :: AddressDescriptor) = ((DescriptorUpdate_descaddr result)) in + return descaddr2) + else + (let hwupdatewalk = True in + liftR (AArch64_SecondStageWalk(DescriptorUpdate_descaddr result) vaddress acctype iswrite + (( 8 :: int)::ii) hwupdatewalk) \<bind> (\<lambda> (w__3 :: AddressDescriptor) . + (let descaddr2 = w__3 in + (if ((IsFault descaddr2)) then + (early_return(AddressDescriptor_fault descaddr2) :: (unit, FaultRecord) MR) + else return () ) \<then> + return descaddr2)))) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . + liftR (CreateAccessDescriptor AccType_ATOMICRW) \<bind> (\<lambda> (w__4 :: AccessDescriptor) . + (let accdesc = w__4 in + liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__5 :: 64 bits) . + (let desc = w__5 in + (if reversedescriptors then liftR ((BigEndianReverse desc :: ( 64 Word.word) M)) + else return desc) \<bind> (\<lambda> (desc :: 64 bits) . + (let (desc :: 64 bits) = + (if hw_update_AF then + (set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 10 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word) + else desc) in + (let (desc :: 64 bits) = + (if hw_update_AP then + (set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) desc (( 7 :: int)::ii) + (if secondstage then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word) + else desc) in + (if reversedescriptors then liftR ((BigEndianReverse desc :: ( 64 Word.word) M)) + else return desc) \<bind> (\<lambda> (desc :: 64 bits) . + liftR (aset__Mem descaddr2 (( 8 :: int)::ii) accdesc desc))))))))))) + else return () ) \<then> + return fault)))))))))))))" (*val AArch64_BreakpointValueMatch : ii -> mword ty64 -> bool -> bool*) @@ -14876,9 +14990,9 @@ definition AArch64_StateMatch :: "(2)Word.word \<Rightarrow>(1)Word.word \<Righ (let tmp_50 = tup__1 in (let (tmp_60 :: 5 bits) = tmp_50 in (let HMC = ((vec_of_bits [access_vec_dec tmp_60 (( 4 :: int)::ii)] :: 1 Word.word)) in - (let (tmp_70 :: 4 bits) = ((slice0 tmp_60 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in - (let SSC = ((slice0 tmp_70 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in - (let PxC = ((slice0 tmp_70 (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let (tmp_70 :: 4 bits) = ((slice tmp_60 (( 0 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + (let SSC = ((slice tmp_70 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let PxC = ((slice tmp_70 (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in (liftR (assert_exp ((((((c = Constraint_DISABLED))) \<or> (((c = Constraint_UNKNOWN)))))) (''((c == Constraint_DISABLED) || (c == Constraint_UNKNOWN))'')) \<then> (if (((c = Constraint_DISABLED))) then (early_return False :: (unit, bool) MR) else return () )) \<then> @@ -14896,9 +15010,14 @@ definition AArch64_StateMatch :: "(2)Word.word \<Rightarrow>(1)Word.word \<Righ (if (((((\<not> ispriv)) \<and> ((\<not> isbreakpnt))))) then return EL0_match else liftR (read_reg PSTATE_ref) \<bind> (\<lambda> (w__1 :: ProcState) . - (let (priv_match :: bool) = - ((case (ProcState_EL w__1) of EL31 => EL3_match )) in - return priv_match))) \<bind> (\<lambda> (priv_match :: bool) . + (let p__294 = ((ProcState_EL w__1)) in + (let pat0 = p__294 in + (let (priv_match :: bool) = + (if (((pat0 = EL3))) then EL3_match + else if (((pat0 = EL2))) then EL2_match + else if (((pat0 = EL1))) then EL1_match + else EL0_match) in + return priv_match))))) \<bind> (\<lambda> (priv_match :: bool) . liftR (undefined_bool () ) \<bind> (\<lambda> (security_state_match :: bool) . (let b__0 = SSC in (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return True @@ -14916,10 +15035,10 @@ definition AArch64_StateMatch :: "(2)Word.word \<Rightarrow>(1)Word.word \<Righ liftR ((read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64 bits) . liftR ((read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__5 :: 64 bits) . (let first_ctx_cmp = - (((Word.uint ((slice0 w__4 (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))) - - ((Word.uint ((slice0 w__5 (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word))))) in + (((Word.uint ((slice w__4 (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))) - + ((Word.uint ((slice w__5 (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word))))) in liftR ((read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__6 :: 64 bits) . - (let last_ctx_cmp = (Word.uint ((slice0 w__6 (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word))) in + (let last_ctx_cmp = (Word.uint ((slice w__6 (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word))) in if (((((((ex_int lbn)) < ((ex_int first_ctx_cmp)))) \<or> ((((ex_int lbn)) > ((ex_int last_ctx_cmp))))))) then liftR (ConstrainUnpredictableInteger first_ctx_cmp last_ctx_cmp Unpredictable_BPNOTCTXCMP) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in (let c = tup__0 in @@ -14953,7 +15072,7 @@ definition AArch64_WatchpointMatch :: " int \<Rightarrow>(64)Word.word \<Righta ELUsingAArch32 w__0 \<bind> (\<lambda> (w__1 :: bool) . (assert_exp ((\<not> w__1)) (''!(ELUsingAArch32(S1TranslationRegime()))'') \<then> (read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__2 :: 64 bits) . - (assert_exp ((n \<le> ((Word.uint ((slice0 w__2 (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))) (''(n <= UInt((ID_AA64DFR0_EL1).WRPs))'') \<then> + (assert_exp ((n \<le> ((Word.uint ((slice w__2 (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))) (''(n <= UInt((ID_AA64DFR0_EL1).WRPs))'') \<then> read_reg DBGWCR_EL1_ref) \<bind> (\<lambda> (w__3 :: ( 32 bits) list) . (let (enabled :: bool) = ((vec_of_bits [access_vec_dec ((access_list_dec w__3 n :: 32 Word.word)) (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -14965,15 +15084,15 @@ definition AArch64_WatchpointMatch :: " int \<Rightarrow>(64)Word.word \<Righta read_reg DBGWCR_EL1_ref \<bind> (\<lambda> (w__6 :: ( 32 bits) list) . read_reg DBGWCR_EL1_ref \<bind> (\<lambda> (w__7 :: ( 32 bits) list) . read_reg DBGWCR_EL1_ref \<bind> (\<lambda> (w__8 :: ( 32 bits) list) . - AArch64_StateMatch ((slice0 ((access_list_dec w__5 n :: 32 Word.word)) (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + AArch64_StateMatch ((slice ((access_list_dec w__5 n :: 32 Word.word)) (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) (vec_of_bits [access_vec_dec ((access_list_dec w__6 n :: 32 Word.word)) (( 13 :: int)::ii)] :: 1 Word.word) - ((slice0 ((access_list_dec w__7 n :: 32 Word.word)) (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) linked - ((slice0 ((access_list_dec w__8 n :: 32 Word.word)) (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) isbreakpnt + ((slice ((access_list_dec w__7 n :: 32 Word.word)) (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) linked + ((slice ((access_list_dec w__8 n :: 32 Word.word)) (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) isbreakpnt ispriv \<bind> (\<lambda> (state_match :: bool) . read_reg DBGWCR_EL1_ref \<bind> (\<lambda> (w__9 :: ( 32 bits) list) . (let (ls_match :: bool) = ((vec_of_bits [access_vec_dec - ((slice0 ((access_list_dec w__9 n :: 32 Word.word)) (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + ((slice ((access_list_dec w__9 n :: 32 Word.word)) (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) (if iswrite then (( 1 :: int)::ii) else (( 0 :: int)::ii))] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -14994,7 +15113,7 @@ definition AArch64_BreakpointMatch :: " int \<Rightarrow>(64)Word.word \<Righta ELUsingAArch32 w__0 \<bind> (\<lambda> (w__1 :: bool) . (assert_exp ((\<not> w__1)) (''!(ELUsingAArch32(S1TranslationRegime()))'') \<then> (read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__2 :: 64 bits) . - (assert_exp ((n \<le> ((Word.uint ((slice0 w__2 (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))) (''(n <= UInt((ID_AA64DFR0_EL1).BRPs))'') \<then> + (assert_exp ((n \<le> ((Word.uint ((slice w__2 (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))))) (''(n <= UInt((ID_AA64DFR0_EL1).BRPs))'') \<then> read_reg DBGBCR_EL1_ref) \<bind> (\<lambda> (w__3 :: ( 32 bits) list) . (let (enabled :: bool) = ((vec_of_bits [access_vec_dec ((access_list_dec w__3 n :: 32 Word.word)) (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -15002,7 +15121,7 @@ definition AArch64_BreakpointMatch :: " int \<Rightarrow>(64)Word.word \<Righta (let (ispriv :: bool) = ((ProcState_EL w__4) \<noteq> EL0) in read_reg DBGBCR_EL1_ref \<bind> (\<lambda> (w__5 :: ( 32 bits) list) . (let (linked :: bool) = - (((and_vec ((slice0 ((access_list_dec w__5 n :: 32 Word.word)) (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) + (((and_vec ((slice ((access_list_dec w__5 n :: 32 Word.word)) (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word) :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word)) in (let (isbreakpnt :: bool) = True in @@ -15011,10 +15130,10 @@ definition AArch64_BreakpointMatch :: " int \<Rightarrow>(64)Word.word \<Righta read_reg DBGBCR_EL1_ref \<bind> (\<lambda> (w__7 :: ( 32 bits) list) . read_reg DBGBCR_EL1_ref \<bind> (\<lambda> (w__8 :: ( 32 bits) list) . read_reg DBGBCR_EL1_ref \<bind> (\<lambda> (w__9 :: ( 32 bits) list) . - AArch64_StateMatch ((slice0 ((access_list_dec w__6 n :: 32 Word.word)) (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) + AArch64_StateMatch ((slice ((access_list_dec w__6 n :: 32 Word.word)) (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) (vec_of_bits [access_vec_dec ((access_list_dec w__7 n :: 32 Word.word)) (( 13 :: int)::ii)] :: 1 Word.word) - ((slice0 ((access_list_dec w__8 n :: 32 Word.word)) (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) linked - ((slice0 ((access_list_dec w__9 n :: 32 Word.word)) (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) isbreakpnt + ((slice ((access_list_dec w__8 n :: 32 Word.word)) (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) linked + ((slice ((access_list_dec w__9 n :: 32 Word.word)) (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) isbreakpnt ispriv \<bind> (\<lambda> (state_match :: bool) . (let (value_match_name :: bool) = (AArch64_BreakpointValueMatch n vaddress linked_to) in undefined_bool () \<bind> (\<lambda> (match_i :: bool) . @@ -15028,7 +15147,7 @@ definition AArch64_BreakpointMatch :: " int \<Rightarrow>(64)Word.word \<Righta and_boolM (return ((((vec_of_bits [access_vec_dec vaddress (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word))))) (read_reg DBGBCR_EL1_ref \<bind> (\<lambda> (w__11 :: ( 32 bits) list) . - return (((((slice0 ((access_list_dec w__11 n :: 32 Word.word)) (( 5 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . + return (((((slice ((access_list_dec w__11 n :: 32 Word.word)) (( 5 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . (if w__12 then if value_match_name then ConstrainUnpredictableBool Unpredictable_BPMATCHHALF else return value_match_name @@ -15051,12 +15170,13 @@ definition AArch64_CheckBreakpoint :: "(64)Word.word \<Rightarrow> int \<Righta ((let (val_match :: bool) = False in undefined_bool () \<bind> (\<lambda> (match_i :: bool) . (read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . - (foreachM (index_list (( 0 :: int)::ii) ((Word.uint ((slice0 w__5 (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))) (( 1 :: int)::ii)) val_match - (\<lambda> i val_match . + (foreachM (index_list (( 0 :: int)::ii) ((Word.uint ((slice w__5 (( 12 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))) (( 1 :: int)::ii)) (match_i, + val_match) + (\<lambda> i varstup . (let (match_i, val_match) = varstup in AArch64_BreakpointMatch i vaddress size1 \<bind> (\<lambda> (w__6 :: bool) . (let (match_i :: bool) = w__6 in (let (val_match :: bool) = (val_match \<or> match_i) in - return val_match))))) \<bind> (\<lambda> (val_match :: bool) . + return (match_i, val_match))))))) \<bind> (\<lambda> varstup . (let ((match_i :: bool), (val_match :: bool)) = varstup in undefined_bool () \<bind> (\<lambda> (iswrite :: bool) . undefined_AccType () \<bind> (\<lambda> (acctype :: AccType) . (undefined_bitvector (( 6 :: int)::ii) :: ( 6 Word.word) M) \<bind> (\<lambda> (reason :: 6 bits) . @@ -15074,7 +15194,7 @@ definition AArch64_CheckBreakpoint :: "(64)Word.word \<Rightarrow> int \<Righta (let acctype = AccType_IFETCH in (let iswrite = False in AArch64_DebugFault acctype iswrite)) - else AArch64_NoFault () ))))))))))))))" + else AArch64_NoFault () )))))))))))))))" (*val AArch64_BranchAddr : mword ty64 -> M (mword ty64)*) @@ -15119,7 +15239,7 @@ definition BranchTo :: "('N::len)Word.word \<Rightarrow> BranchType \<Rightarro and_boolM (return (((((int (size target))) = (( 64 :: int)::ii))))) (UsingAArch32 () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2)))) \<bind> (\<lambda> (w__3 :: bool) . (assert_exp w__3 (''((N == 64) && !(UsingAArch32()))'') \<then> - (AArch64_BranchAddr ((slice0 target (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64 + (AArch64_BranchAddr ((slice target (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64 bits) . write_reg PC_ref w__4)))))" @@ -15475,7 +15595,7 @@ definition AArch64_TakeException :: "(2)Word.word \<Rightarrow> ExceptionRecord else return () ) \<then> (aget_VBAR__1 () :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__37 :: 64 Word.word) . (BranchTo - ((concat_vec ((slice0 w__37 (( 11 :: int)::ii) (( 53 :: int)::ii) :: 53 Word.word)) + ((concat_vec ((slice w__37 (( 11 :: int)::ii) (( 53 :: int)::ii) :: 53 Word.word)) ((GetSlice_int ((make_the_value (( 11 :: int)::ii) :: 11 itself)) vect_offset (( 0 :: int)::ii) :: 11 Word.word)) :: 64 Word.word)) BranchType_EXCEPTION \<then> undefined_bool () ) \<bind> (\<lambda> (iesb_req :: bool) . @@ -15522,7 +15642,7 @@ definition Strip :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>((register_v ((replicate_bits (vec_of_bits [access_vec_dec A (( 55 :: int)::ii)] :: 1 Word.word) (( 64 :: int)::ii) :: 64 Word.word)) in (let (original_ptr :: 64 bits) = (if tbi then - (concat_vec ((slice0 A (( 56 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) + (concat_vec ((slice A (( 56 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) ((slice_slice_concat (( 56 :: int)::ii) extfield (( 0 :: int)::ii) ((((- bottom_PAC_bit)) + (( 56 :: int)::ii))) A (( 0 :: int)::ii) bottom_PAC_bit :: 56 Word.word)) @@ -15531,45 +15651,53 @@ definition Strip :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>((register_v (slice_slice_concat (( 64 :: int)::ii) extfield (( 0 :: int)::ii) ((((- bottom_PAC_bit)) + (( 64 :: int)::ii))) A (( 0 :: int)::ii) bottom_PAC_bit :: 64 Word.word)) in - read_reg PSTATE_ref \<bind> (\<lambda> (w__1 :: ProcState) . - (case (ProcState_EL w__1) of - EL01 => - or_boolM - (or_boolM (return ((\<not> ((HaveEL EL2))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__2 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__2 (( 27 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word))))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__4 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__4 (( 34 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (IsEL1Regime :: bool) . - and_boolM - (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) - (IsSecure () \<bind> - (\<lambda> (w__5 :: bool) . return ((\<not> w__5))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__7 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__7 (( 41 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__8 :: bool) . - (let TrapEL2 = w__8 in - and_boolM (return ((HaveEL EL3))) - ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__9 :: 32 bits) . - return - ((((vec_of_bits [access_vec_dec w__9 (( 17 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__10 :: bool) . - (let (TrapEL3 :: bool) = w__10 in return (TrapEL2, TrapEL3)))))) - ) \<bind> (\<lambda> varstup . (let ((TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + read_reg PSTATE_ref \<bind> (\<lambda> (w__1 :: ProcState) . + (let p__293 = ((ProcState_EL w__1)) in + (let pat0 = p__293 in + (if (((pat0 = EL0))) then + or_boolM + (or_boolM (return ((\<not> ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__2 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__4 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . + and_boolM + (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) + (IsSecure () \<bind> (\<lambda> (w__5 :: bool) . return ((\<not> w__5))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__7 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__8 :: bool) . + (let TrapEL2 = w__8 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__9 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__10 :: bool) . + (let (TrapEL3 :: bool) = w__10 in + return (TrapEL2, TrapEL3)))))) + else if (((pat0 = EL1))) then + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \<bind> (\<lambda> (w__11 :: bool) . return ((\<not> w__11))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__13 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . + (let TrapEL2 = w__14 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__15 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__16 :: bool) . + (let (TrapEL3 :: bool) = w__16 in + return (TrapEL2, TrapEL3))))) + else if (((pat0 = EL2))) then + (let TrapEL2 = False in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__17 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__17 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__18 :: bool) . + (let (TrapEL3 :: bool) = w__18 in + return (TrapEL2, TrapEL3)))) + else + (let (TrapEL2 :: bool) = False in + (let (TrapEL3 :: bool) = False in + return (TrapEL2, TrapEL3)))) \<bind> (\<lambda> varstup . (let ((TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) - else return original_ptr))))))))))))))" + else return original_ptr))))))))))))))))" (*val aarch64_integer_pac_strip_dp_1src : ii -> bool -> M unit*) @@ -15602,64 +15730,71 @@ definition AuthIB :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((r (read_reg APIBKeyHi_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (read_reg APIBKeyLo_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . (let (APIBKey_EL1 :: 128 bits) = - ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: 128 Word.word)) in - read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . - (case (ProcState_EL w__2) of - EL01 => - or_boolM - (or_boolM (return ((\<not> ((HaveEL EL2))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__3 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word))))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__5 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (IsEL1Regime :: bool) . - ( - if IsEL1Regime then - (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__6 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__6 (( 30 :: int):: ii)] :: 1 Word.word)) - else - (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__7 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__7 (( 30 :: int):: ii)] :: 1 Word.word))) - \<bind> - (\<lambda> (w__8 :: 1 Word.word) . - (let Enable = w__8 in - and_boolM - (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) - (IsSecure () \<bind> - (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__11 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__12 :: bool) . - (let TrapEL2 = w__12 in - and_boolM (return ((HaveEL EL3))) - ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__13 :: 32 bits) . - return - ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__14 :: bool) . - (let (TrapEL3 :: bool) = w__14 in - return (Enable, TrapEL2, TrapEL3)))))))) - ) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . + (let p__292 = ((ProcState_EL w__2)) in + (let pat0 = p__292 in + (if (((pat0 = EL0))) then + or_boolM + (or_boolM (return ((\<not> ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . + (if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__6 (( 30 :: int)::ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__7 (( 30 :: int)::ii)] :: 1 Word.word))) \<bind> (\<lambda> (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) + (IsSecure () \<bind> (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + else if (((pat0 = EL1))) then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 30 :: int)::ii)] :: 1 Word.word)) in + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \<bind> (\<lambda> (w__16 :: bool) . return ((\<not> w__16))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . + (let TrapEL2 = w__19 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . + (let (TrapEL3 :: bool) = w__21 in + return (Enable, TrapEL2, TrapEL3))))))) + else if (((pat0 = EL2))) then + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 30 :: int)::ii)] :: 1 Word.word)) in + (let TrapEL2 = False in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . + (let (TrapEL3 :: bool) = w__24 in + return (Enable, TrapEL2, TrapEL3)))))) + else + (read_reg SCTLR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . + (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (TrapEL2 :: bool) = False in + (let (TrapEL3 :: bool) = False in + return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: + bool), (TrapEL3 :: bool)) = varstup in if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) - else (Auth X Y APIBKey_EL1 False (vec_of_bits [B1] :: 1 Word.word) :: ( 64 Word.word) M)))))))))))" + else (Auth X Y APIBKey_EL1 False (vec_of_bits [B1] :: 1 Word.word) :: ( 64 Word.word) M)))))))))))))" (*val aarch64_integer_pac_autib_dp_1src : ii -> ii -> bool -> M unit*) @@ -15729,64 +15864,71 @@ definition AuthIA :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((r (read_reg APIAKeyHi_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (read_reg APIAKeyLo_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . (let (APIAKey_EL1 :: 128 bits) = - ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: 128 Word.word)) in - read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . - (case (ProcState_EL w__2) of - EL01 => - or_boolM - (or_boolM (return ((\<not> ((HaveEL EL2))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__3 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word))))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__5 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (IsEL1Regime :: bool) . - ( - if IsEL1Regime then - (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__6 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__6 (( 31 :: int):: ii)] :: 1 Word.word)) - else - (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__7 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__7 (( 31 :: int):: ii)] :: 1 Word.word))) - \<bind> - (\<lambda> (w__8 :: 1 Word.word) . - (let Enable = w__8 in - and_boolM - (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) - (IsSecure () \<bind> - (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__11 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__12 :: bool) . - (let TrapEL2 = w__12 in - and_boolM (return ((HaveEL EL3))) - ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__13 :: 32 bits) . - return - ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__14 :: bool) . - (let (TrapEL3 :: bool) = w__14 in - return (Enable, TrapEL2, TrapEL3)))))))) - ) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . + (let p__291 = ((ProcState_EL w__2)) in + (let pat0 = p__291 in + (if (((pat0 = EL0))) then + or_boolM + (or_boolM (return ((\<not> ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . + (if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__6 (( 31 :: int)::ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__7 (( 31 :: int)::ii)] :: 1 Word.word))) \<bind> (\<lambda> (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) + (IsSecure () \<bind> (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + else if (((pat0 = EL1))) then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 31 :: int)::ii)] :: 1 Word.word)) in + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \<bind> (\<lambda> (w__16 :: bool) . return ((\<not> w__16))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . + (let TrapEL2 = w__19 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . + (let (TrapEL3 :: bool) = w__21 in + return (Enable, TrapEL2, TrapEL3))))))) + else if (((pat0 = EL2))) then + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 31 :: int)::ii)] :: 1 Word.word)) in + (let TrapEL2 = False in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . + (let (TrapEL3 :: bool) = w__24 in + return (Enable, TrapEL2, TrapEL3)))))) + else + (read_reg SCTLR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . + (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (TrapEL2 :: bool) = False in + (let (TrapEL3 :: bool) = False in + return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: + bool), (TrapEL3 :: bool)) = varstup in if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) - else (Auth X Y APIAKey_EL1 False (vec_of_bits [B0] :: 1 Word.word) :: ( 64 Word.word) M)))))))))))" + else (Auth X Y APIAKey_EL1 False (vec_of_bits [B0] :: 1 Word.word) :: ( 64 Word.word) M)))))))))))))" (*val aarch64_integer_pac_autia_dp_1src : ii -> ii -> bool -> M unit*) @@ -15876,64 +16018,71 @@ definition AuthDB :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((r (read_reg APDBKeyHi_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (read_reg APDBKeyLo_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . (let (APDBKey_EL1 :: 128 bits) = - ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: 128 Word.word)) in - read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . - (case (ProcState_EL w__2) of - EL01 => - or_boolM - (or_boolM (return ((\<not> ((HaveEL EL2))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__3 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word))))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__5 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (IsEL1Regime :: bool) . - ( - if IsEL1Regime then - (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__6 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__6 (( 13 :: int):: ii)] :: 1 Word.word)) - else - (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__7 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__7 (( 13 :: int):: ii)] :: 1 Word.word))) - \<bind> - (\<lambda> (w__8 :: 1 Word.word) . - (let Enable = w__8 in - and_boolM - (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) - (IsSecure () \<bind> - (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__11 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__12 :: bool) . - (let TrapEL2 = w__12 in - and_boolM (return ((HaveEL EL3))) - ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__13 :: 32 bits) . - return - ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__14 :: bool) . - (let (TrapEL3 :: bool) = w__14 in - return (Enable, TrapEL2, TrapEL3)))))))) - ) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . + (let p__290 = ((ProcState_EL w__2)) in + (let pat0 = p__290 in + (if (((pat0 = EL0))) then + or_boolM + (or_boolM (return ((\<not> ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . + (if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__6 (( 13 :: int)::ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__7 (( 13 :: int)::ii)] :: 1 Word.word))) \<bind> (\<lambda> (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) + (IsSecure () \<bind> (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + else if (((pat0 = EL1))) then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 13 :: int)::ii)] :: 1 Word.word)) in + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \<bind> (\<lambda> (w__16 :: bool) . return ((\<not> w__16))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . + (let TrapEL2 = w__19 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . + (let (TrapEL3 :: bool) = w__21 in + return (Enable, TrapEL2, TrapEL3))))))) + else if (((pat0 = EL2))) then + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 13 :: int)::ii)] :: 1 Word.word)) in + (let TrapEL2 = False in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . + (let (TrapEL3 :: bool) = w__24 in + return (Enable, TrapEL2, TrapEL3)))))) + else + (read_reg SCTLR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . + (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 13 :: int)::ii)] :: 1 Word.word)) in + (let (TrapEL2 :: bool) = False in + (let (TrapEL3 :: bool) = False in + return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: + bool), (TrapEL3 :: bool)) = varstup in if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) - else (Auth X Y APDBKey_EL1 True (vec_of_bits [B1] :: 1 Word.word) :: ( 64 Word.word) M)))))))))))" + else (Auth X Y APDBKey_EL1 True (vec_of_bits [B1] :: 1 Word.word) :: ( 64 Word.word) M)))))))))))))" (*val aarch64_integer_pac_autdb_dp_1src : ii -> ii -> bool -> M unit*) @@ -15960,64 +16109,71 @@ definition AuthDA :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((r (read_reg APDAKeyHi_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (read_reg APDAKeyLo_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . (let (APDAKey_EL1 :: 128 bits) = - ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: 128 Word.word)) in - read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . - (case (ProcState_EL w__2) of - EL01 => - or_boolM - (or_boolM (return ((\<not> ((HaveEL EL2))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__3 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word))))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__5 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (IsEL1Regime :: bool) . - ( - if IsEL1Regime then - (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__6 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__6 (( 27 :: int):: ii)] :: 1 Word.word)) - else - (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__7 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__7 (( 27 :: int):: ii)] :: 1 Word.word))) - \<bind> - (\<lambda> (w__8 :: 1 Word.word) . - (let Enable = w__8 in - and_boolM - (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) - (IsSecure () \<bind> - (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__11 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__12 :: bool) . - (let TrapEL2 = w__12 in - and_boolM (return ((HaveEL EL3))) - ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__13 :: 32 bits) . - return - ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__14 :: bool) . - (let (TrapEL3 :: bool) = w__14 in - return (Enable, TrapEL2, TrapEL3)))))))) - ) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . + (let p__289 = ((ProcState_EL w__2)) in + (let pat0 = p__289 in + (if (((pat0 = EL0))) then + or_boolM + (or_boolM (return ((\<not> ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . + (if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__6 (( 27 :: int)::ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__7 (( 27 :: int)::ii)] :: 1 Word.word))) \<bind> (\<lambda> (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) + (IsSecure () \<bind> (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + else if (((pat0 = EL1))) then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 27 :: int)::ii)] :: 1 Word.word)) in + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \<bind> (\<lambda> (w__16 :: bool) . return ((\<not> w__16))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . + (let TrapEL2 = w__19 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . + (let (TrapEL3 :: bool) = w__21 in + return (Enable, TrapEL2, TrapEL3))))))) + else if (((pat0 = EL2))) then + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 27 :: int)::ii)] :: 1 Word.word)) in + (let TrapEL2 = False in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . + (let (TrapEL3 :: bool) = w__24 in + return (Enable, TrapEL2, TrapEL3)))))) + else + (read_reg SCTLR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . + (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 27 :: int)::ii)] :: 1 Word.word)) in + (let (TrapEL2 :: bool) = False in + (let (TrapEL3 :: bool) = False in + return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: + bool), (TrapEL3 :: bool)) = varstup in if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) - else (Auth X Y APDAKey_EL1 True (vec_of_bits [B0] :: 1 Word.word) :: ( 64 Word.word) M)))))))))))" + else (Auth X Y APDAKey_EL1 True (vec_of_bits [B0] :: 1 Word.word) :: ( 64 Word.word) M)))))))))))))" (*val aarch64_integer_pac_autda_dp_1src : ii -> ii -> bool -> M unit*) @@ -16044,64 +16200,71 @@ definition AddPACIB :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>( (read_reg APIBKeyHi_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (read_reg APIBKeyLo_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . (let (APIBKey_EL1 :: 128 bits) = - ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: 128 Word.word)) in - read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . - (case (ProcState_EL w__2) of - EL01 => - or_boolM - (or_boolM (return ((\<not> ((HaveEL EL2))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__3 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word))))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__5 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (IsEL1Regime :: bool) . - ( - if IsEL1Regime then - (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__6 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__6 (( 30 :: int):: ii)] :: 1 Word.word)) - else - (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__7 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__7 (( 30 :: int):: ii)] :: 1 Word.word))) - \<bind> - (\<lambda> (w__8 :: 1 Word.word) . - (let Enable = w__8 in - and_boolM - (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) - (IsSecure () \<bind> - (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__11 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__12 :: bool) . - (let TrapEL2 = w__12 in - and_boolM (return ((HaveEL EL3))) - ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__13 :: 32 bits) . - return - ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__14 :: bool) . - (let (TrapEL3 :: bool) = w__14 in - return (Enable, TrapEL2, TrapEL3)))))))) - ) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . + (let p__288 = ((ProcState_EL w__2)) in + (let pat0 = p__288 in + (if (((pat0 = EL0))) then + or_boolM + (or_boolM (return ((\<not> ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . + (if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__6 (( 30 :: int)::ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__7 (( 30 :: int)::ii)] :: 1 Word.word))) \<bind> (\<lambda> (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) + (IsSecure () \<bind> (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + else if (((pat0 = EL1))) then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 30 :: int)::ii)] :: 1 Word.word)) in + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \<bind> (\<lambda> (w__16 :: bool) . return ((\<not> w__16))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . + (let TrapEL2 = w__19 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . + (let (TrapEL3 :: bool) = w__21 in + return (Enable, TrapEL2, TrapEL3))))))) + else if (((pat0 = EL2))) then + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 30 :: int)::ii)] :: 1 Word.word)) in + (let TrapEL2 = False in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . + (let (TrapEL3 :: bool) = w__24 in + return (Enable, TrapEL2, TrapEL3)))))) + else + (read_reg SCTLR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . + (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 30 :: int)::ii)] :: 1 Word.word)) in + (let (TrapEL2 :: bool) = False in + (let (TrapEL3 :: bool) = False in + return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: + bool), (TrapEL3 :: bool)) = varstup in if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) - else (AddPAC X Y APIBKey_EL1 False :: ( 64 Word.word) M)))))))))))" + else (AddPAC X Y APIBKey_EL1 False :: ( 64 Word.word) M)))))))))))))" (*val aarch64_integer_pac_pacib_dp_1src : ii -> ii -> bool -> M unit*) @@ -16171,64 +16334,71 @@ definition AddPACIA :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>( (read_reg APIAKeyHi_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (read_reg APIAKeyLo_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . (let (APIAKey_EL1 :: 128 bits) = - ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: 128 Word.word)) in - read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . - (case (ProcState_EL w__2) of - EL01 => - or_boolM - (or_boolM (return ((\<not> ((HaveEL EL2))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__3 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word))))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__5 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (IsEL1Regime :: bool) . - ( - if IsEL1Regime then - (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__6 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__6 (( 31 :: int):: ii)] :: 1 Word.word)) - else - (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__7 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__7 (( 31 :: int):: ii)] :: 1 Word.word))) - \<bind> - (\<lambda> (w__8 :: 1 Word.word) . - (let Enable = w__8 in - and_boolM - (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) - (IsSecure () \<bind> - (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__11 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__12 :: bool) . - (let TrapEL2 = w__12 in - and_boolM (return ((HaveEL EL3))) - ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__13 :: 32 bits) . - return - ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__14 :: bool) . - (let (TrapEL3 :: bool) = w__14 in - return (Enable, TrapEL2, TrapEL3)))))))) - ) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . + (let p__287 = ((ProcState_EL w__2)) in + (let pat0 = p__287 in + (if (((pat0 = EL0))) then + or_boolM + (or_boolM (return ((\<not> ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . + (if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__6 (( 31 :: int)::ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__7 (( 31 :: int)::ii)] :: 1 Word.word))) \<bind> (\<lambda> (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) + (IsSecure () \<bind> (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + else if (((pat0 = EL1))) then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 31 :: int)::ii)] :: 1 Word.word)) in + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \<bind> (\<lambda> (w__16 :: bool) . return ((\<not> w__16))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . + (let TrapEL2 = w__19 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . + (let (TrapEL3 :: bool) = w__21 in + return (Enable, TrapEL2, TrapEL3))))))) + else if (((pat0 = EL2))) then + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 31 :: int)::ii)] :: 1 Word.word)) in + (let TrapEL2 = False in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . + (let (TrapEL3 :: bool) = w__24 in + return (Enable, TrapEL2, TrapEL3)))))) + else + (read_reg SCTLR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . + (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 31 :: int)::ii)] :: 1 Word.word)) in + (let (TrapEL2 :: bool) = False in + (let (TrapEL3 :: bool) = False in + return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: + bool), (TrapEL3 :: bool)) = varstup in if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) - else (AddPAC X Y APIAKey_EL1 False :: ( 64 Word.word) M)))))))))))" + else (AddPAC X Y APIAKey_EL1 False :: ( 64 Word.word) M)))))))))))))" (*val aarch64_integer_pac_pacia_dp_1src : ii -> ii -> bool -> M unit*) @@ -16297,52 +16467,61 @@ definition AddPACGA :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>( (read_reg APGAKeyHi_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (read_reg APGAKeyLo_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . (let (APGAKey_EL1 :: 128 bits) = - ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: 128 Word.word)) in - read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . - (case (ProcState_EL w__2) of - EL01 => - or_boolM - (or_boolM (return ((\<not> ((HaveEL EL2))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__3 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word))))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__5 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (IsEL1Regime :: bool) . - and_boolM - (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) - (IsSecure () \<bind> - (\<lambda> (w__6 :: bool) . return ((\<not> w__6))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__8 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__8 (( 41 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__9 :: bool) . - (let TrapEL2 = w__9 in - (read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__10 :: 32 bits) . - (let (TrapEL3 :: bool) = - ((vec_of_bits [access_vec_dec w__10 (( 17 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)) in - return (TrapEL2, TrapEL3)))))) - ) \<bind> (\<lambda> varstup . (let ((TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . + (let p__286 = ((ProcState_EL w__2)) in + (let pat0 = p__286 in + (if (((pat0 = EL0))) then + or_boolM + (or_boolM (return ((\<not> ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . + and_boolM + (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) + (IsSecure () \<bind> (\<lambda> (w__6 :: bool) . return ((\<not> w__6))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__8 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__9 :: bool) . + (let TrapEL2 = w__9 in + (read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . + (let (TrapEL3 :: bool) = + ((vec_of_bits [access_vec_dec w__10 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)) in + return (TrapEL2, TrapEL3)))))) + else if (((pat0 = EL1))) then + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \<bind> (\<lambda> (w__11 :: bool) . return ((\<not> w__11))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__13 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . + (let TrapEL2 = w__14 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__15 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__16 :: bool) . + (let (TrapEL3 :: bool) = w__16 in + return (TrapEL2, TrapEL3))))) + else if (((pat0 = EL2))) then + (let TrapEL2 = False in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__17 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__17 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__18 :: bool) . + (let (TrapEL3 :: bool) = w__18 in + return (TrapEL2, TrapEL3)))) + else + (let (TrapEL2 :: bool) = False in + (let (TrapEL3 :: bool) = False in + return (TrapEL2, TrapEL3)))) \<bind> (\<lambda> varstup . (let ((TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) else - (ComputePAC X Y ((slice0 APGAKey_EL1 (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((slice0 APGAKey_EL1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + (ComputePAC X Y ((slice APGAKey_EL1 (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice APGAKey_EL1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__21 :: 64 Word.word) . - return ((concat_vec ((slice0 w__21 (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + return ((concat_vec ((slice w__21 (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) ((Zeros__0 ((make_the_value (( 32 :: int)::ii) :: 32 itself)) :: 32 Word.word)) - :: 64 Word.word))))))))))))" + :: 64 Word.word))))))))))))))" (*val aarch64_integer_pac_pacga_dp_2src : ii -> ii -> ii -> bool -> M unit*) @@ -16369,64 +16548,71 @@ definition AddPACDB :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>( (read_reg APDBKeyHi_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (read_reg APDBKeyLo_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . (let (APDBKey_EL1 :: 128 bits) = - ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: 128 Word.word)) in - read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . - (case (ProcState_EL w__2) of - EL01 => - or_boolM - (or_boolM (return ((\<not> ((HaveEL EL2))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__3 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word))))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__5 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (IsEL1Regime :: bool) . - ( - if IsEL1Regime then - (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__6 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__6 (( 13 :: int):: ii)] :: 1 Word.word)) - else - (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__7 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__7 (( 13 :: int):: ii)] :: 1 Word.word))) - \<bind> - (\<lambda> (w__8 :: 1 Word.word) . - (let Enable = w__8 in - and_boolM - (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) - (IsSecure () \<bind> - (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__11 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__12 :: bool) . - (let TrapEL2 = w__12 in - and_boolM (return ((HaveEL EL3))) - ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__13 :: 32 bits) . - return - ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__14 :: bool) . - (let (TrapEL3 :: bool) = w__14 in - return (Enable, TrapEL2, TrapEL3)))))))) - ) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . + (let p__285 = ((ProcState_EL w__2)) in + (let pat0 = p__285 in + (if (((pat0 = EL0))) then + or_boolM + (or_boolM (return ((\<not> ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . + (if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__6 (( 13 :: int)::ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__7 (( 13 :: int)::ii)] :: 1 Word.word))) \<bind> (\<lambda> (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) + (IsSecure () \<bind> (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + else if (((pat0 = EL1))) then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 13 :: int)::ii)] :: 1 Word.word)) in + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \<bind> (\<lambda> (w__16 :: bool) . return ((\<not> w__16))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . + (let TrapEL2 = w__19 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . + (let (TrapEL3 :: bool) = w__21 in + return (Enable, TrapEL2, TrapEL3))))))) + else if (((pat0 = EL2))) then + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 13 :: int)::ii)] :: 1 Word.word)) in + (let TrapEL2 = False in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . + (let (TrapEL3 :: bool) = w__24 in + return (Enable, TrapEL2, TrapEL3)))))) + else + (read_reg SCTLR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . + (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 13 :: int)::ii)] :: 1 Word.word)) in + (let (TrapEL2 :: bool) = False in + (let (TrapEL3 :: bool) = False in + return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: + bool), (TrapEL3 :: bool)) = varstup in if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) - else (AddPAC X Y APDBKey_EL1 True :: ( 64 Word.word) M)))))))))))" + else (AddPAC X Y APDBKey_EL1 True :: ( 64 Word.word) M)))))))))))))" (*val aarch64_integer_pac_pacdb_dp_1src : ii -> ii -> bool -> M unit*) @@ -16453,64 +16639,71 @@ definition AddPACDA :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>( (read_reg APDAKeyHi_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (read_reg APDAKeyLo_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . (let (APDAKey_EL1 :: 128 bits) = - ((concat_vec ((slice0 w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((slice0 w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((concat_vec ((slice w__0 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice w__1 (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: 128 Word.word)) in - read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . - (case (ProcState_EL w__2) of - EL01 => - or_boolM - (or_boolM (return ((\<not> ((HaveEL EL2))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__3 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word))))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__5 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (IsEL1Regime :: bool) . - ( - if IsEL1Regime then - (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__6 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__6 (( 27 :: int):: ii)] :: 1 Word.word)) - else - (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__7 :: 32 bits) . - return - (vec_of_bits [access_vec_dec w__7 (( 27 :: int):: ii)] :: 1 Word.word))) - \<bind> - (\<lambda> (w__8 :: 1 Word.word) . - (let Enable = w__8 in - and_boolM - (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) - (IsSecure () \<bind> - (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) - ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> - (\<lambda> (w__11 :: 64 bits) . - return - ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__12 :: bool) . - (let TrapEL2 = w__12 in - and_boolM (return ((HaveEL EL3))) - ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__13 :: 32 bits) . - return - ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int):: ii)] :: 1 Word.word) - = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> - (\<lambda> (w__14 :: bool) . - (let (TrapEL3 :: bool) = w__14 in - return (Enable, TrapEL2, TrapEL3)))))))) - ) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: bool), (TrapEL3 :: bool)) = varstup in + read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . + (let p__284 = ((ProcState_EL w__2)) in + (let pat0 = p__284 in + (if (((pat0 = EL0))) then + or_boolM + (or_boolM (return ((\<not> ((HaveEL EL2))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word))))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__5 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (IsEL1Regime :: bool) . + (if IsEL1Regime then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__6 (( 27 :: int)::ii)] :: 1 Word.word)) + else + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . + return (vec_of_bits [access_vec_dec w__7 (( 27 :: int)::ii)] :: 1 Word.word))) \<bind> (\<lambda> (w__8 :: 1 Word.word) . + (let Enable = w__8 in + and_boolM + (and_boolM (return (((((HaveEL EL2)) \<and> IsEL1Regime)))) + (IsSecure () \<bind> (\<lambda> (w__9 :: bool) . return ((\<not> w__9))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__11 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__12 :: bool) . + (let TrapEL2 = w__12 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__13 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__14 :: bool) . + (let (TrapEL3 :: bool) = w__14 in + return (Enable, TrapEL2, TrapEL3)))))))) + else if (((pat0 = EL1))) then + (read_reg SCTLR_EL1_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__15 (( 27 :: int)::ii)] :: 1 Word.word)) in + and_boolM + (and_boolM (return ((HaveEL EL2))) + (IsSecure () \<bind> (\<lambda> (w__16 :: bool) . return ((\<not> w__16))))) + ((read_reg HCR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + return ((((vec_of_bits [access_vec_dec w__18 (( 41 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__19 :: bool) . + (let TrapEL2 = w__19 in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__20 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__21 :: bool) . + (let (TrapEL3 :: bool) = w__21 in + return (Enable, TrapEL2, TrapEL3))))))) + else if (((pat0 = EL2))) then + (read_reg SCTLR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . + (let Enable = ((vec_of_bits [access_vec_dec w__22 (( 27 :: int)::ii)] :: 1 Word.word)) in + (let TrapEL2 = False in + and_boolM (return ((HaveEL EL3))) + ((read_reg SCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . + return ((((vec_of_bits [access_vec_dec w__23 (( 17 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B0] :: 1 Word.word)))))) \<bind> (\<lambda> (w__24 :: bool) . + (let (TrapEL3 :: bool) = w__24 in + return (Enable, TrapEL2, TrapEL3)))))) + else + (read_reg SCTLR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__25 :: 32 bits) . + (let (Enable :: 1 bits) = ((vec_of_bits [access_vec_dec w__25 (( 27 :: int)::ii)] :: 1 Word.word)) in + (let (TrapEL2 :: bool) = False in + (let (TrapEL3 :: bool) = False in + return (Enable, TrapEL2, TrapEL3)))))) \<bind> (\<lambda> varstup . (let ((Enable :: 1 bits), (TrapEL2 :: + bool), (TrapEL3 :: bool)) = varstup in if (((Enable = (vec_of_bits [B0] :: 1 Word.word)))) then return X else if TrapEL2 then TrapPACUse EL2 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) else if TrapEL3 then TrapPACUse EL3 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) - else (AddPAC X Y APDAKey_EL1 True :: ( 64 Word.word) M)))))))))))" + else (AddPAC X Y APDAKey_EL1 True :: ( 64 Word.word) M)))))))))))))" (*val aarch64_integer_pac_pacda_dp_1src : ii -> ii -> bool -> M unit*) @@ -16568,11 +16761,11 @@ definition AArch64_WFxTrap :: "(2)Word.word \<Rightarrow> bool \<Rightarrow>((r ExceptionSyndrome Exception_WFxTrap \<bind> (\<lambda> (exception :: ExceptionRecord) . (let (tmp_2720 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in (ConditionSyndrome () :: ( 5 Word.word) M) \<bind> (\<lambda> (w__1 :: 5 Word.word) . - (let tmp_2720 = ((set_slice0 (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2720 (( 20 :: int)::ii) w__1 :: 25 Word.word)) in + (let tmp_2720 = ((set_slice (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2720 (( 20 :: int)::ii) w__1 :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2720 |))) in (let (tmp_2730 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in (let tmp_2730 = - ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2730 (( 0 :: int)::ii) + ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2730 (( 0 :: int)::ii) (if is_wfe then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word)) :: 25 Word.word)) in @@ -16785,25 +16978,25 @@ definition AArch64_SystemRegisterTrap :: "(2)Word.word \<Rightarrow>(2)Word.wor (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in ExceptionSyndrome Exception_SystemRegisterTrap \<bind> (\<lambda> (exception :: ExceptionRecord) . (let (tmp_2800 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in - (let tmp_2800 = ((set_slice0 (( 25 :: int)::ii) (( 2 :: int)::ii) tmp_2800 (( 20 :: int)::ii) op0 :: 25 Word.word)) in + (let tmp_2800 = ((set_slice (( 25 :: int)::ii) (( 2 :: int)::ii) tmp_2800 (( 20 :: int)::ii) op0 :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2800 |))) in (let (tmp_2810 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in - (let tmp_2810 = ((set_slice0 (( 25 :: int)::ii) (( 3 :: int)::ii) tmp_2810 (( 17 :: int)::ii) op2 :: 25 Word.word)) in + (let tmp_2810 = ((set_slice (( 25 :: int)::ii) (( 3 :: int)::ii) tmp_2810 (( 17 :: int)::ii) op2 :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2810 |))) in (let (tmp_2820 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in - (let tmp_2820 = ((set_slice0 (( 25 :: int)::ii) (( 3 :: int)::ii) tmp_2820 (( 14 :: int)::ii) op1 :: 25 Word.word)) in + (let tmp_2820 = ((set_slice (( 25 :: int)::ii) (( 3 :: int)::ii) tmp_2820 (( 14 :: int)::ii) op1 :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2820 |))) in (let (tmp_2830 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in - (let tmp_2830 = ((set_slice0 (( 25 :: int)::ii) (( 4 :: int)::ii) tmp_2830 (( 10 :: int)::ii) crn :: 25 Word.word)) in + (let tmp_2830 = ((set_slice (( 25 :: int)::ii) (( 4 :: int)::ii) tmp_2830 (( 10 :: int)::ii) crn :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2830 |))) in (let (tmp_2840 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in - (let tmp_2840 = ((set_slice0 (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2840 (( 5 :: int)::ii) rt :: 25 Word.word)) in + (let tmp_2840 = ((set_slice (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2840 (( 5 :: int)::ii) rt :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2840 |))) in (let (tmp_2850 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in - (let tmp_2850 = ((set_slice0 (( 25 :: int)::ii) (( 4 :: int)::ii) tmp_2850 (( 1 :: int)::ii) crm :: 25 Word.word)) in + (let tmp_2850 = ((set_slice (( 25 :: int)::ii) (( 4 :: int)::ii) tmp_2850 (( 1 :: int)::ii) crm :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2850 |))) in (let (tmp_2860 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in - (let tmp_2860 = ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2860 (( 0 :: int)::ii) dir :: 25 Word.word)) in + (let tmp_2860 = ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2860 (( 0 :: int)::ii) dir :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2860 |))) in and_boolM (and_boolM (return ((((((target_el = EL1))) \<and> ((HaveEL EL2)))))) @@ -16836,7 +17029,7 @@ definition AArch64_SoftwareBreakpoint :: "(16)Word.word \<Rightarrow>((register (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in ExceptionSyndrome Exception_SoftwareBreakpoint \<bind> (\<lambda> (exception :: ExceptionRecord) . (let (tmp_2710 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in - (let tmp_2710 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2710 (( 0 :: int)::ii) immediate :: 25 Word.word)) in + (let tmp_2710 = ((set_slice (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2710 (( 0 :: int)::ii) immediate :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2710 |))) in read_reg PSTATE_ref \<bind> (\<lambda> (w__9 :: ProcState) . if ((((Word.uint(ProcState_EL w__9))) > ((Word.uint EL1)))) then @@ -17010,33 +17203,33 @@ definition AArch64_CheckForERetTrap :: " bool \<Rightarrow> bool \<Rightarrow>( (let (tmp_2550 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in (ZeroExtend__0 (vec_of_bits [B0] :: 1 Word.word) ((make_the_value (( 23 :: int)::ii) :: 23 itself)) :: ( 23 Word.word) M) \<bind> (\<lambda> (w__6 :: 23 Word.word) . - (let tmp_2550 = ((set_slice0 (( 25 :: int)::ii) (( 23 :: int)::ii) tmp_2550 (( 2 :: int)::ii) w__6 :: 25 Word.word)) in + (let tmp_2550 = ((set_slice (( 25 :: int)::ii) (( 23 :: int)::ii) tmp_2550 (( 2 :: int)::ii) w__6 :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2550 |))) in (let (exception :: ExceptionRecord) = (if ((\<not> eret_with_pac)) then (let (tmp_2560 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in (let (tmp_2560 :: 25 bits) = - ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2560 (( 1 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 25 Word.word)) in + ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2560 (( 1 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 25 Word.word)) in (let (exception :: ExceptionRecord) = ((exception (| ExceptionRecord_syndrome := tmp_2560 |))) in (let (tmp_2570 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in (let (tmp_2570 :: 25 bits) = - ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2570 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 25 Word.word)) in + ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2570 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 25 Word.word)) in (exception (| ExceptionRecord_syndrome := tmp_2570 |))))))) else (let (tmp_2580 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in (let (tmp_2580 :: 25 bits) = - ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2580 (( 1 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 25 Word.word)) in + ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2580 (( 1 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 25 Word.word)) in (let (exception :: ExceptionRecord) = ((exception (| ExceptionRecord_syndrome := tmp_2580 |))) in if pac_uses_key_a then (let (tmp_2590 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in (let (tmp_2590 :: 25 bits) = - ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2590 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) + ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2590 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 25 Word.word)) in (exception (| ExceptionRecord_syndrome := tmp_2590 |)))) else (let (tmp_2600 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in (let (tmp_2600 :: 25 bits) = - ((set_slice0 (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2600 (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) + ((set_slice (( 25 :: int)::ii) (( 1 :: int)::ii) tmp_2600 (( 0 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 25 Word.word)) in (exception (| ExceptionRecord_syndrome := tmp_2600 |)))))))) in AArch64_TakeException EL2 exception preferred_exception_return vect_offset)))))))))) @@ -17062,7 +17255,7 @@ definition AArch64_CallSupervisor :: "(16)Word.word \<Rightarrow>((register_val (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in ExceptionSyndrome Exception_SupervisorCall \<bind> (\<lambda> (exception :: ExceptionRecord) . (let (tmp_2770 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in - (let tmp_2770 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2770 (( 0 :: int)::ii) immediate :: 25 Word.word)) in + (let tmp_2770 = ((set_slice (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2770 (( 0 :: int)::ii) immediate :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2770 |))) in read_reg PSTATE_ref \<bind> (\<lambda> (w__6 :: ProcState) . if ((((Word.uint(ProcState_EL w__6))) > ((Word.uint EL1)))) then @@ -17103,7 +17296,7 @@ definition AArch64_CallSecureMonitor :: "(16)Word.word \<Rightarrow>((register_ (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in ExceptionSyndrome Exception_MonitorCall \<bind> (\<lambda> (exception :: ExceptionRecord) . (let (tmp_2930 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in - (let tmp_2930 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2930 (( 0 :: int)::ii) immediate :: 25 Word.word)) in + (let tmp_2930 = ((set_slice (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2930 (( 0 :: int)::ii) immediate :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2930 |))) in AArch64_TakeException EL3 exception preferred_exception_return vect_offset)))))))))" @@ -17121,7 +17314,7 @@ definition AArch64_CallHypervisor :: "(16)Word.word \<Rightarrow>((register_val (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in ExceptionSyndrome Exception_HypervisorCall \<bind> (\<lambda> (exception :: ExceptionRecord) . (let (tmp_2890 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in - (let tmp_2890 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2890 (( 0 :: int)::ii) immediate :: 25 Word.word)) in + (let tmp_2890 = ((set_slice (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_2890 (( 0 :: int)::ii) immediate :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2890 |))) in read_reg PSTATE_ref \<bind> (\<lambda> (w__1 :: ProcState) . if ((((ProcState_EL w__1) = EL3))) then @@ -17214,7 +17407,7 @@ definition AArch32_EnterMode :: "(5)Word.word \<Rightarrow>(32)Word.word \<Righ (read_reg SCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) . write_reg SCR_ref - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__4 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__4 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) else return () ) \<then> AArch32_WriteMode target_mode) \<then> aset_SPSR spsr) \<then> @@ -17270,7 +17463,7 @@ definition AArch32_EnterMode :: "(5)Word.word \<Rightarrow>(32)Word.word \<Righ else return () ) \<then> (ExcVectorBase () :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__21 :: 32 Word.word) . BranchTo - ((concat_vec ((slice0 w__21 (( 5 :: int)::ii) (( 27 :: int)::ii) :: 27 Word.word)) + ((concat_vec ((slice w__21 (( 5 :: int)::ii) (( 27 :: int)::ii) :: 27 Word.word)) ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) vect_offset (( 0 :: int)::ii) :: 5 Word.word)) :: 32 Word.word)) BranchType_UNKNOWN \<then> EndOfInstruction () ))))))))))))))" @@ -17297,7 +17490,7 @@ definition AArch64_AdvSIMDFPAccessTrap :: "(2)Word.word \<Rightarrow>((register (let exception = w__4 in (let (tmp_2610 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in (ConditionSyndrome () :: ( 5 Word.word) M) \<bind> (\<lambda> (w__5 :: 5 Word.word) . - (let tmp_2610 = ((set_slice0 (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2610 (( 20 :: int)::ii) w__5 :: 25 Word.word)) in + (let tmp_2610 = ((set_slice (( 25 :: int)::ii) (( 5 :: int)::ii) tmp_2610 (( 20 :: int)::ii) w__5 :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_2610 |))) in AArch64_TakeException target_el exception preferred_exception_return vect_offset)))))))))))" @@ -17315,8 +17508,8 @@ definition AArch64_CheckFPAdvSIMDTrap :: " unit \<Rightarrow>((register_value), return ((((vec_of_bits [access_vec_dec w__2 (( 34 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) \<bind> (\<lambda> (w__3 :: bool) . if w__3 then (read_reg CPTR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 bits) . - (let p__607 = ((slice0 w__4 (( 20 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in - (let v__94 = p__607 in + (let p__283 = ((slice w__4 (( 20 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let v__94 = p__283 in (if (((((subrange_vec_dec v__94 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then and_boolM (read_reg PSTATE_ref \<bind> (\<lambda> (w__5 :: ProcState) . @@ -17359,8 +17552,8 @@ definition AArch64_CheckFPAdvSIMDEnabled :: " unit \<Rightarrow>((register_valu bool) . (if w__2 then (aget_CPACR () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . - (let p__606 = ((slice0 w__3 (( 20 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in - (let v__96 = p__606 in + (let p__282 = ((slice w__3 (( 20 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let v__96 = p__282 in (if (((((subrange_vec_dec v__96 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then return True else if (((v__96 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then @@ -17480,7 +17673,7 @@ definition aarch64_float_convert_int :: " int \<Rightarrow>('fltsize::len)itsel | FPConvOp_MOV_ItoF => (aget_X intsize n :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__8 :: 'intsize bits) . (let intval = w__8 in - (let fltval = ((slice0 intval (( 0 :: int)::ii) fltsize :: ( 'fltsize::len)Word.word)) in + (let fltval = ((slice intval (( 0 :: int)::ii) fltsize :: ( 'fltsize::len)Word.word)) in aset_Vpart d part fltval))) | FPConvOp_CVT_FtoI_JS => (aget_V fltsize n :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__9 :: 'fltsize bits) . @@ -17488,7 +17681,7 @@ definition aarch64_float_convert_int :: " int \<Rightarrow>('fltsize::len)itsel (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . (FPToFixedJS intsize fltval w__10 True :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__11 :: 'intsize bits) . (let intval = w__11 in - (ZeroExtend__0 ((slice0 intval (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + (ZeroExtend__0 ((slice intval (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 :: 64 Word.word) . aset_X d w__12)))))) @@ -18441,7 +18634,7 @@ definition AArch64_CheckWatchpoint :: "(64)Word.word \<Rightarrow> AccType \<Ri ((let (val_match :: bool) = False in AArch64_AccessIsPrivileged acctype \<bind> (\<lambda> (ispriv :: bool) . (read_reg ID_AA64DFR0_EL1_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . - (foreachM (index_list (( 0 :: int)::ii) ((Word.uint ((slice0 w__2 (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))) (( 1 :: int)::ii)) val_match + (foreachM (index_list (( 0 :: int)::ii) ((Word.uint ((slice w__2 (( 20 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)))) (( 1 :: int)::ii)) val_match (\<lambda> i val_match . or_boolM (return val_match) ((AArch64_WatchpointMatch i vaddress size1 ispriv iswrite)))) \<bind> (\<lambda> (val_match :: bool) . @@ -18509,7 +18702,7 @@ definition AArch64_CheckPermission :: " Permissions \<Rightarrow>(64)Word.word (let user_r = ((vec_of_bits [access_vec_dec(Permissions_ap perms) (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in (let user_w = - (((slice0(Permissions_ap perms) (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in + (((slice(Permissions_ap perms) (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)) in AArch64_AccessIsPrivileged acctype \<bind> (\<lambda> (w__8 :: bool) . (let ispriv = w__8 in (if ((HavePANExt () )) then @@ -18774,7 +18967,7 @@ definition aset_Mem :: "(64)Word.word \<Rightarrow> int \<Rightarrow> AccType \ if ((\<not> atomic)) then ((assert_exp ((size1 > (( 1 :: int)::ii))) (''(size > 1)'') \<then> AArch64_aset_MemSingle address (( 1 :: int)::ii) acctype aligned - ((slice0 value_name (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))) \<then> + ((slice value_name (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))) \<then> (if ((\<not> aligned)) then (let c = (ConstrainUnpredictable Unpredictable_DEVPAGE2) in assert_exp ((((((c = Constraint_FAULT))) \<or> (((c = Constraint_NONE)))))) (''((c == Constraint_FAULT) || (c == Constraint_NONE))'') \<then> @@ -18784,12 +18977,12 @@ definition aset_Mem :: "(64)Word.word \<Rightarrow> int \<Rightarrow> AccType \ (foreachM (index_list (( 1 :: int)::ii) ((size1 - (( 1 :: int)::ii))) (( 1 :: int)::ii)) () (\<lambda> i unit_var . AArch64_aset_MemSingle ((add_vec_int address i :: 64 Word.word)) (( 1 :: int)::ii) acctype aligned - ((slice0 value_name (((( 8 :: int)::ii) * i)) (( 8 :: int)::ii) :: 8 Word.word))))) + ((slice value_name (((( 8 :: int)::ii) * i)) (( 8 :: int)::ii) :: 8 Word.word))))) else if ((((((size1 = (( 16 :: int)::ii)))) \<and> ((((((acctype = AccType_VEC))) \<or> (((acctype = AccType_VECSTREAM))))))))) then AArch64_aset_MemSingle address (( 8 :: int)::ii) acctype aligned - ((slice0 value_name (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) \<then> + ((slice value_name (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) \<then> AArch64_aset_MemSingle ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype aligned - ((slice0 value_name (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice value_name (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) else AArch64_aset_MemSingle address size1 acctype aligned value_name))))))))))" @@ -18831,7 +19024,7 @@ definition aget_Mem :: "(64)Word.word \<Rightarrow> int \<Rightarrow> AccType \ (AArch64_aget_MemSingle address (( 1 :: int)::ii) acctype aligned :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__0 :: 8 Word.word) . (let value_name = - ((set_slice0 (((( 8 :: int)::ii) * size1)) (( 8 :: int)::ii) value_name (( 0 :: int)::ii) w__0 + ((set_slice (((( 8 :: int)::ii) * size1)) (( 8 :: int)::ii) value_name (( 0 :: int)::ii) w__0 :: ( 'p8_times_size_::len)Word.word)) in (if ((\<not> aligned)) then (let c = (ConstrainUnpredictable Unpredictable_DEVPAGE2) in @@ -18844,19 +19037,19 @@ definition aget_Mem :: "(64)Word.word \<Rightarrow> int \<Rightarrow> AccType \ (AArch64_aget_MemSingle ((add_vec_int address i :: 64 Word.word)) (( 1 :: int)::ii) acctype aligned :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 Word.word) . (let value_name = - ((set_slice0 (((( 8 :: int)::ii) * size1)) (( 8 :: int)::ii) value_name (((( 8 :: int)::ii) * i)) w__1 + ((set_slice (((( 8 :: int)::ii) * size1)) (( 8 :: int)::ii) value_name (((( 8 :: int)::ii) * i)) w__1 :: ( 'p8_times_size_::len)Word.word)) in return value_name))))))) else if ((((((size1 = (( 16 :: int)::ii)))) \<and> ((((((acctype = AccType_VEC))) \<or> (((acctype = AccType_VECSTREAM))))))))) then (AArch64_aget_MemSingle address (( 8 :: int)::ii) acctype aligned :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . (let value_name = - ((set_slice0 (((( 8 :: int)::ii) * size1)) (( 64 :: int)::ii) value_name (( 0 :: int)::ii) w__2 + ((set_slice (((( 8 :: int)::ii) * (( 16 :: int)::ii))) (( 64 :: int)::ii) value_name (( 0 :: int)::ii) w__2 :: ( 'p8_times_size_::len)Word.word)) in (AArch64_aget_MemSingle ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype aligned :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . (let value_name = - ((set_slice0 (((( 8 :: int)::ii) * size1)) (( 64 :: int)::ii) value_name (( 64 :: int)::ii) w__3 + ((set_slice (((( 8 :: int)::ii) * (( 16 :: int)::ii))) (( 64 :: int)::ii) value_name (( 64 :: int)::ii) w__3 :: ( 'p8_times_size_::len)Word.word)) in return value_name)))) else (AArch64_aget_MemSingle address size1 acctype aligned :: (( 'p8_times_size_::len)Word.word) M)) \<bind> (\<lambda> value_name . @@ -18885,8 +19078,8 @@ definition aarch64_memory_vector_single_nowb :: "('datasize::len)itself \<Right else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M))) \<bind> (\<lambda> (address :: 64 bits) . (let offs = ((Zeros__1 (( 64 :: int)::ii) () :: 64 Word.word)) in (if replicate1 then - (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs - (\<lambda> s offs . + (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (element, offs, t) + (\<lambda> s varstup . (let (element, offs, t) = varstup in (aget_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'esize bits) . (let element = w__2 in @@ -18895,10 +19088,12 @@ definition aarch64_memory_vector_single_nowb :: "('datasize::len)itself \<Right aset_V t ((replicate_bits element v :: ( 'datasize::len)Word.word))) \<then> ((let (offs :: 64 bits) = ((add_vec_int offs ebytes :: 64 Word.word)) in (let (t :: ii) = (((((ex_int t)) + (( 1 :: int)::ii))) mod (( 32 :: int)::ii)) in - return offs)))))))) + return (element, offs, t)))))))))) \<bind> (\<lambda> varstup . (let ((element :: 'esize bits), (offs :: 64 + bits), (t :: ii)) = varstup in + return offs)) else - (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs - (\<lambda> s offs . + (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (offs, rval, t) + (\<lambda> s varstup . (let (offs, rval, t) = varstup in (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \<bind> (\<lambda> (w__3 :: 128 bits) . (let rval = w__3 in (if (((memop = MemOp_LOAD))) then @@ -18907,13 +19102,16 @@ definition aarch64_memory_vector_single_nowb :: "('datasize::len)itself \<Right (aset_Elem__0 rval index1 ((make_the_value esize :: ( 'esize::len)itself)) w__4 :: ( 128 Word.word) M) \<bind> (\<lambda> (w__5 :: 128 bits) . (let rval = w__5 in - aset_V t rval))) + aset_V t rval \<then> return rval))) else (aget_Elem__0 rval index1 ((make_the_value esize :: ( 'esize::len)itself)) :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> w__6 . - aset_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC w__6)) \<then> - ((let (offs :: 64 bits) = ((add_vec_int offs ebytes :: 64 Word.word)) in + aset_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC w__6 \<then> return rval)) \<bind> (\<lambda> (rval :: 128 + bits) . + (let (offs :: 64 bits) = ((add_vec_int offs ebytes :: 64 Word.word)) in (let (t :: ii) = (((((ex_int t)) + (( 1 :: int)::ii))) mod (( 32 :: int)::ii)) in - return offs)))))))) \<bind> (\<lambda> (offs :: 64 bits) . + return (offs, rval, t))))))))) \<bind> (\<lambda> varstup . (let ((offs :: 64 bits), (rval :: 128 bits), (t :: + ii)) = varstup in + return offs))) \<bind> (\<lambda> (offs :: 64 bits) . if wback then (if (((m \<noteq> (( 31 :: int)::ii)))) then (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) else return offs) \<bind> (\<lambda> (offs :: 64 bits) . @@ -18942,13 +19140,13 @@ definition aarch64_memory_vector_multiple_nowb :: "('datasize::len)itself \<Rig (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M))) \<bind> (\<lambda> (address :: 64 bits) . (let offs = ((Zeros__1 (( 64 :: int)::ii) () :: 64 Word.word)) in - (foreachM (index_list (( 0 :: int)::ii) ((rpt - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs - (\<lambda> r offs . - (foreachM (index_list (( 0 :: int)::ii) ((elements - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs - (\<lambda> e offs . + (foreachM (index_list (( 0 :: int)::ii) ((rpt - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (offs, rval, tt) + (\<lambda> r varstup . (let (offs, rval, tt) = varstup in + (foreachM (index_list (( 0 :: int)::ii) ((elements - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (offs, rval, tt) + (\<lambda> e varstup . (let (offs, rval, tt) = varstup in (let tt = (((t + r)) mod (( 32 :: int)::ii)) in - (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) offs - (\<lambda> s offs . + (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (offs, rval, tt) + (\<lambda> s varstup . (let (offs, rval, tt) = varstup in (aget_V datasize tt :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'datasize bits) . (let rval = w__2 in (if (((memop = MemOp_LOAD))) then @@ -18957,19 +19155,21 @@ definition aarch64_memory_vector_multiple_nowb :: "('datasize::len)itself \<Rig (aset_Elem__0 rval e ((make_the_value esize :: ( 'esize::len)itself)) w__3 :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__4 :: 'datasize bits) . (let rval = w__4 in - aset_V tt rval))) + aset_V tt rval \<then> return rval))) else (aget_Elem__0 rval e ((make_the_value esize :: ( 'esize::len)itself)) :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> w__5 . - aset_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC w__5)) \<then> - ((let (offs :: 64 bits) = ((add_vec_int offs ebytes :: 64 Word.word)) in + aset_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC w__5 \<then> + return rval)) \<bind> (\<lambda> (rval :: 'datasize bits) . + (let (offs :: 64 bits) = ((add_vec_int offs ebytes :: 64 Word.word)) in (let (tt :: ii) = (((((ex_int tt)) + (( 1 :: int)::ii))) mod (( 32 :: int)::ii)) in - return offs)))))))))))) \<bind> (\<lambda> (offs :: 64 bits) . + return (offs, rval, tt)))))))))))))))) \<bind> (\<lambda> varstup . (let ((offs :: 64 bits), (rval :: 'datasize + bits), (tt :: ii)) = varstup in if wback then (if (((m \<noteq> (( 31 :: int)::ii)))) then (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) else return offs) \<bind> (\<lambda> (offs :: 64 bits) . if (((n = (( 31 :: int)::ii)))) then aset_SP ((add_vec address offs :: 64 Word.word)) else aset_X n ((add_vec address offs :: 64 Word.word))) - else return () ))))))))))))))" + else return () )))))))))))))))" (*val aarch64_memory_single_simdfp_register : AccType -> ii -> ExtendType -> ii -> MemOp -> ii -> bool -> ii -> ii -> bool -> M unit*) @@ -20339,20 +20539,20 @@ definition aarch64_memory_atomicops_cas_pair :: " int \<Rightarrow> AccType \<R else return () ) \<then> BigEndian () ) \<bind> (\<lambda> (w__5 :: bool) . if w__5 then - (ZeroExtend__0 ((slice0 data (( 8 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) + (ZeroExtend__0 ((slice data (( 8 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: ( 'regsize::len)Word.word) . (aset_X s w__6 \<then> - (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__7 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__7)) else - (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__8 :: ( 'regsize::len)Word.word) . (aset_X s w__8 \<then> - (ZeroExtend__0 ((slice0 data (( 8 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) + (ZeroExtend__0 ((slice data (( 8 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__9 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__9))))))))))))))))))))) @@ -20388,20 +20588,20 @@ definition aarch64_memory_atomicops_cas_pair :: " int \<Rightarrow> AccType \<R else return () ) \<then> BigEndian () ) \<bind> (\<lambda> (w__15 :: bool) . if w__15 then - (ZeroExtend__0 ((slice0 data (( 16 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + (ZeroExtend__0 ((slice data (( 16 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__16 :: ( 'regsize::len)Word.word) . (aset_X s w__16 \<then> - (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__17 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__17)) else - (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__18 :: ( 'regsize::len)Word.word) . (aset_X s w__18 \<then> - (ZeroExtend__0 ((slice0 data (( 16 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + (ZeroExtend__0 ((slice data (( 16 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__19 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__19))))))))))))))))))))) @@ -20437,20 +20637,20 @@ definition aarch64_memory_atomicops_cas_pair :: " int \<Rightarrow> AccType \<R else return () ) \<then> BigEndian () ) \<bind> (\<lambda> (w__25 :: bool) . if w__25 then - (ZeroExtend__0 ((slice0 data (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + (ZeroExtend__0 ((slice data (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__26 :: ( 'regsize::len)Word.word) . (aset_X s w__26 \<then> - (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__27 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__27)) else - (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__28 :: ( 'regsize::len)Word.word) . (aset_X s w__28 \<then> - (ZeroExtend__0 ((slice0 data (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + (ZeroExtend__0 ((slice data (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__29 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__29))))))))))))))))))))) @@ -20486,20 +20686,20 @@ definition aarch64_memory_atomicops_cas_pair :: " int \<Rightarrow> AccType \<R else return () ) \<then> BigEndian () ) \<bind> (\<lambda> (w__35 :: bool) . if w__35 then - (ZeroExtend__0 ((slice0 data (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + (ZeroExtend__0 ((slice data (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__36 :: ( 'regsize::len)Word.word) . (aset_X s w__36 \<then> - (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__37 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__37)) else - (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: ( 'regsize::len)Word.word) . (aset_X s w__38 \<then> - (ZeroExtend__0 ((slice0 data (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + (ZeroExtend__0 ((slice data (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__39 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__39))))))))))))))))))))) @@ -20535,20 +20735,20 @@ definition aarch64_memory_atomicops_cas_pair :: " int \<Rightarrow> AccType \<R else return () ) \<then> BigEndian () ) \<bind> (\<lambda> (w__45 :: bool) . if w__45 then - (ZeroExtend__0 ((slice0 data (( 128 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) + (ZeroExtend__0 ((slice data (( 128 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__46 :: ( 'regsize::len)Word.word) . (aset_X s w__46 \<then> - (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__47 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__47)) else - (ZeroExtend__0 ((slice0 data (( 0 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__48 :: ( 'regsize::len)Word.word) . (aset_X s w__48 \<then> - (ZeroExtend__0 ((slice0 data (( 128 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) + (ZeroExtend__0 ((slice data (( 128 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__49 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__49))))))))))))))))))))) @@ -20645,10 +20845,10 @@ definition AArch32_GenerateDebugExceptionsFrom :: "(2)Word.word \<Rightarrow> b ELUsingAArch32 EL3 \<bind> (\<lambda> (w__9 :: bool) . (if w__9 then (read_reg SDCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . - return ((slice0 w__10 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) + return ((slice w__10 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) else (read_reg MDCR_EL3_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: 32 bits) . - return ((slice0 w__11 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)))) \<bind> (\<lambda> (w__12 :: 2 Word.word) . + return ((slice w__11 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)))) \<bind> (\<lambda> (w__12 :: 2 Word.word) . (let spd = w__12 in (if ((((vec_of_bits [access_vec_dec spd (( 1 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then (let (enabled :: bool) = @@ -20744,12 +20944,12 @@ definition SetPSTATEFromPSR :: "(32)Word.word \<Rightarrow>((register_value),(u PSTATE_ref (w__4 (| ProcState_IL := ((vec_of_bits [access_vec_dec spsr (( 20 :: int)::ii)] :: 1 Word.word))|)) \<then> (if ((((vec_of_bits [access_vec_dec spsr (( 4 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then - AArch32_WriteMode ((slice0 spsr (( 0 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) + AArch32_WriteMode ((slice spsr (( 0 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) else read_reg PSTATE_ref \<bind> (\<lambda> (w__5 :: ProcState) . (write_reg PSTATE_ref (w__5 (| ProcState_nRW := ((vec_of_bits [B0] :: 1 Word.word))|)) \<then> read_reg PSTATE_ref) \<bind> (\<lambda> (w__6 :: ProcState) . - (write_reg PSTATE_ref (w__6 (| ProcState_EL := ((slice0 spsr (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|)) \<then> + (write_reg PSTATE_ref (w__6 (| ProcState_EL := ((slice spsr (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))|)) \<then> read_reg PSTATE_ref) \<bind> (\<lambda> (w__7 :: ProcState) . write_reg PSTATE_ref @@ -20763,11 +20963,11 @@ definition SetPSTATEFromPSR :: "(32)Word.word \<Rightarrow>((register_value),(u ConstrainUnpredictableBool Unpredictable_ILZEROT \<bind> (\<lambda> (w__11 :: bool) . (let (spsr :: 32 Word.word) = (if w__11 then - (set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) spsr (( 5 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word) + (set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) spsr (( 5 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word) else spsr) in return spsr)) else return spsr) \<bind> (\<lambda> (spsr :: 32 Word.word) . - (let split_vec = ((slice0 spsr (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + (let split_vec = ((slice spsr (( 28 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in (let (tup__0, tup__1, tup__2, tup__3) = ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), @@ -20791,12 +20991,12 @@ definition SetPSTATEFromPSR :: "(32)Word.word \<Rightarrow>((register_value),(u (RestoredITBits spsr :: ( 8 Word.word) M) \<bind> (\<lambda> (w__19 :: 8 bits) . (write_reg PSTATE_ref (w__18 (| ProcState_IT := w__19 |)) \<then> read_reg PSTATE_ref) \<bind> (\<lambda> (w__20 :: ProcState) . - (write_reg PSTATE_ref (w__20 (| ProcState_GE := ((slice0 spsr (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word))|)) \<then> + (write_reg PSTATE_ref (w__20 (| ProcState_GE := ((slice spsr (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word))|)) \<then> read_reg PSTATE_ref) \<bind> (\<lambda> (w__21 :: ProcState) . write_reg PSTATE_ref (w__21 (| ProcState_E := ((vec_of_bits [access_vec_dec spsr (( 9 :: int)::ii)] :: 1 Word.word))|)) \<then> - ((let split_vec = ((slice0 spsr (( 6 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + ((let split_vec = ((slice spsr (( 6 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in (let (tup__0, tup__1, tup__2) = ((subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), (subrange_vec_dec split_vec (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word), @@ -20812,7 +21012,7 @@ definition SetPSTATEFromPSR :: "(32)Word.word \<Rightarrow>((register_value),(u PSTATE_ref (w__25 (| ProcState_T := ((vec_of_bits [access_vec_dec spsr (( 5 :: int)::ii)] :: 1 Word.word))|)))))))))))))) else - (let split_vec = ((slice0 spsr (( 6 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in + (let split_vec = ((slice spsr (( 6 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in (let (tup__0, tup__1, tup__2, tup__3) = ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), (subrange_vec_dec split_vec (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word), @@ -20965,9 +21165,9 @@ definition AArch64_ExceptionReturn :: "(64)Word.word \<Rightarrow>(32)Word.word read_reg PSTATE_ref) \<bind> (\<lambda> (w__2 :: ProcState) . (if ((((ProcState_IL w__2) = (vec_of_bits [B1] :: 1 Word.word)))) then (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . - (let new_pc = ((set_slice0 (( 64 :: int)::ii) (( 32 :: int)::ii) new_pc (( 32 :: int)::ii) w__3 :: 64 Word.word)) in + (let new_pc = ((set_slice (( 64 :: int)::ii) (( 32 :: int)::ii) new_pc (( 32 :: int)::ii) w__3 :: 64 Word.word)) in (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__4 :: 2 Word.word) . - (let (new_pc :: 64 Word.word) = ((set_slice0 (( 64 :: int)::ii) (( 2 :: int)::ii) new_pc (( 0 :: int)::ii) w__4 :: 64 Word.word)) in + (let (new_pc :: 64 Word.word) = ((set_slice (( 64 :: int)::ii) (( 2 :: int)::ii) new_pc (( 0 :: int)::ii) w__4 :: 64 Word.word)) in return new_pc)))) else UsingAArch32 () \<bind> (\<lambda> (w__5 :: bool) . @@ -20975,13 +21175,13 @@ definition AArch64_ExceptionReturn :: "(64)Word.word \<Rightarrow>(32)Word.word read_reg PSTATE_ref \<bind> (\<lambda> (w__6 :: ProcState) . (let (new_pc :: 64 Word.word) = (if ((((ProcState_T w__6) = (vec_of_bits [B0] :: 1 Word.word)))) then - (set_slice0 (( 64 :: int)::ii) (( 1 :: int)::ii) new_pc (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word) + (set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) new_pc (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word) else - (set_slice0 (( 64 :: int)::ii) (( 2 :: int)::ii) new_pc (( 0 :: int)::ii) (vec_of_bits [B0,B0] :: 2 Word.word) :: 64 Word.word)) in + (set_slice (( 64 :: int)::ii) (( 2 :: int)::ii) new_pc (( 0 :: int)::ii) (vec_of_bits [B0,B0] :: 2 Word.word) :: 64 Word.word)) in return new_pc)) else (AArch64_BranchAddr new_pc :: ( 64 Word.word) M))) \<bind> (\<lambda> (new_pc :: 64 Word.word) . UsingAArch32 () \<bind> (\<lambda> (w__8 :: bool) . - if w__8 then BranchTo ((slice0 new_pc (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) BranchType_UNKNOWN + if w__8 then BranchTo ((slice new_pc (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) BranchType_UNKNOWN else BranchToAddr new_pc BranchType_ERET))))))))" @@ -21079,7 +21279,7 @@ definition AArch32_EnterHypMode :: " ExceptionRecord \<Rightarrow>(32)Word.word (w__19 (| ProcState_IT := ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))|)) \<then> (read_reg HVBAR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__20 :: 32 bits) . BranchTo - ((concat_vec ((slice0 w__20 (( 5 :: int)::ii) (( 27 :: int)::ii) :: 27 Word.word)) + ((concat_vec ((slice w__20 (( 5 :: int)::ii) (( 27 :: int)::ii) :: 27 Word.word)) ((GetSlice_int ((make_the_value (( 5 :: int)::ii) :: 5 itself)) vect_offset (( 0 :: int)::ii) :: 5 Word.word)) :: 32 Word.word)) BranchType_UNKNOWN \<then> EndOfInstruction () )))))))))))))))" @@ -21124,7 +21324,7 @@ definition UnallocatedEncoding :: " unit \<Rightarrow>((register_value),(unit), (read_reg FPEXC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . write_reg FPEXC_ref - ((set_slice0 (( 32 :: int)::ii) (( 1 :: int)::ii) w__3 (( 29 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) + ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__3 (( 29 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) else return () ) \<then> and_boolM ((UsingAArch32 () )) (AArch32_GeneralExceptionsToAArch64 () \<bind> (\<lambda> (w__5 :: bool) . return ((\<not> w__5))))) \<bind> (\<lambda> (w__6 :: @@ -23405,12 +23605,12 @@ definition aarch64_memory_exclusive_single :: " AccType \<Rightarrow>('datasize BigEndian () \<bind> (\<lambda> (w__56 :: bool) . if w__56 then aset_X t - ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii))) :: 32 Word.word)) \<then> - aset_X t2 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii))) :: 32 Word.word)) \<then> + aset_X t2 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) else - aset_X t ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \<then> + aset_X t ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \<then> aset_X t2 - ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii))) :: 32 Word.word))))) + ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii))) :: 32 Word.word))))) else ((if (((address \<noteq> ((Align__1 address dbytes :: 64 Word.word))))) then (let iswrite = False in @@ -23500,12 +23700,12 @@ definition aarch64_memory_exclusive_single :: " AccType \<Rightarrow>('datasize BigEndian () \<bind> (\<lambda> (w__73 :: bool) . if w__73 then aset_X t - ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii))) :: 96 Word.word)) \<then> - aset_X t2 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii))) :: 96 Word.word)) \<then> + aset_X t2 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) else - aset_X t ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \<then> + aset_X t ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \<then> aset_X t2 - ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii))) :: 96 Word.word))))) + ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii))) :: 96 Word.word))))) else ((if (((address \<noteq> ((Align__1 address dbytes :: 64 Word.word))))) then (let iswrite = False in @@ -23934,12 +24134,12 @@ definition aarch64_memory_exclusive_pair :: " AccType \<Rightarrow>('datasize:: BigEndian () \<bind> (\<lambda> (w__56 :: bool) . if w__56 then aset_X t - ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii))) :: 32 Word.word)) \<then> - aset_X t2 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii))) :: 32 Word.word)) \<then> + aset_X t2 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) else - aset_X t ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \<then> + aset_X t ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \<then> aset_X t2 - ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii))) :: 32 Word.word))))) + ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 64 :: int)::ii))) :: 32 Word.word))))) else ((if (((address \<noteq> ((Align__1 address dbytes :: 64 Word.word))))) then (let iswrite = False in @@ -24029,12 +24229,12 @@ definition aarch64_memory_exclusive_pair :: " AccType \<Rightarrow>('datasize:: BigEndian () \<bind> (\<lambda> (w__73 :: bool) . if w__73 then aset_X t - ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii))) :: 96 Word.word)) \<then> - aset_X t2 ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii))) :: 96 Word.word)) \<then> + aset_X t2 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) else - aset_X t ((slice0 data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \<then> + aset_X t ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \<then> aset_X t2 - ((slice0 data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii))) :: 96 Word.word))))) + ((slice data (( 32 :: int)::ii) ((((- (( 32 :: int)::ii))) + (( 128 :: int)::ii))) :: 96 Word.word))))) else ((if (((address \<noteq> ((Align__1 address dbytes :: 64 Word.word))))) then (let iswrite = False in @@ -24227,13 +24427,13 @@ definition system_barriers_decode :: "(1)Word.word \<Rightarrow>(2)Word.word \< else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return MemBarrierOp_DMB else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then return MemBarrierOp_ISB else UnallocatedEncoding () \<then> return op1) \<bind> (\<lambda> (op1 :: MemBarrierOp) . - (let b__3 = ((slice0 CRm (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let b__3 = ((slice CRm (( 2 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in (let (domain1 :: MBReqDomain) = (if (((b__3 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then MBReqDomain_OuterShareable else if (((b__3 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then MBReqDomain_Nonshareable else if (((b__3 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then MBReqDomain_InnerShareable else MBReqDomain_FullSystem) in - (let b__7 = ((slice0 CRm (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let b__7 = ((slice CRm (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in (let ((domain1 :: MBReqDomain), (types1 :: MBReqTypes)) = (if (((b__7 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then (let (types1 :: MBReqTypes) = MBReqTypes_Reads in @@ -27093,7 +27293,7 @@ definition memory_single_simdfp_register_aarch64_memory_single_simdfp_register__ (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD else MemOp_STORE) in - (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in + (let (datasize :: ii) = (shl_int (( 8 :: int)::ii) scale) in aarch64_memory_single_simdfp_register acctype datasize extend_type m memop n postindex shift t wback))))))))))))))" @@ -27119,7 +27319,7 @@ definition memory_single_simdfp_immediate_unsigned_aarch64_memory_single_simdfp_ (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD else MemOp_STORE) in - (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in + (let (datasize :: ii) = (shl_int (( 8 :: int)::ii) scale) in aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t wback))))))))))))" @@ -27144,7 +27344,7 @@ definition memory_single_simdfp_immediate_signed_preidx_aarch64_memory_single_si (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD else MemOp_STORE) in - (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in + (let (datasize :: ii) = (shl_int (( 8 :: int)::ii) scale) in aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t wback)))))))))))" @@ -27169,7 +27369,7 @@ definition memory_single_simdfp_immediate_signed_postidx_aarch64_memory_single_s (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD else MemOp_STORE) in - (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in + (let (datasize :: ii) = (shl_int (( 8 :: int)::ii) scale) in aarch64_memory_single_simdfp_immediate_signed_postidx acctype datasize memop n offset postindex t wback)))))))))))" @@ -27194,7 +27394,7 @@ definition memory_single_simdfp_immediate_signed_offset_normal_aarch64_memory_si (if ((((vec_of_bits [access_vec_dec opc (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then MemOp_LOAD else MemOp_STORE) in - (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) scale) in + (let (datasize :: ii) = (shl_int (( 8 :: int)::ii) scale) in aarch64_memory_single_simdfp_immediate_signed_offset_normal acctype datasize memop n offset postindex t wback)))))))))))" @@ -30464,7 +30664,7 @@ definition memory_atomicops_st_decode :: "(2)Word.word \<Rightarrow>(1)Word.wor else return () )) \<then> ((let (n :: ii) = (Word.uint Rn) in (let (s :: ii) = (Word.uint Rs) in - (let (datasize :: ii) = (shl_int0 (( 8 :: int)::ii) ((Word.uint size1))) in + (let (datasize :: ii) = (shl_int (( 8 :: int)::ii) ((Word.uint size1))) in (let (regsize :: ii) = (if (((((ex_int datasize)) = (( 64 :: int)::ii)))) then (( 64 :: int)::ii) else (( 32 :: int)::ii)) in (let (ldacctype :: AccType) = AccType_ATOMICRW in (let (stacctype :: AccType) = @@ -31134,13 +31334,13 @@ definition float_convert_int_decode :: "(1)Word.word \<Rightarrow>(1)Word.word (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then return (( 32 :: int)::ii) else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then return (( 64 :: int)::ii) else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then - (if (((((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) \<noteq> (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word)))) then + (if (((((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) \<noteq> (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word)))) then UnallocatedEncoding () else return () ) \<then> return (( 128 :: int)::ii) else if ((HaveFP16Ext () )) then return (( 16 :: int)::ii) else UnallocatedEncoding () \<then> return fltsize) \<bind> (\<lambda> (fltsize :: ii) . - (let v__98 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (let v__98 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in (if (((((subrange_vec_dec v__98 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) then (let (rounding :: FPRounding) = (FPDecodeRounding rmode) in (let (unsigned :: bool) = @@ -31403,7 +31603,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word UnallocatedEncoding () else return () ) \<then> ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in - (let b__2 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (let b__2 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in (if (((b__2 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then (let (rounding :: FPRounding) = FPRounding_ZERO in (let (unsigned :: bool) = @@ -31436,7 +31636,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word UnallocatedEncoding () else return () ) \<then> ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in - (let b__6 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (let b__6 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in (if (((b__6 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then (let (rounding :: FPRounding) = FPRounding_ZERO in (let (unsigned :: bool) = @@ -31469,7 +31669,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word UnallocatedEncoding () else return () )) \<then> ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in - (let b__10 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (let b__10 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in (if (((b__10 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then (let (rounding :: FPRounding) = FPRounding_ZERO in (let (unsigned :: bool) = @@ -31502,7 +31702,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word UnallocatedEncoding () else return () ) \<then> ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in - (let b__14 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (let b__14 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in (if (((b__14 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then (let (rounding :: FPRounding) = FPRounding_ZERO in (let (unsigned :: bool) = @@ -31535,7 +31735,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word UnallocatedEncoding () else return () ) \<then> ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in - (let b__18 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (let b__18 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in (if (((b__18 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then (let (rounding :: FPRounding) = FPRounding_ZERO in (let (unsigned :: bool) = @@ -31568,7 +31768,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word UnallocatedEncoding () else return () ) \<then> ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in - (let b__22 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (let b__22 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in (if (((b__22 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then (let (rounding :: FPRounding) = FPRounding_ZERO in (let (unsigned :: bool) = @@ -31601,7 +31801,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word UnallocatedEncoding () else return () )) \<then> ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in - (let b__26 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (let b__26 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in (if (((b__26 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then (let (rounding :: FPRounding) = FPRounding_ZERO in (let (unsigned :: bool) = @@ -31634,7 +31834,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word UnallocatedEncoding () else return () ) \<then> ((let (fracbits :: ii) = ((( 64 :: int)::ii) - ((Word.uint scale))) in - (let b__30 = ((concat_vec ((slice0 opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in + (let b__30 = ((concat_vec ((slice opcode (( 1 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) rmode :: 4 Word.word)) in (if (((b__30 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) then (let (rounding :: FPRounding) = FPRounding_ZERO in (let (unsigned :: bool) = @@ -31742,7 +31942,7 @@ definition float_arithmetic_round_decode :: "(1)Word.word \<Rightarrow>(1)Word. undefined_FPRounding () \<bind> (\<lambda> (rounding :: FPRounding) . (let v__101 = rmode in (if (((((subrange_vec_dec v__101 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)))) then - (let (rounding :: FPRounding) = (FPDecodeRounding ((slice0 rmode (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) in + (let (rounding :: FPRounding) = (FPDecodeRounding ((slice rmode (( 0 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word))) in return (exact, rounding)) else if (((v__101 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then (let (rounding :: FPRounding) = FPRounding_TIEAWAY in @@ -32144,7 +32344,7 @@ definition AArch64_CheckForSMCUndefOrTrap :: "(16)Word.word \<Rightarrow>((regi ExceptionSyndrome Exception_MonitorCall \<bind> (\<lambda> (w__15 :: ExceptionRecord) . (let exception = w__15 in (let (tmp_40 :: 25 bits) = ((ExceptionRecord_syndrome exception)) in - (let tmp_40 = ((set_slice0 (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_40 (( 0 :: int)::ii) imm :: 25 Word.word)) in + (let tmp_40 = ((set_slice (( 25 :: int)::ii) (( 16 :: int)::ii) tmp_40 (( 0 :: int)::ii) imm :: 25 Word.word)) in (let exception = ((exception (| ExceptionRecord_syndrome := tmp_40 |))) in AArch64_TakeException EL2 exception preferred_exception_return vect_offset))))))) else return () ))))))" @@ -33153,7 +33353,7 @@ definition DecodeBitMasks :: " int \<Rightarrow>(1)Word.word \<Rightarrow>(6)Wo ((assert_exp ((len \<ge> (( 0 :: int)::ii))) ('''') \<then> (if ((len < (( 1 :: int)::ii))) then ReservedValue () else return () )) \<then> - assert_exp ((M__tv \<ge> ((ex_int ((shl_int0 (( 1 :: int)::ii) len)))))) (''(M >= (1 << len))'')) \<then> + assert_exp ((M__tv \<ge> ((ex_int ((shl_int (( 1 :: int)::ii) len)))))) (''(M >= (1 << len))'')) \<then> ((let levels = ((zext_ones (( 6 :: int)::ii) len :: 6 Word.word)) in (if (((immediate \<and> (((((and_vec imms levels :: 6 Word.word)) = levels)))))) then ReservedValue () @@ -33401,7 +33601,7 @@ definition DecodeBitMasks :: " int \<Rightarrow>(1)Word.word \<Rightarrow>(6)Wo (if (((((GetSlice_int ((make_the_value (( 1 :: int)::ii) :: 1 itself)) diff (( 6 :: int)::ii) :: 1 Word.word)) \<noteq> (vec_of_bits [B0] :: 1 Word.word)))) then (and_vec wmask tmask :: 64 Word.word) else (or_vec wmask tmask :: 64 Word.word)) in - return ((slice0 wmask (( 0 :: int)::ii) M__tv :: ( 'M::len)Word.word), (slice0 tmask (( 0 :: int)::ii) M__tv :: ( 'M::len)Word.word))))))))))))))))))))))))))))))))))))" + return ((slice wmask (( 0 :: int)::ii) M__tv :: ( 'M::len)Word.word), (slice tmask (( 0 :: int)::ii) M__tv :: ( 'M::len)Word.word))))))))))))))))))))))))))))))))))))" (*val integer_logical_immediate_decode : mword ty1 -> mword ty2 -> mword ty1 -> mword ty6 -> mword ty6 -> mword ty5 -> mword ty5 -> M unit*) @@ -34546,56 +34746,6 @@ definition decode :: "(32)Word.word \<Rightarrow>((register_value),(unit),(exce integer_arithmetic_div_decode sf op1 S Rm opcode2 o1 Rn Rd)))))))))" -(*val fetch_and_execute : unit -> M unit*) - -definition fetch_and_execute :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " fetch_and_execute _ = ( - (whileM () - (\<lambda> unit_var . return True) - (\<lambda> unit_var . - (try_catch ((read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (aget_Mem w__0 (( 4 :: int)::ii) AccType_IFETCH :: ( 32 Word.word) M) \<bind> (\<lambda> instr . - decode instr))) (\<lambda>x . - (case x of - Error_Undefined _ => exit0 () - | Error_See s => - if(s = (''HINT'')) then (return () ) else (exit0 () ) - | Error_Implementation_Defined _ => exit0 () - | Error_ReservedEncoding _ => exit0 () - | Error_ExceptionTaken _ => exit0 () - )) \<then> - read_reg BranchTaken_ref) \<bind> (\<lambda> (w__1 :: bool) . - if w__1 then write_reg BranchTaken_ref False - else - (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . - write_reg PC_ref ((add_vec_int w__2 (( 4 :: int)::ii) :: 64 Word.word)))))))" - - -(*val main : unit -> M unit*) - -definition main :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " main _ = ( - (write_reg - PC_ref - ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((elf_entry () )) (( 0 :: int)::ii) - :: 64 Word.word)) \<then> - (ZeroExtend__0 (vec_of_bits [B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word) - ((make_the_value (( 64 :: int)::ii) :: 64 itself)) - :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__0 :: 64 bits) . - (write_reg SP_EL0_ref w__0 \<then> - read_reg PSTATE_ref) \<bind> (\<lambda> (w__1 :: ProcState) . - (write_reg PSTATE_ref (w__1 (| ProcState_D := ((vec_of_bits [B1] :: 1 Word.word))|)) \<then> - read_reg PSTATE_ref) \<bind> (\<lambda> (w__2 :: ProcState) . - (write_reg PSTATE_ref (w__2 (| ProcState_A := ((vec_of_bits [B1] :: 1 Word.word))|)) \<then> - read_reg PSTATE_ref) \<bind> (\<lambda> (w__3 :: ProcState) . - (write_reg PSTATE_ref (w__3 (| ProcState_I := ((vec_of_bits [B1] :: 1 Word.word))|)) \<then> - read_reg PSTATE_ref) \<bind> (\<lambda> (w__4 :: ProcState) . - (write_reg PSTATE_ref (w__4 (| ProcState_F := ((vec_of_bits [B1] :: 1 Word.word))|)) \<then> - (ZeroExtend__0 (vec_of_bits [B1,B0] :: 2 Word.word) ((make_the_value (( 32 :: int)::ii) :: 32 itself)) - :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__5 :: 32 bits) . - (write_reg OSLSR_EL1_ref w__5 \<then> write_reg BranchTaken_ref False) \<then> fetch_and_execute () )))))))" - - (*val initialize_registers : unit -> M unit*) definition initialize_registers :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where diff --git a/snapshots/isabelle/aarch64/Aarch64_lemmas.thy b/snapshots/isabelle/aarch64/Aarch64_lemmas.thy index 5a06d97e..5cd63a99 100644 --- a/snapshots/isabelle/aarch64/Aarch64_lemmas.thy +++ b/snapshots/isabelle/aarch64/Aarch64_lemmas.thy @@ -1,11 +1,11 @@ theory Aarch64_lemmas imports - Sail.Sail_values_lemmas - Sail.State_lemmas + Sail.Sail2_values_lemmas + Sail.Sail2_state_lemmas Aarch64 begin -abbreviation "liftS \<equiv> liftState (get_regval, set_regval)" +abbreviation liftS ("\<lbrakk>_\<rbrakk>\<^sub>S") where "liftS \<equiv> liftState (get_regval, set_regval)" lemmas register_defs = get_regval_def set_regval_def APDAKeyHi_EL1_ref_def APDAKeyLo_EL1_ref_def APDBKeyHi_EL1_ref_def APDBKeyLo_EL1_ref_def APGAKeyHi_EL1_ref_def APGAKeyLo_EL1_ref_def @@ -80,996 +80,1009 @@ proof - then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def) qed -lemma liftS_read_reg_APDAKeyHi_EL1[simp]: - "liftS (read_reg APDAKeyHi_EL1_ref) = readS (APDAKeyHi_EL1 \<circ> regstate)" +lemma option_of_rv_rv_of_option[simp]: + assumes "\<And>v. of_rv (rv_of v) = Some v" + shows "option_of_regval of_rv (regval_of_option rv_of v) = Some v" + using assms by (cases v) (auto simp: option_of_regval_def regval_of_option_def) + +lemma list_of_rv_rv_of_list[simp]: + assumes "\<And>v. of_rv (rv_of v) = Some v" + shows "list_of_regval of_rv (regval_of_list rv_of v) = Some v" +proof - + from assms have "of_rv \<circ> rv_of = Some" by auto + with assms show ?thesis by (induction v) (auto simp: list_of_regval_def regval_of_list_def) +qed + +lemma liftS_read_reg_APDAKeyHi_EL1[liftState_simp]: + "\<lbrakk>read_reg APDAKeyHi_EL1_ref\<rbrakk>\<^sub>S = readS (APDAKeyHi_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_APDAKeyHi_EL1[simp]: - "liftS (write_reg APDAKeyHi_EL1_ref v) = updateS (regstate_update (APDAKeyHi_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_APDAKeyHi_EL1[liftState_simp]: + "\<lbrakk>write_reg APDAKeyHi_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APDAKeyHi_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_APDAKeyLo_EL1[simp]: - "liftS (read_reg APDAKeyLo_EL1_ref) = readS (APDAKeyLo_EL1 \<circ> regstate)" +lemma liftS_read_reg_APDAKeyLo_EL1[liftState_simp]: + "\<lbrakk>read_reg APDAKeyLo_EL1_ref\<rbrakk>\<^sub>S = readS (APDAKeyLo_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_APDAKeyLo_EL1[simp]: - "liftS (write_reg APDAKeyLo_EL1_ref v) = updateS (regstate_update (APDAKeyLo_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_APDAKeyLo_EL1[liftState_simp]: + "\<lbrakk>write_reg APDAKeyLo_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APDAKeyLo_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_APDBKeyHi_EL1[simp]: - "liftS (read_reg APDBKeyHi_EL1_ref) = readS (APDBKeyHi_EL1 \<circ> regstate)" +lemma liftS_read_reg_APDBKeyHi_EL1[liftState_simp]: + "\<lbrakk>read_reg APDBKeyHi_EL1_ref\<rbrakk>\<^sub>S = readS (APDBKeyHi_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_APDBKeyHi_EL1[simp]: - "liftS (write_reg APDBKeyHi_EL1_ref v) = updateS (regstate_update (APDBKeyHi_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_APDBKeyHi_EL1[liftState_simp]: + "\<lbrakk>write_reg APDBKeyHi_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APDBKeyHi_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_APDBKeyLo_EL1[simp]: - "liftS (read_reg APDBKeyLo_EL1_ref) = readS (APDBKeyLo_EL1 \<circ> regstate)" +lemma liftS_read_reg_APDBKeyLo_EL1[liftState_simp]: + "\<lbrakk>read_reg APDBKeyLo_EL1_ref\<rbrakk>\<^sub>S = readS (APDBKeyLo_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_APDBKeyLo_EL1[simp]: - "liftS (write_reg APDBKeyLo_EL1_ref v) = updateS (regstate_update (APDBKeyLo_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_APDBKeyLo_EL1[liftState_simp]: + "\<lbrakk>write_reg APDBKeyLo_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APDBKeyLo_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_APGAKeyHi_EL1[simp]: - "liftS (read_reg APGAKeyHi_EL1_ref) = readS (APGAKeyHi_EL1 \<circ> regstate)" +lemma liftS_read_reg_APGAKeyHi_EL1[liftState_simp]: + "\<lbrakk>read_reg APGAKeyHi_EL1_ref\<rbrakk>\<^sub>S = readS (APGAKeyHi_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_APGAKeyHi_EL1[simp]: - "liftS (write_reg APGAKeyHi_EL1_ref v) = updateS (regstate_update (APGAKeyHi_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_APGAKeyHi_EL1[liftState_simp]: + "\<lbrakk>write_reg APGAKeyHi_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APGAKeyHi_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_APGAKeyLo_EL1[simp]: - "liftS (read_reg APGAKeyLo_EL1_ref) = readS (APGAKeyLo_EL1 \<circ> regstate)" +lemma liftS_read_reg_APGAKeyLo_EL1[liftState_simp]: + "\<lbrakk>read_reg APGAKeyLo_EL1_ref\<rbrakk>\<^sub>S = readS (APGAKeyLo_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_APGAKeyLo_EL1[simp]: - "liftS (write_reg APGAKeyLo_EL1_ref v) = updateS (regstate_update (APGAKeyLo_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_APGAKeyLo_EL1[liftState_simp]: + "\<lbrakk>write_reg APGAKeyLo_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APGAKeyLo_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_APIAKeyHi_EL1[simp]: - "liftS (read_reg APIAKeyHi_EL1_ref) = readS (APIAKeyHi_EL1 \<circ> regstate)" +lemma liftS_read_reg_APIAKeyHi_EL1[liftState_simp]: + "\<lbrakk>read_reg APIAKeyHi_EL1_ref\<rbrakk>\<^sub>S = readS (APIAKeyHi_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_APIAKeyHi_EL1[simp]: - "liftS (write_reg APIAKeyHi_EL1_ref v) = updateS (regstate_update (APIAKeyHi_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_APIAKeyHi_EL1[liftState_simp]: + "\<lbrakk>write_reg APIAKeyHi_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APIAKeyHi_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_APIAKeyLo_EL1[simp]: - "liftS (read_reg APIAKeyLo_EL1_ref) = readS (APIAKeyLo_EL1 \<circ> regstate)" +lemma liftS_read_reg_APIAKeyLo_EL1[liftState_simp]: + "\<lbrakk>read_reg APIAKeyLo_EL1_ref\<rbrakk>\<^sub>S = readS (APIAKeyLo_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_APIAKeyLo_EL1[simp]: - "liftS (write_reg APIAKeyLo_EL1_ref v) = updateS (regstate_update (APIAKeyLo_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_APIAKeyLo_EL1[liftState_simp]: + "\<lbrakk>write_reg APIAKeyLo_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APIAKeyLo_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_APIBKeyHi_EL1[simp]: - "liftS (read_reg APIBKeyHi_EL1_ref) = readS (APIBKeyHi_EL1 \<circ> regstate)" +lemma liftS_read_reg_APIBKeyHi_EL1[liftState_simp]: + "\<lbrakk>read_reg APIBKeyHi_EL1_ref\<rbrakk>\<^sub>S = readS (APIBKeyHi_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_APIBKeyHi_EL1[simp]: - "liftS (write_reg APIBKeyHi_EL1_ref v) = updateS (regstate_update (APIBKeyHi_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_APIBKeyHi_EL1[liftState_simp]: + "\<lbrakk>write_reg APIBKeyHi_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APIBKeyHi_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_APIBKeyLo_EL1[simp]: - "liftS (read_reg APIBKeyLo_EL1_ref) = readS (APIBKeyLo_EL1 \<circ> regstate)" +lemma liftS_read_reg_APIBKeyLo_EL1[liftState_simp]: + "\<lbrakk>read_reg APIBKeyLo_EL1_ref\<rbrakk>\<^sub>S = readS (APIBKeyLo_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_APIBKeyLo_EL1[simp]: - "liftS (write_reg APIBKeyLo_EL1_ref v) = updateS (regstate_update (APIBKeyLo_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_APIBKeyLo_EL1[liftState_simp]: + "\<lbrakk>write_reg APIBKeyLo_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (APIBKeyLo_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CONTEXTIDR_EL1[simp]: - "liftS (read_reg CONTEXTIDR_EL1_ref) = readS (CONTEXTIDR_EL1 \<circ> regstate)" +lemma liftS_read_reg_CONTEXTIDR_EL1[liftState_simp]: + "\<lbrakk>read_reg CONTEXTIDR_EL1_ref\<rbrakk>\<^sub>S = readS (CONTEXTIDR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CONTEXTIDR_EL1[simp]: - "liftS (write_reg CONTEXTIDR_EL1_ref v) = updateS (regstate_update (CONTEXTIDR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_CONTEXTIDR_EL1[liftState_simp]: + "\<lbrakk>write_reg CONTEXTIDR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CONTEXTIDR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CONTEXTIDR_EL2[simp]: - "liftS (read_reg CONTEXTIDR_EL2_ref) = readS (CONTEXTIDR_EL2 \<circ> regstate)" +lemma liftS_read_reg_CONTEXTIDR_EL2[liftState_simp]: + "\<lbrakk>read_reg CONTEXTIDR_EL2_ref\<rbrakk>\<^sub>S = readS (CONTEXTIDR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CONTEXTIDR_EL2[simp]: - "liftS (write_reg CONTEXTIDR_EL2_ref v) = updateS (regstate_update (CONTEXTIDR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_CONTEXTIDR_EL2[liftState_simp]: + "\<lbrakk>write_reg CONTEXTIDR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CONTEXTIDR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CPACR_EL1[simp]: - "liftS (read_reg CPACR_EL1_ref) = readS (CPACR_EL1 \<circ> regstate)" +lemma liftS_read_reg_CPACR_EL1[liftState_simp]: + "\<lbrakk>read_reg CPACR_EL1_ref\<rbrakk>\<^sub>S = readS (CPACR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CPACR_EL1[simp]: - "liftS (write_reg CPACR_EL1_ref v) = updateS (regstate_update (CPACR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_CPACR_EL1[liftState_simp]: + "\<lbrakk>write_reg CPACR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CPACR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CPTR_EL2[simp]: - "liftS (read_reg CPTR_EL2_ref) = readS (CPTR_EL2 \<circ> regstate)" +lemma liftS_read_reg_CPTR_EL2[liftState_simp]: + "\<lbrakk>read_reg CPTR_EL2_ref\<rbrakk>\<^sub>S = readS (CPTR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CPTR_EL2[simp]: - "liftS (write_reg CPTR_EL2_ref v) = updateS (regstate_update (CPTR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_CPTR_EL2[liftState_simp]: + "\<lbrakk>write_reg CPTR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CPTR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CPTR_EL3[simp]: - "liftS (read_reg CPTR_EL3_ref) = readS (CPTR_EL3 \<circ> regstate)" +lemma liftS_read_reg_CPTR_EL3[liftState_simp]: + "\<lbrakk>read_reg CPTR_EL3_ref\<rbrakk>\<^sub>S = readS (CPTR_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CPTR_EL3[simp]: - "liftS (write_reg CPTR_EL3_ref v) = updateS (regstate_update (CPTR_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_CPTR_EL3[liftState_simp]: + "\<lbrakk>write_reg CPTR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CPTR_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DBGBCR_EL1[simp]: - "liftS (read_reg DBGBCR_EL1_ref) = readS (DBGBCR_EL1 \<circ> regstate)" +lemma liftS_read_reg_DBGBCR_EL1[liftState_simp]: + "\<lbrakk>read_reg DBGBCR_EL1_ref\<rbrakk>\<^sub>S = readS (DBGBCR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DBGBCR_EL1[simp]: - "liftS (write_reg DBGBCR_EL1_ref v) = updateS (regstate_update (DBGBCR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_DBGBCR_EL1[liftState_simp]: + "\<lbrakk>write_reg DBGBCR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGBCR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DBGBVR_EL1[simp]: - "liftS (read_reg DBGBVR_EL1_ref) = readS (DBGBVR_EL1 \<circ> regstate)" +lemma liftS_read_reg_DBGBVR_EL1[liftState_simp]: + "\<lbrakk>read_reg DBGBVR_EL1_ref\<rbrakk>\<^sub>S = readS (DBGBVR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DBGBVR_EL1[simp]: - "liftS (write_reg DBGBVR_EL1_ref v) = updateS (regstate_update (DBGBVR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_DBGBVR_EL1[liftState_simp]: + "\<lbrakk>write_reg DBGBVR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGBVR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DBGEN[simp]: - "liftS (read_reg DBGEN_ref) = readS (DBGEN \<circ> regstate)" +lemma liftS_read_reg_DBGEN[liftState_simp]: + "\<lbrakk>read_reg DBGEN_ref\<rbrakk>\<^sub>S = readS (DBGEN \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DBGEN[simp]: - "liftS (write_reg DBGEN_ref v) = updateS (regstate_update (DBGEN_update (\<lambda>_. v)))" +lemma liftS_write_reg_DBGEN[liftState_simp]: + "\<lbrakk>write_reg DBGEN_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGEN_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DBGOSDLR[simp]: - "liftS (read_reg DBGOSDLR_ref) = readS (DBGOSDLR \<circ> regstate)" +lemma liftS_read_reg_DBGOSDLR[liftState_simp]: + "\<lbrakk>read_reg DBGOSDLR_ref\<rbrakk>\<^sub>S = readS (DBGOSDLR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DBGOSDLR[simp]: - "liftS (write_reg DBGOSDLR_ref v) = updateS (regstate_update (DBGOSDLR_update (\<lambda>_. v)))" +lemma liftS_write_reg_DBGOSDLR[liftState_simp]: + "\<lbrakk>write_reg DBGOSDLR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGOSDLR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DBGOSLSR[simp]: - "liftS (read_reg DBGOSLSR_ref) = readS (DBGOSLSR \<circ> regstate)" +lemma liftS_read_reg_DBGOSLSR[liftState_simp]: + "\<lbrakk>read_reg DBGOSLSR_ref\<rbrakk>\<^sub>S = readS (DBGOSLSR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DBGOSLSR[simp]: - "liftS (write_reg DBGOSLSR_ref v) = updateS (regstate_update (DBGOSLSR_update (\<lambda>_. v)))" +lemma liftS_write_reg_DBGOSLSR[liftState_simp]: + "\<lbrakk>write_reg DBGOSLSR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGOSLSR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DBGPRCR[simp]: - "liftS (read_reg DBGPRCR_ref) = readS (DBGPRCR \<circ> regstate)" +lemma liftS_read_reg_DBGPRCR[liftState_simp]: + "\<lbrakk>read_reg DBGPRCR_ref\<rbrakk>\<^sub>S = readS (DBGPRCR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DBGPRCR[simp]: - "liftS (write_reg DBGPRCR_ref v) = updateS (regstate_update (DBGPRCR_update (\<lambda>_. v)))" +lemma liftS_write_reg_DBGPRCR[liftState_simp]: + "\<lbrakk>write_reg DBGPRCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGPRCR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DBGPRCR_EL1[simp]: - "liftS (read_reg DBGPRCR_EL1_ref) = readS (DBGPRCR_EL1 \<circ> regstate)" +lemma liftS_read_reg_DBGPRCR_EL1[liftState_simp]: + "\<lbrakk>read_reg DBGPRCR_EL1_ref\<rbrakk>\<^sub>S = readS (DBGPRCR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DBGPRCR_EL1[simp]: - "liftS (write_reg DBGPRCR_EL1_ref v) = updateS (regstate_update (DBGPRCR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_DBGPRCR_EL1[liftState_simp]: + "\<lbrakk>write_reg DBGPRCR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGPRCR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DBGWCR_EL1[simp]: - "liftS (read_reg DBGWCR_EL1_ref) = readS (DBGWCR_EL1 \<circ> regstate)" +lemma liftS_read_reg_DBGWCR_EL1[liftState_simp]: + "\<lbrakk>read_reg DBGWCR_EL1_ref\<rbrakk>\<^sub>S = readS (DBGWCR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DBGWCR_EL1[simp]: - "liftS (write_reg DBGWCR_EL1_ref v) = updateS (regstate_update (DBGWCR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_DBGWCR_EL1[liftState_simp]: + "\<lbrakk>write_reg DBGWCR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGWCR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DBGWVR_EL1[simp]: - "liftS (read_reg DBGWVR_EL1_ref) = readS (DBGWVR_EL1 \<circ> regstate)" +lemma liftS_read_reg_DBGWVR_EL1[liftState_simp]: + "\<lbrakk>read_reg DBGWVR_EL1_ref\<rbrakk>\<^sub>S = readS (DBGWVR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DBGWVR_EL1[simp]: - "liftS (write_reg DBGWVR_EL1_ref v) = updateS (regstate_update (DBGWVR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_DBGWVR_EL1[liftState_simp]: + "\<lbrakk>write_reg DBGWVR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DBGWVR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DLR[simp]: - "liftS (read_reg DLR_ref) = readS (DLR \<circ> regstate)" +lemma liftS_read_reg_DLR[liftState_simp]: + "\<lbrakk>read_reg DLR_ref\<rbrakk>\<^sub>S = readS (DLR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DLR[simp]: - "liftS (write_reg DLR_ref v) = updateS (regstate_update (DLR_update (\<lambda>_. v)))" +lemma liftS_write_reg_DLR[liftState_simp]: + "\<lbrakk>write_reg DLR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DLR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DLR_EL0[simp]: - "liftS (read_reg DLR_EL0_ref) = readS (DLR_EL0 \<circ> regstate)" +lemma liftS_read_reg_DLR_EL0[liftState_simp]: + "\<lbrakk>read_reg DLR_EL0_ref\<rbrakk>\<^sub>S = readS (DLR_EL0 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DLR_EL0[simp]: - "liftS (write_reg DLR_EL0_ref v) = updateS (regstate_update (DLR_EL0_update (\<lambda>_. v)))" +lemma liftS_write_reg_DLR_EL0[liftState_simp]: + "\<lbrakk>write_reg DLR_EL0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DLR_EL0_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DSPSR[simp]: - "liftS (read_reg DSPSR_ref) = readS (DSPSR \<circ> regstate)" +lemma liftS_read_reg_DSPSR[liftState_simp]: + "\<lbrakk>read_reg DSPSR_ref\<rbrakk>\<^sub>S = readS (DSPSR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DSPSR[simp]: - "liftS (write_reg DSPSR_ref v) = updateS (regstate_update (DSPSR_update (\<lambda>_. v)))" +lemma liftS_write_reg_DSPSR[liftState_simp]: + "\<lbrakk>write_reg DSPSR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DSPSR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_DSPSR_EL0[simp]: - "liftS (read_reg DSPSR_EL0_ref) = readS (DSPSR_EL0 \<circ> regstate)" +lemma liftS_read_reg_DSPSR_EL0[liftState_simp]: + "\<lbrakk>read_reg DSPSR_EL0_ref\<rbrakk>\<^sub>S = readS (DSPSR_EL0 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_DSPSR_EL0[simp]: - "liftS (write_reg DSPSR_EL0_ref v) = updateS (regstate_update (DSPSR_EL0_update (\<lambda>_. v)))" +lemma liftS_write_reg_DSPSR_EL0[liftState_simp]: + "\<lbrakk>write_reg DSPSR_EL0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DSPSR_EL0_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_EDSCR[simp]: - "liftS (read_reg EDSCR_ref) = readS (EDSCR \<circ> regstate)" +lemma liftS_read_reg_EDSCR[liftState_simp]: + "\<lbrakk>read_reg EDSCR_ref\<rbrakk>\<^sub>S = readS (EDSCR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_EDSCR[simp]: - "liftS (write_reg EDSCR_ref v) = updateS (regstate_update (EDSCR_update (\<lambda>_. v)))" +lemma liftS_write_reg_EDSCR[liftState_simp]: + "\<lbrakk>write_reg EDSCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (EDSCR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_ELR_EL1[simp]: - "liftS (read_reg ELR_EL1_ref) = readS (ELR_EL1 \<circ> regstate)" +lemma liftS_read_reg_ELR_EL1[liftState_simp]: + "\<lbrakk>read_reg ELR_EL1_ref\<rbrakk>\<^sub>S = readS (ELR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_ELR_EL1[simp]: - "liftS (write_reg ELR_EL1_ref v) = updateS (regstate_update (ELR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_ELR_EL1[liftState_simp]: + "\<lbrakk>write_reg ELR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ELR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_ELR_EL2[simp]: - "liftS (read_reg ELR_EL2_ref) = readS (ELR_EL2 \<circ> regstate)" +lemma liftS_read_reg_ELR_EL2[liftState_simp]: + "\<lbrakk>read_reg ELR_EL2_ref\<rbrakk>\<^sub>S = readS (ELR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_ELR_EL2[simp]: - "liftS (write_reg ELR_EL2_ref v) = updateS (regstate_update (ELR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_ELR_EL2[liftState_simp]: + "\<lbrakk>write_reg ELR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ELR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_ELR_EL3[simp]: - "liftS (read_reg ELR_EL3_ref) = readS (ELR_EL3 \<circ> regstate)" +lemma liftS_read_reg_ELR_EL3[liftState_simp]: + "\<lbrakk>read_reg ELR_EL3_ref\<rbrakk>\<^sub>S = readS (ELR_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_ELR_EL3[simp]: - "liftS (write_reg ELR_EL3_ref v) = updateS (regstate_update (ELR_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_ELR_EL3[liftState_simp]: + "\<lbrakk>write_reg ELR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ELR_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_ELR_hyp[simp]: - "liftS (read_reg ELR_hyp_ref) = readS (ELR_hyp \<circ> regstate)" +lemma liftS_read_reg_ELR_hyp[liftState_simp]: + "\<lbrakk>read_reg ELR_hyp_ref\<rbrakk>\<^sub>S = readS (ELR_hyp \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_ELR_hyp[simp]: - "liftS (write_reg ELR_hyp_ref v) = updateS (regstate_update (ELR_hyp_update (\<lambda>_. v)))" +lemma liftS_write_reg_ELR_hyp[liftState_simp]: + "\<lbrakk>write_reg ELR_hyp_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ELR_hyp_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_ESR_EL1[simp]: - "liftS (read_reg ESR_EL1_ref) = readS (ESR_EL1 \<circ> regstate)" +lemma liftS_read_reg_ESR_EL1[liftState_simp]: + "\<lbrakk>read_reg ESR_EL1_ref\<rbrakk>\<^sub>S = readS (ESR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_ESR_EL1[simp]: - "liftS (write_reg ESR_EL1_ref v) = updateS (regstate_update (ESR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_ESR_EL1[liftState_simp]: + "\<lbrakk>write_reg ESR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ESR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_ESR_EL2[simp]: - "liftS (read_reg ESR_EL2_ref) = readS (ESR_EL2 \<circ> regstate)" +lemma liftS_read_reg_ESR_EL2[liftState_simp]: + "\<lbrakk>read_reg ESR_EL2_ref\<rbrakk>\<^sub>S = readS (ESR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_ESR_EL2[simp]: - "liftS (write_reg ESR_EL2_ref v) = updateS (regstate_update (ESR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_ESR_EL2[liftState_simp]: + "\<lbrakk>write_reg ESR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ESR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_ESR_EL3[simp]: - "liftS (read_reg ESR_EL3_ref) = readS (ESR_EL3 \<circ> regstate)" +lemma liftS_read_reg_ESR_EL3[liftState_simp]: + "\<lbrakk>read_reg ESR_EL3_ref\<rbrakk>\<^sub>S = readS (ESR_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_ESR_EL3[simp]: - "liftS (write_reg ESR_EL3_ref v) = updateS (regstate_update (ESR_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_ESR_EL3[liftState_simp]: + "\<lbrakk>write_reg ESR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ESR_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_EventRegister[simp]: - "liftS (read_reg EventRegister_ref) = readS (EventRegister \<circ> regstate)" +lemma liftS_read_reg_EventRegister[liftState_simp]: + "\<lbrakk>read_reg EventRegister_ref\<rbrakk>\<^sub>S = readS (EventRegister \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_EventRegister[simp]: - "liftS (write_reg EventRegister_ref v) = updateS (regstate_update (EventRegister_update (\<lambda>_. v)))" +lemma liftS_write_reg_EventRegister[liftState_simp]: + "\<lbrakk>write_reg EventRegister_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (EventRegister_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_FAR_EL1[simp]: - "liftS (read_reg FAR_EL1_ref) = readS (FAR_EL1 \<circ> regstate)" +lemma liftS_read_reg_FAR_EL1[liftState_simp]: + "\<lbrakk>read_reg FAR_EL1_ref\<rbrakk>\<^sub>S = readS (FAR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_FAR_EL1[simp]: - "liftS (write_reg FAR_EL1_ref v) = updateS (regstate_update (FAR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_FAR_EL1[liftState_simp]: + "\<lbrakk>write_reg FAR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FAR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_FAR_EL2[simp]: - "liftS (read_reg FAR_EL2_ref) = readS (FAR_EL2 \<circ> regstate)" +lemma liftS_read_reg_FAR_EL2[liftState_simp]: + "\<lbrakk>read_reg FAR_EL2_ref\<rbrakk>\<^sub>S = readS (FAR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_FAR_EL2[simp]: - "liftS (write_reg FAR_EL2_ref v) = updateS (regstate_update (FAR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_FAR_EL2[liftState_simp]: + "\<lbrakk>write_reg FAR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FAR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_FAR_EL3[simp]: - "liftS (read_reg FAR_EL3_ref) = readS (FAR_EL3 \<circ> regstate)" +lemma liftS_read_reg_FAR_EL3[liftState_simp]: + "\<lbrakk>read_reg FAR_EL3_ref\<rbrakk>\<^sub>S = readS (FAR_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_FAR_EL3[simp]: - "liftS (write_reg FAR_EL3_ref v) = updateS (regstate_update (FAR_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_FAR_EL3[liftState_simp]: + "\<lbrakk>write_reg FAR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FAR_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_FPCR[simp]: - "liftS (read_reg FPCR_ref) = readS (FPCR \<circ> regstate)" +lemma liftS_read_reg_FPCR[liftState_simp]: + "\<lbrakk>read_reg FPCR_ref\<rbrakk>\<^sub>S = readS (FPCR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_FPCR[simp]: - "liftS (write_reg FPCR_ref v) = updateS (regstate_update (FPCR_update (\<lambda>_. v)))" +lemma liftS_write_reg_FPCR[liftState_simp]: + "\<lbrakk>write_reg FPCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FPCR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_FPEXC[simp]: - "liftS (read_reg FPEXC_ref) = readS (FPEXC \<circ> regstate)" +lemma liftS_read_reg_FPEXC[liftState_simp]: + "\<lbrakk>read_reg FPEXC_ref\<rbrakk>\<^sub>S = readS (FPEXC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_FPEXC[simp]: - "liftS (write_reg FPEXC_ref v) = updateS (regstate_update (FPEXC_update (\<lambda>_. v)))" +lemma liftS_write_reg_FPEXC[liftState_simp]: + "\<lbrakk>write_reg FPEXC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FPEXC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_FPSCR[simp]: - "liftS (read_reg FPSCR_ref) = readS (FPSCR \<circ> regstate)" +lemma liftS_read_reg_FPSCR[liftState_simp]: + "\<lbrakk>read_reg FPSCR_ref\<rbrakk>\<^sub>S = readS (FPSCR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_FPSCR[simp]: - "liftS (write_reg FPSCR_ref v) = updateS (regstate_update (FPSCR_update (\<lambda>_. v)))" +lemma liftS_write_reg_FPSCR[liftState_simp]: + "\<lbrakk>write_reg FPSCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FPSCR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_FPSR[simp]: - "liftS (read_reg FPSR_ref) = readS (FPSR \<circ> regstate)" +lemma liftS_read_reg_FPSR[liftState_simp]: + "\<lbrakk>read_reg FPSR_ref\<rbrakk>\<^sub>S = readS (FPSR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_FPSR[simp]: - "liftS (write_reg FPSR_ref v) = updateS (regstate_update (FPSR_update (\<lambda>_. v)))" +lemma liftS_write_reg_FPSR[liftState_simp]: + "\<lbrakk>write_reg FPSR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (FPSR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_HCR[simp]: - "liftS (read_reg HCR_ref) = readS (HCR \<circ> regstate)" +lemma liftS_read_reg_HCR[liftState_simp]: + "\<lbrakk>read_reg HCR_ref\<rbrakk>\<^sub>S = readS (HCR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_HCR[simp]: - "liftS (write_reg HCR_ref v) = updateS (regstate_update (HCR_update (\<lambda>_. v)))" +lemma liftS_write_reg_HCR[liftState_simp]: + "\<lbrakk>write_reg HCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HCR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_HCR2[simp]: - "liftS (read_reg HCR2_ref) = readS (HCR2 \<circ> regstate)" +lemma liftS_read_reg_HCR2[liftState_simp]: + "\<lbrakk>read_reg HCR2_ref\<rbrakk>\<^sub>S = readS (HCR2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_HCR2[simp]: - "liftS (write_reg HCR2_ref v) = updateS (regstate_update (HCR2_update (\<lambda>_. v)))" +lemma liftS_write_reg_HCR2[liftState_simp]: + "\<lbrakk>write_reg HCR2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HCR2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_HCR_EL2[simp]: - "liftS (read_reg HCR_EL2_ref) = readS (HCR_EL2 \<circ> regstate)" +lemma liftS_read_reg_HCR_EL2[liftState_simp]: + "\<lbrakk>read_reg HCR_EL2_ref\<rbrakk>\<^sub>S = readS (HCR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_HCR_EL2[simp]: - "liftS (write_reg HCR_EL2_ref v) = updateS (regstate_update (HCR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_HCR_EL2[liftState_simp]: + "\<lbrakk>write_reg HCR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HCR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_HDCR[simp]: - "liftS (read_reg HDCR_ref) = readS (HDCR \<circ> regstate)" +lemma liftS_read_reg_HDCR[liftState_simp]: + "\<lbrakk>read_reg HDCR_ref\<rbrakk>\<^sub>S = readS (HDCR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_HDCR[simp]: - "liftS (write_reg HDCR_ref v) = updateS (regstate_update (HDCR_update (\<lambda>_. v)))" +lemma liftS_write_reg_HDCR[liftState_simp]: + "\<lbrakk>write_reg HDCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HDCR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_HDFAR[simp]: - "liftS (read_reg HDFAR_ref) = readS (HDFAR \<circ> regstate)" +lemma liftS_read_reg_HDFAR[liftState_simp]: + "\<lbrakk>read_reg HDFAR_ref\<rbrakk>\<^sub>S = readS (HDFAR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_HDFAR[simp]: - "liftS (write_reg HDFAR_ref v) = updateS (regstate_update (HDFAR_update (\<lambda>_. v)))" +lemma liftS_write_reg_HDFAR[liftState_simp]: + "\<lbrakk>write_reg HDFAR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HDFAR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_HIFAR[simp]: - "liftS (read_reg HIFAR_ref) = readS (HIFAR \<circ> regstate)" +lemma liftS_read_reg_HIFAR[liftState_simp]: + "\<lbrakk>read_reg HIFAR_ref\<rbrakk>\<^sub>S = readS (HIFAR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_HIFAR[simp]: - "liftS (write_reg HIFAR_ref v) = updateS (regstate_update (HIFAR_update (\<lambda>_. v)))" +lemma liftS_write_reg_HIFAR[liftState_simp]: + "\<lbrakk>write_reg HIFAR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HIFAR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_HPFAR[simp]: - "liftS (read_reg HPFAR_ref) = readS (HPFAR \<circ> regstate)" +lemma liftS_read_reg_HPFAR[liftState_simp]: + "\<lbrakk>read_reg HPFAR_ref\<rbrakk>\<^sub>S = readS (HPFAR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_HPFAR[simp]: - "liftS (write_reg HPFAR_ref v) = updateS (regstate_update (HPFAR_update (\<lambda>_. v)))" +lemma liftS_write_reg_HPFAR[liftState_simp]: + "\<lbrakk>write_reg HPFAR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HPFAR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_HPFAR_EL2[simp]: - "liftS (read_reg HPFAR_EL2_ref) = readS (HPFAR_EL2 \<circ> regstate)" +lemma liftS_read_reg_HPFAR_EL2[liftState_simp]: + "\<lbrakk>read_reg HPFAR_EL2_ref\<rbrakk>\<^sub>S = readS (HPFAR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_HPFAR_EL2[simp]: - "liftS (write_reg HPFAR_EL2_ref v) = updateS (regstate_update (HPFAR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_HPFAR_EL2[liftState_simp]: + "\<lbrakk>write_reg HPFAR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HPFAR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_HSCTLR[simp]: - "liftS (read_reg HSCTLR_ref) = readS (HSCTLR \<circ> regstate)" +lemma liftS_read_reg_HSCTLR[liftState_simp]: + "\<lbrakk>read_reg HSCTLR_ref\<rbrakk>\<^sub>S = readS (HSCTLR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_HSCTLR[simp]: - "liftS (write_reg HSCTLR_ref v) = updateS (regstate_update (HSCTLR_update (\<lambda>_. v)))" +lemma liftS_write_reg_HSCTLR[liftState_simp]: + "\<lbrakk>write_reg HSCTLR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HSCTLR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_HSR[simp]: - "liftS (read_reg HSR_ref) = readS (HSR \<circ> regstate)" +lemma liftS_read_reg_HSR[liftState_simp]: + "\<lbrakk>read_reg HSR_ref\<rbrakk>\<^sub>S = readS (HSR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_HSR[simp]: - "liftS (write_reg HSR_ref v) = updateS (regstate_update (HSR_update (\<lambda>_. v)))" +lemma liftS_write_reg_HSR[liftState_simp]: + "\<lbrakk>write_reg HSR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HSR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_HVBAR[simp]: - "liftS (read_reg HVBAR_ref) = readS (HVBAR \<circ> regstate)" +lemma liftS_read_reg_HVBAR[liftState_simp]: + "\<lbrakk>read_reg HVBAR_ref\<rbrakk>\<^sub>S = readS (HVBAR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_HVBAR[simp]: - "liftS (write_reg HVBAR_ref v) = updateS (regstate_update (HVBAR_update (\<lambda>_. v)))" +lemma liftS_write_reg_HVBAR[liftState_simp]: + "\<lbrakk>write_reg HVBAR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HVBAR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_ID_AA64DFR0_EL1[simp]: - "liftS (read_reg ID_AA64DFR0_EL1_ref) = readS (ID_AA64DFR0_EL1 \<circ> regstate)" +lemma liftS_read_reg_ID_AA64DFR0_EL1[liftState_simp]: + "\<lbrakk>read_reg ID_AA64DFR0_EL1_ref\<rbrakk>\<^sub>S = readS (ID_AA64DFR0_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_ID_AA64DFR0_EL1[simp]: - "liftS (write_reg ID_AA64DFR0_EL1_ref v) = updateS (regstate_update (ID_AA64DFR0_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_ID_AA64DFR0_EL1[liftState_simp]: + "\<lbrakk>write_reg ID_AA64DFR0_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ID_AA64DFR0_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_LR_mon[simp]: - "liftS (read_reg LR_mon_ref) = readS (LR_mon \<circ> regstate)" +lemma liftS_read_reg_LR_mon[liftState_simp]: + "\<lbrakk>read_reg LR_mon_ref\<rbrakk>\<^sub>S = readS (LR_mon \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_LR_mon[simp]: - "liftS (write_reg LR_mon_ref v) = updateS (regstate_update (LR_mon_update (\<lambda>_. v)))" +lemma liftS_write_reg_LR_mon[liftState_simp]: + "\<lbrakk>write_reg LR_mon_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (LR_mon_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_MAIR_EL1[simp]: - "liftS (read_reg MAIR_EL1_ref) = readS (MAIR_EL1 \<circ> regstate)" +lemma liftS_read_reg_MAIR_EL1[liftState_simp]: + "\<lbrakk>read_reg MAIR_EL1_ref\<rbrakk>\<^sub>S = readS (MAIR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_MAIR_EL1[simp]: - "liftS (write_reg MAIR_EL1_ref v) = updateS (regstate_update (MAIR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_MAIR_EL1[liftState_simp]: + "\<lbrakk>write_reg MAIR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (MAIR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_MAIR_EL2[simp]: - "liftS (read_reg MAIR_EL2_ref) = readS (MAIR_EL2 \<circ> regstate)" +lemma liftS_read_reg_MAIR_EL2[liftState_simp]: + "\<lbrakk>read_reg MAIR_EL2_ref\<rbrakk>\<^sub>S = readS (MAIR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_MAIR_EL2[simp]: - "liftS (write_reg MAIR_EL2_ref v) = updateS (regstate_update (MAIR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_MAIR_EL2[liftState_simp]: + "\<lbrakk>write_reg MAIR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (MAIR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_MAIR_EL3[simp]: - "liftS (read_reg MAIR_EL3_ref) = readS (MAIR_EL3 \<circ> regstate)" +lemma liftS_read_reg_MAIR_EL3[liftState_simp]: + "\<lbrakk>read_reg MAIR_EL3_ref\<rbrakk>\<^sub>S = readS (MAIR_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_MAIR_EL3[simp]: - "liftS (write_reg MAIR_EL3_ref v) = updateS (regstate_update (MAIR_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_MAIR_EL3[liftState_simp]: + "\<lbrakk>write_reg MAIR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (MAIR_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_MDCR_EL2[simp]: - "liftS (read_reg MDCR_EL2_ref) = readS (MDCR_EL2 \<circ> regstate)" +lemma liftS_read_reg_MDCR_EL2[liftState_simp]: + "\<lbrakk>read_reg MDCR_EL2_ref\<rbrakk>\<^sub>S = readS (MDCR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_MDCR_EL2[simp]: - "liftS (write_reg MDCR_EL2_ref v) = updateS (regstate_update (MDCR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_MDCR_EL2[liftState_simp]: + "\<lbrakk>write_reg MDCR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (MDCR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_MDCR_EL3[simp]: - "liftS (read_reg MDCR_EL3_ref) = readS (MDCR_EL3 \<circ> regstate)" +lemma liftS_read_reg_MDCR_EL3[liftState_simp]: + "\<lbrakk>read_reg MDCR_EL3_ref\<rbrakk>\<^sub>S = readS (MDCR_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_MDCR_EL3[simp]: - "liftS (write_reg MDCR_EL3_ref v) = updateS (regstate_update (MDCR_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_MDCR_EL3[liftState_simp]: + "\<lbrakk>write_reg MDCR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (MDCR_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_MDSCR_EL1[simp]: - "liftS (read_reg MDSCR_EL1_ref) = readS (MDSCR_EL1 \<circ> regstate)" +lemma liftS_read_reg_MDSCR_EL1[liftState_simp]: + "\<lbrakk>read_reg MDSCR_EL1_ref\<rbrakk>\<^sub>S = readS (MDSCR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_MDSCR_EL1[simp]: - "liftS (write_reg MDSCR_EL1_ref v) = updateS (regstate_update (MDSCR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_MDSCR_EL1[liftState_simp]: + "\<lbrakk>write_reg MDSCR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (MDSCR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_OSDLR_EL1[simp]: - "liftS (read_reg OSDLR_EL1_ref) = readS (OSDLR_EL1 \<circ> regstate)" +lemma liftS_read_reg_OSDLR_EL1[liftState_simp]: + "\<lbrakk>read_reg OSDLR_EL1_ref\<rbrakk>\<^sub>S = readS (OSDLR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_OSDLR_EL1[simp]: - "liftS (write_reg OSDLR_EL1_ref v) = updateS (regstate_update (OSDLR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_OSDLR_EL1[liftState_simp]: + "\<lbrakk>write_reg OSDLR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (OSDLR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_OSLSR_EL1[simp]: - "liftS (read_reg OSLSR_EL1_ref) = readS (OSLSR_EL1 \<circ> regstate)" +lemma liftS_read_reg_OSLSR_EL1[liftState_simp]: + "\<lbrakk>read_reg OSLSR_EL1_ref\<rbrakk>\<^sub>S = readS (OSLSR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_OSLSR_EL1[simp]: - "liftS (write_reg OSLSR_EL1_ref v) = updateS (regstate_update (OSLSR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_OSLSR_EL1[liftState_simp]: + "\<lbrakk>write_reg OSLSR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (OSLSR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_PSTATE[simp]: - "liftS (read_reg PSTATE_ref) = readS (PSTATE \<circ> regstate)" +lemma liftS_read_reg_PSTATE[liftState_simp]: + "\<lbrakk>read_reg PSTATE_ref\<rbrakk>\<^sub>S = readS (PSTATE \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_PSTATE[simp]: - "liftS (write_reg PSTATE_ref v) = updateS (regstate_update (PSTATE_update (\<lambda>_. v)))" +lemma liftS_write_reg_PSTATE[liftState_simp]: + "\<lbrakk>write_reg PSTATE_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PSTATE_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_RC[simp]: - "liftS (read_reg RC_ref) = readS (RC \<circ> regstate)" +lemma liftS_read_reg_RC[liftState_simp]: + "\<lbrakk>read_reg RC_ref\<rbrakk>\<^sub>S = readS (RC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_RC[simp]: - "liftS (write_reg RC_ref v) = updateS (regstate_update (RC_update (\<lambda>_. v)))" +lemma liftS_write_reg_RC[liftState_simp]: + "\<lbrakk>write_reg RC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (RC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_RVBAR_EL1[simp]: - "liftS (read_reg RVBAR_EL1_ref) = readS (RVBAR_EL1 \<circ> regstate)" +lemma liftS_read_reg_RVBAR_EL1[liftState_simp]: + "\<lbrakk>read_reg RVBAR_EL1_ref\<rbrakk>\<^sub>S = readS (RVBAR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_RVBAR_EL1[simp]: - "liftS (write_reg RVBAR_EL1_ref v) = updateS (regstate_update (RVBAR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_RVBAR_EL1[liftState_simp]: + "\<lbrakk>write_reg RVBAR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (RVBAR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_RVBAR_EL2[simp]: - "liftS (read_reg RVBAR_EL2_ref) = readS (RVBAR_EL2 \<circ> regstate)" +lemma liftS_read_reg_RVBAR_EL2[liftState_simp]: + "\<lbrakk>read_reg RVBAR_EL2_ref\<rbrakk>\<^sub>S = readS (RVBAR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_RVBAR_EL2[simp]: - "liftS (write_reg RVBAR_EL2_ref v) = updateS (regstate_update (RVBAR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_RVBAR_EL2[liftState_simp]: + "\<lbrakk>write_reg RVBAR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (RVBAR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_RVBAR_EL3[simp]: - "liftS (read_reg RVBAR_EL3_ref) = readS (RVBAR_EL3 \<circ> regstate)" +lemma liftS_read_reg_RVBAR_EL3[liftState_simp]: + "\<lbrakk>read_reg RVBAR_EL3_ref\<rbrakk>\<^sub>S = readS (RVBAR_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_RVBAR_EL3[simp]: - "liftS (write_reg RVBAR_EL3_ref v) = updateS (regstate_update (RVBAR_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_RVBAR_EL3[liftState_simp]: + "\<lbrakk>write_reg RVBAR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (RVBAR_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SCR[simp]: - "liftS (read_reg SCR_ref) = readS (SCR \<circ> regstate)" +lemma liftS_read_reg_SCR[liftState_simp]: + "\<lbrakk>read_reg SCR_ref\<rbrakk>\<^sub>S = readS (SCR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SCR[simp]: - "liftS (write_reg SCR_ref v) = updateS (regstate_update (SCR_update (\<lambda>_. v)))" +lemma liftS_write_reg_SCR[liftState_simp]: + "\<lbrakk>write_reg SCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SCR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SCR_EL3[simp]: - "liftS (read_reg SCR_EL3_ref) = readS (SCR_EL3 \<circ> regstate)" +lemma liftS_read_reg_SCR_EL3[liftState_simp]: + "\<lbrakk>read_reg SCR_EL3_ref\<rbrakk>\<^sub>S = readS (SCR_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SCR_EL3[simp]: - "liftS (write_reg SCR_EL3_ref v) = updateS (regstate_update (SCR_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_SCR_EL3[liftState_simp]: + "\<lbrakk>write_reg SCR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SCR_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SCTLR[simp]: - "liftS (read_reg SCTLR_ref) = readS (SCTLR \<circ> regstate)" +lemma liftS_read_reg_SCTLR[liftState_simp]: + "\<lbrakk>read_reg SCTLR_ref\<rbrakk>\<^sub>S = readS (SCTLR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SCTLR[simp]: - "liftS (write_reg SCTLR_ref v) = updateS (regstate_update (SCTLR_update (\<lambda>_. v)))" +lemma liftS_write_reg_SCTLR[liftState_simp]: + "\<lbrakk>write_reg SCTLR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SCTLR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SCTLR_EL1[simp]: - "liftS (read_reg SCTLR_EL1_ref) = readS (SCTLR_EL1 \<circ> regstate)" +lemma liftS_read_reg_SCTLR_EL1[liftState_simp]: + "\<lbrakk>read_reg SCTLR_EL1_ref\<rbrakk>\<^sub>S = readS (SCTLR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SCTLR_EL1[simp]: - "liftS (write_reg SCTLR_EL1_ref v) = updateS (regstate_update (SCTLR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_SCTLR_EL1[liftState_simp]: + "\<lbrakk>write_reg SCTLR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SCTLR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SCTLR_EL2[simp]: - "liftS (read_reg SCTLR_EL2_ref) = readS (SCTLR_EL2 \<circ> regstate)" +lemma liftS_read_reg_SCTLR_EL2[liftState_simp]: + "\<lbrakk>read_reg SCTLR_EL2_ref\<rbrakk>\<^sub>S = readS (SCTLR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SCTLR_EL2[simp]: - "liftS (write_reg SCTLR_EL2_ref v) = updateS (regstate_update (SCTLR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_SCTLR_EL2[liftState_simp]: + "\<lbrakk>write_reg SCTLR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SCTLR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SCTLR_EL3[simp]: - "liftS (read_reg SCTLR_EL3_ref) = readS (SCTLR_EL3 \<circ> regstate)" +lemma liftS_read_reg_SCTLR_EL3[liftState_simp]: + "\<lbrakk>read_reg SCTLR_EL3_ref\<rbrakk>\<^sub>S = readS (SCTLR_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SCTLR_EL3[simp]: - "liftS (write_reg SCTLR_EL3_ref v) = updateS (regstate_update (SCTLR_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_SCTLR_EL3[liftState_simp]: + "\<lbrakk>write_reg SCTLR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SCTLR_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SDCR[simp]: - "liftS (read_reg SDCR_ref) = readS (SDCR \<circ> regstate)" +lemma liftS_read_reg_SDCR[liftState_simp]: + "\<lbrakk>read_reg SDCR_ref\<rbrakk>\<^sub>S = readS (SDCR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SDCR[simp]: - "liftS (write_reg SDCR_ref v) = updateS (regstate_update (SDCR_update (\<lambda>_. v)))" +lemma liftS_write_reg_SDCR[liftState_simp]: + "\<lbrakk>write_reg SDCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SDCR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SDER[simp]: - "liftS (read_reg SDER_ref) = readS (SDER \<circ> regstate)" +lemma liftS_read_reg_SDER[liftState_simp]: + "\<lbrakk>read_reg SDER_ref\<rbrakk>\<^sub>S = readS (SDER \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SDER[simp]: - "liftS (write_reg SDER_ref v) = updateS (regstate_update (SDER_update (\<lambda>_. v)))" +lemma liftS_write_reg_SDER[liftState_simp]: + "\<lbrakk>write_reg SDER_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SDER_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SPIDEN[simp]: - "liftS (read_reg SPIDEN_ref) = readS (SPIDEN \<circ> regstate)" +lemma liftS_read_reg_SPIDEN[liftState_simp]: + "\<lbrakk>read_reg SPIDEN_ref\<rbrakk>\<^sub>S = readS (SPIDEN \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SPIDEN[simp]: - "liftS (write_reg SPIDEN_ref v) = updateS (regstate_update (SPIDEN_update (\<lambda>_. v)))" +lemma liftS_write_reg_SPIDEN[liftState_simp]: + "\<lbrakk>write_reg SPIDEN_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPIDEN_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SPSR_EL1[simp]: - "liftS (read_reg SPSR_EL1_ref) = readS (SPSR_EL1 \<circ> regstate)" +lemma liftS_read_reg_SPSR_EL1[liftState_simp]: + "\<lbrakk>read_reg SPSR_EL1_ref\<rbrakk>\<^sub>S = readS (SPSR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SPSR_EL1[simp]: - "liftS (write_reg SPSR_EL1_ref v) = updateS (regstate_update (SPSR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_SPSR_EL1[liftState_simp]: + "\<lbrakk>write_reg SPSR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SPSR_EL2[simp]: - "liftS (read_reg SPSR_EL2_ref) = readS (SPSR_EL2 \<circ> regstate)" +lemma liftS_read_reg_SPSR_EL2[liftState_simp]: + "\<lbrakk>read_reg SPSR_EL2_ref\<rbrakk>\<^sub>S = readS (SPSR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SPSR_EL2[simp]: - "liftS (write_reg SPSR_EL2_ref v) = updateS (regstate_update (SPSR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_SPSR_EL2[liftState_simp]: + "\<lbrakk>write_reg SPSR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SPSR_EL3[simp]: - "liftS (read_reg SPSR_EL3_ref) = readS (SPSR_EL3 \<circ> regstate)" +lemma liftS_read_reg_SPSR_EL3[liftState_simp]: + "\<lbrakk>read_reg SPSR_EL3_ref\<rbrakk>\<^sub>S = readS (SPSR_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SPSR_EL3[simp]: - "liftS (write_reg SPSR_EL3_ref v) = updateS (regstate_update (SPSR_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_SPSR_EL3[liftState_simp]: + "\<lbrakk>write_reg SPSR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SPSR_abt[simp]: - "liftS (read_reg SPSR_abt_ref) = readS (SPSR_abt \<circ> regstate)" +lemma liftS_read_reg_SPSR_abt[liftState_simp]: + "\<lbrakk>read_reg SPSR_abt_ref\<rbrakk>\<^sub>S = readS (SPSR_abt \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SPSR_abt[simp]: - "liftS (write_reg SPSR_abt_ref v) = updateS (regstate_update (SPSR_abt_update (\<lambda>_. v)))" +lemma liftS_write_reg_SPSR_abt[liftState_simp]: + "\<lbrakk>write_reg SPSR_abt_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_abt_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SPSR_fiq[simp]: - "liftS (read_reg SPSR_fiq_ref) = readS (SPSR_fiq \<circ> regstate)" +lemma liftS_read_reg_SPSR_fiq[liftState_simp]: + "\<lbrakk>read_reg SPSR_fiq_ref\<rbrakk>\<^sub>S = readS (SPSR_fiq \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SPSR_fiq[simp]: - "liftS (write_reg SPSR_fiq_ref v) = updateS (regstate_update (SPSR_fiq_update (\<lambda>_. v)))" +lemma liftS_write_reg_SPSR_fiq[liftState_simp]: + "\<lbrakk>write_reg SPSR_fiq_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_fiq_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SPSR_hyp[simp]: - "liftS (read_reg SPSR_hyp_ref) = readS (SPSR_hyp \<circ> regstate)" +lemma liftS_read_reg_SPSR_hyp[liftState_simp]: + "\<lbrakk>read_reg SPSR_hyp_ref\<rbrakk>\<^sub>S = readS (SPSR_hyp \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SPSR_hyp[simp]: - "liftS (write_reg SPSR_hyp_ref v) = updateS (regstate_update (SPSR_hyp_update (\<lambda>_. v)))" +lemma liftS_write_reg_SPSR_hyp[liftState_simp]: + "\<lbrakk>write_reg SPSR_hyp_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_hyp_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SPSR_irq[simp]: - "liftS (read_reg SPSR_irq_ref) = readS (SPSR_irq \<circ> regstate)" +lemma liftS_read_reg_SPSR_irq[liftState_simp]: + "\<lbrakk>read_reg SPSR_irq_ref\<rbrakk>\<^sub>S = readS (SPSR_irq \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SPSR_irq[simp]: - "liftS (write_reg SPSR_irq_ref v) = updateS (regstate_update (SPSR_irq_update (\<lambda>_. v)))" +lemma liftS_write_reg_SPSR_irq[liftState_simp]: + "\<lbrakk>write_reg SPSR_irq_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_irq_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SPSR_mon[simp]: - "liftS (read_reg SPSR_mon_ref) = readS (SPSR_mon \<circ> regstate)" +lemma liftS_read_reg_SPSR_mon[liftState_simp]: + "\<lbrakk>read_reg SPSR_mon_ref\<rbrakk>\<^sub>S = readS (SPSR_mon \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SPSR_mon[simp]: - "liftS (write_reg SPSR_mon_ref v) = updateS (regstate_update (SPSR_mon_update (\<lambda>_. v)))" +lemma liftS_write_reg_SPSR_mon[liftState_simp]: + "\<lbrakk>write_reg SPSR_mon_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_mon_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SPSR_svc[simp]: - "liftS (read_reg SPSR_svc_ref) = readS (SPSR_svc \<circ> regstate)" +lemma liftS_read_reg_SPSR_svc[liftState_simp]: + "\<lbrakk>read_reg SPSR_svc_ref\<rbrakk>\<^sub>S = readS (SPSR_svc \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SPSR_svc[simp]: - "liftS (write_reg SPSR_svc_ref v) = updateS (regstate_update (SPSR_svc_update (\<lambda>_. v)))" +lemma liftS_write_reg_SPSR_svc[liftState_simp]: + "\<lbrakk>write_reg SPSR_svc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_svc_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SPSR_und[simp]: - "liftS (read_reg SPSR_und_ref) = readS (SPSR_und \<circ> regstate)" +lemma liftS_read_reg_SPSR_und[liftState_simp]: + "\<lbrakk>read_reg SPSR_und_ref\<rbrakk>\<^sub>S = readS (SPSR_und \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SPSR_und[simp]: - "liftS (write_reg SPSR_und_ref v) = updateS (regstate_update (SPSR_und_update (\<lambda>_. v)))" +lemma liftS_write_reg_SPSR_und[liftState_simp]: + "\<lbrakk>write_reg SPSR_und_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SPSR_und_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SP_EL0[simp]: - "liftS (read_reg SP_EL0_ref) = readS (SP_EL0 \<circ> regstate)" +lemma liftS_read_reg_SP_EL0[liftState_simp]: + "\<lbrakk>read_reg SP_EL0_ref\<rbrakk>\<^sub>S = readS (SP_EL0 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SP_EL0[simp]: - "liftS (write_reg SP_EL0_ref v) = updateS (regstate_update (SP_EL0_update (\<lambda>_. v)))" +lemma liftS_write_reg_SP_EL0[liftState_simp]: + "\<lbrakk>write_reg SP_EL0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SP_EL0_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SP_EL1[simp]: - "liftS (read_reg SP_EL1_ref) = readS (SP_EL1 \<circ> regstate)" +lemma liftS_read_reg_SP_EL1[liftState_simp]: + "\<lbrakk>read_reg SP_EL1_ref\<rbrakk>\<^sub>S = readS (SP_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SP_EL1[simp]: - "liftS (write_reg SP_EL1_ref v) = updateS (regstate_update (SP_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_SP_EL1[liftState_simp]: + "\<lbrakk>write_reg SP_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SP_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SP_EL2[simp]: - "liftS (read_reg SP_EL2_ref) = readS (SP_EL2 \<circ> regstate)" +lemma liftS_read_reg_SP_EL2[liftState_simp]: + "\<lbrakk>read_reg SP_EL2_ref\<rbrakk>\<^sub>S = readS (SP_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SP_EL2[simp]: - "liftS (write_reg SP_EL2_ref v) = updateS (regstate_update (SP_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_SP_EL2[liftState_simp]: + "\<lbrakk>write_reg SP_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SP_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SP_EL3[simp]: - "liftS (read_reg SP_EL3_ref) = readS (SP_EL3 \<circ> regstate)" +lemma liftS_read_reg_SP_EL3[liftState_simp]: + "\<lbrakk>read_reg SP_EL3_ref\<rbrakk>\<^sub>S = readS (SP_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SP_EL3[simp]: - "liftS (write_reg SP_EL3_ref v) = updateS (regstate_update (SP_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_SP_EL3[liftState_simp]: + "\<lbrakk>write_reg SP_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SP_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_SP_mon[simp]: - "liftS (read_reg SP_mon_ref) = readS (SP_mon \<circ> regstate)" +lemma liftS_read_reg_SP_mon[liftState_simp]: + "\<lbrakk>read_reg SP_mon_ref\<rbrakk>\<^sub>S = readS (SP_mon \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_SP_mon[simp]: - "liftS (write_reg SP_mon_ref v) = updateS (regstate_update (SP_mon_update (\<lambda>_. v)))" +lemma liftS_write_reg_SP_mon[liftState_simp]: + "\<lbrakk>write_reg SP_mon_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (SP_mon_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TCR_EL1[simp]: - "liftS (read_reg TCR_EL1_ref) = readS (TCR_EL1 \<circ> regstate)" +lemma liftS_read_reg_TCR_EL1[liftState_simp]: + "\<lbrakk>read_reg TCR_EL1_ref\<rbrakk>\<^sub>S = readS (TCR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TCR_EL1[simp]: - "liftS (write_reg TCR_EL1_ref v) = updateS (regstate_update (TCR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_TCR_EL1[liftState_simp]: + "\<lbrakk>write_reg TCR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TCR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TCR_EL2[simp]: - "liftS (read_reg TCR_EL2_ref) = readS (TCR_EL2 \<circ> regstate)" +lemma liftS_read_reg_TCR_EL2[liftState_simp]: + "\<lbrakk>read_reg TCR_EL2_ref\<rbrakk>\<^sub>S = readS (TCR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TCR_EL2[simp]: - "liftS (write_reg TCR_EL2_ref v) = updateS (regstate_update (TCR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_TCR_EL2[liftState_simp]: + "\<lbrakk>write_reg TCR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TCR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TCR_EL3[simp]: - "liftS (read_reg TCR_EL3_ref) = readS (TCR_EL3 \<circ> regstate)" +lemma liftS_read_reg_TCR_EL3[liftState_simp]: + "\<lbrakk>read_reg TCR_EL3_ref\<rbrakk>\<^sub>S = readS (TCR_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TCR_EL3[simp]: - "liftS (write_reg TCR_EL3_ref v) = updateS (regstate_update (TCR_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_TCR_EL3[liftState_simp]: + "\<lbrakk>write_reg TCR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TCR_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TTBCR[simp]: - "liftS (read_reg TTBCR_ref) = readS (TTBCR \<circ> regstate)" +lemma liftS_read_reg_TTBCR[liftState_simp]: + "\<lbrakk>read_reg TTBCR_ref\<rbrakk>\<^sub>S = readS (TTBCR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TTBCR[simp]: - "liftS (write_reg TTBCR_ref v) = updateS (regstate_update (TTBCR_update (\<lambda>_. v)))" +lemma liftS_write_reg_TTBCR[liftState_simp]: + "\<lbrakk>write_reg TTBCR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TTBCR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TTBR0_EL1[simp]: - "liftS (read_reg TTBR0_EL1_ref) = readS (TTBR0_EL1 \<circ> regstate)" +lemma liftS_read_reg_TTBR0_EL1[liftState_simp]: + "\<lbrakk>read_reg TTBR0_EL1_ref\<rbrakk>\<^sub>S = readS (TTBR0_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TTBR0_EL1[simp]: - "liftS (write_reg TTBR0_EL1_ref v) = updateS (regstate_update (TTBR0_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_TTBR0_EL1[liftState_simp]: + "\<lbrakk>write_reg TTBR0_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TTBR0_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TTBR0_EL2[simp]: - "liftS (read_reg TTBR0_EL2_ref) = readS (TTBR0_EL2 \<circ> regstate)" +lemma liftS_read_reg_TTBR0_EL2[liftState_simp]: + "\<lbrakk>read_reg TTBR0_EL2_ref\<rbrakk>\<^sub>S = readS (TTBR0_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TTBR0_EL2[simp]: - "liftS (write_reg TTBR0_EL2_ref v) = updateS (regstate_update (TTBR0_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_TTBR0_EL2[liftState_simp]: + "\<lbrakk>write_reg TTBR0_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TTBR0_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TTBR0_EL3[simp]: - "liftS (read_reg TTBR0_EL3_ref) = readS (TTBR0_EL3 \<circ> regstate)" +lemma liftS_read_reg_TTBR0_EL3[liftState_simp]: + "\<lbrakk>read_reg TTBR0_EL3_ref\<rbrakk>\<^sub>S = readS (TTBR0_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TTBR0_EL3[simp]: - "liftS (write_reg TTBR0_EL3_ref v) = updateS (regstate_update (TTBR0_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_TTBR0_EL3[liftState_simp]: + "\<lbrakk>write_reg TTBR0_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TTBR0_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TTBR1_EL1[simp]: - "liftS (read_reg TTBR1_EL1_ref) = readS (TTBR1_EL1 \<circ> regstate)" +lemma liftS_read_reg_TTBR1_EL1[liftState_simp]: + "\<lbrakk>read_reg TTBR1_EL1_ref\<rbrakk>\<^sub>S = readS (TTBR1_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TTBR1_EL1[simp]: - "liftS (write_reg TTBR1_EL1_ref v) = updateS (regstate_update (TTBR1_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_TTBR1_EL1[liftState_simp]: + "\<lbrakk>write_reg TTBR1_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TTBR1_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TTBR1_EL2[simp]: - "liftS (read_reg TTBR1_EL2_ref) = readS (TTBR1_EL2 \<circ> regstate)" +lemma liftS_read_reg_TTBR1_EL2[liftState_simp]: + "\<lbrakk>read_reg TTBR1_EL2_ref\<rbrakk>\<^sub>S = readS (TTBR1_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TTBR1_EL2[simp]: - "liftS (write_reg TTBR1_EL2_ref v) = updateS (regstate_update (TTBR1_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_TTBR1_EL2[liftState_simp]: + "\<lbrakk>write_reg TTBR1_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TTBR1_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_VBAR[simp]: - "liftS (read_reg VBAR_ref) = readS (VBAR \<circ> regstate)" +lemma liftS_read_reg_VBAR[liftState_simp]: + "\<lbrakk>read_reg VBAR_ref\<rbrakk>\<^sub>S = readS (VBAR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_VBAR[simp]: - "liftS (write_reg VBAR_ref v) = updateS (regstate_update (VBAR_update (\<lambda>_. v)))" +lemma liftS_write_reg_VBAR[liftState_simp]: + "\<lbrakk>write_reg VBAR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VBAR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_VBAR_EL1[simp]: - "liftS (read_reg VBAR_EL1_ref) = readS (VBAR_EL1 \<circ> regstate)" +lemma liftS_read_reg_VBAR_EL1[liftState_simp]: + "\<lbrakk>read_reg VBAR_EL1_ref\<rbrakk>\<^sub>S = readS (VBAR_EL1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_VBAR_EL1[simp]: - "liftS (write_reg VBAR_EL1_ref v) = updateS (regstate_update (VBAR_EL1_update (\<lambda>_. v)))" +lemma liftS_write_reg_VBAR_EL1[liftState_simp]: + "\<lbrakk>write_reg VBAR_EL1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VBAR_EL1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_VBAR_EL2[simp]: - "liftS (read_reg VBAR_EL2_ref) = readS (VBAR_EL2 \<circ> regstate)" +lemma liftS_read_reg_VBAR_EL2[liftState_simp]: + "\<lbrakk>read_reg VBAR_EL2_ref\<rbrakk>\<^sub>S = readS (VBAR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_VBAR_EL2[simp]: - "liftS (write_reg VBAR_EL2_ref v) = updateS (regstate_update (VBAR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_VBAR_EL2[liftState_simp]: + "\<lbrakk>write_reg VBAR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VBAR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_VBAR_EL3[simp]: - "liftS (read_reg VBAR_EL3_ref) = readS (VBAR_EL3 \<circ> regstate)" +lemma liftS_read_reg_VBAR_EL3[liftState_simp]: + "\<lbrakk>read_reg VBAR_EL3_ref\<rbrakk>\<^sub>S = readS (VBAR_EL3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_VBAR_EL3[simp]: - "liftS (write_reg VBAR_EL3_ref v) = updateS (regstate_update (VBAR_EL3_update (\<lambda>_. v)))" +lemma liftS_write_reg_VBAR_EL3[liftState_simp]: + "\<lbrakk>write_reg VBAR_EL3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VBAR_EL3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_VDFSR[simp]: - "liftS (read_reg VDFSR_ref) = readS (VDFSR \<circ> regstate)" +lemma liftS_read_reg_VDFSR[liftState_simp]: + "\<lbrakk>read_reg VDFSR_ref\<rbrakk>\<^sub>S = readS (VDFSR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_VDFSR[simp]: - "liftS (write_reg VDFSR_ref v) = updateS (regstate_update (VDFSR_update (\<lambda>_. v)))" +lemma liftS_write_reg_VDFSR[liftState_simp]: + "\<lbrakk>write_reg VDFSR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VDFSR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_VSESR_EL2[simp]: - "liftS (read_reg VSESR_EL2_ref) = readS (VSESR_EL2 \<circ> regstate)" +lemma liftS_read_reg_VSESR_EL2[liftState_simp]: + "\<lbrakk>read_reg VSESR_EL2_ref\<rbrakk>\<^sub>S = readS (VSESR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_VSESR_EL2[simp]: - "liftS (write_reg VSESR_EL2_ref v) = updateS (regstate_update (VSESR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_VSESR_EL2[liftState_simp]: + "\<lbrakk>write_reg VSESR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VSESR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_VTCR_EL2[simp]: - "liftS (read_reg VTCR_EL2_ref) = readS (VTCR_EL2 \<circ> regstate)" +lemma liftS_read_reg_VTCR_EL2[liftState_simp]: + "\<lbrakk>read_reg VTCR_EL2_ref\<rbrakk>\<^sub>S = readS (VTCR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_VTCR_EL2[simp]: - "liftS (write_reg VTCR_EL2_ref v) = updateS (regstate_update (VTCR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_VTCR_EL2[liftState_simp]: + "\<lbrakk>write_reg VTCR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VTCR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_VTTBR_EL2[simp]: - "liftS (read_reg VTTBR_EL2_ref) = readS (VTTBR_EL2 \<circ> regstate)" +lemma liftS_read_reg_VTTBR_EL2[liftState_simp]: + "\<lbrakk>read_reg VTTBR_EL2_ref\<rbrakk>\<^sub>S = readS (VTTBR_EL2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_VTTBR_EL2[simp]: - "liftS (write_reg VTTBR_EL2_ref v) = updateS (regstate_update (VTTBR_EL2_update (\<lambda>_. v)))" +lemma liftS_write_reg_VTTBR_EL2[liftState_simp]: + "\<lbrakk>write_reg VTTBR_EL2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (VTTBR_EL2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_PC[simp]: - "liftS (read_reg PC_ref) = readS (PC \<circ> regstate)" +lemma liftS_read_reg_PC[liftState_simp]: + "\<lbrakk>read_reg PC_ref\<rbrakk>\<^sub>S = readS (PC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_PC[simp]: - "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\<lambda>_. v)))" +lemma liftS_write_reg_PC[liftState_simp]: + "\<lbrakk>write_reg PC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_R[simp]: - "liftS (read_reg R_ref) = readS (R \<circ> regstate)" +lemma liftS_read_reg_R[liftState_simp]: + "\<lbrakk>read_reg R_ref\<rbrakk>\<^sub>S = readS (R \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_R[simp]: - "liftS (write_reg R_ref v) = updateS (regstate_update (R_update (\<lambda>_. v)))" +lemma liftS_write_reg_R[liftState_simp]: + "\<lbrakk>write_reg R_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (R_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_V[simp]: - "liftS (read_reg V_ref) = readS (V \<circ> regstate)" +lemma liftS_read_reg_V[liftState_simp]: + "\<lbrakk>read_reg V_ref\<rbrakk>\<^sub>S = readS (V \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_V[simp]: - "liftS (write_reg V_ref v) = updateS (regstate_update (V_update (\<lambda>_. v)))" +lemma liftS_write_reg_V[liftState_simp]: + "\<lbrakk>write_reg V_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (V_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_BranchTaken[simp]: - "liftS (read_reg BranchTaken_ref) = readS (BranchTaken \<circ> regstate)" +lemma liftS_read_reg_BranchTaken[liftState_simp]: + "\<lbrakk>read_reg BranchTaken_ref\<rbrakk>\<^sub>S = readS (BranchTaken \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_BranchTaken[simp]: - "liftS (write_reg BranchTaken_ref v) = updateS (regstate_update (BranchTaken_update (\<lambda>_. v)))" +lemma liftS_write_reg_BranchTaken[liftState_simp]: + "\<lbrakk>write_reg BranchTaken_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (BranchTaken_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_ExclusiveLocal[simp]: - "liftS (read_reg ExclusiveLocal_ref) = readS (ExclusiveLocal \<circ> regstate)" +lemma liftS_read_reg_ExclusiveLocal[liftState_simp]: + "\<lbrakk>read_reg ExclusiveLocal_ref\<rbrakk>\<^sub>S = readS (ExclusiveLocal \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_ExclusiveLocal[simp]: - "liftS (write_reg ExclusiveLocal_ref v) = updateS (regstate_update (ExclusiveLocal_update (\<lambda>_. v)))" +lemma liftS_write_reg_ExclusiveLocal[liftState_simp]: + "\<lbrakk>write_reg ExclusiveLocal_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ExclusiveLocal_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_Memory[simp]: - "liftS (read_reg Memory_ref) = readS (Memory \<circ> regstate)" +lemma liftS_read_reg_Memory[liftState_simp]: + "\<lbrakk>read_reg Memory_ref\<rbrakk>\<^sub>S = readS (Memory \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_Memory[simp]: - "liftS (write_reg Memory_ref v) = updateS (regstate_update (Memory_update (\<lambda>_. v)))" +lemma liftS_write_reg_Memory[liftState_simp]: + "\<lbrakk>write_reg Memory_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (Memory_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_PendingInterrupt[simp]: - "liftS (read_reg PendingInterrupt_ref) = readS (PendingInterrupt \<circ> regstate)" +lemma liftS_read_reg_PendingInterrupt[liftState_simp]: + "\<lbrakk>read_reg PendingInterrupt_ref\<rbrakk>\<^sub>S = readS (PendingInterrupt \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_PendingInterrupt[simp]: - "liftS (write_reg PendingInterrupt_ref v) = updateS (regstate_update (PendingInterrupt_update (\<lambda>_. v)))" +lemma liftS_write_reg_PendingInterrupt[liftState_simp]: + "\<lbrakk>write_reg PendingInterrupt_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PendingInterrupt_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_PendingPhysicalSError[simp]: - "liftS (read_reg PendingPhysicalSError_ref) = readS (PendingPhysicalSError \<circ> regstate)" +lemma liftS_read_reg_PendingPhysicalSError[liftState_simp]: + "\<lbrakk>read_reg PendingPhysicalSError_ref\<rbrakk>\<^sub>S = readS (PendingPhysicalSError \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_PendingPhysicalSError[simp]: - "liftS (write_reg PendingPhysicalSError_ref v) = updateS (regstate_update (PendingPhysicalSError_update (\<lambda>_. v)))" +lemma liftS_write_reg_PendingPhysicalSError[liftState_simp]: + "\<lbrakk>write_reg PendingPhysicalSError_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PendingPhysicalSError_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_Sleeping[simp]: - "liftS (read_reg Sleeping_ref) = readS (Sleeping \<circ> regstate)" +lemma liftS_read_reg_Sleeping[liftState_simp]: + "\<lbrakk>read_reg Sleeping_ref\<rbrakk>\<^sub>S = readS (Sleeping \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_Sleeping[simp]: - "liftS (write_reg Sleeping_ref v) = updateS (regstate_update (Sleeping_update (\<lambda>_. v)))" +lemma liftS_write_reg_Sleeping[liftState_simp]: + "\<lbrakk>write_reg Sleeping_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (Sleeping_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_ThisInstr[simp]: - "liftS (read_reg ThisInstr_ref) = readS (ThisInstr \<circ> regstate)" +lemma liftS_read_reg_ThisInstr[liftState_simp]: + "\<lbrakk>read_reg ThisInstr_ref\<rbrakk>\<^sub>S = readS (ThisInstr \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_ThisInstr[simp]: - "liftS (write_reg ThisInstr_ref v) = updateS (regstate_update (ThisInstr_update (\<lambda>_. v)))" +lemma liftS_write_reg_ThisInstr[liftState_simp]: + "\<lbrakk>write_reg ThisInstr_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ThisInstr_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_ThisInstrEnc[simp]: - "liftS (read_reg ThisInstrEnc_ref) = readS (ThisInstrEnc \<circ> regstate)" +lemma liftS_read_reg_ThisInstrEnc[liftState_simp]: + "\<lbrakk>read_reg ThisInstrEnc_ref\<rbrakk>\<^sub>S = readS (ThisInstrEnc \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_ThisInstrEnc[simp]: - "liftS (write_reg ThisInstrEnc_ref v) = updateS (regstate_update (ThisInstrEnc_update (\<lambda>_. v)))" +lemma liftS_write_reg_ThisInstrEnc[liftState_simp]: + "\<lbrakk>write_reg ThisInstrEnc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (ThisInstrEnc_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_currentCond[simp]: - "liftS (read_reg currentCond_ref) = readS (currentCond \<circ> regstate)" +lemma liftS_read_reg_currentCond[liftState_simp]: + "\<lbrakk>read_reg currentCond_ref\<rbrakk>\<^sub>S = readS (currentCond \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_currentCond[simp]: - "liftS (write_reg currentCond_ref v) = updateS (regstate_update (currentCond_update (\<lambda>_. v)))" +lemma liftS_write_reg_currentCond[liftState_simp]: + "\<lbrakk>write_reg currentCond_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (currentCond_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_unconditional[simp]: - "liftS (read_reg unconditional_ref) = readS (unconditional \<circ> regstate)" +lemma liftS_read_reg_unconditional[liftState_simp]: + "\<lbrakk>read_reg unconditional_ref\<rbrakk>\<^sub>S = readS (unconditional \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_unconditional[simp]: - "liftS (write_reg unconditional_ref v) = updateS (regstate_update (unconditional_update (\<lambda>_. v)))" +lemma liftS_write_reg_unconditional[liftState_simp]: + "\<lbrakk>write_reg unconditional_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (unconditional_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) end diff --git a/snapshots/isabelle/aarch64/Aarch64_types.thy b/snapshots/isabelle/aarch64/Aarch64_types.thy index b2379614..33d9cafc 100644 --- a/snapshots/isabelle/aarch64/Aarch64_types.thy +++ b/snapshots/isabelle/aarch64/Aarch64_types.thy @@ -5,23 +5,23 @@ theory "Aarch64_types" imports Main "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" - "Sail_operators_mwords" - "Prompt_monad" - "Prompt" - "State" + "/tmp/sail/src/lem_interp/Sail2_instr_kinds" + "/tmp/sail/src/gen_lib/Sail2_values" + "/tmp/sail/src/gen_lib/Sail2_operators_mwords" + "/tmp/sail/src/gen_lib/Sail2_prompt_monad" + "/tmp/sail/src/gen_lib/Sail2_prompt" + "/tmp/sail/src/gen_lib/Sail2_string" begin (*Generated by Sail from aarch64.*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) -(*open import State*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) type_synonym 'n bits =" ( 'n::len)Word.word " datatype exception = @@ -957,7 +957,7 @@ record regstate = fun ProcState_of_regval :: " register_value \<Rightarrow>(ProcState)option " where " ProcState_of_regval (Regval_ProcState (v)) = ( Some v )" -|" ProcState_of_regval g__605 = ( None )" +|" ProcState_of_regval g__281 = ( None )" (*val regval_of_ProcState : ProcState -> register_value*) @@ -970,7 +970,7 @@ definition regval_of_ProcState :: " ProcState \<Rightarrow> register_value " w fun InstrEnc_of_regval :: " register_value \<Rightarrow>(InstrEnc)option " where " InstrEnc_of_regval (Regval___InstrEnc (v)) = ( Some v )" -|" InstrEnc_of_regval g__604 = ( None )" +|" InstrEnc_of_regval g__280 = ( None )" (*val regval_of___InstrEnc : __InstrEnc -> register_value*) @@ -983,7 +983,7 @@ definition regval_of___InstrEnc :: " InstrEnc \<Rightarrow> register_value " w fun bool_of_regval :: " register_value \<Rightarrow>(bool)option " where " bool_of_regval (Regval_bool (v)) = ( Some v )" -|" bool_of_regval g__603 = ( None )" +|" bool_of_regval g__279 = ( None )" (*val regval_of_bool : bool -> register_value*) @@ -996,7 +996,7 @@ definition regval_of_bool :: " bool \<Rightarrow> register_value " where fun signal_of_regval :: " register_value \<Rightarrow>(signal)option " where " signal_of_regval (Regval_signal (v)) = ( Some v )" -|" signal_of_regval g__602 = ( None )" +|" signal_of_regval g__278 = ( None )" (*val regval_of_signal : signal -> register_value*) @@ -1009,7 +1009,7 @@ definition regval_of_signal :: " signal \<Rightarrow> register_value " where fun vector_128_dec_bit_of_regval :: " register_value \<Rightarrow>((128)Word.word)option " where " vector_128_dec_bit_of_regval (Regval_vector_128_dec_bit (v)) = ( Some v )" -|" vector_128_dec_bit_of_regval g__601 = ( None )" +|" vector_128_dec_bit_of_regval g__277 = ( None )" (*val regval_of_vector_128_dec_bit : mword ty128 -> register_value*) @@ -1022,7 +1022,7 @@ definition regval_of_vector_128_dec_bit :: "(128)Word.word \<Rightarrow> regist fun vector_1_dec_bit_of_regval :: " register_value \<Rightarrow>((1)Word.word)option " where " vector_1_dec_bit_of_regval (Regval_vector_1_dec_bit (v)) = ( Some v )" -|" vector_1_dec_bit_of_regval g__600 = ( None )" +|" vector_1_dec_bit_of_regval g__276 = ( None )" (*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*) @@ -1035,7 +1035,7 @@ definition regval_of_vector_1_dec_bit :: "(1)Word.word \<Rightarrow> register_v fun vector_32_dec_bit_of_regval :: " register_value \<Rightarrow>((32)Word.word)option " where " vector_32_dec_bit_of_regval (Regval_vector_32_dec_bit (v)) = ( Some v )" -|" vector_32_dec_bit_of_regval g__599 = ( None )" +|" vector_32_dec_bit_of_regval g__275 = ( None )" (*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*) @@ -1048,7 +1048,7 @@ definition regval_of_vector_32_dec_bit :: "(32)Word.word \<Rightarrow> register fun vector_4_dec_bit_of_regval :: " register_value \<Rightarrow>((4)Word.word)option " where " vector_4_dec_bit_of_regval (Regval_vector_4_dec_bit (v)) = ( Some v )" -|" vector_4_dec_bit_of_regval g__598 = ( None )" +|" vector_4_dec_bit_of_regval g__274 = ( None )" (*val regval_of_vector_4_dec_bit : mword ty4 -> register_value*) @@ -1061,7 +1061,7 @@ definition regval_of_vector_4_dec_bit :: "(4)Word.word \<Rightarrow> register_v fun vector_52_dec_bit_of_regval :: " register_value \<Rightarrow>((52)Word.word)option " where " vector_52_dec_bit_of_regval (Regval_vector_52_dec_bit (v)) = ( Some v )" -|" vector_52_dec_bit_of_regval g__597 = ( None )" +|" vector_52_dec_bit_of_regval g__273 = ( None )" (*val regval_of_vector_52_dec_bit : mword ty52 -> register_value*) @@ -1074,7 +1074,7 @@ definition regval_of_vector_52_dec_bit :: "(52)Word.word \<Rightarrow> register fun vector_64_dec_bit_of_regval :: " register_value \<Rightarrow>((64)Word.word)option " where " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )" -|" vector_64_dec_bit_of_regval g__596 = ( None )" +|" vector_64_dec_bit_of_regval g__272 = ( None )" (*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) @@ -1116,7 +1116,10 @@ definition regval_of_list :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a (*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) definition option_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a option)option " where " option_of_regval of_regval1 = ( \<lambda>x . - (case x of Regval_option v => map_option of_regval1 v | _ => None ) )" + (case x of + Regval_option v => Some (Option.bind v of_regval1) + | _ => None + ) )" (*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) @@ -2506,6 +2509,6 @@ definition register_accessors :: "(string \<Rightarrow> regstate \<Rightarrow>( -type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, exception) monadR " -type_synonym 'a M =" (register_value, 'a, exception) monad " +type_synonym( 'a, 'r) MR =" (register_value, regstate, 'a, 'r, exception) base_monadR " +type_synonym 'a M =" (register_value, regstate, 'a, exception) base_monad " end diff --git a/snapshots/isabelle/cheri/Cheri.thy b/snapshots/isabelle/cheri/Cheri.thy index eed49a23..af6852b6 100644 --- a/snapshots/isabelle/cheri/Cheri.thy +++ b/snapshots/isabelle/cheri/Cheri.thy @@ -5,12 +5,12 @@ theory "Cheri" imports Main "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" - "Sail_operators_mwords" - "Prompt_monad" - "Prompt" - "State" + "Sail2_instr_kinds" + "Sail2_values" + "Sail2_string" + "Sail2_operators_mwords" + "Sail2_prompt_monad" + "Sail2_prompt" "Cheri_types" "Mips_extras" @@ -18,12 +18,12 @@ begin (*Generated by Sail from cheri.*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) -(*open import State*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) (*open import Cheri_types*) (*open import Mips_extras*) @@ -31,12 +31,6 @@ definition cap_size :: " int " where " cap_size = ( (( 32 :: int)::ii))" -(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*) - -definition undefined_option :: " 'a \<Rightarrow>((register_value),('a option),(exception))monad " where - " undefined_option typ_a = ( undefined_unit () \<then> internal_pick [None,Some typ_a])" - - @@ -49,15 +43,39 @@ definition neq_bool :: " bool \<Rightarrow> bool \<Rightarrow> bool " where " neq_bool x y = ( \<not> (((x = y))))" +(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*) + +definition undefined_option :: " 'a \<Rightarrow>((register_value),('a option),(exception))monad " where + " undefined_option typ_a = ( + undefined_unit () \<bind> (\<lambda> (u_0 :: unit) . + (let (u_1 :: 'a) = typ_a in + internal_pick [Some u_1,None])))" + + +(*val is_none : forall 'a. maybe 'a -> bool*) + +fun is_none :: " 'a option \<Rightarrow> bool " where + " is_none (Some (_)) = ( False )" +|" is_none None = ( True )" + +(*val is_some : forall 'a. maybe 'a -> bool*) +fun is_some :: " 'a option \<Rightarrow> bool " where + " is_some (Some (_)) = ( True )" +|" is_some None = ( False )" -(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) +(*val sail_mask : forall 'len 'v . Size 'len, Size 'v => itself 'len -> mword 'v -> mword 'len*) + +definition sail_mask :: "('len::len)itself \<Rightarrow>('v::len)Word.word \<Rightarrow>('len::len)Word.word " where + " sail_mask len v = ( + (let len = (size_itself_int len) in + if ((len \<le> ((int (size v))))) then (vector_truncate v len :: ( 'len::len)Word.word) + else (zero_extend v len :: ( 'len::len)Word.word)))" -(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) @@ -65,29 +83,25 @@ definition neq_bool :: " bool \<Rightarrow> bool \<Rightarrow> bool " where fun cast_unit_vec0 :: " bitU \<Rightarrow>(1)Word.word " where " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))" -|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))" - +|" cast_unit_vec0 _ = ( (vec_of_bits [B1] :: 1 Word.word))" -(*val DecStr : ii -> string*) - -(*val HexStr : ii -> string*) (*val __MIPS_write : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) definition MIPS_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " MIPS_write addr width data = ( - write_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width + write_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word) addr data )" -(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) +(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) definition MIPS_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where " MIPS_read addr width = ( - (read_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width + (read_ram instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] @@ -101,27 +115,22 @@ definition MIPS_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((registe definition undefined_exception :: " unit \<Rightarrow>((register_value),(exception),(exception))monad " where " undefined_exception _ = ( - (undefined_unit () \<then> - undefined_string () ) \<bind> (\<lambda> (w__0 :: string) . - ((undefined_unit () \<then> - undefined_unit () ) \<then> - undefined_unit () ) \<then> + undefined_string () \<bind> (\<lambda> (u_0 :: string) . + undefined_unit () \<bind> (\<lambda> (u_1 :: unit) . internal_pick - [ISAException () ,Error_not_implemented w__0,Error_misaligned_access () ,Error_EBREAK () ,Error_internal_error () ]))" + [ISAException u_1,Error_not_implemented u_0,Error_misaligned_access u_1,Error_EBREAK u_1,Error_internal_error u_1])))" -(*val sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) +(*val mips_sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) -(*val zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) +(*val mips_zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) -definition sign_extend1 :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where - " sign_extend1 (m__tv :: int) v = ( (sign_extend0 - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv :: ( 'm::len)Word.word))" +definition mips_sign_extend :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " mips_sign_extend (m__tv :: int) v = ( (sign_extend v m__tv :: ( 'm::len)Word.word))" -definition zero_extend1 :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where - " zero_extend1 (m__tv :: int) v = ( (zero_extend0 - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv :: ( 'm::len)Word.word))" +definition mips_zero_extend :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " mips_zero_extend (m__tv :: int) v = ( (zero_extend v m__tv :: ( 'm::len)Word.word))" (*val zeros : forall 'n . Size 'n => integer -> unit -> mword 'n*) @@ -136,13 +145,13 @@ definition ones :: " int \<Rightarrow> unit \<Rightarrow>('n::len)Word.word " " ones (n__tv :: int) _ = ( (replicate_bits (vec_of_bits [B1] :: 1 Word.word) n__tv :: ( 'n::len)Word.word))" -(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) +(*val zopz0zI_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) -(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) +(*val zopz0zKzJ_s : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) -(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) +(*val zopz0zI_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) -(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) +(*val zopz0zKzJ_u : forall 'n . Size 'n => mword 'n -> mword 'n -> bool*) definition zopz0zI_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))" @@ -170,7 +179,7 @@ definition bool_to_bits :: " bool \<Rightarrow>(1)Word.word " where fun bit_to_bool :: " bitU \<Rightarrow> bool " where " bit_to_bool B1 = ( True )" -|" bit_to_bool B0 = ( False )" +|" bit_to_bool _ = ( False )" (*val bits_to_bool : mword ty1 -> bool*) @@ -182,12 +191,12 @@ definition bits_to_bool :: "(1)Word.word \<Rightarrow> bool " where (* function{to_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits. *) -(*val to_bits : forall 'l. Size 'l => itself 'l -> ii -> mword 'l*) +(*val to_bits : forall 'l . Size 'l => itself 'l -> ii -> mword 'l*) definition to_bits :: "('l::len)itself \<Rightarrow> int \<Rightarrow>('l::len)Word.word " where " to_bits l n = ( (let l = (size_itself_int l) in - (get_slice_int0 instance_Sail_values_Bitvector_Machine_word_mword_dict l n (( 0 :: int)::ii) :: ( 'l::len)Word.word)))" + (get_slice_int0 instance_Sail2_values_Bitvector_Machine_word_mword_dict l n (( 0 :: int)::ii) :: ( 'l::len)Word.word)))" (*val mask : forall 'm 'n . Size 'm, Size 'n => integer -> mword 'm -> mword 'n*) @@ -197,333 +206,245 @@ definition mask0 :: " int \<Rightarrow>('m::len)Word.word \<Rightarrow>('n::len (subrange_vec_dec bs ((n__tv - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: ( 'n::len)Word.word))" -(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) - -definition extzv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where - " extzv (m__tv :: int) v = ( (extz_vec m__tv v :: ( 'm::len)Word.word))" - - -(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) - -definition extsv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where - " extsv (m__tv :: int) v = ( (exts_vec m__tv v :: ( 'm::len)Word.word))" - - -(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*) - -definition slice_mask :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where - " slice_mask (n__tv :: int) i l = ( - (let (one :: 'n bits) = ((extzv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in - (shiftl ((sub_vec ((shiftl one l :: ( 'n::len)Word.word)) one :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)))" - - -(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) - -definition is_zero_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where - " is_zero_subrange xs i j = ( - (((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0] :: 1 Word.word) :: ( 'n::len)Word.word))))" - - -(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) - -definition is_ones_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where - " is_ones_subrange xs i j = ( - (let (m :: 'n bits) = ((slice_mask ((int (size xs))) j ((j - i)) :: ( 'n::len)Word.word)) in - (((and_vec xs m :: ( 'n::len)Word.word)) = m)))" - - -(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*) - -definition slice_slice_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word " where - " slice_slice_concat (r__tv :: int) xs i l ys i' l' = ( - (let xs = - ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in - (let ys = - ((shiftr ((and_vec ys ((slice_mask ((int (size ys))) i' l' :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) i' - :: ( 'm::len)Word.word)) in - (or_vec ((shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)) ((extzv r__tv ys :: ( 'r::len)Word.word)) - :: ( 'r::len)Word.word))))" - - -(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*) - -definition slice_zeros_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word " where - " slice_zeros_concat (r__tv :: int) xs i l l' = ( - (let xs = - ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in - (shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)))" - - -(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*) - -definition subrange_subrange_eq :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where - " subrange_subrange_eq xs i j ys i' j' = ( - (let xs = - ((shiftr - ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j - :: ( 'n::len)Word.word)) in - (let ys = - ((shiftr - ((and_vec ys ((slice_mask ((int (size xs))) j' ((i' - j')) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) - j' - :: ( 'n::len)Word.word)) in - (xs = ys))))" - - -(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*) - -definition subrange_subrange_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('s::len)Word.word " where - " subrange_subrange_concat (s__tv :: int) xs i j ys i' j' = ( - (let xs = - ((shiftr - ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j - :: ( 'n::len)Word.word)) in - (let ys = - ((shiftr - ((and_vec ys ((slice_mask ((int (size ys))) j' ((i' - j')) :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) - j' - :: ( 'm::len)Word.word)) in - (or_vec - ((sub_vec_int ((shiftl ((extzv s__tv xs :: ( 's::len)Word.word)) i' :: ( 's::len)Word.word)) - ((j' - (( 1 :: int)::ii))) - :: ( 's::len)Word.word)) ((extzv s__tv ys :: ( 's::len)Word.word)) - :: ( 's::len)Word.word))))" - - -(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) - -definition place_subrange :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where - " place_subrange (m__tv :: int) xs i j shift = ( - (let xs = - ((shiftr - ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j - :: ( 'n::len)Word.word)) in - (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" - - -(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) - -definition place_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where - " place_slice (m__tv :: int) xs i l shift = ( - (let xs = - ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in - (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" - - -(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) - -definition zext_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where - " zext_slice (m__tv :: int) xs i l = ( - (let xs = - ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in - (extzv m__tv xs :: ( 'm::len)Word.word)))" - - -(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) +(*val undefined_CauseReg : unit -> M CauseReg*) -definition sext_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where - " sext_slice (m__tv :: int) xs i l = ( - (let xs = - ((arith_shiftr - ((shiftl ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) - ((((((int (size xs))) - i)) - l)) - :: ( 'n::len)Word.word)) ((((int (size xs))) - l)) - :: ( 'n::len)Word.word)) in - (extsv m__tv xs :: ( 'm::len)Word.word)))" +definition undefined_CauseReg :: " unit \<Rightarrow>((register_value),(CauseReg),(exception))monad " where + " undefined_CauseReg _ = ( + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + return ((| CauseReg_CauseReg_chunk_0 = w__0 |))))" -(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) +(*val Mk_CauseReg : mword ty32 -> CauseReg*) -definition unsigned_slice :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int " where - " unsigned_slice xs i l = ( - (let xs = - ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in - Word.uint xs))" +definition Mk_CauseReg :: "(32)Word.word \<Rightarrow> CauseReg " where + " Mk_CauseReg v = ( + (| CauseReg_CauseReg_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )" -(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) +(*val _get_CauseReg_bits : CauseReg -> mword ty32*) -definition unsigned_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int " where - " unsigned_subrange xs i j = ( - (let xs = - ((shiftr - ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i - :: ( 'n::len)Word.word)) in - Word.uint xs))" - - -(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*) +definition get_CauseReg_bits :: " CauseReg \<Rightarrow>(32)Word.word " where + " get_CauseReg_bits v = ( + (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))" -definition zext_ones :: " int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where - " zext_ones (n__tv :: int) m = ( - (let (v :: 'n bits) = ((extsv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in - (shiftr v ((((int (size v))) - m)) :: ( 'n::len)Word.word)))" - - -(*val undefined_CauseReg : unit -> M CauseReg*) - -definition undefined_CauseReg :: " unit \<Rightarrow>((register_value),(CauseReg),(exception))monad " where - " undefined_CauseReg _ = ( - (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . - internal_pick [Mk_CauseReg w__0]))" +(*val _set_CauseReg_bits : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*) -(*val _get_CauseReg : CauseReg -> mword ty32*) +definition set_CauseReg_bits :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_bits r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" -fun get_CauseReg :: " CauseReg \<Rightarrow>(32)Word.word " where - " get_CauseReg (Mk_CauseReg (v)) = ( v )" +(*val _update_CauseReg_bits : CauseReg -> mword ty32 -> CauseReg*) -(*val _set_CauseReg : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*) +definition update_CauseReg_bits :: " CauseReg \<Rightarrow>(32)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_bits v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word))|)))" -definition set_CauseReg :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_CauseReg r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_CauseReg v) in - write_reg r_ref r)))" +(*val _update_CapCauseReg_bits : CapCauseReg -> mword ty16 -> CapCauseReg*) -(*val _get_CapCauseReg : CapCauseReg -> mword ty16*) +(*val _get_CapCauseReg_bits : CapCauseReg -> mword ty16*) -(*val _set_CapCauseReg : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*) +(*val _set_CapCauseReg_bits : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*) (*val _get_CauseReg_BD : CauseReg -> mword ty1*) -fun get_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word " where - " get_CauseReg_BD (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" +definition get_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word " where + " get_CauseReg_BD v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" (*val _set_CauseReg_BD : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) definition set_CauseReg_BD :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CauseReg_BD r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . - (let r = ((get_CauseReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 31 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_CauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 31 :: int)::ii) (( 31 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CauseReg_BD : CauseReg -> mword ty1 -> CauseReg*) -fun update_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where - " update_CauseReg_BD (Mk_CauseReg (v)) x = ( - Mk_CauseReg ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) x :: 32 Word.word)))" +definition update_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_BD v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_CauseReg_CE : CauseReg -> mword ty2*) -fun get_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word " where - " get_CauseReg_CE (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 29 :: int)::ii) (( 28 :: int)::ii) :: 2 Word.word))" +definition get_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word " where + " get_CauseReg_CE v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 29 :: int)::ii) (( 28 :: int)::ii) :: 2 Word.word))" (*val _set_CauseReg_CE : register_ref regstate register_value CauseReg -> mword ty2 -> M unit*) definition set_CauseReg_CE :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CauseReg_CE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . - (let r = ((get_CauseReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 28 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_CauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 29 :: int)::ii) (( 28 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CauseReg_CE : CauseReg -> mword ty2 -> CauseReg*) -fun update_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word \<Rightarrow> CauseReg " where - " update_CauseReg_CE (Mk_CauseReg (v)) x = ( - Mk_CauseReg ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 28 :: int)::ii) x :: 32 Word.word)))" +definition update_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_CE v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 29 :: int)::ii) (( 28 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 32 Word.word))|)))" (*val _get_CauseReg_IV : CauseReg -> mword ty1*) -fun get_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word " where - " get_CauseReg_IV (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))" +definition get_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word " where + " get_CauseReg_IV v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))" (*val _set_CauseReg_IV : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) definition set_CauseReg_IV :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CauseReg_IV r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . - (let r = ((get_CauseReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 23 :: int)::ii) (( 23 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_CauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 23 :: int)::ii) (( 23 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CauseReg_IV : CauseReg -> mword ty1 -> CauseReg*) -fun update_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where - " update_CauseReg_IV (Mk_CauseReg (v)) x = ( - Mk_CauseReg ((update_subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) x :: 32 Word.word)))" +definition update_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_IV v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 23 :: int)::ii) (( 23 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_CauseReg_WP : CauseReg -> mword ty1*) -fun get_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word " where - " get_CauseReg_WP (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" +definition get_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word " where + " get_CauseReg_WP v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" (*val _set_CauseReg_WP : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) definition set_CauseReg_WP :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CauseReg_WP r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . - (let r = ((get_CauseReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_CauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 22 :: int)::ii) (( 22 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CauseReg_WP : CauseReg -> mword ty1 -> CauseReg*) -fun update_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where - " update_CauseReg_WP (Mk_CauseReg (v)) x = ( - Mk_CauseReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 32 Word.word)))" +definition update_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_WP v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_CauseReg_IP : CauseReg -> mword ty8*) -fun get_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word " where - " get_CauseReg_IP (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" +definition get_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word " where + " get_CauseReg_IP v = ( (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" (*val _set_CauseReg_IP : register_ref regstate register_value CauseReg -> mword ty8 -> M unit*) definition set_CauseReg_IP :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CauseReg_IP r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . - (let r = ((get_CauseReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_CauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 15 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CauseReg_IP : CauseReg -> mword ty8 -> CauseReg*) -fun update_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CauseReg " where - " update_CauseReg_IP (Mk_CauseReg (v)) x = ( - Mk_CauseReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 32 Word.word)))" +definition update_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_IP v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word))|)))" (*val _get_CauseReg_ExcCode : CauseReg -> mword ty5*) -fun get_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word " where - " get_CauseReg_ExcCode (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word))" +definition get_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word " where + " get_CauseReg_ExcCode v = ( + (subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word))" (*val _set_CauseReg_ExcCode : register_ref regstate register_value CauseReg -> mword ty5 -> M unit*) definition set_CauseReg_ExcCode :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CauseReg_ExcCode r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . - (let r = ((get_CauseReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 2 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_CauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 r) (( 6 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CauseReg_ExcCode : CauseReg -> mword ty5 -> CauseReg*) -fun update_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word \<Rightarrow> CauseReg " where - " update_CauseReg_ExcCode (Mk_CauseReg (v)) x = ( - Mk_CauseReg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 2 :: int)::ii) x :: 32 Word.word)))" +definition update_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_ExcCode v x = ( + (v (| + CauseReg_CauseReg_chunk_0 := + ((update_subrange_vec_dec(CauseReg_CauseReg_chunk_0 v) (( 6 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) + :: 32 Word.word))|)))" (*val _update_CapCauseReg_ExcCode : CapCauseReg -> mword ty8 -> CapCauseReg*) @@ -537,187 +458,271 @@ fun update_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word \<Rightarro definition undefined_TLBEntryLoReg :: " unit \<Rightarrow>((register_value),(TLBEntryLoReg),(exception))monad " where " undefined_TLBEntryLoReg _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - internal_pick [Mk_TLBEntryLoReg w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + return ((| TLBEntryLoReg_TLBEntryLoReg_chunk_0 = w__0 |))))" + + +(*val Mk_TLBEntryLoReg : mword ty64 -> TLBEntryLoReg*) + +definition Mk_TLBEntryLoReg :: "(64)Word.word \<Rightarrow> TLBEntryLoReg " where + " Mk_TLBEntryLoReg v = ( + (| TLBEntryLoReg_TLBEntryLoReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -(*val _get_TLBEntryLoReg : TLBEntryLoReg -> mword ty64*) +(*val _get_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64*) -fun get_TLBEntryLoReg :: " TLBEntryLoReg \<Rightarrow>(64)Word.word " where - " get_TLBEntryLoReg (Mk_TLBEntryLoReg (v)) = ( v )" +definition get_TLBEntryLoReg_bits :: " TLBEntryLoReg \<Rightarrow>(64)Word.word " where + " get_TLBEntryLoReg_bits v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_TLBEntryLoReg : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*) +(*val _set_TLBEntryLoReg_bits : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*) -definition set_TLBEntryLoReg :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_TLBEntryLoReg r_ref v = ( +definition set_TLBEntryLoReg_bits :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_TLBEntryLoReg v) in + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_TLBEntryLoReg_bits : TLBEntryLoReg -> mword ty64 -> TLBEntryLoReg*) + +definition update_TLBEntryLoReg_bits :: " TLBEntryLoReg \<Rightarrow>(64)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_bits v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1*) -fun get_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where - " get_TLBEntryLoReg_CapS (Mk_TLBEntryLoReg (v)) = ( - (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_CapS v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntryLoReg_CapS : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) definition set_TLBEntryLoReg_CapS :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_CapS r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_CapS (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_CapS v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1*) -fun get_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where - " get_TLBEntryLoReg_CapL (Mk_TLBEntryLoReg (v)) = ( - (subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_CapL v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntryLoReg_CapL : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) definition set_TLBEntryLoReg_CapL :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_CapL r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 62 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_CapL (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_CapL v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 62 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24*) -fun get_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word " where - " get_TLBEntryLoReg_PFN (Mk_TLBEntryLoReg (v)) = ( - (subrange_vec_dec v (( 29 :: int)::ii) (( 6 :: int)::ii) :: 24 Word.word))" +definition get_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word " where + " get_TLBEntryLoReg_PFN v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 29 :: int)::ii) (( 6 :: int)::ii) :: 24 Word.word))" (*val _set_TLBEntryLoReg_PFN : register_ref regstate register_value TLBEntryLoReg -> mword ty24 -> M unit*) definition set_TLBEntryLoReg_PFN :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_PFN r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 29 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec v (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_PFN (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_PFN v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 29 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec x (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3*) -fun get_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word " where - " get_TLBEntryLoReg_C (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word))" +definition get_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word " where + " get_TLBEntryLoReg_C v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word))" (*val _set_TLBEntryLoReg_C : register_ref regstate register_value TLBEntryLoReg -> mword ty3 -> M unit*) definition set_TLBEntryLoReg_C :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_C r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 5 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec v (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_C (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_C v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 5 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec x (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1*) -fun get_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where - " get_TLBEntryLoReg_D (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_D v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntryLoReg_D : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) definition set_TLBEntryLoReg_D :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_D r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_D (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_D v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1*) -fun get_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where - " get_TLBEntryLoReg_V (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_V v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntryLoReg_V : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) definition set_TLBEntryLoReg_V :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_V r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_V (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_V v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1*) -fun get_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where - " get_TLBEntryLoReg_G (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_G v = ( + (subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntryLoReg_G : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) definition set_TLBEntryLoReg_G :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryLoReg_G r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . - (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryLoReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) -fun update_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where - " update_TLBEntryLoReg_G (Mk_TLBEntryLoReg (v)) x = ( - Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_G v x = ( + (v (| + TLBEntryLoReg_TLBEntryLoReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryLoReg_TLBEntryLoReg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val undefined_TLBEntryHiReg : unit -> M TLBEntryHiReg*) @@ -725,93 +730,143 @@ fun update_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Right definition undefined_TLBEntryHiReg :: " unit \<Rightarrow>((register_value),(TLBEntryHiReg),(exception))monad " where " undefined_TLBEntryHiReg _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - internal_pick [Mk_TLBEntryHiReg w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + return ((| TLBEntryHiReg_TLBEntryHiReg_chunk_0 = w__0 |))))" + + +(*val Mk_TLBEntryHiReg : mword ty64 -> TLBEntryHiReg*) +definition Mk_TLBEntryHiReg :: "(64)Word.word \<Rightarrow> TLBEntryHiReg " where + " Mk_TLBEntryHiReg v = ( + (| TLBEntryHiReg_TLBEntryHiReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -(*val _get_TLBEntryHiReg : TLBEntryHiReg -> mword ty64*) -fun get_TLBEntryHiReg :: " TLBEntryHiReg \<Rightarrow>(64)Word.word " where - " get_TLBEntryHiReg (Mk_TLBEntryHiReg (v)) = ( v )" +(*val _get_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64*) +definition get_TLBEntryHiReg_bits :: " TLBEntryHiReg \<Rightarrow>(64)Word.word " where + " get_TLBEntryHiReg_bits v = ( + (subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_TLBEntryHiReg : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*) -definition set_TLBEntryHiReg :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_TLBEntryHiReg r_ref v = ( +(*val _set_TLBEntryHiReg_bits : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*) + +definition set_TLBEntryHiReg_bits :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_TLBEntryHiReg v) in + (let r = + ((r (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_TLBEntryHiReg_bits : TLBEntryHiReg -> mword ty64 -> TLBEntryHiReg*) + +definition update_TLBEntryHiReg_bits :: " TLBEntryHiReg \<Rightarrow>(64)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_bits v x = ( + (v (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2*) -fun get_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word " where - " get_TLBEntryHiReg_R (Mk_TLBEntryHiReg (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))" +definition get_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word " where + " get_TLBEntryHiReg_R v = ( + (subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))" (*val _set_TLBEntryHiReg_R : register_ref regstate register_value TLBEntryHiReg -> mword ty2 -> M unit*) definition set_TLBEntryHiReg_R :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryHiReg_R r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . - (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryHiReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 r) (( 63 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2 -> TLBEntryHiReg*) -fun update_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntryHiReg " where - " update_TLBEntryHiReg_R (Mk_TLBEntryHiReg (v)) x = ( - Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_R v x = ( + (v (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 63 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27*) -fun get_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word " where - " get_TLBEntryHiReg_VPN2 (Mk_TLBEntryHiReg (v)) = ( - (subrange_vec_dec v (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))" +definition get_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word " where + " get_TLBEntryHiReg_VPN2 v = ( + (subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))" (*val _set_TLBEntryHiReg_VPN2 : register_ref regstate register_value TLBEntryHiReg -> mword ty27 -> M unit*) definition set_TLBEntryHiReg_VPN2 :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryHiReg_VPN2 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . - (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 39 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryHiReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 r) (( 39 :: int)::ii) (( 13 :: int)::ii) + ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27 -> TLBEntryHiReg*) -fun update_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntryHiReg " where - " update_TLBEntryHiReg_VPN2 (Mk_TLBEntryHiReg (v)) x = ( - Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 39 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_VPN2 v x = ( + (v (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 39 :: int)::ii) (( 13 :: int)::ii) + ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8*) -fun get_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word " where - " get_TLBEntryHiReg_ASID (Mk_TLBEntryHiReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" +definition get_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word " where + " get_TLBEntryHiReg_ASID v = ( + (subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" (*val _set_TLBEntryHiReg_ASID : register_ref regstate register_value TLBEntryHiReg -> mword ty8 -> M unit*) definition set_TLBEntryHiReg_ASID :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntryHiReg_ASID r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . - (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_TLBEntryHiReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8 -> TLBEntryHiReg*) -fun update_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntryHiReg " where - " update_TLBEntryHiReg_ASID (Mk_TLBEntryHiReg (v)) x = ( - Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_ASID v x = ( + (v (| + TLBEntryHiReg_TLBEntryHiReg_chunk_0 := + ((update_subrange_vec_dec(TLBEntryHiReg_TLBEntryHiReg_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word))|)))" (*val undefined_ContextReg : unit -> M ContextReg*) @@ -819,69 +874,111 @@ fun update_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word \<Ri definition undefined_ContextReg :: " unit \<Rightarrow>((register_value),(ContextReg),(exception))monad " where " undefined_ContextReg _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - internal_pick [Mk_ContextReg w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + return ((| ContextReg_ContextReg_chunk_0 = w__0 |))))" + +(*val Mk_ContextReg : mword ty64 -> ContextReg*) -(*val _get_ContextReg : ContextReg -> mword ty64*) +definition Mk_ContextReg :: "(64)Word.word \<Rightarrow> ContextReg " where + " Mk_ContextReg v = ( + (| ContextReg_ContextReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -fun get_ContextReg :: " ContextReg \<Rightarrow>(64)Word.word " where - " get_ContextReg (Mk_ContextReg (v)) = ( v )" +(*val _get_ContextReg_bits : ContextReg -> mword ty64*) -(*val _set_ContextReg : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*) +definition get_ContextReg_bits :: " ContextReg \<Rightarrow>(64)Word.word " where + " get_ContextReg_bits v = ( + (subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -definition set_ContextReg :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_ContextReg r_ref v = ( + +(*val _set_ContextReg_bits : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*) + +definition set_ContextReg_bits :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_ContextReg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_ContextReg v) in + (let r = + ((r (| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_ContextReg_bits : ContextReg -> mword ty64 -> ContextReg*) + +definition update_ContextReg_bits :: " ContextReg \<Rightarrow>(64)Word.word \<Rightarrow> ContextReg " where + " update_ContextReg_bits v x = ( + (v (| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_ContextReg_PTEBase : ContextReg -> mword ty41*) -fun get_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word " where - " get_ContextReg_PTEBase (Mk_ContextReg (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 23 :: int)::ii) :: 41 Word.word))" +definition get_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word " where + " get_ContextReg_PTEBase v = ( + (subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 63 :: int)::ii) (( 23 :: int)::ii) :: 41 Word.word))" (*val _set_ContextReg_PTEBase : register_ref regstate register_value ContextReg -> mword ty41 -> M unit*) definition set_ContextReg_PTEBase :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(41)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_ContextReg_PTEBase r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: ContextReg) . - (let r = ((get_ContextReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 23 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_ContextReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 r) (( 63 :: int)::ii) (( 23 :: int)::ii) + ((subrange_vec_dec v (( 40 :: int)::ii) (( 0 :: int)::ii) :: 41 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_ContextReg_PTEBase : ContextReg -> mword ty41 -> ContextReg*) -fun update_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word \<Rightarrow> ContextReg " where - " update_ContextReg_PTEBase (Mk_ContextReg (v)) x = ( - Mk_ContextReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 23 :: int)::ii) x :: 64 Word.word)))" +definition update_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word \<Rightarrow> ContextReg " where + " update_ContextReg_PTEBase v x = ( + (v (| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 63 :: int)::ii) (( 23 :: int)::ii) + ((subrange_vec_dec x (( 40 :: int)::ii) (( 0 :: int)::ii) :: 41 Word.word)) + :: 64 Word.word))|)))" (*val _get_ContextReg_BadVPN2 : ContextReg -> mword ty19*) -fun get_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word " where - " get_ContextReg_BadVPN2 (Mk_ContextReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 4 :: int)::ii) :: 19 Word.word))" +definition get_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word " where + " get_ContextReg_BadVPN2 v = ( + (subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 22 :: int)::ii) (( 4 :: int)::ii) :: 19 Word.word))" (*val _set_ContextReg_BadVPN2 : register_ref regstate register_value ContextReg -> mword ty19 -> M unit*) definition set_ContextReg_BadVPN2 :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(19)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_ContextReg_BadVPN2 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: ContextReg) . - (let r = ((get_ContextReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_ContextReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 r) (( 22 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec v (( 18 :: int)::ii) (( 0 :: int)::ii) :: 19 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_ContextReg_BadVPN2 : ContextReg -> mword ty19 -> ContextReg*) -fun update_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word \<Rightarrow> ContextReg " where - " update_ContextReg_BadVPN2 (Mk_ContextReg (v)) x = ( - Mk_ContextReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" +definition update_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word \<Rightarrow> ContextReg " where + " update_ContextReg_BadVPN2 v x = ( + (v (| + ContextReg_ContextReg_chunk_0 := + ((update_subrange_vec_dec(ContextReg_ContextReg_chunk_0 v) (( 22 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec x (( 18 :: int)::ii) (( 0 :: int)::ii) :: 19 Word.word)) + :: 64 Word.word))|)))" (*val undefined_XContextReg : unit -> M XContextReg*) @@ -889,94 +986,143 @@ fun update_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word \<Righ definition undefined_XContextReg :: " unit \<Rightarrow>((register_value),(XContextReg),(exception))monad " where " undefined_XContextReg _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - internal_pick [Mk_XContextReg w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + return ((| XContextReg_XContextReg_chunk_0 = w__0 |))))" + + +(*val Mk_XContextReg : mword ty64 -> XContextReg*) +definition Mk_XContextReg :: "(64)Word.word \<Rightarrow> XContextReg " where + " Mk_XContextReg v = ( + (| XContextReg_XContextReg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -(*val _get_XContextReg : XContextReg -> mword ty64*) -fun get_XContextReg :: " XContextReg \<Rightarrow>(64)Word.word " where - " get_XContextReg (Mk_XContextReg (v)) = ( v )" +(*val _get_XContextReg_bits : XContextReg -> mword ty64*) +definition get_XContextReg_bits :: " XContextReg \<Rightarrow>(64)Word.word " where + " get_XContextReg_bits v = ( + (subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_XContextReg : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*) -definition set_XContextReg :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_XContextReg r_ref v = ( +(*val _set_XContextReg_bits : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*) + +definition set_XContextReg_bits :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_XContextReg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_XContextReg v) in + (let r = + ((r (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_XContextReg_bits : XContextReg -> mword ty64 -> XContextReg*) + +definition update_XContextReg_bits :: " XContextReg \<Rightarrow>(64)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_bits v x = ( + (v (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_XContextReg_XPTEBase : XContextReg -> mword ty31*) -fun get_XContextReg_XPTEBase :: " XContextReg \<Rightarrow>(31)Word.word " where - " get_XContextReg_XPTEBase (Mk_XContextReg (v)) = ( - (subrange_vec_dec v (( 63 :: int)::ii) (( 33 :: int)::ii) :: 31 Word.word))" +definition get_XContextReg_XPTEBase :: " XContextReg \<Rightarrow>(31)Word.word " where + " get_XContextReg_XPTEBase v = ( + (subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 63 :: int)::ii) (( 33 :: int)::ii) :: 31 Word.word))" (*val _set_XContextReg_XPTEBase : register_ref regstate register_value XContextReg -> mword ty31 -> M unit*) definition set_XContextReg_XPTEBase :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(31)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_XContextReg_XPTEBase r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . - (let r = ((get_XContextReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 33 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_XContextReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 r) (( 63 :: int)::ii) (( 33 :: int)::ii) + ((subrange_vec_dec v (( 30 :: int)::ii) (( 0 :: int)::ii) :: 31 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_XContextReg_XPTEBase : XContextReg -> mword ty31 -> XContextReg*) -fun update_XContextReg_XPTEBase :: " XContextReg \<Rightarrow>(31)Word.word \<Rightarrow> XContextReg " where - " update_XContextReg_XPTEBase (Mk_XContextReg (v)) x = ( - Mk_XContextReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 33 :: int)::ii) x :: 64 Word.word)))" +definition update_XContextReg_XPTEBase :: " XContextReg \<Rightarrow>(31)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_XPTEBase v x = ( + (v (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 63 :: int)::ii) (( 33 :: int)::ii) + ((subrange_vec_dec x (( 30 :: int)::ii) (( 0 :: int)::ii) :: 31 Word.word)) + :: 64 Word.word))|)))" (*val _get_XContextReg_XR : XContextReg -> mword ty2*) -fun get_XContextReg_XR :: " XContextReg \<Rightarrow>(2)Word.word " where - " get_XContextReg_XR (Mk_XContextReg (v)) = ( (subrange_vec_dec v (( 32 :: int)::ii) (( 31 :: int)::ii) :: 2 Word.word))" +definition get_XContextReg_XR :: " XContextReg \<Rightarrow>(2)Word.word " where + " get_XContextReg_XR v = ( + (subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 32 :: int)::ii) (( 31 :: int)::ii) :: 2 Word.word))" (*val _set_XContextReg_XR : register_ref regstate register_value XContextReg -> mword ty2 -> M unit*) definition set_XContextReg_XR :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_XContextReg_XR r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . - (let r = ((get_XContextReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 32 :: int)::ii) (( 31 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_XContextReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 r) (( 32 :: int)::ii) (( 31 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_XContextReg_XR : XContextReg -> mword ty2 -> XContextReg*) -fun update_XContextReg_XR :: " XContextReg \<Rightarrow>(2)Word.word \<Rightarrow> XContextReg " where - " update_XContextReg_XR (Mk_XContextReg (v)) x = ( - Mk_XContextReg ((update_subrange_vec_dec v (( 32 :: int)::ii) (( 31 :: int)::ii) x :: 64 Word.word)))" +definition update_XContextReg_XR :: " XContextReg \<Rightarrow>(2)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_XR v x = ( + (v (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 32 :: int)::ii) (( 31 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" (*val _get_XContextReg_XBadVPN2 : XContextReg -> mword ty27*) -fun get_XContextReg_XBadVPN2 :: " XContextReg \<Rightarrow>(27)Word.word " where - " get_XContextReg_XBadVPN2 (Mk_XContextReg (v)) = ( - (subrange_vec_dec v (( 30 :: int)::ii) (( 4 :: int)::ii) :: 27 Word.word))" +definition get_XContextReg_XBadVPN2 :: " XContextReg \<Rightarrow>(27)Word.word " where + " get_XContextReg_XBadVPN2 v = ( + (subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 30 :: int)::ii) (( 4 :: int)::ii) :: 27 Word.word))" (*val _set_XContextReg_XBadVPN2 : register_ref regstate register_value XContextReg -> mword ty27 -> M unit*) definition set_XContextReg_XBadVPN2 :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_XContextReg_XBadVPN2 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . - (let r = ((get_XContextReg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 30 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_XContextReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 r) (( 30 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_XContextReg_XBadVPN2 : XContextReg -> mword ty27 -> XContextReg*) -fun update_XContextReg_XBadVPN2 :: " XContextReg \<Rightarrow>(27)Word.word \<Rightarrow> XContextReg " where - " update_XContextReg_XBadVPN2 (Mk_XContextReg (v)) x = ( - Mk_XContextReg ((update_subrange_vec_dec v (( 30 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" +definition update_XContextReg_XBadVPN2 :: " XContextReg \<Rightarrow>(27)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_XBadVPN2 v x = ( + (v (| + XContextReg_XContextReg_chunk_0 := + ((update_subrange_vec_dec(XContextReg_XContextReg_chunk_0 v) (( 30 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 64 Word.word))|)))" definition TLBNumEntries :: " int " where @@ -1010,437 +1156,632 @@ definition MAX_PA :: " int " where definition undefined_TLBEntry :: " unit \<Rightarrow>((register_value),(TLBEntry),(exception))monad " where " undefined_TLBEntry _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 117 :: int)::ii) :: ( 117 Word.word) M) \<bind> (\<lambda> (w__0 :: 117 Word.word) . - internal_pick [Mk_TLBEntry w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 53 :: int)::ii) :: ( 53 Word.word) M) \<bind> (\<lambda> (w__0 :: 53 Word.word) . + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + return ((| TLBEntry_TLBEntry_chunk_1 = w__0, + TLBEntry_TLBEntry_chunk_0 = w__1 |)))))" + +(*val Mk_TLBEntry : mword ty117 -> TLBEntry*) -(*val _get_TLBEntry : TLBEntry -> mword ty117*) +definition Mk_TLBEntry :: "(117)Word.word \<Rightarrow> TLBEntry " where + " Mk_TLBEntry v = ( + (| TLBEntry_TLBEntry_chunk_1 = ((subrange_vec_dec v (( 116 :: int)::ii) (( 64 :: int)::ii) :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -fun get_TLBEntry :: " TLBEntry \<Rightarrow>(117)Word.word " where - " get_TLBEntry (Mk_TLBEntry (v)) = ( v )" +(*val _get_TLBEntry_bits : TLBEntry -> mword ty117*) -(*val _set_TLBEntry : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*) +definition get_TLBEntry_bits :: " TLBEntry \<Rightarrow>(117)Word.word " where + " get_TLBEntry_bits v = ( + (concat_vec ((subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 52 :: int)::ii) (( 0 :: int)::ii) :: 53 Word.word)) + ((subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 117 Word.word))" -definition set_TLBEntry :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(117)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_TLBEntry r_ref v = ( + +(*val _set_TLBEntry_bits : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*) + +definition set_TLBEntry_bits :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(117)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_TLBEntry v) in - write_reg r_ref r)))" + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 r) (( 52 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 116 :: int)::ii) (( 64 :: int)::ii) :: 53 Word.word)) + :: 53 Word.word))|))) in + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r))))" + + +(*val _update_TLBEntry_bits : TLBEntry -> mword ty117 -> TLBEntry*) + +definition update_TLBEntry_bits :: " TLBEntry \<Rightarrow>(117)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_bits v x = ( + (let v = + ((v (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 52 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 116 :: int)::ii) (( 64 :: int)::ii) :: 53 Word.word)) + :: 53 Word.word))|))) in + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))))" (*val _get_TLBEntry_pagemask : TLBEntry -> mword ty16*) -fun get_TLBEntry_pagemask :: " TLBEntry \<Rightarrow>(16)Word.word " where - " get_TLBEntry_pagemask (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 116 :: int)::ii) (( 101 :: int)::ii) :: 16 Word.word))" +definition get_TLBEntry_pagemask :: " TLBEntry \<Rightarrow>(16)Word.word " where + " get_TLBEntry_pagemask v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 52 :: int)::ii) (( 37 :: int)::ii) :: 16 Word.word))" (*val _set_TLBEntry_pagemask : register_ref regstate register_value TLBEntry -> mword ty16 -> M unit*) definition set_TLBEntry_pagemask :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_pagemask r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 116 :: int)::ii) (( 101 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 r) (( 52 :: int)::ii) (( 37 :: int)::ii) + ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 53 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_pagemask : TLBEntry -> mword ty16 -> TLBEntry*) -fun update_TLBEntry_pagemask :: " TLBEntry \<Rightarrow>(16)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_pagemask (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 116 :: int)::ii) (( 101 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_pagemask :: " TLBEntry \<Rightarrow>(16)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_pagemask v x = ( + (v (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 52 :: int)::ii) (( 37 :: int)::ii) + ((subrange_vec_dec x (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 53 Word.word))|)))" (*val _get_TLBEntry_r : TLBEntry -> mword ty2*) -fun get_TLBEntry_r :: " TLBEntry \<Rightarrow>(2)Word.word " where - " get_TLBEntry_r (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 100 :: int)::ii) (( 99 :: int)::ii) :: 2 Word.word))" +definition get_TLBEntry_r :: " TLBEntry \<Rightarrow>(2)Word.word " where + " get_TLBEntry_r v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 36 :: int)::ii) (( 35 :: int)::ii) :: 2 Word.word))" (*val _set_TLBEntry_r : register_ref regstate register_value TLBEntry -> mword ty2 -> M unit*) definition set_TLBEntry_r :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_r r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 100 :: int)::ii) (( 99 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 r) (( 36 :: int)::ii) (( 35 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 53 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_r : TLBEntry -> mword ty2 -> TLBEntry*) -fun update_TLBEntry_r :: " TLBEntry \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_r (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 100 :: int)::ii) (( 99 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_r :: " TLBEntry \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_r v x = ( + (v (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 36 :: int)::ii) (( 35 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 53 Word.word))|)))" (*val _get_TLBEntry_vpn2 : TLBEntry -> mword ty27*) -fun get_TLBEntry_vpn2 :: " TLBEntry \<Rightarrow>(27)Word.word " where - " get_TLBEntry_vpn2 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 98 :: int)::ii) (( 72 :: int)::ii) :: 27 Word.word))" +definition get_TLBEntry_vpn2 :: " TLBEntry \<Rightarrow>(27)Word.word " where + " get_TLBEntry_vpn2 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 34 :: int)::ii) (( 8 :: int)::ii) :: 27 Word.word))" (*val _set_TLBEntry_vpn2 : register_ref regstate register_value TLBEntry -> mword ty27 -> M unit*) definition set_TLBEntry_vpn2 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_vpn2 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 98 :: int)::ii) (( 72 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 r) (( 34 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 53 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_vpn2 : TLBEntry -> mword ty27 -> TLBEntry*) -fun update_TLBEntry_vpn2 :: " TLBEntry \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_vpn2 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 98 :: int)::ii) (( 72 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_vpn2 :: " TLBEntry \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_vpn2 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 34 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 53 Word.word))|)))" (*val _get_TLBEntry_asid : TLBEntry -> mword ty8*) -fun get_TLBEntry_asid :: " TLBEntry \<Rightarrow>(8)Word.word " where - " get_TLBEntry_asid (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 71 :: int)::ii) (( 64 :: int)::ii) :: 8 Word.word))" +definition get_TLBEntry_asid :: " TLBEntry \<Rightarrow>(8)Word.word " where + " get_TLBEntry_asid v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" (*val _set_TLBEntry_asid : register_ref regstate register_value TLBEntry -> mword ty8 -> M unit*) definition set_TLBEntry_asid :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_asid r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 71 :: int)::ii) (( 64 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 r) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 53 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_asid : TLBEntry -> mword ty8 -> TLBEntry*) -fun update_TLBEntry_asid :: " TLBEntry \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_asid (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 71 :: int)::ii) (( 64 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_asid :: " TLBEntry \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_asid v x = ( + (v (| + TLBEntry_TLBEntry_chunk_1 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_1 v) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 53 Word.word))|)))" (*val _get_TLBEntry_g : TLBEntry -> mword ty1*) -fun get_TLBEntry_g :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_g (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_g :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_g v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_g : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_g :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_g r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_g : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_g :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_g (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_g :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_g v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_valid : TLBEntry -> mword ty1*) -fun get_TLBEntry_valid :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_valid (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_valid :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_valid v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_valid : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_valid :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_valid r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 62 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 62 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_valid : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_valid :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_valid (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_valid :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_valid v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 62 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_caps1 : TLBEntry -> mword ty1*) -fun get_TLBEntry_caps1 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_caps1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 61 :: int)::ii) (( 61 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_caps1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_caps1 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 61 :: int)::ii) (( 61 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_caps1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_caps1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_caps1 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 61 :: int)::ii) (( 61 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 61 :: int)::ii) (( 61 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_caps1 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_caps1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_caps1 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 61 :: int)::ii) (( 61 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_caps1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_caps1 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 61 :: int)::ii) (( 61 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_capl1 : TLBEntry -> mword ty1*) -fun get_TLBEntry_capl1 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_capl1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 60 :: int)::ii) (( 60 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_capl1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_capl1 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 60 :: int)::ii) (( 60 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_capl1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_capl1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_capl1 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 60 :: int)::ii) (( 60 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 60 :: int)::ii) (( 60 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_capl1 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_capl1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_capl1 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 60 :: int)::ii) (( 60 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_capl1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_capl1 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 60 :: int)::ii) (( 60 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_pfn1 : TLBEntry -> mword ty24*) -fun get_TLBEntry_pfn1 :: " TLBEntry \<Rightarrow>(24)Word.word " where - " get_TLBEntry_pfn1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 59 :: int)::ii) (( 36 :: int)::ii) :: 24 Word.word))" +definition get_TLBEntry_pfn1 :: " TLBEntry \<Rightarrow>(24)Word.word " where + " get_TLBEntry_pfn1 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 59 :: int)::ii) (( 36 :: int)::ii) :: 24 Word.word))" (*val _set_TLBEntry_pfn1 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) definition set_TLBEntry_pfn1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_pfn1 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 59 :: int)::ii) (( 36 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 59 :: int)::ii) (( 36 :: int)::ii) + ((subrange_vec_dec v (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_pfn1 : TLBEntry -> mword ty24 -> TLBEntry*) -fun update_TLBEntry_pfn1 :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_pfn1 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 59 :: int)::ii) (( 36 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_pfn1 :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_pfn1 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 59 :: int)::ii) (( 36 :: int)::ii) + ((subrange_vec_dec x (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_c1 : TLBEntry -> mword ty3*) -fun get_TLBEntry_c1 :: " TLBEntry \<Rightarrow>(3)Word.word " where - " get_TLBEntry_c1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 35 :: int)::ii) (( 33 :: int)::ii) :: 3 Word.word))" +definition get_TLBEntry_c1 :: " TLBEntry \<Rightarrow>(3)Word.word " where + " get_TLBEntry_c1 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 35 :: int)::ii) (( 33 :: int)::ii) :: 3 Word.word))" (*val _set_TLBEntry_c1 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) definition set_TLBEntry_c1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_c1 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 35 :: int)::ii) (( 33 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 35 :: int)::ii) (( 33 :: int)::ii) + ((subrange_vec_dec v (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_c1 : TLBEntry -> mword ty3 -> TLBEntry*) -fun update_TLBEntry_c1 :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_c1 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 35 :: int)::ii) (( 33 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_c1 :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_c1 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 35 :: int)::ii) (( 33 :: int)::ii) + ((subrange_vec_dec x (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_d1 : TLBEntry -> mword ty1*) -fun get_TLBEntry_d1 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_d1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 32 :: int)::ii) (( 32 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_d1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_d1 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 32 :: int)::ii) (( 32 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_d1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_d1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_d1 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 32 :: int)::ii) (( 32 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 32 :: int)::ii) (( 32 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_d1 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_d1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_d1 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 32 :: int)::ii) (( 32 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_d1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_d1 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 32 :: int)::ii) (( 32 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_v1 : TLBEntry -> mword ty1*) -fun get_TLBEntry_v1 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_v1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_v1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_v1 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_v1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_v1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_v1 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 31 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 31 :: int)::ii) (( 31 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_v1 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_v1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_v1 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_v1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_v1 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 31 :: int)::ii) (( 31 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_caps0 : TLBEntry -> mword ty1*) -fun get_TLBEntry_caps0 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_caps0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 30 :: int)::ii) (( 30 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_caps0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_caps0 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 30 :: int)::ii) (( 30 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_caps0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_caps0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_caps0 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 30 :: int)::ii) (( 30 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 30 :: int)::ii) (( 30 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_caps0 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_caps0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_caps0 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 30 :: int)::ii) (( 30 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_caps0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_caps0 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 30 :: int)::ii) (( 30 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_capl0 : TLBEntry -> mword ty1*) -fun get_TLBEntry_capl0 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_capl0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 29 :: int)::ii) (( 29 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_capl0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_capl0 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 29 :: int)::ii) (( 29 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_capl0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_capl0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_capl0 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 29 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 29 :: int)::ii) (( 29 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_capl0 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_capl0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_capl0 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 29 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_capl0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_capl0 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 29 :: int)::ii) (( 29 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_pfn0 : TLBEntry -> mword ty24*) -fun get_TLBEntry_pfn0 :: " TLBEntry \<Rightarrow>(24)Word.word " where - " get_TLBEntry_pfn0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 28 :: int)::ii) (( 5 :: int)::ii) :: 24 Word.word))" +definition get_TLBEntry_pfn0 :: " TLBEntry \<Rightarrow>(24)Word.word " where + " get_TLBEntry_pfn0 v = ( + (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 28 :: int)::ii) (( 5 :: int)::ii) :: 24 Word.word))" (*val _set_TLBEntry_pfn0 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) definition set_TLBEntry_pfn0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_pfn0 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 28 :: int)::ii) (( 5 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 28 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec v (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_pfn0 : TLBEntry -> mword ty24 -> TLBEntry*) -fun update_TLBEntry_pfn0 :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_pfn0 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 28 :: int)::ii) (( 5 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_pfn0 :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_pfn0 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 28 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec x (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_c0 : TLBEntry -> mword ty3*) -fun get_TLBEntry_c0 :: " TLBEntry \<Rightarrow>(3)Word.word " where - " get_TLBEntry_c0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word))" +definition get_TLBEntry_c0 :: " TLBEntry \<Rightarrow>(3)Word.word " where + " get_TLBEntry_c0 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word))" (*val _set_TLBEntry_c0 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) definition set_TLBEntry_c0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_c0 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 2 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 4 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_c0 : TLBEntry -> mword ty3 -> TLBEntry*) -fun update_TLBEntry_c0 :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_c0 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 2 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_c0 :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_c0 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 4 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_d0 : TLBEntry -> mword ty1*) -fun get_TLBEntry_d0 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_d0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_d0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_d0 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_d0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_d0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_d0 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_d0 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_d0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_d0 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_d0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_d0 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_TLBEntry_v0 : TLBEntry -> mword ty1*) -fun get_TLBEntry_v0 :: " TLBEntry \<Rightarrow>(1)Word.word " where - " get_TLBEntry_v0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_TLBEntry_v0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_v0 v = ( (subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" (*val _set_TLBEntry_v0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) definition set_TLBEntry_v0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_TLBEntry_v0 r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . - (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 117 Word.word)) in - write_reg r_ref (Mk_TLBEntry r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_TLBEntry_v0 : TLBEntry -> mword ty1 -> TLBEntry*) -fun update_TLBEntry_v0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where - " update_TLBEntry_v0 (Mk_TLBEntry (v)) x = ( - Mk_TLBEntry ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 117 Word.word)))" +definition update_TLBEntry_v0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_v0 v x = ( + (v (| + TLBEntry_TLBEntry_chunk_0 := + ((update_subrange_vec_dec(TLBEntry_TLBEntry_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" definition TLBEntries :: "(((regstate),(register_value),(TLBEntry))register_ref)list " where @@ -1463,253 +1804,367 @@ definition TLBEntries :: "(((regstate),(register_value),(TLBEntry))register_ref definition undefined_StatusReg :: " unit \<Rightarrow>((register_value),(StatusReg),(exception))monad " where " undefined_StatusReg _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . - internal_pick [Mk_StatusReg w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + return ((| StatusReg_StatusReg_chunk_0 = w__0 |))))" + + +(*val Mk_StatusReg : mword ty32 -> StatusReg*) + +definition Mk_StatusReg :: "(32)Word.word \<Rightarrow> StatusReg " where + " Mk_StatusReg v = ( + (| StatusReg_StatusReg_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )" -(*val _get_StatusReg : StatusReg -> mword ty32*) +(*val _get_StatusReg_bits : StatusReg -> mword ty32*) -fun get_StatusReg :: " StatusReg \<Rightarrow>(32)Word.word " where - " get_StatusReg (Mk_StatusReg (v)) = ( v )" +definition get_StatusReg_bits :: " StatusReg \<Rightarrow>(32)Word.word " where + " get_StatusReg_bits v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))" -(*val _set_StatusReg : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*) +(*val _set_StatusReg_bits : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*) -definition set_StatusReg :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_StatusReg r_ref v = ( +definition set_StatusReg_bits :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_StatusReg v) in + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word))|))) in write_reg r_ref r)))" +(*val _update_StatusReg_bits : StatusReg -> mword ty32 -> StatusReg*) + +definition update_StatusReg_bits :: " StatusReg \<Rightarrow>(32)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_bits v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word))|)))" + + (*val _get_StatusReg_CU : StatusReg -> mword ty4*) -fun get_StatusReg_CU :: " StatusReg \<Rightarrow>(4)Word.word " where - " get_StatusReg_CU (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word))" +definition get_StatusReg_CU :: " StatusReg \<Rightarrow>(4)Word.word " where + " get_StatusReg_CU v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word))" (*val _set_StatusReg_CU : register_ref regstate register_value StatusReg -> mword ty4 -> M unit*) definition set_StatusReg_CU :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_CU r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 28 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 31 :: int)::ii) (( 28 :: int)::ii) + ((subrange_vec_dec v (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_CU : StatusReg -> mword ty4 -> StatusReg*) -fun update_StatusReg_CU :: " StatusReg \<Rightarrow>(4)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_CU (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 28 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_CU :: " StatusReg \<Rightarrow>(4)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_CU v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 31 :: int)::ii) (( 28 :: int)::ii) + ((subrange_vec_dec x (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_BEV : StatusReg -> mword ty1*) -fun get_StatusReg_BEV :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_BEV (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_BEV :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_BEV v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_BEV : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_BEV :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_BEV r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 22 :: int)::ii) (( 22 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_BEV : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_BEV :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_BEV (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_BEV :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_BEV v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_IM : StatusReg -> mword ty8*) -fun get_StatusReg_IM :: " StatusReg \<Rightarrow>(8)Word.word " where - " get_StatusReg_IM (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" +definition get_StatusReg_IM :: " StatusReg \<Rightarrow>(8)Word.word " where + " get_StatusReg_IM v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" (*val _set_StatusReg_IM : register_ref regstate register_value StatusReg -> mword ty8 -> M unit*) definition set_StatusReg_IM :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_IM r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 15 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_IM : StatusReg -> mword ty8 -> StatusReg*) -fun update_StatusReg_IM :: " StatusReg \<Rightarrow>(8)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_IM (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_IM :: " StatusReg \<Rightarrow>(8)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_IM v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_KX : StatusReg -> mword ty1*) -fun get_StatusReg_KX :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_KX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_KX :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_KX v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_KX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_KX :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_KX r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_KX : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_KX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_KX (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_KX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_KX v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_SX : StatusReg -> mword ty1*) -fun get_StatusReg_SX :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_SX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_SX :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_SX v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_SX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_SX :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_SX r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_SX : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_SX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_SX (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_SX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_SX v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_UX : StatusReg -> mword ty1*) -fun get_StatusReg_UX :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_UX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_UX :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_UX v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_UX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_UX :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_UX r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_UX : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_UX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_UX (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_UX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_UX v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_KSU : StatusReg -> mword ty2*) -fun get_StatusReg_KSU :: " StatusReg \<Rightarrow>(2)Word.word " where - " get_StatusReg_KSU (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word))" +definition get_StatusReg_KSU :: " StatusReg \<Rightarrow>(2)Word.word " where + " get_StatusReg_KSU v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word))" (*val _set_StatusReg_KSU : register_ref regstate register_value StatusReg -> mword ty2 -> M unit*) definition set_StatusReg_KSU :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_KSU r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 3 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 4 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_KSU : StatusReg -> mword ty2 -> StatusReg*) -fun update_StatusReg_KSU :: " StatusReg \<Rightarrow>(2)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_KSU (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 3 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_KSU :: " StatusReg \<Rightarrow>(2)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_KSU v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 4 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_ERL : StatusReg -> mword ty1*) -fun get_StatusReg_ERL :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_ERL (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_ERL :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_ERL v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_ERL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_ERL :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_ERL r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_ERL : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_ERL :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_ERL (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_ERL :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_ERL v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_EXL : StatusReg -> mword ty1*) -fun get_StatusReg_EXL :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_EXL (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_EXL :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_EXL v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_EXL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_EXL :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_EXL r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_EXL : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_EXL :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_EXL (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_EXL :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_EXL v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val _get_StatusReg_IE : StatusReg -> mword ty1*) -fun get_StatusReg_IE :: " StatusReg \<Rightarrow>(1)Word.word " where - " get_StatusReg_IE (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_StatusReg_IE :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_IE v = ( + (subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" (*val _set_StatusReg_IE : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) definition set_StatusReg_IE :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_StatusReg_IE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let r = ((get_StatusReg w__0 :: 32 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 32 Word.word)) in - write_reg r_ref (Mk_StatusReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" (*val _update_StatusReg_IE : StatusReg -> mword ty1 -> StatusReg*) -fun update_StatusReg_IE :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where - " update_StatusReg_IE (Mk_StatusReg (v)) x = ( - Mk_StatusReg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 32 Word.word)))" +definition update_StatusReg_IE :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_IE v x = ( + (v (| + StatusReg_StatusReg_chunk_0 := + ((update_subrange_vec_dec(StatusReg_StatusReg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" (*val execute_branch : mword ty64 -> M unit*) @@ -1747,10 +2202,10 @@ definition rGPR :: "(5)Word.word \<Rightarrow>((register_value),((64)Word.word) definition wGPR :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " wGPR idx v = ( (let i = (Word.uint idx) in - if (((i = (( 0 :: int)::ii)))) then return () - else + if (((i \<noteq> (( 0 :: int)::ii)))) then read_reg GPR_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . - write_reg GPR_ref ((update_list_dec w__0 i v :: ( 64 Word.word) list)))))" + write_reg GPR_ref ((update_list_dec w__0 i v :: ( 64 Word.word) list))) + else return () ))" @@ -1771,25 +2226,25 @@ definition wGPR :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((regi definition Exception_of_num :: " int \<Rightarrow> Exception " where " Exception_of_num arg0 = ( - (let l__81 = arg0 in - if (((l__81 = (( 0 :: int)::ii)))) then Interrupt - else if (((l__81 = (( 1 :: int)::ii)))) then TLBMod - else if (((l__81 = (( 2 :: int)::ii)))) then TLBL - else if (((l__81 = (( 3 :: int)::ii)))) then TLBS - else if (((l__81 = (( 4 :: int)::ii)))) then AdEL - else if (((l__81 = (( 5 :: int)::ii)))) then AdES - else if (((l__81 = (( 6 :: int)::ii)))) then Sys - else if (((l__81 = (( 7 :: int)::ii)))) then Bp - else if (((l__81 = (( 8 :: int)::ii)))) then ResI - else if (((l__81 = (( 9 :: int)::ii)))) then CpU - else if (((l__81 = (( 10 :: int)::ii)))) then Ov - else if (((l__81 = (( 11 :: int)::ii)))) then Tr - else if (((l__81 = (( 12 :: int)::ii)))) then C2E - else if (((l__81 = (( 13 :: int)::ii)))) then C2Trap - else if (((l__81 = (( 14 :: int)::ii)))) then XTLBRefillL - else if (((l__81 = (( 15 :: int)::ii)))) then XTLBRefillS - else if (((l__81 = (( 16 :: int)::ii)))) then XTLBInvL - else if (((l__81 = (( 17 :: int)::ii)))) then XTLBInvS + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Interrupt + else if (((p00 = (( 1 :: int)::ii)))) then TLBMod + else if (((p00 = (( 2 :: int)::ii)))) then TLBL + else if (((p00 = (( 3 :: int)::ii)))) then TLBS + else if (((p00 = (( 4 :: int)::ii)))) then AdEL + else if (((p00 = (( 5 :: int)::ii)))) then AdES + else if (((p00 = (( 6 :: int)::ii)))) then Sys + else if (((p00 = (( 7 :: int)::ii)))) then Bp + else if (((p00 = (( 8 :: int)::ii)))) then ResI + else if (((p00 = (( 9 :: int)::ii)))) then CpU + else if (((p00 = (( 10 :: int)::ii)))) then Ov + else if (((p00 = (( 11 :: int)::ii)))) then Tr + else if (((p00 = (( 12 :: int)::ii)))) then C2E + else if (((p00 = (( 13 :: int)::ii)))) then C2Trap + else if (((p00 = (( 14 :: int)::ii)))) then XTLBRefillL + else if (((p00 = (( 15 :: int)::ii)))) then XTLBRefillS + else if (((p00 = (( 16 :: int)::ii)))) then XTLBInvL + else if (((p00 = (( 17 :: int)::ii)))) then XTLBInvS else MCheck))" @@ -1892,7 +2347,7 @@ definition SignalExceptionMIPS :: " Exception \<Rightarrow>(64)Word.word \<Righ ((write_reg nextPC_ref ((sub_vec - ((add_vec vectorBase ((sign_extend1 (( 64 :: int)::ii) vectorOffset :: 64 Word.word)) :: 64 Word.word)) + ((add_vec vectorBase ((mips_sign_extend (( 64 :: int)::ii) vectorOffset :: 64 Word.word)) :: 64 Word.word)) kccBase :: 64 Word.word)) \<then> set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex :: 5 Word.word))) \<then> @@ -2051,10 +2506,10 @@ definition SignalException :: " Exception \<Rightarrow>((register_value),'o,(ex (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__1 :: 257 Word.word) . (let pcc = (capRegToCapStruct w__1) in (let (success, epcc) = (setCapOffset pcc pc) in - if success then write_reg C31_ref ((capStructToCapReg epcc :: 257 Word.word)) + if success then write_reg EPCC_ref ((capStructToCapReg epcc :: 257 Word.word)) else write_reg - C31_ref + EPCC_ref ((capStructToCapReg ((int_to_cap ((add_vec_int @@ -2063,11 +2518,11 @@ definition SignalException :: " Exception \<Rightarrow>((register_value),'o,(ex :: 64 Word.word)))) :: 257 Word.word)))))) else return () ) \<then> - (read_reg C29_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__2 :: CapReg) . + (read_reg KCC_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__2 :: CapReg) . (write_reg nextPCC_ref w__2 \<then> - (read_reg C29_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__3 :: CapReg) . + (read_reg KCC_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__3 :: CapReg) . (write_reg delayedPCC_ref w__3 \<then> - (read_reg C29_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__4 :: 257 Word.word) . + (read_reg KCC_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__4 :: 257 Word.word) . (let base = (getCapBase ((capRegToCapStruct w__4))) in SignalExceptionMIPS ex ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) base :: 64 Word.word))))))))" @@ -2094,9 +2549,9 @@ definition SignalExceptionTLB :: " Exception \<Rightarrow>(64)Word.word \<Right definition MemAccessType_of_num :: " int \<Rightarrow> MemAccessType " where " MemAccessType_of_num arg0 = ( - (let l__79 = arg0 in - if (((l__79 = (( 0 :: int)::ii)))) then Instruction - else if (((l__79 = (( 1 :: int)::ii)))) then LoadData + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Instruction + else if (((p00 = (( 1 :: int)::ii)))) then LoadData else StoreData))" @@ -2118,9 +2573,9 @@ definition undefined_MemAccessType :: " unit \<Rightarrow>((register_value),(Me definition AccessLevel_of_num :: " int \<Rightarrow> AccessLevel " where " AccessLevel_of_num arg0 = ( - (let l__77 = arg0 in - if (((l__77 = (( 0 :: int)::ii)))) then User - else if (((l__77 = (( 1 :: int)::ii)))) then Supervisor + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then User + else if (((p00 = (( 1 :: int)::ii)))) then Supervisor else Kernel))" @@ -2171,8 +2626,8 @@ definition getAccessLevel :: " unit \<Rightarrow>((register_value),(AccessLevel if w__2 then return Kernel else read_reg CP0Status_ref \<bind> (\<lambda> (w__3 :: StatusReg) . - (let p__133 = ((get_StatusReg_KSU w__3 :: 2 Word.word)) in - (let b__0 = p__133 in + (let p__31 = ((get_StatusReg_KSU w__3 :: 2 Word.word)) in + (let b__0 = p__31 in return (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then Kernel else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Supervisor else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then User @@ -2234,10 +2689,10 @@ definition incrementCP0Count :: " unit \<Rightarrow>((register_value),(unit),(e definition decode_failure_of_num :: " int \<Rightarrow> decode_failure " where " decode_failure_of_num arg0 = ( - (let l__74 = arg0 in - if (((l__74 = (( 0 :: int)::ii)))) then No_matching_pattern - else if (((l__74 = (( 1 :: int)::ii)))) then Unsupported_instruction - else if (((l__74 = (( 2 :: int)::ii)))) then Illegal_instruction + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then No_matching_pattern + else if (((p00 = (( 1 :: int)::ii)))) then Unsupported_instruction + else if (((p00 = (( 2 :: int)::ii)))) then Illegal_instruction else Internal_error))" @@ -2258,14 +2713,14 @@ definition undefined_decode_failure :: " unit \<Rightarrow>((register_value),(d definition Comparison_of_num :: " int \<Rightarrow> Comparison " where " Comparison_of_num arg0 = ( - (let l__67 = arg0 in - if (((l__67 = (( 0 :: int)::ii)))) then EQ' - else if (((l__67 = (( 1 :: int)::ii)))) then NE - else if (((l__67 = (( 2 :: int)::ii)))) then GE - else if (((l__67 = (( 3 :: int)::ii)))) then GEU - else if (((l__67 = (( 4 :: int)::ii)))) then GT' - else if (((l__67 = (( 5 :: int)::ii)))) then LE - else if (((l__67 = (( 6 :: int)::ii)))) then LT' + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then EQ' + else if (((p00 = (( 1 :: int)::ii)))) then NE + else if (((p00 = (( 2 :: int)::ii)))) then GE + else if (((p00 = (( 3 :: int)::ii)))) then GEU + else if (((p00 = (( 4 :: int)::ii)))) then GT' + else if (((p00 = (( 5 :: int)::ii)))) then LE + else if (((p00 = (( 6 :: int)::ii)))) then LT' else LTU))" @@ -2305,10 +2760,10 @@ fun compare :: " Comparison \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.wo definition WordType_of_num :: " int \<Rightarrow> WordType " where " WordType_of_num arg0 = ( - (let l__64 = arg0 in - if (((l__64 = (( 0 :: int)::ii)))) then B - else if (((l__64 = (( 1 :: int)::ii)))) then H - else if (((l__64 = (( 2 :: int)::ii)))) then W + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then B + else if (((p00 = (( 1 :: int)::ii)))) then H + else if (((p00 = (( 2 :: int)::ii)))) then W else D))" @@ -2327,6 +2782,32 @@ definition undefined_WordType :: " unit \<Rightarrow>((register_value),(WordTyp " undefined_WordType _ = ( internal_pick [B,H,W,D])" +(*val WordTypeUnaligned_of_num : integer -> WordTypeUnaligned*) + +definition WordTypeUnaligned_of_num :: " int \<Rightarrow> WordTypeUnaligned " where + " WordTypeUnaligned_of_num arg0 = ( + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then WL + else if (((p00 = (( 1 :: int)::ii)))) then WR + else if (((p00 = (( 2 :: int)::ii)))) then DL + else DR))" + + +(*val num_of_WordTypeUnaligned : WordTypeUnaligned -> integer*) + +fun num_of_WordTypeUnaligned :: " WordTypeUnaligned \<Rightarrow> int " where + " num_of_WordTypeUnaligned WL = ( (( 0 :: int)::ii))" +|" num_of_WordTypeUnaligned WR = ( (( 1 :: int)::ii))" +|" num_of_WordTypeUnaligned DL = ( (( 2 :: int)::ii))" +|" num_of_WordTypeUnaligned DR = ( (( 3 :: int)::ii))" + + +(*val undefined_WordTypeUnaligned : unit -> M WordTypeUnaligned*) + +definition undefined_WordTypeUnaligned :: " unit \<Rightarrow>((register_value),(WordTypeUnaligned),(exception))monad " where + " undefined_WordTypeUnaligned _ = ( internal_pick [WL,WR,DL,DR])" + + (*val wordWidthBytes : WordType -> integer*) fun wordWidthBytes :: " WordType \<Rightarrow> int " where @@ -2349,19 +2830,52 @@ definition isAddressAligned :: "(64)Word.word \<Rightarrow> WordType \<Rightarr alignment_width)))))" -(*val MEMr_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) +(*val MEMr_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => integer -> mword ty64 -> integer -> M (mword 'p8_times_n_)*) -definition MEMr_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where - " MEMr_wrapper addr size1 = ( - (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . - return ((reverse_endianness w__0 :: ( 'p8_times_n_::len)Word.word))))" +definition MEMr_wrapper :: " int \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where + " MEMr_wrapper (p8_times_n___tv :: int) addr size1 = ( + if (((addr = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + (read_reg UART_RVALID_ref :: ( 1 Word.word) M) \<bind> (\<lambda> rvalid . + (write_reg UART_RVALID_ref (vec_of_bits [B0] :: 1 Word.word) \<then> + (read_reg UART_RDATA_ref :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__0 :: 8 bits) . + return ((mask0 p8_times_n___tv + ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) + ((concat_vec w__0 + ((concat_vec rvalid + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 16 Word.word) + :: 23 Word.word)) + :: 24 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) + :: ( 'p8_times_n_::len)Word.word)))) + else if (((addr = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] + :: 64 Word.word)))) then + return ((mask0 p8_times_n___tv + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1, + B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] + :: 64 Word.word) + :: ( 'p8_times_n_::len)Word.word)) + else + (MEMr instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__1 . + return ((reverse_endianness w__1 :: ( 'p8_times_n_::len)Word.word))))" (*val MEMr_reserve_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) definition MEMr_reserve_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where " MEMr_reserve_wrapper addr size1 = ( - (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . + (MEMr_reserve instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . return ((reverse_endianness w__0 :: ( 'p8_times_n_::len)Word.word))))" @@ -2377,6 +2891,181 @@ definition init_cp0_state :: " unit \<Rightarrow>((register_value),(unit),(exce (*val dump_cp2_state : unit -> M unit*) +(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition extzv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " extzv (m__tv :: int) v = ( (extz_vec m__tv v :: ( 'm::len)Word.word))" + + +(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition extsv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " extsv (m__tv :: int) v = ( (exts_vec m__tv v :: ( 'm::len)Word.word))" + + +(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*) + +definition slice_mask :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where + " slice_mask (n__tv :: int) i l = ( + (let (one :: 'n bits) = ((extzv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (shiftl ((sub_vec ((shiftl one l :: ( 'n::len)Word.word)) one :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)))" + + +(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +definition is_zero_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where + " is_zero_subrange xs i j = ( + (((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0] :: 1 Word.word) :: ( 'n::len)Word.word))))" + + +(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +definition is_ones_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where + " is_ones_subrange xs i j = ( + (let (m :: 'n bits) = + ((slice_mask ((int (size xs))) j ((((j - i)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) in + (((and_vec xs m :: ( 'n::len)Word.word)) = m)))" + + +(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*) + +definition slice_slice_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word " where + " slice_slice_concat (r__tv :: int) xs i l ys i' l' = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr ((and_vec ys ((slice_mask ((int (size ys))) i' l' :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) i' + :: ( 'm::len)Word.word)) in + (or_vec ((shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)) ((extzv r__tv ys :: ( 'r::len)Word.word)) + :: ( 'r::len)Word.word))))" + + +(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*) + +definition slice_zeros_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word " where + " slice_zeros_concat (r__tv :: int) xs i l l' = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)))" + + +(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*) + +definition subrange_subrange_eq :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where + " subrange_subrange_eq xs i j ys i' j' = ( + (let xs = + ((shiftr + ((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr + ((and_vec ys + ((slice_mask ((int (size xs))) j' ((((i' - j')) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) j' + :: ( 'n::len)Word.word)) in + (xs = ys))))" + + +(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*) + +definition subrange_subrange_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('s::len)Word.word " where + " subrange_subrange_concat (s__tv :: int) xs i j ys i' j' = ( + (let xs = + ((shiftr + ((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr + ((and_vec ys + ((slice_mask ((int (size ys))) j' ((((i' - j')) + (( 1 :: int)::ii))) :: ( 'm::len)Word.word)) + :: ( 'm::len)Word.word)) j' + :: ( 'm::len)Word.word)) in + (or_vec + ((shiftl ((extzv s__tv xs :: ( 's::len)Word.word)) ((((i' - j')) + (( 1 :: int)::ii))) + :: ( 's::len)Word.word)) ((extzv s__tv ys :: ( 's::len)Word.word)) + :: ( 's::len)Word.word))))" + + +(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +definition place_subrange :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " place_subrange (m__tv :: int) xs i j shift = ( + (let xs = + ((shiftr + ((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" + + +(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +definition place_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " place_slice (m__tv :: int) xs i l shift = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" + + +(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +definition zext_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " zext_slice (m__tv :: int) xs i l = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (extzv m__tv xs :: ( 'm::len)Word.word)))" + + +(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +definition sext_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " sext_slice (m__tv :: int) xs i l = ( + (let xs = + ((arith_shiftr + ((shiftl ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) + ((((((int (size xs))) - i)) - l)) + :: ( 'n::len)Word.word)) ((((int (size xs))) - l)) + :: ( 'n::len)Word.word)) in + (extsv m__tv xs :: ( 'm::len)Word.word)))" + + +(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +definition unsigned_slice :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int " where + " unsigned_slice xs i l = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + Word.uint xs))" + + +(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +definition unsigned_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int " where + " unsigned_subrange xs i j = ( + (let xs = + ((shiftr + ((and_vec xs + ((slice_mask ((int (size xs))) j ((((i - j)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) + :: ( 'n::len)Word.word)) i + :: ( 'n::len)Word.word)) in + Word.uint xs))" + + +(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*) + +definition zext_ones :: " int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where + " zext_ones (n__tv :: int) m = ( + (let (v :: 'n bits) = ((extsv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (shiftr v ((((int (size v))) - m)) :: ( 'n::len)Word.word)))" + + (*val tlbEntryMatch : mword ty2 -> mword ty27 -> mword ty8 -> TLBEntry -> bool*) definition tlbEntryMatch :: "(2)Word.word \<Rightarrow>(27)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry \<Rightarrow> bool " where @@ -2388,7 +3077,7 @@ definition tlbEntryMatch :: "(2)Word.word \<Rightarrow>(27)Word.word \<Rightarr (let entryASID = ((get_TLBEntry_asid entry :: 8 Word.word)) in (let entryG = ((get_TLBEntry_g entry :: 1 Word.word)) in (let (vpnMask :: 27 bits) = - ((not_vec ((zero_extend1 (( 27 :: int)::ii) entryMask :: 27 Word.word)) :: 27 Word.word)) in + ((not_vec ((mips_zero_extend (( 27 :: int)::ii) entryMask :: 27 Word.word)) :: 27 Word.word)) in (((bits_to_bool entryValid)) \<and> ((((((r = entryR))) \<and> ((((((((and_vec vpn2 vpnMask :: 27 Word.word)) = ((and_vec entryVPN vpnMask :: 27 Word.word))))) \<and> ((((((asid = entryASID))) \<or> ((bits_to_bool entryG))))))))))))))))))))" @@ -2470,7 +3159,7 @@ definition TLBTranslate2 :: "(64)Word.word \<Rightarrow> MemAccessType \<Righta (SignalExceptionTLB TLBMod vAddr :: (( 64 Word.word * bool)) M) else (let (res :: 64 bits) = - ((zero_extend1 (( 64 :: int)::ii) + ((mips_zero_extend (( 64 :: int)::ii) ((subrange_subrange_concat (((((((( 23 :: int)::ii) - ((((evenOddBit - (( 12 :: int)::ii))) - (( 1 :: int)::ii))))) @@ -2514,7 +3203,7 @@ definition TLBTranslateC :: "(64)Word.word \<Rightarrow> MemAccessType \<Righta ((subrange_vec_dec vAddr (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word)) :: 32 Word.word)) :: 64 Word.word))) - else + else if (((b__1 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then (Kernel, Some ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -2524,7 +3213,8 @@ definition TLBTranslateC :: "(64)Word.word \<Rightarrow> MemAccessType \<Righta ((subrange_vec_dec vAddr (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word)) :: 32 Word.word)) :: 64 Word.word))) - | (g__131, g__132) => (Kernel, None) + else (case (True, b__1) of (g__29, g__30) => (Kernel, None) ) + | (g__29, g__30) => (Kernel, None) ) else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then (Kernel, @@ -2563,14 +3253,14 @@ definition TLBTranslate :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightar definition CPtrCmpOp_of_num :: " int \<Rightarrow> CPtrCmpOp " where " CPtrCmpOp_of_num arg0 = ( - (let l__57 = arg0 in - if (((l__57 = (( 0 :: int)::ii)))) then CEQ - else if (((l__57 = (( 1 :: int)::ii)))) then CNE - else if (((l__57 = (( 2 :: int)::ii)))) then CLT - else if (((l__57 = (( 3 :: int)::ii)))) then CLE - else if (((l__57 = (( 4 :: int)::ii)))) then CLTU - else if (((l__57 = (( 5 :: int)::ii)))) then CLEU - else if (((l__57 = (( 6 :: int)::ii)))) then CEXEQ + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then CEQ + else if (((p00 = (( 1 :: int)::ii)))) then CNE + else if (((p00 = (( 2 :: int)::ii)))) then CLT + else if (((p00 = (( 3 :: int)::ii)))) then CLE + else if (((p00 = (( 4 :: int)::ii)))) then CLTU + else if (((p00 = (( 5 :: int)::ii)))) then CLEU + else if (((p00 = (( 6 :: int)::ii)))) then CEXEQ else CNEXEQ))" @@ -2597,10 +3287,10 @@ definition undefined_CPtrCmpOp :: " unit \<Rightarrow>((register_value),(CPtrCm definition ClearRegSet_of_num :: " int \<Rightarrow> ClearRegSet " where " ClearRegSet_of_num arg0 = ( - (let l__54 = arg0 in - if (((l__54 = (( 0 :: int)::ii)))) then GPLo - else if (((l__54 = (( 1 :: int)::ii)))) then GPHi - else if (((l__54 = (( 2 :: int)::ii)))) then CLo + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then GPLo + else if (((p00 = (( 1 :: int)::ii)))) then GPHi + else if (((p00 = (( 2 :: int)::ii)))) then CLo else CHi))" @@ -2625,13 +3315,13 @@ definition undefined_CapStruct :: " unit \<Rightarrow>((register_value),(CapStr " undefined_CapStruct _ = ( undefined_bool () \<bind> (\<lambda> (w__0 :: bool) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 24 :: int)::ii) :: ( 24 Word.word) M) \<bind> (\<lambda> (w__2 :: 24 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 24 :: int)::ii) :: ( 24 Word.word) M) \<bind> (\<lambda> (w__2 :: 24 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: 4 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: 4 bits) . undefined_bool () \<bind> (\<lambda> (w__5 :: bool) . undefined_bool () \<bind> (\<lambda> (w__6 :: bool) . undefined_bool () \<bind> (\<lambda> (w__7 :: bool) . @@ -2645,11 +3335,11 @@ definition undefined_CapStruct :: " unit \<Rightarrow>((register_value),(CapStr undefined_bool () \<bind> (\<lambda> (w__15 :: bool) . undefined_bool () \<bind> (\<lambda> (w__16 :: bool) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 bits) . return ((| CapStruct_tag = w__0, CapStruct_padding = w__1, CapStruct_otype = w__2, @@ -2678,7 +3368,7 @@ definition default_cap :: " CapStruct " where CapStruct_padding = ((zeros0 (( 8 :: int)::ii) () :: 8 Word.word)), CapStruct_otype = ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word)), CapStruct_uperms = ((ones (( 16 :: int)::ii) () :: 16 Word.word)), - CapStruct_perm_reserved11_14 = ((ones (( 4 :: int)::ii) () :: 4 Word.word)), + CapStruct_perm_reserved11_14 = ((zeros0 (( 4 :: int)::ii) () :: 4 Word.word)), CapStruct_access_system_regs = True, CapStruct_permit_unseal = True, CapStruct_permit_ccall = True, @@ -2724,8 +3414,7 @@ definition memBitsToCapBits :: " bool \<Rightarrow>(256)Word.word \<Rightarrow> definition setCapPerms :: " CapStruct \<Rightarrow>(31)Word.word \<Rightarrow> CapStruct " where " setCapPerms cap perms = ( (cap (| - CapStruct_uperms := ((subrange_vec_dec perms (( 30 :: int)::ii) (( 15 :: int)::ii) :: 16 Word.word)), CapStruct_perm_reserved11_14 := - ((subrange_vec_dec perms (( 14 :: int)::ii) (( 11 :: int)::ii) :: 4 Word.word)), CapStruct_access_system_regs := + CapStruct_uperms := ((subrange_vec_dec perms (( 30 :: int)::ii) (( 15 :: int)::ii) :: 16 Word.word)), CapStruct_access_system_regs := ((bit_to_bool ((access_vec_dec perms (( 10 :: int)::ii))))), CapStruct_permit_unseal := ((bit_to_bool ((access_vec_dec perms (( 9 :: int)::ii))))), CapStruct_permit_ccall := ((bit_to_bool ((access_vec_dec perms (( 8 :: int)::ii))))), CapStruct_permit_seal := @@ -2801,738 +3490,70 @@ definition setCapBounds :: " CapStruct \<Rightarrow>(64)Word.word \<Rightarrow> definition undefined_ast :: " unit \<Rightarrow>((register_value),(ast),(exception))monad " where " undefined_ast _ = ( + undefined_CPtrCmpOp () \<bind> (\<lambda> (u_0 :: CPtrCmpOp) . + undefined_ClearRegSet () \<bind> (\<lambda> (u_1 :: ClearRegSet) . + undefined_Comparison () \<bind> (\<lambda> (u_2 :: Comparison) . + undefined_WordType () \<bind> (\<lambda> (u_3 :: WordType) . + undefined_bool () \<bind> (\<lambda> (u_5 :: bool) . + undefined_bool () \<bind> (\<lambda> (u_4 :: bool) . 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5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__351 :: 5 Word.word) . - undefined_unit () \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 26 :: int)::ii) :: ( 26 Word.word) M) \<bind> (\<lambda> (u_16 :: 26 bits) . internal_pick - [DADDIU (w__0,w__1,w__2),DADDU (w__3,w__4,w__5),DADDI (w__6,w__7,w__8),DADD (w__9,w__10,w__11),ADD (w__12,w__13,w__14),ADDI (w__15,w__16,w__17),ADDU (w__18,w__19,w__20),ADDIU (w__21,w__22,w__23),DSUBU (w__24,w__25,w__26),DSUB (w__27,w__28,w__29),SUB (w__30,w__31,w__32),SUBU (w__33,w__34,w__35),AND0 (w__36,w__37,w__38),ANDI (w__39,w__40,w__41),OR0 (w__42,w__43,w__44),ORI (w__45,w__46,w__47),NOR (w__48,w__49,w__50),XOR0 (w__51,w__52,w__53),XORI (w__54,w__55,w__56),LUI (w__57,w__58),DSLL (w__59,w__60,w__61),DSLL32 (w__62,w__63,w__64),DSLLV (w__65,w__66,w__67),DSRA (w__68,w__69,w__70),DSRA32 (w__71,w__72,w__73),DSRAV (w__74,w__75,w__76),DSRL (w__77,w__78,w__79),DSRL32 (w__80,w__81,w__82),DSRLV (w__83,w__84,w__85),SLL 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(w__180,w__181,w__182,w__183,w__184),LWL (w__185,w__186,w__187),LWR (w__188,w__189,w__190),SWL (w__191,w__192,w__193),SWR (w__194,w__195,w__196),LDL (w__197,w__198,w__199),LDR (w__200,w__201,w__202),SDL (w__203,w__204,w__205),SDR (w__206,w__207,w__208),CACHE (w__209,w__210,w__211),PREF (w__212,w__213,w__214),SYNC () ,MFC0 (w__215,w__216,w__217,w__218),HCF () ,MTC0 (w__219,w__220,w__221,w__222),TLBWI () ,TLBWR () ,TLBR () ,TLBP () ,RDHWR (w__223,w__224),ERET () ,CGetPerm (w__225,w__226),CGetType (w__227,w__228),CGetBase (w__229,w__230),CGetLen (w__231,w__232),CGetTag (w__233,w__234),CGetSealed (w__235,w__236),CGetOffset (w__237,w__238),CGetAddr (w__239,w__240),CGetPCC w__241,CGetPCCSetOffset (w__242,w__243),CGetCause w__244,CSetCause w__245,CReadHwr (w__246,w__247),CWriteHwr (w__248,w__249),CAndPerm (w__250,w__251,w__252),CToPtr (w__253,w__254,w__255),CSub (w__256,w__257,w__258),CPtrCmp (w__259,w__260,w__261,w__262),CIncOffset (w__263,w__264,w__265),CIncOffsetImmediate (w__266,w__267,w__268),CSetOffset (w__269,w__270,w__271),CSetBounds (w__272,w__273,w__274),CSetBoundsImmediate (w__275,w__276,w__277),CSetBoundsExact (w__278,w__279,w__280),CClearTag (w__281,w__282),CMOVX (w__283,w__284,w__285,w__286),ClearRegs (w__287,w__288),CFromPtr (w__289,w__290,w__291),CBuildCap (w__292,w__293,w__294),CCopyType (w__295,w__296,w__297),CCheckPerm (w__298,w__299),CCheckType (w__300,w__301),CTestSubset (w__302,w__303,w__304),CSeal (w__305,w__306,w__307),CCSeal (w__308,w__309,w__310),CUnseal (w__311,w__312,w__313),CCall (w__314,w__315,w__316),CReturn () ,CBX (w__317,w__318,w__319),CBZ (w__320,w__321,w__322),CJALR (w__323,w__324,w__325),CLoad (w__326,w__327,w__328,w__329,w__330,w__331,w__332),CStore (w__333,w__334,w__335,w__336,w__337,w__338,w__339),CSC (w__340,w__341,w__342,w__343,w__344,w__345),CLC (w__346,w__347,w__348,w__349,w__350),C2Dump w__351,RI () ])))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + [DADDIU (u_8,u_7,u_6),DADDU (u_9,u_8,u_7),DADDI (u_8,u_7,u_15),DADD (u_9,u_8,u_7),ADD (u_9,u_8,u_7),ADDI (u_8,u_7,u_15),ADDU (u_9,u_8,u_7),ADDIU (u_8,u_7,u_15),DSUBU (u_9,u_8,u_7),DSUB (u_9,u_8,u_7),SUB (u_9,u_8,u_7),SUBU (u_9,u_8,u_7),AND0 (u_9,u_8,u_7),ANDI (u_8,u_7,u_15),OR0 (u_9,u_8,u_7),ORI (u_8,u_7,u_15),NOR (u_9,u_8,u_7),XOR0 (u_9,u_8,u_7),XORI (u_8,u_7,u_15),LUI (u_7,u_6),DSLL (u_9,u_8,u_7),DSLL32 (u_9,u_8,u_7),DSLLV (u_9,u_8,u_7),DSRA (u_9,u_8,u_7),DSRA32 (u_9,u_8,u_7),DSRAV (u_9,u_8,u_7),DSRL (u_9,u_8,u_7),DSRL32 (u_9,u_8,u_7),DSRLV (u_9,u_8,u_7),SLL (u_9,u_8,u_7),SLLV (u_9,u_8,u_7),SRA (u_9,u_8,u_7),SRAV (u_9,u_8,u_7),SRL (u_9,u_8,u_7),SRLV (u_9,u_8,u_7),SLT (u_9,u_8,u_7),SLTI (u_8,u_7,u_15),SLTU (u_9,u_8,u_7),SLTIU (u_8,u_7,u_15),MOVN (u_9,u_8,u_7),MOVZ (u_9,u_8,u_7),MFHI u_7,MFLO u_7,MTHI u_7,MTLO u_7,MUL (u_9,u_8,u_7),MULT (u_8,u_7),MULTU (u_8,u_7),DMULT (u_8,u_7),DMULTU (u_8,u_7),MADD (u_8,u_7),MADDU (u_8,u_7),MSUB (u_8,u_7),MSUBU (u_8,u_7),DIV (u_8,u_7),DIVU (u_8,u_7),DDIV (u_8,u_7),DDIVU (u_8,u_7),J u_16,JAL u_16,JR u_7,JALR (u_8,u_7),BEQ (u_8,u_7,u_6,u_5,u_4),BCMPZ (u_7,u_6,u_2,u_5,u_4),SYSCALL u_11,BREAK u_11,WAIT u_11,TRAPREG (u_8,u_7,u_2),TRAPIMM (u_7,u_6,u_2),Load (u_3,u_5,u_4,u_8,u_7,u_6),Store (u_3,u_4,u_8,u_7,u_6),LWL (u_8,u_7,u_15),LWR (u_8,u_7,u_15),SWL (u_8,u_7,u_15),SWR (u_8,u_7,u_15),LDL (u_8,u_7,u_15),LDR (u_8,u_7,u_15),SDL (u_8,u_7,u_15),SDR (u_8,u_7,u_15),CACHE (u_8,u_7,u_15),SYNC u_11,MFC0 (u_8,u_7,u_12,u_4),HCF u_11,MTC0 (u_8,u_7,u_12,u_4),TLBWI u_11,TLBWR u_11,TLBR u_11,TLBP u_11,RDHWR (u_8,u_7),ERET u_11,CGetPerm (u_8,u_7),CGetType (u_8,u_7),CGetBase (u_8,u_7),CGetLen (u_8,u_7),CGetTag (u_8,u_7),CGetSealed (u_8,u_7),CGetOffset (u_8,u_7),CGetAddr (u_8,u_7),CGetPCC u_7,CGetPCCSetOffset (u_8,u_7),CGetCause u_7,CSetCause u_7,CReadHwr (u_8,u_7),CWriteHwr (u_8,u_7),CAndPerm (u_9,u_8,u_7),CToPtr (u_9,u_8,u_7),CSub (u_9,u_8,u_7),CPtrCmp (u_9,u_8,u_7,u_0),CIncOffset (u_9,u_8,u_7),CIncOffsetImmediate (u_8,u_7,u_14),CSetOffset (u_9,u_8,u_7),CSetBounds (u_9,u_8,u_7),CSetBoundsImmediate (u_8,u_7,u_14),CSetBoundsExact (u_9,u_8,u_7),CClearTag (u_8,u_7),CMOVX (u_9,u_8,u_7,u_4),ClearRegs (u_1,u_15),CFromPtr (u_9,u_8,u_7),CBuildCap (u_9,u_8,u_7),CCopyType (u_9,u_8,u_7),CCheckPerm (u_8,u_7),CCheckType (u_8,u_7),CTestSubset (u_9,u_8,u_7),CSeal (u_9,u_8,u_7),CCSeal (u_9,u_8,u_7),CUnseal (u_9,u_8,u_7),CCall (u_8,u_7,u_14),CReturn u_11,CBX (u_7,u_15,u_4),CBZ (u_7,u_15,u_4),CJALR (u_8,u_7,u_4),CLoad (u_9,u_8,u_7,u_13,u_5,u_3,u_4),CStore (u_10,u_9,u_8,u_7,u_13,u_3,u_4),CSC (u_10,u_9,u_8,u_7,u_14,u_4),CLC (u_9,u_8,u_7,u_15,u_4),C2Dump u_7,RI u_11]))))))))))))))))))" (*val execute : ast -> M unit*) (*val decode : mword ty32 -> maybe ast*) -definition DDC :: "(5)Word.word " where - " DDC = ( (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))" - +definition IDCNO :: "(5)Word.word " where + " IDCNO = ( (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word))" -definition IDC :: "(5)Word.word " where - " IDC = ( (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word))" +definition KR1CNO :: "(5)Word.word " where + " KR1CNO = ( (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word))" -definition KR1C :: "(5)Word.word " where - " KR1C = ( (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word))" +definition KR2CNO :: "(5)Word.word " where + " KR2CNO = ( (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word))" -definition KR2C :: "(5)Word.word " where - " KR2C = ( (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word))" +definition KCCNO :: "(5)Word.word " where + " KCCNO = ( (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word))" -definition KCC :: "(5)Word.word " where - " KCC = ( (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word))" +definition KDCNO :: "(5)Word.word " where + " KDCNO = ( (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word))" -definition KDC :: "(5)Word.word " where - " KDC = ( (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word))" - -definition EPCC :: "(5)Word.word " where - " EPCC = ( (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))" +definition EPCCNO :: "(5)Word.word " where + " EPCCNO = ( (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))" definition CapRegs :: "(((regstate),(register_value),((257)Word.word))register_ref)list " where " CapRegs = ( [C31_ref,C30_ref,C29_ref,C28_ref,C27_ref,C26_ref,C25_ref,C24_ref,C23_ref,C22_ref,C21_ref,C20_ref, C19_ref,C18_ref,C17_ref,C16_ref,C15_ref,C14_ref,C13_ref,C12_ref,C11_ref,C10_ref,C09_ref,C08_ref, - C07_ref,C06_ref,C05_ref,C04_ref,C03_ref,C02_ref,C01_ref,C00_ref])" + C07_ref,C06_ref,C05_ref,C04_ref,C03_ref,C02_ref,C01_ref,DDC_ref])" definition max_otype :: " int " where @@ -3545,11 +3566,29 @@ definition have_cp2 :: " bool " where (* This function reads a given capability register and returns its contents converted to a CapStruct. +If the argument is zero then the null capability is returned. *) (*val readCapReg : mword ty5 -> M CapStruct*) definition readCapReg :: "(5)Word.word \<Rightarrow>((register_value),(CapStruct),(exception))monad " where " readCapReg n = ( + if (((n = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then return null_cap + else + (let i = (Word.uint n) in + (reg_deref ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) + :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + return ((capRegToCapStruct w__0)))))" + + +(* +This is the same as readCapReg except that when the argument is zero the value of DDC is returned +instead of the null capability. This is used for instructions that expect an address, where using +null would always generate an exception. +*) +(*val readCapRegDDC : mword ty5 -> M CapStruct*) + +definition readCapRegDDC :: "(5)Word.word \<Rightarrow>((register_value),(CapStruct),(exception))monad " where + " readCapRegDDC n = ( (let i = (Word.uint n) in (reg_deref ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . @@ -3560,39 +3599,41 @@ definition readCapReg :: "(5)Word.word \<Rightarrow>((register_value),(CapStruc definition writeCapReg :: "(5)Word.word \<Rightarrow> CapStruct \<Rightarrow>((register_value),(unit),(exception))monad " where " writeCapReg n cap = ( - (let i = (Word.uint n) in - write_reg - ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) - ((capStructToCapReg cap :: 257 Word.word))))" + if (((n = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then return () + else + (let i = (Word.uint n) in + write_reg + ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) + ((capStructToCapReg cap :: 257 Word.word))))" (*val CapEx_of_num : integer -> CapEx*) definition CapEx_of_num :: " int \<Rightarrow> CapEx " where " CapEx_of_num arg0 = ( - (let l__32 = arg0 in - if (((l__32 = (( 0 :: int)::ii)))) then CapEx_None - else if (((l__32 = (( 1 :: int)::ii)))) then CapEx_LengthViolation - else if (((l__32 = (( 2 :: int)::ii)))) then CapEx_TagViolation - else if (((l__32 = (( 3 :: int)::ii)))) then CapEx_SealViolation - else if (((l__32 = (( 4 :: int)::ii)))) then CapEx_TypeViolation - else if (((l__32 = (( 5 :: int)::ii)))) then CapEx_CallTrap - else if (((l__32 = (( 6 :: int)::ii)))) then CapEx_ReturnTrap - else if (((l__32 = (( 7 :: int)::ii)))) then CapEx_TSSUnderFlow - else if (((l__32 = (( 8 :: int)::ii)))) then CapEx_UserDefViolation - else if (((l__32 = (( 9 :: int)::ii)))) then CapEx_TLBNoStoreCap - else if (((l__32 = (( 10 :: int)::ii)))) then CapEx_InexactBounds - else if (((l__32 = (( 11 :: int)::ii)))) then CapEx_GlobalViolation - else if (((l__32 = (( 12 :: int)::ii)))) then CapEx_PermitExecuteViolation - else if (((l__32 = (( 13 :: int)::ii)))) then CapEx_PermitLoadViolation - else if (((l__32 = (( 14 :: int)::ii)))) then CapEx_PermitStoreViolation - else if (((l__32 = (( 15 :: int)::ii)))) then CapEx_PermitLoadCapViolation - else if (((l__32 = (( 16 :: int)::ii)))) then CapEx_PermitStoreCapViolation - else if (((l__32 = (( 17 :: int)::ii)))) then CapEx_PermitStoreLocalCapViolation - else if (((l__32 = (( 18 :: int)::ii)))) then CapEx_PermitSealViolation - else if (((l__32 = (( 19 :: int)::ii)))) then CapEx_AccessSystemRegsViolation - else if (((l__32 = (( 20 :: int)::ii)))) then CapEx_PermitCCallViolation - else if (((l__32 = (( 21 :: int)::ii)))) then CapEx_AccessCCallIDCViolation + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then CapEx_None + else if (((p00 = (( 1 :: int)::ii)))) then CapEx_LengthViolation + else if (((p00 = (( 2 :: int)::ii)))) then CapEx_TagViolation + else if (((p00 = (( 3 :: int)::ii)))) then CapEx_SealViolation + else if (((p00 = (( 4 :: int)::ii)))) then CapEx_TypeViolation + else if (((p00 = (( 5 :: int)::ii)))) then CapEx_CallTrap + else if (((p00 = (( 6 :: int)::ii)))) then CapEx_ReturnTrap + else if (((p00 = (( 7 :: int)::ii)))) then CapEx_TSSUnderFlow + else if (((p00 = (( 8 :: int)::ii)))) then CapEx_UserDefViolation + else if (((p00 = (( 9 :: int)::ii)))) then CapEx_TLBNoStoreCap + else if (((p00 = (( 10 :: int)::ii)))) then CapEx_InexactBounds + else if (((p00 = (( 11 :: int)::ii)))) then CapEx_GlobalViolation + else if (((p00 = (( 12 :: int)::ii)))) then CapEx_PermitExecuteViolation + else if (((p00 = (( 13 :: int)::ii)))) then CapEx_PermitLoadViolation + else if (((p00 = (( 14 :: int)::ii)))) then CapEx_PermitStoreViolation + else if (((p00 = (( 15 :: int)::ii)))) then CapEx_PermitLoadCapViolation + else if (((p00 = (( 16 :: int)::ii)))) then CapEx_PermitStoreCapViolation + else if (((p00 = (( 17 :: int)::ii)))) then CapEx_PermitStoreLocalCapViolation + else if (((p00 = (( 18 :: int)::ii)))) then CapEx_PermitSealViolation + else if (((p00 = (( 19 :: int)::ii)))) then CapEx_AccessSystemRegsViolation + else if (((p00 = (( 20 :: int)::ii)))) then CapEx_PermitCCallViolation + else if (((p00 = (( 21 :: int)::ii)))) then CapEx_AccessCCallIDCViolation else CapEx_PermitUnsealViolation))" @@ -3665,59 +3706,99 @@ fun CapExCode :: " CapEx \<Rightarrow>(8)Word.word " where definition undefined_CapCauseReg :: " unit \<Rightarrow>((register_value),(CapCauseReg),(exception))monad " where " undefined_CapCauseReg _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__0 :: 16 Word.word) . - internal_pick [Mk_CapCauseReg w__0]))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__0 :: 16 Word.word) . + return ((| CapCauseReg_CapCauseReg_chunk_0 = w__0 |))))" + +(*val Mk_CapCauseReg : mword ty16 -> CapCauseReg*) -fun get_CapCauseReg :: " CapCauseReg \<Rightarrow>(16)Word.word " where - " get_CapCauseReg (Mk_CapCauseReg (v)) = ( v )" +definition Mk_CapCauseReg :: "(16)Word.word \<Rightarrow> CapCauseReg " where + " Mk_CapCauseReg v = ( + (| CapCauseReg_CapCauseReg_chunk_0 = ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) |) )" -definition set_CapCauseReg :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_CapCauseReg r_ref v = ( +definition get_CapCauseReg_bits :: " CapCauseReg \<Rightarrow>(16)Word.word " where + " get_CapCauseReg_bits v = ( + (subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 v) (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word))" + + +definition set_CapCauseReg_bits :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CapCauseReg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_CapCauseReg v) in + (let r = + ((r (| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 r) (( 15 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 16 Word.word))|))) in write_reg r_ref r)))" -fun get_CapCauseReg_ExcCode :: " CapCauseReg \<Rightarrow>(8)Word.word " where - " get_CapCauseReg_ExcCode (Mk_CapCauseReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" +definition update_CapCauseReg_bits :: " CapCauseReg \<Rightarrow>(16)Word.word \<Rightarrow> CapCauseReg " where + " update_CapCauseReg_bits v x = ( + (v (| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 v) (( 15 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 16 Word.word))|)))" + + +definition get_CapCauseReg_ExcCode :: " CapCauseReg \<Rightarrow>(8)Word.word " where + " get_CapCauseReg_ExcCode v = ( + (subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" definition set_CapCauseReg_ExcCode :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CapCauseReg_ExcCode r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CapCauseReg) . - (let r = ((get_CapCauseReg w__0 :: 16 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 16 Word.word)) in - write_reg r_ref (Mk_CapCauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 r) (( 15 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 16 Word.word))|))) in + write_reg r_ref r)))" -fun update_CapCauseReg_ExcCode :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg " where - " update_CapCauseReg_ExcCode (Mk_CapCauseReg (v)) x = ( - Mk_CapCauseReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 16 Word.word)))" +definition update_CapCauseReg_ExcCode :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg " where + " update_CapCauseReg_ExcCode v x = ( + (v (| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 v) (( 15 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 16 Word.word))|)))" (*val _get_CapCauseReg_RegNum : CapCauseReg -> mword ty8*) -fun get_CapCauseReg_RegNum :: " CapCauseReg \<Rightarrow>(8)Word.word " where - " get_CapCauseReg_RegNum (Mk_CapCauseReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" +definition get_CapCauseReg_RegNum :: " CapCauseReg \<Rightarrow>(8)Word.word " where + " get_CapCauseReg_RegNum v = ( + (subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" (*val _set_CapCauseReg_RegNum : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*) definition set_CapCauseReg_RegNum :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_CapCauseReg_RegNum r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: CapCauseReg) . - (let r = ((get_CapCauseReg w__0 :: 16 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 16 Word.word)) in - write_reg r_ref (Mk_CapCauseReg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 16 Word.word))|))) in + write_reg r_ref r)))" (*val _update_CapCauseReg_RegNum : CapCauseReg -> mword ty8 -> CapCauseReg*) -fun update_CapCauseReg_RegNum :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg " where - " update_CapCauseReg_RegNum (Mk_CapCauseReg (v)) x = ( - Mk_CapCauseReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 16 Word.word)))" +definition update_CapCauseReg_RegNum :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg " where + " update_CapCauseReg_RegNum v x = ( + (v (| + CapCauseReg_CapCauseReg_chunk_0 := + ((update_subrange_vec_dec(CapCauseReg_CapCauseReg_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 16 Word.word))|)))" (*val execute_branch_pcc : CapStruct -> M unit*) @@ -3735,9 +3816,9 @@ definition execute_branch_pcc :: " CapStruct \<Rightarrow>((register_value),(un definition ERETHook :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " ERETHook _ = ( - (read_reg C31_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: CapReg) . + (read_reg EPCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: CapReg) . (write_reg nextPCC_ref w__0 \<then> - (read_reg C31_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__1 :: CapReg) . write_reg delayedPCC_ref w__1)))" + (read_reg EPCC_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__1 :: CapReg) . write_reg delayedPCC_ref w__1)))" (*val raise_c2_exception8 : forall 'o. CapEx -> mword ty8 -> M 'o*) @@ -3757,7 +3838,7 @@ definition raise_c2_exception8 :: " CapEx \<Rightarrow>(8)Word.word \<Rightarro definition raise_c2_exception :: " CapEx \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),'o,(exception))monad " where " raise_c2_exception capEx regnum = ( (let reg8 = ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) regnum :: 8 Word.word)) in - if ((((((capEx = CapEx_AccessSystemRegsViolation))) \<and> (((regnum = IDC)))))) then + if ((((((capEx = CapEx_AccessSystemRegsViolation))) \<and> (((regnum = IDCNO)))))) then raise_c2_exception8 CapEx_AccessCCallIDCViolation reg8 else raise_c2_exception8 capEx reg8))" @@ -3786,11 +3867,11 @@ The following function should be called before reading or writing any capability definition register_inaccessible :: "(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " register_inaccessible r = ( or_boolM - (and_boolM (return (((r = IDC)))) + (and_boolM (return (((r = IDCNO)))) ((read_reg inCCallDelay_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__0 :: 1 Word.word) . return ((bits_to_bool w__0))))) (and_boolM - (return ((((((r = KR1C))) \<or> ((((((r = KR2C))) \<or> ((((((r = KDC))) \<or> ((((((r = KCC))) \<or> (((r = EPCC)))))))))))))))) + (return ((((((r = KR1CNO))) \<or> ((((((r = KR2CNO))) \<or> ((((((r = KDCNO))) \<or> ((((((r = KCCNO))) \<or> (((r = EPCCNO)))))))))))))))) (pcc_access_system_regs () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2))))))" @@ -3798,44 +3879,42 @@ definition register_inaccessible :: "(5)Word.word \<Rightarrow>((register_value definition MEMr_tagged :: "(64)Word.word \<Rightarrow>((register_value),(bool*(256)Word.word),(exception))monad " where " MEMr_tagged addr = ( - (assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> - read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . - (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \<bind> (\<lambda> data . - (let ((cast_0 :: bool), (cast_1 :: 256 Word.word)) = (tag, (reverse_endianness data :: 256 Word.word)) in - return (cast_0, (Word.ucast cast_1 :: 256 Word.word))))))" + (assert_exp (((((((Word.uint addr)) mod cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + read_tag_bool instance_Sail2_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . + (MEMr instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \<bind> (\<lambda> data . + return (tag, (reverse_endianness data :: 256 Word.word)))))" (*val MEMr_tagged_reserve : mword ty64 -> M (bool * mword ty256)*) definition MEMr_tagged_reserve :: "(64)Word.word \<Rightarrow>((register_value),(bool*(256)Word.word),(exception))monad " where " MEMr_tagged_reserve addr = ( - (assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> - read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . - (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \<bind> (\<lambda> data . - (let ((cast_0 :: bool), (cast_1 :: 256 Word.word)) = (tag, (reverse_endianness data :: 256 Word.word)) in - return (cast_0, (Word.ucast cast_1 :: 256 Word.word))))))" + (assert_exp (((((((Word.uint addr)) mod cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + read_tag_bool instance_Sail2_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . + (MEMr_reserve instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \<bind> (\<lambda> data . + return (tag, (reverse_endianness data :: 256 Word.word)))))" (*val MEMw_tagged : mword ty64 -> bool -> mword ty256 -> M unit*) definition MEMw_tagged :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>(256)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " MEMw_tagged addr tag data = ( - ((assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> - MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then> - MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \<then> write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag )" + ((assert_exp (((((((Word.uint addr)) mod cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + MEMea instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then> + MEMval instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \<then> write_tag_bool + instance_Sail2_values_Bitvector_Machine_word_mword_dict addr tag )" (*val MEMw_tagged_conditional : mword ty64 -> bool -> mword ty256 -> M bool*) definition MEMw_tagged_conditional :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>(256)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " MEMw_tagged_conditional addr tag data = ( - ((assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> - MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then> + ((assert_exp (((((((Word.uint addr)) mod cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + MEMea_conditional instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then> MEMval_conditional - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \<bind> (\<lambda> success . + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \<bind> (\<lambda> success . (if success then write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag else return () ) \<then> return success))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict addr tag else return () ) \<then> return success))" definition cap_addr_mask :: "(64)Word.word " where @@ -3863,9 +3942,9 @@ definition MEMw_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_t :: 64 Word.word)) :: 64 Word.word)) cap_addr_mask :: 64 Word.word))))) ('''') \<then> - MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1) \<then> - MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ledata) \<then> write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False))" + MEMea instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1) \<then> + MEMval instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ledata) \<then> write_tag_bool + instance_Sail2_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False))" (*val MEMw_conditional_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M bool*) @@ -3879,47 +3958,87 @@ definition MEMw_conditional_wrapper :: "(64)Word.word \<Rightarrow> int \<Right :: 64 Word.word)) :: 64 Word.word)) cap_addr_mask :: 64 Word.word))))) ('''') \<then> - MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1) \<then> + MEMea_conditional instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1) \<then> MEMval_conditional - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data :: ( 'p8_times_n_::len)Word.word))) \<bind> (\<lambda> success . + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data :: ( 'p8_times_n_::len)Word.word))) \<bind> (\<lambda> success . (if success then write_tag_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False + instance_Sail2_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False else return () ) \<then> return success))" -(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*) +(*val checkDDCPerms : CapStruct -> MemAccessType -> M unit*) -definition addrWrapper :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow> WordType \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where - " addrWrapper addr accessType width = ( - (let capno = ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)) in - readCapReg capno \<bind> (\<lambda> cap . - ((if ((\<not>(CapStruct_tag cap))) then raise_c2_exception CapEx_TagViolation capno - else if(CapStruct_sealed cap) then raise_c2_exception CapEx_SealViolation capno +definition checkDDCPerms :: " CapStruct \<Rightarrow> MemAccessType \<Rightarrow>((register_value),(unit),(exception))monad " where + " checkDDCPerms (ddc :: CapStruct) (accessType :: MemAccessType) = ( + (if ((\<not>(CapStruct_tag ddc))) then + raise_c2_exception CapEx_TagViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + else if(CapStruct_sealed ddc) then + raise_c2_exception CapEx_SealViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) else return () ) \<then> (case accessType of - Instruction => - if ((\<not>(CapStruct_permit_execute cap))) then - raise_c2_exception CapEx_PermitExecuteViolation capno - else return () + Instruction => assert_exp False ('''') | LoadData => - if ((\<not>(CapStruct_permit_load cap))) then raise_c2_exception CapEx_PermitLoadViolation capno + if ((\<not>(CapStruct_permit_load ddc))) then + raise_c2_exception CapEx_PermitLoadViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) else return () | StoreData => - if ((\<not>(CapStruct_permit_store cap))) then raise_c2_exception CapEx_PermitStoreViolation capno + if ((\<not>(CapStruct_permit_store ddc))) then + raise_c2_exception CapEx_PermitStoreViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) else return () - )) \<then> - ((let cursor = (getCapCursor cap) in - (let vAddr = (hardware_mod ((cursor + ((Word.uint addr)))) ((pow2 (( 64 :: int)::ii)))) in + ))" + + +(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*) + +definition addrWrapper :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow> WordType \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " addrWrapper addr accessType width = ( + (read_reg DDC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + (let ddc = (capRegToCapStruct w__0) in + checkDDCPerms ddc accessType \<then> + ((let cursor = (getCapCursor ddc) in + (let vAddr = (((cursor + ((Word.uint addr)))) mod ((pow2 (( 64 :: int)::ii)))) in (let size1 = (wordWidthBytes width) in - (let base = (getCapBase cap) in - (let top1 = (getCapTop cap) in + (let base = (getCapBase ddc) in + (let top1 = (getCapTop ddc) in if ((((vAddr + size1)) > top1)) then - (raise_c2_exception CapEx_LengthViolation capno :: ( 64 Word.word) M) - else if ((vAddr < base)) then (raise_c2_exception CapEx_LengthViolation capno :: ( 64 Word.word) M) + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + :: ( 64 Word.word) M) + else if ((vAddr < base)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + :: ( 64 Word.word) M) else return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)))))))))))" +(*val addrWrapperUnaligned : mword ty64 -> MemAccessType -> WordTypeUnaligned -> M (mword ty64)*) + +definition addrWrapperUnaligned :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow> WordTypeUnaligned \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " addrWrapperUnaligned addr accessType width = ( + (read_reg DDC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + (let ddc = (capRegToCapStruct w__0) in + checkDDCPerms ddc accessType \<then> + ((let cursor = (getCapCursor ddc) in + (let vAddr = (((cursor + ((Word.uint addr)))) mod ((pow2 (( 64 :: int)::ii)))) in + (let woffset = (vAddr mod (( 4 :: int)::ii)) in + (let doffset = (vAddr mod (( 8 :: int)::ii)) in + (let ((waddr :: ii), (size1 :: ii)) = + ((case width of + WL => (vAddr, (( 4 :: int)::ii) - woffset) + | WR => (vAddr - woffset, woffset + (( 1 :: int)::ii)) + | DL => (vAddr, (( 8 :: int)::ii) - doffset) + | DR => (vAddr - doffset, doffset + (( 1 :: int)::ii)) + )) in + (let base = (getCapBase ddc) in + (let top1 = (getCapTop ddc) in + if ((((waddr + size1)) > top1)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + :: ( 64 Word.word) M) + else if ((waddr < base)) then + (raise_c2_exception CapEx_LengthViolation (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + :: ( 64 Word.word) M) + else return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)))))))))))))" + + (*val TranslatePC : mword ty64 -> M (mword ty64)*) definition TranslatePC :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where @@ -3964,13 +4083,22 @@ definition checkCP2usable :: " unit \<Rightarrow>((register_value),(unit),(exce definition init_cp2_state :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " init_cp2_state _ = ( (let defaultBits = ((capStructToCapReg default_cap :: 257 Word.word)) in - ((write_reg PCC_ref defaultBits \<then> + (let nullBits = ((capStructToCapReg null_cap :: 257 Word.word)) in + ((((((((((write_reg PCC_ref defaultBits \<then> write_reg nextPCC_ref defaultBits) \<then> write_reg delayedPCC_ref defaultBits) \<then> - (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + write_reg DDC_ref defaultBits) \<then> + write_reg KCC_ref defaultBits) \<then> + write_reg EPCC_ref defaultBits) \<then> + write_reg KDC_ref nullBits) \<then> + write_reg KR1C_ref nullBits) \<then> + write_reg KR2C_ref nullBits) \<then> + write_reg CTLSP_ref nullBits) \<then> + write_reg CTLSU_ref nullBits) \<then> + (foreachM (index_list (( 1 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () (\<lambda> i unit_var . (let idx = ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) in - writeCapReg idx default_cap)))))" + writeCapReg idx null_cap))))))" definition cp2_next_pc :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where @@ -3995,34 +4123,29 @@ definition capToString :: " CapStruct \<Rightarrow>((register_value),(string),( (((op@) (if(CapStruct_sealed cap) then (''1'') else (''0'')) (((op@) ('' perms:'') (((op@) - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict + ((string_of_bits ((concat_vec (vec_of_bits [B0] :: 1 Word.word) ((getCapPerms cap :: 31 Word.word)) :: 32 Word.word)))) (((op@) ('' type:'') - (((op@) ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict(CapStruct_otype cap))) + (((op@) ((string_of_bits(CapStruct_otype cap))) (((op@) ('' offset:'') (((op@) - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict + ((string_of_bits ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapOffset cap)) :: 64 Word.word)))) (((op@) ('' base:'') (((op@) - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict + ((string_of_bits ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cap)) :: 64 Word.word)))) (((op@) ('' length:'') - ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict + ((string_of_bits ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) @@ -4035,24 +4158,48 @@ definition dump_cp2_state :: " unit \<Rightarrow>((register_value),(unit),(exce " dump_cp2_state _ = ( (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . capToString ((capRegToCapStruct w__0)) \<bind> (\<lambda> (w__1 :: string) . - (let (_ :: unit) = (prerr_endline (((op@) (''DEBUG CAP PCC'') w__1))) in - (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP PCC'') w__1))) in + ((foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () (\<lambda> i unit_var . readCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) \<bind> (\<lambda> (w__2 :: CapStruct) . capToString w__2 \<bind> (\<lambda> (w__3 :: string) . return ((let _ = - (prerr_endline (((op@) (''DEBUG CAP REG '') (((op@) ((string_of_int + (print_endline (((op@) (''DEBUG CAP REG '') (((op@) ((string_of_int instance_Show_Show_Num_integer_dict i)) w__3))))) in - () ))))))))))" + () )))))) \<then> + (read_reg DDC_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__4 :: 257 Word.word) . + capToString ((capRegToCapStruct w__4)) \<bind> (\<lambda> (w__5 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 00'') w__5))) in + (read_reg CTLSU_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__6 :: 257 Word.word) . + capToString ((capRegToCapStruct w__6)) \<bind> (\<lambda> (w__7 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 01'') w__7))) in + (read_reg CTLSP_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__8 :: 257 Word.word) . + capToString ((capRegToCapStruct w__8)) \<bind> (\<lambda> (w__9 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 08'') w__9))) in + (read_reg KR1C_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__10 :: 257 Word.word) . + capToString ((capRegToCapStruct w__10)) \<bind> (\<lambda> (w__11 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 22'') w__11))) in + (read_reg KR2C_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__12 :: 257 Word.word) . + capToString ((capRegToCapStruct w__12)) \<bind> (\<lambda> (w__13 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 23'') w__13))) in + (read_reg KCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__14 :: 257 Word.word) . + capToString ((capRegToCapStruct w__14)) \<bind> (\<lambda> (w__15 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 29'') w__15))) in + (read_reg KDC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__16 :: 257 Word.word) . + capToString ((capRegToCapStruct w__16)) \<bind> (\<lambda> (w__17 :: string) . + (let (_ :: unit) = (print_endline (((op@) (''DEBUG CAP HWREG 30'') w__17))) in + (read_reg EPCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__18 :: 257 Word.word) . + capToString ((capRegToCapStruct w__18)) \<bind> (\<lambda> (w__19 :: string) . + return ((print_endline (((op@) (''DEBUG CAP HWREG 31'') w__19)))))))))))))))))))))))))))))))" (*val extendLoad : forall 'sz . Size 'sz => mword 'sz -> bool -> mword ty64*) definition extendLoad :: "('sz::len)Word.word \<Rightarrow> bool \<Rightarrow>(64)Word.word " where " extendLoad memResult sign = ( - if sign then (sign_extend1 (( 64 :: int)::ii) memResult :: 64 Word.word) - else (zero_extend1 (( 64 :: int)::ii) memResult :: 64 Word.word))" + if sign then (mips_sign_extend (( 64 :: int)::ii) memResult :: 64 Word.word) + else (mips_zero_extend (( 64 :: int)::ii) memResult :: 64 Word.word))" (*val TLBWriteEntry : mword ty6 -> M unit*) @@ -4489,10 +4636,6 @@ definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in Some (BCMPZ (rs,imm,LE,False,True)))) - else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, - B1,B1,B0,B0,B1,B1,B0,B0] - :: 32 Word.word)))) then - Some (SYSCALL_THREAD_START () ) else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word))))))) then Some (SYSCALL () ) else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word))))))) then @@ -4669,11 +4812,6 @@ definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where (let (op1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in Some (CACHE (base,op1,imm))))) - else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1] :: 6 Word.word)))) then - (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in - (let (op1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in - (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in - Some (PREF (base,op1,imm))))) else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 11 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 21 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1] :: 6 Word.word))))))) then Some (SYNC () ) @@ -5267,13 +5405,19 @@ definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in (let (offset :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in - Some (CLC (cd1,cb,rt,offset,False)))))) + Some (CLC (cd1,cb,rt,(mips_sign_extend (( 16 :: int)::ii) offset :: 16 Word.word),False)))))) else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] :: 11 Word.word))))))) then (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in Some (CLC (cd1,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0] - :: 11 Word.word),True)))) + B0,B0,B0,B0,B0,B0,B0, + B0,B0] + :: 16 Word.word),True)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1] :: 6 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CLC (cd1,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,False))))) else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0] :: 16 Word.word))))))) then (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in @@ -5286,7 +5430,7 @@ definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where definition execute_XORI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_XORI rs rt imm = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - wGPR rt ((xor_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + wGPR rt ((xor_vec w__0 ((mips_zero_extend (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" (*val execute_XOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5301,7 +5445,7 @@ definition execute_XOR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (*val execute_WAIT : unit -> M unit*) definition execute_WAIT :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_WAIT g__121 = ( + " execute_WAIT g__19 = ( (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . write_reg nextPC_ref w__0))" @@ -5321,7 +5465,7 @@ definition execute_TRAPREG :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightar definition execute_TRAPIMM :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> Comparison \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_TRAPIMM rs imm cmp = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . - (let (imm_val :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let (imm_val :: 64 bits) = ((mips_sign_extend (( 64 :: int)::ii) imm :: 64 Word.word)) in (let condition = (compare cmp rs_val imm_val) in if condition then SignalException Tr else return () ))))" @@ -5330,7 +5474,7 @@ definition execute_TRAPIMM :: "(5)Word.word \<Rightarrow>(16)Word.word \<Righta (*val execute_TLBWR : unit -> M unit*) definition execute_TLBWR :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_TLBWR g__125 = ( + " execute_TLBWR g__23 = ( (checkCP0Access () \<then> (read_reg TLBRandom_ref :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: 6 Word.word) . TLBWriteEntry w__0))" @@ -5338,7 +5482,7 @@ definition execute_TLBWR :: " unit \<Rightarrow>((register_value),(unit),(excep (*val execute_TLBWI : unit -> M unit*) definition execute_TLBWI :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_TLBWI g__124 = ( + " execute_TLBWI g__22 = ( (checkCP0Access () \<then> (read_reg TLBIndex_ref :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: 6 Word.word) . TLBWriteEntry w__0))" @@ -5346,7 +5490,7 @@ definition execute_TLBWI :: " unit \<Rightarrow>((register_value),(unit),(excep (*val execute_TLBR : unit -> M unit*) definition execute_TLBR :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_TLBR g__126 = ( + " execute_TLBR g__24 = ( (checkCP0Access () \<then> (read_reg TLBIndex_ref :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: TLBIndexT) . (let i = (Word.uint w__0) in @@ -5374,10 +5518,10 @@ definition execute_TLBR :: " unit \<Rightarrow>((register_value),(unit),(except (*val execute_TLBP : unit -> M unit*) definition execute_TLBP :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_TLBP g__127 = ( + " execute_TLBP g__25 = ( (checkCP0Access () \<then> read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . - (tlbSearch ((get_TLBEntryHiReg w__0 :: 64 Word.word)) :: ( ( 6 Word.word)option) M) \<bind> (\<lambda> result . + (tlbSearch ((get_TLBEntryHiReg_bits w__0 :: 64 Word.word)) :: ( ( 6 Word.word)option) M) \<bind> (\<lambda> result . (case result of Some (idx) => write_reg TLBProbe_ref (vec_of_bits [B0] :: 1 Word.word) \<then> write_reg TLBIndex_ref idx @@ -5392,7 +5536,7 @@ definition execute_TLBP :: " unit \<Rightarrow>((register_value),(unit),(except definition execute_Store :: " WordType \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_Store width conditional base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + (addrWrapper ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) StoreData width :: ( 64 Word.word) M) \<bind> (\<lambda> (vAddr :: 64 bits) . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . @@ -5403,19 +5547,14 @@ definition execute_Store :: " WordType \<Rightarrow> bool \<Rightarrow>(5)Word. (read_reg CP0LLBit_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . (if ((bit_to_bool ((access_vec_dec w__1 (( 0 :: int)::ii))))) then (case width of - B => - MEMw_conditional_wrapper pAddr (( 1 :: int)::ii) - ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) - | H => - MEMw_conditional_wrapper pAddr (( 2 :: int)::ii) - ((subrange_vec_dec rt_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) - | W => + W => MEMw_conditional_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec rt_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) | D => MEMw_conditional_wrapper pAddr (( 8 :: int)::ii) rt_val + | _ => throw (Error_internal_error () ) ) else return False) \<bind> (\<lambda> (success :: bool) . - wGPR rt ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + wGPR rt ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) else (case width of B => MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) @@ -5425,22 +5564,16 @@ definition execute_Store :: " WordType \<Rightarrow> bool \<Rightarrow>(5)Word. ))))))" -(*val execute_SYSCALL_THREAD_START : unit -> unit*) - -definition execute_SYSCALL_THREAD_START :: " unit \<Rightarrow> unit " where - " execute_SYSCALL_THREAD_START g__117 = ( () )" - - (*val execute_SYSCALL : unit -> M unit*) definition execute_SYSCALL :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_SYSCALL g__119 = ( SignalException Sys )" + " execute_SYSCALL g__17 = ( SignalException Sys )" (*val execute_SYNC : unit -> M unit*) definition execute_SYNC :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_SYNC g__122 = ( MEM_sync () )" + " execute_SYNC g__20 = ( MEM_sync () )" (*val execute_SWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) @@ -5448,8 +5581,8 @@ definition execute_SYNC :: " unit \<Rightarrow>((register_value),(unit),(except definition execute_SWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_SWR base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) - StoreData W + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) StoreData WR :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . (let wordAddr = @@ -5472,8 +5605,8 @@ definition execute_SWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> definition execute_SWL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_SWL base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) - StoreData W + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) StoreData WL :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . @@ -5495,10 +5628,10 @@ definition execute_SUBU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> opB . if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) else wGPR rd - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((sub_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 32 Word.word)) @@ -5513,19 +5646,21 @@ definition execute_SUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> opB . if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) else (let (temp33 :: 33 bits) = ((sub_vec - ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) - ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 33 Word.word)) + ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 33 Word.word)) :: 33 Word.word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 :: int)::ii))))) ((bit_to_bool ((access_vec_dec temp33 (( 31 :: int)::ii))))))) then SignalException Ov else wGPR rd - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec temp33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec temp33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" @@ -5538,12 +5673,12 @@ definition execute_SRLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in if ((NotWordVal temp)) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) else (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in (shift_bits_right - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . - wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" (*val execute_SRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5553,12 +5688,12 @@ definition execute_SRL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . if ((NotWordVal temp)) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) else (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in (shift_bits_right - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . - wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" (*val execute_SRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5570,12 +5705,12 @@ definition execute_SRAV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in if ((NotWordVal temp)) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) else (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . - wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" (*val execute_SRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5585,12 +5720,12 @@ definition execute_SRA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . if ((NotWordVal temp)) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) else (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . - wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" (*val execute_SLTU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5600,7 +5735,7 @@ definition execute_SLTU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . wGPR rd - ((zero_extend1 (( 64 :: int)::ii) + ((mips_zero_extend (( 64 :: int)::ii) (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word)) :: 64 Word.word)))))" @@ -5611,9 +5746,9 @@ definition execute_SLTU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow definition execute_SLTIU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_SLTIU rs rt imm = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . - (let (immext :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let (immext :: 64 bits) = ((mips_sign_extend (( 64 :: int)::ii) imm :: 64 Word.word)) in wGPR rt - ((zero_extend1 (( 64 :: int)::ii) + ((mips_zero_extend (( 64 :: int)::ii) (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word)) :: 64 Word.word)))))" @@ -5627,7 +5762,7 @@ definition execute_SLTI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let rs_val = (Word.sint w__0) in wGPR rt - ((zero_extend1 (( 64 :: int)::ii) + ((mips_zero_extend (( 64 :: int)::ii) (if ((rs_val < imm_val)) then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word)) :: 64 Word.word))))))" @@ -5640,7 +5775,7 @@ definition execute_SLT :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd - ((zero_extend1 (( 64 :: int)::ii) + ((mips_zero_extend (( 64 :: int)::ii) (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word)) :: 64 Word.word)))))" @@ -5654,8 +5789,8 @@ definition execute_SLLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let rt32 = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . - wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" (*val execute_SLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5664,8 +5799,8 @@ definition execute_SLL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> " execute_SLL rt rd sa = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let rt32 = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . - wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + wGPR rd ((mips_sign_extend (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" (*val execute_SDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) @@ -5673,8 +5808,8 @@ definition execute_SLL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> definition execute_SDR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_SDR base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) - StoreData D + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) StoreData DR :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . @@ -5705,8 +5840,8 @@ definition execute_SDR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> definition execute_SDL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_SDL base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) - StoreData D + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) StoreData DL :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . @@ -5731,7 +5866,7 @@ definition execute_SDL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (*val execute_RI : unit -> M unit*) definition execute_RI :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_RI g__130 = ( SignalException ResI )" + " execute_RI g__28 = ( SignalException ResI )" (*val execute_RDHWR : mword ty5 -> mword ty5 -> M unit*) @@ -5741,7 +5876,8 @@ definition execute_RDHWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro getAccessLevel () \<bind> (\<lambda> accessLevel . (let (haveAccessLevel :: bool) = (accessLevel = Kernel) in read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . - (let (haveCU0 :: bool) = (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 0 :: int)::ii)))) in + (let (haveCU0 :: bool) = + (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 0 :: int)::ii)))) in (let rdi = (Word.uint rd) in (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . (let (haveHWREna :: bool) = (B1 = ((access_vec_dec w__1 rdi))) in @@ -5749,32 +5885,26 @@ definition execute_RDHWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro else return () ) \<then> ((let b__146 = rd in (if (((b__146 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then - return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) else if (((b__146 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) then - return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) else if (((b__146 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) then (read_reg CP0Count_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . - return ((zero_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))) + return ((mips_zero_extend (( 64 :: int)::ii) w__2 :: 64 Word.word))) else if (((b__146 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) then - return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) else if (((b__146 = (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))) then (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) else (SignalException ResI :: ( 64 Word.word) M)) \<bind> (\<lambda> (temp :: 64 bits) . wGPR rt temp)))))))))))" -(*val execute_PREF : mword ty5 -> mword ty5 -> mword ty16 -> unit*) - -definition execute_PREF :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> unit " where - " execute_PREF base op1 imm = ( () )" - - (*val execute_ORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) definition execute_ORI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_ORI rs rt imm = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - wGPR rt ((or_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + wGPR rt ((or_vec w__0 ((mips_zero_extend (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" (*val execute_OR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5803,17 +5933,19 @@ definition execute_MULTU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))) \<bind> (\<lambda> (result :: 64 bits) . write_reg HI_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) \<then> write_reg LO_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))))))" (*val execute_MULT : mword ty5 -> mword ty5 -> M unit*) @@ -5824,17 +5956,19 @@ definition execute_MULT :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))) \<bind> (\<lambda> (result :: 64 bits) . write_reg HI_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) \<then> write_reg LO_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))))))" (*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -5844,16 +5978,16 @@ definition execute_MUL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (let (result :: 64 bits) = - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) :: 64 Word.word)) in (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else - return ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + return ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" @@ -5877,204 +6011,93 @@ definition execute_MTHI :: "(5)Word.word \<Rightarrow>((register_value),(unit), definition execute_MTC0 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(3)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_MTC0 rt rd sel double = ( (checkCP0Access () \<then> - (rGPR rt :: ( 64 Word.word) M)) \<bind> (\<lambda> reg_val . - (case (rd, sel) of - (b__108, b__109) => - if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> - (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - write_reg TLBIndex_ref - ((mask0 (( 6 :: int):: ii) reg_val :: 6 Word.word)) else - if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and> - (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - return () else - if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) - \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - set_TLBEntryLoReg TLBEntryLo0_ref reg_val else - if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) - \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - set_TLBEntryLoReg TLBEntryLo1_ref reg_val else - if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - set_ContextReg_PTEBase TLBContext_ref - ((subrange_vec_dec reg_val (( 63 :: int):: ii) - (( 23 :: int):: ii) :: 41 Word.word)) else - if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__109 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then - write_reg CP0UserLocal_ref reg_val else - if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) - \<and> - (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - write_reg TLBPageMask_ref - ((subrange_vec_dec reg_val (( 28 :: int):: ii) - (( 13 :: int):: ii) :: 16 Word.word)) else - if ((((((b__108 = - (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) - \<and> - (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - write_reg TLBWired_ref - ((mask0 (( 6 :: int):: ii) reg_val :: 6 Word.word)) - \<then> write_reg TLBRandom_ref TLBIndexMax else - if ((((((b__108 = - (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) - \<and> - (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - write_reg CP0HWREna_ref - ((concat_vec - ((subrange_vec_dec reg_val (( 31 :: int):: ii) - (( 29 :: int):: ii) :: 3 Word.word)) - ((concat_vec - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0] :: 25 Word.word) - ((subrange_vec_dec reg_val (( 3 :: int):: ii) - (( 0 :: int):: ii) :: 4 Word.word)) - :: 29 Word.word)) :: 32 Word.word)) else - if ((((((b__108 = - (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - return () else - if ((((((b__108 = - (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - write_reg CP0Count_ref - ((subrange_vec_dec reg_val (( 31 :: int):: ii) - (( 0 :: int):: ii) :: 32 Word.word)) else - if ((((((b__108 = - (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (set_TLBEntryHiReg_R TLBEntryHi_ref - ((subrange_vec_dec reg_val (( 63 :: int):: ii) - (( 62 :: int):: ii) :: 2 Word.word)) \<then> - set_TLBEntryHiReg_VPN2 TLBEntryHi_ref - ((subrange_vec_dec reg_val (( 39 :: int):: ii) - (( 13 :: int):: ii) :: 27 Word.word))) - \<then> - set_TLBEntryHiReg_ASID TLBEntryHi_ref - ((subrange_vec_dec reg_val (( 7 :: int):: ii) - (( 0 :: int):: ii) :: 8 Word.word)) else - if ((((((b__108 = - (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (write_reg CP0Compare_ref - ((subrange_vec_dec reg_val (( 31 :: int):: ii) - (( 0 :: int):: ii) :: 32 Word.word)) - \<then> read_reg CP0Cause_ref) \<bind> - (\<lambda> (w__0 :: CauseReg) . - set_CauseReg_IP CP0Cause_ref - ((and_vec - ((get_CauseReg_IP w__0 :: 8 Word.word)) - (vec_of_bits [B0,B1,B1,B1,B1,B1,B1,B1] :: 8 Word.word) - :: 8 Word.word))) else - if ((((((b__108 = - (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - ((((((((set_StatusReg_CU CP0Status_ref - ((subrange_vec_dec reg_val - (( 31 :: int):: ii) - (( 28 :: int):: ii) :: 4 Word.word)) - \<then> - set_StatusReg_BEV CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 22 :: int):: ii))) :: 1 Word.word))) - \<then> - set_StatusReg_IM CP0Status_ref - ((subrange_vec_dec reg_val - (( 15 :: int):: ii) - (( 8 :: int):: ii) :: 8 Word.word))) - \<then> - set_StatusReg_KX CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 7 :: int):: ii))) :: 1 Word.word))) - \<then> - set_StatusReg_SX CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 6 :: int):: ii))) :: 1 Word.word))) - \<then> - set_StatusReg_UX CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 5 :: int):: ii))) :: 1 Word.word))) - \<then> - set_StatusReg_KSU CP0Status_ref - ((subrange_vec_dec reg_val - (( 4 :: int):: ii) - (( 3 :: int):: ii) :: 2 Word.word))) - \<then> - set_StatusReg_ERL CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 2 :: int):: ii))) :: 1 Word.word))) - \<then> - set_StatusReg_EXL CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 1 :: int):: ii))) :: 1 Word.word))) - \<then> - set_StatusReg_IE CP0Status_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 0 :: int):: ii))) :: 1 Word.word)) - else - if ((((((b__108 = - (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (set_CauseReg_IV CP0Cause_ref - ((cast_unit_vec0 - ((access_vec_dec reg_val - (( 23 :: int):: ii))) :: 1 Word.word)) - \<then> read_reg CP0Cause_ref) \<bind> - (\<lambda> (w__1 :: CauseReg) . - (let ip = ((get_CauseReg_IP w__1 :: 8 Word.word)) in - set_CauseReg_IP CP0Cause_ref - ((concat_vec - ((subrange_vec_dec ip - (( 7 :: int):: ii) - (( 2 :: int):: ii) :: 6 Word.word)) - ((subrange_vec_dec reg_val - (( 9 :: int):: ii) - (( 8 :: int):: ii) :: 2 Word.word)) - :: 8 Word.word)))) else - if ((((((b__108 = - (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - write_reg CP0EPC_ref reg_val else - if ((((((b__108 = - (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - return () else - if ((((((b__108 = - (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__109 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - set_XContextReg_XPTEBase - TLBXContext_ref - ((subrange_vec_dec reg_val - (( 63 :: int):: ii) - (( 33 :: int):: ii) :: 31 Word.word)) - else write_reg CP0ErrorEPC_ref reg_val - )))" + (rGPR rt :: ( 64 Word.word) M)) \<bind> (\<lambda> reg_val . + (case (rd, sel) of + (b__108, b__109) => + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBIndex_ref ((mask0 (( 6 :: int)::ii) reg_val :: 6 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () + else if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_TLBEntryLoReg_bits TLBEntryLo0_ref reg_val + else if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_TLBEntryLoReg_bits TLBEntryLo1_ref reg_val + else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_ContextReg_PTEBase TLBContext_ref + ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 23 :: int)::ii) :: 41 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + write_reg CP0UserLocal_ref reg_val + else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBPageMask_ref ((subrange_vec_dec reg_val (( 28 :: int)::ii) (( 13 :: int)::ii) :: 16 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBWired_ref ((mask0 (( 6 :: int)::ii) reg_val :: 6 Word.word)) \<then> + write_reg TLBRandom_ref TLBIndexMax + else if ((((((b__108 = (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg + CP0HWREna_ref + ((concat_vec ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 29 :: int)::ii) :: 3 Word.word)) + ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0] + :: 25 Word.word) ((subrange_vec_dec reg_val (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) + :: 29 Word.word)) + :: 32 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () + else if ((((((b__108 = (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0Count_ref ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (set_TLBEntryHiReg_R TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word)) \<then> + set_TLBEntryHiReg_VPN2 TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))) \<then> + set_TLBEntryHiReg_ASID TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (write_reg CP0Compare_ref ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) \<then> + read_reg CP0Cause_ref) \<bind> (\<lambda> (w__0 :: CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((and_vec ((get_CauseReg_IP w__0 :: 8 Word.word)) + (vec_of_bits [B0,B1,B1,B1,B1,B1,B1,B1] :: 8 Word.word) + :: 8 Word.word))) + else if ((((((b__108 = (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + ((((((((set_StatusReg_CU CP0Status_ref ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) \<then> + set_StatusReg_BEV CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 22 :: int)::ii))) :: 1 Word.word))) \<then> + set_StatusReg_IM CP0Status_ref ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))) \<then> + set_StatusReg_KX CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 7 :: int)::ii))) :: 1 Word.word))) \<then> + set_StatusReg_SX CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 6 :: int)::ii))) :: 1 Word.word))) \<then> + set_StatusReg_UX CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 5 :: int)::ii))) :: 1 Word.word))) \<then> + set_StatusReg_KSU CP0Status_ref ((subrange_vec_dec reg_val (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word))) \<then> + set_StatusReg_ERL CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 2 :: int)::ii))) :: 1 Word.word))) \<then> + set_StatusReg_EXL CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 1 :: int)::ii))) :: 1 Word.word))) \<then> + set_StatusReg_IE CP0Status_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 0 :: int)::ii))) :: 1 Word.word)) + else if ((((((b__108 = (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (set_CauseReg_IV CP0Cause_ref + ((cast_unit_vec0 ((access_vec_dec reg_val (( 23 :: int)::ii))) :: 1 Word.word)) \<then> + read_reg CP0Cause_ref) \<bind> (\<lambda> (w__1 :: CauseReg) . + (let ip = ((get_CauseReg_IP w__1 :: 8 Word.word)) in + set_CauseReg_IP CP0Cause_ref + ((concat_vec ((subrange_vec_dec ip (( 7 :: int)::ii) (( 2 :: int)::ii) :: 6 Word.word)) + ((subrange_vec_dec reg_val (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word)) + :: 8 Word.word)))) + else if ((((((b__108 = (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0EPC_ref reg_val + else if ((((((b__108 = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0ConfigK0_ref ((subrange_vec_dec reg_val (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) + else if ((((((b__108 = (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_XContextReg_XPTEBase TLBXContext_ref + ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 33 :: int)::ii) :: 31 Word.word)) + else if ((((((b__108 = (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))) \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0ErrorEPC_ref reg_val + else SignalException ResI + )))" (*val execute_MSUBU : mword ty5 -> mword ty5 -> M unit*) @@ -6085,7 +6108,7 @@ definition execute_MSUBU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) @@ -6100,10 +6123,12 @@ definition execute_MSUBU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro :: 64 Word.word)) in write_reg HI_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) \<then> write_reg LO_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)))))))))" (*val execute_MSUB : mword ty5 -> mword ty5 -> M unit*) @@ -6114,7 +6139,7 @@ definition execute_MSUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) @@ -6129,10 +6154,12 @@ definition execute_MSUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow :: 64 Word.word)) in write_reg HI_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) \<then> write_reg LO_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)))))))))" (*val execute_MOVZ : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -6179,483 +6206,184 @@ definition execute_MFHI :: "(5)Word.word \<Rightarrow>((register_value),(unit), definition execute_MFC0 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(3)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_MFC0 rt rd sel double = ( - (checkCP0Access () \<then> - (case (rd, sel) of - (b__48, b__49) => - if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> - (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg TLBIndex_ref :: ( 6 Word.word) M) \<bind> - (\<lambda> (w__0 :: TLBIndexT) . - (let (idx :: 31 bits) = ((zero_extend1 (( 31 :: int):: ii) w__0 :: 31 Word.word)) in - (read_reg TLBProbe_ref :: ( 1 Word.word) M) \<bind> - (\<lambda> (w__1 :: 1 bits) . - return - ((concat_vec - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 32 Word.word) - ((concat_vec w__1 idx :: 32 Word.word)) :: 64 Word.word))))) - else - if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and> - (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg TLBRandom_ref :: ( 6 Word.word) M) \<bind> - (\<lambda> (w__2 :: TLBIndexT) . - return ((zero_extend1 (( 64 :: int):: ii) w__2 :: 64 Word.word))) - else - if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) - \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - read_reg TLBEntryLo0_ref \<bind> - (\<lambda> (w__3 :: TLBEntryLoReg) . - return ((get_TLBEntryLoReg w__3 :: 64 Word.word))) else - if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) - \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - read_reg TLBEntryLo1_ref \<bind> - (\<lambda> (w__4 :: TLBEntryLoReg) . - return ((get_TLBEntryLoReg w__4 :: 64 Word.word))) else - if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - read_reg TLBContext_ref \<bind> - (\<lambda> (w__5 :: ContextReg) . - return ((get_ContextReg w__5 :: 64 Word.word))) else - if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then - (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) else - if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) - \<and> - (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg TLBPageMask_ref :: ( 16 Word.word) M) \<bind> - (\<lambda> (w__7 :: 16 bits) . - return - ((zero_extend1 (( 64 :: int):: ii) - ((concat_vec w__7 - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) - :: 28 Word.word)) :: 64 Word.word))) else - if ((((((b__48 = - (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) - \<and> - (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg TLBWired_ref :: ( 6 Word.word) M) \<bind> - (\<lambda> (w__8 :: TLBIndexT) . - return - ((zero_extend1 (( 64 :: int):: ii) w__8 :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) - \<and> - (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \<bind> - (\<lambda> (w__9 :: 32 bits) . - return - ((zero_extend1 (( 64 :: int):: ii) w__9 :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg CP0BadVAddr_ref :: ( 64 Word.word) M) else - if ((((((b__48 = - (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then - return - ((zero_extend1 (( 64 :: int):: ii) - (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg CP0Count_ref :: ( 32 Word.word) M) - \<bind> - (\<lambda> (w__11 :: 32 bits) . - return - ((zero_extend1 (( 64 :: int):: ii) w__11 :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - read_reg TLBEntryHi_ref \<bind> - (\<lambda> (w__12 :: TLBEntryHiReg) . - return - ((get_TLBEntryHiReg w__12 :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg CP0Compare_ref :: ( 32 Word.word) M) - \<bind> - (\<lambda> (w__13 :: 32 bits) . - return - ((zero_extend1 (( 64 :: int):: ii) w__13 :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - read_reg CP0Status_ref \<bind> - (\<lambda> (w__14 :: StatusReg) . - return - ((zero_extend1 (( 64 :: int):: ii) - ((get_StatusReg w__14 :: 32 Word.word)) :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - read_reg CP0Cause_ref \<bind> - (\<lambda> (w__15 :: CauseReg) . - return - ((zero_extend1 (( 64 :: int):: ii) - ((get_CauseReg w__15 :: 32 Word.word)) :: 64 Word.word))) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg CP0EPC_ref :: ( 64 Word.word) M) - else - if ((((((b__48 = - (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then - return - ((zero_extend1 (( 64 :: int):: ii) - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 32 Word.word) :: 64 Word.word)) - else - if ((((((b__48 = - (vec_of_bits - [B0,B1,B1,B1,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) then - return - ((zero_extend1 (( 64 :: int):: ii) - (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) - else - if ((((((b__48 = - (vec_of_bits - [B0,B1,B1,B1,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) then - return - ((zero_extend1 - (( 64 :: int):: ii) - (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) - else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B0,B0,B0] :: 3 Word.word))))))) then - return - ((zero_extend1 - (( 64 :: int):: ii) - ((concat_vec - (vec_of_bits [B1] :: 1 Word.word) - ((concat_vec - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 15 Word.word) - ((concat_vec - (vec_of_bits - [B1] :: 1 Word.word) - ((concat_vec - (vec_of_bits - [B1,B0] :: 2 Word.word) - ((concat_vec - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B1] :: 3 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - :: 7 Word.word)) - :: 10 Word.word)) - :: 13 Word.word)) - :: 15 Word.word)) - :: 16 Word.word)) - :: 31 Word.word)) - :: 32 Word.word)) - :: 64 Word.word)) else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B0,B0,B1] :: 3 Word.word))))))) then - return - ((zero_extend1 - (( 64 :: int):: ii) - ((concat_vec - (vec_of_bits [B1] :: 1 Word.word) - ((concat_vec - TLBIndexMax - ((concat_vec - (vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ((concat_vec - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ( - ( - concat_vec - ( - ( - bool_to_bits - have_cp2 :: 1 Word.word)) - ( - ( - concat_vec - ( - vec_of_bits - [B0] :: 1 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] :: 1 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] :: 1 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] - :: 1 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0] - :: 1 Word.word) - ( - vec_of_bits - [B0] - :: 1 Word.word) - :: 2 Word.word)) - :: 3 Word.word)) - :: 4 Word.word)) - :: 5 Word.word)) - :: 6 Word.word)) - :: 7 Word.word)) - :: 10 Word.word)) - :: 13 Word.word)) - :: 16 Word.word)) - :: 19 Word.word)) - :: 22 Word.word)) - :: 25 Word.word)) - :: 31 Word.word)) - :: 32 Word.word)) - :: 64 Word.word)) else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B0,B1,B0] :: 3 Word.word))))))) then - return - ((zero_extend1 - (( 64 :: int):: ii) - ((concat_vec - (vec_of_bits [B1] :: 1 Word.word) - ((concat_vec - (vec_of_bits - [B0,B0,B0] :: 3 Word.word) - ((concat_vec - (vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ((concat_vec - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ( - ( - concat_vec - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - ( - vec_of_bits - [B0,B0,B0,B0] :: 4 Word.word) - :: 8 Word.word)) - :: 12 Word.word)) - :: 16 Word.word)) - :: 20 Word.word)) - :: 24 Word.word)) - :: 28 Word.word)) - :: 31 Word.word)) - :: 32 Word.word)) - :: 64 Word.word)) else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B0,B1,B1] :: 3 Word.word))))))) then - return - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word) else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B0,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B1,B0,B1] :: 3 Word.word))))))) then - return - (vec_of_bits - [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word) else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B0,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B0,B0,B0] :: 3 Word.word))))))) then - (read_reg CP0LLAddr_ref :: ( 64 Word.word) M) - else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B1,B0] :: 5 Word.word)))) - \<and> - (((b__49 = - (vec_of_bits - [B0,B0,B0] :: 3 Word.word))))))) then - return - ((zero_extend1 - (( 64 :: int):: ii) - (vec_of_bits - [B0] :: 1 Word.word) :: 64 Word.word)) - else - if ((((((b__48 = - (vec_of_bits - [B1,B0,B0,B1,B1] :: 5 Word.word)))) - \<and> - (((b__49 = - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word))))))) then - return - ((zero_extend1 - (( 64 :: int):: ii) - (vec_of_bits - [B0] :: 1 Word.word) :: 64 Word.word)) - else - if ((((((b__48 = - ( - vec_of_bits - [B1,B0,B1,B0,B0] :: 5 Word.word)))) - \<and> - ((( - b__49 = - ( - vec_of_bits - [B0,B0,B0] :: 3 Word.word))))))) then - read_reg - TLBXContext_ref - \<bind> - (\<lambda> (w__18 :: XContextReg) . - return - ((get_XContextReg - w__18 :: 64 Word.word))) - else - (read_reg - CP0ErrorEPC_ref :: ( 64 Word.word) M) - )) \<bind> (\<lambda> (result :: 64 bits) . + (checkCP0Access () \<then> + (case (rd, sel) of + (b__48, b__49) => + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBIndex_ref :: ( 6 Word.word) M) \<bind> (\<lambda> (w__0 :: TLBIndexT) . + (let (idx :: 31 bits) = ((mips_zero_extend (( 31 :: int)::ii) w__0 :: 31 Word.word)) in + (read_reg TLBProbe_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . + return ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) ((concat_vec w__1 idx :: 32 Word.word)) + :: 64 Word.word))))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBRandom_ref :: ( 6 Word.word) M) \<bind> (\<lambda> (w__2 :: TLBIndexT) . + return ((mips_zero_extend (( 64 :: int)::ii) w__2 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryLo0_ref \<bind> (\<lambda> (w__3 :: TLBEntryLoReg) . + return ((get_TLBEntryLoReg_bits w__3 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryLo1_ref \<bind> (\<lambda> (w__4 :: TLBEntryLoReg) . + return ((get_TLBEntryLoReg_bits w__4 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBContext_ref \<bind> (\<lambda> (w__5 :: ContextReg) . + return ((get_ContextReg_bits w__5 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) + else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBPageMask_ref :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 bits) . + return ((mips_zero_extend (( 64 :: int)::ii) + ((concat_vec w__7 + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + :: 28 Word.word)) + :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBWired_ref :: ( 6 Word.word) M) \<bind> (\<lambda> (w__8 :: TLBIndexT) . + return ((mips_zero_extend (( 64 :: int)::ii) w__8 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 bits) . + return ((mips_zero_extend (( 64 :: int)::ii) w__9 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0BadVAddr_ref :: ( 64 Word.word) M) + else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0Count_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: 32 bits) . + return ((mips_zero_extend (( 64 :: int)::ii) w__11 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryHi_ref \<bind> (\<lambda> (w__12 :: TLBEntryHiReg) . + return ((get_TLBEntryHiReg_bits w__12 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0Compare_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . + return ((mips_zero_extend (( 64 :: int)::ii) w__13 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg CP0Status_ref \<bind> (\<lambda> (w__14 :: StatusReg) . + return ((mips_zero_extend (( 64 :: int)::ii) ((get_StatusReg_bits w__14 :: 32 Word.word)) :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg CP0Cause_ref \<bind> (\<lambda> (w__15 :: CauseReg) . + return ((mips_zero_extend (( 64 :: int)::ii) ((get_CauseReg_bits w__15 :: 32 Word.word)) :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0EPC_ref :: ( 64 Word.word) M) + else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) + :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0ConfigK0_ref :: ( 3 Word.word) M) \<bind> (\<lambda> (w__17 :: 3 bits) . + return ((mips_zero_extend (( 64 :: int)::ii) + ((concat_vec (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 15 Word.word) + ((concat_vec (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec (vec_of_bits [B1,B0] :: 2 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + w__17 + :: 7 Word.word)) + :: 10 Word.word)) + :: 13 Word.word)) + :: 15 Word.word)) + :: 16 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) + ((concat_vec (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec TLBIndexMax + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec + ((bool_to_bits have_cp2 :: 1 Word.word)) + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((concat_vec + (vec_of_bits [B0] :: 1 Word.word) + ((concat_vec + (vec_of_bits [B0] :: 1 Word.word) + ((concat_vec + (vec_of_bits [B0] + :: 1 Word.word) + ((concat_vec + (vec_of_bits [B0] + :: 1 Word.word) + (vec_of_bits [B0] + :: 1 Word.word) + :: 2 Word.word)) + :: 3 Word.word)) + :: 4 Word.word)) + :: 5 Word.word)) + :: 6 Word.word)) + :: 7 Word.word)) + :: 10 Word.word)) + :: 13 Word.word)) + :: 16 Word.word)) + :: 19 Word.word)) + :: 22 Word.word)) + :: 25 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) + ((concat_vec (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + :: 8 Word.word)) + :: 12 Word.word)) + :: 16 Word.word)) + :: 20 Word.word)) + :: 24 Word.word)) + :: 28 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B1,B1] :: 3 Word.word))))))) then + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) then + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0LLAddr_ref :: ( 64 Word.word) M) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if ((((((b__48 = (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBXContext_ref \<bind> (\<lambda> (w__19 :: XContextReg) . + return ((get_XContextReg_bits w__19 :: 64 Word.word))) + else if ((((((b__48 = (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))) \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0ErrorEPC_ref :: ( 64 Word.word) M) + else (SignalException ResI :: ( 64 Word.word) M) + )) \<bind> (\<lambda> (result :: 64 bits) . wGPR rt (if double then result else - (sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))" + (mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))))" (*val execute_MADDU : mword ty5 -> mword ty5 -> M unit*) @@ -6666,7 +6394,7 @@ definition execute_MADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) @@ -6681,10 +6409,12 @@ definition execute_MADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro :: 64 Word.word)) in write_reg HI_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) \<then> write_reg LO_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)))))))))" (*val execute_MADD : mword ty5 -> mword ty5 -> M unit*) @@ -6695,7 +6425,7 @@ definition execute_MADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) else return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) @@ -6710,10 +6440,12 @@ definition execute_MADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow :: 64 Word.word)) in write_reg HI_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) \<then> write_reg LO_ref - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)))))))))" (*val execute_Load : WordType -> bool -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) @@ -6721,8 +6453,8 @@ definition execute_MADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow definition execute_Load :: " WordType \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_Load width sign linked base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData - width + (addrWrapper ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + LoadData width :: ( 64 Word.word) M) \<bind> (\<lambda> (vAddr :: 64 bits) . if ((\<not> ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr else @@ -6731,33 +6463,28 @@ definition execute_Load :: " WordType \<Rightarrow> bool \<Rightarrow> bool \<R (write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> write_reg CP0LLAddr_ref pAddr) \<then> (case width of - B => - (MEMr_reserve_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 Word.word) . + W => + (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . return ((extendLoad w__1 sign :: 64 Word.word))) - | H => - (MEMr_reserve_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__2 :: 16 Word.word) . - return ((extendLoad w__2 sign :: 64 Word.word))) - | W => - (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . - return ((extendLoad w__3 sign :: 64 Word.word))) | D => - (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . - return ((extendLoad w__4 sign :: 64 Word.word))) + (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + return ((extendLoad w__2 sign :: 64 Word.word))) + | _ => throw (Error_internal_error () ) ) else (case width of B => - (MEMr_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__6 :: 8 Word.word) . - return ((extendLoad w__6 sign :: 64 Word.word))) + (MEMr_wrapper (( 8 :: int)::ii) pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__5 :: 8 Word.word) . + return ((extendLoad w__5 sign :: 64 Word.word))) | H => - (MEMr_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 Word.word) . - return ((extendLoad w__7 sign :: 64 Word.word))) + (MEMr_wrapper (( 16 :: int)::ii) pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__6 :: 16 Word.word) . + return ((extendLoad w__6 sign :: 64 Word.word))) | W => - (MEMr_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 Word.word) . - return ((extendLoad w__8 sign :: 64 Word.word))) + (MEMr_wrapper (( 32 :: int)::ii) pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 Word.word) . + return ((extendLoad w__7 sign :: 64 Word.word))) | D => - (MEMr_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 Word.word) . - return ((extendLoad w__9 sign :: 64 Word.word))) + (MEMr_wrapper (( 64 :: int)::ii) pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 :: 64 Word.word) . + return ((extendLoad w__8 sign :: 64 Word.word))) )) \<bind> (\<lambda> (memResult :: 64 bits) . wGPR rt memResult)))))" @@ -6767,11 +6494,11 @@ definition execute_Load :: " WordType \<Rightarrow> bool \<Rightarrow> bool \<R definition execute_LWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_LWR base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData - W + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData WR :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . - (MEMr_wrapper + (MEMr_wrapper (( 32 :: int)::ii) ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) :: 64 Word.word)) (( 4 :: int)::ii) @@ -6792,7 +6519,7 @@ definition execute_LWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 8 :: int)::ii) :: 24 Word.word)) :: 32 Word.word) else mem_val) in - wGPR rt ((sign_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))" + wGPR rt ((mips_sign_extend (( 64 :: int)::ii) result :: 64 Word.word))))))))))" (*val execute_LWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) @@ -6800,11 +6527,11 @@ definition execute_LWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> definition execute_LWL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_LWL base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData - W + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData WL :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . - (MEMr_wrapper + (MEMr_wrapper (( 32 :: int)::ii) ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) :: 64 Word.word)) (( 4 :: int)::ii) @@ -6825,7 +6552,7 @@ definition execute_LWL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (concat_vec ((subrange_vec_dec mem_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) :: 32 Word.word)) in - wGPR rt ((sign_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))" + wGPR rt ((mips_sign_extend (( 64 :: int)::ii) result :: 64 Word.word))))))))))" (*val execute_LUI : mword ty5 -> mword ty16 -> M unit*) @@ -6833,7 +6560,7 @@ definition execute_LWL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> definition execute_LUI :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_LUI rt imm = ( wGPR rt - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word) :: 32 Word.word)) @@ -6845,11 +6572,11 @@ definition execute_LUI :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow definition execute_LDR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_LDR base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData - D + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData DR :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . - (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . - (MEMr_wrapper + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (MEMr_wrapper (( 64 :: int)::ii) ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 64 Word.word)) (( 8 :: int)::ii) @@ -6893,11 +6620,11 @@ definition execute_LDR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> definition execute_LDL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_LDL base rt offset = ( (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData - D + (addrWrapperUnaligned + ((add_vec ((mips_sign_extend (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData DL :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . - (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . - (MEMr_wrapper + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (MEMr_wrapper (( 64 :: int)::ii) ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 64 Word.word)) (( 8 :: int)::ii) @@ -6978,22 +6705,16 @@ definition execute_J :: "(26)Word.word \<Rightarrow>((register_value),(unit),(e :: 64 Word.word))))" -(*val execute_ImplementationDefinedStopFetching : unit -> unit*) - -definition execute_ImplementationDefinedStopFetching :: " unit \<Rightarrow> unit " where - " execute_ImplementationDefinedStopFetching g__118 = ( () )" - - (*val execute_HCF : unit -> unit*) definition execute_HCF :: " unit \<Rightarrow> unit " where - " execute_HCF g__123 = ( () )" + " execute_HCF g__21 = ( () )" (*val execute_ERET : unit -> M unit*) definition execute_ERET :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_ERET g__128 = ( + " execute_ERET g__26 = ( (((checkCP0Access () \<then> ERETHook () ) \<then> write_reg CP0LLBit_ref (vec_of_bits [B0] :: 1 Word.word)) \<then> @@ -7022,7 +6743,8 @@ definition execute_DSUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let (temp65 :: 65 bits) = - ((sub_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) w__1 :: 65 Word.word)) + ((sub_vec ((mips_sign_extend (( 65 :: int)::ii) w__0 :: 65 Word.word)) + ((mips_sign_extend (( 65 :: int)::ii) w__1 :: 65 Word.word)) :: 65 Word.word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 :: int)::ii))))) ((bit_to_bool ((access_vec_dec temp65 (( 63 :: int)::ii))))))) then @@ -7037,7 +6759,7 @@ definition execute_DSRLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let sa = ((subrange_vec_dec w__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) in - (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" + (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" (*val execute_DSRL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7046,7 +6768,7 @@ definition execute_DSRL32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr " execute_DSRL32 rt rd sa = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . (let sa32 = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) in - (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))))" + (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))))" (*val execute_DSRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7054,7 +6776,7 @@ definition execute_DSRL32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr definition execute_DSRL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_DSRL rt rd sa = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . - (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0)))" + (shift_bits_right instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0)))" (*val execute_DSRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7065,7 +6787,7 @@ definition execute_DSRAV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let sa = ((subrange_vec_dec w__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) in (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" (*val execute_DSRA32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7075,7 +6797,7 @@ definition execute_DSRA32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . (let sa32 = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) in (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))))" (*val execute_DSRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7084,7 +6806,7 @@ definition execute_DSRA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow " execute_DSRA rt rd sa = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . (shift_bits_right_arith - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0)))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0)))" (*val execute_DSLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7093,7 +6815,7 @@ definition execute_DSLLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro " execute_DSLLV rs rt rd = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . wGPR rd w__2))))" @@ -7103,7 +6825,7 @@ definition execute_DSLLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro definition execute_DSLL32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_DSLL32 rt rd sa = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))" @@ -7113,7 +6835,7 @@ definition execute_DSLL32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr definition execute_DSLL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_DSLL rt rd sa = ( (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))" + (shift_bits_left instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict w__0 sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))" (*val execute_DMULTU : mword ty5 -> mword ty5 -> M unit*) @@ -7149,9 +6871,9 @@ definition execute_DIVU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)))))))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . return (w__0, w__1))) else (let si = (Word.uint ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in @@ -7160,8 +6882,8 @@ definition execute_DIVU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (let ri = (hardware_mod si ti) in return ((to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) qi :: 32 Word.word), (to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) ri :: 32 Word.word))))))) \<bind> (\<lambda> varstup . (let (q, r) = varstup in - write_reg HI_ref ((sign_extend1 (( 64 :: int)::ii) r :: 64 Word.word)) \<then> - write_reg LO_ref ((sign_extend1 (( 64 :: int)::ii) q :: 64 Word.word)))))))" + write_reg HI_ref ((mips_sign_extend (( 64 :: int)::ii) r :: 64 Word.word)) \<then> + write_reg LO_ref ((mips_sign_extend (( 64 :: int)::ii) q :: 64 Word.word)))))))" (*val execute_DIV : mword ty5 -> mword ty5 -> M unit*) @@ -7175,9 +6897,9 @@ definition execute_DIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)))))))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . return (w__0, w__1))) else (let si = (Word.sint ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in @@ -7186,8 +6908,8 @@ definition execute_DIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (let ri = (si - ((ti * qi))) in return ((to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) qi :: 32 Word.word), (to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) ri :: 32 Word.word))))))) \<bind> (\<lambda> varstup . (let (q, r) = varstup in - write_reg HI_ref ((sign_extend1 (( 64 :: int)::ii) r :: 64 Word.word)) \<then> - write_reg LO_ref ((sign_extend1 (( 64 :: int)::ii) q :: 64 Word.word)))))))" + write_reg HI_ref ((mips_sign_extend (( 64 :: int)::ii) r :: 64 Word.word)) \<then> + write_reg LO_ref ((mips_sign_extend (( 64 :: int)::ii) q :: 64 Word.word)))))))" (*val execute_DDIVU : mword ty5 -> mword ty5 -> M unit*) @@ -7200,9 +6922,9 @@ definition execute_DDIVU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (let rtVal = (Word.uint w__1) in (if (((rtVal = (( 0 :: int)::ii)))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . return (w__2, w__3))) else (let qi = (hardware_quot rsVal rtVal) in @@ -7222,9 +6944,9 @@ definition execute_DDIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (let rtVal = (Word.sint w__1) in (if (((rtVal = (( 0 :: int)::ii)))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . return (w__2, w__3))) else (let qi = (hardware_quot rsVal rtVal) in @@ -7248,7 +6970,7 @@ definition execute_DADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro definition execute_DADDIU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_DADDIU rs rt imm = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - wGPR rt ((add_vec w__0 ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + wGPR rt ((add_vec w__0 ((mips_sign_extend (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" (*val execute_DADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) @@ -7257,7 +6979,8 @@ definition execute_DADDI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro " execute_DADDI rs rt imm = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let (sum65 :: 65 bits) = - ((add_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) imm :: 65 Word.word)) + ((add_vec ((mips_sign_extend (( 65 :: int)::ii) w__0 :: 65 Word.word)) + ((mips_sign_extend (( 65 :: int)::ii) imm :: 65 Word.word)) :: 65 Word.word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 :: int)::ii))))) ((bit_to_bool ((access_vec_dec sum65 (( 63 :: int)::ii))))))) then @@ -7272,7 +6995,8 @@ definition execute_DADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let (sum65 :: 65 bits) = - ((add_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) w__1 :: 65 Word.word)) + ((add_vec ((mips_sign_extend (( 65 :: int)::ii) w__0 :: 65 Word.word)) + ((mips_sign_extend (( 65 :: int)::ii) w__1 :: 65 Word.word)) :: 65 Word.word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 :: int)::ii))))) ((bit_to_bool ((access_vec_dec sum65 (( 63 :: int)::ii))))))) then @@ -7308,7 +7032,10 @@ definition execute_ClearRegs :: " ClearRegSet \<Rightarrow>(16)Word.word \<Righ ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) :: 5 Word.word)) ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)) | CLo => - writeCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) null_cap + if (((i = (( 0 :: int)::ii)))) then write_reg DDC_ref ((capStructToCapReg null_cap :: 257 Word.word)) + else + writeCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) + null_cap | CHi => writeCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) @@ -7322,15 +7049,15 @@ definition execute_ClearRegs :: " ClearRegSet \<Rightarrow>(16)Word.word \<Righ definition execute_CWriteHwr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CWriteHwr cb sel = ( checkCP2usable () \<then> - ((let l__24 = (Word.uint sel) in - (if (((l__24 = (( 0 :: int)::ii)))) then return (False, False) - else if (((l__24 = (( 1 :: int)::ii)))) then return (False, False) - else if (((l__24 = (( 8 :: int)::ii)))) then return (False, True) - else if (((l__24 = (( 22 :: int)::ii)))) then return (True, False) - else if (((l__24 = (( 23 :: int)::ii)))) then return (True, False) - else if (((l__24 = (( 29 :: int)::ii)))) then return (True, True) - else if (((l__24 = (( 30 :: int)::ii)))) then return (True, True) - else if (((l__24 = (( 31 :: int)::ii)))) then return (True, True) + ((let p00 = (Word.uint sel) in + (if (((p00 = (( 0 :: int)::ii)))) then return (False, False) + else if (((p00 = (( 1 :: int)::ii)))) then return (False, False) + else if (((p00 = (( 8 :: int)::ii)))) then return (False, True) + else if (((p00 = (( 22 :: int)::ii)))) then return (True, False) + else if (((p00 = (( 23 :: int)::ii)))) then return (True, False) + else if (((p00 = (( 29 :: int)::ii)))) then return (True, True) + else if (((p00 = (( 30 :: int)::ii)))) then return (True, True) + else if (((p00 = (( 31 :: int)::ii)))) then return (True, True) else SignalException ResI) \<bind> (\<lambda> varstup . (let ((needSup :: bool), (needAccessSys :: bool)) = varstup in register_inaccessible cb \<bind> (\<lambda> (w__8 :: bool) . if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cb @@ -7346,17 +7073,22 @@ definition execute_CWriteHwr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Right if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel else readCapReg cb \<bind> (\<lambda> capVal . - (let l__16 = (Word.uint sel) in - if (((l__16 = (( 0 :: int)::ii)))) then writeCapReg DDC capVal - else if (((l__16 = (( 1 :: int)::ii)))) then + (let p00 = (Word.uint sel) in + if (((p00 = (( 0 :: int)::ii)))) then write_reg DDC_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((p00 = (( 1 :: int)::ii)))) then write_reg CTLSU_ref ((capStructToCapReg capVal :: 257 Word.word)) - else if (((l__16 = (( 8 :: int)::ii)))) then + else if (((p00 = (( 8 :: int)::ii)))) then write_reg CTLSP_ref ((capStructToCapReg capVal :: 257 Word.word)) - else if (((l__16 = (( 22 :: int)::ii)))) then writeCapReg KR1C capVal - else if (((l__16 = (( 23 :: int)::ii)))) then writeCapReg KR2C capVal - else if (((l__16 = (( 29 :: int)::ii)))) then writeCapReg KCC capVal - else if (((l__16 = (( 30 :: int)::ii)))) then writeCapReg KDC capVal - else if (((l__16 = (( 31 :: int)::ii)))) then writeCapReg EPCC capVal + else if (((p00 = (( 22 :: int)::ii)))) then + write_reg KR1C_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((p00 = (( 23 :: int)::ii)))) then + write_reg KR2C_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((p00 = (( 29 :: int)::ii)))) then + write_reg KCC_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((p00 = (( 30 :: int)::ii)))) then + write_reg KDC_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((p00 = (( 31 :: int)::ii)))) then + write_reg EPCC_ref ((capStructToCapReg capVal :: 257 Word.word)) else assert_exp False (''should be unreachable code'')))))))))))" @@ -7400,7 +7132,7 @@ definition execute_CUnseal :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightar definition execute_CToPtr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CToPtr rd cb ct = ( (checkCP2usable () \<then> - readCapReg ct) \<bind> (\<lambda> ct_val . + readCapRegDDC ct) \<bind> (\<lambda> ct_val . readCapReg cb \<bind> (\<lambda> cb_val . register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb @@ -7429,7 +7161,7 @@ definition execute_CToPtr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr definition execute_CTestSubset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CTestSubset rd cb ct = ( (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . readCapReg ct \<bind> (\<lambda> ct_val . (let ct_top = (getCapTop ct_val) in (let ct_base = (getCapBase ct_val) in @@ -7451,7 +7183,7 @@ definition execute_CTestSubset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rig else if (((((and_vec ct_perms cb_perms :: 31 Word.word)) \<noteq> ct_perms))) then (vec_of_bits [B0] :: 1 Word.word) else (vec_of_bits [B1] :: 1 Word.word)) in - wGPR rd ((zero_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))))))" + wGPR rd ((mips_zero_extend (( 64 :: int)::ii) result :: 64 Word.word))))))))))))))" (*val execute_CSub : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -7478,7 +7210,7 @@ definition execute_CSub :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow definition execute_CStore :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> WordType \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CStore rs cb rt rd offset width conditional = ( (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb @@ -7490,8 +7222,8 @@ definition execute_CStore :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__1)))) + ((size1 * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__1)))) + ((size1 * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + size1)) > ((getCapTop cb_val)))) then @@ -7517,7 +7249,7 @@ definition execute_CStore :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr | D => MEMw_conditional_wrapper pAddr (( 8 :: int)::ii) rs_val ) else return False) \<bind> (\<lambda> (success :: bool) . - wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) else (case width of B => MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec rs_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) @@ -7694,7 +7426,7 @@ definition execute_CSC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> " execute_CSC cs cb rt rd offset conditional = ( (checkCP2usable () \<then> readCapReg cs) \<bind> (\<lambda> cs_val . - readCapReg cb \<bind> (\<lambda> cb_val . + readCapRegDDC cb \<bind> (\<lambda> cb_val . register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs else @@ -7712,15 +7444,14 @@ definition execute_CSC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then raise_c2_exception CapEx_LengthViolation cb else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb - else if (((((hardware_mod vAddr cap_size)) \<noteq> (( 0 :: int)::ii)))) then - SignalExceptionBadAddr AdES vAddr64 + else if (((((vAddr mod cap_size)) \<noteq> (( 0 :: int)::ii)))) then SignalExceptionBadAddr AdES vAddr64 else (TLBTranslateC vAddr64 StoreData :: (( 64 Word.word * bool)) M) \<bind> (\<lambda> varstup . (let (pAddr, noStoreCap) = varstup in if ((((CapStruct_tag cs_val) \<and> noStoreCap))) then @@ -7731,14 +7462,14 @@ definition execute_CSC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> MEMw_tagged_conditional pAddr(CapStruct_tag cs_val) ((capStructToMemBits cs_val :: 256 Word.word)) else return False) \<bind> (\<lambda> success . - wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) else MEMw_tagged pAddr(CapStruct_tag cs_val) ((capStructToMemBits cs_val :: 256 Word.word)))))))))))))" (*val execute_CReturn : unit -> M unit*) definition execute_CReturn :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_CReturn g__129 = ( checkCP2usable () \<then> raise_c2_exception_noreg CapEx_ReturnTrap )" + " execute_CReturn g__27 = ( checkCP2usable () \<then> raise_c2_exception_noreg CapEx_ReturnTrap )" (*val execute_CReadHwr : mword ty5 -> mword ty5 -> M unit*) @@ -7746,15 +7477,15 @@ definition execute_CReturn :: " unit \<Rightarrow>((register_value),(unit),(exc definition execute_CReadHwr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CReadHwr cd1 sel = ( checkCP2usable () \<then> - ((let l__8 = (Word.uint sel) in - (if (((l__8 = (( 0 :: int)::ii)))) then return (False, False) - else if (((l__8 = (( 1 :: int)::ii)))) then return (False, False) - else if (((l__8 = (( 8 :: int)::ii)))) then return (False, True) - else if (((l__8 = (( 22 :: int)::ii)))) then return (True, False) - else if (((l__8 = (( 23 :: int)::ii)))) then return (True, False) - else if (((l__8 = (( 29 :: int)::ii)))) then return (True, True) - else if (((l__8 = (( 30 :: int)::ii)))) then return (True, True) - else if (((l__8 = (( 31 :: int)::ii)))) then return (True, True) + ((let p00 = (Word.uint sel) in + (if (((p00 = (( 0 :: int)::ii)))) then return (False, False) + else if (((p00 = (( 1 :: int)::ii)))) then return (False, False) + else if (((p00 = (( 8 :: int)::ii)))) then return (False, True) + else if (((p00 = (( 22 :: int)::ii)))) then return (True, False) + else if (((p00 = (( 23 :: int)::ii)))) then return (True, False) + else if (((p00 = (( 29 :: int)::ii)))) then return (True, True) + else if (((p00 = (( 30 :: int)::ii)))) then return (True, True) + else if (((p00 = (( 31 :: int)::ii)))) then return (True, True) else SignalException ResI) \<bind> (\<lambda> varstup . (let ((needSup :: bool), (needAccessSys :: bool)) = varstup in register_inaccessible cd1 \<bind> (\<lambda> (w__8 :: bool) . if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 @@ -7769,19 +7500,31 @@ definition execute_CReadHwr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righta return ((\<not> ((grantsAccess w__11 Supervisor)))))) \<bind> (\<lambda> (w__12 :: bool) . if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel else - (let l__0 = (Word.uint sel) in - (if (((l__0 = (( 0 :: int)::ii)))) then readCapReg DDC - else if (((l__0 = (( 1 :: int)::ii)))) then + (let p00 = (Word.uint sel) in + (if (((p00 = (( 0 :: int)::ii)))) then + (read_reg DDC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__13 :: 257 Word.word) . + return ((capRegToCapStruct w__13))) + else if (((p00 = (( 1 :: int)::ii)))) then (read_reg CTLSU_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__14 :: 257 Word.word) . return ((capRegToCapStruct w__14))) - else if (((l__0 = (( 8 :: int)::ii)))) then + else if (((p00 = (( 8 :: int)::ii)))) then (read_reg CTLSP_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__15 :: 257 Word.word) . return ((capRegToCapStruct w__15))) - else if (((l__0 = (( 22 :: int)::ii)))) then readCapReg KR1C - else if (((l__0 = (( 23 :: int)::ii)))) then readCapReg KR2C - else if (((l__0 = (( 29 :: int)::ii)))) then readCapReg KCC - else if (((l__0 = (( 30 :: int)::ii)))) then readCapReg KDC - else if (((l__0 = (( 31 :: int)::ii)))) then readCapReg EPCC + else if (((p00 = (( 22 :: int)::ii)))) then + (read_reg KR1C_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__16 :: 257 Word.word) . + return ((capRegToCapStruct w__16))) + else if (((p00 = (( 23 :: int)::ii)))) then + (read_reg KR2C_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__17 :: 257 Word.word) . + return ((capRegToCapStruct w__17))) + else if (((p00 = (( 29 :: int)::ii)))) then + (read_reg KCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__18 :: 257 Word.word) . + return ((capRegToCapStruct w__18))) + else if (((p00 = (( 30 :: int)::ii)))) then + (read_reg KDC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__19 :: 257 Word.word) . + return ((capRegToCapStruct w__19))) + else if (((p00 = (( 31 :: int)::ii)))) then + (read_reg EPCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__20 :: 257 Word.word) . + return ((capRegToCapStruct w__20))) else assert_exp False (''should be unreachable code'') \<then> undefined_CapStruct () ) \<bind> (\<lambda> (capVal :: CapStruct) . writeCapReg cd1 capVal))))))))))" @@ -7832,7 +7575,7 @@ definition execute_CPtrCmp :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightar | CEXEQ => (cb_val = ct_val) | CNEXEQ => (cb_val \<noteq> ct_val) )) in - wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits cmp :: 1 Word.word)) :: 64 Word.word))))))))))))" + wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits cmp :: 1 Word.word)) :: 64 Word.word))))))))))))" (*val execute_CMOVX : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) @@ -7864,7 +7607,7 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (case merge_var of (rd, cb, rt, offset, signext, B, linked) => (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb @@ -7875,8 +7618,8 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__1)))) + (((( 1 :: int)::ii) * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__1)))) + (((( 1 :: int)::ii) * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + (( 1 :: int)::ii))) > ((getCapTop cb_val)))) then @@ -7891,12 +7634,12 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (MEMr_reserve_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__2 :: 8 Word.word) . return ((extendLoad w__2 signext :: 64 Word.word))) else - (MEMr_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 Word.word) . + (MEMr_wrapper (( 8 :: int)::ii) pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 Word.word) . return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . wGPR rd memResult)))))))) | (rd, cb, rt, offset, signext, D, linked) => (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb @@ -7907,8 +7650,8 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__1)))) + (((( 8 :: int)::ii) * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__1)))) + (((( 8 :: int)::ii) * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + (( 8 :: int)::ii))) > ((getCapTop cb_val)))) then @@ -7923,12 +7666,12 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__2 :: 64 Word.word) . return ((extendLoad w__2 signext :: 64 Word.word))) else - (MEMr_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . + (MEMr_wrapper (( 64 :: int)::ii) pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . wGPR rd memResult)))))))) | (rd, cb, rt, offset, signext, H, linked) => (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb @@ -7939,8 +7682,8 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__1)))) + (((( 2 :: int)::ii) * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__1)))) + (((( 2 :: int)::ii) * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + (( 2 :: int)::ii))) > ((getCapTop cb_val)))) then @@ -7955,12 +7698,12 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (MEMr_reserve_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__2 :: 16 Word.word) . return ((extendLoad w__2 signext :: 64 Word.word))) else - (MEMr_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 Word.word) . + (MEMr_wrapper (( 16 :: int)::ii) pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 Word.word) . return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . wGPR rd memResult)))))))) | (rd, cb, rt, offset, signext, W, linked) => (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb @@ -7971,8 +7714,8 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__1)))) + (((( 4 :: int)::ii) * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__1)))) + (((( 4 :: int)::ii) * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + (( 4 :: int)::ii))) > ((getCapTop cb_val)))) then @@ -7987,18 +7730,18 @@ definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 :: 32 Word.word) . return ((extendLoad w__2 signext :: 64 Word.word))) else - (MEMr_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . + (MEMr_wrapper (( 32 :: int)::ii) pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . wGPR rd memResult)))))))) )))" -(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*) +(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty16 -> bool -> M unit*) -definition execute_CLC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where +definition execute_CLC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CLC cd1 cb rt offset linked = ( (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 else @@ -8012,15 +7755,14 @@ definition execute_CLC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (let cursor = (getCapCursor cb_val) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . (let vAddr = - (hardware_mod - ((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + (((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + mod ((pow2 (( 64 :: int)::ii)))) in (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then raise_c2_exception CapEx_LengthViolation cb else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb - else if (((((hardware_mod vAddr cap_size)) \<noteq> (( 0 :: int)::ii)))) then - SignalExceptionBadAddr AdEL vAddr64 + else if (((((vAddr mod cap_size)) \<noteq> (( 0 :: int)::ii)))) then SignalExceptionBadAddr AdEL vAddr64 else (TLBTranslateC vAddr64 LoadData :: (( 64 Word.word * bool)) M) \<bind> (\<lambda> varstup . (let (pAddr, suppressTag) = varstup in (let cd1 = (Word.uint cd1) in @@ -8065,7 +7807,7 @@ definition execute_CJALR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro else if ((cb_ptr < cb_base)) then raise_c2_exception CapEx_LengthViolation cb else if ((((cb_ptr + (( 4 :: int)::ii))) > cb_top)) then raise_c2_exception CapEx_LengthViolation cb - else if (((((hardware_mod cb_ptr (( 4 :: int)::ii))) \<noteq> (( 0 :: int)::ii)))) then SignalException AdEL + else if (((((cb_ptr mod (( 4 :: int)::ii))) \<noteq> (( 0 :: int)::ii)))) then SignalException AdEL else (if link then (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__3 :: 257 Word.word) . @@ -8084,7 +7826,7 @@ definition execute_CIncOffsetImmediate :: "(5)Word.word \<Rightarrow>(5)Word.wo " execute_CIncOffsetImmediate cd1 cb imm = ( (checkCP2usable () \<then> readCapReg cb) \<bind> (\<lambda> cb_val . - (let (imm64 :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let (imm64 :: 64 bits) = ((mips_sign_extend (( 64 :: int)::ii) imm :: 64 Word.word)) in register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 else @@ -8144,7 +7886,8 @@ definition execute_CGetType :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righta else readCapReg cb \<bind> (\<lambda> capVal . wGPR rd - (if(CapStruct_sealed capVal) then (zero_extend1 (( 64 :: int)::ii)(CapStruct_otype capVal) :: 64 Word.word) + (if(CapStruct_sealed capVal) then + (mips_zero_extend (( 64 :: int)::ii)(CapStruct_otype capVal) :: 64 Word.word) else (replicate_bits ((cast_unit_vec0 B1 :: 1 Word.word)) (( 64 :: int)::ii) :: 64 Word.word)))))" @@ -8158,7 +7901,7 @@ definition execute_CGetTag :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightar else readCapReg cb \<bind> (\<lambda> capVal . wGPR rd - ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits(CapStruct_tag capVal) :: 1 Word.word)) :: 64 Word.word)))))" + ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits(CapStruct_tag capVal) :: 1 Word.word)) :: 64 Word.word)))))" (*val execute_CGetSealed : mword ty5 -> mword ty5 -> M unit*) @@ -8171,7 +7914,8 @@ definition execute_CGetSealed :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righ else readCapReg cb \<bind> (\<lambda> capVal . wGPR rd - ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits(CapStruct_sealed capVal) :: 1 Word.word)) :: 64 Word.word)))))" + ((mips_zero_extend (( 64 :: int)::ii) ((bool_to_bits(CapStruct_sealed capVal) :: 1 Word.word)) + :: 64 Word.word)))))" (*val execute_CGetPerm : mword ty5 -> mword ty5 -> M unit*) @@ -8183,7 +7927,7 @@ definition execute_CGetPerm :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righta if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb else readCapReg cb \<bind> (\<lambda> capVal . - wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((getCapPerms capVal :: 31 Word.word)) :: 64 Word.word)))))" + wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((getCapPerms capVal :: 31 Word.word)) :: 64 Word.word)))))" (*val execute_CGetPCCSetOffset : mword ty5 -> mword ty5 -> M unit*) @@ -8256,7 +8000,7 @@ definition execute_CGetCause :: "(5)Word.word \<Rightarrow>((register_value),(u if ((\<not> w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation else read_reg CapCause_ref \<bind> (\<lambda> (w__1 :: CapCauseReg) . - wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((get_CapCauseReg w__1 :: 16 Word.word)) :: 64 Word.word)))))" + wGPR rd ((mips_zero_extend (( 64 :: int)::ii) ((get_CapCauseReg_bits w__1 :: 16 Word.word)) :: 64 Word.word)))))" (*val execute_CGetBase : mword ty5 -> mword ty5 -> M unit*) @@ -8290,14 +8034,18 @@ definition execute_CGetAddr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righta definition execute_CFromPtr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CFromPtr cd1 cb rt = ( (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 else register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb - else if (((rt = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then writeCapReg cd1 null_cap + else if (((rt_val = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + writeCapReg cd1 null_cap else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb else @@ -8387,7 +8135,7 @@ definition execute_CCheckPerm :: "(5)Word.word \<Rightarrow>(5)Word.word \<Righ (checkCP2usable () \<then> readCapReg cs) \<bind> (\<lambda> cs_val . (let (cs_perms :: 64 bits) = - ((zero_extend1 (( 64 :: int)::ii) ((getCapPerms cs_val :: 31 Word.word)) :: 64 Word.word)) in + ((mips_zero_extend (( 64 :: int)::ii) ((getCapPerms cs_val :: 31 Word.word)) :: 64 Word.word)) in (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_perms . register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs @@ -8509,7 +8257,7 @@ definition execute_CCSeal :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarr definition execute_CBuildCap :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_CBuildCap cd1 cb ct = ( (checkCP2usable () \<then> - readCapReg cb) \<bind> (\<lambda> cb_val . + readCapRegDDC cb) \<bind> (\<lambda> cb_val . readCapReg ct \<bind> (\<lambda> ct_val . (let cb_base = (getCapBase cb_val) in (let ct_base = (getCapBase ct_val) in @@ -8560,7 +8308,7 @@ definition execute_CBZ :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow :: 1 Word.word)))) then (let (offset :: 64 bits) = ((add_vec_int - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) :: 64 Word.word)) (( 4 :: int)::ii) :: 64 Word.word)) in @@ -8584,7 +8332,7 @@ definition execute_CBX :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow :: 1 Word.word)))) then (let (offset :: 64 bits) = ((add_vec_int - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) :: 64 Word.word)) (( 4 :: int)::ii) :: 64 Word.word)) in @@ -8630,7 +8378,7 @@ definition execute_C2Dump :: "(5)Word.word \<Rightarrow> unit " where (*val execute_BREAK : unit -> M unit*) definition execute_BREAK :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_BREAK g__120 = ( SignalException Bp )" + " execute_BREAK g__18 = ( SignalException Bp )" (*val execute_BEQ : mword ty5 -> mword ty5 -> mword ty16 -> bool -> bool -> M unit*) @@ -8645,7 +8393,8 @@ definition execute_BEQ :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> :: 1 Word.word)))) then (let (offset :: 64 bits) = ((add_vec_int - ((sign_extend1 (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + ((mips_sign_extend (( 64 :: int)::ii) + ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) :: 64 Word.word)) (( 4 :: int)::ii) :: 64 Word.word)) in (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . @@ -8664,11 +8413,12 @@ definition execute_BCMPZ :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarr (let linkVal = ((add_vec_int w__0 (( 8 :: int)::ii) :: 64 Word.word)) in (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> regVal . (let condition = - (compare cmp regVal ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in + (compare cmp regVal ((mips_zero_extend (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in (if condition then (let (offset :: 64 bits) = ((add_vec_int - ((sign_extend1 (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + ((mips_sign_extend (( 64 :: int)::ii) + ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) :: 64 Word.word)) (( 4 :: int)::ii) :: 64 Word.word)) in (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . @@ -8686,7 +8436,7 @@ definition execute_BCMPZ :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarr definition execute_ANDI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " execute_ANDI rs rt imm = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - wGPR rt ((and_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + wGPR rt ((and_vec w__0 ((mips_zero_extend (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" (*val execute_AND : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -8706,10 +8456,10 @@ definition execute_ADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> opB . if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) else wGPR rd - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((add_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 32 Word.word)) @@ -8723,12 +8473,12 @@ definition execute_ADDIU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarro (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . if ((NotWordVal opA)) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rt w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rt w__0) else wGPR rt - ((sign_extend1 (( 64 :: int)::ii) + ((mips_sign_extend (( 64 :: int)::ii) ((add_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) - ((sign_extend1 (( 32 :: int)::ii) imm :: 32 Word.word)) + ((mips_sign_extend (( 32 :: int)::ii) imm :: 32 Word.word)) :: 32 Word.word)) :: 64 Word.word))))" @@ -8740,19 +8490,20 @@ definition execute_ADDI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . if ((NotWordVal opA)) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rt w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rt w__0) else (let (sum33 :: 33 bits) = ((add_vec - ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) - ((sign_extend1 (( 33 :: int)::ii) imm :: 33 Word.word)) + ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 33 Word.word)) ((mips_sign_extend (( 33 :: int)::ii) imm :: 33 Word.word)) :: 33 Word.word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 :: int)::ii))))) ((bit_to_bool ((access_vec_dec sum33 (( 31 :: int)::ii))))))) then SignalException Ov else wGPR rt - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)))))" (*val execute_ADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) @@ -8763,19 +8514,22 @@ definition execute_ADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (opB :: 64 bits) . if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) else (let (sum33 :: 33 bits) = ((add_vec - ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) - ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 33 Word.word)) + ((mips_sign_extend (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 33 Word.word)) :: 33 Word.word)) in if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 :: int)::ii))))) ((bit_to_bool ((access_vec_dec sum33 (( 31 :: int)::ii))))))) then SignalException Ov else wGPR rd - ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + ((mips_sign_extend (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))))))" fun execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " where @@ -8843,12 +8597,9 @@ fun execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " |" execute (JALR (rs,rd)) = ( execute_JALR rs rd )" |" execute (BEQ (rs,rd,imm,ne,likely)) = ( execute_BEQ rs rd imm ne likely )" |" execute (BCMPZ (rs,imm,cmp,link,likely)) = ( execute_BCMPZ rs imm cmp link likely )" -|" execute (SYSCALL_THREAD_START (g__117)) = ( return ((execute_SYSCALL_THREAD_START g__117)))" -|" execute (ImplementationDefinedStopFetching (g__118)) = ( - return ((execute_ImplementationDefinedStopFetching g__118)))" -|" execute (SYSCALL (g__119)) = ( execute_SYSCALL g__119 )" -|" execute (BREAK (g__120)) = ( execute_BREAK g__120 )" -|" execute (WAIT (g__121)) = ( execute_WAIT g__121 )" +|" execute (SYSCALL (g__17)) = ( execute_SYSCALL g__17 )" +|" execute (BREAK (g__18)) = ( execute_BREAK g__18 )" +|" execute (WAIT (g__19)) = ( execute_WAIT g__19 )" |" execute (TRAPREG (rs,rt,cmp)) = ( execute_TRAPREG rs rt cmp )" |" execute (TRAPIMM (rs,imm,cmp)) = ( execute_TRAPIMM rs imm cmp )" |" execute (Load (width,sign,linked,base,rt,offset)) = ( execute_Load width sign linked base rt offset )" @@ -8862,17 +8613,16 @@ fun execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " |" execute (SDL (base,rt,offset)) = ( execute_SDL base rt offset )" |" execute (SDR (base,rt,offset)) = ( execute_SDR base rt offset )" |" execute (CACHE (base,op1,imm)) = ( execute_CACHE base op1 imm )" -|" execute (PREF (base,op1,imm)) = ( return ((execute_PREF base op1 imm)))" -|" execute (SYNC (g__122)) = ( execute_SYNC g__122 )" +|" execute (SYNC (g__20)) = ( execute_SYNC g__20 )" |" execute (MFC0 (rt,rd,sel,double)) = ( execute_MFC0 rt rd sel double )" -|" execute (HCF (g__123)) = ( return ((execute_HCF g__123)))" +|" execute (HCF (g__21)) = ( return ((execute_HCF g__21)))" |" execute (MTC0 (rt,rd,sel,double)) = ( execute_MTC0 rt rd sel double )" -|" execute (TLBWI (g__124)) = ( execute_TLBWI g__124 )" -|" execute (TLBWR (g__125)) = ( execute_TLBWR g__125 )" -|" execute (TLBR (g__126)) = ( execute_TLBR g__126 )" -|" execute (TLBP (g__127)) = ( execute_TLBP g__127 )" +|" execute (TLBWI (g__22)) = ( execute_TLBWI g__22 )" +|" execute (TLBWR (g__23)) = ( execute_TLBWR g__23 )" +|" execute (TLBR (g__24)) = ( execute_TLBR g__24 )" +|" execute (TLBP (g__25)) = ( execute_TLBP g__25 )" |" execute (RDHWR (rt,rd)) = ( execute_RDHWR rt rd )" -|" execute (ERET (g__128)) = ( execute_ERET g__128 )" +|" execute (ERET (g__26)) = ( execute_ERET g__26 )" |" execute (CGetPerm (rd,cb)) = ( execute_CGetPerm rd cb )" |" execute (CGetType (rd,cb)) = ( execute_CGetType rd cb )" |" execute (CGetBase (rd,cb)) = ( execute_CGetBase rd cb )" @@ -8910,7 +8660,7 @@ fun execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " |" execute (CCSeal (cd1,cs,ct)) = ( execute_CCSeal cd1 cs ct )" |" execute (CUnseal (cd1,cs,ct)) = ( execute_CUnseal cd1 cs ct )" |" execute (CCall (cs,cb,b__151)) = ( execute_CCall cs cb b__151 )" -|" execute (CReturn (g__129)) = ( execute_CReturn g__129 )" +|" execute (CReturn (g__27)) = ( execute_CReturn g__27 )" |" execute (CBX (cb,imm,notset)) = ( execute_CBX cb imm notset )" |" execute (CBZ (cb,imm,notzero)) = ( execute_CBZ cb imm notzero )" |" execute (CJALR (cd1,cb,link)) = ( execute_CJALR cd1 cb link )" @@ -8921,7 +8671,7 @@ fun execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " |" execute (CSC (cs,cb,rt,rd,offset,conditional)) = ( execute_CSC cs cb rt rd offset conditional )" |" execute (CLC (cd1,cb,rt,offset,linked)) = ( execute_CLC cd1 cb rt offset linked )" |" execute (C2Dump (rt)) = ( return ((execute_C2Dump rt)))" -|" execute (RI (g__130)) = ( execute_RI g__130 )" +|" execute (RI (g__28)) = ( execute_RI g__28 )" (*val supported_instructions : ast -> maybe ast*) @@ -8930,50 +8680,62 @@ definition supported_instructions :: " ast \<Rightarrow>(ast)option " where " supported_instructions instr = ( Some instr )" -(*val fetch_and_execute : unit -> M unit*) +(*val cycle_limit_reached : unit -> bool*) -definition fetch_and_execute :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " fetch_and_execute _ = ( - catch_early_return - (((whileM () - (\<lambda> unit_var . return True) - (\<lambda> unit_var . - liftR ((read_reg nextPC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__0 :: 64 bits) . - (liftR (write_reg PC_ref w__0) \<then> - liftR ((read_reg branchPending_ref :: ( 1 Word.word) M))) \<bind> (\<lambda> (w__1 :: 1 bits) . - ((liftR (write_reg inBranchDelay_ref w__1) \<then> - liftR (write_reg branchPending_ref (vec_of_bits [B0] :: 1 Word.word))) \<then> - liftR ((read_reg inBranchDelay_ref :: ( 1 Word.word) M))) \<bind> (\<lambda> (w__2 :: 1 Word.word) . - (if ((bits_to_bool w__2)) then liftR ((read_reg delayedPC_ref :: ( 64 Word.word) M)) - else - liftR ((read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64 Word.word) . - return ((add_vec_int w__4 (( 4 :: int)::ii) :: 64 Word.word)))) \<bind> (\<lambda> (w__5 :: 64 Word.word) . - ((liftR (write_reg nextPC_ref w__5) \<then> - liftR (cp2_next_pc () )) \<then> - liftR (read_reg instCount_ref)) \<bind> (\<lambda> (w__6 :: ii) . - (liftR (write_reg instCount_ref ((w__6 + (( 1 :: int)::ii)))) \<then> - liftR ((read_reg PC_ref :: ( 64 Word.word) M))) \<bind> (\<lambda> (w__7 :: 64 bits) . - (let (_ :: unit) = (print_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict (''PC: '') w__7) in - try_catchR (liftR ((read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__8 :: 64 Word.word) . - liftR ((TranslatePC w__8 :: ( 64 Word.word) M)) \<bind> (\<lambda> pc_pa . - liftR ((MEMr_wrapper pc_pa (( 4 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> instr . - (let instr_ast = (decode instr) in - (case instr_ast of - Some ((HCF (_))) => - (let (_ :: unit) = - (prerr_endline (''simulation stopped due to halt instruction.'')) in - (early_return () :: (unit, unit) MR)) - | Some (ast) => liftR (execute ast) - | None => - (let (_ :: unit) = (prerr_endline (''Decode failed'')) in - liftR (exit0 () )) - )))))) (\<lambda>x . - (case x of ISAException (_) => return ((prerr_endline (''EXCEPTION''))) ))))))))))) \<then> - liftR (skip () )) \<then> liftR (skip () )))" +definition cycle_limit_reached :: " unit \<Rightarrow> bool " where + " cycle_limit_reached _ = ( False )" -(*val main : unit -> M unit*) +(*val fetch_and_execute : unit -> M bool*) + +definition fetch_and_execute :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " fetch_and_execute _ = ( + (read_reg nextPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + (write_reg PC_ref w__0 \<then> + (read_reg branchPending_ref :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__1 :: 1 bits) . + ((write_reg inBranchDelay_ref w__1 \<then> + write_reg branchPending_ref (vec_of_bits [B0] :: 1 Word.word)) \<then> + (read_reg inBranchDelay_ref :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__2 :: 1 Word.word) . + (if ((bits_to_bool w__2)) then (read_reg delayedPC_ref :: ( 64 Word.word) M) + else + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . + return ((add_vec_int w__4 (( 4 :: int)::ii) :: 64 Word.word)))) \<bind> (\<lambda> (w__5 :: 64 Word.word) . + ((write_reg nextPC_ref w__5 \<then> + cp2_next_pc () ) \<then> + read_reg instCount_ref) \<bind> (\<lambda> (w__6 :: ii) . + (write_reg instCount_ref ((w__6 + (( 1 :: int)::ii))) \<then> + (read_reg UART_WRITTEN_ref :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__7 :: 1 Word.word) . + (((if ((bits_to_bool w__7)) then + (read_reg UART_WDATA_ref :: ( 8 Word.word) M) \<bind> (\<lambda> (w__8 :: 8 bits) . + (let (_ :: unit) = (putchar ((Word.uint w__8))) in + write_reg UART_WRITTEN_ref (vec_of_bits [B0] :: 1 Word.word))) + else return () ) \<then> + skip () ) \<then> + skip () ) \<then> + ((let loop_again = True in + try_catch ((read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 Word.word) . + (TranslatePC w__9 :: ( 64 Word.word) M) \<bind> (\<lambda> pc_pa . + (MEMr_wrapper (( 32 :: int)::ii) pc_pa (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> instr . + (let instr_ast = (decode instr) in + (case instr_ast of + Some ((HCF (_))) => + (let (_ :: unit) = (print_endline (''simulation stopped due to halt instruction.'')) in + return False) + | Some (ast) => execute ast \<then> return loop_again + | None => + (let (_ :: unit) = (print_endline (''Decode failed'')) in + return False) + )))))) (\<lambda>x . + (case x of ISAException (_) => return loop_again )) \<bind> (\<lambda> (loop_again :: bool) . + return (((loop_again \<and> ((\<not> ((cycle_limit_reached () )))))))))))))))))" + + +(*val init_registers : mword ty64 -> M unit*) + +definition init_registers :: "(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " init_registers initialPC = ( + (init_cp0_state () \<then> init_cp2_state () ) \<then> write_reg nextPC_ref initialPC )" + (*val dump_mips_state : unit -> M unit*) @@ -8981,38 +8743,36 @@ definition dump_mips_state :: " unit \<Rightarrow>((register_value),(unit),(exc " dump_mips_state _ = ( (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (let (_ :: unit) = (print_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict (''DEBUG MIPS PC '') w__0) in + instance_Sail2_values_Bitvector_Machine_word_mword_dict (''DEBUG MIPS PC '') w__0) in (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () (\<lambda> idx unit_var . (rGPR ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) idx :: 5 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . return ((let _ = - (prerr_endline + (print_endline (((op@) (''DEBUG MIPS REG '') (((op@) ((string_of_int - instance_Show_Show_Num_integer_dict idx)) (((op@) ('' '') ((string_of_bits - instance_Sail_values_Bitvector_Machine_word_mword_dict w__1))))))))) in + instance_Show_Show_Num_integer_dict idx)) (((op@) ('' '') ((string_of_bits w__1))))))))) in () ))))))))" +(*val main : unit -> M unit*) + definition main :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " main _ = ( - ((init_cp0_state () \<then> - init_cp2_state () ) \<then> - write_reg - nextPC_ref - ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((elf_entry () )) :: 64 Word.word))) \<then> + init_registers + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((elf_entry () )) :: 64 Word.word)) \<then> ((let startTime = (get_time_ns () ) in - fetch_and_execute () \<then> + (whileM () (\<lambda> unit_var . fetch_and_execute () ) (\<lambda> unit_var . return () )) \<then> ((let endTime = (get_time_ns () ) in (let elapsed = (endTime - startTime) in - read_reg instCount_ref \<bind> (\<lambda> (w__0 :: ii) . - (let inst_1e9 = (w__0 * (( 1000000000 :: int)::ii)) in + read_reg instCount_ref \<bind> (\<lambda> (w__1 :: ii) . + (let inst_1e9 = (w__1 * (( 1000000000 :: int)::ii)) in (let ips = (inst_1e9 div elapsed) in ((dump_mips_state () \<then> dump_cp2_state () ) \<then> - read_reg instCount_ref) \<bind> (\<lambda> (w__1 :: ii) . - (let (_ :: unit) = (print_int (''Executed instructions: '') w__1) in + read_reg instCount_ref) \<bind> (\<lambda> (w__2 :: ii) . + (let (_ :: unit) = (print_int (''Executed instructions: '') w__2) in (let (_ :: unit) = (print_int (''Nanoseconds elapsed: '') elapsed) in return ((print_int (''Instructions per second: '') ips))))))))))))))" @@ -9022,19 +8782,19 @@ definition main :: " unit \<Rightarrow>((register_value),(unit),(exception))mon definition initialize_registers :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " initialize_registers _ = ( (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . (write_reg PC_ref w__0 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 bits) . (write_reg nextPC_ref w__1 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__2 :: 1 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__2 :: 1 bits) . (write_reg TLBProbe_ref w__2 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__3 :: TLBIndexT) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__3 :: TLBIndexT) . (write_reg TLBIndex_ref w__3 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__4 :: TLBIndexT) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__4 :: TLBIndexT) . (write_reg TLBRandom_ref w__4 \<then> undefined_TLBEntryLoReg () ) \<bind> (\<lambda> (w__5 :: TLBEntryLoReg) . (write_reg TLBEntryLo0_ref w__5 \<then> @@ -9043,10 +8803,10 @@ definition initialize_registers :: " unit \<Rightarrow>((register_value),(unit) undefined_ContextReg () ) \<bind> (\<lambda> (w__7 :: ContextReg) . (write_reg TLBContext_ref w__7 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__8 :: 16 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__8 :: 16 bits) . (write_reg TLBPageMask_ref w__8 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__9 :: TLBIndexT) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__9 :: TLBIndexT) . (write_reg TLBWired_ref w__9 \<then> undefined_TLBEntryHiReg () ) \<bind> (\<lambda> (w__10 :: TLBEntryHiReg) . (write_reg TLBEntryHi_ref w__10 \<then> @@ -9181,191 +8941,270 @@ definition initialize_registers :: " unit \<Rightarrow>((register_value),(unit) undefined_TLBEntry () ) \<bind> (\<lambda> (w__75 :: TLBEntry) . (write_reg TLBEntry63_ref w__75 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__76 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__76 :: 32 bits) . (write_reg CP0Compare_ref w__76 \<then> undefined_CauseReg () ) \<bind> (\<lambda> (w__77 :: CauseReg) . (write_reg CP0Cause_ref w__77 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__78 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__78 :: 64 bits) . (write_reg CP0EPC_ref w__78 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__79 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__79 :: 64 bits) . (write_reg CP0ErrorEPC_ref w__79 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__80 :: 1 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__80 :: 1 bits) . (write_reg CP0LLBit_ref w__80 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__81 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__81 :: 64 bits) . (write_reg CP0LLAddr_ref w__81 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__82 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__82 :: 64 bits) . (write_reg CP0BadVAddr_ref w__82 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__83 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__83 :: 32 bits) . (write_reg CP0Count_ref w__83 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__84 :: 32 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__84 :: 32 bits) . (write_reg CP0HWREna_ref w__84 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__85 :: 64 bits) . + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__85 :: 64 bits) . (write_reg CP0UserLocal_ref w__85 \<then> - undefined_StatusReg () ) \<bind> (\<lambda> (w__86 :: StatusReg) . - (write_reg CP0Status_ref w__86 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__87 :: 1 bits) . - (write_reg branchPending_ref w__87 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 3 :: int)::ii) :: ( 3 Word.word) M)) \<bind> (\<lambda> (w__86 :: 3 bits) . + (write_reg CP0ConfigK0_ref w__86 \<then> + undefined_StatusReg () ) \<bind> (\<lambda> (w__87 :: StatusReg) . + (write_reg CP0Status_ref w__87 \<then> + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__88 :: 1 bits) . + (write_reg branchPending_ref w__88 \<then> + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__89 :: 1 bits) . + (write_reg inBranchDelay_ref w__89 \<then> + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__90 :: 64 bits) . + (write_reg delayedPC_ref w__90 \<then> + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__91 :: 64 bits) . + (write_reg HI_ref w__91 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__88 :: 1 bits) . - (write_reg inBranchDelay_ref w__88 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__92 :: 64 bits) . + (write_reg LO_ref w__92 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__89 :: 64 bits) . - (write_reg delayedPC_ref w__89 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__93 :: 64 Word.word) . + (undefined_vector (( 32 :: int)::ii) w__93 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__94 :: ( 64 bits) list) . + (write_reg GPR_ref w__94 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__90 :: 64 bits) . - (write_reg HI_ref w__90 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__95 :: 8 bits) . + (write_reg UART_WDATA_ref w__95 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__91 :: 64 bits) . - (write_reg LO_ref w__91 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__96 :: 1 bits) . + (write_reg UART_WRITTEN_ref w__96 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__92 :: 64 Word.word) . - (undefined_vector (( 32 :: int)::ii) w__92 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__93 :: ( 64 bits) list) . - (write_reg GPR_ref w__93 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__97 :: 8 bits) . + (write_reg UART_RDATA_ref w__97 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__94 :: 8 bits) . - (write_reg UART_WDATA_ref w__94 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__98 :: 1 bits) . + (write_reg UART_RVALID_ref w__98 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__95 :: 1 bits) . - (write_reg UART_WRITTEN_ref w__95 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__99 :: CapReg) . + (write_reg PCC_ref w__99 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__96 :: 8 bits) . - (write_reg UART_RDATA_ref w__96 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__100 :: CapReg) . + (write_reg nextPCC_ref w__100 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__97 :: 1 bits) . - (write_reg UART_RVALID_ref w__97 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__101 :: CapReg) . + (write_reg delayedPCC_ref w__101 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__98 :: CapReg) . - (write_reg PCC_ref w__98 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__102 :: 1 bits) . + (write_reg inCCallDelay_ref w__102 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__99 :: CapReg) . - (write_reg nextPCC_ref w__99 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__103 :: CapReg) . + (write_reg DDC_ref w__103 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__100 :: CapReg) . - (write_reg delayedPCC_ref w__100 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__104 :: CapReg) . + (write_reg C01_ref w__104 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__101 :: 1 bits) . - (write_reg inCCallDelay_ref w__101 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__105 :: CapReg) . + (write_reg C02_ref w__105 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__102 :: CapReg) . - (write_reg C00_ref w__102 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__106 :: CapReg) . + (write_reg C03_ref w__106 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__103 :: CapReg) . - (write_reg C01_ref w__103 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__107 :: CapReg) . + (write_reg C04_ref w__107 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__104 :: CapReg) . - (write_reg C02_ref w__104 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__108 :: CapReg) . + (write_reg C05_ref w__108 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__105 :: CapReg) . - (write_reg C03_ref w__105 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__109 :: CapReg) . + (write_reg C06_ref w__109 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__106 :: CapReg) . - (write_reg C04_ref w__106 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__110 :: CapReg) . + (write_reg C07_ref w__110 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__107 :: CapReg) . - (write_reg C05_ref w__107 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__111 :: CapReg) . + (write_reg C08_ref w__111 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__108 :: CapReg) . - (write_reg C06_ref w__108 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__112 :: CapReg) . + (write_reg C09_ref w__112 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__109 :: CapReg) . - (write_reg C07_ref w__109 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__113 :: CapReg) . + (write_reg C10_ref w__113 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__110 :: CapReg) . - (write_reg C08_ref w__110 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__114 :: CapReg) . + (write_reg C11_ref w__114 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__111 :: CapReg) . - (write_reg C09_ref w__111 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__115 :: CapReg) . + (write_reg C12_ref w__115 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__112 :: CapReg) . - (write_reg C10_ref w__112 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__116 :: CapReg) . + (write_reg C13_ref w__116 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__113 :: CapReg) . - (write_reg C11_ref w__113 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__117 :: CapReg) . + (write_reg C14_ref w__117 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__114 :: CapReg) . - (write_reg C12_ref w__114 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__118 :: CapReg) . + (write_reg C15_ref w__118 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__115 :: CapReg) . - (write_reg C13_ref w__115 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__119 :: CapReg) . + (write_reg C16_ref w__119 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__116 :: CapReg) . - (write_reg C14_ref w__116 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__120 :: CapReg) . + (write_reg C17_ref w__120 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__117 :: CapReg) . - (write_reg C15_ref w__117 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__121 :: CapReg) . + (write_reg C18_ref w__121 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__118 :: CapReg) . - (write_reg C16_ref w__118 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__122 :: CapReg) . + (write_reg C19_ref w__122 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__119 :: CapReg) . - (write_reg C17_ref w__119 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__123 :: CapReg) . + (write_reg C20_ref w__123 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__120 :: CapReg) . - (write_reg C18_ref w__120 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__124 :: CapReg) . + (write_reg C21_ref w__124 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__121 :: CapReg) . - (write_reg C19_ref w__121 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__125 :: CapReg) . + (write_reg C22_ref w__125 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__122 :: CapReg) . - (write_reg C20_ref w__122 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__126 :: CapReg) . + (write_reg C23_ref w__126 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__123 :: CapReg) . - (write_reg C21_ref w__123 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__127 :: CapReg) . + (write_reg C24_ref w__127 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__124 :: CapReg) . - (write_reg C22_ref w__124 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__128 :: CapReg) . + (write_reg C25_ref w__128 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__125 :: CapReg) . - (write_reg C23_ref w__125 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__129 :: CapReg) . + (write_reg C26_ref w__129 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__126 :: CapReg) . - (write_reg C24_ref w__126 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__130 :: CapReg) . + (write_reg C27_ref w__130 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__127 :: CapReg) . - (write_reg C25_ref w__127 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__131 :: CapReg) . + (write_reg C28_ref w__131 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__128 :: CapReg) . - (write_reg C26_ref w__128 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__132 :: CapReg) . + (write_reg C29_ref w__132 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__129 :: CapReg) . - (write_reg C27_ref w__129 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__133 :: CapReg) . + (write_reg C30_ref w__133 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__130 :: CapReg) . - (write_reg C28_ref w__130 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__134 :: CapReg) . + (write_reg C31_ref w__134 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__131 :: CapReg) . - (write_reg C29_ref w__131 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__135 :: CapReg) . + (write_reg CTLSU_ref w__135 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__132 :: CapReg) . - (write_reg C30_ref w__132 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__136 :: CapReg) . + (write_reg CTLSP_ref w__136 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__133 :: CapReg) . - (write_reg C31_ref w__133 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__137 :: CapReg) . + (write_reg KR1C_ref w__137 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__134 :: CapReg) . - (write_reg CTLSU_ref w__134 \<then> + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__138 :: CapReg) . + (write_reg KR2C_ref w__138 \<then> (undefined_bitvector - instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__135 :: CapReg) . - (write_reg CTLSP_ref w__135 \<then> - undefined_CapCauseReg () ) \<bind> (\<lambda> (w__136 :: CapCauseReg) . - (write_reg CapCause_ref w__136 \<then> - undefined_int () ) \<bind> (\<lambda> (w__137 :: ii) . write_reg instCount_ref w__137)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__139 :: CapReg) . + (write_reg KCC_ref w__139 \<then> + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__140 :: CapReg) . + (write_reg KDC_ref w__140 \<then> + (undefined_bitvector + instance_Sail2_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__141 :: CapReg) . + (write_reg EPCC_ref w__141 \<then> + undefined_CapCauseReg () ) \<bind> (\<lambda> (w__142 :: CapCauseReg) . + (write_reg CapCause_ref w__142 \<then> + undefined_int () ) \<bind> (\<lambda> (w__143 :: ii) . write_reg instCount_ref w__143)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" definition initial_regstate :: " regstate " where " initial_regstate = ( (| instCount = ((( 0 :: int)::ii)), CapCause = - (Mk_CapCauseReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)), + ((| CapCauseReg_CapCauseReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)) |)), + EPCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + KDC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + KCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + KR2C = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + KR1C = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), CTLSP = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -9762,7 +9601,7 @@ definition initial_regstate :: " regstate " where B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 257 Word.word)), - C00 = + DDC = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -9962,9 +9801,11 @@ definition initial_regstate :: " regstate " where inBranchDelay = ((vec_of_bits [B0] :: 1 Word.word)), branchPending = ((vec_of_bits [B0] :: 1 Word.word)), CP0Status = - (Mk_StatusReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 32 Word.word)), + ((| StatusReg_StatusReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)) |)), + CP0ConfigK0 = ((vec_of_bits [B0,B0,B0] :: 3 Word.word)), CP0UserLocal = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -10000,557 +9841,750 @@ definition initial_regstate :: " regstate " where B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)), CP0Cause = - (Mk_CauseReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 32 Word.word)), + ((| CauseReg_CauseReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)) |)), CP0Compare = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0] :: 32 Word.word)), TLBEntry63 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry62 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry61 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry60 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry59 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry58 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry57 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry56 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry55 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry54 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry53 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry52 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry51 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry50 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry49 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry48 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry47 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry46 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry45 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry44 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry43 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry42 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry41 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry40 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry39 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry38 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry37 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry36 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry35 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry34 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry33 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry32 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry31 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry30 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry29 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry28 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry27 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry26 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry25 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry24 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry23 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry22 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry21 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry20 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry19 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry18 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry17 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry16 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry15 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry14 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry13 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry12 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry11 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry10 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry09 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry08 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry07 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry06 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry05 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry04 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry03 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry02 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry01 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntry00 = - (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0] - :: 117 Word.word)), + ((| TLBEntry_TLBEntry_chunk_1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 53 Word.word)), + TLBEntry_TLBEntry_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBXContext = - (Mk_XContextReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0] - :: 64 Word.word)), + ((| XContextReg_XContextReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntryHi = - (Mk_TLBEntryHiReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0] - :: 64 Word.word)), + ((| TLBEntryHiReg_TLBEntryHiReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBWired = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), TLBPageMask = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)), TLBContext = - (Mk_ContextReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0] - :: 64 Word.word)), + ((| ContextReg_ContextReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntryLo1 = - (Mk_TLBEntryLoReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0] - :: 64 Word.word)), + ((| TLBEntryLoReg_TLBEntryLoReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBEntryLo0 = - (Mk_TLBEntryLoReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0] - :: 64 Word.word)), + ((| TLBEntryLoReg_TLBEntryLoReg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), TLBRandom = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), TLBIndex = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), TLBProbe = ((vec_of_bits [B0] :: 1 Word.word)), diff --git a/snapshots/isabelle/cheri/Cheri_lemmas.thy b/snapshots/isabelle/cheri/Cheri_lemmas.thy index 6dbee433..50ef7af2 100644 --- a/snapshots/isabelle/cheri/Cheri_lemmas.thy +++ b/snapshots/isabelle/cheri/Cheri_lemmas.thy @@ -1,38 +1,38 @@ theory Cheri_lemmas imports - Sail.Sail_values_lemmas - Sail.State_lemmas + Sail.Sail2_values_lemmas + Sail.Sail2_state_lemmas Cheri begin -abbreviation "liftS \<equiv> liftState (get_regval, set_regval)" - -lemmas register_defs = get_regval_def set_regval_def instCount_ref_def CapCause_ref_def - CTLSP_ref_def CTLSU_ref_def C30_ref_def C28_ref_def C27_ref_def C26_ref_def C25_ref_def - C24_ref_def C23_ref_def C22_ref_def C21_ref_def C20_ref_def C19_ref_def C18_ref_def C17_ref_def - C16_ref_def C15_ref_def C14_ref_def C13_ref_def C12_ref_def C11_ref_def C10_ref_def C09_ref_def - C08_ref_def C07_ref_def C06_ref_def C05_ref_def C04_ref_def C03_ref_def C02_ref_def C01_ref_def - C00_ref_def inCCallDelay_ref_def nextPCC_ref_def delayedPCC_ref_def PCC_ref_def C31_ref_def - C29_ref_def UART_RVALID_ref_def UART_RDATA_ref_def UART_WRITTEN_ref_def UART_WDATA_ref_def - GPR_ref_def LO_ref_def HI_ref_def delayedPC_ref_def inBranchDelay_ref_def branchPending_ref_def - CP0Status_ref_def CP0UserLocal_ref_def CP0HWREna_ref_def CP0Count_ref_def CP0BadVAddr_ref_def - CP0LLAddr_ref_def CP0LLBit_ref_def CP0ErrorEPC_ref_def CP0EPC_ref_def CP0Cause_ref_def - CP0Compare_ref_def TLBEntry63_ref_def TLBEntry62_ref_def TLBEntry61_ref_def TLBEntry60_ref_def - TLBEntry59_ref_def TLBEntry58_ref_def TLBEntry57_ref_def TLBEntry56_ref_def TLBEntry55_ref_def - TLBEntry54_ref_def TLBEntry53_ref_def TLBEntry52_ref_def TLBEntry51_ref_def TLBEntry50_ref_def - TLBEntry49_ref_def TLBEntry48_ref_def TLBEntry47_ref_def TLBEntry46_ref_def TLBEntry45_ref_def - TLBEntry44_ref_def TLBEntry43_ref_def TLBEntry42_ref_def TLBEntry41_ref_def TLBEntry40_ref_def - TLBEntry39_ref_def TLBEntry38_ref_def TLBEntry37_ref_def TLBEntry36_ref_def TLBEntry35_ref_def - TLBEntry34_ref_def TLBEntry33_ref_def TLBEntry32_ref_def TLBEntry31_ref_def TLBEntry30_ref_def - TLBEntry29_ref_def TLBEntry28_ref_def TLBEntry27_ref_def TLBEntry26_ref_def TLBEntry25_ref_def - TLBEntry24_ref_def TLBEntry23_ref_def TLBEntry22_ref_def TLBEntry21_ref_def TLBEntry20_ref_def - TLBEntry19_ref_def TLBEntry18_ref_def TLBEntry17_ref_def TLBEntry16_ref_def TLBEntry15_ref_def - TLBEntry14_ref_def TLBEntry13_ref_def TLBEntry12_ref_def TLBEntry11_ref_def TLBEntry10_ref_def - TLBEntry09_ref_def TLBEntry08_ref_def TLBEntry07_ref_def TLBEntry06_ref_def TLBEntry05_ref_def - TLBEntry04_ref_def TLBEntry03_ref_def TLBEntry02_ref_def TLBEntry01_ref_def TLBEntry00_ref_def - TLBXContext_ref_def TLBEntryHi_ref_def TLBWired_ref_def TLBPageMask_ref_def TLBContext_ref_def - TLBEntryLo1_ref_def TLBEntryLo0_ref_def TLBRandom_ref_def TLBIndex_ref_def TLBProbe_ref_def - nextPC_ref_def PC_ref_def +abbreviation liftS ("\<lbrakk>_\<rbrakk>\<^sub>S") where "liftS \<equiv> liftState (get_regval, set_regval)" + +lemmas register_defs = get_regval_def set_regval_def instCount_ref_def CapCause_ref_def KDC_ref_def + KR2C_ref_def KR1C_ref_def CTLSP_ref_def CTLSU_ref_def C31_ref_def C30_ref_def C29_ref_def + C28_ref_def C27_ref_def C26_ref_def C25_ref_def C24_ref_def C23_ref_def C22_ref_def C21_ref_def + C20_ref_def C19_ref_def C18_ref_def C17_ref_def C16_ref_def C15_ref_def C14_ref_def C13_ref_def + C12_ref_def C11_ref_def C10_ref_def C09_ref_def C08_ref_def C07_ref_def C06_ref_def C05_ref_def + C04_ref_def C03_ref_def C02_ref_def C01_ref_def DDC_ref_def inCCallDelay_ref_def nextPCC_ref_def + delayedPCC_ref_def PCC_ref_def KCC_ref_def EPCC_ref_def UART_RVALID_ref_def UART_RDATA_ref_def + UART_WRITTEN_ref_def UART_WDATA_ref_def GPR_ref_def LO_ref_def HI_ref_def delayedPC_ref_def + inBranchDelay_ref_def branchPending_ref_def CP0Status_ref_def CP0ConfigK0_ref_def + CP0UserLocal_ref_def CP0HWREna_ref_def CP0Count_ref_def CP0BadVAddr_ref_def CP0LLAddr_ref_def + CP0LLBit_ref_def CP0ErrorEPC_ref_def CP0EPC_ref_def CP0Cause_ref_def CP0Compare_ref_def + TLBEntry63_ref_def TLBEntry62_ref_def TLBEntry61_ref_def TLBEntry60_ref_def TLBEntry59_ref_def + TLBEntry58_ref_def TLBEntry57_ref_def TLBEntry56_ref_def TLBEntry55_ref_def TLBEntry54_ref_def + TLBEntry53_ref_def TLBEntry52_ref_def TLBEntry51_ref_def TLBEntry50_ref_def TLBEntry49_ref_def + TLBEntry48_ref_def TLBEntry47_ref_def TLBEntry46_ref_def TLBEntry45_ref_def TLBEntry44_ref_def + TLBEntry43_ref_def TLBEntry42_ref_def TLBEntry41_ref_def TLBEntry40_ref_def TLBEntry39_ref_def + TLBEntry38_ref_def TLBEntry37_ref_def TLBEntry36_ref_def TLBEntry35_ref_def TLBEntry34_ref_def + TLBEntry33_ref_def TLBEntry32_ref_def TLBEntry31_ref_def TLBEntry30_ref_def TLBEntry29_ref_def + TLBEntry28_ref_def TLBEntry27_ref_def TLBEntry26_ref_def TLBEntry25_ref_def TLBEntry24_ref_def + TLBEntry23_ref_def TLBEntry22_ref_def TLBEntry21_ref_def TLBEntry20_ref_def TLBEntry19_ref_def + TLBEntry18_ref_def TLBEntry17_ref_def TLBEntry16_ref_def TLBEntry15_ref_def TLBEntry14_ref_def + TLBEntry13_ref_def TLBEntry12_ref_def TLBEntry11_ref_def TLBEntry10_ref_def TLBEntry09_ref_def + TLBEntry08_ref_def TLBEntry07_ref_def TLBEntry06_ref_def TLBEntry05_ref_def TLBEntry04_ref_def + TLBEntry03_ref_def TLBEntry02_ref_def TLBEntry01_ref_def TLBEntry00_ref_def TLBXContext_ref_def + TLBEntryHi_ref_def TLBWired_ref_def TLBPageMask_ref_def TLBContext_ref_def TLBEntryLo1_ref_def + TLBEntryLo0_ref_def TLBRandom_ref_def TLBIndex_ref_def TLBProbe_ref_def nextPC_ref_def PC_ref_def lemma regval_CapCauseReg[simp]: "CapCauseReg_of_regval (regval_of_CapCauseReg v) = Some v" @@ -86,6 +86,10 @@ lemma regval_vector_32_dec_bit[simp]: "vector_32_dec_bit_of_regval (regval_of_vector_32_dec_bit v) = Some v" by (auto simp: regval_of_vector_32_dec_bit_def) +lemma regval_vector_3_dec_bit[simp]: + "vector_3_dec_bit_of_regval (regval_of_vector_3_dec_bit v) = Some v" + by (auto simp: regval_of_vector_3_dec_bit_def) + lemma regval_vector_64_dec_bit[simp]: "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v" by (auto simp: regval_of_vector_64_dec_bit_def) @@ -106,1100 +110,1161 @@ proof - then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def) qed -lemma liftS_read_reg_instCount[simp]: - "liftS (read_reg instCount_ref) = readS (instCount \<circ> regstate)" +lemma option_of_rv_rv_of_option[simp]: + assumes "\<And>v. of_rv (rv_of v) = Some v" + shows "option_of_regval of_rv (regval_of_option rv_of v) = Some v" + using assms by (cases v) (auto simp: option_of_regval_def regval_of_option_def) + +lemma list_of_rv_rv_of_list[simp]: + assumes "\<And>v. of_rv (rv_of v) = Some v" + shows "list_of_regval of_rv (regval_of_list rv_of v) = Some v" +proof - + from assms have "of_rv \<circ> rv_of = Some" by auto + with assms show ?thesis by (induction v) (auto simp: list_of_regval_def regval_of_list_def) +qed + +lemma liftS_read_reg_instCount[liftState_simp]: + "\<lbrakk>read_reg instCount_ref\<rbrakk>\<^sub>S = readS (instCount \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_instCount[liftState_simp]: + "\<lbrakk>write_reg instCount_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (instCount_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CapCause[liftState_simp]: + "\<lbrakk>read_reg CapCause_ref\<rbrakk>\<^sub>S = readS (CapCause \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CapCause[liftState_simp]: + "\<lbrakk>write_reg CapCause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CapCause_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_KDC[liftState_simp]: + "\<lbrakk>read_reg KDC_ref\<rbrakk>\<^sub>S = readS (KDC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_KDC[liftState_simp]: + "\<lbrakk>write_reg KDC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (KDC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_KR2C[liftState_simp]: + "\<lbrakk>read_reg KR2C_ref\<rbrakk>\<^sub>S = readS (KR2C \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_KR2C[liftState_simp]: + "\<lbrakk>write_reg KR2C_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (KR2C_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_KR1C[liftState_simp]: + "\<lbrakk>read_reg KR1C_ref\<rbrakk>\<^sub>S = readS (KR1C \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_KR1C[liftState_simp]: + "\<lbrakk>write_reg KR1C_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (KR1C_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CTLSP[liftState_simp]: + "\<lbrakk>read_reg CTLSP_ref\<rbrakk>\<^sub>S = readS (CTLSP \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CTLSP[liftState_simp]: + "\<lbrakk>write_reg CTLSP_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CTLSP_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CTLSU[liftState_simp]: + "\<lbrakk>read_reg CTLSU_ref\<rbrakk>\<^sub>S = readS (CTLSU \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_instCount[simp]: - "liftS (write_reg instCount_ref v) = updateS (regstate_update (instCount_update (\<lambda>_. v)))" +lemma liftS_write_reg_CTLSU[liftState_simp]: + "\<lbrakk>write_reg CTLSU_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CTLSU_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CapCause[simp]: - "liftS (read_reg CapCause_ref) = readS (CapCause \<circ> regstate)" +lemma liftS_read_reg_C31[liftState_simp]: + "\<lbrakk>read_reg C31_ref\<rbrakk>\<^sub>S = readS (C31 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CapCause[simp]: - "liftS (write_reg CapCause_ref v) = updateS (regstate_update (CapCause_update (\<lambda>_. v)))" +lemma liftS_write_reg_C31[liftState_simp]: + "\<lbrakk>write_reg C31_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C31_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CTLSP[simp]: - "liftS (read_reg CTLSP_ref) = readS (CTLSP \<circ> regstate)" +lemma liftS_read_reg_C30[liftState_simp]: + "\<lbrakk>read_reg C30_ref\<rbrakk>\<^sub>S = readS (C30 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CTLSP[simp]: - "liftS (write_reg CTLSP_ref v) = updateS (regstate_update (CTLSP_update (\<lambda>_. v)))" +lemma liftS_write_reg_C30[liftState_simp]: + "\<lbrakk>write_reg C30_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C30_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CTLSU[simp]: - "liftS (read_reg CTLSU_ref) = readS (CTLSU \<circ> regstate)" +lemma liftS_read_reg_C29[liftState_simp]: + "\<lbrakk>read_reg C29_ref\<rbrakk>\<^sub>S = readS (C29 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CTLSU[simp]: - "liftS (write_reg CTLSU_ref v) = updateS (regstate_update (CTLSU_update (\<lambda>_. v)))" +lemma liftS_write_reg_C29[liftState_simp]: + "\<lbrakk>write_reg C29_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C29_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C30[simp]: - "liftS (read_reg C30_ref) = readS (C30 \<circ> regstate)" +lemma liftS_read_reg_C28[liftState_simp]: + "\<lbrakk>read_reg C28_ref\<rbrakk>\<^sub>S = readS (C28 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C30[simp]: - "liftS (write_reg C30_ref v) = updateS (regstate_update (C30_update (\<lambda>_. v)))" +lemma liftS_write_reg_C28[liftState_simp]: + "\<lbrakk>write_reg C28_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C28_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C28[simp]: - "liftS (read_reg C28_ref) = readS (C28 \<circ> regstate)" +lemma liftS_read_reg_C27[liftState_simp]: + "\<lbrakk>read_reg C27_ref\<rbrakk>\<^sub>S = readS (C27 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C28[simp]: - "liftS (write_reg C28_ref v) = updateS (regstate_update (C28_update (\<lambda>_. v)))" +lemma liftS_write_reg_C27[liftState_simp]: + "\<lbrakk>write_reg C27_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C27_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C27[simp]: - "liftS (read_reg C27_ref) = readS (C27 \<circ> regstate)" +lemma liftS_read_reg_C26[liftState_simp]: + "\<lbrakk>read_reg C26_ref\<rbrakk>\<^sub>S = readS (C26 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C27[simp]: - "liftS (write_reg C27_ref v) = updateS (regstate_update (C27_update (\<lambda>_. v)))" +lemma liftS_write_reg_C26[liftState_simp]: + "\<lbrakk>write_reg C26_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C26_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C26[simp]: - "liftS (read_reg C26_ref) = readS (C26 \<circ> regstate)" +lemma liftS_read_reg_C25[liftState_simp]: + "\<lbrakk>read_reg C25_ref\<rbrakk>\<^sub>S = readS (C25 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C26[simp]: - "liftS (write_reg C26_ref v) = updateS (regstate_update (C26_update (\<lambda>_. v)))" +lemma liftS_write_reg_C25[liftState_simp]: + "\<lbrakk>write_reg C25_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C25_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C25[simp]: - "liftS (read_reg C25_ref) = readS (C25 \<circ> regstate)" +lemma liftS_read_reg_C24[liftState_simp]: + "\<lbrakk>read_reg C24_ref\<rbrakk>\<^sub>S = readS (C24 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C25[simp]: - "liftS (write_reg C25_ref v) = updateS (regstate_update (C25_update (\<lambda>_. v)))" +lemma liftS_write_reg_C24[liftState_simp]: + "\<lbrakk>write_reg C24_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C24_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C24[simp]: - "liftS (read_reg C24_ref) = readS (C24 \<circ> regstate)" +lemma liftS_read_reg_C23[liftState_simp]: + "\<lbrakk>read_reg C23_ref\<rbrakk>\<^sub>S = readS (C23 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C24[simp]: - "liftS (write_reg C24_ref v) = updateS (regstate_update (C24_update (\<lambda>_. v)))" +lemma liftS_write_reg_C23[liftState_simp]: + "\<lbrakk>write_reg C23_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C23_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C23[simp]: - "liftS (read_reg C23_ref) = readS (C23 \<circ> regstate)" +lemma liftS_read_reg_C22[liftState_simp]: + "\<lbrakk>read_reg C22_ref\<rbrakk>\<^sub>S = readS (C22 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C23[simp]: - "liftS (write_reg C23_ref v) = updateS (regstate_update (C23_update (\<lambda>_. v)))" +lemma liftS_write_reg_C22[liftState_simp]: + "\<lbrakk>write_reg C22_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C22_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C22[simp]: - "liftS (read_reg C22_ref) = readS (C22 \<circ> regstate)" +lemma liftS_read_reg_C21[liftState_simp]: + "\<lbrakk>read_reg C21_ref\<rbrakk>\<^sub>S = readS (C21 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C22[simp]: - "liftS (write_reg C22_ref v) = updateS (regstate_update (C22_update (\<lambda>_. v)))" +lemma liftS_write_reg_C21[liftState_simp]: + "\<lbrakk>write_reg C21_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C21_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C21[simp]: - "liftS (read_reg C21_ref) = readS (C21 \<circ> regstate)" +lemma liftS_read_reg_C20[liftState_simp]: + "\<lbrakk>read_reg C20_ref\<rbrakk>\<^sub>S = readS (C20 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C21[simp]: - "liftS (write_reg C21_ref v) = updateS (regstate_update (C21_update (\<lambda>_. v)))" +lemma liftS_write_reg_C20[liftState_simp]: + "\<lbrakk>write_reg C20_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C20_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C20[simp]: - "liftS (read_reg C20_ref) = readS (C20 \<circ> regstate)" +lemma liftS_read_reg_C19[liftState_simp]: + "\<lbrakk>read_reg C19_ref\<rbrakk>\<^sub>S = readS (C19 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C20[simp]: - "liftS (write_reg C20_ref v) = updateS (regstate_update (C20_update (\<lambda>_. v)))" +lemma liftS_write_reg_C19[liftState_simp]: + "\<lbrakk>write_reg C19_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C19_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C19[simp]: - "liftS (read_reg C19_ref) = readS (C19 \<circ> regstate)" +lemma liftS_read_reg_C18[liftState_simp]: + "\<lbrakk>read_reg C18_ref\<rbrakk>\<^sub>S = readS (C18 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C19[simp]: - "liftS (write_reg C19_ref v) = updateS (regstate_update (C19_update (\<lambda>_. v)))" +lemma liftS_write_reg_C18[liftState_simp]: + "\<lbrakk>write_reg C18_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C18_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C18[simp]: - "liftS (read_reg C18_ref) = readS (C18 \<circ> regstate)" +lemma liftS_read_reg_C17[liftState_simp]: + "\<lbrakk>read_reg C17_ref\<rbrakk>\<^sub>S = readS (C17 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C18[simp]: - "liftS (write_reg C18_ref v) = updateS (regstate_update (C18_update (\<lambda>_. v)))" +lemma liftS_write_reg_C17[liftState_simp]: + "\<lbrakk>write_reg C17_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C17_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C17[simp]: - "liftS (read_reg C17_ref) = readS (C17 \<circ> regstate)" +lemma liftS_read_reg_C16[liftState_simp]: + "\<lbrakk>read_reg C16_ref\<rbrakk>\<^sub>S = readS (C16 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C17[simp]: - "liftS (write_reg C17_ref v) = updateS (regstate_update (C17_update (\<lambda>_. v)))" +lemma liftS_write_reg_C16[liftState_simp]: + "\<lbrakk>write_reg C16_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C16_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C16[simp]: - "liftS (read_reg C16_ref) = readS (C16 \<circ> regstate)" +lemma liftS_read_reg_C15[liftState_simp]: + "\<lbrakk>read_reg C15_ref\<rbrakk>\<^sub>S = readS (C15 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C16[simp]: - "liftS (write_reg C16_ref v) = updateS (regstate_update (C16_update (\<lambda>_. v)))" +lemma liftS_write_reg_C15[liftState_simp]: + "\<lbrakk>write_reg C15_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C15_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C15[simp]: - "liftS (read_reg C15_ref) = readS (C15 \<circ> regstate)" +lemma liftS_read_reg_C14[liftState_simp]: + "\<lbrakk>read_reg C14_ref\<rbrakk>\<^sub>S = readS (C14 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C15[simp]: - "liftS (write_reg C15_ref v) = updateS (regstate_update (C15_update (\<lambda>_. v)))" +lemma liftS_write_reg_C14[liftState_simp]: + "\<lbrakk>write_reg C14_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C14_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C14[simp]: - "liftS (read_reg C14_ref) = readS (C14 \<circ> regstate)" +lemma liftS_read_reg_C13[liftState_simp]: + "\<lbrakk>read_reg C13_ref\<rbrakk>\<^sub>S = readS (C13 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C14[simp]: - "liftS (write_reg C14_ref v) = updateS (regstate_update (C14_update (\<lambda>_. v)))" +lemma liftS_write_reg_C13[liftState_simp]: + "\<lbrakk>write_reg C13_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C13_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C13[simp]: - "liftS (read_reg C13_ref) = readS (C13 \<circ> regstate)" +lemma liftS_read_reg_C12[liftState_simp]: + "\<lbrakk>read_reg C12_ref\<rbrakk>\<^sub>S = readS (C12 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C13[simp]: - "liftS (write_reg C13_ref v) = updateS (regstate_update (C13_update (\<lambda>_. v)))" +lemma liftS_write_reg_C12[liftState_simp]: + "\<lbrakk>write_reg C12_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C12_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C12[simp]: - "liftS (read_reg C12_ref) = readS (C12 \<circ> regstate)" +lemma liftS_read_reg_C11[liftState_simp]: + "\<lbrakk>read_reg C11_ref\<rbrakk>\<^sub>S = readS (C11 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C12[simp]: - "liftS (write_reg C12_ref v) = updateS (regstate_update (C12_update (\<lambda>_. v)))" +lemma liftS_write_reg_C11[liftState_simp]: + "\<lbrakk>write_reg C11_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C11_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C11[simp]: - "liftS (read_reg C11_ref) = readS (C11 \<circ> regstate)" +lemma liftS_read_reg_C10[liftState_simp]: + "\<lbrakk>read_reg C10_ref\<rbrakk>\<^sub>S = readS (C10 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C11[simp]: - "liftS (write_reg C11_ref v) = updateS (regstate_update (C11_update (\<lambda>_. v)))" +lemma liftS_write_reg_C10[liftState_simp]: + "\<lbrakk>write_reg C10_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C10_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C10[simp]: - "liftS (read_reg C10_ref) = readS (C10 \<circ> regstate)" +lemma liftS_read_reg_C09[liftState_simp]: + "\<lbrakk>read_reg C09_ref\<rbrakk>\<^sub>S = readS (C09 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C10[simp]: - "liftS (write_reg C10_ref v) = updateS (regstate_update (C10_update (\<lambda>_. v)))" +lemma liftS_write_reg_C09[liftState_simp]: + "\<lbrakk>write_reg C09_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C09_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C09[simp]: - "liftS (read_reg C09_ref) = readS (C09 \<circ> regstate)" +lemma liftS_read_reg_C08[liftState_simp]: + "\<lbrakk>read_reg C08_ref\<rbrakk>\<^sub>S = readS (C08 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C09[simp]: - "liftS (write_reg C09_ref v) = updateS (regstate_update (C09_update (\<lambda>_. v)))" +lemma liftS_write_reg_C08[liftState_simp]: + "\<lbrakk>write_reg C08_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C08_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C08[simp]: - "liftS (read_reg C08_ref) = readS (C08 \<circ> regstate)" +lemma liftS_read_reg_C07[liftState_simp]: + "\<lbrakk>read_reg C07_ref\<rbrakk>\<^sub>S = readS (C07 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C08[simp]: - "liftS (write_reg C08_ref v) = updateS (regstate_update (C08_update (\<lambda>_. v)))" +lemma liftS_write_reg_C07[liftState_simp]: + "\<lbrakk>write_reg C07_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C07_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C07[simp]: - "liftS (read_reg C07_ref) = readS (C07 \<circ> regstate)" +lemma liftS_read_reg_C06[liftState_simp]: + "\<lbrakk>read_reg C06_ref\<rbrakk>\<^sub>S = readS (C06 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C07[simp]: - "liftS (write_reg C07_ref v) = updateS (regstate_update (C07_update (\<lambda>_. v)))" +lemma liftS_write_reg_C06[liftState_simp]: + "\<lbrakk>write_reg C06_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C06_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C06[simp]: - "liftS (read_reg C06_ref) = readS (C06 \<circ> regstate)" +lemma liftS_read_reg_C05[liftState_simp]: + "\<lbrakk>read_reg C05_ref\<rbrakk>\<^sub>S = readS (C05 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C06[simp]: - "liftS (write_reg C06_ref v) = updateS (regstate_update (C06_update (\<lambda>_. v)))" +lemma liftS_write_reg_C05[liftState_simp]: + "\<lbrakk>write_reg C05_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C05_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C05[simp]: - "liftS (read_reg C05_ref) = readS (C05 \<circ> regstate)" +lemma liftS_read_reg_C04[liftState_simp]: + "\<lbrakk>read_reg C04_ref\<rbrakk>\<^sub>S = readS (C04 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C05[simp]: - "liftS (write_reg C05_ref v) = updateS (regstate_update (C05_update (\<lambda>_. v)))" +lemma liftS_write_reg_C04[liftState_simp]: + "\<lbrakk>write_reg C04_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C04_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C04[simp]: - "liftS (read_reg C04_ref) = readS (C04 \<circ> regstate)" +lemma liftS_read_reg_C03[liftState_simp]: + "\<lbrakk>read_reg C03_ref\<rbrakk>\<^sub>S = readS (C03 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C04[simp]: - "liftS (write_reg C04_ref v) = updateS (regstate_update (C04_update (\<lambda>_. v)))" +lemma liftS_write_reg_C03[liftState_simp]: + "\<lbrakk>write_reg C03_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C03_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C03[simp]: - "liftS (read_reg C03_ref) = readS (C03 \<circ> regstate)" +lemma liftS_read_reg_C02[liftState_simp]: + "\<lbrakk>read_reg C02_ref\<rbrakk>\<^sub>S = readS (C02 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C03[simp]: - "liftS (write_reg C03_ref v) = updateS (regstate_update (C03_update (\<lambda>_. v)))" +lemma liftS_write_reg_C02[liftState_simp]: + "\<lbrakk>write_reg C02_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C02_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C02[simp]: - "liftS (read_reg C02_ref) = readS (C02 \<circ> regstate)" +lemma liftS_read_reg_C01[liftState_simp]: + "\<lbrakk>read_reg C01_ref\<rbrakk>\<^sub>S = readS (C01 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C02[simp]: - "liftS (write_reg C02_ref v) = updateS (regstate_update (C02_update (\<lambda>_. v)))" +lemma liftS_write_reg_C01[liftState_simp]: + "\<lbrakk>write_reg C01_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (C01_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C01[simp]: - "liftS (read_reg C01_ref) = readS (C01 \<circ> regstate)" +lemma liftS_read_reg_DDC[liftState_simp]: + "\<lbrakk>read_reg DDC_ref\<rbrakk>\<^sub>S = readS (DDC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C01[simp]: - "liftS (write_reg C01_ref v) = updateS (regstate_update (C01_update (\<lambda>_. v)))" +lemma liftS_write_reg_DDC[liftState_simp]: + "\<lbrakk>write_reg DDC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (DDC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C00[simp]: - "liftS (read_reg C00_ref) = readS (C00 \<circ> regstate)" +lemma liftS_read_reg_inCCallDelay[liftState_simp]: + "\<lbrakk>read_reg inCCallDelay_ref\<rbrakk>\<^sub>S = readS (inCCallDelay \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C00[simp]: - "liftS (write_reg C00_ref v) = updateS (regstate_update (C00_update (\<lambda>_. v)))" +lemma liftS_write_reg_inCCallDelay[liftState_simp]: + "\<lbrakk>write_reg inCCallDelay_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (inCCallDelay_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_inCCallDelay[simp]: - "liftS (read_reg inCCallDelay_ref) = readS (inCCallDelay \<circ> regstate)" +lemma liftS_read_reg_nextPCC[liftState_simp]: + "\<lbrakk>read_reg nextPCC_ref\<rbrakk>\<^sub>S = readS (nextPCC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_inCCallDelay[simp]: - "liftS (write_reg inCCallDelay_ref v) = updateS (regstate_update (inCCallDelay_update (\<lambda>_. v)))" +lemma liftS_write_reg_nextPCC[liftState_simp]: + "\<lbrakk>write_reg nextPCC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (nextPCC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_nextPCC[simp]: - "liftS (read_reg nextPCC_ref) = readS (nextPCC \<circ> regstate)" +lemma liftS_read_reg_delayedPCC[liftState_simp]: + "\<lbrakk>read_reg delayedPCC_ref\<rbrakk>\<^sub>S = readS (delayedPCC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_nextPCC[simp]: - "liftS (write_reg nextPCC_ref v) = updateS (regstate_update (nextPCC_update (\<lambda>_. v)))" +lemma liftS_write_reg_delayedPCC[liftState_simp]: + "\<lbrakk>write_reg delayedPCC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (delayedPCC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_delayedPCC[simp]: - "liftS (read_reg delayedPCC_ref) = readS (delayedPCC \<circ> regstate)" +lemma liftS_read_reg_PCC[liftState_simp]: + "\<lbrakk>read_reg PCC_ref\<rbrakk>\<^sub>S = readS (PCC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_delayedPCC[simp]: - "liftS (write_reg delayedPCC_ref v) = updateS (regstate_update (delayedPCC_update (\<lambda>_. v)))" +lemma liftS_write_reg_PCC[liftState_simp]: + "\<lbrakk>write_reg PCC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PCC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_PCC[simp]: - "liftS (read_reg PCC_ref) = readS (PCC \<circ> regstate)" +lemma liftS_read_reg_KCC[liftState_simp]: + "\<lbrakk>read_reg KCC_ref\<rbrakk>\<^sub>S = readS (KCC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_PCC[simp]: - "liftS (write_reg PCC_ref v) = updateS (regstate_update (PCC_update (\<lambda>_. v)))" +lemma liftS_write_reg_KCC[liftState_simp]: + "\<lbrakk>write_reg KCC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (KCC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C31[simp]: - "liftS (read_reg C31_ref) = readS (C31 \<circ> regstate)" +lemma liftS_read_reg_EPCC[liftState_simp]: + "\<lbrakk>read_reg EPCC_ref\<rbrakk>\<^sub>S = readS (EPCC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C31[simp]: - "liftS (write_reg C31_ref v) = updateS (regstate_update (C31_update (\<lambda>_. v)))" +lemma liftS_write_reg_EPCC[liftState_simp]: + "\<lbrakk>write_reg EPCC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (EPCC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_C29[simp]: - "liftS (read_reg C29_ref) = readS (C29 \<circ> regstate)" +lemma liftS_read_reg_UART_RVALID[liftState_simp]: + "\<lbrakk>read_reg UART_RVALID_ref\<rbrakk>\<^sub>S = readS (UART_RVALID \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_C29[simp]: - "liftS (write_reg C29_ref v) = updateS (regstate_update (C29_update (\<lambda>_. v)))" +lemma liftS_write_reg_UART_RVALID[liftState_simp]: + "\<lbrakk>write_reg UART_RVALID_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (UART_RVALID_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_UART_RVALID[simp]: - "liftS (read_reg UART_RVALID_ref) = readS (UART_RVALID \<circ> regstate)" +lemma liftS_read_reg_UART_RDATA[liftState_simp]: + "\<lbrakk>read_reg UART_RDATA_ref\<rbrakk>\<^sub>S = readS (UART_RDATA \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_UART_RVALID[simp]: - "liftS (write_reg UART_RVALID_ref v) = updateS (regstate_update (UART_RVALID_update (\<lambda>_. v)))" +lemma liftS_write_reg_UART_RDATA[liftState_simp]: + "\<lbrakk>write_reg UART_RDATA_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (UART_RDATA_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_UART_RDATA[simp]: - "liftS (read_reg UART_RDATA_ref) = readS (UART_RDATA \<circ> regstate)" +lemma liftS_read_reg_UART_WRITTEN[liftState_simp]: + "\<lbrakk>read_reg UART_WRITTEN_ref\<rbrakk>\<^sub>S = readS (UART_WRITTEN \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_UART_RDATA[simp]: - "liftS (write_reg UART_RDATA_ref v) = updateS (regstate_update (UART_RDATA_update (\<lambda>_. v)))" +lemma liftS_write_reg_UART_WRITTEN[liftState_simp]: + "\<lbrakk>write_reg UART_WRITTEN_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (UART_WRITTEN_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_UART_WRITTEN[simp]: - "liftS (read_reg UART_WRITTEN_ref) = readS (UART_WRITTEN \<circ> regstate)" +lemma liftS_read_reg_UART_WDATA[liftState_simp]: + "\<lbrakk>read_reg UART_WDATA_ref\<rbrakk>\<^sub>S = readS (UART_WDATA \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_UART_WRITTEN[simp]: - "liftS (write_reg UART_WRITTEN_ref v) = updateS (regstate_update (UART_WRITTEN_update (\<lambda>_. v)))" +lemma liftS_write_reg_UART_WDATA[liftState_simp]: + "\<lbrakk>write_reg UART_WDATA_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (UART_WDATA_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_UART_WDATA[simp]: - "liftS (read_reg UART_WDATA_ref) = readS (UART_WDATA \<circ> regstate)" +lemma liftS_read_reg_GPR[liftState_simp]: + "\<lbrakk>read_reg GPR_ref\<rbrakk>\<^sub>S = readS (GPR \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_UART_WDATA[simp]: - "liftS (write_reg UART_WDATA_ref v) = updateS (regstate_update (UART_WDATA_update (\<lambda>_. v)))" +lemma liftS_write_reg_GPR[liftState_simp]: + "\<lbrakk>write_reg GPR_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (GPR_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_GPR[simp]: - "liftS (read_reg GPR_ref) = readS (GPR \<circ> regstate)" +lemma liftS_read_reg_LO[liftState_simp]: + "\<lbrakk>read_reg LO_ref\<rbrakk>\<^sub>S = readS (LO \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_GPR[simp]: - "liftS (write_reg GPR_ref v) = updateS (regstate_update (GPR_update (\<lambda>_. v)))" +lemma liftS_write_reg_LO[liftState_simp]: + "\<lbrakk>write_reg LO_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (LO_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_LO[simp]: - "liftS (read_reg LO_ref) = readS (LO \<circ> regstate)" +lemma liftS_read_reg_HI[liftState_simp]: + "\<lbrakk>read_reg HI_ref\<rbrakk>\<^sub>S = readS (HI \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_LO[simp]: - "liftS (write_reg LO_ref v) = updateS (regstate_update (LO_update (\<lambda>_. v)))" +lemma liftS_write_reg_HI[liftState_simp]: + "\<lbrakk>write_reg HI_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (HI_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_HI[simp]: - "liftS (read_reg HI_ref) = readS (HI \<circ> regstate)" +lemma liftS_read_reg_delayedPC[liftState_simp]: + "\<lbrakk>read_reg delayedPC_ref\<rbrakk>\<^sub>S = readS (delayedPC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_HI[simp]: - "liftS (write_reg HI_ref v) = updateS (regstate_update (HI_update (\<lambda>_. v)))" +lemma liftS_write_reg_delayedPC[liftState_simp]: + "\<lbrakk>write_reg delayedPC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (delayedPC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_delayedPC[simp]: - "liftS (read_reg delayedPC_ref) = readS (delayedPC \<circ> regstate)" +lemma liftS_read_reg_inBranchDelay[liftState_simp]: + "\<lbrakk>read_reg inBranchDelay_ref\<rbrakk>\<^sub>S = readS (inBranchDelay \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_delayedPC[simp]: - "liftS (write_reg delayedPC_ref v) = updateS (regstate_update (delayedPC_update (\<lambda>_. v)))" +lemma liftS_write_reg_inBranchDelay[liftState_simp]: + "\<lbrakk>write_reg inBranchDelay_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (inBranchDelay_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_inBranchDelay[simp]: - "liftS (read_reg inBranchDelay_ref) = readS (inBranchDelay \<circ> regstate)" +lemma liftS_read_reg_branchPending[liftState_simp]: + "\<lbrakk>read_reg branchPending_ref\<rbrakk>\<^sub>S = readS (branchPending \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_inBranchDelay[simp]: - "liftS (write_reg inBranchDelay_ref v) = updateS (regstate_update (inBranchDelay_update (\<lambda>_. v)))" +lemma liftS_write_reg_branchPending[liftState_simp]: + "\<lbrakk>write_reg branchPending_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (branchPending_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_branchPending[simp]: - "liftS (read_reg branchPending_ref) = readS (branchPending \<circ> regstate)" +lemma liftS_read_reg_CP0Status[liftState_simp]: + "\<lbrakk>read_reg CP0Status_ref\<rbrakk>\<^sub>S = readS (CP0Status \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_branchPending[simp]: - "liftS (write_reg branchPending_ref v) = updateS (regstate_update (branchPending_update (\<lambda>_. v)))" +lemma liftS_write_reg_CP0Status[liftState_simp]: + "\<lbrakk>write_reg CP0Status_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0Status_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CP0Status[simp]: - "liftS (read_reg CP0Status_ref) = readS (CP0Status \<circ> regstate)" +lemma liftS_read_reg_CP0ConfigK0[liftState_simp]: + "\<lbrakk>read_reg CP0ConfigK0_ref\<rbrakk>\<^sub>S = readS (CP0ConfigK0 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CP0Status[simp]: - "liftS (write_reg CP0Status_ref v) = updateS (regstate_update (CP0Status_update (\<lambda>_. v)))" +lemma liftS_write_reg_CP0ConfigK0[liftState_simp]: + "\<lbrakk>write_reg CP0ConfigK0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0ConfigK0_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CP0UserLocal[simp]: - "liftS (read_reg CP0UserLocal_ref) = readS (CP0UserLocal \<circ> regstate)" +lemma liftS_read_reg_CP0UserLocal[liftState_simp]: + "\<lbrakk>read_reg CP0UserLocal_ref\<rbrakk>\<^sub>S = readS (CP0UserLocal \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CP0UserLocal[simp]: - "liftS (write_reg CP0UserLocal_ref v) = updateS (regstate_update (CP0UserLocal_update (\<lambda>_. v)))" +lemma liftS_write_reg_CP0UserLocal[liftState_simp]: + "\<lbrakk>write_reg CP0UserLocal_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0UserLocal_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CP0HWREna[simp]: - "liftS (read_reg CP0HWREna_ref) = readS (CP0HWREna \<circ> regstate)" +lemma liftS_read_reg_CP0HWREna[liftState_simp]: + "\<lbrakk>read_reg CP0HWREna_ref\<rbrakk>\<^sub>S = readS (CP0HWREna \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CP0HWREna[simp]: - "liftS (write_reg CP0HWREna_ref v) = updateS (regstate_update (CP0HWREna_update (\<lambda>_. v)))" +lemma liftS_write_reg_CP0HWREna[liftState_simp]: + "\<lbrakk>write_reg CP0HWREna_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0HWREna_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CP0Count[simp]: - "liftS (read_reg CP0Count_ref) = readS (CP0Count \<circ> regstate)" +lemma liftS_read_reg_CP0Count[liftState_simp]: + "\<lbrakk>read_reg CP0Count_ref\<rbrakk>\<^sub>S = readS (CP0Count \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CP0Count[simp]: - "liftS (write_reg CP0Count_ref v) = updateS (regstate_update (CP0Count_update (\<lambda>_. v)))" +lemma liftS_write_reg_CP0Count[liftState_simp]: + "\<lbrakk>write_reg CP0Count_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0Count_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CP0BadVAddr[simp]: - "liftS (read_reg CP0BadVAddr_ref) = readS (CP0BadVAddr \<circ> regstate)" +lemma liftS_read_reg_CP0BadVAddr[liftState_simp]: + "\<lbrakk>read_reg CP0BadVAddr_ref\<rbrakk>\<^sub>S = readS (CP0BadVAddr \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CP0BadVAddr[simp]: - "liftS (write_reg CP0BadVAddr_ref v) = updateS (regstate_update (CP0BadVAddr_update (\<lambda>_. v)))" +lemma liftS_write_reg_CP0BadVAddr[liftState_simp]: + "\<lbrakk>write_reg CP0BadVAddr_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0BadVAddr_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CP0LLAddr[simp]: - "liftS (read_reg CP0LLAddr_ref) = readS (CP0LLAddr \<circ> regstate)" +lemma liftS_read_reg_CP0LLAddr[liftState_simp]: + "\<lbrakk>read_reg CP0LLAddr_ref\<rbrakk>\<^sub>S = readS (CP0LLAddr \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CP0LLAddr[simp]: - "liftS (write_reg CP0LLAddr_ref v) = updateS (regstate_update (CP0LLAddr_update (\<lambda>_. v)))" +lemma liftS_write_reg_CP0LLAddr[liftState_simp]: + "\<lbrakk>write_reg CP0LLAddr_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0LLAddr_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CP0LLBit[simp]: - "liftS (read_reg CP0LLBit_ref) = readS (CP0LLBit \<circ> regstate)" +lemma liftS_read_reg_CP0LLBit[liftState_simp]: + "\<lbrakk>read_reg CP0LLBit_ref\<rbrakk>\<^sub>S = readS (CP0LLBit \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CP0LLBit[simp]: - "liftS (write_reg CP0LLBit_ref v) = updateS (regstate_update (CP0LLBit_update (\<lambda>_. v)))" +lemma liftS_write_reg_CP0LLBit[liftState_simp]: + "\<lbrakk>write_reg CP0LLBit_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0LLBit_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CP0ErrorEPC[simp]: - "liftS (read_reg CP0ErrorEPC_ref) = readS (CP0ErrorEPC \<circ> regstate)" +lemma liftS_read_reg_CP0ErrorEPC[liftState_simp]: + "\<lbrakk>read_reg CP0ErrorEPC_ref\<rbrakk>\<^sub>S = readS (CP0ErrorEPC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CP0ErrorEPC[simp]: - "liftS (write_reg CP0ErrorEPC_ref v) = updateS (regstate_update (CP0ErrorEPC_update (\<lambda>_. v)))" +lemma liftS_write_reg_CP0ErrorEPC[liftState_simp]: + "\<lbrakk>write_reg CP0ErrorEPC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0ErrorEPC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CP0EPC[simp]: - "liftS (read_reg CP0EPC_ref) = readS (CP0EPC \<circ> regstate)" +lemma liftS_read_reg_CP0EPC[liftState_simp]: + "\<lbrakk>read_reg CP0EPC_ref\<rbrakk>\<^sub>S = readS (CP0EPC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CP0EPC[simp]: - "liftS (write_reg CP0EPC_ref v) = updateS (regstate_update (CP0EPC_update (\<lambda>_. v)))" +lemma liftS_write_reg_CP0EPC[liftState_simp]: + "\<lbrakk>write_reg CP0EPC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0EPC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CP0Cause[simp]: - "liftS (read_reg CP0Cause_ref) = readS (CP0Cause \<circ> regstate)" +lemma liftS_read_reg_CP0Cause[liftState_simp]: + "\<lbrakk>read_reg CP0Cause_ref\<rbrakk>\<^sub>S = readS (CP0Cause \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CP0Cause[simp]: - "liftS (write_reg CP0Cause_ref v) = updateS (regstate_update (CP0Cause_update (\<lambda>_. v)))" +lemma liftS_write_reg_CP0Cause[liftState_simp]: + "\<lbrakk>write_reg CP0Cause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0Cause_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_CP0Compare[simp]: - "liftS (read_reg CP0Compare_ref) = readS (CP0Compare \<circ> regstate)" +lemma liftS_read_reg_CP0Compare[liftState_simp]: + "\<lbrakk>read_reg CP0Compare_ref\<rbrakk>\<^sub>S = readS (CP0Compare \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_CP0Compare[simp]: - "liftS (write_reg CP0Compare_ref v) = updateS (regstate_update (CP0Compare_update (\<lambda>_. v)))" +lemma liftS_write_reg_CP0Compare[liftState_simp]: + "\<lbrakk>write_reg CP0Compare_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (CP0Compare_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry63[simp]: - "liftS (read_reg TLBEntry63_ref) = readS (TLBEntry63 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry63[liftState_simp]: + "\<lbrakk>read_reg TLBEntry63_ref\<rbrakk>\<^sub>S = readS (TLBEntry63 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry63[simp]: - "liftS (write_reg TLBEntry63_ref v) = updateS (regstate_update (TLBEntry63_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry63[liftState_simp]: + "\<lbrakk>write_reg TLBEntry63_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry63_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry62[simp]: - "liftS (read_reg TLBEntry62_ref) = readS (TLBEntry62 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry62[liftState_simp]: + "\<lbrakk>read_reg TLBEntry62_ref\<rbrakk>\<^sub>S = readS (TLBEntry62 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry62[simp]: - "liftS (write_reg TLBEntry62_ref v) = updateS (regstate_update (TLBEntry62_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry62[liftState_simp]: + "\<lbrakk>write_reg TLBEntry62_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry62_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry61[simp]: - "liftS (read_reg TLBEntry61_ref) = readS (TLBEntry61 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry61[liftState_simp]: + "\<lbrakk>read_reg TLBEntry61_ref\<rbrakk>\<^sub>S = readS (TLBEntry61 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry61[simp]: - "liftS (write_reg TLBEntry61_ref v) = updateS (regstate_update (TLBEntry61_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry61[liftState_simp]: + "\<lbrakk>write_reg TLBEntry61_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry61_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry60[simp]: - "liftS (read_reg TLBEntry60_ref) = readS (TLBEntry60 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry60[liftState_simp]: + "\<lbrakk>read_reg TLBEntry60_ref\<rbrakk>\<^sub>S = readS (TLBEntry60 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry60[simp]: - "liftS (write_reg TLBEntry60_ref v) = updateS (regstate_update (TLBEntry60_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry60[liftState_simp]: + "\<lbrakk>write_reg TLBEntry60_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry60_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry59[simp]: - "liftS (read_reg TLBEntry59_ref) = readS (TLBEntry59 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry59[liftState_simp]: + "\<lbrakk>read_reg TLBEntry59_ref\<rbrakk>\<^sub>S = readS (TLBEntry59 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry59[simp]: - "liftS (write_reg TLBEntry59_ref v) = updateS (regstate_update (TLBEntry59_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry59[liftState_simp]: + "\<lbrakk>write_reg TLBEntry59_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry59_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry58[simp]: - "liftS (read_reg TLBEntry58_ref) = readS (TLBEntry58 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry58[liftState_simp]: + "\<lbrakk>read_reg TLBEntry58_ref\<rbrakk>\<^sub>S = readS (TLBEntry58 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry58[simp]: - "liftS (write_reg TLBEntry58_ref v) = updateS (regstate_update (TLBEntry58_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry58[liftState_simp]: + "\<lbrakk>write_reg TLBEntry58_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry58_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry57[simp]: - "liftS (read_reg TLBEntry57_ref) = readS (TLBEntry57 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry57[liftState_simp]: + "\<lbrakk>read_reg TLBEntry57_ref\<rbrakk>\<^sub>S = readS (TLBEntry57 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry57[simp]: - "liftS (write_reg TLBEntry57_ref v) = updateS (regstate_update (TLBEntry57_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry57[liftState_simp]: + "\<lbrakk>write_reg TLBEntry57_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry57_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry56[simp]: - "liftS (read_reg TLBEntry56_ref) = readS (TLBEntry56 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry56[liftState_simp]: + "\<lbrakk>read_reg TLBEntry56_ref\<rbrakk>\<^sub>S = readS (TLBEntry56 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry56[simp]: - "liftS (write_reg TLBEntry56_ref v) = updateS (regstate_update (TLBEntry56_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry56[liftState_simp]: + "\<lbrakk>write_reg TLBEntry56_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry56_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry55[simp]: - "liftS (read_reg TLBEntry55_ref) = readS (TLBEntry55 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry55[liftState_simp]: + "\<lbrakk>read_reg TLBEntry55_ref\<rbrakk>\<^sub>S = readS (TLBEntry55 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry55[simp]: - "liftS (write_reg TLBEntry55_ref v) = updateS (regstate_update (TLBEntry55_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry55[liftState_simp]: + "\<lbrakk>write_reg TLBEntry55_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry55_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry54[simp]: - "liftS (read_reg TLBEntry54_ref) = readS (TLBEntry54 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry54[liftState_simp]: + "\<lbrakk>read_reg TLBEntry54_ref\<rbrakk>\<^sub>S = readS (TLBEntry54 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry54[simp]: - "liftS (write_reg TLBEntry54_ref v) = updateS (regstate_update (TLBEntry54_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry54[liftState_simp]: + "\<lbrakk>write_reg TLBEntry54_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry54_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry53[simp]: - "liftS (read_reg TLBEntry53_ref) = readS (TLBEntry53 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry53[liftState_simp]: + "\<lbrakk>read_reg TLBEntry53_ref\<rbrakk>\<^sub>S = readS (TLBEntry53 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry53[simp]: - "liftS (write_reg TLBEntry53_ref v) = updateS (regstate_update (TLBEntry53_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry53[liftState_simp]: + "\<lbrakk>write_reg TLBEntry53_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry53_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry52[simp]: - "liftS (read_reg TLBEntry52_ref) = readS (TLBEntry52 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry52[liftState_simp]: + "\<lbrakk>read_reg TLBEntry52_ref\<rbrakk>\<^sub>S = readS (TLBEntry52 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry52[simp]: - "liftS (write_reg TLBEntry52_ref v) = updateS (regstate_update (TLBEntry52_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry52[liftState_simp]: + "\<lbrakk>write_reg TLBEntry52_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry52_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry51[simp]: - "liftS (read_reg TLBEntry51_ref) = readS (TLBEntry51 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry51[liftState_simp]: + "\<lbrakk>read_reg TLBEntry51_ref\<rbrakk>\<^sub>S = readS (TLBEntry51 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry51[simp]: - "liftS (write_reg TLBEntry51_ref v) = updateS (regstate_update (TLBEntry51_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry51[liftState_simp]: + "\<lbrakk>write_reg TLBEntry51_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry51_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry50[simp]: - "liftS (read_reg TLBEntry50_ref) = readS (TLBEntry50 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry50[liftState_simp]: + "\<lbrakk>read_reg TLBEntry50_ref\<rbrakk>\<^sub>S = readS (TLBEntry50 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry50[simp]: - "liftS (write_reg TLBEntry50_ref v) = updateS (regstate_update (TLBEntry50_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry50[liftState_simp]: + "\<lbrakk>write_reg TLBEntry50_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry50_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry49[simp]: - "liftS (read_reg TLBEntry49_ref) = readS (TLBEntry49 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry49[liftState_simp]: + "\<lbrakk>read_reg TLBEntry49_ref\<rbrakk>\<^sub>S = readS (TLBEntry49 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry49[simp]: - "liftS (write_reg TLBEntry49_ref v) = updateS (regstate_update (TLBEntry49_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry49[liftState_simp]: + "\<lbrakk>write_reg TLBEntry49_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry49_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry48[simp]: - "liftS (read_reg TLBEntry48_ref) = readS (TLBEntry48 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry48[liftState_simp]: + "\<lbrakk>read_reg TLBEntry48_ref\<rbrakk>\<^sub>S = readS (TLBEntry48 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry48[simp]: - "liftS (write_reg TLBEntry48_ref v) = updateS (regstate_update (TLBEntry48_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry48[liftState_simp]: + "\<lbrakk>write_reg TLBEntry48_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry48_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry47[simp]: - "liftS (read_reg TLBEntry47_ref) = readS (TLBEntry47 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry47[liftState_simp]: + "\<lbrakk>read_reg TLBEntry47_ref\<rbrakk>\<^sub>S = readS (TLBEntry47 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry47[simp]: - "liftS (write_reg TLBEntry47_ref v) = updateS (regstate_update (TLBEntry47_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry47[liftState_simp]: + "\<lbrakk>write_reg TLBEntry47_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry47_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry46[simp]: - "liftS (read_reg TLBEntry46_ref) = readS (TLBEntry46 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry46[liftState_simp]: + "\<lbrakk>read_reg TLBEntry46_ref\<rbrakk>\<^sub>S = readS (TLBEntry46 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry46[simp]: - "liftS (write_reg TLBEntry46_ref v) = updateS (regstate_update (TLBEntry46_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry46[liftState_simp]: + "\<lbrakk>write_reg TLBEntry46_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry46_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry45[simp]: - "liftS (read_reg TLBEntry45_ref) = readS (TLBEntry45 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry45[liftState_simp]: + "\<lbrakk>read_reg TLBEntry45_ref\<rbrakk>\<^sub>S = readS (TLBEntry45 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry45[simp]: - "liftS (write_reg TLBEntry45_ref v) = updateS (regstate_update (TLBEntry45_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry45[liftState_simp]: + "\<lbrakk>write_reg TLBEntry45_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry45_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry44[simp]: - "liftS (read_reg TLBEntry44_ref) = readS (TLBEntry44 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry44[liftState_simp]: + "\<lbrakk>read_reg TLBEntry44_ref\<rbrakk>\<^sub>S = readS (TLBEntry44 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry44[simp]: - "liftS (write_reg TLBEntry44_ref v) = updateS (regstate_update (TLBEntry44_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry44[liftState_simp]: + "\<lbrakk>write_reg TLBEntry44_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry44_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry43[simp]: - "liftS (read_reg TLBEntry43_ref) = readS (TLBEntry43 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry43[liftState_simp]: + "\<lbrakk>read_reg TLBEntry43_ref\<rbrakk>\<^sub>S = readS (TLBEntry43 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry43[simp]: - "liftS (write_reg TLBEntry43_ref v) = updateS (regstate_update (TLBEntry43_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry43[liftState_simp]: + "\<lbrakk>write_reg TLBEntry43_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry43_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry42[simp]: - "liftS (read_reg TLBEntry42_ref) = readS (TLBEntry42 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry42[liftState_simp]: + "\<lbrakk>read_reg TLBEntry42_ref\<rbrakk>\<^sub>S = readS (TLBEntry42 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry42[simp]: - "liftS (write_reg TLBEntry42_ref v) = updateS (regstate_update (TLBEntry42_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry42[liftState_simp]: + "\<lbrakk>write_reg TLBEntry42_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry42_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry41[simp]: - "liftS (read_reg TLBEntry41_ref) = readS (TLBEntry41 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry41[liftState_simp]: + "\<lbrakk>read_reg TLBEntry41_ref\<rbrakk>\<^sub>S = readS (TLBEntry41 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry41[simp]: - "liftS (write_reg TLBEntry41_ref v) = updateS (regstate_update (TLBEntry41_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry41[liftState_simp]: + "\<lbrakk>write_reg TLBEntry41_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry41_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry40[simp]: - "liftS (read_reg TLBEntry40_ref) = readS (TLBEntry40 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry40[liftState_simp]: + "\<lbrakk>read_reg TLBEntry40_ref\<rbrakk>\<^sub>S = readS (TLBEntry40 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry40[simp]: - "liftS (write_reg TLBEntry40_ref v) = updateS (regstate_update (TLBEntry40_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry40[liftState_simp]: + "\<lbrakk>write_reg TLBEntry40_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry40_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry39[simp]: - "liftS (read_reg TLBEntry39_ref) = readS (TLBEntry39 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry39[liftState_simp]: + "\<lbrakk>read_reg TLBEntry39_ref\<rbrakk>\<^sub>S = readS (TLBEntry39 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry39[simp]: - "liftS (write_reg TLBEntry39_ref v) = updateS (regstate_update (TLBEntry39_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry39[liftState_simp]: + "\<lbrakk>write_reg TLBEntry39_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry39_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry38[simp]: - "liftS (read_reg TLBEntry38_ref) = readS (TLBEntry38 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry38[liftState_simp]: + "\<lbrakk>read_reg TLBEntry38_ref\<rbrakk>\<^sub>S = readS (TLBEntry38 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry38[simp]: - "liftS (write_reg TLBEntry38_ref v) = updateS (regstate_update (TLBEntry38_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry38[liftState_simp]: + "\<lbrakk>write_reg TLBEntry38_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry38_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry37[simp]: - "liftS (read_reg TLBEntry37_ref) = readS (TLBEntry37 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry37[liftState_simp]: + "\<lbrakk>read_reg TLBEntry37_ref\<rbrakk>\<^sub>S = readS (TLBEntry37 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry37[simp]: - "liftS (write_reg TLBEntry37_ref v) = updateS (regstate_update (TLBEntry37_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry37[liftState_simp]: + "\<lbrakk>write_reg TLBEntry37_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry37_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry36[simp]: - "liftS (read_reg TLBEntry36_ref) = readS (TLBEntry36 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry36[liftState_simp]: + "\<lbrakk>read_reg TLBEntry36_ref\<rbrakk>\<^sub>S = readS (TLBEntry36 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry36[simp]: - "liftS (write_reg TLBEntry36_ref v) = updateS (regstate_update (TLBEntry36_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry36[liftState_simp]: + "\<lbrakk>write_reg TLBEntry36_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry36_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry35[simp]: - "liftS (read_reg TLBEntry35_ref) = readS (TLBEntry35 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry35[liftState_simp]: + "\<lbrakk>read_reg TLBEntry35_ref\<rbrakk>\<^sub>S = readS (TLBEntry35 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry35[simp]: - "liftS (write_reg TLBEntry35_ref v) = updateS (regstate_update (TLBEntry35_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry35[liftState_simp]: + "\<lbrakk>write_reg TLBEntry35_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry35_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry34[simp]: - "liftS (read_reg TLBEntry34_ref) = readS (TLBEntry34 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry34[liftState_simp]: + "\<lbrakk>read_reg TLBEntry34_ref\<rbrakk>\<^sub>S = readS (TLBEntry34 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry34[simp]: - "liftS (write_reg TLBEntry34_ref v) = updateS (regstate_update (TLBEntry34_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry34[liftState_simp]: + "\<lbrakk>write_reg TLBEntry34_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry34_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry33[simp]: - "liftS (read_reg TLBEntry33_ref) = readS (TLBEntry33 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry33[liftState_simp]: + "\<lbrakk>read_reg TLBEntry33_ref\<rbrakk>\<^sub>S = readS (TLBEntry33 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry33[simp]: - "liftS (write_reg TLBEntry33_ref v) = updateS (regstate_update (TLBEntry33_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry33[liftState_simp]: + "\<lbrakk>write_reg TLBEntry33_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry33_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry32[simp]: - "liftS (read_reg TLBEntry32_ref) = readS (TLBEntry32 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry32[liftState_simp]: + "\<lbrakk>read_reg TLBEntry32_ref\<rbrakk>\<^sub>S = readS (TLBEntry32 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry32[simp]: - "liftS (write_reg TLBEntry32_ref v) = updateS (regstate_update (TLBEntry32_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry32[liftState_simp]: + "\<lbrakk>write_reg TLBEntry32_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry32_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry31[simp]: - "liftS (read_reg TLBEntry31_ref) = readS (TLBEntry31 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry31[liftState_simp]: + "\<lbrakk>read_reg TLBEntry31_ref\<rbrakk>\<^sub>S = readS (TLBEntry31 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry31[simp]: - "liftS (write_reg TLBEntry31_ref v) = updateS (regstate_update (TLBEntry31_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry31[liftState_simp]: + "\<lbrakk>write_reg TLBEntry31_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry31_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry30[simp]: - "liftS (read_reg TLBEntry30_ref) = readS (TLBEntry30 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry30[liftState_simp]: + "\<lbrakk>read_reg TLBEntry30_ref\<rbrakk>\<^sub>S = readS (TLBEntry30 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry30[simp]: - "liftS (write_reg TLBEntry30_ref v) = updateS (regstate_update (TLBEntry30_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry30[liftState_simp]: + "\<lbrakk>write_reg TLBEntry30_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry30_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry29[simp]: - "liftS (read_reg TLBEntry29_ref) = readS (TLBEntry29 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry29[liftState_simp]: + "\<lbrakk>read_reg TLBEntry29_ref\<rbrakk>\<^sub>S = readS (TLBEntry29 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry29[simp]: - "liftS (write_reg TLBEntry29_ref v) = updateS (regstate_update (TLBEntry29_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry29[liftState_simp]: + "\<lbrakk>write_reg TLBEntry29_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry29_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry28[simp]: - "liftS (read_reg TLBEntry28_ref) = readS (TLBEntry28 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry28[liftState_simp]: + "\<lbrakk>read_reg TLBEntry28_ref\<rbrakk>\<^sub>S = readS (TLBEntry28 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry28[simp]: - "liftS (write_reg TLBEntry28_ref v) = updateS (regstate_update (TLBEntry28_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry28[liftState_simp]: + "\<lbrakk>write_reg TLBEntry28_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry28_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry27[simp]: - "liftS (read_reg TLBEntry27_ref) = readS (TLBEntry27 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry27[liftState_simp]: + "\<lbrakk>read_reg TLBEntry27_ref\<rbrakk>\<^sub>S = readS (TLBEntry27 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry27[simp]: - "liftS (write_reg TLBEntry27_ref v) = updateS (regstate_update (TLBEntry27_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry27[liftState_simp]: + "\<lbrakk>write_reg TLBEntry27_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry27_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry26[simp]: - "liftS (read_reg TLBEntry26_ref) = readS (TLBEntry26 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry26[liftState_simp]: + "\<lbrakk>read_reg TLBEntry26_ref\<rbrakk>\<^sub>S = readS (TLBEntry26 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry26[simp]: - "liftS (write_reg TLBEntry26_ref v) = updateS (regstate_update (TLBEntry26_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry26[liftState_simp]: + "\<lbrakk>write_reg TLBEntry26_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry26_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry25[simp]: - "liftS (read_reg TLBEntry25_ref) = readS (TLBEntry25 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry25[liftState_simp]: + "\<lbrakk>read_reg TLBEntry25_ref\<rbrakk>\<^sub>S = readS (TLBEntry25 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry25[simp]: - "liftS (write_reg TLBEntry25_ref v) = updateS (regstate_update (TLBEntry25_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry25[liftState_simp]: + "\<lbrakk>write_reg TLBEntry25_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry25_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry24[simp]: - "liftS (read_reg TLBEntry24_ref) = readS (TLBEntry24 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry24[liftState_simp]: + "\<lbrakk>read_reg TLBEntry24_ref\<rbrakk>\<^sub>S = readS (TLBEntry24 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry24[simp]: - "liftS (write_reg TLBEntry24_ref v) = updateS (regstate_update (TLBEntry24_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry24[liftState_simp]: + "\<lbrakk>write_reg TLBEntry24_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry24_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry23[simp]: - "liftS (read_reg TLBEntry23_ref) = readS (TLBEntry23 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry23[liftState_simp]: + "\<lbrakk>read_reg TLBEntry23_ref\<rbrakk>\<^sub>S = readS (TLBEntry23 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry23[simp]: - "liftS (write_reg TLBEntry23_ref v) = updateS (regstate_update (TLBEntry23_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry23[liftState_simp]: + "\<lbrakk>write_reg TLBEntry23_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry23_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry22[simp]: - "liftS (read_reg TLBEntry22_ref) = readS (TLBEntry22 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry22[liftState_simp]: + "\<lbrakk>read_reg TLBEntry22_ref\<rbrakk>\<^sub>S = readS (TLBEntry22 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry22[simp]: - "liftS (write_reg TLBEntry22_ref v) = updateS (regstate_update (TLBEntry22_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry22[liftState_simp]: + "\<lbrakk>write_reg TLBEntry22_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry22_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry21[simp]: - "liftS (read_reg TLBEntry21_ref) = readS (TLBEntry21 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry21[liftState_simp]: + "\<lbrakk>read_reg TLBEntry21_ref\<rbrakk>\<^sub>S = readS (TLBEntry21 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry21[simp]: - "liftS (write_reg TLBEntry21_ref v) = updateS (regstate_update (TLBEntry21_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry21[liftState_simp]: + "\<lbrakk>write_reg TLBEntry21_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry21_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry20[simp]: - "liftS (read_reg TLBEntry20_ref) = readS (TLBEntry20 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry20[liftState_simp]: + "\<lbrakk>read_reg TLBEntry20_ref\<rbrakk>\<^sub>S = readS (TLBEntry20 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry20[simp]: - "liftS (write_reg TLBEntry20_ref v) = updateS (regstate_update (TLBEntry20_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry20[liftState_simp]: + "\<lbrakk>write_reg TLBEntry20_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry20_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry19[simp]: - "liftS (read_reg TLBEntry19_ref) = readS (TLBEntry19 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry19[liftState_simp]: + "\<lbrakk>read_reg TLBEntry19_ref\<rbrakk>\<^sub>S = readS (TLBEntry19 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry19[simp]: - "liftS (write_reg TLBEntry19_ref v) = updateS (regstate_update (TLBEntry19_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry19[liftState_simp]: + "\<lbrakk>write_reg TLBEntry19_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry19_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry18[simp]: - "liftS (read_reg TLBEntry18_ref) = readS (TLBEntry18 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry18[liftState_simp]: + "\<lbrakk>read_reg TLBEntry18_ref\<rbrakk>\<^sub>S = readS (TLBEntry18 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry18[simp]: - "liftS (write_reg TLBEntry18_ref v) = updateS (regstate_update (TLBEntry18_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry18[liftState_simp]: + "\<lbrakk>write_reg TLBEntry18_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry18_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry17[simp]: - "liftS (read_reg TLBEntry17_ref) = readS (TLBEntry17 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry17[liftState_simp]: + "\<lbrakk>read_reg TLBEntry17_ref\<rbrakk>\<^sub>S = readS (TLBEntry17 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry17[simp]: - "liftS (write_reg TLBEntry17_ref v) = updateS (regstate_update (TLBEntry17_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry17[liftState_simp]: + "\<lbrakk>write_reg TLBEntry17_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry17_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry16[simp]: - "liftS (read_reg TLBEntry16_ref) = readS (TLBEntry16 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry16[liftState_simp]: + "\<lbrakk>read_reg TLBEntry16_ref\<rbrakk>\<^sub>S = readS (TLBEntry16 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry16[simp]: - "liftS (write_reg TLBEntry16_ref v) = updateS (regstate_update (TLBEntry16_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry16[liftState_simp]: + "\<lbrakk>write_reg TLBEntry16_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry16_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry15[simp]: - "liftS (read_reg TLBEntry15_ref) = readS (TLBEntry15 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry15[liftState_simp]: + "\<lbrakk>read_reg TLBEntry15_ref\<rbrakk>\<^sub>S = readS (TLBEntry15 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry15[simp]: - "liftS (write_reg TLBEntry15_ref v) = updateS (regstate_update (TLBEntry15_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry15[liftState_simp]: + "\<lbrakk>write_reg TLBEntry15_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry15_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry14[simp]: - "liftS (read_reg TLBEntry14_ref) = readS (TLBEntry14 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry14[liftState_simp]: + "\<lbrakk>read_reg TLBEntry14_ref\<rbrakk>\<^sub>S = readS (TLBEntry14 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry14[simp]: - "liftS (write_reg TLBEntry14_ref v) = updateS (regstate_update (TLBEntry14_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry14[liftState_simp]: + "\<lbrakk>write_reg TLBEntry14_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry14_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry13[simp]: - "liftS (read_reg TLBEntry13_ref) = readS (TLBEntry13 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry13[liftState_simp]: + "\<lbrakk>read_reg TLBEntry13_ref\<rbrakk>\<^sub>S = readS (TLBEntry13 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry13[simp]: - "liftS (write_reg TLBEntry13_ref v) = updateS (regstate_update (TLBEntry13_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry13[liftState_simp]: + "\<lbrakk>write_reg TLBEntry13_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry13_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry12[simp]: - "liftS (read_reg TLBEntry12_ref) = readS (TLBEntry12 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry12[liftState_simp]: + "\<lbrakk>read_reg TLBEntry12_ref\<rbrakk>\<^sub>S = readS (TLBEntry12 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry12[simp]: - "liftS (write_reg TLBEntry12_ref v) = updateS (regstate_update (TLBEntry12_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry12[liftState_simp]: + "\<lbrakk>write_reg TLBEntry12_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry12_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry11[simp]: - "liftS (read_reg TLBEntry11_ref) = readS (TLBEntry11 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry11[liftState_simp]: + "\<lbrakk>read_reg TLBEntry11_ref\<rbrakk>\<^sub>S = readS (TLBEntry11 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry11[simp]: - "liftS (write_reg TLBEntry11_ref v) = updateS (regstate_update (TLBEntry11_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry11[liftState_simp]: + "\<lbrakk>write_reg TLBEntry11_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry11_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry10[simp]: - "liftS (read_reg TLBEntry10_ref) = readS (TLBEntry10 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry10[liftState_simp]: + "\<lbrakk>read_reg TLBEntry10_ref\<rbrakk>\<^sub>S = readS (TLBEntry10 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry10[simp]: - "liftS (write_reg TLBEntry10_ref v) = updateS (regstate_update (TLBEntry10_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry10[liftState_simp]: + "\<lbrakk>write_reg TLBEntry10_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry10_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry09[simp]: - "liftS (read_reg TLBEntry09_ref) = readS (TLBEntry09 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry09[liftState_simp]: + "\<lbrakk>read_reg TLBEntry09_ref\<rbrakk>\<^sub>S = readS (TLBEntry09 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry09[simp]: - "liftS (write_reg TLBEntry09_ref v) = updateS (regstate_update (TLBEntry09_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry09[liftState_simp]: + "\<lbrakk>write_reg TLBEntry09_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry09_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry08[simp]: - "liftS (read_reg TLBEntry08_ref) = readS (TLBEntry08 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry08[liftState_simp]: + "\<lbrakk>read_reg TLBEntry08_ref\<rbrakk>\<^sub>S = readS (TLBEntry08 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry08[simp]: - "liftS (write_reg TLBEntry08_ref v) = updateS (regstate_update (TLBEntry08_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry08[liftState_simp]: + "\<lbrakk>write_reg TLBEntry08_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry08_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry07[simp]: - "liftS (read_reg TLBEntry07_ref) = readS (TLBEntry07 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry07[liftState_simp]: + "\<lbrakk>read_reg TLBEntry07_ref\<rbrakk>\<^sub>S = readS (TLBEntry07 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry07[simp]: - "liftS (write_reg TLBEntry07_ref v) = updateS (regstate_update (TLBEntry07_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry07[liftState_simp]: + "\<lbrakk>write_reg TLBEntry07_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry07_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry06[simp]: - "liftS (read_reg TLBEntry06_ref) = readS (TLBEntry06 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry06[liftState_simp]: + "\<lbrakk>read_reg TLBEntry06_ref\<rbrakk>\<^sub>S = readS (TLBEntry06 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry06[simp]: - "liftS (write_reg TLBEntry06_ref v) = updateS (regstate_update (TLBEntry06_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry06[liftState_simp]: + "\<lbrakk>write_reg TLBEntry06_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry06_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry05[simp]: - "liftS (read_reg TLBEntry05_ref) = readS (TLBEntry05 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry05[liftState_simp]: + "\<lbrakk>read_reg TLBEntry05_ref\<rbrakk>\<^sub>S = readS (TLBEntry05 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry05[simp]: - "liftS (write_reg TLBEntry05_ref v) = updateS (regstate_update (TLBEntry05_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry05[liftState_simp]: + "\<lbrakk>write_reg TLBEntry05_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry05_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry04[simp]: - "liftS (read_reg TLBEntry04_ref) = readS (TLBEntry04 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry04[liftState_simp]: + "\<lbrakk>read_reg TLBEntry04_ref\<rbrakk>\<^sub>S = readS (TLBEntry04 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry04[simp]: - "liftS (write_reg TLBEntry04_ref v) = updateS (regstate_update (TLBEntry04_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry04[liftState_simp]: + "\<lbrakk>write_reg TLBEntry04_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry04_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry03[simp]: - "liftS (read_reg TLBEntry03_ref) = readS (TLBEntry03 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry03[liftState_simp]: + "\<lbrakk>read_reg TLBEntry03_ref\<rbrakk>\<^sub>S = readS (TLBEntry03 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry03[simp]: - "liftS (write_reg TLBEntry03_ref v) = updateS (regstate_update (TLBEntry03_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry03[liftState_simp]: + "\<lbrakk>write_reg TLBEntry03_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry03_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry02[simp]: - "liftS (read_reg TLBEntry02_ref) = readS (TLBEntry02 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry02[liftState_simp]: + "\<lbrakk>read_reg TLBEntry02_ref\<rbrakk>\<^sub>S = readS (TLBEntry02 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry02[simp]: - "liftS (write_reg TLBEntry02_ref v) = updateS (regstate_update (TLBEntry02_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry02[liftState_simp]: + "\<lbrakk>write_reg TLBEntry02_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry02_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry01[simp]: - "liftS (read_reg TLBEntry01_ref) = readS (TLBEntry01 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry01[liftState_simp]: + "\<lbrakk>read_reg TLBEntry01_ref\<rbrakk>\<^sub>S = readS (TLBEntry01 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry01[simp]: - "liftS (write_reg TLBEntry01_ref v) = updateS (regstate_update (TLBEntry01_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry01[liftState_simp]: + "\<lbrakk>write_reg TLBEntry01_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry01_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntry00[simp]: - "liftS (read_reg TLBEntry00_ref) = readS (TLBEntry00 \<circ> regstate)" +lemma liftS_read_reg_TLBEntry00[liftState_simp]: + "\<lbrakk>read_reg TLBEntry00_ref\<rbrakk>\<^sub>S = readS (TLBEntry00 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntry00[simp]: - "liftS (write_reg TLBEntry00_ref v) = updateS (regstate_update (TLBEntry00_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntry00[liftState_simp]: + "\<lbrakk>write_reg TLBEntry00_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntry00_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBXContext[simp]: - "liftS (read_reg TLBXContext_ref) = readS (TLBXContext \<circ> regstate)" +lemma liftS_read_reg_TLBXContext[liftState_simp]: + "\<lbrakk>read_reg TLBXContext_ref\<rbrakk>\<^sub>S = readS (TLBXContext \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBXContext[simp]: - "liftS (write_reg TLBXContext_ref v) = updateS (regstate_update (TLBXContext_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBXContext[liftState_simp]: + "\<lbrakk>write_reg TLBXContext_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBXContext_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntryHi[simp]: - "liftS (read_reg TLBEntryHi_ref) = readS (TLBEntryHi \<circ> regstate)" +lemma liftS_read_reg_TLBEntryHi[liftState_simp]: + "\<lbrakk>read_reg TLBEntryHi_ref\<rbrakk>\<^sub>S = readS (TLBEntryHi \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntryHi[simp]: - "liftS (write_reg TLBEntryHi_ref v) = updateS (regstate_update (TLBEntryHi_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntryHi[liftState_simp]: + "\<lbrakk>write_reg TLBEntryHi_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntryHi_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBWired[simp]: - "liftS (read_reg TLBWired_ref) = readS (TLBWired \<circ> regstate)" +lemma liftS_read_reg_TLBWired[liftState_simp]: + "\<lbrakk>read_reg TLBWired_ref\<rbrakk>\<^sub>S = readS (TLBWired \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBWired[simp]: - "liftS (write_reg TLBWired_ref v) = updateS (regstate_update (TLBWired_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBWired[liftState_simp]: + "\<lbrakk>write_reg TLBWired_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBWired_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBPageMask[simp]: - "liftS (read_reg TLBPageMask_ref) = readS (TLBPageMask \<circ> regstate)" +lemma liftS_read_reg_TLBPageMask[liftState_simp]: + "\<lbrakk>read_reg TLBPageMask_ref\<rbrakk>\<^sub>S = readS (TLBPageMask \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBPageMask[simp]: - "liftS (write_reg TLBPageMask_ref v) = updateS (regstate_update (TLBPageMask_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBPageMask[liftState_simp]: + "\<lbrakk>write_reg TLBPageMask_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBPageMask_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBContext[simp]: - "liftS (read_reg TLBContext_ref) = readS (TLBContext \<circ> regstate)" +lemma liftS_read_reg_TLBContext[liftState_simp]: + "\<lbrakk>read_reg TLBContext_ref\<rbrakk>\<^sub>S = readS (TLBContext \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBContext[simp]: - "liftS (write_reg TLBContext_ref v) = updateS (regstate_update (TLBContext_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBContext[liftState_simp]: + "\<lbrakk>write_reg TLBContext_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBContext_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntryLo1[simp]: - "liftS (read_reg TLBEntryLo1_ref) = readS (TLBEntryLo1 \<circ> regstate)" +lemma liftS_read_reg_TLBEntryLo1[liftState_simp]: + "\<lbrakk>read_reg TLBEntryLo1_ref\<rbrakk>\<^sub>S = readS (TLBEntryLo1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntryLo1[simp]: - "liftS (write_reg TLBEntryLo1_ref v) = updateS (regstate_update (TLBEntryLo1_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntryLo1[liftState_simp]: + "\<lbrakk>write_reg TLBEntryLo1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntryLo1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBEntryLo0[simp]: - "liftS (read_reg TLBEntryLo0_ref) = readS (TLBEntryLo0 \<circ> regstate)" +lemma liftS_read_reg_TLBEntryLo0[liftState_simp]: + "\<lbrakk>read_reg TLBEntryLo0_ref\<rbrakk>\<^sub>S = readS (TLBEntryLo0 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBEntryLo0[simp]: - "liftS (write_reg TLBEntryLo0_ref v) = updateS (regstate_update (TLBEntryLo0_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBEntryLo0[liftState_simp]: + "\<lbrakk>write_reg TLBEntryLo0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBEntryLo0_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBRandom[simp]: - "liftS (read_reg TLBRandom_ref) = readS (TLBRandom \<circ> regstate)" +lemma liftS_read_reg_TLBRandom[liftState_simp]: + "\<lbrakk>read_reg TLBRandom_ref\<rbrakk>\<^sub>S = readS (TLBRandom \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBRandom[simp]: - "liftS (write_reg TLBRandom_ref v) = updateS (regstate_update (TLBRandom_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBRandom[liftState_simp]: + "\<lbrakk>write_reg TLBRandom_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBRandom_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBIndex[simp]: - "liftS (read_reg TLBIndex_ref) = readS (TLBIndex \<circ> regstate)" +lemma liftS_read_reg_TLBIndex[liftState_simp]: + "\<lbrakk>read_reg TLBIndex_ref\<rbrakk>\<^sub>S = readS (TLBIndex \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBIndex[simp]: - "liftS (write_reg TLBIndex_ref v) = updateS (regstate_update (TLBIndex_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBIndex[liftState_simp]: + "\<lbrakk>write_reg TLBIndex_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBIndex_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_TLBProbe[simp]: - "liftS (read_reg TLBProbe_ref) = readS (TLBProbe \<circ> regstate)" +lemma liftS_read_reg_TLBProbe[liftState_simp]: + "\<lbrakk>read_reg TLBProbe_ref\<rbrakk>\<^sub>S = readS (TLBProbe \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_TLBProbe[simp]: - "liftS (write_reg TLBProbe_ref v) = updateS (regstate_update (TLBProbe_update (\<lambda>_. v)))" +lemma liftS_write_reg_TLBProbe[liftState_simp]: + "\<lbrakk>write_reg TLBProbe_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (TLBProbe_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_nextPC[simp]: - "liftS (read_reg nextPC_ref) = readS (nextPC \<circ> regstate)" +lemma liftS_read_reg_nextPC[liftState_simp]: + "\<lbrakk>read_reg nextPC_ref\<rbrakk>\<^sub>S = readS (nextPC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_nextPC[simp]: - "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\<lambda>_. v)))" +lemma liftS_write_reg_nextPC[liftState_simp]: + "\<lbrakk>write_reg nextPC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (nextPC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_PC[simp]: - "liftS (read_reg PC_ref) = readS (PC \<circ> regstate)" +lemma liftS_read_reg_PC[liftState_simp]: + "\<lbrakk>read_reg PC_ref\<rbrakk>\<^sub>S = readS (PC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_PC[simp]: - "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\<lambda>_. v)))" +lemma liftS_write_reg_PC[liftState_simp]: + "\<lbrakk>write_reg PC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) end diff --git a/snapshots/isabelle/cheri/Cheri_types.thy b/snapshots/isabelle/cheri/Cheri_types.thy index 4139164a..3f439184 100644 --- a/snapshots/isabelle/cheri/Cheri_types.thy +++ b/snapshots/isabelle/cheri/Cheri_types.thy @@ -5,23 +5,23 @@ theory "Cheri_types" imports Main "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" - "Sail_operators_mwords" - "Prompt_monad" - "Prompt" - "State" + "Sail2_instr_kinds" + "Sail2_values" + "Sail2_string" + "Sail2_operators_mwords" + "Sail2_prompt_monad" + "Sail2_prompt" begin (*Generated by Sail from cheri.*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) -(*open import State*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) type_synonym 'n bits =" ( 'n::len)Word.word " @@ -35,37 +35,47 @@ datatype exception = -datatype CauseReg = Mk_CauseReg " ( 32 Word.word)" +record CauseReg = + CauseReg_CauseReg_chunk_0 ::" 32 Word.word " -datatype CapCauseReg = Mk_CapCauseReg " ( 16 Word.word)" +record CapCauseReg = + CapCauseReg_CapCauseReg_chunk_0 ::" 16 Word.word " -datatype TLBEntryLoReg = Mk_TLBEntryLoReg " ( 64 Word.word)" +record TLBEntryLoReg = + TLBEntryLoReg_TLBEntryLoReg_chunk_0 ::" 64 Word.word " -datatype TLBEntryHiReg = Mk_TLBEntryHiReg " ( 64 Word.word)" +record TLBEntryHiReg = + TLBEntryHiReg_TLBEntryHiReg_chunk_0 ::" 64 Word.word " -datatype ContextReg = Mk_ContextReg " ( 64 Word.word)" +record ContextReg = + ContextReg_ContextReg_chunk_0 ::" 64 Word.word " -datatype XContextReg = Mk_XContextReg " ( 64 Word.word)" +record XContextReg = + XContextReg_XContextReg_chunk_0 ::" 64 Word.word " type_synonym TLBIndexT =" 6 bits " -datatype TLBEntry = Mk_TLBEntry " ( 117 Word.word)" +record TLBEntry = + + TLBEntry_TLBEntry_chunk_1 ::" 53 Word.word " + TLBEntry_TLBEntry_chunk_0 ::" 64 Word.word " -datatype StatusReg = Mk_StatusReg " ( 32 Word.word)" +record StatusReg = + StatusReg_StatusReg_chunk_0 ::" 32 Word.word " @@ -167,6 +177,10 @@ datatype WordType = B | H | W | D +datatype WordTypeUnaligned = WL | WR | DL | DR + + + type_synonym CapLen =" int " type_synonym uint64 =" int " @@ -244,8 +258,6 @@ datatype (plugins only: size) ast = | JALR " ((regno * regno))" | BEQ " ((regno * regno * imm16 * bool * bool))" | BCMPZ " ((regno * imm16 * Comparison * bool * bool))" - | SYSCALL_THREAD_START " (unit)" - | ImplementationDefinedStopFetching " (unit)" | SYSCALL " (unit)" | BREAK " (unit)" | WAIT " (unit)" @@ -262,7 +274,6 @@ datatype (plugins only: size) ast = | SDL " ((regno * regno * 16 bits))" | SDR " ((regno * regno * 16 bits))" | CACHE " ((regno * regno * 16 bits))" - | PREF " ((regno * regno * 16 bits))" | SYNC " (unit)" | MFC0 " ((regno * regno * 3 bits * bool))" | HCF " (unit)" @@ -317,7 +328,7 @@ datatype (plugins only: size) ast = | CLoad " ((regno * regno * regno * 8 bits * bool * WordType * bool))" | CStore " ((regno * regno * regno * regno * 8 bits * WordType * bool))" | CSC " ((regno * regno * regno * regno * 11 bits * bool))" - | CLC " ((regno * regno * regno * 11 bits * bool))" + | CLC " ((regno * regno * regno * 16 bits * bool))" | C2Dump " (regno)" | RI " (unit)" @@ -367,6 +378,7 @@ datatype register_value = | Regval_vector_1_dec_bit " ( 1 Word.word)" | Regval_vector_257_dec_bit " ( 257 Word.word)" | Regval_vector_32_dec_bit " ( 32 Word.word)" + | Regval_vector_3_dec_bit " ( 3 Word.word)" | Regval_vector_64_dec_bit " ( 64 Word.word)" | Regval_vector_6_dec_bit " ( 6 Word.word)" | Regval_vector_8_dec_bit " ( 8 Word.word)" @@ -379,6 +391,16 @@ record regstate = CapCause ::" CapCauseReg " + EPCC ::" 257 Word.word " + + KDC ::" 257 Word.word " + + KCC ::" 257 Word.word " + + KR2C ::" 257 Word.word " + + KR1C ::" 257 Word.word " + CTLSP ::" 257 Word.word " CTLSU ::" 257 Word.word " @@ -445,7 +467,7 @@ record regstate = C01 ::" 257 Word.word " - C00 ::" 257 Word.word " + DDC ::" 257 Word.word " inCCallDelay ::" 1 Word.word " @@ -477,6 +499,8 @@ record regstate = CP0Status ::" StatusReg " + CP0ConfigK0 ::" 3 Word.word " + CP0UserLocal ::" 64 Word.word " CP0HWREna ::" 32 Word.word " @@ -657,7 +681,7 @@ record regstate = fun CapCauseReg_of_regval :: " register_value \<Rightarrow>(CapCauseReg)option " where " CapCauseReg_of_regval (Regval_CapCauseReg (v)) = ( Some v )" -|" CapCauseReg_of_regval g__114 = ( None )" +|" CapCauseReg_of_regval g__16 = ( None )" (*val regval_of_CapCauseReg : CapCauseReg -> register_value*) @@ -670,7 +694,7 @@ definition regval_of_CapCauseReg :: " CapCauseReg \<Rightarrow> register_value fun CauseReg_of_regval :: " register_value \<Rightarrow>(CauseReg)option " where " CauseReg_of_regval (Regval_CauseReg (v)) = ( Some v )" -|" CauseReg_of_regval g__113 = ( None )" +|" CauseReg_of_regval g__15 = ( None )" (*val regval_of_CauseReg : CauseReg -> register_value*) @@ -683,7 +707,7 @@ definition regval_of_CauseReg :: " CauseReg \<Rightarrow> register_value " whe fun ContextReg_of_regval :: " register_value \<Rightarrow>(ContextReg)option " where " ContextReg_of_regval (Regval_ContextReg (v)) = ( Some v )" -|" ContextReg_of_regval g__112 = ( None )" +|" ContextReg_of_regval g__14 = ( None )" (*val regval_of_ContextReg : ContextReg -> register_value*) @@ -696,7 +720,7 @@ definition regval_of_ContextReg :: " ContextReg \<Rightarrow> register_value " fun StatusReg_of_regval :: " register_value \<Rightarrow>(StatusReg)option " where " StatusReg_of_regval (Regval_StatusReg (v)) = ( Some v )" -|" StatusReg_of_regval g__111 = ( None )" +|" StatusReg_of_regval g__13 = ( None )" (*val regval_of_StatusReg : StatusReg -> register_value*) @@ -709,7 +733,7 @@ definition regval_of_StatusReg :: " StatusReg \<Rightarrow> register_value " w fun TLBEntry_of_regval :: " register_value \<Rightarrow>(TLBEntry)option " where " TLBEntry_of_regval (Regval_TLBEntry (v)) = ( Some v )" -|" TLBEntry_of_regval g__110 = ( None )" +|" TLBEntry_of_regval g__12 = ( None )" (*val regval_of_TLBEntry : TLBEntry -> register_value*) @@ -722,7 +746,7 @@ definition regval_of_TLBEntry :: " TLBEntry \<Rightarrow> register_value " whe fun TLBEntryHiReg_of_regval :: " register_value \<Rightarrow>(TLBEntryHiReg)option " where " TLBEntryHiReg_of_regval (Regval_TLBEntryHiReg (v)) = ( Some v )" -|" TLBEntryHiReg_of_regval g__109 = ( None )" +|" TLBEntryHiReg_of_regval g__11 = ( None )" (*val regval_of_TLBEntryHiReg : TLBEntryHiReg -> register_value*) @@ -735,7 +759,7 @@ definition regval_of_TLBEntryHiReg :: " TLBEntryHiReg \<Rightarrow> register_va fun TLBEntryLoReg_of_regval :: " register_value \<Rightarrow>(TLBEntryLoReg)option " where " TLBEntryLoReg_of_regval (Regval_TLBEntryLoReg (v)) = ( Some v )" -|" TLBEntryLoReg_of_regval g__108 = ( None )" +|" TLBEntryLoReg_of_regval g__10 = ( None )" (*val regval_of_TLBEntryLoReg : TLBEntryLoReg -> register_value*) @@ -748,7 +772,7 @@ definition regval_of_TLBEntryLoReg :: " TLBEntryLoReg \<Rightarrow> register_va fun XContextReg_of_regval :: " register_value \<Rightarrow>(XContextReg)option " where " XContextReg_of_regval (Regval_XContextReg (v)) = ( Some v )" -|" XContextReg_of_regval g__107 = ( None )" +|" XContextReg_of_regval g__9 = ( None )" (*val regval_of_XContextReg : XContextReg -> register_value*) @@ -761,7 +785,7 @@ definition regval_of_XContextReg :: " XContextReg \<Rightarrow> register_value fun int_of_regval :: " register_value \<Rightarrow>(int)option " where " int_of_regval (Regval_int (v)) = ( Some v )" -|" int_of_regval g__106 = ( None )" +|" int_of_regval g__8 = ( None )" (*val regval_of_int : ii -> register_value*) @@ -774,7 +798,7 @@ definition regval_of_int :: " int \<Rightarrow> register_value " where fun vector_16_dec_bit_of_regval :: " register_value \<Rightarrow>((16)Word.word)option " where " vector_16_dec_bit_of_regval (Regval_vector_16_dec_bit (v)) = ( Some v )" -|" vector_16_dec_bit_of_regval g__105 = ( None )" +|" vector_16_dec_bit_of_regval g__7 = ( None )" (*val regval_of_vector_16_dec_bit : mword ty16 -> register_value*) @@ -787,7 +811,7 @@ definition regval_of_vector_16_dec_bit :: "(16)Word.word \<Rightarrow> register fun vector_1_dec_bit_of_regval :: " register_value \<Rightarrow>((1)Word.word)option " where " vector_1_dec_bit_of_regval (Regval_vector_1_dec_bit (v)) = ( Some v )" -|" vector_1_dec_bit_of_regval g__104 = ( None )" +|" vector_1_dec_bit_of_regval g__6 = ( None )" (*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*) @@ -800,7 +824,7 @@ definition regval_of_vector_1_dec_bit :: "(1)Word.word \<Rightarrow> register_v fun vector_257_dec_bit_of_regval :: " register_value \<Rightarrow>((257)Word.word)option " where " vector_257_dec_bit_of_regval (Regval_vector_257_dec_bit (v)) = ( Some v )" -|" vector_257_dec_bit_of_regval g__103 = ( None )" +|" vector_257_dec_bit_of_regval g__5 = ( None )" (*val regval_of_vector_257_dec_bit : mword ty257 -> register_value*) @@ -813,7 +837,7 @@ definition regval_of_vector_257_dec_bit :: "(257)Word.word \<Rightarrow> regist fun vector_32_dec_bit_of_regval :: " register_value \<Rightarrow>((32)Word.word)option " where " vector_32_dec_bit_of_regval (Regval_vector_32_dec_bit (v)) = ( Some v )" -|" vector_32_dec_bit_of_regval g__102 = ( None )" +|" vector_32_dec_bit_of_regval g__4 = ( None )" (*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*) @@ -822,11 +846,24 @@ definition regval_of_vector_32_dec_bit :: "(32)Word.word \<Rightarrow> register " regval_of_vector_32_dec_bit v = ( Regval_vector_32_dec_bit v )" +(*val vector_3_dec_bit_of_regval : register_value -> maybe (mword ty3)*) + +fun vector_3_dec_bit_of_regval :: " register_value \<Rightarrow>((3)Word.word)option " where + " vector_3_dec_bit_of_regval (Regval_vector_3_dec_bit (v)) = ( Some v )" +|" vector_3_dec_bit_of_regval g__3 = ( None )" + + +(*val regval_of_vector_3_dec_bit : mword ty3 -> register_value*) + +definition regval_of_vector_3_dec_bit :: "(3)Word.word \<Rightarrow> register_value " where + " regval_of_vector_3_dec_bit v = ( Regval_vector_3_dec_bit v )" + + (*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) fun vector_64_dec_bit_of_regval :: " register_value \<Rightarrow>((64)Word.word)option " where " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )" -|" vector_64_dec_bit_of_regval g__101 = ( None )" +|" vector_64_dec_bit_of_regval g__2 = ( None )" (*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) @@ -839,7 +876,7 @@ definition regval_of_vector_64_dec_bit :: "(64)Word.word \<Rightarrow> register fun vector_6_dec_bit_of_regval :: " register_value \<Rightarrow>((6)Word.word)option " where " vector_6_dec_bit_of_regval (Regval_vector_6_dec_bit (v)) = ( Some v )" -|" vector_6_dec_bit_of_regval g__100 = ( None )" +|" vector_6_dec_bit_of_regval g__1 = ( None )" (*val regval_of_vector_6_dec_bit : mword ty6 -> register_value*) @@ -852,7 +889,7 @@ definition regval_of_vector_6_dec_bit :: "(6)Word.word \<Rightarrow> register_v fun vector_8_dec_bit_of_regval :: " register_value \<Rightarrow>((8)Word.word)option " where " vector_8_dec_bit_of_regval (Regval_vector_8_dec_bit (v)) = ( Some v )" -|" vector_8_dec_bit_of_regval g__99 = ( None )" +|" vector_8_dec_bit_of_regval g__0 = ( None )" (*val regval_of_vector_8_dec_bit : mword ty8 -> register_value*) @@ -894,7 +931,10 @@ definition regval_of_list :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a (*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) definition option_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a option)option " where " option_of_regval of_regval1 = ( \<lambda>x . - (case x of Regval_option v => map_option of_regval1 v | _ => None ) )" + (case x of + Regval_option v => Some (Option.bind v of_regval1) + | _ => None + ) )" (*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) @@ -921,6 +961,33 @@ definition CapCause_ref :: "((regstate),(register_value),(CapCauseReg))register regval_of = (\<lambda> v . regval_of_CapCauseReg v) |) )" +definition KDC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " KDC_ref = ( (| + name = (''KDC''), + read_from = (\<lambda> s . (KDC s)), + write_to = (\<lambda> v s . (( s (| KDC := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition KR2C_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " KR2C_ref = ( (| + name = (''KR2C''), + read_from = (\<lambda> s . (KR2C s)), + write_to = (\<lambda> v s . (( s (| KR2C := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition KR1C_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " KR1C_ref = ( (| + name = (''KR1C''), + read_from = (\<lambda> s . (KR1C s)), + write_to = (\<lambda> v s . (( s (| KR1C := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + definition CTLSP_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where " CTLSP_ref = ( (| name = (''CTLSP''), @@ -939,6 +1006,15 @@ definition CTLSU_ref :: "((regstate),(register_value),((257)Word.word))register regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" +definition C31_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C31_ref = ( (| + name = (''C31''), + read_from = (\<lambda> s . (C31 s)), + write_to = (\<lambda> v s . (( s (| C31 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + definition C30_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where " C30_ref = ( (| name = (''C30''), @@ -948,6 +1024,15 @@ definition C30_ref :: "((regstate),(register_value),((257)Word.word))register_r regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" +definition C29_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C29_ref = ( (| + name = (''C29''), + read_from = (\<lambda> s . (C29 s)), + write_to = (\<lambda> v s . (( s (| C29 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + definition C28_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where " C28_ref = ( (| name = (''C28''), @@ -1200,11 +1285,11 @@ definition C01_ref :: "((regstate),(register_value),((257)Word.word))register_r regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" -definition C00_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where - " C00_ref = ( (| - name = (''C00''), - read_from = (\<lambda> s . (C00 s)), - write_to = (\<lambda> v s . (( s (| C00 := v |)))), +definition DDC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " DDC_ref = ( (| + name = (''DDC''), + read_from = (\<lambda> s . (DDC s)), + write_to = (\<lambda> v s . (( s (| DDC := v |)))), of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" @@ -1245,20 +1330,20 @@ definition PCC_ref :: "((regstate),(register_value),((257)Word.word))register_r regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" -definition C31_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where - " C31_ref = ( (| - name = (''C31''), - read_from = (\<lambda> s . (C31 s)), - write_to = (\<lambda> v s . (( s (| C31 := v |)))), +definition KCC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " KCC_ref = ( (| + name = (''KCC''), + read_from = (\<lambda> s . (KCC s)), + write_to = (\<lambda> v s . (( s (| KCC := v |)))), of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" -definition C29_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where - " C29_ref = ( (| - name = (''C29''), - read_from = (\<lambda> s . (C29 s)), - write_to = (\<lambda> v s . (( s (| C29 := v |)))), +definition EPCC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " EPCC_ref = ( (| + name = (''EPCC''), + read_from = (\<lambda> s . (EPCC s)), + write_to = (\<lambda> v s . (( s (| EPCC := v |)))), of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" @@ -1362,6 +1447,15 @@ definition CP0Status_ref :: "((regstate),(register_value),(StatusReg))register_ regval_of = (\<lambda> v . regval_of_StatusReg v) |) )" +definition CP0ConfigK0_ref :: "((regstate),(register_value),((3)Word.word))register_ref " where + " CP0ConfigK0_ref = ( (| + name = (''CP0ConfigK0''), + read_from = (\<lambda> s . (CP0ConfigK0 s)), + write_to = (\<lambda> v s . (( s (| CP0ConfigK0 := v |)))), + of_regval = (\<lambda> v . vector_3_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_3_dec_bit v) |) )" + + definition CP0UserLocal_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where " CP0UserLocal_ref = ( (| name = (''CP0UserLocal''), @@ -2141,9 +2235,14 @@ definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register " get_regval reg_name s = ( if reg_name = (''instCount'') then Some ((regval_of instCount_ref) ((read_from instCount_ref) s)) else if reg_name = (''CapCause'') then Some ((regval_of CapCause_ref) ((read_from CapCause_ref) s)) else + if reg_name = (''KDC'') then Some ((regval_of KDC_ref) ((read_from KDC_ref) s)) else + if reg_name = (''KR2C'') then Some ((regval_of KR2C_ref) ((read_from KR2C_ref) s)) else + if reg_name = (''KR1C'') then Some ((regval_of KR1C_ref) ((read_from KR1C_ref) s)) else if reg_name = (''CTLSP'') then Some ((regval_of CTLSP_ref) ((read_from CTLSP_ref) s)) else if reg_name = (''CTLSU'') then Some ((regval_of CTLSU_ref) ((read_from CTLSU_ref) s)) else + if reg_name = (''C31'') then Some ((regval_of C31_ref) ((read_from C31_ref) s)) else if reg_name = (''C30'') then Some ((regval_of C30_ref) ((read_from C30_ref) s)) else + if reg_name = (''C29'') then Some ((regval_of C29_ref) ((read_from C29_ref) s)) else if reg_name = (''C28'') then Some ((regval_of C28_ref) ((read_from C28_ref) s)) else if reg_name = (''C27'') then Some ((regval_of C27_ref) ((read_from C27_ref) s)) else if reg_name = (''C26'') then Some ((regval_of C26_ref) ((read_from C26_ref) s)) else @@ -2172,13 +2271,13 @@ definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register if reg_name = (''C03'') then Some ((regval_of C03_ref) ((read_from C03_ref) s)) else if reg_name = (''C02'') then Some ((regval_of C02_ref) ((read_from C02_ref) s)) else if reg_name = (''C01'') then Some ((regval_of C01_ref) ((read_from C01_ref) s)) else - if reg_name = (''C00'') then Some ((regval_of C00_ref) ((read_from C00_ref) s)) else + if reg_name = (''DDC'') then Some ((regval_of DDC_ref) ((read_from DDC_ref) s)) else if reg_name = (''inCCallDelay'') then Some ((regval_of inCCallDelay_ref) ((read_from inCCallDelay_ref) s)) else if reg_name = (''nextPCC'') then Some ((regval_of nextPCC_ref) ((read_from nextPCC_ref) s)) else if reg_name = (''delayedPCC'') then Some ((regval_of delayedPCC_ref) ((read_from delayedPCC_ref) s)) else if reg_name = (''PCC'') then Some ((regval_of PCC_ref) ((read_from PCC_ref) s)) else - if reg_name = (''C31'') then Some ((regval_of C31_ref) ((read_from C31_ref) s)) else - if reg_name = (''C29'') then Some ((regval_of C29_ref) ((read_from C29_ref) s)) else + if reg_name = (''KCC'') then Some ((regval_of KCC_ref) ((read_from KCC_ref) s)) else + if reg_name = (''EPCC'') then Some ((regval_of EPCC_ref) ((read_from EPCC_ref) s)) else if reg_name = (''UART_RVALID'') then Some ((regval_of UART_RVALID_ref) ((read_from UART_RVALID_ref) s)) else if reg_name = (''UART_RDATA'') then Some ((regval_of UART_RDATA_ref) ((read_from UART_RDATA_ref) s)) else if reg_name = (''UART_WRITTEN'') then Some ((regval_of UART_WRITTEN_ref) ((read_from UART_WRITTEN_ref) s)) else @@ -2190,6 +2289,7 @@ definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register if reg_name = (''inBranchDelay'') then Some ((regval_of inBranchDelay_ref) ((read_from inBranchDelay_ref) s)) else if reg_name = (''branchPending'') then Some ((regval_of branchPending_ref) ((read_from branchPending_ref) s)) else if reg_name = (''CP0Status'') then Some ((regval_of CP0Status_ref) ((read_from CP0Status_ref) s)) else + if reg_name = (''CP0ConfigK0'') then Some ((regval_of CP0ConfigK0_ref) ((read_from CP0ConfigK0_ref) s)) else if reg_name = (''CP0UserLocal'') then Some ((regval_of CP0UserLocal_ref) ((read_from CP0UserLocal_ref) s)) else if reg_name = (''CP0HWREna'') then Some ((regval_of CP0HWREna_ref) ((read_from CP0HWREna_ref) s)) else if reg_name = (''CP0Count'') then Some ((regval_of CP0Count_ref) ((read_from CP0Count_ref) s)) else @@ -2284,9 +2384,14 @@ definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> re " set_regval reg_name v s = ( if reg_name = (''instCount'') then map_option (\<lambda> v . (write_to instCount_ref) v s) ((of_regval instCount_ref) v) else if reg_name = (''CapCause'') then map_option (\<lambda> v . (write_to CapCause_ref) v s) ((of_regval CapCause_ref) v) else + if reg_name = (''KDC'') then map_option (\<lambda> v . (write_to KDC_ref) v s) ((of_regval KDC_ref) v) else + if reg_name = (''KR2C'') then map_option (\<lambda> v . (write_to KR2C_ref) v s) ((of_regval KR2C_ref) v) else + if reg_name = (''KR1C'') then map_option (\<lambda> v . (write_to KR1C_ref) v s) ((of_regval KR1C_ref) v) else if reg_name = (''CTLSP'') then map_option (\<lambda> v . (write_to CTLSP_ref) v s) ((of_regval CTLSP_ref) v) else if reg_name = (''CTLSU'') then map_option (\<lambda> v . (write_to CTLSU_ref) v s) ((of_regval CTLSU_ref) v) else + if reg_name = (''C31'') then map_option (\<lambda> v . (write_to C31_ref) v s) ((of_regval C31_ref) v) else if reg_name = (''C30'') then map_option (\<lambda> v . (write_to C30_ref) v s) ((of_regval C30_ref) v) else + if reg_name = (''C29'') then map_option (\<lambda> v . (write_to C29_ref) v s) ((of_regval C29_ref) v) else if reg_name = (''C28'') then map_option (\<lambda> v . (write_to C28_ref) v s) ((of_regval C28_ref) v) else if reg_name = (''C27'') then map_option (\<lambda> v . (write_to C27_ref) v s) ((of_regval C27_ref) v) else if reg_name = (''C26'') then map_option (\<lambda> v . (write_to C26_ref) v s) ((of_regval C26_ref) v) else @@ -2315,13 +2420,13 @@ definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> re if reg_name = (''C03'') then map_option (\<lambda> v . (write_to C03_ref) v s) ((of_regval C03_ref) v) else if reg_name = (''C02'') then map_option (\<lambda> v . (write_to C02_ref) v s) ((of_regval C02_ref) v) else if reg_name = (''C01'') then map_option (\<lambda> v . (write_to C01_ref) v s) ((of_regval C01_ref) v) else - if reg_name = (''C00'') then map_option (\<lambda> v . (write_to C00_ref) v s) ((of_regval C00_ref) v) else + if reg_name = (''DDC'') then map_option (\<lambda> v . (write_to DDC_ref) v s) ((of_regval DDC_ref) v) else if reg_name = (''inCCallDelay'') then map_option (\<lambda> v . (write_to inCCallDelay_ref) v s) ((of_regval inCCallDelay_ref) v) else if reg_name = (''nextPCC'') then map_option (\<lambda> v . (write_to nextPCC_ref) v s) ((of_regval nextPCC_ref) v) else if reg_name = (''delayedPCC'') then map_option (\<lambda> v . (write_to delayedPCC_ref) v s) ((of_regval delayedPCC_ref) v) else if reg_name = (''PCC'') then map_option (\<lambda> v . (write_to PCC_ref) v s) ((of_regval PCC_ref) v) else - if reg_name = (''C31'') then map_option (\<lambda> v . (write_to C31_ref) v s) ((of_regval C31_ref) v) else - if reg_name = (''C29'') then map_option (\<lambda> v . (write_to C29_ref) v s) ((of_regval C29_ref) v) else + if reg_name = (''KCC'') then map_option (\<lambda> v . (write_to KCC_ref) v s) ((of_regval KCC_ref) v) else + if reg_name = (''EPCC'') then map_option (\<lambda> v . (write_to EPCC_ref) v s) ((of_regval EPCC_ref) v) else if reg_name = (''UART_RVALID'') then map_option (\<lambda> v . (write_to UART_RVALID_ref) v s) ((of_regval UART_RVALID_ref) v) else if reg_name = (''UART_RDATA'') then map_option (\<lambda> v . (write_to UART_RDATA_ref) v s) ((of_regval UART_RDATA_ref) v) else if reg_name = (''UART_WRITTEN'') then map_option (\<lambda> v . (write_to UART_WRITTEN_ref) v s) ((of_regval UART_WRITTEN_ref) v) else @@ -2333,6 +2438,7 @@ definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> re if reg_name = (''inBranchDelay'') then map_option (\<lambda> v . (write_to inBranchDelay_ref) v s) ((of_regval inBranchDelay_ref) v) else if reg_name = (''branchPending'') then map_option (\<lambda> v . (write_to branchPending_ref) v s) ((of_regval branchPending_ref) v) else if reg_name = (''CP0Status'') then map_option (\<lambda> v . (write_to CP0Status_ref) v s) ((of_regval CP0Status_ref) v) else + if reg_name = (''CP0ConfigK0'') then map_option (\<lambda> v . (write_to CP0ConfigK0_ref) v s) ((of_regval CP0ConfigK0_ref) v) else if reg_name = (''CP0UserLocal'') then map_option (\<lambda> v . (write_to CP0UserLocal_ref) v s) ((of_regval CP0UserLocal_ref) v) else if reg_name = (''CP0HWREna'') then map_option (\<lambda> v . (write_to CP0HWREna_ref) v s) ((of_regval CP0HWREna_ref) v) else if reg_name = (''CP0Count'') then map_option (\<lambda> v . (write_to CP0Count_ref) v s) ((of_regval CP0Count_ref) v) else @@ -2427,6 +2533,6 @@ definition register_accessors :: "(string \<Rightarrow> regstate \<Rightarrow>( -type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, exception) monadR " -type_synonym 'a M =" (register_value, 'a, exception) monad " +type_synonym( 'a, 'r) MR =" (register_value, regstate, 'a, 'r, exception) base_monadR " +type_synonym 'a M =" (register_value, regstate, 'a, exception) base_monad " end diff --git a/snapshots/isabelle/cheri/Mips_extras.thy b/snapshots/isabelle/cheri/Mips_extras.thy index c0379d3a..387b5ea7 100644 --- a/snapshots/isabelle/cheri/Mips_extras.thy +++ b/snapshots/isabelle/cheri/Mips_extras.thy @@ -1,4 +1,4 @@ -chapter \<open>Generated by Lem from /auto/homes/tb592/REMS/rems/sail/mips/mips_extras.lem.\<close> +chapter \<open>Generated by Lem from /tmp/sail/mips/mips_extras.lem.\<close> theory "Mips_extras" @@ -6,21 +6,21 @@ imports Main "Lem_pervasives" "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" - "Prompt_monad" - "Prompt" - "Sail_operators" + "Sail2_instr_kinds" + "Sail2_values" + "Sail2_prompt_monad" + "Sail2_prompt" + "Sail2_operators" begin (*open import Pervasives*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators*) -(*open import Prompt_monad*) -(*open import Prompt*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_operators*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) (*val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) (*val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) @@ -28,39 +28,39 @@ begin (*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*) definition MEMr :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,'b,'e)monad " where - " MEMr dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( read_mem - dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 )" + " MEMr dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 = ( read_mem + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1 )" definition MEMr_reserve :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,'b,'e)monad " where - " MEMr_reserve dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( read_mem - dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_reserve addr size1 )" + " MEMr_reserve dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 = ( read_mem + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_reserve addr size1 )" (*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*) definition read_tag_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('regval,(bool),'e)monad " where - " read_tag_bool dict_Sail_values_Bitvector_a addr = ( - read_tag dict_Sail_values_Bitvector_a addr \<bind> (\<lambda> t . + " read_tag_bool dict_Sail2_values_Bitvector_a addr = ( + read_tag dict_Sail2_values_Bitvector_a addr \<bind> (\<lambda> t . maybe_fail (''read_tag_bool'') (bool_of_bitU t)))" (*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*) definition write_tag_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow>('regval,(unit),'e)monad " where - " write_tag_bool dict_Sail_values_Bitvector_a addr t = ( write_tag - dict_Sail_values_Bitvector_a addr (bitU_of_bool t) \<bind> + " write_tag_bool dict_Sail2_values_Bitvector_a addr t = ( write_tag + dict_Sail2_values_Bitvector_a addr (bitU_of_bool t) \<bind> (\<lambda>x . (case x of _ => return () )) )" definition MEMr_tag :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(bool*'b),'e)monad " where - " MEMr_tag dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( - read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 \<bind> (\<lambda> v . - read_tag_bool dict_Sail_values_Bitvector_a addr \<bind> (\<lambda> t . + " MEMr_tag dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 = ( + read_mem dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1 \<bind> (\<lambda> v . + read_tag_bool dict_Sail2_values_Bitvector_a addr \<bind> (\<lambda> t . return (t, v))))" definition MEMr_tag_reserve :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(bool*'b),'e)monad " where - " MEMr_tag_reserve dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( - read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 \<bind> (\<lambda> v . - read_tag_bool dict_Sail_values_Bitvector_a addr \<bind> (\<lambda> t . + " MEMr_tag_reserve dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 = ( + read_mem dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b Read_plain addr size1 \<bind> (\<lambda> v . + read_tag_bool dict_Sail2_values_Bitvector_a addr \<bind> (\<lambda> t . return (t, v))))" @@ -71,21 +71,21 @@ definition MEMr_tag_reserve :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_ (*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) definition MEMea :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad " where - " MEMea dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea - dict_Sail_values_Bitvector_a Write_plain addr size1 )" + " MEMea dict_Sail2_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail2_values_Bitvector_a Write_plain addr size1 )" definition MEMea_conditional :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad " where - " MEMea_conditional dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea - dict_Sail_values_Bitvector_a Write_conditional addr size1 )" + " MEMea_conditional dict_Sail2_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail2_values_Bitvector_a Write_conditional addr size1 )" definition MEMea_tag :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad " where - " MEMea_tag dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea - dict_Sail_values_Bitvector_a Write_plain addr size1 )" + " MEMea_tag dict_Sail2_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail2_values_Bitvector_a Write_plain addr size1 )" definition MEMea_tag_conditional :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad " where - " MEMea_tag_conditional dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea - dict_Sail_values_Bitvector_a Write_conditional addr size1 )" + " MEMea_tag_conditional dict_Sail2_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail2_values_Bitvector_a Write_conditional addr size1 )" @@ -95,25 +95,25 @@ definition MEMea_tag_conditional :: " 'a Bitvector_class \<Rightarrow> 'a \<Rig (*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e*) definition MEMval :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b \<Rightarrow>('regval,(unit),'e)monad " where - " MEMval dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v = ( write_mem_val - dict_Sail_values_Bitvector_b v \<bind> (\<lambda>x . (case x of _ => return () )) )" + " MEMval dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 v = ( write_mem_val + dict_Sail2_values_Bitvector_b v \<bind> (\<lambda>x . (case x of _ => return () )) )" definition MEMval_conditional :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b \<Rightarrow>('regval,(bool),'e)monad " where - " MEMval_conditional dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v = ( write_mem_val - dict_Sail_values_Bitvector_b v \<bind> (\<lambda> b . return (if b then True else False)))" + " MEMval_conditional dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 v = ( write_mem_val + dict_Sail2_values_Bitvector_b v \<bind> (\<lambda> b . return (if b then True else False)))" definition MEMval_tag :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'b \<Rightarrow>('regval,(unit),'e)monad " where - " MEMval_tag dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v = ( write_mem_val - dict_Sail_values_Bitvector_b v \<bind> (\<lambda>x . (case x of - _ => write_tag_bool dict_Sail_values_Bitvector_a addr t + " MEMval_tag dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 t v = ( write_mem_val + dict_Sail2_values_Bitvector_b v \<bind> (\<lambda>x . (case x of + _ => write_tag_bool dict_Sail2_values_Bitvector_a addr t \<bind> (\<lambda>x . (case x of _ => return () )) )) )" definition MEMval_tag_conditional :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'b \<Rightarrow>('regval,(bool),'e)monad " where - " MEMval_tag_conditional dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v = ( write_mem_val - dict_Sail_values_Bitvector_b v \<bind> (\<lambda> b . write_tag_bool - dict_Sail_values_Bitvector_a addr t \<bind> (\<lambda>x . (case x of _ => return (if b then True else False) ))))" + " MEMval_tag_conditional dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b addr size1 t v = ( write_mem_val + dict_Sail2_values_Bitvector_b v \<bind> (\<lambda> b . write_tag_bool + dict_Sail2_values_Bitvector_a addr t \<bind> (\<lambda>x . (case x of _ => return (if b then True else False) ))))" (*val MEM_sync : forall 'regval 'e. unit -> monad 'regval unit 'e*) @@ -135,62 +135,45 @@ definition get_slice_int_bl :: " int \<Rightarrow> int \<Rightarrow> int \<Righ (*val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*) definition get_slice_int0 :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a " where - " get_slice_int0 dict_Sail_values_Bitvector_a len n lo = ( - (of_bools_method dict_Sail_values_Bitvector_a) (get_slice_int_bl len n lo))" + " get_slice_int0 dict_Sail2_values_Bitvector_a len n lo = ( + (of_bools_method dict_Sail2_values_Bitvector_a) (get_slice_int_bl len n lo))" definition write_ram :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'e \<Rightarrow> int \<Rightarrow> 'f \<Rightarrow> 'b \<Rightarrow> 'a \<Rightarrow>('d,(unit),'c)monad " where - " write_ram dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 _ addr data = ( - MEMea dict_Sail_values_Bitvector_b addr size1 \<then> - MEMval dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a addr size1 data )" + " write_ram dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b _ size1 _ addr data = ( + MEMea dict_Sail2_values_Bitvector_b addr size1 \<then> + MEMval dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a addr size1 data )" definition read_ram :: " 'a Bitvector_class \<Rightarrow> 'c Bitvector_class \<Rightarrow> 'e \<Rightarrow> int \<Rightarrow> 'f \<Rightarrow> 'a \<Rightarrow>('d,'c,'b)monad " where - " read_ram dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c _ size1 _ addr = ( MEMr - dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c addr size1 )" + " read_ram dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_c _ size1 _ addr = ( MEMr + dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_c addr size1 )" -definition string_of_bits :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> string " where - " string_of_bits dict_Sail_values_Bitvector_a bs = ( string_of_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) ((bits_of_method dict_Sail_values_Bitvector_a) bs))" - definition string_of_int :: " 'a Show_class \<Rightarrow> 'a \<Rightarrow> string " where " string_of_int dict_Show_Show_a = ((show_method dict_Show_Show_a))" -definition sign_extend0 :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b " where - " sign_extend0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len = ( maybe_failwith ( - (of_bits_method dict_Sail_values_Bitvector_b) (exts_bv dict_Sail_values_Bitvector_a len bits)))" - -definition zero_extend0 :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b " where - " zero_extend0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len = ( maybe_failwith ( - (of_bits_method dict_Sail_values_Bitvector_b) (extz_bv dict_Sail_values_Bitvector_a len bits)))" - - definition shift_bits_left :: " 'b Bitvector_class \<Rightarrow> 'd Bitvector_class \<Rightarrow> 'e Bitvector_class \<Rightarrow> 'd \<Rightarrow> 'e \<Rightarrow>('c,'b,'a)monad " where - " shift_bits_left dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = ( + " shift_bits_left dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n = ( (let r = (Option.bind ( - (unsigned_method dict_Sail_values_Bitvector_e) n) (\<lambda> n . (of_bits_method dict_Sail_values_Bitvector_b) (shiftl_bv dict_Sail_values_Bitvector_d v n))) in + (unsigned_method dict_Sail2_values_Bitvector_e) n) (\<lambda> n . (of_bits_method dict_Sail2_values_Bitvector_b) (shiftl_bv dict_Sail2_values_Bitvector_d v n))) in maybe_fail (''shift_bits_left'') r))" definition shift_bits_right :: " 'b Bitvector_class \<Rightarrow> 'd Bitvector_class \<Rightarrow> 'e Bitvector_class \<Rightarrow> 'd \<Rightarrow> 'e \<Rightarrow>('c,'b,'a)monad " where - " shift_bits_right dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = ( + " shift_bits_right dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n = ( (let r = (Option.bind ( - (unsigned_method dict_Sail_values_Bitvector_e) n) (\<lambda> n . (of_bits_method dict_Sail_values_Bitvector_b) (shiftr_bv dict_Sail_values_Bitvector_d v n))) in + (unsigned_method dict_Sail2_values_Bitvector_e) n) (\<lambda> n . (of_bits_method dict_Sail2_values_Bitvector_b) (shiftr_bv dict_Sail2_values_Bitvector_d v n))) in maybe_fail (''shift_bits_right'') r))" definition shift_bits_right_arith :: " 'b Bitvector_class \<Rightarrow> 'd Bitvector_class \<Rightarrow> 'e Bitvector_class \<Rightarrow> 'd \<Rightarrow> 'e \<Rightarrow>('c,'b,'a)monad " where - " shift_bits_right_arith dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = ( + " shift_bits_right_arith dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_d dict_Sail2_values_Bitvector_e v n = ( (let r = (Option.bind ( - (unsigned_method dict_Sail_values_Bitvector_e) n) (\<lambda> n . (of_bits_method dict_Sail_values_Bitvector_b) (arith_shiftr_bv dict_Sail_values_Bitvector_d v n))) in + (unsigned_method dict_Sail2_values_Bitvector_e) n) (\<lambda> n . (of_bits_method dict_Sail2_values_Bitvector_b) (arith_shiftr_bv dict_Sail2_values_Bitvector_d v n))) in maybe_fail (''shift_bits_right_arith'') r))" (* Use constants for undefined values for now *) -definition internal_pick :: " 'a list \<Rightarrow>('c,'a,'b)monad " where - " internal_pick vs = ( return (List.hd vs))" - definition undefined_string :: " unit \<Rightarrow>('b,(string),'a)monad " where " undefined_string _ = ( return (''''))" @@ -206,13 +189,13 @@ definition undefined_vector :: " int \<Rightarrow> 'a \<Rightarrow>('rv,('a lis (*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) definition undefined_bitvector :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow>('rv,'a,'e)monad " where - " undefined_bitvector dict_Sail_values_Bitvector_a len = ( return ( - (of_bools_method dict_Sail_values_Bitvector_a) (repeat [False] len)))" + " undefined_bitvector dict_Sail2_values_Bitvector_a len = ( return ( + (of_bools_method dict_Sail2_values_Bitvector_a) (repeat [False] len)))" (*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) definition undefined_bits :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow>('rv,'a,'e)monad " where - " undefined_bits dict_Sail_values_Bitvector_a = ( - undefined_bitvector dict_Sail_values_Bitvector_a )" + " undefined_bits dict_Sail2_values_Bitvector_a = ( + undefined_bitvector dict_Sail2_values_Bitvector_a )" definition undefined_bit :: " unit \<Rightarrow>('b,(bitU),'a)monad " where " undefined_bit _ = ( return B0 )" @@ -240,12 +223,26 @@ definition elf_entry :: " unit \<Rightarrow> int " where definition print_bits :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow> 'a \<Rightarrow> unit " where - " print_bits dict_Sail_values_Bitvector_a msg bs = ( prerr_endline (msg @ (string_of_bits - dict_Sail_values_Bitvector_a bs)))" + " print_bits dict_Sail2_values_Bitvector_a msg bs = ( print_endline (msg @ (string_of_bv + dict_Sail2_values_Bitvector_a bs)))" + +definition prerr_bits :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow> 'a \<Rightarrow> unit " where + " prerr_bits dict_Sail2_values_Bitvector_a msg bs = ( prerr_endline (msg @ (string_of_bv + dict_Sail2_values_Bitvector_a bs)))" + + +(*val prerr_string : string -> unit*) +definition prerr_string :: " string \<Rightarrow> unit " where + " prerr_string _ = ( () )" (*val get_time_ns : unit -> integer*) definition get_time_ns :: " unit \<Rightarrow> int " where " get_time_ns _ = (( 0 :: int))" + +(*val cycle_count : unit -> unit*) +definition cycle_count :: " unit \<Rightarrow> unit " where + " cycle_count _ = ( () )" + end diff --git a/snapshots/isabelle/lib/lem/Lem_basic_classes.thy b/snapshots/isabelle/lib/lem/Lem_basic_classes.thy index c2032dc1..c23da22b 100644 --- a/snapshots/isabelle/lib/lem/Lem_basic_classes.thy +++ b/snapshots/isabelle/lib/lem/Lem_basic_classes.thy @@ -15,6 +15,7 @@ begin (*open import Bool*) (*open import {coq} `Coq.Strings.Ascii`*) +(*open import {hol} `ternaryComparisonsTheory`*) (* ========================================================================== *) (* Equality *) diff --git a/snapshots/isabelle/lib/lem/Lem_machine_word.thy b/snapshots/isabelle/lib/lem/Lem_machine_word.thy index 3f83789c..85323bb2 100644 --- a/snapshots/isabelle/lib/lem/Lem_machine_word.thy +++ b/snapshots/isabelle/lib/lem/Lem_machine_word.thy @@ -8,13 +8,14 @@ imports "Lem_num" "Lem_basic_classes" "Lem_show" + "Lem_function" "~~/src/HOL/Word/Word" begin -(*open import Bool Num Basic_classes Show*) +(*open import Bool Num Basic_classes Show Function*) (*open import {isabelle} `~~/src/HOL/Word/Word`*) (*open import {hol} `wordsTheory` `wordsLib` `bitstringTheory` `integer_wordTheory`*) diff --git a/snapshots/isabelle/lib/lem/Lem_num.thy b/snapshots/isabelle/lib/lem/Lem_num.thy index 0d7a72ea..ddbdd533 100644 --- a/snapshots/isabelle/lib/lem/Lem_num.thy +++ b/snapshots/isabelle/lib/lem/Lem_num.thy @@ -16,8 +16,8 @@ begin (*open import Bool Basic_classes*) (*open import {isabelle} `~~/src/HOL/Word/Word` `Real` `~~/src/HOL/NthRoot`*) -(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory`*) -(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*) +(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory` `transcTheory`*) +(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.QArith.Qround` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*) (*class inline ( Numeral 'a ) val fromNumeral : numeral -> 'a diff --git a/snapshots/isabelle/lib/sail/Hoare.thy b/snapshots/isabelle/lib/sail/Hoare.thy index ee7a5fa6..76750117 100644 --- a/snapshots/isabelle/lib/sail/Hoare.thy +++ b/snapshots/isabelle/lib/sail/Hoare.thy @@ -1,6 +1,6 @@ theory Hoare imports - State_lemmas + Sail2_state_lemmas "HOL-Eisbach.Eisbach_Tools" begin @@ -13,7 +13,7 @@ subsection \<open>Hoare triples\<close> type_synonym 'regs predS = "'regs sequential_state \<Rightarrow> bool" -definition PrePost :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> (('a, 'e) result \<Rightarrow> 'regs predS) \<Rightarrow> bool" +definition PrePost :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> (('a, 'e) result \<Rightarrow> 'regs predS) \<Rightarrow> bool" ("\<lbrace>_\<rbrace> _ \<lbrace>_\<rbrace>") where "PrePost P f Q \<equiv> (\<forall>s. P s \<longrightarrow> (\<forall>(r, s') \<in> f s. Q r s'))" lemma PrePostI: @@ -42,19 +42,20 @@ lemma PrePost_weaken_post: shows "PrePost A f C" using assms by (blast intro: PrePost_consequence) -named_theorems PrePost_intro +named_theorems PrePost_compositeI +named_theorems PrePost_atomI -lemma PrePost_True_post[PrePost_intro, intro, simp]: +lemma PrePost_True_post[PrePost_atomI, intro, simp]: "PrePost P m (\<lambda>_ _. True)" unfolding PrePost_def by auto lemma PrePost_any: "PrePost (\<lambda>s. \<forall>(r, s') \<in> m s. Q r s') m Q" unfolding PrePost_def by auto -lemma PrePost_returnS[intro, PrePost_intro]: "PrePost (P (Value x)) (returnS x) P" +lemma PrePost_returnS[intro, PrePost_atomI]: "PrePost (P (Value x)) (returnS x) P" unfolding PrePost_def returnS_def by auto -lemma PrePost_bindS[intro, PrePost_intro]: +lemma PrePost_bindS[intro, PrePost_compositeI]: assumes f: "\<And>s a s'. (Value a, s') \<in> m s \<Longrightarrow> PrePost (R a) (f a) Q" and m: "PrePost P m (\<lambda>r. case r of Value a \<Rightarrow> R a | Ex e \<Rightarrow> Q (Ex e))" shows "PrePost P (bindS m f) Q" @@ -89,10 +90,10 @@ lemma PrePost_bindS_unit: shows "PrePost P (bindS m f) Q" using assms by auto -lemma PrePost_readS[intro, PrePost_intro]: "PrePost (\<lambda>s. P (Value (f s)) s) (readS f) P" +lemma PrePost_readS[intro, PrePost_atomI]: "PrePost (\<lambda>s. P (Value (f s)) s) (readS f) P" unfolding PrePost_def readS_def returnS_def by auto -lemma PrePost_updateS[intro, PrePost_intro]: "PrePost (\<lambda>s. P (Value ()) (f s)) (updateS f) P" +lemma PrePost_updateS[intro, PrePost_atomI]: "PrePost (\<lambda>s. P (Value ()) (f s)) (updateS f) P" unfolding PrePost_def updateS_def returnS_def by auto lemma PrePost_if: @@ -100,7 +101,7 @@ lemma PrePost_if: shows "PrePost P (if b then f else g) Q" using assms by auto -lemma PrePost_if_branch[PrePost_intro]: +lemma PrePost_if_branch[PrePost_compositeI]: assumes "b \<Longrightarrow> PrePost Pf f Q" and "\<not>b \<Longrightarrow> PrePost Pg g Q" shows "PrePost (if b then Pf else Pg) (if b then f else g) Q" using assms by auto @@ -115,35 +116,65 @@ lemma PrePost_if_else: shows "PrePost P (if b then f else g) Q" using assms by auto -lemma PrePost_prod_cases[PrePost_intro]: +lemma PrePost_prod_cases[PrePost_compositeI]: assumes "PrePost P (f (fst x) (snd x)) Q" shows "PrePost P (case x of (a, b) \<Rightarrow> f a b) Q" using assms by (auto split: prod.splits) -lemma PrePost_option_cases[PrePost_intro]: +lemma PrePost_option_cases[PrePost_compositeI]: assumes "\<And>a. PrePost (PS a) (s a) Q" and "PrePost PN n Q" shows "PrePost (case x of Some a \<Rightarrow> PS a | None \<Rightarrow> PN) (case x of Some a \<Rightarrow> s a | None \<Rightarrow> n) Q" using assms by (auto split: option.splits) -lemma PrePost_let[intro, PrePost_intro]: +lemma PrePost_let[intro, PrePost_compositeI]: assumes "PrePost P (m y) Q" shows "PrePost P (let x = y in m x) Q" using assms by auto -lemma PrePost_assert_expS[intro, PrePost_intro]: "PrePost (if c then P (Value ()) else P (Ex (Failure m))) (assert_expS c m) P" +lemma PrePost_and_boolS[PrePost_compositeI]: + assumes r: "PrePost R r Q" + and l: "PrePost P l (\<lambda>r. case r of Value True \<Rightarrow> R | _ \<Rightarrow> Q r)" + shows "PrePost P (and_boolS l r) Q" + unfolding and_boolS_def +proof (rule PrePost_bindS) + fix s a s' + assume "(Value a, s') \<in> l s" + show "PrePost (if a then R else Q (Value False)) (if a then r else returnS False) Q" + using r by auto +next + show "PrePost P l (\<lambda>r. case r of Value a \<Rightarrow> if a then R else Q (Value False) | Ex e \<Rightarrow> Q (Ex e))" + using l by (elim PrePost_weaken_post) (auto split: result.splits) +qed + +lemma PrePost_or_boolS[PrePost_compositeI]: + assumes r: "PrePost R r Q" + and l: "PrePost P l (\<lambda>r. case r of Value False \<Rightarrow> R | _ \<Rightarrow> Q r)" + shows "PrePost P (or_boolS l r) Q" + unfolding or_boolS_def +proof (rule PrePost_bindS) + fix s a s' + assume "(Value a, s') \<in> l s" + show "PrePost (if a then Q (Value True) else R) (if a then returnS True else r) Q" + using r by auto +next + show "PrePost P l (\<lambda>r. case r of Value a \<Rightarrow> if a then Q (Value True) else R | Ex e \<Rightarrow> Q (Ex e))" + using l by (elim PrePost_weaken_post) (auto split: result.splits) +qed + +lemma PrePost_assert_expS[intro, PrePost_atomI]: "PrePost (if c then P (Value ()) else P (Ex (Failure m))) (assert_expS c m) P" unfolding PrePost_def assert_expS_def by (auto simp: returnS_def failS_def) -lemma PrePost_chooseS[intro, PrePost_intro]: "PrePost (\<lambda>s. \<forall>x \<in> xs. Q (Value x) s) (chooseS xs) Q" +lemma PrePost_chooseS[intro, PrePost_atomI]: "PrePost (\<lambda>s. \<forall>x \<in> xs. Q (Value x) s) (chooseS xs) Q" by (auto simp: PrePost_def chooseS_def) -lemma PrePost_failS[intro, PrePost_intro]: "PrePost (Q (Ex (Failure msg))) (failS msg) Q" +lemma PrePost_failS[intro, PrePost_atomI]: "PrePost (Q (Ex (Failure msg))) (failS msg) Q" by (auto simp: PrePost_def failS_def) lemma case_result_combine[simp]: "(case r of Value a \<Rightarrow> Q (Value a) | Ex e \<Rightarrow> Q (Ex e)) = Q r" by (auto split: result.splits) -lemma PrePost_foreachS_Nil[intro, simp, PrePost_intro]: +lemma PrePost_foreachS_Nil[intro, simp, PrePost_atomI]: "PrePost (Q (Value vars)) (foreachS [] vars body) Q" by auto @@ -180,7 +211,7 @@ there is an exception. [1] D. Cock, G. Klein, and T. Sewell, ‘Secure Microkernels, State Monads and Scalable Refinement’, in Theorem Proving in Higher Order Logics, 2008, pp. 167–182.\<close> -definition PrePostE :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> ('a \<Rightarrow> 'regs predS) \<Rightarrow> ('e ex \<Rightarrow> 'regs predS) \<Rightarrow> bool" +definition PrePostE :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> ('a \<Rightarrow> 'regs predS) \<Rightarrow> ('e ex \<Rightarrow> 'regs predS) \<Rightarrow> bool" ("\<lbrace>_\<rbrace> _ \<lbrace>_ \<bar> _\<rbrace>") where "PrePostE P f Q E \<equiv> PrePost P f (\<lambda>v. case v of Value a \<Rightarrow> Q a | Ex e \<Rightarrow> E e)" lemmas PrePost_defs = PrePost_def PrePostE_def @@ -219,20 +250,42 @@ lemma PrePostE_weaken_post: shows "PrePostE A f C E" using assms by (blast intro: PrePostE_consequence) -named_theorems PrePostE_intro +named_theorems PrePostE_compositeI +named_theorems PrePostE_atomI + +lemma PrePostE_conj_conds: + assumes "PrePostE P1 m Q1 E1" + and "PrePostE P2 m Q2 E2" + shows "PrePostE (\<lambda>s. P1 s \<and> P2 s) m (\<lambda>r s. Q1 r s \<and> Q2 r s) (\<lambda>e s. E1 e s \<and> E2 e s)" + using assms by (auto intro: PrePostE_I elim: PrePostE_elim) + +lemmas PrePostE_conj_conds_consequence = PrePostE_conj_conds[THEN PrePostE_consequence] + +lemma PrePostE_post_mp: + assumes "PrePostE P m Q' E" + and "PrePostE P m (\<lambda>r s. Q' r s \<longrightarrow> Q r s) E" + shows "PrePostE P m Q E" + using PrePostE_conj_conds[OF assms] by (auto intro: PrePostE_weaken_post) + +lemma PrePostE_cong: + assumes "\<And>s. P1 s \<longleftrightarrow> P2 s" and "\<And>s. P1 s \<Longrightarrow> m1 s = m2 s" and "\<And>r s. Q1 r s \<longleftrightarrow> Q2 r s" + and "\<And>e s. E1 e s \<longleftrightarrow> E2 e s" + shows "PrePostE P1 m1 Q1 E1 \<longleftrightarrow> PrePostE P2 m2 Q2 E2" + using assms unfolding PrePostE_def PrePost_def + by (auto split: result.splits) -lemma PrePostE_True_post[PrePost_intro, intro, simp]: +lemma PrePostE_True_post[PrePostE_atomI, intro, simp]: "PrePostE P m (\<lambda>_ _. True) (\<lambda>_ _. True)" unfolding PrePost_defs by (auto split: result.splits) lemma PrePostE_any: "PrePostE (\<lambda>s. \<forall>(r, s') \<in> m s. case r of Value a \<Rightarrow> Q a s' | Ex e \<Rightarrow> E e s') m Q E" by (intro PrePostE_I) auto -lemma PrePostE_returnS[PrePostE_intro, intro, simp]: +lemma PrePostE_returnS[PrePostE_atomI, intro, simp]: "PrePostE (P x) (returnS x) P Q" unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) -lemma PrePostE_bindS[intro, PrePostE_intro]: +lemma PrePostE_bindS[intro, PrePostE_compositeI]: assumes f: "\<And>s a s'. (Value a, s') \<in> m s \<Longrightarrow> PrePostE (R a) (f a) Q E" and m: "PrePostE P m R E" shows "PrePostE P (bindS m f) Q E" @@ -252,13 +305,13 @@ lemma PrePostE_bindS_unit: shows "PrePostE P (bindS m f) Q E" using assms by auto -lemma PrePostE_readS[PrePostE_intro, intro]: "PrePostE (\<lambda>s. Q (f s) s) (readS f) Q E" +lemma PrePostE_readS[PrePostE_atomI, intro]: "PrePostE (\<lambda>s. Q (f s) s) (readS f) Q E" unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) -lemma PrePostE_updateS[PrePostE_intro, intro]: "PrePostE (\<lambda>s. Q () (f s)) (updateS f) Q E" +lemma PrePostE_updateS[PrePostE_atomI, intro]: "PrePostE (\<lambda>s. Q () (f s)) (updateS f) Q E" unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) -lemma PrePostE_if_branch[PrePostE_intro]: +lemma PrePostE_if_branch[PrePostE_compositeI]: assumes "b \<Longrightarrow> PrePostE Pf f Q E" and "\<not>b \<Longrightarrow> PrePostE Pg g Q E" shows "PrePostE (if b then Pf else Pg) (if b then f else g) Q E" using assms by (auto) @@ -278,33 +331,93 @@ lemma PrePostE_if_else: shows "PrePostE P (if b then f else g) Q E" using assms by auto -lemma PrePostE_prod_cases[PrePostE_intro]: +lemma PrePostE_prod_cases[PrePostE_compositeI]: assumes "PrePostE P (f (fst x) (snd x)) Q E" shows "PrePostE P (case x of (a, b) \<Rightarrow> f a b) Q E" using assms by (auto split: prod.splits) -lemma PrePostE_option_cases[PrePostE_intro]: +lemma PrePostE_option_cases[PrePostE_compositeI]: assumes "\<And>a. PrePostE (PS a) (s a) Q E" and "PrePostE PN n Q E" shows "PrePostE (case x of Some a \<Rightarrow> PS a | None \<Rightarrow> PN) (case x of Some a \<Rightarrow> s a | None \<Rightarrow> n) Q E" using assms by (auto split: option.splits) -lemma PrePostE_let[PrePostE_intro]: +lemma PrePostE_sum_cases[PrePostE_compositeI]: + assumes "\<And>a. PrePostE (Pl a) (l a) Q E" and "\<And>b. PrePostE (Pr b) (r b) Q E" + shows "PrePostE (case x of Inl a \<Rightarrow> Pl a | Inr b \<Rightarrow> Pr b) (case x of Inl a \<Rightarrow> l a | Inr b \<Rightarrow> r b) Q E" + using assms by (auto split: sum.splits) + +lemma PrePostE_let[PrePostE_compositeI]: assumes "PrePostE P (m y) Q E" shows "PrePostE P (let x = y in m x) Q E" using assms by auto -lemma PrePostE_assert_expS[PrePostE_intro, intro]: +lemma PrePostE_and_boolS[PrePostE_compositeI]: + assumes r: "PrePostE R r Q E" + and l: "PrePostE P l (\<lambda>r. if r then R else Q False) E" + shows "PrePostE P (and_boolS l r) Q E" + using assms unfolding PrePostE_def + by (intro PrePost_and_boolS) (auto elim: PrePost_weaken_post split: if_splits result.splits) + +lemma PrePostE_or_boolS[PrePostE_compositeI]: + assumes r: "PrePostE R r Q E" + and l: "PrePostE P l (\<lambda>r. if r then Q True else R) E" + shows "PrePostE P (or_boolS l r) Q E" + using assms unfolding PrePostE_def + by (intro PrePost_or_boolS) (auto elim: PrePost_weaken_post split: if_splits result.splits) + +lemma PrePostE_assert_expS[PrePostE_atomI, intro]: "PrePostE (if c then P () else Q (Failure m)) (assert_expS c m) P Q" unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) -lemma PrePostE_failS[PrePost_intro, intro]: +lemma PrePostE_failS[PrePostE_atomI, intro]: "PrePostE (E (Failure msg)) (failS msg) Q E" unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) -lemma PrePostE_chooseS[intro, PrePostE_intro]: +lemma PrePostE_maybe_failS[PrePostE_atomI]: + "PrePostE (\<lambda>s. case v of Some v \<Rightarrow> Q v s | None \<Rightarrow> E (Failure msg) s) (maybe_failS msg v) Q E" + by (auto simp: maybe_failS_def split: option.splits) + +lemma PrePostE_exitS[PrePostE_atomI, intro]: "PrePostE (E (Failure ''exit'')) (exitS msg) Q E" + unfolding exitS_def PrePostE_def PrePost_def failS_def by auto + +lemma PrePostE_chooseS[intro, PrePostE_atomI]: "PrePostE (\<lambda>s. \<forall>x \<in> xs. Q x s) (chooseS xs) Q E" unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) +lemma PrePostE_throwS[PrePostE_atomI]: "PrePostE (E (Throw e)) (throwS e) Q E" + by (intro PrePostE_I) (auto simp: throwS_def) + +lemma PrePostE_try_catchS[PrePostE_compositeI]: + assumes Ph: "\<And>s e s'. (Ex (Throw e), s') \<in> m s \<Longrightarrow> PrePostE (Ph e) (h e) Q E" + and m: "PrePostE P m Q (\<lambda>ex. case ex of Throw e \<Rightarrow> Ph e | Failure msg \<Rightarrow> E (Failure msg))" + shows "PrePostE P (try_catchS m h) Q E" + unfolding PrePostE_def +proof (intro PrePostI) + fix s r s' + assume "(r, s') \<in> try_catchS m h s" and P: "P s" + then show "(case r of Value a \<Rightarrow> Q a | result.Ex e \<Rightarrow> E e) s'" using m + proof (cases rule: try_catchS_cases) + case (h e s'') + then have "Ph e s''" using P m by (auto elim!: PrePostE_elim) + then show ?thesis using Ph[OF h(1)] h(2) by (auto elim!: PrePostE_elim) + qed (auto elim!: PrePostE_elim) +qed + +lemma PrePostE_catch_early_returnS[PrePostE_compositeI]: + assumes "PrePostE P m Q (\<lambda>ex. case ex of Throw (Inl a) \<Rightarrow> Q a | Throw (Inr e) \<Rightarrow> E (Throw e) | Failure msg \<Rightarrow> E (Failure msg))" + shows "PrePostE P (catch_early_returnS m) Q E" + unfolding catch_early_returnS_def + by (rule PrePostE_try_catchS, rule PrePostE_sum_cases[OF PrePostE_returnS PrePostE_throwS]) + (auto intro: assms) + +lemma PrePostE_early_returnS[PrePostE_atomI]: "PrePostE (E (Throw (Inl r))) (early_returnS r) Q E" + by (auto simp: early_returnS_def intro: PrePostE_throwS) + +lemma PrePostE_liftRS[PrePostE_compositeI]: + assumes "PrePostE P m Q (\<lambda>ex. case ex of Throw e \<Rightarrow> E (Throw (Inr e)) | Failure msg \<Rightarrow> E (Failure msg))" + shows "PrePostE P (liftRS m) Q E" + using assms unfolding liftRS_def by (intro PrePostE_try_catchS[OF PrePostE_throwS]) + lemma PrePostE_foreachS_Cons: assumes "\<And>s vars' s'. (Value vars', s') \<in> body x vars s \<Longrightarrow> PrePostE (Q vars') (foreachS xs vars' body) Q E" and "PrePostE (Q vars) (body x vars) Q E" @@ -317,4 +430,88 @@ lemma PrePostE_foreachS_invariant: using assms unfolding PrePostE_def by (intro PrePost_foreachS_invariant[THEN PrePost_strengthen_pre]) auto +lemma PrePostE_untilS: + assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilS_dom (vars, cond, body, s)" + and cond: "\<And>vars. PrePostE (Inv' Q vars) (cond vars) (\<lambda>c s'. Inv Q vars s' \<and> (c \<longrightarrow> Q vars s')) E" + and body: "\<And>vars. PrePostE (Inv Q vars) (body vars) (Inv' Q) E" + shows "PrePostE (Inv Q vars) (untilS vars cond body) Q E" +proof (unfold PrePostE_def, rule PrePostI) + fix s r s' + assume Inv_s: "Inv Q vars s" and r: "(r, s') \<in> untilS vars cond body s" + with dom[OF Inv_s] cond body + show "(case r of Value a \<Rightarrow> Q a | result.Ex e \<Rightarrow> E e) s'" + proof (induction vars cond body s rule: untilS.pinduct[case_names Step]) + case (Step vars cond body s) + consider + (Value) vars' c sb sc where "(Value vars', sb) \<in> body vars s" and "(Value c, sc) \<in> cond vars' sb" + and "if c then r = Value vars' \<and> s' = sc else (r, s') \<in> untilS vars' cond body sc" + | (Ex) e where "(Ex e, s') \<in> bindS (body vars) cond s" and "r = Ex e" + using Step(1,6) + by (auto simp: untilS.psimps returnS_def Ex_bindS_iff elim!: bindS_cases split: if_splits; fastforce) + then show ?case + proof cases + case Value + then show ?thesis using Step.IH[OF Value(1,2) _ Step(3,4)] Step(3,4,5) + by (auto split: if_splits elim: PrePostE_elim) + next + case Ex + then show ?thesis using Step(3,4,5) by (auto elim!: bindS_cases PrePostE_elim) + qed + qed +qed + +lemma PrePostE_untilS_pure_cond: + assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilS_dom (vars, returnS \<circ> cond, body, s)" + and body: "\<And>vars. PrePostE (Inv Q vars) (body vars) (\<lambda>vars' s'. Inv Q vars' s' \<and> (cond vars' \<longrightarrow> Q vars' s')) E" + shows "PrePostE (Inv Q vars) (untilS vars (returnS \<circ> cond) body) Q E" + using assms by (intro PrePostE_untilS) (auto simp: comp_def) + +lemma PrePostE_liftState_untilM: + assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilM_dom (vars, cond, body)" + and cond: "\<And>vars. PrePostE (Inv' Q vars) (liftState r (cond vars)) (\<lambda>c s'. Inv Q vars s' \<and> (c \<longrightarrow> Q vars s')) E" + and body: "\<And>vars. PrePostE (Inv Q vars) (liftState r (body vars)) (Inv' Q) E" + shows "PrePostE (Inv Q vars) (liftState r (untilM vars cond body)) Q E" +proof - + have domS: "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)" if "Inv Q vars s" for s + using dom that by (intro untilM_dom_untilS_dom) + then have "PrePostE (Inv Q vars) (untilS vars (liftState r \<circ> cond) (liftState r \<circ> body)) Q E" + using cond body by (auto intro: PrePostE_untilS simp: comp_def) + moreover have "liftState r (untilM vars cond body) s = untilS vars (liftState r \<circ> cond) (liftState r \<circ> body) s" + if "Inv Q vars s" for s + unfolding liftState_untilM[OF domS[OF that] dom[OF that]] .. + ultimately show ?thesis by (auto cong: PrePostE_cong) +qed + +lemma PrePostE_liftState_untilM_pure_cond: + assumes dom: "\<And>s. Inv Q vars s \<Longrightarrow> untilM_dom (vars, return \<circ> cond, body)" + and body: "\<And>vars. PrePostE (Inv Q vars) (liftState r (body vars)) (\<lambda>vars' s'. Inv Q vars' s' \<and> (cond vars' \<longrightarrow> Q vars' s')) E" + shows "PrePostE (Inv Q vars) (liftState r (untilM vars (return \<circ> cond) body)) Q E" + using assms by (intro PrePostE_liftState_untilM) (auto simp: comp_def liftState_simp) + +lemma PrePostE_undefined_boolS[PrePostE_atomI]: + "PrePostE (\<lambda>s. \<forall>b. Q b s) + (undefined_boolS unit) Q E" + unfolding undefined_boolS_def seqS_def + by (auto intro: PrePostE_strengthen_pre PrePostE_chooseS) + +lemma PrePostE_bool_of_bitU_nondetS_any: + "PrePostE (\<lambda>s. \<forall>b. Q b s) (bool_of_bitU_nondetS b) Q E" + unfolding bool_of_bitU_nondetS_def undefined_boolS_def + by (cases b; simp; rule PrePostE_strengthen_pre, rule PrePostE_atomI) auto + +lemma PrePostE_bools_of_bits_nondetS_any: + "PrePostE (\<lambda>s. \<forall>bs. Q bs s) (bools_of_bits_nondetS bs) Q E" + unfolding bools_of_bits_nondetS_def + by (rule PrePostE_weaken_post[where B = "\<lambda>_ s. \<forall>bs. Q bs s"], rule PrePostE_strengthen_pre, + (rule PrePostE_foreachS_invariant[OF PrePostE_strengthen_pre] PrePostE_bindS PrePostE_returnS + PrePostE_bool_of_bitU_nondetS_any)+) + auto + +lemma PrePostE_internal_pick: + "xs \<noteq> [] \<Longrightarrow> PrePostE (\<lambda>s. \<forall>x \<in> set xs. Q x s) (internal_pickS xs) Q E" + unfolding internal_pickS_def Let_def + by (rule PrePostE_strengthen_pre, + (rule PrePostE_compositeI PrePostE_atomI PrePostE_bools_of_bits_nondetS_any)+) + (auto split: option.splits) + end diff --git a/snapshots/isabelle/lib/sail/ROOT b/snapshots/isabelle/lib/sail/ROOT index 3189f216..6bdedc43 100644 --- a/snapshots/isabelle/lib/sail/ROOT +++ b/snapshots/isabelle/lib/sail/ROOT @@ -3,9 +3,10 @@ session "Sail" = "LEM" + sessions "HOL-Eisbach" theories - Sail_values_lemmas - Prompt - State_lemmas - Sail_operators_mwords_lemmas - Sail_operators_bitlists + Sail2_values_lemmas + Sail2_prompt + Sail2_state_lemmas + Sail2_operators_mwords_lemmas + Sail2_operators_bitlists + Sail2_string Hoare diff --git a/snapshots/isabelle/lib/sail/Sail_instr_kinds.thy b/snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy index 088ff4a8..7f9fc60b 100644 --- a/snapshots/isabelle/lib/sail/Sail_instr_kinds.thy +++ b/snapshots/isabelle/lib/sail/Sail2_instr_kinds.thy @@ -1,6 +1,6 @@ -chapter \<open>Generated by Lem from ../../src/lem_interp/sail_instr_kinds.lem.\<close> +chapter \<open>Generated by Lem from ../../src/lem_interp/sail2_instr_kinds.lem.\<close> -theory "Sail_instr_kinds" +theory "Sail2_instr_kinds" imports Main @@ -70,29 +70,29 @@ record 'a EnumerationType_class= (*val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering*) definition enumeration_typeCompare :: " 'a EnumerationType_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> ordering " where - " enumeration_typeCompare dict_Sail_instr_kinds_EnumerationType_a e1 e2 = ( + " enumeration_typeCompare dict_Sail2_instr_kinds_EnumerationType_a e1 e2 = ( (genericCompare (op<) (op=) ( - (toNat_method dict_Sail_instr_kinds_EnumerationType_a) e1) ((toNat_method dict_Sail_instr_kinds_EnumerationType_a) e2)))" + (toNat_method dict_Sail2_instr_kinds_EnumerationType_a) e1) ((toNat_method dict_Sail2_instr_kinds_EnumerationType_a) e2)))" definition instance_Basic_classes_Ord_var_dict :: " 'a EnumerationType_class \<Rightarrow> 'a Ord_class " where - " instance_Basic_classes_Ord_var_dict dict_Sail_instr_kinds_EnumerationType_a = ((| + " instance_Basic_classes_Ord_var_dict dict_Sail2_instr_kinds_EnumerationType_a = ((| compare_method = - (enumeration_typeCompare dict_Sail_instr_kinds_EnumerationType_a), + (enumeration_typeCompare dict_Sail2_instr_kinds_EnumerationType_a), isLess_method = (\<lambda> r1 r2. (enumeration_typeCompare - dict_Sail_instr_kinds_EnumerationType_a r1 r2) = LT), + dict_Sail2_instr_kinds_EnumerationType_a r1 r2) = LT), isLessEqual_method = (\<lambda> r1 r2. (enumeration_typeCompare - dict_Sail_instr_kinds_EnumerationType_a r1 r2) \<noteq> GT), + dict_Sail2_instr_kinds_EnumerationType_a r1 r2) \<noteq> GT), isGreater_method = (\<lambda> r1 r2. (enumeration_typeCompare - dict_Sail_instr_kinds_EnumerationType_a r1 r2) = GT), + dict_Sail2_instr_kinds_EnumerationType_a r1 r2) = GT), isGreaterEqual_method = (\<lambda> r1 r2. (enumeration_typeCompare - dict_Sail_instr_kinds_EnumerationType_a r1 r2) \<noteq> LT)|) )" + dict_Sail2_instr_kinds_EnumerationType_a r1 r2) \<noteq> LT)|) )" @@ -114,8 +114,8 @@ datatype read_kind = (* x86 reads *) | Read_X86_locked (* the read part of a lock'd instruction (rmw) *) -definition instance_Show_Show_Sail_instr_kinds_read_kind_dict :: "(read_kind)Show_class " where - " instance_Show_Show_Sail_instr_kinds_read_kind_dict = ((| +definition instance_Show_Show_Sail2_instr_kinds_read_kind_dict :: "(read_kind)Show_class " where + " instance_Show_Show_Sail2_instr_kinds_read_kind_dict = ((| show_method = (\<lambda>x . (case x of @@ -148,8 +148,8 @@ datatype write_kind = (* x86 writes *) | Write_X86_locked (* the write part of a lock'd instruction (rmw) *) -definition instance_Show_Show_Sail_instr_kinds_write_kind_dict :: "(write_kind)Show_class " where - " instance_Show_Show_Sail_instr_kinds_write_kind_dict = ((| +definition instance_Show_Show_Sail2_instr_kinds_write_kind_dict :: "(write_kind)Show_class " where + " instance_Show_Show_Sail2_instr_kinds_write_kind_dict = ((| show_method = (\<lambda>x . (case x of @@ -182,13 +182,17 @@ datatype barrier_kind = | Barrier_RISCV_r_r | Barrier_RISCV_rw_w | Barrier_RISCV_w_w + | Barrier_RISCV_w_rw + | Barrier_RISCV_rw_r + | Barrier_RISCV_r_w + | Barrier_RISCV_w_r | Barrier_RISCV_i (* X86 *) | Barrier_x86_MFENCE -definition instance_Show_Show_Sail_instr_kinds_barrier_kind_dict :: "(barrier_kind)Show_class " where - " instance_Show_Show_Sail_instr_kinds_barrier_kind_dict = ((| +definition instance_Show_Show_Sail2_instr_kinds_barrier_kind_dict :: "(barrier_kind)Show_class " where + " instance_Show_Show_Sail2_instr_kinds_barrier_kind_dict = ((| show_method = (\<lambda>x . (case x of @@ -210,6 +214,10 @@ definition instance_Show_Show_Sail_instr_kinds_barrier_kind_dict :: "(barrier_k | Barrier_RISCV_r_r => (''Barrier_RISCV_r_r'') | Barrier_RISCV_rw_w => (''Barrier_RISCV_rw_w'') | Barrier_RISCV_w_w => (''Barrier_RISCV_w_w'') + | Barrier_RISCV_w_rw => (''Barrier_RISCV_w_rw'') + | Barrier_RISCV_rw_r => (''Barrier_RISCV_rw_r'') + | Barrier_RISCV_r_w => (''Barrier_RISCV_r_w'') + | Barrier_RISCV_w_r => (''Barrier_RISCV_w_r'') | Barrier_RISCV_i => (''Barrier_RISCV_i'') | Barrier_x86_MFENCE => (''Barrier_x86_MFENCE'') ))|) )" @@ -219,8 +227,8 @@ datatype trans_kind = (* AArch64 *) Transaction_start | Transaction_commit | Transaction_abort -definition instance_Show_Show_Sail_instr_kinds_trans_kind_dict :: "(trans_kind)Show_class " where - " instance_Show_Show_Sail_instr_kinds_trans_kind_dict = ((| +definition instance_Show_Show_Sail2_instr_kinds_trans_kind_dict :: "(trans_kind)Show_class " where + " instance_Show_Show_Sail2_instr_kinds_trans_kind_dict = ((| show_method = (\<lambda>x . (case x of @@ -235,15 +243,15 @@ datatype instruction_kind = | IK_mem_read " read_kind " | IK_mem_write " write_kind " | IK_mem_rmw " (read_kind * write_kind)" - | IK_branch (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address), + | IK_branch " unit "(* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address), indirect/computed-branch (single nia of kind NIA_indirect_address) and branch/jump (single nia of kind NIA_concrete_address) *) | IK_trans " trans_kind " - | IK_simple + | IK_simple " unit " -definition instance_Show_Show_Sail_instr_kinds_instruction_kind_dict :: "(instruction_kind)Show_class " where - " instance_Show_Show_Sail_instr_kinds_instruction_kind_dict = ((| +definition instance_Show_Show_Sail2_instr_kinds_instruction_kind_dict :: "(instruction_kind)Show_class " where + " instance_Show_Show_Sail2_instr_kinds_instruction_kind_dict = ((| show_method = (\<lambda>x . (case x of @@ -285,6 +293,14 @@ definition instance_Show_Show_Sail_instr_kinds_instruction_kind_dict :: "(instr (''Barrier_RISCV_rw_w'') | Barrier_RISCV_w_w => (''Barrier_RISCV_w_w'') + | Barrier_RISCV_w_rw => + (''Barrier_RISCV_w_rw'') + | Barrier_RISCV_rw_r => + (''Barrier_RISCV_rw_r'') + | Barrier_RISCV_r_w => + (''Barrier_RISCV_r_w'') + | Barrier_RISCV_w_r => + (''Barrier_RISCV_w_r'') | Barrier_RISCV_i => (''Barrier_RISCV_i'') | Barrier_x86_MFENCE => @@ -390,7 +406,7 @@ definition instance_Show_Show_Sail_instr_kinds_instruction_kind_dict :: "(instr | Write_X86_locked => (''Write_X86_locked'') )) w)))) - | IK_branch => (''IK_branch'') + | IK_branch _ => (''IK_branch'') | IK_trans trans_kind => (''IK_trans '') @ (((\<lambda>x . (case x of Transaction_start => @@ -400,7 +416,7 @@ definition instance_Show_Show_Sail_instr_kinds_instruction_kind_dict :: "(instr | Transaction_abort => (''Transaction_abort'') )) trans_kind)) - | IK_simple => (''IK_simple'') + | IK_simple _ => (''IK_simple'') ))|) )" @@ -425,8 +441,8 @@ definition read_is_exclusive :: " read_kind \<Rightarrow> bool " where -definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_read_kind_dict :: "(read_kind)EnumerationType_class " where - " instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_read_kind_dict = ((| +definition instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_read_kind_dict :: "(read_kind)EnumerationType_class " where + " instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_read_kind_dict = ((| toNat_method = (\<lambda>x . (case x of @@ -445,8 +461,8 @@ definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_read_kind_ ))|) )" -definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_write_kind_dict :: "(write_kind)EnumerationType_class " where - " instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_write_kind_dict = ((| +definition instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_write_kind_dict :: "(write_kind)EnumerationType_class " where + " instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_write_kind_dict = ((| toNat_method = (\<lambda>x . (case x of @@ -464,8 +480,8 @@ definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_write_kind ))|) )" -definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_barrier_kind_dict :: "(barrier_kind)EnumerationType_class " where - " instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_barrier_kind_dict = ((| +definition instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_barrier_kind_dict :: "(barrier_kind)EnumerationType_class " where + " instance_Sail2_instr_kinds_EnumerationType_Sail2_instr_kinds_barrier_kind_dict = ((| toNat_method = (\<lambda>x . (case x of @@ -487,8 +503,12 @@ definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_barrier_ki | Barrier_RISCV_r_r =>( 15 :: nat) | Barrier_RISCV_rw_w =>( 16 :: nat) | Barrier_RISCV_w_w =>( 17 :: nat) - | Barrier_RISCV_i =>( 18 :: nat) - | Barrier_x86_MFENCE =>( 19 :: nat) + | Barrier_RISCV_w_rw =>( 18 :: nat) + | Barrier_RISCV_rw_r =>( 19 :: nat) + | Barrier_RISCV_r_w =>( 20 :: nat) + | Barrier_RISCV_w_r =>( 21 :: nat) + | Barrier_RISCV_i =>( 22 :: nat) + | Barrier_x86_MFENCE =>( 23 :: nat) ))|) )" end diff --git a/snapshots/isabelle/lib/sail/Sail_operators.thy b/snapshots/isabelle/lib/sail/Sail2_operators.thy index 00b32a85..fc4d4749 100644 --- a/snapshots/isabelle/lib/sail/Sail_operators.thy +++ b/snapshots/isabelle/lib/sail/Sail2_operators.thy @@ -1,31 +1,31 @@ -chapter \<open>Generated by Lem from ../../src/gen_lib/sail_operators.lem.\<close> +chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_operators.lem.\<close> -theory "Sail_operators" +theory "Sail2_operators" imports Main "Lem_pervasives_extra" "Lem_machine_word" - "Sail_values" + "Sail2_values" begin (*open import Pervasives_extra*) (*open import Machine_word*) -(*open import Sail_values*) +(*open import Sail2_values*) (*** Bit vector operations *) (*val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list bitU*) definition concat_bv :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'b \<Rightarrow>(bitU)list " where - " concat_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b l r = ( ( - (bits_of_method dict_Sail_values_Bitvector_a) l @(bits_of_method dict_Sail_values_Bitvector_b) r))" + " concat_bv dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b l r = ( ( + (bits_of_method dict_Sail2_values_Bitvector_a) l @(bits_of_method dict_Sail2_values_Bitvector_b) r))" (*val cons_bv : forall 'a. Bitvector 'a => bitU -> 'a -> list bitU*) definition cons_bv :: " 'a Bitvector_class \<Rightarrow> bitU \<Rightarrow> 'a \<Rightarrow>(bitU)list " where - " cons_bv dict_Sail_values_Bitvector_a b v = ( b # - (bits_of_method dict_Sail_values_Bitvector_a) v )" + " cons_bv dict_Sail2_values_Bitvector_a b v = ( b # + (bits_of_method dict_Sail2_values_Bitvector_a) v )" (*val cast_unit_bv : bitU -> list bitU*) @@ -39,8 +39,8 @@ definition bv_of_bit :: " int \<Rightarrow> bitU \<Rightarrow>(bitU)list " whe definition most_significant :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU " where - " most_significant dict_Sail_values_Bitvector_a v = ( (case - (bits_of_method dict_Sail_values_Bitvector_a) v of + " most_significant dict_Sail2_values_Bitvector_a v = ( (case + (bits_of_method dict_Sail2_values_Bitvector_a) v of b # _ => b | _ => B0 (* Treat empty bitvector as all zeros *) ))" @@ -69,24 +69,24 @@ definition get_min_representable_in :: " 'a \<Rightarrow> int \<Rightarrow> int (*val arith_op_bv_int : forall 'a 'b. Bitvector 'a => (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*) definition arith_op_bv_int :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'a " where - " arith_op_bv_int dict_Sail_values_Bitvector_a op1 sign l r = ( - (let r' = ((of_int_method dict_Sail_values_Bitvector_a) ((length_method dict_Sail_values_Bitvector_a) l) r) in (arith_op_bv_method dict_Sail_values_Bitvector_a) op1 sign l r'))" + " arith_op_bv_int dict_Sail2_values_Bitvector_a op1 sign l r = ( + (let r' = ((of_int_method dict_Sail2_values_Bitvector_a) ((length_method dict_Sail2_values_Bitvector_a) l) r) in (arith_op_bv_method dict_Sail2_values_Bitvector_a) op1 sign l r'))" (*val arith_op_int_bv : forall 'a 'b. Bitvector 'a => (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*) definition arith_op_int_bv :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a " where - " arith_op_int_bv dict_Sail_values_Bitvector_a op1 sign l r = ( - (let l' = ((of_int_method dict_Sail_values_Bitvector_a) ((length_method dict_Sail_values_Bitvector_a) r) l) in (arith_op_bv_method dict_Sail_values_Bitvector_a) op1 sign l' r))" + " arith_op_int_bv dict_Sail2_values_Bitvector_a op1 sign l r = ( + (let l' = ((of_int_method dict_Sail2_values_Bitvector_a) ((length_method dict_Sail2_values_Bitvector_a) r) l) in (arith_op_bv_method dict_Sail2_values_Bitvector_a) op1 sign l' r))" definition arith_op_bv_bool :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where - " arith_op_bv_bool dict_Sail_values_Bitvector_a op1 sign l r = ( arith_op_bv_int - dict_Sail_values_Bitvector_a op1 sign l (if r then( 1 :: int) else( 0 :: int)))" + " arith_op_bv_bool dict_Sail2_values_Bitvector_a op1 sign l r = ( arith_op_bv_int + dict_Sail2_values_Bitvector_a op1 sign l (if r then( 1 :: int) else( 0 :: int)))" definition arith_op_bv_bit :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where - " arith_op_bv_bit dict_Sail_values_Bitvector_a op1 sign l r = ( map_option (arith_op_bv_bool - dict_Sail_values_Bitvector_a op1 sign l) (bool_of_bitU r))" + " arith_op_bv_bit dict_Sail2_values_Bitvector_a op1 sign l r = ( map_option (arith_op_bv_bool + dict_Sail2_values_Bitvector_a op1 sign l) (bool_of_bitU r))" (* TODO (or just omit and define it per spec if needed) @@ -163,8 +163,8 @@ definition invert_shift :: " shift \<Rightarrow> shift " where (*val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> list bitU*) definition shift_op_bv :: " 'a Bitvector_class \<Rightarrow> shift \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where - " shift_op_bv dict_Sail_values_Bitvector_a op1 v n = ( - (let v = ((bits_of_method dict_Sail_values_Bitvector_a) v) in + " shift_op_bv dict_Sail2_values_Bitvector_a op1 v n = ( + (let v = ((bits_of_method dict_Sail2_values_Bitvector_a) v) in if n =( 0 :: int) then v else (let (op1, n) = (if n >( 0 :: int) then (op1, n) else (invert_shift op1, - n)) in (case op1 of @@ -174,8 +174,8 @@ definition shift_op_bv :: " 'a Bitvector_class \<Rightarrow> shift \<Rightarrow repeat [B0] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int)) | RR_shift_arith => repeat [most_significant - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) v] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int)) + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) v] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int)) | LL_rot => subrange_list True v n (int (List.length v) -( 1 :: int)) @ subrange_list True v(( 0 :: int)) (n -( 1 :: int)) | RR_rot => @@ -184,24 +184,24 @@ definition shift_op_bv :: " 'a Bitvector_class \<Rightarrow> shift \<Rightarrow definition shiftl_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where - " shiftl_bv dict_Sail_values_Bitvector_a = ( shift_op_bv - dict_Sail_values_Bitvector_a LL_shift )" + " shiftl_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv + dict_Sail2_values_Bitvector_a LL_shift )" (*<<*) definition shiftr_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where - " shiftr_bv dict_Sail_values_Bitvector_a = ( shift_op_bv - dict_Sail_values_Bitvector_a RR_shift )" + " shiftr_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv + dict_Sail2_values_Bitvector_a RR_shift )" (*>>*) definition arith_shiftr_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where - " arith_shiftr_bv dict_Sail_values_Bitvector_a = ( shift_op_bv - dict_Sail_values_Bitvector_a RR_shift_arith )" + " arith_shiftr_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv + dict_Sail2_values_Bitvector_a RR_shift_arith )" definition rotl_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where - " rotl_bv dict_Sail_values_Bitvector_a = ( shift_op_bv - dict_Sail_values_Bitvector_a LL_rot )" + " rotl_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv + dict_Sail2_values_Bitvector_a LL_rot )" (*<<<*) definition rotr_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where - " rotr_bv dict_Sail_values_Bitvector_a = ( shift_op_bv - dict_Sail_values_Bitvector_a LL_rot )" + " rotr_bv dict_Sail2_values_Bitvector_a = ( shift_op_bv + dict_Sail2_values_Bitvector_a LL_rot )" (*>>>*) definition shiftl_mword :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where @@ -230,26 +230,26 @@ fun arith_op_no0 :: "(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> in (*val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b => (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> maybe 'b*) definition arith_op_bv_no0 :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'b option " where - " arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op1 sign size1 l r = ( + " arith_op_bv_no0 dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op1 sign size1 l r = ( Option.bind (int_of_bv - dict_Sail_values_Bitvector_a sign l) (\<lambda> l' . + dict_Sail2_values_Bitvector_a sign l) (\<lambda> l' . Option.bind (int_of_bv - dict_Sail_values_Bitvector_a sign r) (\<lambda> r' . + dict_Sail2_values_Bitvector_a sign r) (\<lambda> r' . if r' =( 0 :: int) then None else Some ( - (of_int_method dict_Sail_values_Bitvector_b) ((length_method dict_Sail_values_Bitvector_a) l * size1) (op1 l' r')))))" + (of_int_method dict_Sail2_values_Bitvector_b) ((length_method dict_Sail2_values_Bitvector_a) l * size1) (op1 l' r')))))" definition mod_bv :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option " where - " mod_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_no0 - dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod False(( 1 :: int)))" + " mod_bv dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_no0 + dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_mod False(( 1 :: int)))" definition quot_bv :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option " where - " quot_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_no0 - dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot False(( 1 :: int)))" + " quot_bv dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_no0 + dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot False(( 1 :: int)))" definition quots_bv :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option " where - " quots_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_no0 - dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot True(( 1 :: int)))" + " quots_bv dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_no0 + dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot True(( 1 :: int)))" definition mod_mword :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where @@ -263,17 +263,17 @@ definition quots_mword :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \ definition arith_op_bv_int_no0 :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b option " where - " arith_op_bv_int_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op1 sign size1 l r = ( - arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op1 sign size1 l ((of_int_method dict_Sail_values_Bitvector_a) ((length_method dict_Sail_values_Bitvector_a) l) r))" + " arith_op_bv_int_no0 dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op1 sign size1 l r = ( + arith_op_bv_no0 dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b op1 sign size1 l ((of_int_method dict_Sail2_values_Bitvector_a) ((length_method dict_Sail2_values_Bitvector_a) l) r))" definition quot_bv_int :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> 'a option " where - " quot_bv_int dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_int_no0 - dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot False(( 1 :: int)))" + " quot_bv_int dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_int_no0 + dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_quot False(( 1 :: int)))" definition mod_bv_int :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> 'a option " where - " mod_bv_int dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_int_no0 - dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod False(( 1 :: int)))" + " mod_bv_int dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b = ( arith_op_bv_int_no0 + dict_Sail2_values_Bitvector_b dict_Sail2_values_Bitvector_a hardware_mod False(( 1 :: int)))" definition mod_mword_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where @@ -287,40 +287,40 @@ definition quots_mword_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarro definition replicate_bits_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where - " replicate_bits_bv dict_Sail_values_Bitvector_a v count1 = ( repeat ( - (bits_of_method dict_Sail_values_Bitvector_a) v) count1 )" + " replicate_bits_bv dict_Sail2_values_Bitvector_a v count1 = ( repeat ( + (bits_of_method dict_Sail2_values_Bitvector_a) v) count1 )" definition duplicate_bit_bv :: " 'a BitU_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where - " duplicate_bit_bv dict_Sail_values_BitU_a bit len = ( replicate_bits_bv - (instance_Sail_values_Bitvector_list_dict dict_Sail_values_BitU_a) [bit] len )" + " duplicate_bit_bv dict_Sail2_values_BitU_a bit len = ( replicate_bits_bv + (instance_Sail2_values_Bitvector_list_dict dict_Sail2_values_BitU_a) [bit] len )" (*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) definition eq_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> bool " where - " eq_bv dict_Sail_values_Bitvector_a l r = ( ( - (bits_of_method dict_Sail_values_Bitvector_a) l =(bits_of_method dict_Sail_values_Bitvector_a) r))" + " eq_bv dict_Sail2_values_Bitvector_a l r = ( ( + (bits_of_method dict_Sail2_values_Bitvector_a) l =(bits_of_method dict_Sail2_values_Bitvector_a) r))" (*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) definition neq_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> bool " where - " neq_bv dict_Sail_values_Bitvector_a l r = ( \<not> (eq_bv - dict_Sail_values_Bitvector_a l r))" + " neq_bv dict_Sail2_values_Bitvector_a l r = ( \<not> (eq_bv + dict_Sail2_values_Bitvector_a l r))" (*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*) definition get_slice_int_bv :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a " where - " get_slice_int_bv dict_Sail_values_Bitvector_a len n lo = ( + " get_slice_int_bv dict_Sail2_values_Bitvector_a len n lo = ( (let hi = ((lo + len) -( 1 :: int)) in (let bs = (bools_of_int (hi +( 1 :: int)) n) in - (of_bools_method dict_Sail_values_Bitvector_a) (subrange_list False bs hi lo))))" + (of_bools_method dict_Sail2_values_Bitvector_a) (subrange_list False bs hi lo))))" (*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer*) definition set_slice_int_bv :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> int " where - " set_slice_int_bv dict_Sail_values_Bitvector_a len n lo v = ( + " set_slice_int_bv dict_Sail2_values_Bitvector_a len n lo v = ( (let hi = ((lo + len) -( 1 :: int)) in (let bs = (bits_of_int (hi +( 1 :: int)) n) in maybe_failwith (signed_of_bits (update_subrange_list False bs hi lo ( - (bits_of_method dict_Sail_values_Bitvector_a) v))))))" + (bits_of_method dict_Sail2_values_Bitvector_a) v))))))" end diff --git a/snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy b/snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy index d3d886ed..96c38a6a 100644 --- a/snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy +++ b/snapshots/isabelle/lib/sail/Sail2_operators_bitlists.thy @@ -1,24 +1,24 @@ -chapter \<open>Generated by Lem from ../../src/gen_lib/sail_operators_bitlists.lem.\<close> +chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_operators_bitlists.lem.\<close> -theory "Sail_operators_bitlists" +theory "Sail2_operators_bitlists" imports Main "Lem_pervasives_extra" "Lem_machine_word" - "Sail_values" - "Sail_operators" - "Prompt_monad" - "Prompt" + "Sail2_values" + "Sail2_operators" + "Sail2_prompt_monad" + "Sail2_prompt" begin (*open import Pervasives_extra*) (*open import Machine_word*) -(*open import Sail_values*) -(*open import Sail_operators*) -(*open import Prompt_monad*) -(*open import Prompt*) +(*open import Sail2_values*) +(*open import Sail2_operators*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) (* Specialisation of operators to bit lists *) @@ -27,12 +27,12 @@ definition uint_maybe :: "(bitU)list \<Rightarrow>(int)option " where " uint_maybe v = ( unsigned_of_bits (List.map (\<lambda> b. b) v))" definition uint_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('c,(int),'b)monad " where - " uint_fail dict_Sail_values_Bitvector_a v = ( maybe_fail (''uint'') ( - (unsigned_method dict_Sail_values_Bitvector_a) v))" + " uint_fail dict_Sail2_values_Bitvector_a v = ( maybe_fail (''uint'') ( + (unsigned_method dict_Sail2_values_Bitvector_a) v))" -definition uint_oracle :: "(bitU)list \<Rightarrow>('b,(int),'a)monad " where - " uint_oracle v = ( - bools_of_bits_oracle v \<bind> (\<lambda> bs . +definition uint_nondet :: "(bitU)list \<Rightarrow>('b,(int),'a)monad " where + " uint_nondet v = ( + bools_of_bits_nondet v \<bind> (\<lambda> bs . return (int_of_bools False bs)))" definition uint :: "(bitU)list \<Rightarrow> int " where @@ -44,12 +44,12 @@ definition sint_maybe :: "(bitU)list \<Rightarrow>(int)option " where " sint_maybe v = ( signed_of_bits (List.map (\<lambda> b. b) v))" definition sint_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('c,(int),'b)monad " where - " sint_fail dict_Sail_values_Bitvector_a v = ( maybe_fail (''sint'') ( - (signed_method dict_Sail_values_Bitvector_a) v))" + " sint_fail dict_Sail2_values_Bitvector_a v = ( maybe_fail (''sint'') ( + (signed_method dict_Sail2_values_Bitvector_a) v))" -definition sint_oracle :: "(bitU)list \<Rightarrow>('b,(int),'a)monad " where - " sint_oracle v = ( - bools_of_bits_oracle v \<bind> (\<lambda> bs . +definition sint_nondet :: "(bitU)list \<Rightarrow>('b,(int),'a)monad " where + " sint_nondet v = ( + bools_of_bits_nondet v \<bind> (\<lambda> bs . return (int_of_bools True bs)))" definition sint :: "(bitU)list \<Rightarrow> int " where @@ -60,16 +60,16 @@ definition sint :: "(bitU)list \<Rightarrow> int " where definition extz_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where " extz_vec = ( extz_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val exts_vec : integer -> list bitU -> list bitU*) definition exts_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where " exts_vec = ( exts_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val zero_extend : list bitU -> integer -> list bitU*) @@ -90,13 +90,13 @@ definition zeros :: " int \<Rightarrow>(bitU)list " where (*val vector_truncate : list bitU -> integer -> list bitU*) definition vector_truncate :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where " vector_truncate bs len = ( extz_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) len bs )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) len bs )" (*val vec_of_bits_maybe : list bitU -> maybe (list bitU)*) (*val vec_of_bits_fail : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) -(*val vec_of_bits_oracle : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) +(*val vec_of_bits_nondet : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) (*val vec_of_bits_failwith : list bitU -> list bitU*) (*val vec_of_bits : list bitU -> list bitU*) @@ -104,24 +104,24 @@ definition vector_truncate :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU) definition access_vec_inc :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU " where " access_vec_inc = ( access_bv_inc - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val access_vec_dec : list bitU -> integer -> bitU*) definition access_vec_dec :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU " where " access_vec_dec = ( access_bv_dec - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val update_vec_inc : list bitU -> integer -> bitU -> list bitU*) definition update_vec_inc :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where " update_vec_inc = ( update_bv_inc - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" definition update_vec_inc_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option " where " update_vec_inc_maybe v i b = ( Some (update_vec_inc v i b))" @@ -129,16 +129,16 @@ definition update_vec_inc_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow> definition update_vec_inc_fail :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where " update_vec_inc_fail v i b = ( return (update_vec_inc v i b))" -definition update_vec_inc_oracle :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where - " update_vec_inc_oracle v i b = ( return (update_vec_inc v i b))" +definition update_vec_inc_nondet :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where + " update_vec_inc_nondet v i b = ( return (update_vec_inc v i b))" (*val update_vec_dec : list bitU -> integer -> bitU -> list bitU*) definition update_vec_dec :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where " update_vec_dec = ( update_bv_dec - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" definition update_vec_dec_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option " where " update_vec_dec_maybe v i b = ( Some (update_vec_dec v i b))" @@ -146,62 +146,62 @@ definition update_vec_dec_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow> definition update_vec_dec_fail :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where " update_vec_dec_fail v i b = ( return (update_vec_dec v i b))" -definition update_vec_dec_oracle :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where - " update_vec_dec_oracle v i b = ( return (update_vec_dec v i b))" +definition update_vec_dec_nondet :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where + " update_vec_dec_nondet v i b = ( return (update_vec_dec v i b))" (*val subrange_vec_inc : list bitU -> integer -> integer -> list bitU*) definition subrange_vec_inc :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where " subrange_vec_inc = ( subrange_bv_inc - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val subrange_vec_dec : list bitU -> integer -> integer -> list bitU*) definition subrange_vec_dec :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where " subrange_vec_dec = ( subrange_bv_dec - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU*) definition update_subrange_vec_inc :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where " update_subrange_vec_inc = ( update_subrange_bv_inc - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU*) definition update_subrange_vec_dec :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where " update_subrange_vec_dec = ( update_subrange_bv_dec - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val concat_vec : list bitU -> list bitU -> list bitU*) definition concat_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where " concat_vec = ( concat_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val cons_vec : bitU -> list bitU -> list bitU*) definition cons_vec :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where " cons_vec = ( cons_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" definition cons_vec_maybe :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option " where " cons_vec_maybe b v = ( Some (cons_vec b v))" @@ -209,8 +209,8 @@ definition cons_vec_maybe :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>((bitU definition cons_vec_fail :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>('b,((bitU)list),'a)monad " where " cons_vec_fail b v = ( return (cons_vec b v))" -definition cons_vec_oracle :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>('b,((bitU)list),'a)monad " where - " cons_vec_oracle b v = ( return (cons_vec b v))" +definition cons_vec_nondet :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>('b,((bitU)list),'a)monad " where + " cons_vec_nondet b v = ( return (cons_vec b v))" (*val cast_unit_vec : bitU -> list bitU*) @@ -223,8 +223,8 @@ definition cast_unit_vec_maybe :: " bitU \<Rightarrow>((bitU)list)option " whe definition cast_unit_vec_fail :: " bitU \<Rightarrow>('b,((bitU)list),'a)monad " where " cast_unit_vec_fail b = ( return (cast_unit_vec b))" -definition cast_unit_vec_oracle :: " bitU \<Rightarrow>('b,((bitU)list),'a)monad " where - " cast_unit_vec_oracle b = ( return (cast_unit_vec b))" +definition cast_unit_vec_nondet :: " bitU \<Rightarrow>('b,((bitU)list),'a)monad " where + " cast_unit_vec_nondet b = ( return (cast_unit_vec b))" (*val vec_of_bit : integer -> bitU -> list bitU*) @@ -237,41 +237,41 @@ definition vec_of_bit_maybe :: " int \<Rightarrow> bitU \<Rightarrow>((bitU)lis definition vec_of_bit_fail :: " int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where " vec_of_bit_fail len b = ( return (vec_of_bit len b))" -definition vec_of_bit_oracle :: " int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where - " vec_of_bit_oracle len b = ( return (vec_of_bit len b))" +definition vec_of_bit_nondet :: " int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where + " vec_of_bit_nondet len b = ( return (vec_of_bit len b))" (*val msb : list bitU -> bitU*) definition msb :: "(bitU)list \<Rightarrow> bitU " where " msb = ( most_significant - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val int_of_vec_maybe : bool -> list bitU -> maybe integer*) definition int_of_vec_maybe :: " bool \<Rightarrow>(bitU)list \<Rightarrow>(int)option " where " int_of_vec_maybe = ( int_of_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" definition int_of_vec_fail :: " bool \<Rightarrow>(bitU)list \<Rightarrow>('b,(int),'a)monad " where " int_of_vec_fail sign v = ( maybe_fail (''int_of_vec'') (int_of_vec_maybe sign v))" -definition int_of_vec_oracle :: " bool \<Rightarrow>(bitU)list \<Rightarrow>('b,(int),'a)monad " where - " int_of_vec_oracle sign v = ( bools_of_bits_oracle v \<bind> (\<lambda> v . return (int_of_bools sign v)))" +definition int_of_vec_nondet :: " bool \<Rightarrow>(bitU)list \<Rightarrow>('b,(int),'a)monad " where + " int_of_vec_nondet sign v = ( bools_of_bits_nondet v \<bind> (\<lambda> v . return (int_of_bools sign v)))" definition int_of_vec :: " bool \<Rightarrow>(bitU)list \<Rightarrow> int " where " int_of_vec sign v = ( maybe_failwith (int_of_vec_maybe sign v))" -(*val string_of_vec : list bitU -> string*) -definition string_of_vec :: "(bitU)list \<Rightarrow> string " where - " string_of_vec = ( +(*val string_of_bits : list bitU -> string*) +definition string_of_bits :: "(bitU)list \<Rightarrow> string " where + " string_of_bits = ( string_of_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val and_vec : list bitU -> list bitU -> list bitU*) @@ -294,13 +294,13 @@ definition not_vec :: "(bitU)list \<Rightarrow>(bitU)list " where (*val arith_op_double_bl : forall 'a 'b. Bitvector 'a => (integer -> integer -> integer) -> bool -> 'a -> 'a -> list bitU*) definition arith_op_double_bl :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow>(bitU)list " where - " arith_op_double_bl dict_Sail_values_Bitvector_a op1 sign l r = ( + " arith_op_double_bl dict_Sail2_values_Bitvector_a op1 sign l r = ( (let len =(( 2 :: int) * - (length_method dict_Sail_values_Bitvector_a) l) in + (length_method dict_Sail2_values_Bitvector_a) l) in (let l' = (if sign then exts_bv - dict_Sail_values_Bitvector_a len l else extz_bv dict_Sail_values_Bitvector_a len l) in + dict_Sail2_values_Bitvector_a len l else extz_bv dict_Sail2_values_Bitvector_a len l) in (let r' = (if sign then exts_bv - dict_Sail_values_Bitvector_a len r else extz_bv dict_Sail_values_Bitvector_a len r) in + dict_Sail2_values_Bitvector_a len r else extz_bv dict_Sail2_values_Bitvector_a len r) in List.map (\<lambda> b. b) (arith_op_bits op1 sign (List.map (\<lambda> b. b) l') (List.map (\<lambda> b. b) r'))))))" @@ -324,87 +324,51 @@ definition subs_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)l definition mult_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where " mult_vec = ( arith_op_double_bl - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) False )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) False )" definition mults_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where " mults_vec = ( arith_op_double_bl - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) True )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) True )" -(*val add_vec_int : list bitU -> integer -> list bitU*) -(*val adds_vec_int : list bitU -> integer -> list bitU*) -(*val sub_vec_int : list bitU -> integer -> list bitU*) -(*val subs_vec_int : list bitU -> integer -> list bitU*) -(*val mult_vec_int : list bitU -> integer -> list bitU*) -(*val mults_vec_int : list bitU -> integer -> list bitU*) +(*val add_vec_int : list bitU -> integer -> list bitU*) +(*val sub_vec_int : list bitU -> integer -> list bitU*) +(*val mult_vec_int : list bitU -> integer -> list bitU*) definition add_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where - " add_vec_int l r = ( arith_op_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) False l r )" - -definition adds_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where - " adds_vec_int l r = ( arith_op_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) True l r )" + " add_vec_int l r = ( arith_op_bv_int + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op+) True l r )" definition sub_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where - " sub_vec_int l r = ( arith_op_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) False l r )" - -definition subs_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where - " subs_vec_int l r = ( arith_op_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) True l r )" + " sub_vec_int l r = ( arith_op_bv_int + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op-) True l r )" definition mult_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where - " mult_vec_int l r = ( arith_op_double_bl - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) False l (List.map (\<lambda> b. b) (bits_of_int (int (List.length l)) r)))" - -definition mults_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where - " mults_vec_int l r = ( arith_op_double_bl - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) True l (List.map (\<lambda> b. b) (bits_of_int (int (List.length l)) r)))" - - -(*val add_int_vec : integer -> list bitU -> list bitU*) -(*val adds_int_vec : integer -> list bitU -> list bitU*) -(*val sub_int_vec : integer -> list bitU -> list bitU*) -(*val subs_int_vec : integer -> list bitU -> list bitU*) -(*val mult_int_vec : integer -> list bitU -> list bitU*) -(*val mults_int_vec : integer -> list bitU -> list bitU*) -definition add_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where - " add_int_vec l r = ( arith_op_int_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) False l r )" + " mult_vec_int l r = ( arith_op_double_bl + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) True l (List.map (\<lambda> b. b) (bits_of_int (int (List.length l)) r)))" -definition adds_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where - " adds_int_vec l r = ( arith_op_int_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) True l r )" -definition sub_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where - " sub_int_vec l r = ( arith_op_int_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) False l r )" +(*val add_int_vec : integer -> list bitU -> list bitU*) +(*val sub_int_vec : integer -> list bitU -> list bitU*) +(*val mult_int_vec : integer -> list bitU -> list bitU*) +definition add_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " add_int_vec l r = ( arith_op_int_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op+) True l r )" -definition subs_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where - " subs_int_vec l r = ( arith_op_int_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) True l r )" +definition sub_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " sub_int_vec l r = ( arith_op_int_bv + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op-) True l r )" definition mult_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where - " mult_int_vec l r = ( arith_op_double_bl - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) False (List.map (\<lambda> b. b) (bits_of_int (int (List.length r)) l)) r )" - -definition mults_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where - " mults_int_vec l r = ( arith_op_double_bl - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) True (List.map (\<lambda> b. b) (bits_of_int (int (List.length r)) l)) r )" + " mult_int_vec l r = ( arith_op_double_bl + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (op*) True (List.map (\<lambda> b. b) (bits_of_int (int (List.length r)) l)) r )" (*val add_vec_bit : list bitU -> bitU -> list bitU*) @@ -413,91 +377,91 @@ definition mults_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)li (*val subs_vec_bit : list bitU -> bitU -> list bitU*) definition add_vec_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where - " add_vec_bool dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bool - dict_Sail_values_Bitvector_a (op+) False l r )" + " add_vec_bool dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bool + dict_Sail2_values_Bitvector_a (op+) False l r )" definition add_vec_bit_maybe :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where - " add_vec_bit_maybe dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bit - dict_Sail_values_Bitvector_a (op+) False l r )" + " add_vec_bit_maybe dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bit + dict_Sail2_values_Bitvector_a (op+) False l r )" definition add_vec_bit_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where - " add_vec_bit_fail dict_Sail_values_Bitvector_a l r = ( maybe_fail (''add_vec_bit'') (add_vec_bit_maybe - dict_Sail_values_Bitvector_a l r))" + " add_vec_bit_fail dict_Sail2_values_Bitvector_a l r = ( maybe_fail (''add_vec_bit'') (add_vec_bit_maybe + dict_Sail2_values_Bitvector_a l r))" -definition add_vec_bit_oracle :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where - " add_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (add_vec_bool - dict_Sail_values_Bitvector_a l r)))" +definition add_vec_bit_nondet :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where + " add_vec_bit_nondet dict_Sail2_values_Bitvector_a l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (add_vec_bool + dict_Sail2_values_Bitvector_a l r)))" definition add_vec_bit :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list " where " add_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (add_vec_bit_maybe - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" definition adds_vec_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where - " adds_vec_bool dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bool - dict_Sail_values_Bitvector_a (op+) True l r )" + " adds_vec_bool dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bool + dict_Sail2_values_Bitvector_a (op+) True l r )" definition adds_vec_bit_maybe :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where - " adds_vec_bit_maybe dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bit - dict_Sail_values_Bitvector_a (op+) True l r )" + " adds_vec_bit_maybe dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bit + dict_Sail2_values_Bitvector_a (op+) True l r )" definition adds_vec_bit_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where - " adds_vec_bit_fail dict_Sail_values_Bitvector_a l r = ( maybe_fail (''adds_vec_bit'') (adds_vec_bit_maybe - dict_Sail_values_Bitvector_a l r))" + " adds_vec_bit_fail dict_Sail2_values_Bitvector_a l r = ( maybe_fail (''adds_vec_bit'') (adds_vec_bit_maybe + dict_Sail2_values_Bitvector_a l r))" -definition adds_vec_bit_oracle :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where - " adds_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (adds_vec_bool - dict_Sail_values_Bitvector_a l r)))" +definition adds_vec_bit_nondet :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where + " adds_vec_bit_nondet dict_Sail2_values_Bitvector_a l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (adds_vec_bool + dict_Sail2_values_Bitvector_a l r)))" definition adds_vec_bit :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list " where " adds_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (adds_vec_bit_maybe - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" definition sub_vec_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where - " sub_vec_bool dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bool - dict_Sail_values_Bitvector_a (op-) False l r )" + " sub_vec_bool dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bool + dict_Sail2_values_Bitvector_a (op-) False l r )" definition sub_vec_bit_maybe :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where - " sub_vec_bit_maybe dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bit - dict_Sail_values_Bitvector_a (op-) False l r )" + " sub_vec_bit_maybe dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bit + dict_Sail2_values_Bitvector_a (op-) False l r )" definition sub_vec_bit_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where - " sub_vec_bit_fail dict_Sail_values_Bitvector_a l r = ( maybe_fail (''sub_vec_bit'') (sub_vec_bit_maybe - dict_Sail_values_Bitvector_a l r))" + " sub_vec_bit_fail dict_Sail2_values_Bitvector_a l r = ( maybe_fail (''sub_vec_bit'') (sub_vec_bit_maybe + dict_Sail2_values_Bitvector_a l r))" -definition sub_vec_bit_oracle :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where - " sub_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (sub_vec_bool - dict_Sail_values_Bitvector_a l r)))" +definition sub_vec_bit_nondet :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where + " sub_vec_bit_nondet dict_Sail2_values_Bitvector_a l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (sub_vec_bool + dict_Sail2_values_Bitvector_a l r)))" definition sub_vec_bit :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list " where " sub_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (sub_vec_bit_maybe - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" definition subs_vec_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where - " subs_vec_bool dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bool - dict_Sail_values_Bitvector_a (op-) True l r )" + " subs_vec_bool dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bool + dict_Sail2_values_Bitvector_a (op-) True l r )" definition subs_vec_bit_maybe :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where - " subs_vec_bit_maybe dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bit - dict_Sail_values_Bitvector_a (op-) True l r )" + " subs_vec_bit_maybe dict_Sail2_values_Bitvector_a l r = ( arith_op_bv_bit + dict_Sail2_values_Bitvector_a (op-) True l r )" definition subs_vec_bit_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where - " subs_vec_bit_fail dict_Sail_values_Bitvector_a l r = ( maybe_fail (''sub_vec_bit'') (subs_vec_bit_maybe - dict_Sail_values_Bitvector_a l r))" + " subs_vec_bit_fail dict_Sail2_values_Bitvector_a l r = ( maybe_fail (''sub_vec_bit'') (subs_vec_bit_maybe + dict_Sail2_values_Bitvector_a l r))" -definition subs_vec_bit_oracle :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where - " subs_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (subs_vec_bool - dict_Sail_values_Bitvector_a l r)))" +definition subs_vec_bit_nondet :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where + " subs_vec_bit_nondet dict_Sail2_values_Bitvector_a l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (subs_vec_bool + dict_Sail2_values_Bitvector_a l r)))" definition subs_vec_bit :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list " where " subs_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (subs_vec_bit_maybe - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" (*val add_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) @@ -530,186 +494,186 @@ let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*) definition shiftl :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where " shiftl = ( shiftl_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" definition shiftr :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where " shiftr = ( shiftr_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" definition arith_shiftr :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where " arith_shiftr = ( arith_shiftr_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" definition rotl :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where " rotl = ( rotl_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" definition rotr :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where " rotr = ( rotr_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val mod_vec : list bitU -> list bitU -> list bitU*) (*val mod_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) (*val mod_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) -(*val mod_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val mod_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) definition mod_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where " mod_vec l r = ( case_option (repeat [BU] (int (List.length l))) id (mod_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" definition mod_vec_maybe :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option " where " mod_vec_maybe l r = ( mod_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )" definition mod_vec_fail :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where " mod_vec_fail l r = ( maybe_fail (''mod_vec'') (mod_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" -definition mod_vec_oracle :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where - " mod_vec_oracle l r = ( of_bits_oracle - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec l r))" +definition mod_vec_nondet :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where + " mod_vec_nondet l r = ( of_bits_nondet + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (mod_vec l r))" (*val quot_vec : list bitU -> list bitU -> list bitU*) (*val quot_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) (*val quot_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) -(*val quot_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val quot_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) definition quot_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where " quot_vec l r = ( case_option (repeat [BU] (int (List.length l))) id (quot_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" definition quot_vec_maybe :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option " where " quot_vec_maybe l r = ( quot_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )" definition quot_vec_fail :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where " quot_vec_fail l r = ( maybe_fail (''quot_vec'') (quot_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" -definition quot_vec_oracle :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where - " quot_vec_oracle l r = ( of_bits_oracle - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec l r))" +definition quot_vec_nondet :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where + " quot_vec_nondet l r = ( of_bits_nondet + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quot_vec l r))" (*val quots_vec : list bitU -> list bitU -> list bitU*) (*val quots_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) (*val quots_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) -(*val quots_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val quots_vec_nondet : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) definition quots_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where " quots_vec l r = ( case_option (repeat [BU] (int (List.length l))) id (quots_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" definition quots_vec_maybe :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option " where " quots_vec_maybe l r = ( quots_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )" definition quots_vec_fail :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where " quots_vec_fail l r = ( maybe_fail (''quots_vec'') (quots_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" -definition quots_vec_oracle :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where - " quots_vec_oracle l r = ( of_bits_oracle - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (quots_vec l r))" +definition quots_vec_nondet :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where + " quots_vec_nondet l r = ( of_bits_nondet + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quots_vec l r))" (*val mod_vec_int : list bitU -> integer -> list bitU*) (*val mod_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*) (*val mod_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) -(*val mod_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +(*val mod_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) definition mod_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where " mod_vec_int l r = ( case_option (repeat [BU] (int (List.length l))) id (mod_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" definition mod_vec_int_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow>((bitU)list)option " where " mod_vec_int_maybe l r = ( mod_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )" definition mod_vec_int_fail :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where " mod_vec_int_fail l r = ( maybe_fail (''mod_vec_int'') (mod_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" -definition mod_vec_int_oracle :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where - " mod_vec_int_oracle l r = ( of_bits_oracle - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec_int l r))" +definition mod_vec_int_nondet :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where + " mod_vec_int_nondet l r = ( of_bits_nondet + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (mod_vec_int l r))" (*val quot_vec_int : list bitU -> integer -> list bitU*) (*val quot_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*) (*val quot_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) -(*val quot_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +(*val quot_vec_int_nondet : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) definition quot_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where " quot_vec_int l r = ( case_option (repeat [BU] (int (List.length l))) id (quot_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" definition quot_vec_int_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow>((bitU)list)option " where " quot_vec_int_maybe l r = ( quot_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r )" definition quot_vec_int_fail :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where " quot_vec_int_fail l r = ( maybe_fail (''quot_vec_int'') (quot_bv_int - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) l r))" -definition quot_vec_int_oracle :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where - " quot_vec_int_oracle l r = ( of_bits_oracle - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec_int l r))" +definition quot_vec_int_nondet :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where + " quot_vec_int_nondet l r = ( of_bits_nondet + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) (quot_vec_int l r))" (*val replicate_bits : list bitU -> integer -> list bitU*) definition replicate_bits :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where " replicate_bits = ( replicate_bits_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val duplicate : bitU -> integer -> list bitU*) definition duplicate :: " bitU \<Rightarrow> int \<Rightarrow>(bitU)list " where " duplicate = ( - duplicate_bit_bv instance_Sail_values_BitU_Sail_values_bitU_dict )" + duplicate_bit_bv instance_Sail2_values_BitU_Sail2_values_bitU_dict )" definition duplicate_maybe :: " bitU \<Rightarrow> int \<Rightarrow>((bitU)list)option " where " duplicate_maybe b n = ( Some (duplicate b n))" @@ -717,9 +681,9 @@ definition duplicate_maybe :: " bitU \<Rightarrow> int \<Rightarrow>((bitU)list definition duplicate_fail :: " bitU \<Rightarrow> int \<Rightarrow>('b,((bitU)list),'a)monad " where " duplicate_fail b n = ( return (duplicate b n))" -definition duplicate_oracle :: " bitU \<Rightarrow> int \<Rightarrow>('b,((bitU)list),'a)monad " where - " duplicate_oracle b n = ( - bool_of_bitU_oracle b \<bind> (\<lambda> b . +definition duplicate_nondet :: " bitU \<Rightarrow> int \<Rightarrow>('b,((bitU)list),'a)monad " where + " duplicate_nondet b n = ( + bool_of_bitU_nondet b \<bind> (\<lambda> b . return (duplicate (bitU_of_bool b) n)))" @@ -732,16 +696,16 @@ definition reverse_endianness :: "(bitU)list \<Rightarrow>(bitU)list " where definition get_slice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where " get_slice_int = ( get_slice_int_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val set_slice_int : integer -> integer -> integer -> list bitU -> integer*) definition set_slice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow> int " where " set_slice_int = ( set_slice_int_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" (*val slice : list bitU -> integer -> integer -> list bitU*) @@ -761,13 +725,13 @@ definition set_slice :: " int \<Rightarrow> int \<Rightarrow>(bitU)list \<Right definition eq_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow> bool " where " eq_vec = ( eq_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" definition neq_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow> bool " where " neq_vec = ( neq_bv - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) )" + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) )" end diff --git a/snapshots/isabelle/lib/sail/Sail_operators_mwords.thy b/snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy index edaec4e3..c6d1a865 100644 --- a/snapshots/isabelle/lib/sail/Sail_operators_mwords.thy +++ b/snapshots/isabelle/lib/sail/Sail2_operators_mwords.thy @@ -1,32 +1,32 @@ -chapter \<open>Generated by Lem from ../../src/gen_lib/sail_operators_mwords.lem.\<close> +chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_operators_mwords.lem.\<close> -theory "Sail_operators_mwords" +theory "Sail2_operators_mwords" imports Main "Lem_pervasives_extra" "Lem_machine_word" - "Sail_values" - "Sail_operators" - "Prompt_monad" - "Prompt" + "Sail2_values" + "Sail2_operators" + "Sail2_prompt_monad" + "Sail2_prompt" begin (*open import Pervasives_extra*) (*open import Machine_word*) -(*open import Sail_values*) -(*open import Sail_operators*) -(*open import Prompt_monad*) -(*open import Prompt*) +(*open import Sail2_values*) +(*open import Sail2_operators*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) definition uint_maybe :: "('a::len)Word.word \<Rightarrow>(int)option " where " uint_maybe v = ( Some (Word.uint v))" definition uint_fail :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where " uint_fail v = ( return (Word.uint v))" -definition uint_oracle :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where - " uint_oracle v = ( return (Word.uint v))" +definition uint_nondet :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where + " uint_nondet v = ( return (Word.uint v))" definition sint_maybe :: "('a::len)Word.word \<Rightarrow>(int)option " where " sint_maybe v = ( Some (Word.sint v))" @@ -34,13 +34,13 @@ definition sint_maybe :: "('a::len)Word.word \<Rightarrow>(int)option " where definition sint_fail :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where " sint_fail v = ( return (Word.sint v))" -definition sint_oracle :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where - " sint_oracle v = ( return (Word.sint v))" +definition sint_nondet :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where + " sint_nondet v = ( return (Word.sint v))" (*val vec_of_bits_maybe : forall 'a. Size 'a => list bitU -> maybe (mword 'a)*) (*val vec_of_bits_fail : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*) -(*val vec_of_bits_oracle : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*) +(*val vec_of_bits_nondet : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*) (*val vec_of_bits_failwith : forall 'a. Size 'a => list bitU -> mword 'a*) (*val vec_of_bits : forall 'a. Size 'a => list bitU -> mword 'a*) definition vec_of_bits_maybe :: "(bitU)list \<Rightarrow>(('a::len)Word.word)option " where @@ -48,31 +48,31 @@ definition vec_of_bits_maybe :: "(bitU)list \<Rightarrow>(('a::len)Word.word)op definition vec_of_bits_fail :: "(bitU)list \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where " vec_of_bits_fail bits = ( of_bits_fail - instance_Sail_values_Bitvector_Machine_word_mword_dict bits )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict bits )" -definition vec_of_bits_oracle :: "(bitU)list \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where - " vec_of_bits_oracle bits = ( of_bits_oracle - instance_Sail_values_Bitvector_Machine_word_mword_dict bits )" +definition vec_of_bits_nondet :: "(bitU)list \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " vec_of_bits_nondet bits = ( of_bits_nondet + instance_Sail2_values_Bitvector_Machine_word_mword_dict bits )" definition vec_of_bits_failwith :: "(bitU)list \<Rightarrow>('a::len)Word.word " where " vec_of_bits_failwith bits = ( of_bits_failwith - instance_Sail_values_Bitvector_Machine_word_mword_dict bits )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict bits )" definition vec_of_bits :: "(bitU)list \<Rightarrow>('a::len)Word.word " where " vec_of_bits bits = ( of_bits_failwith - instance_Sail_values_Bitvector_Machine_word_mword_dict bits )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict bits )" (*val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*) definition access_vec_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU " where " access_vec_inc = ( - access_bv_inc instance_Sail_values_Bitvector_Machine_word_mword_dict )" + access_bv_inc instance_Sail2_values_Bitvector_Machine_word_mword_dict )" (*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*) definition access_vec_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU " where " access_vec_dec = ( - access_bv_dec instance_Sail_values_Bitvector_Machine_word_mword_dict )" + access_bv_dec instance_Sail2_values_Bitvector_Machine_word_mword_dict )" definition update_vec_dec_maybe :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where @@ -83,9 +83,9 @@ definition update_vec_dec_fail :: "('a::len)Word.word \<Rightarrow> int \<Right bool_of_bitU_fail b \<bind> (\<lambda> b . return (update_mword_bool_dec w i b)))" -definition update_vec_dec_oracle :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where - " update_vec_dec_oracle w i b = ( - bool_of_bitU_oracle b \<bind> (\<lambda> b . +definition update_vec_dec_nondet :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " update_vec_dec_nondet w i b = ( + bool_of_bitU_nondet b \<bind> (\<lambda> b . return (update_mword_bool_dec w i b)))" definition update_vec_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where @@ -100,9 +100,9 @@ definition update_vec_inc_fail :: "('a::len)Word.word \<Rightarrow> int \<Right bool_of_bitU_fail b \<bind> (\<lambda> b . return (update_mword_bool_inc w i b)))" -definition update_vec_inc_oracle :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where - " update_vec_inc_oracle w i b = ( - bool_of_bitU_oracle b \<bind> (\<lambda> b . +definition update_vec_inc_nondet :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " update_vec_inc_nondet w i b = ( + bool_of_bitU_nondet b \<bind> (\<lambda> b . return (update_mword_bool_inc w i b)))" definition update_vec_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where @@ -174,8 +174,8 @@ definition cons_vec_maybe :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarro definition cons_vec_fail :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>('e,(('b::len)Word.word),'d)monad " where " cons_vec_fail b w = ( bool_of_bitU_fail b \<bind> (\<lambda> b . return (cons_vec_bool b w)))" -definition cons_vec_oracle :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>('e,(('b::len)Word.word),'d)monad " where - " cons_vec_oracle b w = ( bool_of_bitU_oracle b \<bind> (\<lambda> b . return (cons_vec_bool b w)))" +definition cons_vec_nondet :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>('e,(('b::len)Word.word),'d)monad " where + " cons_vec_nondet b w = ( bool_of_bitU_nondet b \<bind> (\<lambda> b . return (cons_vec_bool b w)))" definition cons_vec :: " bitU \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where " cons_vec b w = ( maybe_failwith (cons_vec_maybe b w))" @@ -191,8 +191,8 @@ definition vec_of_bit_maybe :: " int \<Rightarrow> bitU \<Rightarrow>(('a::len) definition vec_of_bit_fail :: " int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where " vec_of_bit_fail len b = ( bool_of_bitU_fail b \<bind> (\<lambda> b . return (vec_of_bool len b)))" -definition vec_of_bit_oracle :: " int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where - " vec_of_bit_oracle len b = ( bool_of_bitU_oracle b \<bind> (\<lambda> b . return (vec_of_bool len b)))" +definition vec_of_bit_nondet :: " int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " vec_of_bit_nondet len b = ( bool_of_bitU_nondet b \<bind> (\<lambda> b . return (vec_of_bool len b)))" definition vec_of_bit :: " int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where " vec_of_bit len b = ( maybe_failwith (vec_of_bit_maybe len b))" @@ -208,8 +208,8 @@ definition cast_unit_vec_maybe :: " bitU \<Rightarrow>(('a::len)Word.word)optio definition cast_unit_vec_fail :: " bitU \<Rightarrow>('b,((1)Word.word),'a)monad " where " cast_unit_vec_fail b = ( bool_of_bitU_fail b \<bind> (\<lambda> b . return (cast_bool_vec b)))" -definition cast_unit_vec_oracle :: " bitU \<Rightarrow>('b,((1)Word.word),'a)monad " where - " cast_unit_vec_oracle b = ( bool_of_bitU_oracle b \<bind> (\<lambda> b . return (cast_bool_vec b)))" +definition cast_unit_vec_nondet :: " bitU \<Rightarrow>('b,((1)Word.word),'a)monad " where + " cast_unit_vec_nondet b = ( bool_of_bitU_nondet b \<bind> (\<lambda> b . return (cast_bool_vec b)))" definition cast_unit_vec :: " bitU \<Rightarrow>('a::len)Word.word " where " cast_unit_vec b = ( maybe_failwith (cast_unit_vec_maybe b))" @@ -218,7 +218,7 @@ definition cast_unit_vec :: " bitU \<Rightarrow>('a::len)Word.word " where (*val msb : forall 'a. Size 'a => mword 'a -> bitU*) definition msb :: "('a::len)Word.word \<Rightarrow> bitU " where " msb = ( - most_significant instance_Sail_values_Bitvector_Machine_word_mword_dict )" + most_significant instance_Sail2_values_Bitvector_Machine_word_mword_dict )" (*val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer*) @@ -235,10 +235,10 @@ definition int_of_vec_fail :: " bool \<Rightarrow>('a::len)Word.word \<Rightarr " int_of_vec_fail sign w = ( return (int_of_vec sign w))" -(*val string_of_vec : forall 'a. Size 'a => mword 'a -> string*) -definition string_of_vec :: "('a::len)Word.word \<Rightarrow> string " where - " string_of_vec = ( - string_of_bv instance_Sail_values_Bitvector_Machine_word_mword_dict )" +(*val string_of_bits : forall 'a. Size 'a => mword 'a -> string*) +definition string_of_bits :: "('a::len)Word.word \<Rightarrow> string " where + " string_of_bits = ( + string_of_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict )" (*val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) @@ -283,66 +283,36 @@ definition mults_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<R " mults_vec l r = ( Word.word_of_int ((int_of_mword True (Word.scast l :: ( 'b::len)Word.word)) * (int_of_mword True (Word.scast r :: ( 'b::len)Word.word))))" -(*val add_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) -(*val adds_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) -(*val sub_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) -(*val subs_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) -(*val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) -(*val mults_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +(*val add_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val sub_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) definition add_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where - " add_vec_int l r = ( arith_op_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) False l r )" - -definition adds_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where - " adds_vec_int l r = ( arith_op_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) True l r )" + " add_vec_int l r = ( arith_op_bv_int + instance_Sail2_values_Bitvector_Machine_word_mword_dict (op+) True l r )" definition sub_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where - " sub_vec_int l r = ( arith_op_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) False l r )" - -definition subs_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where - " subs_vec_int l r = ( arith_op_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) True l r )" + " sub_vec_int l r = ( arith_op_bv_int + instance_Sail2_values_Bitvector_Machine_word_mword_dict (op-) True l r )" definition mult_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where - " mult_vec_int l r = ( arith_op_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict (op*) False (Word.ucast l :: ( 'b::len)Word.word) r )" - -definition mults_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where - " mults_vec_int l r = ( arith_op_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict (op*) True (Word.scast l :: ( 'b::len)Word.word) r )" + " mult_vec_int l r = ( arith_op_bv_int + instance_Sail2_values_Bitvector_Machine_word_mword_dict (op*) True (Word.scast l :: ( 'b::len)Word.word) r )" -(*val add_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) -(*val adds_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) -(*val sub_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) -(*val subs_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) -(*val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) -(*val mults_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) +(*val add_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val sub_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) definition add_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where - " add_int_vec l r = ( arith_op_int_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) False l r )" - -definition adds_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where - " adds_int_vec l r = ( arith_op_int_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) True l r )" + " add_int_vec l r = ( arith_op_int_bv + instance_Sail2_values_Bitvector_Machine_word_mword_dict (op+) True l r )" definition sub_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where - " sub_int_vec l r = ( arith_op_int_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) False l r )" - -definition subs_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where - " subs_int_vec l r = ( arith_op_int_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) True l r )" + " sub_int_vec l r = ( arith_op_int_bv + instance_Sail2_values_Bitvector_Machine_word_mword_dict (op-) True l r )" definition mult_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where - " mult_int_vec l r = ( arith_op_int_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict (op*) False l (Word.ucast r :: ( 'b::len)Word.word))" - -definition mults_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where - " mults_int_vec l r = ( arith_op_int_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict (op*) True l (Word.scast r :: ( 'b::len)Word.word))" + " mult_int_vec l r = ( arith_op_int_bv + instance_Sail2_values_Bitvector_Machine_word_mword_dict (op*) True l (Word.scast r :: ( 'b::len)Word.word))" (*val add_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) @@ -352,7 +322,7 @@ definition mults_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow> definition add_vec_bool :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where " add_vec_bool l r = ( arith_op_bv_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) False l r )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (op+) False l r )" definition add_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where " add_vec_bit_maybe l r = ( map_option (add_vec_bool l) (bool_of_bitU r))" @@ -360,8 +330,8 @@ definition add_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Righta definition add_vec_bit_fail :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where " add_vec_bit_fail l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r . return (add_vec_bool l r)))" -definition add_vec_bit_oracle :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where - " add_vec_bit_oracle l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (add_vec_bool l r)))" +definition add_vec_bit_nondet :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " add_vec_bit_nondet l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (add_vec_bool l r)))" definition add_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where " add_vec_bit l r = ( maybe_failwith (add_vec_bit_maybe l r))" @@ -369,7 +339,7 @@ definition add_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>( definition adds_vec_bool :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where " adds_vec_bool l r = ( arith_op_bv_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) True l r )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (op+) True l r )" definition adds_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where " adds_vec_bit_maybe l r = ( map_option (adds_vec_bool l) (bool_of_bitU r))" @@ -377,8 +347,8 @@ definition adds_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Right definition adds_vec_bit_fail :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where " adds_vec_bit_fail l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r . return (adds_vec_bool l r)))" -definition adds_vec_bit_oracle :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where - " adds_vec_bit_oracle l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (adds_vec_bool l r)))" +definition adds_vec_bit_nondet :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " adds_vec_bit_nondet l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (adds_vec_bool l r)))" definition adds_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where " adds_vec_bit l r = ( maybe_failwith (adds_vec_bit_maybe l r))" @@ -386,7 +356,7 @@ definition adds_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow> definition sub_vec_bool :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where " sub_vec_bool l r = ( arith_op_bv_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) False l r )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (op-) False l r )" definition sub_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where " sub_vec_bit_maybe l r = ( map_option (sub_vec_bool l) (bool_of_bitU r))" @@ -394,8 +364,8 @@ definition sub_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Righta definition sub_vec_bit_fail :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where " sub_vec_bit_fail l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r . return (sub_vec_bool l r)))" -definition sub_vec_bit_oracle :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where - " sub_vec_bit_oracle l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (sub_vec_bool l r)))" +definition sub_vec_bit_nondet :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " sub_vec_bit_nondet l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (sub_vec_bool l r)))" definition sub_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where " sub_vec_bit l r = ( maybe_failwith (sub_vec_bit_maybe l r))" @@ -403,7 +373,7 @@ definition sub_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>( definition subs_vec_bool :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where " subs_vec_bool l r = ( arith_op_bv_bool - instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) True l r )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict (op-) True l r )" definition subs_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where " subs_vec_bit_maybe l r = ( map_option (subs_vec_bool l) (bool_of_bitU r))" @@ -411,8 +381,8 @@ definition subs_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Right definition subs_vec_bit_fail :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where " subs_vec_bit_fail l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r . return (subs_vec_bool l r)))" -definition subs_vec_bit_oracle :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where - " subs_vec_bit_oracle l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (subs_vec_bool l r)))" +definition subs_vec_bit_nondet :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " subs_vec_bit_nondet l r = ( bool_of_bitU_nondet r \<bind> (\<lambda> r . return (subs_vec_bool l r)))" definition subs_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where " subs_vec_bit l r = ( maybe_failwith (subs_vec_bit_maybe l r))" @@ -469,116 +439,116 @@ definition rotr :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len) (*val mod_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) (*val mod_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) (*val mod_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) -(*val mod_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val mod_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) definition mod_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where " mod_vec l r = ( mod_mword l r )" definition mod_vec_maybe :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option " where " mod_vec_maybe l r = ( mod_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )" definition mod_vec_fail :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where " mod_vec_fail l r = ( maybe_fail (''mod_vec'') (mod_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))" -definition mod_vec_oracle :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where - " mod_vec_oracle l r = ( - (case (mod_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of +definition mod_vec_nondet :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " mod_vec_nondet l r = ( + (case (mod_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of Some w => return w - | None => mword_oracle () + | None => mword_nondet () ))" (*val quot_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) (*val quot_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) (*val quot_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) -(*val quot_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val quot_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) definition quot_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where " quot_vec l r = ( quot_mword l r )" definition quot_vec_maybe :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option " where " quot_vec_maybe l r = ( quot_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )" definition quot_vec_fail :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where " quot_vec_fail l r = ( maybe_fail (''quot_vec'') (quot_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))" -definition quot_vec_oracle :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where - " quot_vec_oracle l r = ( - (case (quot_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of +definition quot_vec_nondet :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " quot_vec_nondet l r = ( + (case (quot_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of Some w => return w - | None => mword_oracle () + | None => mword_nondet () ))" (*val quots_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) (*val quots_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) (*val quots_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) -(*val quots_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val quots_vec_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) definition quots_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where " quots_vec l r = ( quots_mword l r )" definition quots_vec_maybe :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option " where " quots_vec_maybe l r = ( quots_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )" definition quots_vec_fail :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where " quots_vec_fail l r = ( maybe_fail (''quots_vec'') (quots_bv - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))" -definition quots_vec_oracle :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where - " quots_vec_oracle l r = ( - (case (quots_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of +definition quots_vec_nondet :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " quots_vec_nondet l r = ( + (case (quots_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of Some w => return w - | None => mword_oracle () + | None => mword_nondet () ))" (*val mod_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) (*val mod_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*) (*val mod_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) -(*val mod_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +(*val mod_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) definition mod_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where " mod_vec_int l r = ( mod_mword_int l r )" definition mod_vec_int_maybe :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option " where " mod_vec_int_maybe l r = ( mod_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )" definition mod_vec_int_fail :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where " mod_vec_int_fail l r = ( maybe_fail (''mod_vec_int'') (mod_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))" -definition mod_vec_int_oracle :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where - " mod_vec_int_oracle l r = ( - (case (mod_bv_int instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of +definition mod_vec_int_nondet :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " mod_vec_int_nondet l r = ( + (case (mod_bv_int instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of Some w => return w - | None => mword_oracle () + | None => mword_nondet () ))" (*val quot_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) (*val quot_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*) (*val quot_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) -(*val quot_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +(*val quot_vec_int_nondet : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) definition quot_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where " quot_vec_int l r = ( quot_mword_int l r )" definition quot_vec_int_maybe :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option " where " quot_vec_int_maybe l r = ( quot_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r )" definition quot_vec_int_fail :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where " quot_vec_int_fail l r = ( maybe_fail (''quot_vec_int'') (quot_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r))" -definition quot_vec_int_oracle :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where - " quot_vec_int_oracle l r = ( +definition quot_vec_int_nondet :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " quot_vec_int_nondet l r = ( (case (quot_bv_int - instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict l r) of Some w => return w - | None => mword_oracle () + | None => mword_nondet () ))" @@ -597,8 +567,8 @@ definition duplicate_maybe :: " bitU \<Rightarrow> int \<Rightarrow>(('a::len)W definition duplicate_fail :: " bitU \<Rightarrow> int \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where " duplicate_fail b n = ( bool_of_bitU_fail b \<bind> (\<lambda> b . return (duplicate_bool b n)))" -definition duplicate_oracle :: " bitU \<Rightarrow> int \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where - " duplicate_oracle b n = ( bool_of_bitU_oracle b \<bind> (\<lambda> b . return (duplicate_bool b n)))" +definition duplicate_nondet :: " bitU \<Rightarrow> int \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " duplicate_nondet b n = ( bool_of_bitU_nondet b \<bind> (\<lambda> b . return (duplicate_bool b n)))" definition duplicate :: " bitU \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where " duplicate b n = ( maybe_failwith (duplicate_maybe b n))" @@ -612,13 +582,13 @@ definition reverse_endianness :: "('a::len)Word.word \<Rightarrow>('a::len)Word (*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a*) definition get_slice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where " get_slice_int = ( - get_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict )" + get_slice_int_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict )" (*val set_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer*) definition set_slice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow> int " where " set_slice_int = ( - set_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict )" + set_slice_int_bv instance_Sail2_values_Bitvector_Machine_word_mword_dict )" (*val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*) diff --git a/snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy b/snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy new file mode 100644 index 00000000..47bf32b2 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail2_operators_mwords_lemmas.thy @@ -0,0 +1,170 @@ +theory Sail2_operators_mwords_lemmas + imports Sail2_operators_mwords +begin + +lemmas uint_simps[simp] = uint_maybe_def uint_fail_def uint_nondet_def +lemmas sint_simps[simp] = sint_maybe_def sint_fail_def sint_nondet_def + +lemma bools_of_bits_nondet_just_list[simp]: + assumes "just_list (map bool_of_bitU bus) = Some bs" + shows "bools_of_bits_nondet bus = return bs" +proof - + have f: "foreachM bus bools (\<lambda>b bools. bool_of_bitU_nondet b \<bind> (\<lambda>b. return (bools @ [b]))) = return (bools @ bs)" + if "just_list (map bool_of_bitU bus) = Some bs" for bus bs bools + proof (use that in \<open>induction bus arbitrary: bs bools\<close>) + case (Cons bu bus bs) + obtain b bs' where bs: "bs = b # bs'" and bu: "bool_of_bitU bu = Some b" + using Cons.prems by (cases bu) (auto split: option.splits) + then show ?case + using Cons.prems Cons.IH[where bs = bs' and bools = "bools @ [b]"] + by (cases bu) (auto simp: bool_of_bitU_nondet_def split: option.splits) + qed auto + then show ?thesis using f[OF assms, of "[]"] unfolding bools_of_bits_nondet_def + by auto +qed + +lemma of_bits_mword_return_of_bl[simp]: + assumes "just_list (map bool_of_bitU bus) = Some bs" + shows "of_bits_nondet BC_mword bus = return (of_bl bs)" + and "of_bits_fail BC_mword bus = return (of_bl bs)" + by (auto simp: of_bits_nondet_def of_bits_fail_def maybe_fail_def assms BC_mword_defs) + +lemma vec_of_bits_of_bl[simp]: + assumes "just_list (map bool_of_bitU bus) = Some bs" + shows "vec_of_bits_maybe bus = Some (of_bl bs)" + and "vec_of_bits_fail bus = return (of_bl bs)" + and "vec_of_bits_nondet bus = return (of_bl bs)" + and "vec_of_bits_failwith bus = of_bl bs" + and "vec_of_bits bus = of_bl bs" + unfolding vec_of_bits_maybe_def vec_of_bits_fail_def vec_of_bits_nondet_def + vec_of_bits_failwith_def vec_of_bits_def + by (auto simp: assms) + +lemmas access_vec_dec_test_bit[simp] = access_bv_dec_mword[folded access_vec_dec_def] + +lemma access_vec_inc_test_bit[simp]: + fixes w :: "('a::len) word" + assumes "n \<ge> 0" and "nat n < LENGTH('a)" + shows "access_vec_inc w n = bitU_of_bool (w !! (LENGTH('a) - 1 - nat n))" + using assms + by (auto simp: access_vec_inc_def access_bv_inc_def access_list_def BC_mword_defs rev_nth test_bit_bl) + +lemma bool_of_bitU_monadic_simps[simp]: + "bool_of_bitU_fail B0 = return False" + "bool_of_bitU_fail B1 = return True" + "bool_of_bitU_fail BU = Fail ''bool_of_bitU''" + "bool_of_bitU_nondet B0 = return False" + "bool_of_bitU_nondet B1 = return True" + "bool_of_bitU_nondet BU = undefined_bool ()" + unfolding bool_of_bitU_fail_def bool_of_bitU_nondet_def + by auto + +lemma update_vec_dec_simps[simp]: + "update_vec_dec_maybe w i B0 = Some (set_bit w (nat i) False)" + "update_vec_dec_maybe w i B1 = Some (set_bit w (nat i) True)" + "update_vec_dec_maybe w i BU = None" + "update_vec_dec_fail w i B0 = return (set_bit w (nat i) False)" + "update_vec_dec_fail w i B1 = return (set_bit w (nat i) True)" + "update_vec_dec_fail w i BU = Fail ''bool_of_bitU''" + "update_vec_dec_nondet w i B0 = return (set_bit w (nat i) False)" + "update_vec_dec_nondet w i B1 = return (set_bit w (nat i) True)" + "update_vec_dec_nondet w i BU = undefined_bool () \<bind> (\<lambda>b. return (set_bit w (nat i) b))" + "update_vec_dec w i B0 = set_bit w (nat i) False" + "update_vec_dec w i B1 = set_bit w (nat i) True" + unfolding update_vec_dec_maybe_def update_vec_dec_fail_def update_vec_dec_nondet_def update_vec_dec_def + by (auto simp: update_mword_dec_def update_mword_bool_dec_def maybe_failwith_def) + +lemma len_of_minus_One_minus_nonneg_lt_len_of[simp]: + "n \<ge> 0 \<Longrightarrow> nat (int LENGTH('a::len) - 1 - n) < LENGTH('a)" + by (metis diff_mono diff_zero len_gt_0 nat_eq_iff2 nat_less_iff order_refl zle_diff1_eq) + +declare subrange_vec_dec_def[simp] + +lemma update_subrange_vec_dec_update_subrange_list_dec: + assumes "0 \<le> j" and "j \<le> i" and "i < int LENGTH('a)" + shows "update_subrange_vec_dec (w :: 'a::len word) i j w' = + of_bl (update_subrange_list_dec (to_bl w) i j (to_bl w'))" + using assms + unfolding update_subrange_vec_dec_def update_subrange_list_dec_def update_subrange_list_inc_def + by (auto simp: word_update_def split_at_def Let_def nat_diff_distrib min_def) + +lemma subrange_vec_dec_subrange_list_dec: + assumes "0 \<le> j" and "j \<le> i" and "i < int LENGTH('a)" and "int LENGTH('b) = i - j + 1" + shows "subrange_vec_dec (w :: 'a::len word) i j = (of_bl (subrange_list_dec (to_bl w) i j) :: 'b::len word)" + using assms unfolding subrange_vec_dec_def + by (auto simp: subrange_list_dec_drop_take slice_take of_bl_drop') + +lemma slice_simp[simp]: "slice w lo len = Word.slice (nat lo) w" + by (auto simp: slice_def) + +declare slice_id[simp] + +lemma of_bools_of_bl[simp]: "of_bools_method BC_mword = of_bl" + by (auto simp: BC_mword_defs) + +lemma of_bl_bin_word_of_int: + "len = LENGTH('a) \<Longrightarrow> of_bl (bin_to_bl_aux len n []) = (word_of_int n :: ('a::len) word)" + by (auto simp: of_bl_def bin_bl_bin') + +lemma get_slice_int_0_bin_to_bl[simp]: + "len > 0 \<Longrightarrow> get_slice_int len n 0 = of_bl (bin_to_bl (nat len) n)" + unfolding get_slice_int_def get_slice_int_bv_def subrange_list_def + by (auto simp: subrange_list_dec_drop_take len_bin_to_bl_aux) + +lemma to_bl_of_bl[simp]: + fixes bl :: "bool list" + defines w: "w \<equiv> of_bl bl :: 'a::len word" + assumes len: "length bl = LENGTH('a)" + shows "to_bl w = bl" + using len unfolding w by (intro word_bl.Abs_inverse) auto + +lemma reverse_endianness_byte[simp]: + "LENGTH('a) = 8 \<Longrightarrow> reverse_endianness (w :: 'a::len word) = w" + unfolding reverse_endianness_def by (auto simp: reverse_endianness_list_simps) + +lemma reverse_reverse_endianness[simp]: + "8 dvd LENGTH('a) \<Longrightarrow> reverse_endianness (reverse_endianness w) = (w :: 'a::len word)" + unfolding reverse_endianness_def by (simp) + +lemma replicate_bits_zero[simp]: "replicate_bits 0 n = 0" + by (intro word_eqI) (auto simp: replicate_bits_def test_bit_of_bl rev_nth nth_repeat simp del: repeat.simps) + +declare extz_vec_def[simp] +declare exts_vec_def[simp] +declare concat_vec_def[simp] + +lemma msb_Bits_msb[simp]: + "msb w = bitU_of_bool (Bits.msb w)" + by (auto simp: msb_def most_significant_def BC_mword_defs word_msb_alt split: list.splits) + +declare and_vec_def[simp] +declare or_vec_def[simp] +declare xor_vec_def[simp] +declare not_vec_def[simp] + +lemma arith_vec_simps[simp]: + "add_vec l r = l + r" + "sub_vec l r = l - r" + "mult_vec l r = (ucast l) * (ucast r)" + unfolding add_vec_def sub_vec_def mult_vec_def + by (auto simp: int_of_mword_def word_add_def word_sub_wi word_mult_def) + +declare adds_vec_def[simp] +declare subs_vec_def[simp] +declare mults_vec_def[simp] + +lemma arith_vec_int_simps: + fixes l :: "'a::len word" + shows "add_vec_int l r = word_of_int (sint l + sint (word_of_int r :: 'a word))" + and "sub_vec_int l r = word_of_int (sint l - sint (word_of_int r :: 'a word))" + and "(mult_vec_int l r :: 'b::len word) = word_of_int (sint (scast l :: 'b word) * sint (word_of_int r :: 'b word))" + unfolding add_vec_int_def sub_vec_int_def mult_vec_int_def + by (auto simp: arith_op_bv_int_def BC_mword_defs word_add_def word_sub_wi word_mult_def) + +lemma shiftl_simp[simp]: "shiftl w l = w << (nat l)" + by (auto simp: shiftl_def shiftl_mword_def) + +lemma shiftr_simp[simp]: "shiftr w l = w >> (nat l)" + by (auto simp: shiftr_def shiftr_mword_def) + +end diff --git a/snapshots/isabelle/lib/sail/Prompt.thy b/snapshots/isabelle/lib/sail/Sail2_prompt.thy index 5792e575..e639d59a 100644 --- a/snapshots/isabelle/lib/sail/Prompt.thy +++ b/snapshots/isabelle/lib/sail/Sail2_prompt.thy @@ -1,21 +1,21 @@ -chapter \<open>Generated by Lem from ../../src/gen_lib/prompt.lem.\<close> +chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_prompt.lem.\<close> -theory "Prompt" +theory "Sail2_prompt" imports Main "Lem_pervasives_extra" - "Sail_values" - "Prompt_monad" - "Prompt_monad_lemmas" + "Sail2_values" + "Sail2_prompt_monad" + "Sail2_prompt_monad_lemmas" begin (*open import Pervasives_extra*) (*open import Sail_impl_base*) -(*open import Sail_values*) -(*open import Prompt_monad*) -(*open import {isabelle} `Prompt_monad_lemmas`*) +(*open import Sail2_values*) +(*open import Sail2_prompt_monad*) +(*open import {isabelle} `Sail2_prompt_monad_lemmas`*) (*val >>= : forall 'rv 'a 'b 'e. monad 'rv 'a 'e -> ('a -> monad 'rv 'b 'e) -> monad 'rv 'b 'e*) @@ -67,9 +67,9 @@ definition bool_of_bitU_fail :: " bitU \<Rightarrow>('rv,(bool),'e)monad " whe ) )" -(*val bool_of_bitU_oracle : forall 'rv 'e. bitU -> monad 'rv bool 'e*) -definition bool_of_bitU_oracle :: " bitU \<Rightarrow>('rv,(bool),'e)monad " where - " bool_of_bitU_oracle = ( \<lambda>x . +(*val bool_of_bitU_nondet : forall 'rv 'e. bitU -> monad 'rv bool 'e*) +definition bool_of_bitU_nondet :: " bitU \<Rightarrow>('rv,(bool),'e)monad " where + " bool_of_bitU_nondet = ( \<lambda>x . (case x of B0 => return False | B1 => return True @@ -77,32 +77,32 @@ definition bool_of_bitU_oracle :: " bitU \<Rightarrow>('rv,(bool),'e)monad " w ) )" -(*val bools_of_bits_oracle : forall 'rv 'e. list bitU -> monad 'rv (list bool) 'e*) -definition bools_of_bits_oracle :: "(bitU)list \<Rightarrow>('rv,((bool)list),'e)monad " where - " bools_of_bits_oracle bits = ( +(*val bools_of_bits_nondet : forall 'rv 'e. list bitU -> monad 'rv (list bool) 'e*) +definition bools_of_bits_nondet :: "(bitU)list \<Rightarrow>('rv,((bool)list),'e)monad " where + " bools_of_bits_nondet bits = ( foreachM bits [] (\<lambda> b bools . - bool_of_bitU_oracle b \<bind> (\<lambda> b . + bool_of_bitU_nondet b \<bind> (\<lambda> b . return (bools @ [b]))))" -(*val of_bits_oracle : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e*) -definition of_bits_oracle :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monad " where - " of_bits_oracle dict_Sail_values_Bitvector_a bits = ( - bools_of_bits_oracle bits \<bind> (\<lambda> bs . - return ((of_bools_method dict_Sail_values_Bitvector_a) bs)))" +(*val of_bits_nondet : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e*) +definition of_bits_nondet :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monad " where + " of_bits_nondet dict_Sail2_values_Bitvector_a bits = ( + bools_of_bits_nondet bits \<bind> (\<lambda> bs . + return ((of_bools_method dict_Sail2_values_Bitvector_a) bs)))" (*val of_bits_fail : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e*) definition of_bits_fail :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monad " where - " of_bits_fail dict_Sail_values_Bitvector_a bits = ( maybe_fail (''of_bits'') ( - (of_bits_method dict_Sail_values_Bitvector_a) bits))" + " of_bits_fail dict_Sail2_values_Bitvector_a bits = ( maybe_fail (''of_bits'') ( + (of_bits_method dict_Sail2_values_Bitvector_a) bits))" -(*val mword_oracle : forall 'rv 'a 'e. Size 'a => unit -> monad 'rv (mword 'a) 'e*) -definition mword_oracle :: " unit \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where - " mword_oracle _ = ( - bools_of_bits_oracle (repeat [BU] (int (len_of (TYPE(_) :: 'a itself)))) \<bind> (\<lambda> bs . +(*val mword_nondet : forall 'rv 'a 'e. Size 'a => unit -> monad 'rv (mword 'a) 'e*) +definition mword_nondet :: " unit \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " mword_nondet _ = ( + bools_of_bits_nondet (repeat [BU] (int (len_of (TYPE(_) :: 'a itself)))) \<bind> (\<lambda> bs . return (Word.of_bl bs)))" @@ -127,6 +127,18 @@ function (sequential,domintros) untilM :: " 'vars \<Rightarrow>('vars \<Righta by pat_completeness auto +(*val internal_pick : forall 'rv 'a 'e. list 'a -> monad 'rv 'a 'e*) +definition internal_pick :: " 'a list \<Rightarrow>('rv,'a,'e)monad " where + " internal_pick xs = ( + (* Use sufficiently many undefined bits and convert into an index into the list *) + bools_of_bits_nondet (repeat [BU] (int (List.length xs))) \<bind> (\<lambda> bs . + (let idx = (( (nat_of_bools bs)) mod List.length xs) in + (case index xs idx of + Some x => return x + | None => Fail (''internal_pick'') + ))))" + + (*let write_two_regs r1 r2 vec = let is_inc = let is_inc_r1 = is_inc_of_reg r1 in diff --git a/snapshots/isabelle/lib/sail/Prompt_monad.thy b/snapshots/isabelle/lib/sail/Sail2_prompt_monad.thy index e4aecfba..d1259332 100644 --- a/snapshots/isabelle/lib/sail/Prompt_monad.thy +++ b/snapshots/isabelle/lib/sail/Sail2_prompt_monad.thy @@ -1,19 +1,19 @@ -chapter \<open>Generated by Lem from ../../src/gen_lib/prompt_monad.lem.\<close> +chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_prompt_monad.lem.\<close> -theory "Prompt_monad" +theory "Sail2_prompt_monad" imports Main "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" + "Sail2_instr_kinds" + "Sail2_values" begin (*open import Pervasives_extra*) (*open import Sail_impl_base*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) type_synonym register_name =" string " type_synonym address =" bitU list " @@ -41,6 +41,7 @@ datatype( 'regval, 'a, 'e) monad = | Read_reg " register_name " " ('regval \<Rightarrow> ('regval, 'a, 'e) monad)" (* Request to write register *) | Write_reg " register_name " " 'regval " " ('regval, 'a, 'e) monad " + (* Request to choose a Boolean, e.g. to resolve an undefined bit *) | Undefined " (bool \<Rightarrow> ('regval, 'a, 'e) monad)" (* Print debugging or tracing information *) | Print " string " " ('regval, 'a, 'e) monad " @@ -153,24 +154,24 @@ definition maybe_fail :: " string \<Rightarrow> 'a option \<Rightarrow>('rv,'a, (*val read_mem_bytes : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv (list memory_byte) 'e*) definition read_mem_bytes :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,((memory_byte)list),'e)monad " where - " read_mem_bytes dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk addr sz = ( - Read_mem rk ((bits_of_method dict_Sail_values_Bitvector_a) addr) (nat_of_int sz) return )" + " read_mem_bytes dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk addr sz = ( + Read_mem rk ((bits_of_method dict_Sail2_values_Bitvector_a) addr) (nat_of_int sz) return )" (*val read_mem : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv 'b 'e*) definition read_mem :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,'b,'e)monad " where - " read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk addr sz = ( + " read_mem dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk addr sz = ( bind - (read_mem_bytes dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_a rk addr sz) + (read_mem_bytes dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_a rk addr sz) (\<lambda> bytes . maybe_fail (''bits_of_mem_bytes'') ( - (of_bits_method dict_Sail_values_Bitvector_b) (bits_of_mem_bytes bytes))))" + (of_bits_method dict_Sail2_values_Bitvector_b) (bits_of_mem_bytes bytes))))" (*val read_tag : forall 'rv 'a 'e. Bitvector 'a => 'a -> monad 'rv bitU 'e*) definition read_tag :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('rv,(bitU),'e)monad " where - " read_tag dict_Sail_values_Bitvector_a addr = ( Read_tag ( - (bits_of_method dict_Sail_values_Bitvector_a) addr) return )" + " read_tag dict_Sail2_values_Bitvector_a addr = ( Read_tag ( + (bits_of_method dict_Sail2_values_Bitvector_a) addr) return )" (*val excl_result : forall 'rv 'e. unit -> monad 'rv bool 'e*) @@ -181,14 +182,14 @@ definition excl_result :: " unit \<Rightarrow>('rv,(bool),'e)monad " where (*val write_mem_ea : forall 'rv 'a 'e. Bitvector 'a => write_kind -> 'a -> integer -> monad 'rv unit 'e*) definition write_mem_ea :: " 'a Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where - " write_mem_ea dict_Sail_values_Bitvector_a wk addr sz = ( Write_ea wk ( - (bits_of_method dict_Sail_values_Bitvector_a) addr) (nat_of_int sz) (Done () ))" + " write_mem_ea dict_Sail2_values_Bitvector_a wk addr sz = ( Write_ea wk ( + (bits_of_method dict_Sail2_values_Bitvector_a) addr) (nat_of_int sz) (Done () ))" (*val write_mem_val : forall 'rv 'a 'e. Bitvector 'a => 'a -> monad 'rv bool 'e*) definition write_mem_val :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('rv,(bool),'e)monad " where - " write_mem_val dict_Sail_values_Bitvector_a v = ( (case mem_bytes_of_bits - dict_Sail_values_Bitvector_a v of + " write_mem_val dict_Sail2_values_Bitvector_a v = ( (case mem_bytes_of_bits + dict_Sail2_values_Bitvector_a v of Some v => Write_memv v return | None => Fail (''write_mem_val'') ))" @@ -196,8 +197,8 @@ definition write_mem_val :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> (*val write_tag : forall 'rv 'a 'e. Bitvector 'a => 'a -> bitU -> monad 'rv bool 'e*) definition write_tag :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('rv,(bool),'e)monad " where - " write_tag dict_Sail_values_Bitvector_a addr b = ( Write_tag ( - (bits_of_method dict_Sail_values_Bitvector_a) addr) b return )" + " write_tag dict_Sail2_values_Bitvector_a addr b = ( Write_tag ( + (bits_of_method dict_Sail2_values_Bitvector_a) addr) b return )" (*val read_reg : forall 's 'rv 'a 'e. register_ref 's 'rv 'a -> monad 'rv 'a 'e*) @@ -264,4 +265,11 @@ definition barrier :: " barrier_kind \<Rightarrow>('rv,(unit),'e)monad " where definition footprint :: " unit \<Rightarrow>('rv,(unit),'e)monad " where " footprint _ = ( Footprint (Done () ))" + +(* Define a type synonym that also takes the register state as a type parameter, + in order to make switching to the state monad without changing generated + definitions easier, see also lib/hol/prompt_monad.lem. *) + +type_synonym( 'regval, 'regstate, 'a, 'e) base_monad =" ('regval, 'a, 'e) monad " +type_synonym( 'regval, 'regstate, 'a, 'r, 'e) base_monadR =" ('regval, 'a, 'r, 'e) monadR " end diff --git a/snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy b/snapshots/isabelle/lib/sail/Sail2_prompt_monad_lemmas.thy index e883c2a0..25eb9f52 100644 --- a/snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy +++ b/snapshots/isabelle/lib/sail/Sail2_prompt_monad_lemmas.thy @@ -1,7 +1,7 @@ -theory Prompt_monad_lemmas +theory Sail2_prompt_monad_lemmas imports - Prompt_monad - Sail_values_lemmas + Sail2_prompt_monad + Sail2_values_lemmas begin notation bind (infixr "\<bind>" 54) @@ -17,6 +17,7 @@ lemmas bind_induct[case_names Done Read_mem Write_memv Read_reg Excl_res Write_e lemma bind_return[simp]: "bind (return a) f = f a" by (auto simp: return_def) +lemma bind_return_right[simp]: "bind x return = x" by (induction x) (auto simp: return_def) lemma bind_assoc[simp]: "bind (bind m f) g = bind m (\<lambda>x. bind (f x) g)" by (induction m f arbitrary: g rule: bind.induct) auto @@ -63,7 +64,7 @@ inductive_set T :: "(('rv, 'a, 'e) monad \<times> 'rv event \<times> ('rv, 'a, ' | Barrier: "((Barrier bk k), e_barrier bk, k) \<in> T" | Read_reg: "((Read_reg r k), e_read_reg r v, k v) \<in> T" | Write_reg: "((Write_reg r v k), e_write_reg r v, k) \<in> T" -| Undefined : "((Undefined k), e_undefined v, k v) \<in> T" +| Undefined: "((Undefined k), e_undefined v, k v) \<in> T" | Print: "((Print msg k), e_print msg, k) \<in> T" inductive_set Traces :: "(('rv, 'a, 'e) monad \<times> 'rv event list \<times> ('rv, 'a, 'e) monad) set" where @@ -94,7 +95,7 @@ lemma Traces_cases: | (Write_ea) wk addr s k t' where "m = Write_ea wk addr s k" and "t = e_write_ea wk addr s # t'" and "(k, t', m') \<in> Traces" | (Footprint) k t' where "m = Footprint k" and "t = e_footprint # t'" and "(k, t', m') \<in> Traces" | (Write_reg) reg v k t' where "m = Write_reg reg v k" and "t = e_write_reg reg v # t'" and "(k, t', m') \<in> Traces" - | (Undefined) v k t' where "m = Undefined k" and "t = e_undefined v # t'" and "(k v, t', m') \<in> Traces" + | (Undefined) xs v k t' where "m = Undefined k" and "t = e_undefined v # t'" and "(k v, t', m') \<in> Traces" | (Print) msg k t' where "m = Print msg k" and "t = e_print msg # t'" and "(k, t', m') \<in> Traces" proof (use Run in \<open>cases m t m' set: Traces\<close>) case Nil @@ -128,6 +129,16 @@ lemma bind_T_cases: | (Bind) m' where "s' = bind m' f" and "(m, e, m') \<in> T" using assms by (cases; blast elim: bind.elims) +lemma Run_bindI: + fixes m :: "('r, 'a, 'e) monad" + assumes "Run m t1 a1" + and "Run (f a1) t2 a2" + shows "Run (m \<bind> f) (t1 @ t2) a2" +proof (use assms in \<open>induction m t1 "Done a1 :: ('r, 'a, 'e) monad" rule: Traces.induct\<close>) + case (Step s e s'' t) + then show ?case by (elim T.cases) auto +qed auto + lemma Run_bindE: fixes m :: "('rv, 'b, 'e) monad" and a :: 'a assumes "Run (bind m f) t a" @@ -160,6 +171,31 @@ lemma Run_DoneE: lemma Run_Done_iff_Nil[simp]: "Run (Done a) t a' \<longleftrightarrow> t = [] \<and> a' = a" by (auto elim: Run_DoneE) +lemma Run_bindE_ignore_trace: + assumes "Run (m \<bind> f) t a" + obtains tm tf am where "Run m tm am" and "Run (f am) tf a" + using assms by (elim Run_bindE) + +lemma Run_letE: + assumes "Run (let x = y in f x) t a" + obtains "Run (f y) t a" + using assms by auto + +lemma Run_ifE: + assumes "Run (if b then f else g) t a" + obtains "b" and "Run f t a" | "\<not>b" and "Run g t a" + using assms by (auto split: if_splits) + +lemma Run_returnE: + assumes "Run (return x) t a" + obtains "t = []" and "a = x" + using assms by (auto simp: return_def) + +lemma Run_early_returnE: + assumes "Run (early_return x) t a" + shows P + using assms by (auto simp: early_return_def throw_def elim: Traces_cases) + lemma bind_cong[fundef_cong]: assumes m: "m1 = m2" and f: "\<And>t a. Run m2 t a \<Longrightarrow> f1 a = f2 a" @@ -167,4 +203,10 @@ lemma bind_cong[fundef_cong]: unfolding m using f by (induction m2 f1 arbitrary: f2 rule: bind.induct; unfold bind.simps; blast) +lemma liftR_read_reg[simp]: "liftR (read_reg reg) = read_reg reg" by (auto simp: read_reg_def liftR_def split: option.splits) +lemma try_catch_return[simp]: "try_catch (return x) h = return x" by (auto simp: return_def) +lemma liftR_return[simp]: "liftR (return x) = return x" by (auto simp: liftR_def) +lemma liftR_undefined_bool[simp]: "liftR (undefined_bool ()) = undefined_bool ()" by (auto simp: undefined_bool_def liftR_def) +lemma assert_exp_True_return[simp]: "assert_exp True msg = return ()" by (auto simp: assert_exp_def return_def) + end diff --git a/snapshots/isabelle/lib/sail/Sail2_state.thy b/snapshots/isabelle/lib/sail/Sail2_state.thy new file mode 100644 index 00000000..dd591a86 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail2_state.thy @@ -0,0 +1,137 @@ +chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_state.lem.\<close> + +theory "Sail2_state" + +imports + Main + "Lem_pervasives_extra" + "Sail2_values" + "Sail2_state_monad" + "Sail2_state_monad_lemmas" + +begin + +(*open import Pervasives_extra*) +(*open import Sail2_values*) +(*open import Sail2_state_monad*) +(*open import {isabelle} `Sail2_state_monad_lemmas`*) + +(*val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) +fun iterS_aux :: " int \<Rightarrow>(int \<Rightarrow> 'a \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monadS " where + " iterS_aux i f (x # xs) = ( seqS (f i x) (iterS_aux (i +( 1 :: int)) f xs))" +|" iterS_aux i f ([]) = ( returnS () )" + + +(*val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) +definition iteriS :: "(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monadS)\<Rightarrow> 'a list \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set " where + " iteriS f xs = ( iterS_aux(( 0 :: int)) f xs )" + + +(*val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) +definition iterS :: "('a \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set)\<Rightarrow> 'a list \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set " where + " iterS f xs = ( iteriS ( \<lambda>x . + (case x of _ => \<lambda> x . f x )) xs )" + + +(*val foreachS : forall 'a 'rv 'vars 'e. + list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) +fun foreachS :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set " where + " foreachS ([]) vars body = ( returnS vars )" +|" foreachS (x # xs) vars body = ( bindS + (body x vars) (\<lambda> vars . + foreachS xs vars body))" + + +(*val and_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*) +definition and_boolS :: "('rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('rv,(bool),'e)monadS " where + " and_boolS l r = ( bindS l (\<lambda> l . if l then r else returnS False))" + + +(*val or_boolS : forall 'rv 'e. monadS 'rv bool 'e -> monadS 'rv bool 'e -> monadS 'rv bool 'e*) +definition or_boolS :: "('rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('rv,(bool),'e)monadS " where + " or_boolS l r = ( bindS l (\<lambda> l . if l then returnS True else r))" + + +(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monadS 'rv bool 'e*) +definition bool_of_bitU_fail :: " bitU \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set " where + " bool_of_bitU_fail = ( \<lambda>x . + (case x of + B0 => returnS False + | B1 => returnS True + | BU => failS (''bool_of_bitU'') + ) )" + + +(*val bool_of_bitU_nondetS : forall 'rv 'e. bitU -> monadS 'rv bool 'e*) +definition bool_of_bitU_nondetS :: " bitU \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set " where + " bool_of_bitU_nondetS = ( \<lambda>x . + (case x of + B0 => returnS False + | B1 => returnS True + | BU => undefined_boolS () + ) )" + + +(*val bools_of_bits_nondetS : forall 'rv 'e. list bitU -> monadS 'rv (list bool) 'e*) +definition bools_of_bits_nondetS :: "(bitU)list \<Rightarrow> 'rv sequential_state \<Rightarrow>((((bool)list),'e)result*'rv sequential_state)set " where + " bools_of_bits_nondetS bits = ( + foreachS bits [] + (\<lambda> b bools . bindS + (bool_of_bitU_nondetS b) (\<lambda> b . + returnS (bools @ [b]))))" + + +(*val of_bits_nondetS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*) +definition of_bits_nondetS :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monadS " where + " of_bits_nondetS dict_Sail2_values_Bitvector_a bits = ( bindS + (bools_of_bits_nondetS bits) (\<lambda> bs . + returnS ((of_bools_method dict_Sail2_values_Bitvector_a) bs)))" + + +(*val of_bits_failS : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monadS 'rv 'a 'e*) +definition of_bits_failS :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow> 'rv sequential_state \<Rightarrow>(('a,'e)result*'rv sequential_state)set " where + " of_bits_failS dict_Sail2_values_Bitvector_a bits = ( maybe_failS (''of_bits'') ( + (of_bits_method dict_Sail2_values_Bitvector_a) bits))" + + +(*val mword_nondetS : forall 'rv 'a 'e. Size 'a => unit -> monadS 'rv (mword 'a) 'e*) +definition mword_nondetS :: " unit \<Rightarrow>('rv,(('a::len)Word.word),'e)monadS " where + " mword_nondetS _ = ( bindS + (bools_of_bits_nondetS (repeat [BU] (int (len_of (TYPE(_) :: 'a itself))))) (\<lambda> bs . + returnS (Word.of_bl bs)))" + + + +(*val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) -> + ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) +function (sequential,domintros) whileS :: " 'vars \<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set " where + " whileS vars cond body s = ( + ( bindS(cond vars) (\<lambda> cond_val s' . + if cond_val then + ( bindS(body vars) (\<lambda> vars s'' . whileS vars cond body s'')) s' + else returnS vars s')) s )" +by pat_completeness auto + + +(*val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) -> + ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) +function (sequential,domintros) untilS :: " 'vars \<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set " where + " untilS vars cond body s = ( + ( bindS(body vars) (\<lambda> vars s' . + ( bindS(cond vars) (\<lambda> cond_val s'' . + if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s )" +by pat_completeness auto + + +(*val internal_pickS : forall 'rv 'a 'e. list 'a -> monadS 'rv 'a 'e*) +definition internal_pickS :: " 'a list \<Rightarrow>('rv,'a,'e)monadS " where + " internal_pickS xs = ( bindS + ( + (* Use sufficiently many undefined bits and convert into an index into the list *)bools_of_bits_nondetS (repeat [BU] (int (List.length xs)))) (\<lambda> bs . + (let idx = (( (nat_of_bools bs)) mod List.length xs) in + (case index xs idx of + Some x => returnS x + | None => failS (''internal_pick'') + ))))" + +end diff --git a/snapshots/isabelle/lib/sail/Sail2_state_lemmas.thy b/snapshots/isabelle/lib/sail/Sail2_state_lemmas.thy new file mode 100644 index 00000000..ba69d0d8 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail2_state_lemmas.thy @@ -0,0 +1,387 @@ +theory Sail2_state_lemmas + imports Sail2_state Sail2_state_lifting +begin + +lemma All_liftState_dom: "liftState_dom (r, m)" + by (induction m) (auto intro: liftState.domintros) +termination liftState using All_liftState_dom by auto + +named_theorems liftState_simp + +lemma liftState_bind[liftState_simp]: + "liftState r (bind m f) = bindS (liftState r m) (liftState r \<circ> f)" + by (induction m f rule: bind.induct) auto + +lemma liftState_return[liftState_simp]: "liftState r (return a) = returnS a" by (auto simp: return_def) + +lemma Value_liftState_Run: + assumes "(Value a, s') \<in> liftState r m s" + obtains t where "Run m t a" + by (use assms in \<open>induction r m arbitrary: s s' rule: liftState.induct\<close>; + auto simp add: failS_def throwS_def returnS_def simp del: read_regvalS.simps; + blast elim: Value_bindS_elim) + +lemmas liftState_if_distrib[liftState_simp] = if_distrib[where f = "liftState ra" for ra] + +lemma Value_bindS_iff: + "(Value b, s'') \<in> bindS m f s \<longleftrightarrow> (\<exists>a s'. (Value a, s') \<in> m s \<and> (Value b, s'') \<in> f a s')" + by (auto elim!: bindS_cases intro: bindS_intros) + +lemma Ex_bindS_iff: + "(Ex e, s'') \<in> bindS m f s \<longleftrightarrow> (Ex e, s'') \<in> m s \<or> (\<exists>a s'. (Value a, s') \<in> m s \<and> (Ex e, s'') \<in> f a s')" + by (auto elim!: bindS_cases intro: bindS_intros) + +lemma liftState_throw[liftState_simp]: "liftState r (throw e) = throwS e" + by (auto simp: throw_def) +lemma liftState_assert[liftState_simp]: "liftState r (assert_exp c msg) = assert_expS c msg" + by (auto simp: assert_exp_def assert_expS_def) +lemma liftState_exit[liftState_simp]: "liftState r (exit0 ()) = exitS ()" + by (auto simp: exit0_def exitS_def) +lemma liftState_exclResult[liftState_simp]: "liftState r (excl_result ()) = excl_resultS ()" + by (auto simp: excl_result_def liftState_simp) +lemma liftState_barrier[liftState_simp]: "liftState r (barrier bk) = returnS ()" + by (auto simp: barrier_def) +lemma liftState_footprint[liftState_simp]: "liftState r (footprint ()) = returnS ()" + by (auto simp: footprint_def) +lemma liftState_undefined[liftState_simp]: "liftState r (undefined_bool ()) = undefined_boolS ()" + by (auto simp: undefined_bool_def liftState_simp) +lemma liftState_maybe_fail[liftState_simp]: "liftState r (maybe_fail msg x) = maybe_failS msg x" + by (auto simp: maybe_fail_def maybe_failS_def liftState_simp split: option.splits) +lemma liftState_and_boolM[liftState_simp]: + "liftState r (and_boolM x y) = and_boolS (liftState r x) (liftState r y)" + by (auto simp: and_boolM_def and_boolS_def liftState_simp cong: bindS_cong if_cong) +lemma liftState_or_boolM[liftState_simp]: + "liftState r (or_boolM x y) = or_boolS (liftState r x) (liftState r y)" + by (auto simp: or_boolM_def or_boolS_def liftState_simp cong: bindS_cong if_cong) + +lemma liftState_try_catch[liftState_simp]: + "liftState r (try_catch m h) = try_catchS (liftState r m) (liftState r \<circ> h)" + by (induction m h rule: try_catch_induct) (auto simp: try_catchS_bindS_no_throw) + +lemma liftState_early_return[liftState_simp]: + "liftState r (early_return x) = early_returnS x" + by (auto simp: early_return_def early_returnS_def liftState_simp) + +lemma liftState_catch_early_return[liftState_simp]: + "liftState r (catch_early_return m) = catch_early_returnS (liftState r m)" + by (auto simp: catch_early_return_def catch_early_returnS_def sum.case_distrib liftState_simp cong: sum.case_cong) + +lemma liftState_liftR[liftState_simp]: + "liftState r (liftR m) = liftRS (liftState r m)" + by (auto simp: liftR_def liftRS_def liftState_simp) + +lemma liftState_try_catchR[liftState_simp]: + "liftState r (try_catchR m h) = try_catchRS (liftState r m) (liftState r \<circ> h)" + by (auto simp: try_catchR_def try_catchRS_def sum.case_distrib liftState_simp cong: sum.case_cong) + +lemma liftState_bool_of_bitU_nondet[liftState_simp]: + "liftState r (bool_of_bitU_nondet b) = bool_of_bitU_nondetS b" + by (cases b; auto simp: bool_of_bitU_nondet_def bool_of_bitU_nondetS_def liftState_simp) + +lemma liftState_read_mem_BC: + assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a" + shows "liftState r (read_mem BCa BCb rk a sz) = read_memS BCa BCb rk a sz" + using assms + by (auto simp: read_mem_def read_mem_bytes_def read_memS_def read_mem_bytesS_def maybe_failS_def liftState_simp split: option.splits) + +lemma liftState_read_mem[liftState_simp]: + "\<And>a. liftState r (read_mem BC_mword BC_mword rk a sz) = read_memS BC_mword BC_mword rk a sz" + "\<And>a. liftState r (read_mem BC_bitU_list BC_bitU_list rk a sz) = read_memS BC_bitU_list BC_bitU_list rk a sz" + by (auto simp: liftState_read_mem_BC) + +lemma liftState_write_mem_ea_BC: + assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a" + shows "liftState r (write_mem_ea BCa rk a sz) = write_mem_eaS BCa rk a (nat sz)" + using assms by (auto simp: write_mem_ea_def write_mem_eaS_def) + +lemma liftState_write_mem_ea[liftState_simp]: + "\<And>a. liftState r (write_mem_ea BC_mword rk a sz) = write_mem_eaS BC_mword rk a (nat sz)" + "\<And>a. liftState r (write_mem_ea BC_bitU_list rk a sz) = write_mem_eaS BC_bitU_list rk a (nat sz)" + by (auto simp: liftState_write_mem_ea_BC) + +lemma liftState_write_mem_val[liftState_simp]: + "liftState r (write_mem_val BC v) = write_mem_valS BC v" + by (auto simp: write_mem_val_def write_mem_valS_def liftState_simp split: option.splits) + +lemma liftState_read_reg_readS: + assumes "\<And>s. Option.bind (get_regval' (name reg) s) (of_regval reg) = Some (read_from reg s)" + shows "liftState (get_regval', set_regval') (read_reg reg) = readS (read_from reg \<circ> regstate)" +proof + fix s :: "'a sequential_state" + obtain rv v where "get_regval' (name reg) (regstate s) = Some rv" + and "of_regval reg rv \<equiv> Some v" and "read_from reg (regstate s) = v" + using assms unfolding bind_eq_Some_conv by blast + then show "liftState (get_regval', set_regval') (read_reg reg) s = readS (read_from reg \<circ> regstate) s" + by (auto simp: read_reg_def bindS_def returnS_def read_regS_def readS_def) +qed + +lemma liftState_write_reg_updateS: + assumes "\<And>s. set_regval' (name reg) (regval_of reg v) s = Some (write_to reg v s)" + shows "liftState (get_regval', set_regval') (write_reg reg v) = updateS (regstate_update (write_to reg v))" + using assms by (auto simp: write_reg_def updateS_def returnS_def bindS_readS) + +lemma liftState_iter_aux[liftState_simp]: + shows "liftState r (iter_aux i f xs) = iterS_aux i (\<lambda>i x. liftState r (f i x)) xs" + by (induction i "\<lambda>i x. liftState r (f i x)" xs rule: iterS_aux.induct) + (auto simp: liftState_simp cong: bindS_cong) + +lemma liftState_iteri[liftState_simp]: + "liftState r (iteri f xs) = iteriS (\<lambda>i x. liftState r (f i x)) xs" + by (auto simp: iteri_def iteriS_def liftState_simp) + +lemma liftState_iter[liftState_simp]: + "liftState r (iter f xs) = iterS (liftState r \<circ> f) xs" + by (auto simp: iter_def iterS_def liftState_simp) + +lemma liftState_foreachM[liftState_simp]: + "liftState r (foreachM xs vars body) = foreachS xs vars (\<lambda>x vars. liftState r (body x vars))" + by (induction xs vars "\<lambda>x vars. liftState r (body x vars)" rule: foreachS.induct) + (auto simp: liftState_simp cong: bindS_cong) + +lemma liftState_bools_of_bits_nondet[liftState_simp]: + "liftState r (bools_of_bits_nondet bs) = bools_of_bits_nondetS bs" + unfolding bools_of_bits_nondet_def bools_of_bits_nondetS_def + by (auto simp: liftState_simp comp_def) + +lemma liftState_internal_pick[liftState_simp]: + "liftState r (internal_pick xs) = internal_pickS xs" + by (auto simp: internal_pick_def internal_pickS_def liftState_simp comp_def + option.case_distrib[where h = "liftState r"] + simp del: repeat.simps + cong: option.case_cong) + +lemma liftRS_returnS[simp]: "liftRS (returnS x) = returnS x" + by (auto simp: liftRS_def) + +lemma liftRS_bindS: + fixes m :: "('regs, 'a, 'e) monadS" and f :: "'a \<Rightarrow> ('regs, 'b, 'e) monadS" + shows "(liftRS (bindS m f) :: ('regs, 'b, 'r, 'e) monadRS) = bindS (liftRS m) (liftRS \<circ> f)" +proof (intro ext set_eqI iffI) + fix s and rs' :: "('b, 'r + 'e) result \<times> 'regs sequential_state" + assume lhs: "rs' \<in> liftRS (bindS m f) s" + then show "rs' \<in> bindS (liftRS m) (liftRS \<circ> f) s" + by (cases rs') + (fastforce simp: liftRS_def throwS_def elim!: bindS_cases try_catchS_cases + intro: bindS_intros try_catchS_intros) +next + fix s and rs' :: "('b, 'r + 'e) result \<times> 'regs sequential_state" + assume "rs' \<in> bindS (liftRS m) (liftRS \<circ> f) s" + then show "rs' \<in> liftRS (bindS m f) s" + by (cases rs') + (fastforce simp: liftRS_def throwS_def elim!: bindS_cases try_catchS_cases + intro: bindS_intros try_catchS_intros) +qed + +lemma liftRS_assert_expS_True[simp]: "liftRS (assert_expS True msg) = returnS ()" + by (auto simp: liftRS_def assert_expS_def) + +lemma untilM_domI: + fixes V :: "'vars \<Rightarrow> nat" + assumes "Inv vars" + and "\<And>vars t vars' t'. \<lbrakk>Inv vars; Run (body vars) t vars'; Run (cond vars') t' False\<rbrakk> \<Longrightarrow> V vars' < V vars \<and> Inv vars'" + shows "untilM_dom (vars, cond, body)" + using assms + by (induction vars rule: measure_induct_rule[where f = V]) + (auto intro: untilM.domintros) + +lemma untilM_dom_untilS_dom: + assumes "untilM_dom (vars, cond, body)" + shows "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)" + using assms + by (induction vars cond body arbitrary: s rule: untilM.pinduct) + (rule untilS.domintros, auto elim!: Value_liftState_Run) + +lemma measure2_induct: + fixes f :: "'a \<Rightarrow> 'b \<Rightarrow> nat" + assumes "\<And>x1 y1. (\<And>x2 y2. f x2 y2 < f x1 y1 \<Longrightarrow> P x2 y2) \<Longrightarrow> P x1 y1" + shows "P x y" +proof - + have "P (fst x) (snd x)" for x + by (induction x rule: measure_induct_rule[where f = "\<lambda>x. f (fst x) (snd x)"]) (auto intro: assms) + then show ?thesis by auto +qed + +lemma untilS_domI: + fixes V :: "'vars \<Rightarrow> 'regs sequential_state \<Rightarrow> nat" + assumes "Inv vars s" + and "\<And>vars s vars' s' s''. + \<lbrakk>Inv vars s; (Value vars', s') \<in> body vars s; (Value False, s'') \<in> cond vars' s'\<rbrakk> + \<Longrightarrow> V vars' s'' < V vars s \<and> Inv vars' s''" + shows "untilS_dom (vars, cond, body, s)" + using assms + by (induction vars s rule: measure2_induct[where f = V]) + (auto intro: untilS.domintros) + +lemma whileS_dom_step: + assumes "whileS_dom (vars, cond, body, s)" + and "(Value True, s') \<in> cond vars s" + and "(Value vars', s'') \<in> body vars s'" + shows "whileS_dom (vars', cond, body, s'')" + by (use assms in \<open>induction vars cond body s arbitrary: vars' s' s'' rule: whileS.pinduct\<close>) + (auto intro: whileS.domintros) + +lemma whileM_dom_step: + assumes "whileM_dom (vars, cond, body)" + and "Run (cond vars) t True" + and "Run (body vars) t' vars'" + shows "whileM_dom (vars', cond, body)" + by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: whileM.pinduct\<close>) + (auto intro: whileM.domintros) + +lemma whileM_dom_ex_step: + assumes "whileM_dom (vars, cond, body)" + and "\<exists>t. Run (cond vars) t True" + and "\<exists>t'. Run (body vars) t' vars'" + shows "whileM_dom (vars', cond, body)" + using assms by (blast intro: whileM_dom_step) + +lemmas whileS_pinduct = whileS.pinduct[case_names Step] + +lemma liftState_whileM: + assumes "whileS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)" + and "whileM_dom (vars, cond, body)" + shows "liftState r (whileM vars cond body) s = whileS vars (liftState r \<circ> cond) (liftState r \<circ> body) s" +proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: whileS.pinduct\<close>) + case Step: (1 vars s) + note domS = Step(1) and IH = Step(2) and domM = Step(3) + show ?case unfolding whileS.psimps[OF domS] whileM.psimps[OF domM] liftState_bind + proof (intro bindS_ext_cong, goal_cases cond while) + case (while a s') + have "bindS (liftState r (body vars)) (liftState r \<circ> (\<lambda>vars. whileM vars cond body)) s' = + bindS (liftState r (body vars)) (\<lambda>vars. whileS vars (liftState r \<circ> cond) (liftState r \<circ> body)) s'" + if "a" + proof (intro bindS_ext_cong, goal_cases body while') + case (while' vars' s'') + have "whileM_dom (vars', cond, body)" proof (rule whileM_dom_ex_step[OF domM]) + show "\<exists>t. Run (cond vars) t True" using while that by (auto elim: Value_liftState_Run) + show "\<exists>t'. Run (body vars) t' vars'" using while' that by (auto elim: Value_liftState_Run) + qed + then show ?case using while while' that IH by auto + qed auto + then show ?case by (auto simp: liftState_simp) + qed auto +qed + + +lemma untilM_dom_step: + assumes "untilM_dom (vars, cond, body)" + and "Run (body vars) t vars'" + and "Run (cond vars') t' False" + shows "untilM_dom (vars', cond, body)" + by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: untilM.pinduct\<close>) + (auto intro: untilM.domintros) + +lemma untilM_dom_ex_step: + assumes "untilM_dom (vars, cond, body)" + and "\<exists>t. Run (body vars) t vars'" + and "\<exists>t'. Run (cond vars') t' False" + shows "untilM_dom (vars', cond, body)" + using assms by (blast intro: untilM_dom_step) + +lemma liftState_untilM: + assumes "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)" + and "untilM_dom (vars, cond, body)" + shows "liftState r (untilM vars cond body) s = untilS vars (liftState r \<circ> cond) (liftState r \<circ> body) s" +proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: untilS.pinduct\<close>) + case Step: (1 vars s) + note domS = Step(1) and IH = Step(2) and domM = Step(3) + show ?case unfolding untilS.psimps[OF domS] untilM.psimps[OF domM] liftState_bind + proof (intro bindS_ext_cong, goal_cases body k) + case (k vars' s') + show ?case unfolding comp_def liftState_bind + proof (intro bindS_ext_cong, goal_cases cond until) + case (until a s'') + have "untilM_dom (vars', cond, body)" if "\<not>a" + proof (rule untilM_dom_ex_step[OF domM]) + show "\<exists>t. Run (body vars) t vars'" using k by (auto elim: Value_liftState_Run) + show "\<exists>t'. Run (cond vars') t' False" using until that by (auto elim: Value_liftState_Run) + qed + then show ?case using k until IH by (auto simp: comp_def liftState_simp) + qed auto + qed auto +qed + +(* Simplification rules for monadic Boolean connectives *) + +lemma if_return_return[simp]: "(if a then return True else return False) = return a" by auto + +lemma and_boolM_simps[simp]: + "and_boolM (return b) (return c) = return (b \<and> c)" + "and_boolM x (return True) = x" + "and_boolM x (return False) = x \<bind> (\<lambda>_. return False)" + "\<And>x y z. and_boolM (x \<bind> y) z = (x \<bind> (\<lambda>r. and_boolM (y r) z))" + by (auto simp: and_boolM_def) + +lemma and_boolM_return_if: + "and_boolM (return b) y = (if b then y else return False)" + by (auto simp: and_boolM_def) + +lemma and_boolM_return_return_and[simp]: "and_boolM (return l) (return r) = return (l \<and> r)" + by (auto simp: and_boolM_def) + +lemmas and_boolM_if_distrib[simp] = if_distrib[where f = "\<lambda>x. and_boolM x y" for y] + +lemma or_boolM_simps[simp]: + "or_boolM (return b) (return c) = return (b \<or> c)" + "or_boolM x (return True) = x \<bind> (\<lambda>_. return True)" + "or_boolM x (return False) = x" + "\<And>x y z. or_boolM (x \<bind> y) z = (x \<bind> (\<lambda>r. or_boolM (y r) z))" + by (auto simp: or_boolM_def) + +lemma or_boolM_return_if: + "or_boolM (return b) y = (if b then return True else y)" + by (auto simp: or_boolM_def) + +lemma or_boolM_return_return_or[simp]: "or_boolM (return l) (return r) = return (l \<or> r)" + by (auto simp: or_boolM_def) + +lemmas or_boolM_if_distrib[simp] = if_distrib[where f = "\<lambda>x. or_boolM x y" for y] + +lemma if_returnS_returnS[simp]: "(if a then returnS True else returnS False) = returnS a" by auto + +lemma and_boolS_simps[simp]: + "and_boolS (returnS b) (returnS c) = returnS (b \<and> c)" + "and_boolS x (returnS True) = x" + "and_boolS x (returnS False) = bindS x (\<lambda>_. returnS False)" + "\<And>x y z. and_boolS (bindS x y) z = (bindS x (\<lambda>r. and_boolS (y r) z))" + by (auto simp: and_boolS_def) + +lemma and_boolS_returnS_if: + "and_boolS (returnS b) y = (if b then y else returnS False)" + by (auto simp: and_boolS_def) + +lemmas and_boolS_if_distrib[simp] = if_distrib[where f = "\<lambda>x. and_boolS x y" for y] + +lemma and_boolS_returnS_True[simp]: "and_boolS (returnS True) c = c" + by (auto simp: and_boolS_def) + +lemma or_boolS_simps[simp]: + "or_boolS (returnS b) (returnS c) = returnS (b \<or> c)" + "or_boolS (returnS False) m = m" + "or_boolS x (returnS True) = bindS x (\<lambda>_. returnS True)" + "or_boolS x (returnS False) = x" + "\<And>x y z. or_boolS (bindS x y) z = (bindS x (\<lambda>r. or_boolS (y r) z))" + by (auto simp: or_boolS_def) + +lemma or_boolS_returnS_if: + "or_boolS (returnS b) y = (if b then returnS True else y)" + by (auto simp: or_boolS_def) + +lemmas or_boolS_if_distrib[simp] = if_distrib[where f = "\<lambda>x. or_boolS x y" for y] + +lemma Run_or_boolM_E: + assumes "Run (or_boolM l r) t a" + obtains "Run l t True" and "a" + | tl tr where "Run l tl False" and "Run r tr a" and "t = tl @ tr" + using assms by (auto simp: or_boolM_def elim!: Run_bindE Run_ifE Run_returnE) + +lemma Run_and_boolM_E: + assumes "Run (and_boolM l r) t a" + obtains "Run l t False" and "\<not>a" + | tl tr where "Run l tl True" and "Run r tr a" and "t = tl @ tr" + using assms by (auto simp: and_boolM_def elim!: Run_bindE Run_ifE Run_returnE) + +lemma maybe_failS_Some[simp]: "maybe_failS msg (Some v) = returnS v" + by (auto simp: maybe_failS_def) + +end diff --git a/snapshots/isabelle/lib/sail/Sail2_state_lifting.thy b/snapshots/isabelle/lib/sail/Sail2_state_lifting.thy new file mode 100644 index 00000000..957a7940 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail2_state_lifting.thy @@ -0,0 +1,52 @@ +chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_state_lifting.lem.\<close> + +theory "Sail2_state_lifting" + +imports + Main + "Lem_pervasives_extra" + "Sail2_values" + "Sail2_prompt_monad" + "Sail2_prompt" + "Sail2_state_monad" + "Sail2_state_monad_lemmas" + +begin + +(*open import Pervasives_extra*) +(*open import Sail2_values*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) +(*open import Sail2_state_monad*) +(*open import {isabelle} `Sail2_state_monad_lemmas`*) + +(* State monad wrapper around prompt monad *) + +(*val liftState : forall 'regval 'regs 'a 'e. register_accessors 'regs 'regval -> monad 'regval 'a 'e -> monadS 'regs 'a 'e*) +function (sequential,domintros) liftState :: "(string \<Rightarrow> 'regs \<Rightarrow> 'regval option)*(string \<Rightarrow> 'regval \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow>('regval,'a,'e)monad \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where + " liftState ra (Done a) = ( returnS a )" +|" liftState ra (Read_mem rk a sz k) = ( bindS (read_mem_bytesS + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) rk a sz) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Read_tag t k) = ( bindS (read_tagS + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) t) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Write_memv a k) = ( bindS (write_mem_bytesS a) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Write_tag a t k) = ( bindS (write_tagS + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) a t) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Read_reg r k) = ( bindS (read_regvalS ra r) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Excl_res k) = ( bindS (excl_resultS () ) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Undefined k) = ( bindS (undefined_boolS () ) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Write_ea wk a sz k) = ( seqS (write_mem_eaS + (instance_Sail2_values_Bitvector_list_dict + instance_Sail2_values_BitU_Sail2_values_bitU_dict) wk a sz) (liftState ra k))" +|" liftState ra (Write_reg r v k) = ( seqS (write_regvalS ra r v) (liftState ra k))" +|" liftState ra (Footprint k) = ( liftState ra k )" +|" liftState ra (Barrier _ k) = ( liftState ra k )" +|" liftState ra (Print _ k) = ( liftState ra k )" +|" liftState ra (Fail descr) = ( failS descr )" +|" liftState ra (Exception e) = ( throwS e )" +by pat_completeness auto + +end diff --git a/snapshots/isabelle/lib/sail/State_monad.thy b/snapshots/isabelle/lib/sail/Sail2_state_monad.thy index 8e19f0b6..e1bf0048 100644 --- a/snapshots/isabelle/lib/sail/State_monad.thy +++ b/snapshots/isabelle/lib/sail/Sail2_state_monad.thy @@ -1,18 +1,18 @@ -chapter \<open>Generated by Lem from ../../src/gen_lib/state_monad.lem.\<close> +chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_state_monad.lem.\<close> -theory "State_monad" +theory "Sail2_state_monad" imports Main "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" + "Sail2_instr_kinds" + "Sail2_values" begin (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) (* 'a is result type *) @@ -32,22 +32,15 @@ record 'regs sequential_state = last_exclusive_operation_was_load ::" bool " - (* Random bool generator for use as an undefined bit oracle *) - next_bool ::" nat \<Rightarrow> (bool * nat)" - seed ::" nat " - - -(*val init_state : forall 'regs. 'regs -> (nat -> (bool* nat)) -> nat -> sequential_state 'regs*) -definition init_state :: " 'regs \<Rightarrow>(nat \<Rightarrow> bool*nat)\<Rightarrow> nat \<Rightarrow> 'regs sequential_state " where - " init_state regs o1 s = ( +(*val init_state : forall 'regs. 'regs -> sequential_state 'regs*) +definition init_state :: " 'regs \<Rightarrow> 'regs sequential_state " where + " init_state regs = ( (| regstate = regs, memstate = Map.empty, tagstate = Map.empty, write_ea = None, - last_exclusive_operation_was_load = False, - next_bool = o1, - seed = s |) )" + last_exclusive_operation_was_load = False |) )" datatype 'e ex = @@ -101,13 +94,8 @@ definition failS :: " string \<Rightarrow> 'regs sequential_state \<Rightarrow> (*val undefined_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e*) -definition undefined_boolS :: " unit \<Rightarrow>('regs,(bool),'e)monadS " where - " undefined_boolS _ = ( bindS - (readS (\<lambda> s . (next_bool s) ((seed s)))) ( \<lambda>x . - (case x of - (b, seed1) => seqS (updateS (\<lambda> s . ( s (| seed := seed1 |)))) - (returnS b) - )))" +definition undefined_boolS :: " unit \<Rightarrow> 'regs sequential_state \<Rightarrow>(((bool),'e)result*'regs sequential_state)set " where + " undefined_boolS _ = ( chooseS {False, True})" (*val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e*) @@ -139,14 +127,14 @@ definition assert_expS :: " bool \<Rightarrow> string \<Rightarrow> 'regs seque (* For early return, we abuse exceptions by throwing and catching the return value. The exception type is either 'r 'e, where Right e represents a proper exception and Left r an early return of value r. *) -type_synonym( 'regs, 'a, 'r, 'e) monadSR =" ('regs, 'a, ( ('r, 'e)sum)) monadS " +type_synonym( 'regs, 'a, 'r, 'e) monadRS =" ('regs, 'a, ( ('r, 'e)sum)) monadS " -(*val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadSR 'regs 'a 'r 'e*) +(*val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadRS 'regs 'a 'r 'e*) definition early_returnS :: " 'r \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e)sum))result*'regs sequential_state)set " where " early_returnS r = ( throwS (Inl r))" -(*val catch_early_returnS : forall 'regs 'a 'e. monadSR 'regs 'a 'a 'e -> monadS 'regs 'a 'e*) +(*val catch_early_returnS : forall 'regs 'a 'e. monadRS 'regs 'a 'a 'e -> monadS 'regs 'a 'e*) definition catch_early_returnS :: "('regs sequential_state \<Rightarrow>(('a,(('a,'e)sum))result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where " catch_early_returnS m = ( try_catchS m @@ -154,15 +142,15 @@ definition catch_early_returnS :: "('regs sequential_state \<Rightarrow>(('a,(( (* Lift to monad with early return by wrapping exceptions *) -(*val liftSR : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadSR 'regs 'a 'r 'e*) -definition liftSR :: "('regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e)sum))result*'regs sequential_state)set " where - " liftSR m = ( try_catchS m (\<lambda> e . throwS (Inr e)))" +(*val liftRS : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadRS 'regs 'a 'r 'e*) +definition liftRS :: "('regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e)sum))result*'regs sequential_state)set " where + " liftRS m = ( try_catchS m (\<lambda> e . throwS (Inr e)))" (* Catch exceptions in the presence of early returns *) -(*val try_catchSR : forall 'regs 'a 'r 'e1 'e2. monadSR 'regs 'a 'r 'e1 -> ('e1 -> monadSR 'regs 'a 'r 'e2) -> monadSR 'regs 'a 'r 'e2*) -definition try_catchSR :: "('regs sequential_state \<Rightarrow>(('a,(('r,'e1)sum))result*'regs sequential_state)set)\<Rightarrow>('e1 \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e2)sum))result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e2)sum))result*'regs sequential_state)set " where - " try_catchSR m h = ( +(*val try_catchRS : forall 'regs 'a 'r 'e1 'e2. monadRS 'regs 'a 'r 'e1 -> ('e1 -> monadRS 'regs 'a 'r 'e2) -> monadRS 'regs 'a 'r 'e2*) +definition try_catchRS :: "('regs sequential_state \<Rightarrow>(('a,(('r,'e1)sum))result*'regs sequential_state)set)\<Rightarrow>('e1 \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e2)sum))result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e2)sum))result*'regs sequential_state)set " where + " try_catchRS m h = ( try_catchS m (\<lambda>x . (case x of Inl r => throwS (Inl r) | Inr e => h e )))" @@ -175,18 +163,18 @@ definition maybe_failS :: " string \<Rightarrow> 'a option \<Rightarrow> 'regs (*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e*) definition read_tagS :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('regs,(bitU),'e)monadS " where - " read_tagS dict_Sail_values_Bitvector_a addr = ( bindS + " read_tagS dict_Sail2_values_Bitvector_a addr = ( bindS (maybe_failS (''unsigned'') ( - (unsigned_method dict_Sail_values_Bitvector_a) addr)) (\<lambda> addr . + (unsigned_method dict_Sail2_values_Bitvector_a) addr)) (\<lambda> addr . readS (\<lambda> s . case_option B0 id ((tagstate s) addr))))" (* Read bytes from memory and return in little endian order *) (*val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => read_kind -> 'a -> nat -> monadS 'regs (list memory_byte) 'e*) definition read_mem_bytesS :: " 'a Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow>('regs,(((bitU)list)list),'e)monadS " where - " read_mem_bytesS dict_Sail_values_Bitvector_a read_kind addr sz = ( bindS + " read_mem_bytesS dict_Sail2_values_Bitvector_a read_kind addr sz = ( bindS (maybe_failS (''unsigned'') ( - (unsigned_method dict_Sail_values_Bitvector_a) addr)) (\<lambda> addr . + (unsigned_method dict_Sail2_values_Bitvector_a) addr)) (\<lambda> addr . (let sz = (int sz) in (let addrs = (index_list addr ((addr+sz)-( 1 :: int))(( 1 :: int))) in (let read_byte = (\<lambda> s addr . (memstate s) addr) in @@ -205,10 +193,10 @@ definition read_mem_bytesS :: " 'a Bitvector_class \<Rightarrow> read_kind \<Ri (*val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e*) definition read_memS :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regs,'b,'e)monadS " where - " read_memS dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk a sz = ( bindS - (read_mem_bytesS dict_Sail_values_Bitvector_a rk a (nat_of_int sz)) (\<lambda> bytes . + " read_memS dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b rk a sz = ( bindS + (read_mem_bytesS dict_Sail2_values_Bitvector_a rk a (nat_of_int sz)) (\<lambda> bytes . maybe_failS (''bits_of_mem_bytes'') ( - (of_bits_method dict_Sail_values_Bitvector_b) (bits_of_mem_bytes bytes))))" + (of_bits_method dict_Sail2_values_Bitvector_b) (bits_of_mem_bytes bytes))))" (*val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e*) @@ -221,9 +209,9 @@ definition excl_resultS :: " unit \<Rightarrow>('regs,(bool),'e)monadS " where (*val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => write_kind -> 'a -> nat -> monadS 'regs unit 'e*) definition write_mem_eaS :: " 'a Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow>('regs,(unit),'e)monadS " where - " write_mem_eaS dict_Sail_values_Bitvector_a write_kind addr sz = ( bindS + " write_mem_eaS dict_Sail2_values_Bitvector_a write_kind addr sz = ( bindS (maybe_failS (''unsigned'') ( - (unsigned_method dict_Sail_values_Bitvector_a) addr)) (\<lambda> addr . + (unsigned_method dict_Sail2_values_Bitvector_a) addr)) (\<lambda> addr . (let sz = (int sz) in updateS (\<lambda> s . ( s (| write_ea := (Some (write_kind, addr, sz)) |))))))" @@ -254,8 +242,8 @@ definition write_mem_bytesS :: "((bitU)list)list \<Rightarrow>('regs,(bool),'e) (*val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e*) definition write_mem_valS :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'regs sequential_state \<Rightarrow>(((bool),'e)result*'regs sequential_state)set " where - " write_mem_valS dict_Sail_values_Bitvector_a v = ( (case mem_bytes_of_bits - dict_Sail_values_Bitvector_a v of + " write_mem_valS dict_Sail2_values_Bitvector_a v = ( (case mem_bytes_of_bits + dict_Sail2_values_Bitvector_a v of Some v => write_mem_bytesS v | None => failS (''write_mem_val'') ))" @@ -263,9 +251,9 @@ definition write_mem_valS :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow (*val write_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> bitU -> monadS 'regs bool 'e*) definition write_tagS :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('regs,(bool),'e)monadS " where - " write_tagS dict_Sail_values_Bitvector_a addr t = ( bindS + " write_tagS dict_Sail2_values_Bitvector_a addr t = ( bindS (maybe_failS (''unsigned'') ( - (unsigned_method dict_Sail_values_Bitvector_a) addr)) (\<lambda> addr . seqS + (unsigned_method dict_Sail2_values_Bitvector_a) addr)) (\<lambda> addr . seqS (updateS (\<lambda> s . ( s (| tagstate := (map_update addr t(tagstate s)) |)))) (returnS True)))" diff --git a/snapshots/isabelle/lib/sail/State_monad_lemmas.thy b/snapshots/isabelle/lib/sail/Sail2_state_monad_lemmas.thy index e0d684ba..3a286c10 100644 --- a/snapshots/isabelle/lib/sail/State_monad_lemmas.thy +++ b/snapshots/isabelle/lib/sail/Sail2_state_monad_lemmas.thy @@ -1,13 +1,16 @@ -theory State_monad_lemmas +theory Sail2_state_monad_lemmas imports - State_monad - Sail_values_lemmas + Sail2_state_monad + Sail2_values_lemmas begin (*context notes returnS_def[simp] and failS_def[simp] and throwS_def[simp] and readS_def[simp] and updateS_def[simp] begin*) +notation bindS (infixr "\<bind>\<^sub>S" 54) +notation seqS (infixr "\<then>\<^sub>S" 54) + lemma bindS_ext_cong[fundef_cong]: assumes m: "m1 s = m2 s" and f: "\<And>a s'. (Value a, s') \<in> (m2 s) \<Longrightarrow> f1 a s' = f2 a s'" @@ -35,6 +38,9 @@ lemma bindS_updateS: "bindS (updateS f) m = (\<lambda>s. m () (f s))" lemma bindS_assertS_True[simp]: "bindS (assert_expS True msg) f = f ()" by (auto simp: assert_expS_def) +lemma bindS_chooseS_returnS[simp]: "bindS (chooseS xs) (\<lambda>x. returnS (f x)) = chooseS (f ` xs)" + by (intro ext) (auto simp: bindS_def chooseS_def returnS_def) + lemma result_cases: fixes r :: "('a, 'e) result" diff --git a/snapshots/isabelle/lib/sail/Sail2_string.thy b/snapshots/isabelle/lib/sail/Sail2_string.thy new file mode 100644 index 00000000..fd2c1d04 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail2_string.thy @@ -0,0 +1,215 @@ +chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_string.lem.\<close> + +theory "Sail2_string" + +imports + Main + "Lem_pervasives" + "Lem_list" + "Lem_list_extra" + "Lem_string" + "Lem_string_extra" + "Sail2_operators" + "Sail2_values" + +begin + +(*open import Pervasives*) +(*open import List*) +(*open import List_extra*) +(*open import String*) +(*open import String_extra*) + +(*open import Sail2_operators*) +(*open import Sail2_values*) + +(*val string_sub : string -> ii -> ii -> string*) +definition string_sub :: " string \<Rightarrow> int \<Rightarrow> int \<Rightarrow> string " where + " string_sub str start len = ( + (List.take (nat (abs ( len))) (List.drop (nat (abs ( start))) ( str))))" + + +(*val string_startswith : string -> string -> bool*) +definition string_startswith :: " string \<Rightarrow> string \<Rightarrow> bool " where + " string_startswith str1 str2 = ( + (let prefix = (string_sub str1(( 0 :: int)) (int (List.length str2))) in + (prefix = str2)))" + + +(*val string_drop : string -> ii -> string*) +definition string_drop :: " string \<Rightarrow> int \<Rightarrow> string " where + " string_drop str n = ( + (List.drop (nat (abs ( n))) ( str)))" + + +(*val string_length : string -> ii*) +definition string_length :: " string \<Rightarrow> int " where + " string_length s = ( int (List.length s))" + + +definition string_append :: " string \<Rightarrow> string \<Rightarrow> string " where + " string_append = ( (op@))" + + +(*********************************************** + * Begin stuff that should be in Lem Num_extra * + ***********************************************) + +(*val maybeIntegerOfString : string -> maybe integer*) +definition maybeIntegerOfString :: " string \<Rightarrow>(int)option " where + " maybeIntegerOfString _ = ( None )" + + +(*********************************************** + * end stuff that should be in Lem Num_extra * + ***********************************************) + +function (sequential,domintros) maybe_int_of_prefix :: " string \<Rightarrow>(int*int)option " where + " maybe_int_of_prefix s = ( + if(s = ('''')) then None else + ((let len = (string_length s) in + (case maybeIntegerOfString s of + Some n => Some (n, len) + | None => maybe_int_of_prefix + (string_sub s (( 0 :: int)) (len - ( 1 :: int))) + ))) )" +by pat_completeness auto + + +definition maybe_int_of_string :: " string \<Rightarrow>(int)option " where + " maybe_int_of_string = ( maybeIntegerOfString )" + + +(*val n_leading_spaces : string -> ii*) +function (sequential,domintros) n_leading_spaces :: " string \<Rightarrow> int " where + " n_leading_spaces s = ( + (let len = (string_length s) in + if len =( 0 :: int) then( 0 :: int) else + if len =( 1 :: int) then + if(s = ('' '')) then ( 1 :: int) else ( 0 :: int) + else + (* match len with + * (* | 0 -> 0 *) + * (* | 1 -> *) + * | len -> *) + (* Isabelle generation for pattern matching on characters + is currently broken, so use an if-expression *) + if nth s(( 0 :: nat)) = (CHR '' '') + then( 1 :: int) + (n_leading_spaces (string_sub s(( 1 :: int)) (len -( 1 :: int)))) + else( 0 :: int)))" +by pat_completeness auto + + (* end *) + +definition opt_spc_matches_prefix :: " string \<Rightarrow>(unit*int)option " where + " opt_spc_matches_prefix s = ( + Some (() , n_leading_spaces s))" + + +definition spc_matches_prefix :: " string \<Rightarrow>(unit*int)option " where + " spc_matches_prefix s = ( + (let n = (n_leading_spaces s) in + (* match n with *) +(* | 0 -> Nothing *) + if n =( 0 :: int) then None else + (* | n -> *) Some (() , n)))" + + (* end *) + +definition hex_bits_5_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where + " hex_bits_5_matches_prefix dict_Sail2_values_Bitvector_a s = ( + (case maybe_int_of_prefix s of + None => None + | Some (n, len) => + if(( 0 :: int) \<le> n) \<and> (n <( 32 :: int)) then + Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 5 :: int)) n, len)) + else + None + ))" + + +definition hex_bits_6_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where + " hex_bits_6_matches_prefix dict_Sail2_values_Bitvector_a s = ( + (case maybe_int_of_prefix s of + None => None + | Some (n, len) => + if(( 0 :: int) \<le> n) \<and> (n <( 64 :: int)) then + Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 6 :: int)) n, len)) + else + None + ))" + + +definition hex_bits_12_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where + " hex_bits_12_matches_prefix dict_Sail2_values_Bitvector_a s = ( + (case maybe_int_of_prefix s of + None => None + | Some (n, len) => + if(( 0 :: int) \<le> n) \<and> (n <( 4096 :: int)) then + Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 12 :: int)) n, len)) + else + None + ))" + + +definition hex_bits_13_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where + " hex_bits_13_matches_prefix dict_Sail2_values_Bitvector_a s = ( + (case maybe_int_of_prefix s of + None => None + | Some (n, len) => + if(( 0 :: int) \<le> n) \<and> (n <( 8192 :: int)) then + Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 13 :: int)) n, len)) + else + None + ))" + + +definition hex_bits_16_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where + " hex_bits_16_matches_prefix dict_Sail2_values_Bitvector_a s = ( + (case maybe_int_of_prefix s of + None => None + | Some (n, len) => + if(( 0 :: int) \<le> n) \<and> (n <( 65536 :: int)) then + Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 16 :: int)) n, len)) + else + None + ))" + + + +definition hex_bits_20_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where + " hex_bits_20_matches_prefix dict_Sail2_values_Bitvector_a s = ( + (case maybe_int_of_prefix s of + None => None + | Some (n, len) => + if(( 0 :: int) \<le> n) \<and> (n <( 1048576 :: int)) then + Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 20 :: int)) n, len)) + else + None + ))" + + +definition hex_bits_21_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where + " hex_bits_21_matches_prefix dict_Sail2_values_Bitvector_a s = ( + (case maybe_int_of_prefix s of + None => None + | Some (n, len) => + if(( 0 :: int) \<le> n) \<and> (n <( 2097152 :: int)) then + Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 21 :: int)) n, len)) + else + None + ))" + + +definition hex_bits_32_matches_prefix :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow>('a*int)option " where + " hex_bits_32_matches_prefix dict_Sail2_values_Bitvector_a s = ( + (case maybe_int_of_prefix s of + None => None + | Some (n, len) => + if(( 0 :: int) \<le> n) \<and> (n <( 4294967296 :: int)) then + Some (((of_int_method dict_Sail2_values_Bitvector_a)(( 2147483648 :: int)) n, len)) + else + None + ))" + +end diff --git a/snapshots/isabelle/lib/sail/Sail_values.thy b/snapshots/isabelle/lib/sail/Sail2_values.thy index 7338ac40..6278f8e3 100644 --- a/snapshots/isabelle/lib/sail/Sail_values.thy +++ b/snapshots/isabelle/lib/sail/Sail2_values.thy @@ -1,6 +1,6 @@ -chapter \<open>Generated by Lem from ../../src/gen_lib/sail_values.lem.\<close> +chapter \<open>Generated by Lem from ../../src/gen_lib/sail2_values.lem.\<close> -theory "Sail_values" +theory "Sail2_values" imports Main @@ -55,14 +55,29 @@ let negate_real r = realNegate r let abs_real r = realAbs r let power_real b e = realPowInteger b e*) +(*val print_endline : string -> unit*) +definition print_endline :: " string \<Rightarrow> unit " where + " print_endline _ = ( () )" + +(* declare ocaml target_rep function print_endline = `print_endline` *) + (*val prerr_endline : string -> unit*) definition prerr_endline :: " string \<Rightarrow> unit " where " prerr_endline _ = ( () )" +definition prerr :: " string \<Rightarrow> unit " where + " prerr x = ( prerr_endline x )" + + (*val print_int : string -> integer -> unit*) definition print_int :: " string \<Rightarrow> int \<Rightarrow> unit " where - " print_int msg i = ( prerr_endline (msg @ (stringFromInteger i)))" + " print_int msg i = ( print_endline (msg @ (stringFromInteger i)))" + + +(*val prerr_int : string -> integer -> unit*) +definition prerr_int :: " string \<Rightarrow> int \<Rightarrow> unit " where + " prerr_int msg i = ( prerr_endline (msg @ (stringFromInteger i)))" (*val putchar : integer -> unit*) @@ -193,8 +208,8 @@ definition bitU_char :: " bitU \<Rightarrow> char " where (case x of B0 => (CHR ''0'') | B1 => (CHR ''1'') | BU => (CHR ''?'') ) )" -definition instance_Show_Show_Sail_values_bitU_dict :: "(bitU)Show_class " where - " instance_Show_Show_Sail_values_bitU_dict = ((| +definition instance_Show_Show_Sail2_values_bitU_dict :: "(bitU)Show_class " where + " instance_Show_Show_Sail2_values_bitU_dict = ((| show_method = showBitU |) )" @@ -210,8 +225,8 @@ fun compare_bitU :: " bitU \<Rightarrow> bitU \<Rightarrow> ordering " where |" compare_bitU _ _ = ( GT )" -definition instance_Basic_classes_Ord_Sail_values_bitU_dict :: "(bitU)Ord_class " where - " instance_Basic_classes_Ord_Sail_values_bitU_dict = ((| +definition instance_Basic_classes_Ord_Sail2_values_bitU_dict :: "(bitU)Ord_class " where + " instance_Basic_classes_Ord_Sail2_values_bitU_dict = ((| compare_method = compare_bitU, @@ -232,8 +247,8 @@ record 'a BitU_class= -definition instance_Sail_values_BitU_Sail_values_bitU_dict :: "(bitU)BitU_class " where - " instance_Sail_values_BitU_Sail_values_bitU_dict = ((| +definition instance_Sail2_values_BitU_Sail2_values_bitU_dict :: "(bitU)BitU_class " where + " instance_Sail2_values_BitU_Sail2_values_bitU_dict = ((| to_bitU_method = (\<lambda> b. b), @@ -733,45 +748,45 @@ record 'a Bitvector_class= (*val of_bits_failwith : forall 'a. Bitvector 'a => list bitU -> 'a*) definition of_bits_failwith :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow> 'a " where - " of_bits_failwith dict_Sail_values_Bitvector_a bits = ( maybe_failwith ( - (of_bits_method dict_Sail_values_Bitvector_a) bits))" + " of_bits_failwith dict_Sail2_values_Bitvector_a bits = ( maybe_failwith ( + (of_bits_method dict_Sail2_values_Bitvector_a) bits))" definition int_of_bv :: " 'a Bitvector_class \<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow>(int)option " where - " int_of_bv dict_Sail_values_Bitvector_a sign = ( if sign then - (signed_method dict_Sail_values_Bitvector_a) else (unsigned_method dict_Sail_values_Bitvector_a) )" + " int_of_bv dict_Sail2_values_Bitvector_a sign = ( if sign then + (signed_method dict_Sail2_values_Bitvector_a) else (unsigned_method dict_Sail2_values_Bitvector_a) )" -definition instance_Sail_values_Bitvector_list_dict :: " 'a BitU_class \<Rightarrow>('a list)Bitvector_class " where - " instance_Sail_values_Bitvector_list_dict dict_Sail_values_BitU_a = ((| +definition instance_Sail2_values_Bitvector_list_dict :: " 'a BitU_class \<Rightarrow>('a list)Bitvector_class " where + " instance_Sail2_values_Bitvector_list_dict dict_Sail2_values_BitU_a = ((| bits_of_method = (\<lambda> v. List.map - (to_bitU_method dict_Sail_values_BitU_a) v), + (to_bitU_method dict_Sail2_values_BitU_a) v), of_bits_method = (\<lambda> v. Some (List.map - (of_bitU_method dict_Sail_values_BitU_a) v)), + (of_bitU_method dict_Sail2_values_BitU_a) v)), of_bools_method = (\<lambda> v. List.map - (of_bitU_method dict_Sail_values_BitU_a) (List.map bitU_of_bool v)), + (of_bitU_method dict_Sail2_values_BitU_a) (List.map bitU_of_bool v)), length_method = (\<lambda> xs. int (List.length xs)), of_int_method = (\<lambda> len n. List.map - (of_bitU_method dict_Sail_values_BitU_a) (bits_of_int len n)), + (of_bitU_method dict_Sail2_values_BitU_a) (bits_of_int len n)), unsigned_method = (\<lambda> v. unsigned_of_bits (List.map - (to_bitU_method dict_Sail_values_BitU_a) v)), + (to_bitU_method dict_Sail2_values_BitU_a) v)), signed_method = (\<lambda> v. signed_of_bits (List.map - (to_bitU_method dict_Sail_values_BitU_a) v)), + (to_bitU_method dict_Sail2_values_BitU_a) v)), arith_op_bv_method = (\<lambda> op1 sign l r. List.map - (of_bitU_method dict_Sail_values_BitU_a) (arith_op_bits op1 sign (List.map - (to_bitU_method dict_Sail_values_BitU_a) l) (List.map (to_bitU_method dict_Sail_values_BitU_a) r)))|) )" + (of_bitU_method dict_Sail2_values_BitU_a) (arith_op_bits op1 sign (List.map + (to_bitU_method dict_Sail2_values_BitU_a) l) (List.map (to_bitU_method dict_Sail2_values_BitU_a) r)))|) )" -definition instance_Sail_values_Bitvector_Machine_word_mword_dict :: "(('a::len)Word.word)Bitvector_class " where - " instance_Sail_values_Bitvector_Machine_word_mword_dict = ((| +definition instance_Sail2_values_Bitvector_Machine_word_mword_dict :: "(('a::len)Word.word)Bitvector_class " where + " instance_Sail2_values_Bitvector_Machine_word_mword_dict = ((| bits_of_method = (\<lambda> v. List.map bitU_of_bool (Word.to_bl v)), @@ -792,57 +807,57 @@ definition instance_Sail_values_Bitvector_Machine_word_mword_dict :: "(('a::len definition access_bv_inc :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU " where - " access_bv_inc dict_Sail_values_Bitvector_a v n = ( access_list True ( - (bits_of_method dict_Sail_values_Bitvector_a) v) n )" + " access_bv_inc dict_Sail2_values_Bitvector_a v n = ( access_list True ( + (bits_of_method dict_Sail2_values_Bitvector_a) v) n )" definition access_bv_dec :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU " where - " access_bv_dec dict_Sail_values_Bitvector_a v n = ( access_list False ( - (bits_of_method dict_Sail_values_Bitvector_a) v) n )" + " access_bv_dec dict_Sail2_values_Bitvector_a v n = ( access_list False ( + (bits_of_method dict_Sail2_values_Bitvector_a) v) n )" definition update_bv_inc :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where - " update_bv_inc dict_Sail_values_Bitvector_a v n b = ( update_list True ( - (bits_of_method dict_Sail_values_Bitvector_a) v) n b )" + " update_bv_inc dict_Sail2_values_Bitvector_a v n b = ( update_list True ( + (bits_of_method dict_Sail2_values_Bitvector_a) v) n b )" definition update_bv_dec :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where - " update_bv_dec dict_Sail_values_Bitvector_a v n b = ( update_list False ( - (bits_of_method dict_Sail_values_Bitvector_a) v) n b )" + " update_bv_dec dict_Sail2_values_Bitvector_a v n b = ( update_list False ( + (bits_of_method dict_Sail2_values_Bitvector_a) v) n b )" definition subrange_bv_inc :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where - " subrange_bv_inc dict_Sail_values_Bitvector_a v i j = ( subrange_list True ( - (bits_of_method dict_Sail_values_Bitvector_a) v) i j )" + " subrange_bv_inc dict_Sail2_values_Bitvector_a v i j = ( subrange_list True ( + (bits_of_method dict_Sail2_values_Bitvector_a) v) i j )" definition subrange_bv_dec :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where - " subrange_bv_dec dict_Sail_values_Bitvector_a v i j = ( subrange_list False ( - (bits_of_method dict_Sail_values_Bitvector_a) v) i j )" + " subrange_bv_dec dict_Sail2_values_Bitvector_a v i j = ( subrange_list False ( + (bits_of_method dict_Sail2_values_Bitvector_a) v) i j )" definition update_subrange_bv_inc :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list " where - " update_subrange_bv_inc dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v' = ( update_subrange_list True ( - (bits_of_method dict_Sail_values_Bitvector_b) v) i j ((bits_of_method dict_Sail_values_Bitvector_a) v'))" + " update_subrange_bv_inc dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b v i j v' = ( update_subrange_list True ( + (bits_of_method dict_Sail2_values_Bitvector_b) v) i j ((bits_of_method dict_Sail2_values_Bitvector_a) v'))" definition update_subrange_bv_dec :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list " where - " update_subrange_bv_dec dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v' = ( update_subrange_list False ( - (bits_of_method dict_Sail_values_Bitvector_b) v) i j ((bits_of_method dict_Sail_values_Bitvector_a) v'))" + " update_subrange_bv_dec dict_Sail2_values_Bitvector_a dict_Sail2_values_Bitvector_b v i j v' = ( update_subrange_list False ( + (bits_of_method dict_Sail2_values_Bitvector_b) v) i j ((bits_of_method dict_Sail2_values_Bitvector_a) v'))" (*val extz_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*) definition extz_bv :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list " where - " extz_bv dict_Sail_values_Bitvector_a n v = ( extz_bits n ( - (bits_of_method dict_Sail_values_Bitvector_a) v))" + " extz_bv dict_Sail2_values_Bitvector_a n v = ( extz_bits n ( + (bits_of_method dict_Sail2_values_Bitvector_a) v))" (*val exts_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*) definition exts_bv :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list " where - " exts_bv dict_Sail_values_Bitvector_a n v = ( exts_bits n ( - (bits_of_method dict_Sail_values_Bitvector_a) v))" + " exts_bv dict_Sail2_values_Bitvector_a n v = ( exts_bits n ( + (bits_of_method dict_Sail2_values_Bitvector_a) v))" (*val string_of_bv : forall 'a. Bitvector 'a => 'a -> string*) definition string_of_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> string " where - " string_of_bv dict_Sail_values_Bitvector_a v = ( show_bitlist ( - (bits_of_method dict_Sail_values_Bitvector_a) v))" + " string_of_bv dict_Sail2_values_Bitvector_a v = ( show_bitlist ( + (bits_of_method dict_Sail2_values_Bitvector_a) v))" (*** Bytes and addresses *) @@ -859,8 +874,8 @@ fun byte_chunks :: " 'a list \<Rightarrow>(('a list)list)option " where (*val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> maybe (list memory_byte)*) definition bytes_of_bits :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>(((bitU)list)list)option " where - " bytes_of_bits dict_Sail_values_Bitvector_a bs = ( byte_chunks ( - (bits_of_method dict_Sail_values_Bitvector_a) bs))" + " bytes_of_bits dict_Sail2_values_Bitvector_a bs = ( byte_chunks ( + (bits_of_method dict_Sail2_values_Bitvector_a) bs))" (*val bits_of_bytes : list memory_byte -> list bitU*) @@ -869,8 +884,8 @@ definition bits_of_bytes :: "((bitU)list)list \<Rightarrow>(bitU)list " where definition mem_bytes_of_bits :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>(((bitU)list)list)option " where - " mem_bytes_of_bits dict_Sail_values_Bitvector_a bs = ( map_option List.rev (bytes_of_bits - dict_Sail_values_Bitvector_a bs))" + " mem_bytes_of_bits dict_Sail2_values_Bitvector_a bs = ( map_option List.rev (bytes_of_bits + dict_Sail2_values_Bitvector_a bs))" definition bits_of_mem_bytes :: "((bitU)list)list \<Rightarrow>(bitU)list " where " bits_of_mem_bytes bs = ( bits_of_bytes (List.rev bs))" @@ -1134,30 +1149,30 @@ record 'a ToNatural_class= toNatural_method ::" 'a \<Rightarrow> nat " (* eta-expanded for Isabelle output, otherwise it breaks *) -definition instance_Sail_values_ToNatural_Num_integer_dict :: "(int)ToNatural_class " where - " instance_Sail_values_ToNatural_Num_integer_dict = ((| +definition instance_Sail2_values_ToNatural_Num_integer_dict :: "(int)ToNatural_class " where + " instance_Sail2_values_ToNatural_Num_integer_dict = ((| toNatural_method = (\<lambda> n . nat (abs n))|) )" -definition instance_Sail_values_ToNatural_Num_int_dict :: "(int)ToNatural_class " where - " instance_Sail_values_ToNatural_Num_int_dict = ((| +definition instance_Sail2_values_ToNatural_Num_int_dict :: "(int)ToNatural_class " where + " instance_Sail2_values_ToNatural_Num_int_dict = ((| toNatural_method = (\<lambda> n . (nat (abs n)))|) )" -definition instance_Sail_values_ToNatural_nat_dict :: "(nat)ToNatural_class " where - " instance_Sail_values_ToNatural_nat_dict = ((| +definition instance_Sail2_values_ToNatural_nat_dict :: "(nat)ToNatural_class " where + " instance_Sail2_values_ToNatural_nat_dict = ((| toNatural_method = (\<lambda> n . n)|) )" -definition instance_Sail_values_ToNatural_Num_natural_dict :: "(nat)ToNatural_class " where - " instance_Sail_values_ToNatural_Num_natural_dict = ((| +definition instance_Sail2_values_ToNatural_Num_natural_dict :: "(nat)ToNatural_class " where + " instance_Sail2_values_ToNatural_Num_natural_dict = ((| toNatural_method = (\<lambda> n . n)|) )" fun toNaturalFiveTup :: " 'a ToNatural_class \<Rightarrow> 'b ToNatural_class \<Rightarrow> 'c ToNatural_class \<Rightarrow> 'd ToNatural_class \<Rightarrow> 'e ToNatural_class \<Rightarrow> 'd*'c*'b*'a*'e \<Rightarrow> nat*nat*nat*nat*nat " where - " toNaturalFiveTup dict_Sail_values_ToNatural_a dict_Sail_values_ToNatural_b dict_Sail_values_ToNatural_c dict_Sail_values_ToNatural_d dict_Sail_values_ToNatural_e (n1,n2,n3,n4,n5) = ( - ((toNatural_method dict_Sail_values_ToNatural_d) n1,(toNatural_method dict_Sail_values_ToNatural_c) n2,(toNatural_method dict_Sail_values_ToNatural_b) n3,(toNatural_method dict_Sail_values_ToNatural_a) n4,(toNatural_method dict_Sail_values_ToNatural_e) n5))" + " toNaturalFiveTup dict_Sail2_values_ToNatural_a dict_Sail2_values_ToNatural_b dict_Sail2_values_ToNatural_c dict_Sail2_values_ToNatural_d dict_Sail2_values_ToNatural_e (n1,n2,n3,n4,n5) = ( + ((toNatural_method dict_Sail2_values_ToNatural_d) n1,(toNatural_method dict_Sail2_values_ToNatural_c) n2,(toNatural_method dict_Sail2_values_ToNatural_b) n3,(toNatural_method dict_Sail2_values_ToNatural_a) n4,(toNatural_method dict_Sail2_values_ToNatural_e) n5))" (* Let the following types be generated by Sail per spec, using either bitlists diff --git a/snapshots/isabelle/lib/sail/Sail_values_lemmas.thy b/snapshots/isabelle/lib/sail/Sail2_values_lemmas.thy index dd008695..576cd8ea 100644 --- a/snapshots/isabelle/lib/sail/Sail_values_lemmas.thy +++ b/snapshots/isabelle/lib/sail/Sail2_values_lemmas.thy @@ -1,19 +1,136 @@ -theory Sail_values_lemmas - imports Sail_values +theory Sail2_values_lemmas + imports Sail2_values begin +lemma while_domI: + fixes V :: "'vars \<Rightarrow> nat" + assumes "\<And>vars. cond vars \<Longrightarrow> V (body vars) < V vars" + shows "while_dom (vars, cond, body)" + by (induction vars rule: measure_induct_rule[where f = V]) + (use assms in \<open>auto intro: while.domintros\<close>) + lemma nat_of_int_nat_simps[simp]: "nat_of_int = nat" by (auto simp: nat_of_int_def) termination reverse_endianness_list by (lexicographic_order simp add: drop_list_def) +declare reverse_endianness_list.simps[simp del] +declare take_list_def[simp] +declare drop_list_def[simp] + +function take_chunks :: "nat \<Rightarrow> 'a list \<Rightarrow> 'a list list" where + "take_chunks n [] = []" +| "take_chunks 0 xs = []" +| "take_chunks n xs = take n xs # take_chunks n (drop n xs)" if "n > 0" and "xs \<noteq> []" + by auto blast +termination by lexicographic_order + +lemma take_chunks_length_leq_n: "length xs \<le> n \<Longrightarrow> xs \<noteq> [] \<Longrightarrow> take_chunks n xs = [xs]" + by (cases n) auto + +lemma take_chunks_append: "n dvd length a \<Longrightarrow> take_chunks n (a @ b) = take_chunks n a @ take_chunks n b" + by (induction n a rule: take_chunks.induct) (auto simp: dvd_imp_le) + +lemma Suc8_plus8: "Suc (Suc (Suc (Suc (Suc (Suc (Suc (Suc x))))))) = 8 + x" + by auto + +lemma byte_chunks_take_chunks_8: + assumes "8 dvd length xs" + shows "byte_chunks xs = Some (take_chunks 8 xs)" +proof - + have Suc8_plus8: "Suc (Suc (Suc (Suc (Suc (Suc (Suc (Suc x))))))) = 8 + x" for x + by auto + from assms show ?thesis + by (induction xs rule: byte_chunks.induct) (auto simp: Suc8_plus8 nat_dvd_not_less) +qed + +lemma reverse_endianness_list_rev_take_chunks: + "reverse_endianness_list bits = List.concat (rev (take_chunks 8 bits))" + by (induction "8 :: nat" bits rule: take_chunks.induct) + (auto simp: reverse_endianness_list.simps) + +lemma reverse_endianness_list_simps: + "length bits \<le> 8 \<Longrightarrow> reverse_endianness_list bits = bits" + "length bits > 8 \<Longrightarrow> reverse_endianness_list bits = reverse_endianness_list (drop 8 bits) @ take 8 bits" + by (cases bits; auto simp: reverse_endianness_list_rev_take_chunks)+ + +lemma reverse_endianness_list_append: + assumes "8 dvd length a" + shows "reverse_endianness_list (a @ b) = reverse_endianness_list b @ reverse_endianness_list a" + using assms by (auto simp: reverse_endianness_list_rev_take_chunks take_chunks_append) + +lemma length_reverse_endianness_list[simp]: + "length (reverse_endianness_list l) = length l" + by (induction l rule: reverse_endianness_list.induct) (auto simp: reverse_endianness_list.simps) + +lemma reverse_endianness_list_take_8[simp]: + "reverse_endianness_list (take 8 bits) = take 8 bits" + by (auto simp: reverse_endianness_list_simps) + +lemma reverse_reverse_endianness_list[simp]: + assumes "8 dvd length l" + shows "reverse_endianness_list (reverse_endianness_list l) = l" +proof (use assms in \<open>induction l rule: reverse_endianness_list.induct[case_names Step]\<close>) + case (Step bits) + then show ?case + by (auto simp: reverse_endianness_list.simps[of bits] reverse_endianness_list_append) +qed + +declare repeat.simps[simp del] + +lemma length_repeat[simp]: "length (repeat xs n) = nat n * length xs" +proof (induction xs n rule: repeat.induct[case_names Step]) + case (Step xs n) + then show ?case unfolding repeat.simps[of xs n] + by (auto simp del: mult_Suc simp: mult_Suc[symmetric]) +qed + +lemma nth_repeat: + assumes "i < nat n * length xs" + shows "repeat xs n ! i = xs ! (i mod length xs)" +proof (use assms in \<open>induction xs n arbitrary: i rule: repeat.induct[case_names Step]\<close>) + case (Step xs n i) + show ?case + using Step.prems Step.IH[of "i - length xs"] + unfolding repeat.simps[of xs n] + by (auto simp: nth_append mod_geq[symmetric] nat_diff_distrib diff_mult_distrib) +qed termination index_list by (relation "measure (\<lambda>(i, j, step). nat ((j - i + step) * sgn step))") auto +lemma index_list_Zero[simp]: "index_list i j 0 = []" + by auto + +lemma index_list_singleton[simp]: "n \<noteq> 0 \<Longrightarrow> index_list i i n = [i]" + by auto + +lemma index_list_simps: + "0 < step \<Longrightarrow> from \<le> to \<Longrightarrow> index_list from to step = from # index_list (from + step) to step" + "0 < step \<Longrightarrow> from > to \<Longrightarrow> index_list from to step = []" + "0 > step \<Longrightarrow> from \<ge> to \<Longrightarrow> index_list from to step = from # index_list (from + step) to step" + "0 > step \<Longrightarrow> from < to \<Longrightarrow> index_list from to step = []" + by auto + +lemma index_list_step1_upto[simp]: "index_list i j 1 = [i..j]" + by (induction i j "1 :: int" rule: index_list.induct) + (auto simp: index_list_simps upto.simps) + +lemma length_upto[simp]: "i \<le> j \<Longrightarrow> length [i..j] = nat (j - i + 1)" + by (induction i j rule: upto.induct) (auto simp: upto.simps) + +lemma nth_upto[simp]: "i + int n \<le> j \<Longrightarrow> [i..j] ! n = i + int n" + by (induction i j arbitrary: n rule: upto.induct) + (auto simp: upto.simps nth_Cons split: nat.splits) + +declare index_list.simps[simp del] + lemma just_list_map_Some[simp]: "just_list (map Some v) = Some v" by (induction v) auto lemma just_list_None_iff[simp]: "just_list xs = None \<longleftrightarrow> None \<in> set xs" by (induction xs) (auto split: option.splits) +lemma just_list_None_member_None: "None \<in> set xs \<Longrightarrow> just_list xs = None" + by auto + lemma just_list_Some_iff[simp]: "just_list xs = Some ys \<longleftrightarrow> xs = map Some ys" by (induction xs arbitrary: ys) (auto split: option.splits) @@ -28,10 +145,10 @@ lemma repeat_singleton_replicate[simp]: proof (induction n) case (nonneg n) have "nat (1 + int m) = Suc m" for m by auto - then show ?case by (induction n) auto + then show ?case by (induction n) (auto simp: repeat.simps) next case (neg n) - then show ?case by auto + then show ?case by (auto simp: repeat.simps) qed lemma bool_of_bitU_simps[simp]: @@ -57,10 +174,10 @@ lemma bool_of_bitU_bitU_of_bool[simp]: "bool_of_bitU (bitU_of_bool x) = Some x" by (intro ext, auto simp: bool_of_bitU_def bitU_of_bool_def)+ -abbreviation "BC_bitU_list \<equiv> instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict" -lemmas BC_bitU_list_def = instance_Sail_values_Bitvector_list_dict_def instance_Sail_values_BitU_Sail_values_bitU_dict_def -abbreviation "BC_mword \<equiv> instance_Sail_values_Bitvector_Machine_word_mword_dict" -lemmas BC_mword_defs = instance_Sail_values_Bitvector_Machine_word_mword_dict_def +abbreviation "BC_bitU_list \<equiv> instance_Sail2_values_Bitvector_list_dict instance_Sail2_values_BitU_Sail2_values_bitU_dict" +lemmas BC_bitU_list_def = instance_Sail2_values_Bitvector_list_dict_def instance_Sail2_values_BitU_Sail2_values_bitU_dict_def +abbreviation "BC_mword \<equiv> instance_Sail2_values_Bitvector_Machine_word_mword_dict" +lemmas BC_mword_defs = instance_Sail2_values_Bitvector_Machine_word_mword_dict_def access_mword_def access_mword_inc_def access_mword_dec_def (*update_mword_def update_mword_inc_def update_mword_dec_def*) subrange_list_def subrange_list_inc_def subrange_list_dec_def @@ -102,6 +219,15 @@ lemma unsigned_bits_of_mword[simp]: "unsigned_method BC_bitU_list (bits_of_method BC_mword a) = Some (uint a)" by (auto simp: BC_bitU_list_def BC_mword_defs unsigned_of_bits_def unsigned_of_bools_def) +definition mem_bytes_of_word :: "'a::len word \<Rightarrow> bitU list list" where + "mem_bytes_of_word w = rev (take_chunks 8 (map bitU_of_bool (to_bl w)))" + +lemma mem_bytes_of_bits_mem_bytes_of_word[simp]: + assumes "8 dvd LENGTH('a)" + shows "mem_bytes_of_bits BC_mword (w :: 'a::len word) = Some (mem_bytes_of_word w)" + using assms + by (auto simp: mem_bytes_of_bits_def bytes_of_bits_def BC_mword_defs byte_chunks_take_chunks_8 mem_bytes_of_word_def) + lemma bits_of_bitU_list[simp]: "bits_of_method BC_bitU_list v = v" "of_bits_method BC_bitU_list v = Some v" @@ -158,6 +284,14 @@ lemma update_list_dec_update[simp]: "update_list_dec xs n x = xs[length xs - nat (n + 1) := x]" by (auto simp: update_list_dec_def add.commute diff_diff_add nat_minus_as_int) +lemma update_list_dec_update_rev: + "0 \<le> n \<Longrightarrow> nat n < length xs \<Longrightarrow> update_list_dec xs n x = rev ((rev xs)[nat n := x])" + by (auto simp: update_list_dec_def add.commute diff_diff_add nat_minus_as_int rev_update) + +lemma access_list_dec_update_list_dec[simp]: + "0 \<le> n \<Longrightarrow> nat n < length xs \<Longrightarrow> access_list_dec (update_list_dec xs n x) n = x" + by (auto simp: access_list_dec_rev_nth update_list_dec_update_rev) + lemma bools_of_nat_aux_simps[simp]: "\<And>len. len \<le> 0 \<Longrightarrow> bools_of_nat_aux len x acc = acc" "\<And>len. bools_of_nat_aux (int (Suc len)) x acc = @@ -200,7 +334,7 @@ proof (induction len arbitrary: n acc) qed auto lemma bools_of_int_bin_to_bl[simp]: - "bools_of_int (int len) n = bin_to_bl len n" + "bools_of_int len n = bin_to_bl (nat len) n" by (auto simp: bools_of_int_def Let_def map_Not_bin_to_bl rbl_succ[unfolded bin_to_bl_def]) end diff --git a/snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy b/snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy deleted file mode 100644 index 22c35e1f..00000000 --- a/snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy +++ /dev/null @@ -1,112 +0,0 @@ -theory "Sail_operators_mwords_lemmas" - imports Sail_operators_mwords -begin - -lemmas uint_simps[simp] = uint_maybe_def uint_fail_def uint_oracle_def -lemmas sint_simps[simp] = sint_maybe_def sint_fail_def sint_oracle_def - -lemma bools_of_bits_oracle_just_list[simp]: - assumes "just_list (map bool_of_bitU bus) = Some bs" - shows "bools_of_bits_oracle bus = return bs" -proof - - have f: "foreachM bus bools (\<lambda>b bools. bool_of_bitU_oracle b \<bind> (\<lambda>b. return (bools @ [b]))) = return (bools @ bs)" - if "just_list (map bool_of_bitU bus) = Some bs" for bus bs bools - proof (use that in \<open>induction bus arbitrary: bs bools\<close>) - case (Cons bu bus bs) - obtain b bs' where bs: "bs = b # bs'" and bu: "bool_of_bitU bu = Some b" - using Cons.prems by (cases bu) (auto split: option.splits) - then show ?case - using Cons.prems Cons.IH[where bs = bs' and bools = "bools @ [b]"] - by (cases bu) (auto simp: bool_of_bitU_oracle_def split: option.splits) - qed auto - then show ?thesis using f[OF assms, of "[]"] unfolding bools_of_bits_oracle_def - by auto -qed - -lemma of_bits_mword_return_of_bl[simp]: - assumes "just_list (map bool_of_bitU bus) = Some bs" - shows "of_bits_oracle BC_mword bus = return (of_bl bs)" - and "of_bits_fail BC_mword bus = return (of_bl bs)" - by (auto simp: of_bits_oracle_def of_bits_fail_def maybe_fail_def assms BC_mword_defs) - -lemma vec_of_bits_of_bl[simp]: - assumes "just_list (map bool_of_bitU bus) = Some bs" - shows "vec_of_bits_maybe bus = Some (of_bl bs)" - and "vec_of_bits_fail bus = return (of_bl bs)" - and "vec_of_bits_oracle bus = return (of_bl bs)" - and "vec_of_bits_failwith bus = of_bl bs" - and "vec_of_bits bus = of_bl bs" - unfolding vec_of_bits_maybe_def vec_of_bits_fail_def vec_of_bits_oracle_def - vec_of_bits_failwith_def vec_of_bits_def - by (auto simp: assms) - -lemmas access_vec_dec_test_bit[simp] = access_bv_dec_mword[folded access_vec_dec_def] - -lemma access_vec_inc_test_bit[simp]: - fixes w :: "('a::len) word" - assumes "n \<ge> 0" and "nat n < LENGTH('a)" - shows "access_vec_inc w n = bitU_of_bool (w !! (LENGTH('a) - 1 - nat n))" - using assms - by (auto simp: access_vec_inc_def access_bv_inc_def access_list_def BC_mword_defs rev_nth test_bit_bl) - -lemma bool_of_bitU_monadic_simps[simp]: - "bool_of_bitU_fail B0 = return False" - "bool_of_bitU_fail B1 = return True" - "bool_of_bitU_fail BU = Fail ''bool_of_bitU''" - "bool_of_bitU_oracle B0 = return False" - "bool_of_bitU_oracle B1 = return True" - "bool_of_bitU_oracle BU = undefined_bool ()" - unfolding bool_of_bitU_fail_def bool_of_bitU_oracle_def - by auto - -lemma update_vec_dec_simps[simp]: - "update_vec_dec_maybe w i B0 = Some (set_bit w (nat i) False)" - "update_vec_dec_maybe w i B1 = Some (set_bit w (nat i) True)" - "update_vec_dec_maybe w i BU = None" - "update_vec_dec_fail w i B0 = return (set_bit w (nat i) False)" - "update_vec_dec_fail w i B1 = return (set_bit w (nat i) True)" - "update_vec_dec_fail w i BU = Fail ''bool_of_bitU''" - "update_vec_dec_oracle w i B0 = return (set_bit w (nat i) False)" - "update_vec_dec_oracle w i B1 = return (set_bit w (nat i) True)" - "update_vec_dec_oracle w i BU = undefined_bool () \<bind> (\<lambda>b. return (set_bit w (nat i) b))" - "update_vec_dec w i B0 = set_bit w (nat i) False" - "update_vec_dec w i B1 = set_bit w (nat i) True" - unfolding update_vec_dec_maybe_def update_vec_dec_fail_def update_vec_dec_oracle_def update_vec_dec_def - by (auto simp: update_mword_dec_def update_mword_bool_dec_def maybe_failwith_def) - -lemma len_of_minus_One_minus_nonneg_lt_len_of[simp]: - "n \<ge> 0 \<Longrightarrow> nat (int LENGTH('a::len) - 1 - n) < LENGTH('a)" - by (metis diff_mono diff_zero len_gt_0 nat_eq_iff2 nat_less_iff order_refl zle_diff1_eq) - -declare extz_vec_def[simp] -declare exts_vec_def[simp] -declare concat_vec_def[simp] - -lemma msb_Bits_msb[simp]: - "msb w = bitU_of_bool (Bits.msb w)" - by (auto simp: msb_def most_significant_def BC_mword_defs word_msb_alt split: list.splits) - -declare and_vec_def[simp] -declare or_vec_def[simp] -declare xor_vec_def[simp] -declare not_vec_def[simp] - -lemma arith_vec_simps[simp]: - "add_vec l r = l + r" - "sub_vec l r = l - r" - "mult_vec l r = (ucast l) * (ucast r)" - unfolding add_vec_def sub_vec_def mult_vec_def - by (auto simp: int_of_mword_def word_add_def word_sub_wi word_mult_def) - -declare adds_vec_def[simp] -declare subs_vec_def[simp] -declare mults_vec_def[simp] - -lemma arith_vec_int_simps[simp]: - "add_vec_int l r = l + (word_of_int r)" - "sub_vec_int l r = l - (word_of_int r)" - "mult_vec_int l r = (ucast l) * (word_of_int r)" - unfolding add_vec_int_def sub_vec_int_def mult_vec_int_def - by (auto simp: arith_op_bv_int_def BC_mword_defs word_add_def word_sub_wi word_mult_def) - -end diff --git a/snapshots/isabelle/lib/sail/State.thy b/snapshots/isabelle/lib/sail/State.thy deleted file mode 100644 index 9d460e8e..00000000 --- a/snapshots/isabelle/lib/sail/State.thy +++ /dev/null @@ -1,102 +0,0 @@ -chapter \<open>Generated by Lem from ../../src/gen_lib/state.lem.\<close> - -theory "State" - -imports - Main - "Lem_pervasives_extra" - "Sail_values" - "Prompt_monad" - "Prompt" - "State_monad" - "State_monad_lemmas" - -begin - -(*open import Pervasives_extra*) -(*open import Sail_impl_base*) -(*open import Sail_values*) -(*open import Prompt_monad*) -(*open import Prompt*) -(*open import State_monad*) -(*open import {isabelle} `State_monad_lemmas`*) - -(* State monad wrapper around prompt monad *) - -(*val liftState : forall 'regval 'regs 'a 'e. register_accessors 'regs 'regval -> monad 'regval 'a 'e -> monadS 'regs 'a 'e*) -function (sequential,domintros) liftState :: "(string \<Rightarrow> 'regs \<Rightarrow> 'regval option)*(string \<Rightarrow> 'regval \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow>('regval,'a,'e)monad \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where - " liftState ra (Done a) = ( returnS a )" -|" liftState ra (Read_mem rk a sz k) = ( bindS (read_mem_bytesS - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) rk a sz) (\<lambda> v . liftState ra (k v)))" -|" liftState ra (Read_tag t k) = ( bindS (read_tagS - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) t) (\<lambda> v . liftState ra (k v)))" -|" liftState ra (Write_memv a k) = ( bindS (write_mem_bytesS a) (\<lambda> v . liftState ra (k v)))" -|" liftState ra (Write_tag a t k) = ( bindS (write_tagS - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) a t) (\<lambda> v . liftState ra (k v)))" -|" liftState ra (Read_reg r k) = ( bindS (read_regvalS ra r) (\<lambda> v . liftState ra (k v)))" -|" liftState ra (Excl_res k) = ( bindS (excl_resultS () ) (\<lambda> v . liftState ra (k v)))" -|" liftState ra (Undefined k) = ( bindS (undefined_boolS () ) (\<lambda> v . liftState ra (k v)))" -|" liftState ra (Write_ea wk a sz k) = ( seqS (write_mem_eaS - (instance_Sail_values_Bitvector_list_dict - instance_Sail_values_BitU_Sail_values_bitU_dict) wk a sz) (liftState ra k))" -|" liftState ra (Write_reg r v k) = ( seqS (write_regvalS ra r v) (liftState ra k))" -|" liftState ra (Footprint k) = ( liftState ra k )" -|" liftState ra (Barrier _ k) = ( liftState ra k )" -|" liftState ra (Print _ k) = ( liftState ra k )" -|" liftState ra (Fail descr) = ( failS descr )" -|" liftState ra (Exception e) = ( throwS e )" -by pat_completeness auto - - - -(*val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) -fun iterS_aux :: " int \<Rightarrow>(int \<Rightarrow> 'a \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monadS " where - " iterS_aux i f (x # xs) = ( seqS (f i x) (iterS_aux (i +( 1 :: int)) f xs))" -|" iterS_aux i f ([]) = ( returnS () )" - - -(*val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) -definition iteriS :: "(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monadS)\<Rightarrow> 'a list \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set " where - " iteriS f xs = ( iterS_aux(( 0 :: int)) f xs )" - - -(*val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) -definition iterS :: "('a \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set)\<Rightarrow> 'a list \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set " where - " iterS f xs = ( iteriS ( \<lambda>x . - (case x of _ => \<lambda> x . f x )) xs )" - - -(*val foreachS : forall 'a 'rv 'vars 'e. - list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) -fun foreachS :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set " where - " foreachS ([]) vars body = ( returnS vars )" -|" foreachS (x # xs) vars body = ( bindS - (body x vars) (\<lambda> vars . - foreachS xs vars body))" - - - -(*val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) -> - ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) -function (sequential,domintros) whileS :: " 'vars \<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set " where - " whileS vars cond body s = ( - ( bindS(cond vars) (\<lambda> cond_val s' . - if cond_val then - ( bindS(body vars) (\<lambda> vars s'' . whileS vars cond body s'')) s' - else returnS vars s')) s )" -by pat_completeness auto - - -(*val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) -> - ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) -function (sequential,domintros) untilS :: " 'vars \<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set " where - " untilS vars cond body s = ( - ( bindS(body vars) (\<lambda> vars s' . - ( bindS(cond vars) (\<lambda> cond_val s'' . - if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s )" -by pat_completeness auto - -end diff --git a/snapshots/isabelle/lib/sail/State_lemmas.thy b/snapshots/isabelle/lib/sail/State_lemmas.thy deleted file mode 100644 index 84b08e6c..00000000 --- a/snapshots/isabelle/lib/sail/State_lemmas.thy +++ /dev/null @@ -1,202 +0,0 @@ -theory State_lemmas - imports State -begin - -lemma All_liftState_dom: "liftState_dom (r, m)" - by (induction m) (auto intro: liftState.domintros) -termination liftState using All_liftState_dom by auto - -lemma liftState_bind[simp]: - "liftState r (bind m f) = bindS (liftState r m) (liftState r \<circ> f)" - by (induction m f rule: bind.induct) auto - -lemma liftState_return[simp]: "liftState r (return a) = returnS a" by (auto simp: return_def) - -lemma Value_liftState_Run: - assumes "(Value a, s') \<in> liftState r m s" - obtains t where "Run m t a" - by (use assms in \<open>induction r m arbitrary: s s' rule: liftState.induct\<close>; - auto simp add: failS_def throwS_def returnS_def simp del: read_regvalS.simps; - blast elim: Value_bindS_elim) - -lemmas liftState_if_distrib[simp] = if_distrib[where f = "liftState ra" for ra] - -lemma liftState_throw[simp]: "liftState r (throw e) = throwS e" by (auto simp: throw_def) -lemma liftState_assert[simp]: "liftState r (assert_exp c msg) = assert_expS c msg" by (auto simp: assert_exp_def assert_expS_def) -lemma liftState_exit[simp]: "liftState r (exit0 ()) = exitS ()" by (auto simp: exit0_def exitS_def) -lemma liftState_exclResult[simp]: "liftState r (excl_result ()) = excl_resultS ()" by (auto simp: excl_result_def) -lemma liftState_barrier[simp]: "liftState r (barrier bk) = returnS ()" by (auto simp: barrier_def) -lemma liftState_footprint[simp]: "liftState r (footprint ()) = returnS ()" by (auto simp: footprint_def) -lemma liftState_undefined[simp]: "liftState r (undefined_bool ()) = undefined_boolS ()" by (auto simp: undefined_bool_def) -lemma liftState_maybe_fail[simp]: "liftState r (maybe_fail msg x) = maybe_failS msg x" - by (auto simp: maybe_fail_def maybe_failS_def split: option.splits) - -lemma liftState_try_catch[simp]: - "liftState r (try_catch m h) = try_catchS (liftState r m) (liftState r \<circ> h)" - by (induction m h rule: try_catch_induct) (auto simp: try_catchS_bindS_no_throw) - -lemma liftState_early_return[simp]: - "liftState r (early_return r) = early_returnS r" - by (auto simp: early_return_def early_returnS_def) - -lemma liftState_catch_early_return[simp]: - "liftState r (catch_early_return m) = catch_early_returnS (liftState r m)" - by (auto simp: catch_early_return_def catch_early_returnS_def sum.case_distrib cong: sum.case_cong) - -lemma liftState_liftR[simp]: - "liftState r (liftR m) = liftSR (liftState r m)" - by (auto simp: liftR_def liftSR_def) - -lemma liftState_try_catchR[simp]: - "liftState r (try_catchR m h) = try_catchSR (liftState r m) (liftState r \<circ> h)" - by (auto simp: try_catchR_def try_catchSR_def sum.case_distrib cong: sum.case_cong) - -lemma liftState_read_mem_BC: - assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a" - shows "liftState r (read_mem BCa BCb rk a sz) = read_memS BCa BCb rk a sz" - using assms - by (auto simp: read_mem_def read_mem_bytes_def read_memS_def read_mem_bytesS_def maybe_failS_def split: option.splits) - -lemma liftState_read_mem[simp]: - "\<And>a. liftState r (read_mem BC_mword BC_mword rk a sz) = read_memS BC_mword BC_mword rk a sz" - "\<And>a. liftState r (read_mem BC_bitU_list BC_bitU_list rk a sz) = read_memS BC_bitU_list BC_bitU_list rk a sz" - by (auto simp: liftState_read_mem_BC) - -lemma liftState_write_mem_ea_BC: - assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a" - shows "liftState r (write_mem_ea BCa rk a sz) = write_mem_eaS BCa rk a (nat sz)" - using assms by (auto simp: write_mem_ea_def write_mem_eaS_def) - -lemma liftState_write_mem_ea[simp]: - "\<And>a. liftState r (write_mem_ea BC_mword rk a sz) = write_mem_eaS BC_mword rk a (nat sz)" - "\<And>a. liftState r (write_mem_ea BC_bitU_list rk a sz) = write_mem_eaS BC_bitU_list rk a (nat sz)" - by (auto simp: liftState_write_mem_ea_BC) - -lemma liftState_write_mem_val: - "liftState r (write_mem_val BC v) = write_mem_valS BC v" - by (auto simp: write_mem_val_def write_mem_valS_def split: option.splits) - -lemma liftState_read_reg_readS: - assumes "\<And>s. Option.bind (get_regval' (name reg) s) (of_regval reg) = Some (read_from reg s)" - shows "liftState (get_regval', set_regval') (read_reg reg) = readS (read_from reg \<circ> regstate)" -proof - fix s :: "'a sequential_state" - obtain rv v where "get_regval' (name reg) (regstate s) = Some rv" - and "of_regval reg rv \<equiv> Some v" and "read_from reg (regstate s) = v" - using assms unfolding bind_eq_Some_conv by blast - then show "liftState (get_regval', set_regval') (read_reg reg) s = readS (read_from reg \<circ> regstate) s" - by (auto simp: read_reg_def bindS_def returnS_def read_regS_def readS_def) -qed - -lemma liftState_write_reg_updateS: - assumes "\<And>s. set_regval' (name reg) (regval_of reg v) s = Some (write_to reg v s)" - shows "liftState (get_regval', set_regval') (write_reg reg v) = updateS (regstate_update (write_to reg v))" - using assms by (auto simp: write_reg_def updateS_def returnS_def bindS_readS) - -lemma liftState_iter_aux[simp]: - shows "liftState r (iter_aux i f xs) = iterS_aux i (\<lambda>i x. liftState r (f i x)) xs" - by (induction i "\<lambda>i x. liftState r (f i x)" xs rule: iterS_aux.induct) (auto cong: bindS_cong) - -lemma liftState_iteri[simp]: - "liftState r (iteri f xs) = iteriS (\<lambda>i x. liftState r (f i x)) xs" - by (auto simp: iteri_def iteriS_def) - -lemma liftState_iter[simp]: - "liftState r (iter f xs) = iterS (liftState r \<circ> f) xs" - by (auto simp: iter_def iterS_def) - -lemma liftState_foreachM[simp]: - "liftState r (foreachM xs vars body) = foreachS xs vars (\<lambda>x vars. liftState r (body x vars))" - by (induction xs vars "\<lambda>x vars. liftState r (body x vars)" rule: foreachS.induct) - (auto cong: bindS_cong) - -lemma whileS_dom_step: - assumes "whileS_dom (vars, cond, body, s)" - and "(Value True, s') \<in> cond vars s" - and "(Value vars', s'') \<in> body vars s'" - shows "whileS_dom (vars', cond, body, s'')" - by (use assms in \<open>induction vars cond body s arbitrary: vars' s' s'' rule: whileS.pinduct\<close>) - (auto intro: whileS.domintros) - -lemma whileM_dom_step: - assumes "whileM_dom (vars, cond, body)" - and "Run (cond vars) t True" - and "Run (body vars) t' vars'" - shows "whileM_dom (vars', cond, body)" - by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: whileM.pinduct\<close>) - (auto intro: whileM.domintros) - -lemma whileM_dom_ex_step: - assumes "whileM_dom (vars, cond, body)" - and "\<exists>t. Run (cond vars) t True" - and "\<exists>t'. Run (body vars) t' vars'" - shows "whileM_dom (vars', cond, body)" - using assms by (blast intro: whileM_dom_step) - -lemmas whileS_pinduct = whileS.pinduct[case_names Step] - -lemma liftState_whileM: - assumes "whileS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)" - and "whileM_dom (vars, cond, body)" - shows "liftState r (whileM vars cond body) s = whileS vars (liftState r \<circ> cond) (liftState r \<circ> body) s" -proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: whileS.pinduct\<close>) - case Step: (1 vars s) - note domS = Step(1) and IH = Step(2) and domM = Step(3) - show ?case unfolding whileS.psimps[OF domS] whileM.psimps[OF domM] liftState_bind - proof (intro bindS_ext_cong, goal_cases cond while) - case (while a s') - have "bindS (liftState r (body vars)) (liftState r \<circ> (\<lambda>vars. whileM vars cond body)) s' = - bindS (liftState r (body vars)) (\<lambda>vars. whileS vars (liftState r \<circ> cond) (liftState r \<circ> body)) s'" - if "a" - proof (intro bindS_ext_cong, goal_cases body while') - case (while' vars' s'') - have "whileM_dom (vars', cond, body)" proof (rule whileM_dom_ex_step[OF domM]) - show "\<exists>t. Run (cond vars) t True" using while that by (auto elim: Value_liftState_Run) - show "\<exists>t'. Run (body vars) t' vars'" using while' that by (auto elim: Value_liftState_Run) - qed - then show ?case using while while' that IH by auto - qed auto - then show ?case by auto - qed auto -qed - - -lemma untilM_dom_step: - assumes "untilM_dom (vars, cond, body)" - and "Run (body vars) t vars'" - and "Run (cond vars') t' False" - shows "untilM_dom (vars', cond, body)" - by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: untilM.pinduct\<close>) - (auto intro: untilM.domintros) - -lemma untilM_dom_ex_step: - assumes "untilM_dom (vars, cond, body)" - and "\<exists>t. Run (body vars) t vars'" - and "\<exists>t'. Run (cond vars') t' False" - shows "untilM_dom (vars', cond, body)" - using assms by (blast intro: untilM_dom_step) - -lemma liftState_untilM: - assumes "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)" - and "untilM_dom (vars, cond, body)" - shows "liftState r (untilM vars cond body) s = untilS vars (liftState r \<circ> cond) (liftState r \<circ> body) s" -proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: untilS.pinduct\<close>) - case Step: (1 vars s) - note domS = Step(1) and IH = Step(2) and domM = Step(3) - show ?case unfolding untilS.psimps[OF domS] untilM.psimps[OF domM] liftState_bind - proof (intro bindS_ext_cong, goal_cases body k) - case (k vars' s') - show ?case unfolding comp_def liftState_bind - proof (intro bindS_ext_cong, goal_cases cond until) - case (until a s'') - have "untilM_dom (vars', cond, body)" if "\<not>a" - proof (rule untilM_dom_ex_step[OF domM]) - show "\<exists>t. Run (body vars) t vars'" using k by (auto elim: Value_liftState_Run) - show "\<exists>t'. Run (cond vars') t' False" using until that by (auto elim: Value_liftState_Run) - qed - then show ?case using k until IH by (auto simp: comp_def) - qed auto - qed auto -qed - -end diff --git a/snapshots/isabelle/riscv/Riscv.thy b/snapshots/isabelle/riscv/Riscv.thy index 71873cec..754caaf5 100644 --- a/snapshots/isabelle/riscv/Riscv.thy +++ b/snapshots/isabelle/riscv/Riscv.thy @@ -5,12 +5,12 @@ theory "Riscv" imports Main "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" - "Sail_operators_mwords" - "Prompt_monad" - "Prompt" - "State" + "Sail2_instr_kinds" + "Sail2_values" + "Sail2_operators_mwords" + "Sail2_prompt_monad" + "Sail2_prompt" + "Sail2_string" "Riscv_types" "Riscv_extras" @@ -18,15 +18,51 @@ begin (*Generated by Sail from riscv.*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) -(*open import State*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) (*open import Riscv_types*) (*open import Riscv_extras*) +(*val spc_forwards : unit -> string*) + +definition spc_forwards :: " unit \<Rightarrow> string " where + " spc_forwards _ = ( ('' ''))" + + +(*val spc_backwards : string -> unit*) + +definition spc_backwards :: " string \<Rightarrow> unit " where + " spc_backwards s = ( () )" + + +(*val opt_spc_forwards : unit -> string*) + +definition opt_spc_forwards :: " unit \<Rightarrow> string " where + " opt_spc_forwards _ = ( (''''))" + + +(*val opt_spc_backwards : string -> unit*) + +definition opt_spc_backwards :: " string \<Rightarrow> unit " where + " opt_spc_backwards s = ( () )" + + +(*val def_spc_forwards : unit -> string*) + +definition def_spc_forwards :: " unit \<Rightarrow> string " where + " def_spc_forwards _ = ( ('' ''))" + + +(*val def_spc_backwards : string -> unit*) + +definition def_spc_backwards :: " string \<Rightarrow> unit " where + " def_spc_backwards s = ( () )" + + @@ -48,7 +84,7 @@ begin (*val __GetSlice_int : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*) definition GetSlice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where - " GetSlice_int n m o1 = ( (get_slice_int0 n m o1 :: ( 'n::len)Word.word))" + " GetSlice_int n m o1 = ( (get_slice_int n m o1 :: ( 'n::len)Word.word))" (*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*) @@ -80,17 +116,59 @@ definition RISCV_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_ (*val __TraceMemoryWrite : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) -(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (maybe (mword 'int8_times_n))*) +(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (maybe (mword 'int8_times_n))*) -definition RISCV_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)option),(exception))monad " where - " RISCV_read addr width = ( - (read_ram (( 64 :: int)::ii) width - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word) addr - :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'int8_times_n::len)Word.word) . - return (Some w__0)))" +fun RISCV_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)option),(exception))monad " where + " RISCV_read addr width False False False = ( + (MEMr (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'int8_times_n::len)Word.word) . + return (Some w__0)))" +|" RISCV_read addr width True False False = ( + (MEMr_acquire (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__1 :: ( 'int8_times_n::len)Word.word) . + return (Some w__1)))" +|" RISCV_read addr width True True False = ( + (MEMr_strong_acquire (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__2 :: ( 'int8_times_n::len)Word.word) . + return (Some w__2)))" +|" RISCV_read addr width False False True = ( + (MEMr_reserved (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__3 :: ( 'int8_times_n::len)Word.word) . + return (Some w__3)))" +|" RISCV_read addr width True False True = ( + (MEMr_reserved_acquire (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__4 :: ( 'int8_times_n::len)Word.word) . + return (Some w__4)))" +|" RISCV_read addr width True True True = ( + (MEMr_reserved_strong_acquire (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__5 :: ( 'int8_times_n::len)Word.word) . + return (Some w__5)))" +|" RISCV_read addr width False True False = ( return None )" +|" RISCV_read addr width False True True = ( return None )" (*val __TraceMemoryRead : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) @@ -171,13 +249,13 @@ fun bit_to_bool :: " bitU \<Rightarrow> bool " where (*val vector64 : ii -> mword ty64*) definition vector64 :: " int \<Rightarrow>(64)Word.word " where - " vector64 n = ( (get_slice_int0 (( 64 :: int)::ii) n (( 0 :: int)::ii) :: 64 Word.word))" + " vector64 n = ( (get_slice_int (( 64 :: int)::ii) n (( 0 :: int)::ii) :: 64 Word.word))" (*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*) definition to_bits :: " int \<Rightarrow> int \<Rightarrow>('l::len)Word.word " where - " to_bits l n = ( (get_slice_int0 l n (( 0 :: int)::ii) :: ( 'l::len)Word.word))" + " to_bits l n = ( (get_slice_int l n (( 0 :: int)::ii) :: ( 'l::len)Word.word))" (*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*) @@ -241,29 +319,89 @@ definition sp :: "(5)Word.word " where (*val rX : integer -> M (mword ty64)*) definition rX :: " int \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where - " rX l__81 = ( - if (((l__81 = (( 0 :: int)::ii)))) then + " rX r = ( + (let p00 = r in + if (((p00 = (( 0 :: int)::ii)))) then return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word) - else - read_reg Xs_ref \<bind> (\<lambda> (w__0 :: xlenbits list) . - return ((access_list_dec w__0 l__81 :: 64 Word.word))))" + else if (((p00 = (( 1 :: int)::ii)))) then (read_reg x1_ref :: ( 64 Word.word) M) + else if (((p00 = (( 2 :: int)::ii)))) then (read_reg x2_ref :: ( 64 Word.word) M) + else if (((p00 = (( 3 :: int)::ii)))) then (read_reg x3_ref :: ( 64 Word.word) M) + else if (((p00 = (( 4 :: int)::ii)))) then (read_reg x4_ref :: ( 64 Word.word) M) + else if (((p00 = (( 5 :: int)::ii)))) then (read_reg x5_ref :: ( 64 Word.word) M) + else if (((p00 = (( 6 :: int)::ii)))) then (read_reg x6_ref :: ( 64 Word.word) M) + else if (((p00 = (( 7 :: int)::ii)))) then (read_reg x7_ref :: ( 64 Word.word) M) + else if (((p00 = (( 8 :: int)::ii)))) then (read_reg x8_ref :: ( 64 Word.word) M) + else if (((p00 = (( 9 :: int)::ii)))) then (read_reg x9_ref :: ( 64 Word.word) M) + else if (((p00 = (( 10 :: int)::ii)))) then (read_reg x10_ref :: ( 64 Word.word) M) + else if (((p00 = (( 11 :: int)::ii)))) then (read_reg x11_ref :: ( 64 Word.word) M) + else if (((p00 = (( 12 :: int)::ii)))) then (read_reg x12_ref :: ( 64 Word.word) M) + else if (((p00 = (( 13 :: int)::ii)))) then (read_reg x13_ref :: ( 64 Word.word) M) + else if (((p00 = (( 14 :: int)::ii)))) then (read_reg x14_ref :: ( 64 Word.word) M) + else if (((p00 = (( 15 :: int)::ii)))) then (read_reg x15_ref :: ( 64 Word.word) M) + else if (((p00 = (( 16 :: int)::ii)))) then (read_reg x16_ref :: ( 64 Word.word) M) + else if (((p00 = (( 17 :: int)::ii)))) then (read_reg x17_ref :: ( 64 Word.word) M) + else if (((p00 = (( 18 :: int)::ii)))) then (read_reg x18_ref :: ( 64 Word.word) M) + else if (((p00 = (( 19 :: int)::ii)))) then (read_reg x19_ref :: ( 64 Word.word) M) + else if (((p00 = (( 20 :: int)::ii)))) then (read_reg x20_ref :: ( 64 Word.word) M) + else if (((p00 = (( 21 :: int)::ii)))) then (read_reg x21_ref :: ( 64 Word.word) M) + else if (((p00 = (( 22 :: int)::ii)))) then (read_reg x22_ref :: ( 64 Word.word) M) + else if (((p00 = (( 23 :: int)::ii)))) then (read_reg x23_ref :: ( 64 Word.word) M) + else if (((p00 = (( 24 :: int)::ii)))) then (read_reg x24_ref :: ( 64 Word.word) M) + else if (((p00 = (( 25 :: int)::ii)))) then (read_reg x25_ref :: ( 64 Word.word) M) + else if (((p00 = (( 26 :: int)::ii)))) then (read_reg x26_ref :: ( 64 Word.word) M) + else if (((p00 = (( 27 :: int)::ii)))) then (read_reg x27_ref :: ( 64 Word.word) M) + else if (((p00 = (( 28 :: int)::ii)))) then (read_reg x28_ref :: ( 64 Word.word) M) + else if (((p00 = (( 29 :: int)::ii)))) then (read_reg x29_ref :: ( 64 Word.word) M) + else if (((p00 = (( 30 :: int)::ii)))) then (read_reg x30_ref :: ( 64 Word.word) M) + else (read_reg x31_ref :: ( 64 Word.word) M)))" (*val wX : integer -> mword ty64 -> M unit*) definition wX :: " int \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " wX r v = ( - if (((r \<noteq> (( 0 :: int)::ii)))) then - read_reg Xs_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . - write_reg Xs_ref ((update_list_dec w__0 r v :: ( 64 Word.word) list)) \<then> - return ((prerr_endline - (((op@) (''x'') - (((op@) ((stringFromInteger r)) - (((op@) ('' <- '') ((string_of_vec v))))))))))) - else return () )" + (let p00 = r in + (if (((p00 = (( 0 :: int)::ii)))) then return () + else if (((p00 = (( 1 :: int)::ii)))) then write_reg x1_ref v + else if (((p00 = (( 2 :: int)::ii)))) then write_reg x2_ref v + else if (((p00 = (( 3 :: int)::ii)))) then write_reg x3_ref v + else if (((p00 = (( 4 :: int)::ii)))) then write_reg x4_ref v + else if (((p00 = (( 5 :: int)::ii)))) then write_reg x5_ref v + else if (((p00 = (( 6 :: int)::ii)))) then write_reg x6_ref v + else if (((p00 = (( 7 :: int)::ii)))) then write_reg x7_ref v + else if (((p00 = (( 8 :: int)::ii)))) then write_reg x8_ref v + else if (((p00 = (( 9 :: int)::ii)))) then write_reg x9_ref v + else if (((p00 = (( 10 :: int)::ii)))) then write_reg x10_ref v + else if (((p00 = (( 11 :: int)::ii)))) then write_reg x11_ref v + else if (((p00 = (( 12 :: int)::ii)))) then write_reg x12_ref v + else if (((p00 = (( 13 :: int)::ii)))) then write_reg x13_ref v + else if (((p00 = (( 14 :: int)::ii)))) then write_reg x14_ref v + else if (((p00 = (( 15 :: int)::ii)))) then write_reg x15_ref v + else if (((p00 = (( 16 :: int)::ii)))) then write_reg x16_ref v + else if (((p00 = (( 17 :: int)::ii)))) then write_reg x17_ref v + else if (((p00 = (( 18 :: int)::ii)))) then write_reg x18_ref v + else if (((p00 = (( 19 :: int)::ii)))) then write_reg x19_ref v + else if (((p00 = (( 20 :: int)::ii)))) then write_reg x20_ref v + else if (((p00 = (( 21 :: int)::ii)))) then write_reg x21_ref v + else if (((p00 = (( 22 :: int)::ii)))) then write_reg x22_ref v + else if (((p00 = (( 23 :: int)::ii)))) then write_reg x23_ref v + else if (((p00 = (( 24 :: int)::ii)))) then write_reg x24_ref v + else if (((p00 = (( 25 :: int)::ii)))) then write_reg x25_ref v + else if (((p00 = (( 26 :: int)::ii)))) then write_reg x26_ref v + else if (((p00 = (( 27 :: int)::ii)))) then write_reg x27_ref v + else if (((p00 = (( 28 :: int)::ii)))) then write_reg x28_ref v + else if (((p00 = (( 29 :: int)::ii)))) then write_reg x29_ref v + else if (((p00 = (( 30 :: int)::ii)))) then write_reg x30_ref v + else write_reg x31_ref v) \<then> + return (if (((r \<noteq> (( 0 :: int)::ii)))) then + print_endline + (((op@) (''x'') + (((op@) ((stringFromInteger r)) + (((op@) ('' <- '') ((string_of_bits v)))))))) + else () )))" (*val reg_name_abi : mword ty5 -> string*) @@ -340,9 +478,9 @@ definition reg_name_abi :: "(5)Word.word \<Rightarrow> string " where definition Architecture_of_num :: " int \<Rightarrow> Architecture " where " Architecture_of_num arg0 = ( - (let l__79 = arg0 in - if (((l__79 = (( 0 :: int)::ii)))) then RV32 - else if (((l__79 = (( 1 :: int)::ii)))) then RV64 + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then RV32 + else if (((p00 = (( 1 :: int)::ii)))) then RV64 else RV128))" @@ -377,9 +515,9 @@ fun arch_to_bits :: " Architecture \<Rightarrow>(2)Word.word " where definition Privilege_of_num :: " int \<Rightarrow> Privilege " where " Privilege_of_num arg0 = ( - (let l__77 = arg0 in - if (((l__77 = (( 0 :: int)::ii)))) then User - else if (((l__77 = (( 1 :: int)::ii)))) then Supervisor + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then User + else if (((p00 = (( 1 :: int)::ii)))) then Supervisor else Machine))" @@ -421,10 +559,10 @@ fun privLevel_to_str :: " Privilege \<Rightarrow> string " where definition AccessType_of_num :: " int \<Rightarrow> AccessType " where " AccessType_of_num arg0 = ( - (let l__74 = arg0 in - if (((l__74 = (( 0 :: int)::ii)))) then Read - else if (((l__74 = (( 1 :: int)::ii)))) then Write - else if (((l__74 = (( 2 :: int)::ii)))) then ReadWrite + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Read + else if (((p00 = (( 1 :: int)::ii)))) then Write + else if (((p00 = (( 2 :: int)::ii)))) then ReadWrite else Execute))" @@ -437,12 +575,21 @@ fun num_of_AccessType :: " AccessType \<Rightarrow> int " where |" num_of_AccessType Execute = ( (( 3 :: int)::ii))" +(*val accessType_to_str : AccessType -> string*) + +fun accessType_to_str :: " AccessType \<Rightarrow> string " where + " accessType_to_str Read = ( (''R''))" +|" accessType_to_str Write = ( (''W''))" +|" accessType_to_str ReadWrite = ( (''RW''))" +|" accessType_to_str Execute = ( (''X''))" + + (*val ReadType_of_num : integer -> ReadType*) definition ReadType_of_num :: " int \<Rightarrow> ReadType " where " ReadType_of_num arg0 = ( - (let l__73 = arg0 in - if (((l__73 = (( 0 :: int)::ii)))) then Instruction + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Instruction else Data))" @@ -453,26 +600,33 @@ fun num_of_ReadType :: " ReadType \<Rightarrow> int " where |" num_of_ReadType Data = ( (( 1 :: int)::ii))" +(*val readType_to_str : ReadType -> string*) + +fun readType_to_str :: " ReadType \<Rightarrow> string " where + " readType_to_str Instruction = ( (''I''))" +|" readType_to_str Data = ( (''D''))" + + (*val ExceptionType_of_num : integer -> ExceptionType*) definition ExceptionType_of_num :: " int \<Rightarrow> ExceptionType " where " ExceptionType_of_num arg0 = ( - (let l__58 = arg0 in - if (((l__58 = (( 0 :: int)::ii)))) then E_Fetch_Addr_Align - else if (((l__58 = (( 1 :: int)::ii)))) then E_Fetch_Access_Fault - else if (((l__58 = (( 2 :: int)::ii)))) then E_Illegal_Instr - else if (((l__58 = (( 3 :: int)::ii)))) then E_Breakpoint - else if (((l__58 = (( 4 :: int)::ii)))) then E_Load_Addr_Align - else if (((l__58 = (( 5 :: int)::ii)))) then E_Load_Access_Fault - else if (((l__58 = (( 6 :: int)::ii)))) then E_SAMO_Addr_Align - else if (((l__58 = (( 7 :: int)::ii)))) then E_SAMO_Access_Fault - else if (((l__58 = (( 8 :: int)::ii)))) then E_U_EnvCall - else if (((l__58 = (( 9 :: int)::ii)))) then E_S_EnvCall - else if (((l__58 = (( 10 :: int)::ii)))) then E_Reserved_10 - else if (((l__58 = (( 11 :: int)::ii)))) then E_M_EnvCall - else if (((l__58 = (( 12 :: int)::ii)))) then E_Fetch_Page_Fault - else if (((l__58 = (( 13 :: int)::ii)))) then E_Load_Page_Fault - else if (((l__58 = (( 14 :: int)::ii)))) then E_Reserved_14 + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then E_Fetch_Addr_Align + else if (((p00 = (( 1 :: int)::ii)))) then E_Fetch_Access_Fault + else if (((p00 = (( 2 :: int)::ii)))) then E_Illegal_Instr + else if (((p00 = (( 3 :: int)::ii)))) then E_Breakpoint + else if (((p00 = (( 4 :: int)::ii)))) then E_Load_Addr_Align + else if (((p00 = (( 5 :: int)::ii)))) then E_Load_Access_Fault + else if (((p00 = (( 6 :: int)::ii)))) then E_SAMO_Addr_Align + else if (((p00 = (( 7 :: int)::ii)))) then E_SAMO_Access_Fault + else if (((p00 = (( 8 :: int)::ii)))) then E_U_EnvCall + else if (((p00 = (( 9 :: int)::ii)))) then E_S_EnvCall + else if (((p00 = (( 10 :: int)::ii)))) then E_Reserved_10 + else if (((p00 = (( 11 :: int)::ii)))) then E_M_EnvCall + else if (((p00 = (( 12 :: int)::ii)))) then E_Fetch_Page_Fault + else if (((p00 = (( 13 :: int)::ii)))) then E_Load_Page_Fault + else if (((p00 = (( 14 :: int)::ii)))) then E_Reserved_14 else E_SAMO_Page_Fault))" @@ -521,7 +675,7 @@ fun exceptionType_to_bits :: " ExceptionType \<Rightarrow>(4)Word.word " where (*val exceptionType_to_str : ExceptionType -> string*) fun exceptionType_to_str :: " ExceptionType \<Rightarrow> string " where - " exceptionType_to_str E_Fetch_Addr_Align = ( (''fisaligned-fetch''))" + " exceptionType_to_str E_Fetch_Addr_Align = ( (''misaligned-fetch''))" |" exceptionType_to_str E_Fetch_Access_Fault = ( (''fetch-access-fault''))" |" exceptionType_to_str E_Illegal_Instr = ( (''illegal-instruction''))" |" exceptionType_to_str E_Breakpoint = ( (''breakpoint''))" @@ -543,15 +697,15 @@ fun exceptionType_to_str :: " ExceptionType \<Rightarrow> string " where definition InterruptType_of_num :: " int \<Rightarrow> InterruptType " where " InterruptType_of_num arg0 = ( - (let l__50 = arg0 in - if (((l__50 = (( 0 :: int)::ii)))) then I_U_Software - else if (((l__50 = (( 1 :: int)::ii)))) then I_S_Software - else if (((l__50 = (( 2 :: int)::ii)))) then I_M_Software - else if (((l__50 = (( 3 :: int)::ii)))) then I_U_Timer - else if (((l__50 = (( 4 :: int)::ii)))) then I_S_Timer - else if (((l__50 = (( 5 :: int)::ii)))) then I_M_Timer - else if (((l__50 = (( 6 :: int)::ii)))) then I_U_External - else if (((l__50 = (( 7 :: int)::ii)))) then I_S_External + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then I_U_Software + else if (((p00 = (( 1 :: int)::ii)))) then I_S_Software + else if (((p00 = (( 2 :: int)::ii)))) then I_M_Software + else if (((p00 = (( 3 :: int)::ii)))) then I_U_Timer + else if (((p00 = (( 4 :: int)::ii)))) then I_S_Timer + else if (((p00 = (( 5 :: int)::ii)))) then I_M_Timer + else if (((p00 = (( 6 :: int)::ii)))) then I_U_External + else if (((p00 = (( 7 :: int)::ii)))) then I_S_External else I_M_External))" @@ -587,9 +741,9 @@ fun interruptType_to_bits :: " InterruptType \<Rightarrow>(4)Word.word " where definition TrapVectorMode_of_num :: " int \<Rightarrow> TrapVectorMode " where " TrapVectorMode_of_num arg0 = ( - (let l__48 = arg0 in - if (((l__48 = (( 0 :: int)::ii)))) then TV_Direct - else if (((l__48 = (( 1 :: int)::ii)))) then TV_Vector + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then TV_Direct + else if (((p00 = (( 1 :: int)::ii)))) then TV_Vector else TV_Reserved))" @@ -627,10 +781,10 @@ definition internal_error :: " string \<Rightarrow>((register_value),'a,(except definition ExtStatus_of_num :: " int \<Rightarrow> ExtStatus " where " ExtStatus_of_num arg0 = ( - (let l__45 = arg0 in - if (((l__45 = (( 0 :: int)::ii)))) then Off - else if (((l__45 = (( 1 :: int)::ii)))) then Initial - else if (((l__45 = (( 2 :: int)::ii)))) then Clean + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Off + else if (((p00 = (( 1 :: int)::ii)))) then Initial + else if (((p00 = (( 2 :: int)::ii)))) then Clean else Dirty))" @@ -667,9 +821,9 @@ definition extStatus_of_bits :: "(2)Word.word \<Rightarrow> ExtStatus " where definition SATPMode_of_num :: " int \<Rightarrow> SATPMode " where " SATPMode_of_num arg0 = ( - (let l__43 = arg0 in - if (((l__43 = (( 0 :: int)::ii)))) then Sbare - else if (((l__43 = (( 1 :: int)::ii)))) then Sv32 + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Sbare + else if (((p00 = (( 1 :: int)::ii)))) then Sv32 else Sv39))" @@ -684,15 +838,26 @@ fun num_of_SATPMode :: " SATPMode \<Rightarrow> int " where (*val satpMode_of_bits : Architecture -> mword ty4 -> maybe SATPMode*) definition satpMode_of_bits :: " Architecture \<Rightarrow>(4)Word.word \<Rightarrow>(SATPMode)option " where - " satpMode_of_bits (g__113 :: Architecture) (b__0 :: satp_mode) = ( Some Sbare )" + " satpMode_of_bits (g__33 :: Architecture) (b__0 :: satp_mode) = ( + if (((b__0 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) then Some Sbare + else + (case (g__33, b__0) of + (RV32, b__1) => + if (((b__1 = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word)))) then Some Sv32 + else (case (RV32, b__1) of (g__34, g__35) => None ) + | (RV64, b__2) => + if (((b__2 = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) then Some Sv39 + else (case (RV64, b__2) of (g__34, g__35) => None ) + | (g__34, g__35) => None + ))" (*val uop_of_num : integer -> uop*) definition uop_of_num :: " int \<Rightarrow> uop " where " uop_of_num arg0 = ( - (let l__42 = arg0 in - if (((l__42 = (( 0 :: int)::ii)))) then RISCV_LUI + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then RISCV_LUI else RISCV_AUIPC))" @@ -707,12 +872,12 @@ fun num_of_uop :: " uop \<Rightarrow> int " where definition bop_of_num :: " int \<Rightarrow> bop " where " bop_of_num arg0 = ( - (let l__37 = arg0 in - if (((l__37 = (( 0 :: int)::ii)))) then RISCV_BEQ - else if (((l__37 = (( 1 :: int)::ii)))) then RISCV_BNE - else if (((l__37 = (( 2 :: int)::ii)))) then RISCV_BLT - else if (((l__37 = (( 3 :: int)::ii)))) then RISCV_BGE - else if (((l__37 = (( 4 :: int)::ii)))) then RISCV_BLTU + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then RISCV_BEQ + else if (((p00 = (( 1 :: int)::ii)))) then RISCV_BNE + else if (((p00 = (( 2 :: int)::ii)))) then RISCV_BLT + else if (((p00 = (( 3 :: int)::ii)))) then RISCV_BGE + else if (((p00 = (( 4 :: int)::ii)))) then RISCV_BLTU else RISCV_BGEU))" @@ -731,12 +896,12 @@ fun num_of_bop :: " bop \<Rightarrow> int " where definition iop_of_num :: " int \<Rightarrow> iop " where " iop_of_num arg0 = ( - (let l__32 = arg0 in - if (((l__32 = (( 0 :: int)::ii)))) then RISCV_ADDI - else if (((l__32 = (( 1 :: int)::ii)))) then RISCV_SLTI - else if (((l__32 = (( 2 :: int)::ii)))) then RISCV_SLTIU - else if (((l__32 = (( 3 :: int)::ii)))) then RISCV_XORI - else if (((l__32 = (( 4 :: int)::ii)))) then RISCV_ORI + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then RISCV_ADDI + else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SLTI + else if (((p00 = (( 2 :: int)::ii)))) then RISCV_SLTIU + else if (((p00 = (( 3 :: int)::ii)))) then RISCV_XORI + else if (((p00 = (( 4 :: int)::ii)))) then RISCV_ORI else RISCV_ANDI))" @@ -755,9 +920,9 @@ fun num_of_iop :: " iop \<Rightarrow> int " where definition sop_of_num :: " int \<Rightarrow> sop " where " sop_of_num arg0 = ( - (let l__30 = arg0 in - if (((l__30 = (( 0 :: int)::ii)))) then RISCV_SLLI - else if (((l__30 = (( 1 :: int)::ii)))) then RISCV_SRLI + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then RISCV_SLLI + else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SRLI else RISCV_SRAI))" @@ -773,16 +938,16 @@ fun num_of_sop :: " sop \<Rightarrow> int " where definition rop_of_num :: " int \<Rightarrow> rop " where " rop_of_num arg0 = ( - (let l__21 = arg0 in - if (((l__21 = (( 0 :: int)::ii)))) then RISCV_ADD - else if (((l__21 = (( 1 :: int)::ii)))) then RISCV_SUB - else if (((l__21 = (( 2 :: int)::ii)))) then RISCV_SLL - else if (((l__21 = (( 3 :: int)::ii)))) then RISCV_SLT - else if (((l__21 = (( 4 :: int)::ii)))) then RISCV_SLTU - else if (((l__21 = (( 5 :: int)::ii)))) then RISCV_XOR - else if (((l__21 = (( 6 :: int)::ii)))) then RISCV_SRL - else if (((l__21 = (( 7 :: int)::ii)))) then RISCV_SRA - else if (((l__21 = (( 8 :: int)::ii)))) then RISCV_OR + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then RISCV_ADD + else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SUB + else if (((p00 = (( 2 :: int)::ii)))) then RISCV_SLL + else if (((p00 = (( 3 :: int)::ii)))) then RISCV_SLT + else if (((p00 = (( 4 :: int)::ii)))) then RISCV_SLTU + else if (((p00 = (( 5 :: int)::ii)))) then RISCV_XOR + else if (((p00 = (( 6 :: int)::ii)))) then RISCV_SRL + else if (((p00 = (( 7 :: int)::ii)))) then RISCV_SRA + else if (((p00 = (( 8 :: int)::ii)))) then RISCV_OR else RISCV_AND))" @@ -805,11 +970,11 @@ fun num_of_rop :: " rop \<Rightarrow> int " where definition ropw_of_num :: " int \<Rightarrow> ropw " where " ropw_of_num arg0 = ( - (let l__17 = arg0 in - if (((l__17 = (( 0 :: int)::ii)))) then RISCV_ADDW - else if (((l__17 = (( 1 :: int)::ii)))) then RISCV_SUBW - else if (((l__17 = (( 2 :: int)::ii)))) then RISCV_SLLW - else if (((l__17 = (( 3 :: int)::ii)))) then RISCV_SRLW + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then RISCV_ADDW + else if (((p00 = (( 1 :: int)::ii)))) then RISCV_SUBW + else if (((p00 = (( 2 :: int)::ii)))) then RISCV_SLLW + else if (((p00 = (( 3 :: int)::ii)))) then RISCV_SRLW else RISCV_SRAW))" @@ -827,15 +992,15 @@ fun num_of_ropw :: " ropw \<Rightarrow> int " where definition amoop_of_num :: " int \<Rightarrow> amoop " where " amoop_of_num arg0 = ( - (let l__9 = arg0 in - if (((l__9 = (( 0 :: int)::ii)))) then AMOSWAP - else if (((l__9 = (( 1 :: int)::ii)))) then AMOADD - else if (((l__9 = (( 2 :: int)::ii)))) then AMOXOR - else if (((l__9 = (( 3 :: int)::ii)))) then AMOAND - else if (((l__9 = (( 4 :: int)::ii)))) then AMOOR - else if (((l__9 = (( 5 :: int)::ii)))) then AMOMIN - else if (((l__9 = (( 6 :: int)::ii)))) then AMOMAX - else if (((l__9 = (( 7 :: int)::ii)))) then AMOMINU + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then AMOSWAP + else if (((p00 = (( 1 :: int)::ii)))) then AMOADD + else if (((p00 = (( 2 :: int)::ii)))) then AMOXOR + else if (((p00 = (( 3 :: int)::ii)))) then AMOAND + else if (((p00 = (( 4 :: int)::ii)))) then AMOOR + else if (((p00 = (( 5 :: int)::ii)))) then AMOMIN + else if (((p00 = (( 6 :: int)::ii)))) then AMOMAX + else if (((p00 = (( 7 :: int)::ii)))) then AMOMINU else AMOMAXU))" @@ -857,9 +1022,9 @@ fun num_of_amoop :: " amoop \<Rightarrow> int " where definition csrop_of_num :: " int \<Rightarrow> csrop " where " csrop_of_num arg0 = ( - (let l__7 = arg0 in - if (((l__7 = (( 0 :: int)::ii)))) then CSRRW - else if (((l__7 = (( 1 :: int)::ii)))) then CSRRS + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then CSRRW + else if (((p00 = (( 1 :: int)::ii)))) then CSRRS else CSRRC))" @@ -875,10 +1040,10 @@ fun num_of_csrop :: " csrop \<Rightarrow> int " where definition word_width_of_num :: " int \<Rightarrow> word_width " where " word_width_of_num arg0 = ( - (let l__4 = arg0 in - if (((l__4 = (( 0 :: int)::ii)))) then BYTE - else if (((l__4 = (( 1 :: int)::ii)))) then HALF - else if (((l__4 = (( 2 :: int)::ii)))) then WORD + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then BYTE + else if (((p00 = (( 1 :: int)::ii)))) then HALF + else if (((p00 = (( 2 :: int)::ii)))) then WORD else DOUBLE))" @@ -891,282 +1056,1141 @@ fun num_of_word_width :: " word_width \<Rightarrow> int " where |" num_of_word_width DOUBLE = ( (( 3 :: int)::ii))" -(*val is_aligned_addr : mword ty64 -> integer -> bool*) +(*val reg_name_forwards : mword ty5 -> string*) -definition is_aligned_addr :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where - " is_aligned_addr (addr :: xlenbits) (width :: int) = ( - (((ex_int ((hardware_mod ((Word.uint addr)) width)))) = (( 0 :: int)::ii)))" - - -(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) +definition reg_name_forwards :: "(5)Word.word \<Rightarrow> string " where + " reg_name_forwards arg0 = ( + (let p00 = arg0 in + if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) + then + (''zero'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) then + (''ra'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) then + (''sp'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) then + (''gp'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then + (''tp'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))))) then + (''t0'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))))) then + (''t1'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))))) then + (''t2'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then + (''fp'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))))) then + (''s1'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))))) then + (''a0'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))))) then + (''a1'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then + (''a2'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))))) then + (''a3'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))))) then + (''a4'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))))) then + (''a5'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then + (''a6'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))))) then + (''a7'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)))))) then + (''s2'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)))))) then + (''s3'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then + (''s4'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)))))) then + (''s5'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word)))))) then + (''s6'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word)))))) then + (''s7'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then + (''s8'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word)))))) then + (''s9'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)))))) then + (''s10'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word)))))) then + (''s11'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then + (''t3'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))))) then + (''t4'') + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))))) then + (''t5'') + else (''t6'')))" -definition checked_mem_read :: " ReadType \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where - " checked_mem_read (t :: ReadType) (addr :: xlenbits) (width :: int) = ( - (RISCV_read addr width :: ( (( 'int8_times_n::len)Word.word)option) M) \<bind> (\<lambda> (w__0 :: - (( 'int8_times_n::len)Word.word)option) . - return ((case (t, w__0) of - (Instruction, None) => MemException E_Fetch_Access_Fault - | (Data, None) => MemException E_Load_Access_Fault - | (_, Some (v)) => MemValue v - ))))" +(*val reg_name_backwards : string -> mword ty5*) + +definition reg_name_backwards :: " string \<Rightarrow>(5)Word.word " where + " reg_name_backwards arg0 = ( + if(arg0 = (''zero'')) then ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)) + else + ( + if(arg0 = (''ra'')) then ((vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)) + else + ( + if(arg0 = (''sp'')) then + ((vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)) else + ( + if(arg0 = (''gp'')) then + ((vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)) else + ( + if(arg0 = (''tp'')) then + ((vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)) else + ( + if(arg0 = (''t0'')) then + ((vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)) else + ( + if(arg0 = (''t1'')) then + ((vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)) else + ( + if(arg0 = (''t2'')) then + ((vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)) else + ( + if(arg0 = (''fp'')) then + ((vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)) else + ( + if(arg0 = (''s1'')) then + ((vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)) else + ( + if(arg0 = (''a0'')) then + ((vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)) else + ( + if(arg0 = (''a1'')) then + ((vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)) + else + ( + if(arg0 = (''a2'')) then + ((vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)) + else + ( + if(arg0 = (''a3'')) then + ((vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)) + else + ( + if(arg0 = (''a4'')) then + ((vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)) + else + ( + if(arg0 = (''a5'')) then + ((vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)) + else + ( + if(arg0 = (''a6'')) then + ((vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)) + else + ( + if(arg0 = (''a7'')) then + ((vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)) + else + ( + if(arg0 = (''s2'')) then + ((vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)) + else + ( + if(arg0 = (''s3'')) then + ((vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)) + else + ( + if(arg0 = (''s4'')) then + ((vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)) + else + ( + if(arg0 = (''s5'')) then + ((vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)) + else + ( + if(arg0 = (''s6'')) then + ((vec_of_bits + [B1,B0,B1,B1,B0] :: 5 Word.word)) + else + ( + if(arg0 = (''s7'')) then + ((vec_of_bits + [B1,B0,B1,B1,B1] :: 5 Word.word)) + else + ( + if(arg0 = (''s8'')) then + ((vec_of_bits + [B1,B1,B0,B0,B0] :: 5 Word.word)) + else + ( + if(arg0 = (''s9'')) then + ((vec_of_bits + [B1,B1,B0,B0,B1] :: 5 Word.word)) + else + ( + if(arg0 = (''s10'')) then + ((vec_of_bits + [B1,B1,B0,B1,B0] :: 5 Word.word)) + else + ( + if(arg0 = (''s11'')) then + ((vec_of_bits + [B1,B1,B0,B1,B1] :: 5 Word.word)) + else + ( + if(arg0 = (''t3'')) then + ((vec_of_bits + [B1,B1,B1,B0,B0] :: 5 Word.word)) + else + ( + if(arg0 = + (''t4'')) then + ((vec_of_bits + [B1,B1,B1,B0,B1] :: 5 Word.word)) + else + ( + if(arg0 = + (''t5'')) then + ((vec_of_bits + [B1,B1,B1,B1,B0] :: 5 Word.word)) + else + ( + if(arg0 = + (''t6'')) then + ((vec_of_bits + [B1,B1,B1,B1,B1] :: 5 Word.word)) + else + undefined))))))))))))))))))))))))))))))) )" + + +(*val reg_name_forwards_matches : mword ty5 -> bool*) + +definition reg_name_forwards_matches :: "(5)Word.word \<Rightarrow> bool " where + " reg_name_forwards_matches arg0 = ( + (let p00 = arg0 in + if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) + then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word)))))) then + True + else False))" -(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) -(*val MEMr_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) +(*val reg_name_backwards_matches : string -> bool*) + +definition reg_name_backwards_matches :: " string \<Rightarrow> bool " where + " reg_name_backwards_matches arg0 = ( + if(arg0 = (''zero'')) then True else + ( + if(arg0 = (''ra'')) then True else + ( + if(arg0 = (''sp'')) then True else + ( + if(arg0 = (''gp'')) then True else + ( + if(arg0 = (''tp'')) then True else + ( + if(arg0 = (''t0'')) then True else + ( + if(arg0 = (''t1'')) then True else + ( + if(arg0 = (''t2'')) then True else + ( + if(arg0 = (''fp'')) then True else + ( + if(arg0 = (''s1'')) then True else + ( + if(arg0 = (''a0'')) then True else + ( + if(arg0 = (''a1'')) then True else + ( + if(arg0 = (''a2'')) then True else + ( + if(arg0 = (''a3'')) then True else + ( + if(arg0 = (''a4'')) then True else + ( + if(arg0 = (''a5'')) then True else + ( + if(arg0 = (''a6'')) then True else + ( + if(arg0 = (''a7'')) then True else + ( + if(arg0 = (''s2'')) then True else + ( + if(arg0 = (''s3'')) then True else + ( + if(arg0 = (''s4'')) then True else + ( + if(arg0 = (''s5'')) then + True else + ( + if(arg0 = (''s6'')) then + True else + ( + if(arg0 = (''s7'')) then + True else + ( + if(arg0 = (''s8'')) then + True else + ( + if(arg0 = (''s9'')) then + True else + ( + if(arg0 = (''s10'')) then + True else + ( + if(arg0 = (''s11'')) then + True else + ( + if(arg0 = (''t3'')) then + True else + ( + if(arg0 = + (''t4'')) then + True else + ( + if(arg0 = + (''t5'')) then + True else + ( + if(arg0 = + (''t6'')) then + True else + False))))))))))))))))))))))))))))))) )" + + +(*val reg_name_matches_prefix : string -> maybe ((mword ty5 * ii))*) + +definition reg_name_matches_prefix :: " string \<Rightarrow>((5)Word.word*int)option " where + " reg_name_matches_prefix arg0 = ( + (let stringappend_18140 = arg0 in + if (((((string_startswith stringappend_18140 (''zero''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''zero''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''zero''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''ra''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''ra''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''ra''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''sp''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''sp''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''sp''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''gp''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''gp''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''gp''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''tp''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''tp''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''tp''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''t0''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''t0''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''t0''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''t1''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''t1''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''t1''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''t2''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''t2''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''t2''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''fp''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''fp''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''fp''))))) of + s0 => + Some ((vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''s1''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''s1''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''s1''))))) of + s0 => + Some ((vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''a0''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''a0''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''a0''))))) of + s0 => + Some ((vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''a1''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''a1''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''a1''))))) of + s0 => + Some ((vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''a2''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''a2''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''a2''))))) of + s0 => + Some ((vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''a3''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''a3''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''a3''))))) of + s0 => + Some ((vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''a4''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''a4''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''a4''))))) of + s0 => + Some ((vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''a5''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''a5''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''a5''))))) of + s0 => + Some ((vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''a6''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''a6''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''a6''))))) of + s0 => + Some ((vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''a7''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''a7''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''a7''))))) of + s0 => + Some ((vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''s2''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''s2''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''s2''))))) of + s0 => + Some ((vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''s3''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''s3''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''s3''))))) of + s0 => + Some ((vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''s4''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''s4''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''s4''))))) of + s0 => + Some ((vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''s5''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''s5''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''s5''))))) of + s0 => + Some ((vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''s6''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''s6''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''s6''))))) of + s0 => + Some ((vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''s7''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''s7''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''s7''))))) of + s0 => + Some ((vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''s8''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''s8''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''s8''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''s9''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''s9''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''s9''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''s10''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''s10''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''s10''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''s11''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''s11''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''s11''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''t3''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''t3''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''t3''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''t4''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''t4''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''t4''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''t5''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''t5''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''t5''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_18140 (''t6''))) \<and> ( + (case ((string_drop stringappend_18140 ((string_length (''t6''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_18140 ((string_length (''t6''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else None))" -(*val MEMr_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) -(*val MEMr_reserved : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) +(*val sep_forwards : unit -> string*) + +definition sep_forwards :: " unit \<Rightarrow> string " where + " sep_forwards _ = ( + string_append ((opt_spc_forwards () )) + ((string_append ('','') ((string_append ((def_spc_forwards () )) (''''))))))" + + +(*val sep_backwards : string -> unit*) + +definition sep_backwards :: " string \<Rightarrow> unit " where + " sep_backwards arg0 = ( + (let stringappend_18070 = arg0 in + (case + (case ((opt_spc_matches_prefix stringappend_18070)) of + Some (stringappend_18080,stringappend_18090) => (stringappend_18080, stringappend_18090) + ) of + (_, stringappend_18090) => + (let stringappend_18100 = (string_drop stringappend_18070 + stringappend_18090) in + (let stringappend_18110 = (string_drop stringappend_18100 + ((string_length ('','')))) in + (case + (case ((opt_spc_matches_prefix stringappend_18110)) of + Some (stringappend_18120,stringappend_18130) => (stringappend_18120, stringappend_18130) + ) of + (_, stringappend_18130) => + if(((string_drop stringappend_18110 stringappend_18130)) = ('''')) then + () else undefined + ))) + )))" + + +(*val sep_forwards_matches : unit -> bool*) + +definition sep_forwards_matches :: " unit \<Rightarrow> bool " where + " sep_forwards_matches _ = ( True )" + + +(*val sep_backwards_matches : string -> bool*) + +definition sep_backwards_matches :: " string \<Rightarrow> bool " where + " sep_backwards_matches arg0 = ( + (let stringappend_18000 = arg0 in + if ((case ((opt_spc_matches_prefix stringappend_18000)) of + Some (stringappend_18010,stringappend_18020) => + (let stringappend_18030 = (string_drop stringappend_18000 stringappend_18020) in + if (((((string_startswith stringappend_18030 ('',''))) \<and> ((let stringappend_18040 = (string_drop stringappend_18030 ((string_length ('','')))) in + if ((case ((opt_spc_matches_prefix stringappend_18040)) of + Some (stringappend_18050,stringappend_18060) => + if(((string_drop stringappend_18040 stringappend_18060)) = ('''')) then + True else False + | None => False + )) then + True + else False))))) then + True + else False) + | None => False + )) then (case + (case ((opt_spc_matches_prefix stringappend_18000)) of + Some (stringappend_18010,stringappend_18020) => + (stringappend_18010, stringappend_18020) + ) of + (_, stringappend_18020) => + (let stringappend_18030 = (string_drop stringappend_18000 stringappend_18020) in + (let stringappend_18040 = (string_drop stringappend_18030 + ((string_length ('','')))) in + (case + (case ((opt_spc_matches_prefix stringappend_18040)) of + Some (stringappend_18050,stringappend_18060) => + (stringappend_18050, stringappend_18060) + ) of + (_, stringappend_18060) => + if(((string_drop stringappend_18040 stringappend_18060)) = ('''')) then + True else undefined + ))) + ) + else False))" -(*val MEMr_reserved_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) -(*val MEMr_reserved_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) +(*val sep_matches_prefix : string -> maybe ((unit * ii))*) + +definition sep_matches_prefix :: " string \<Rightarrow>(unit*int)option " where + " sep_matches_prefix arg0 = ( + (let stringappend_17930 = arg0 in + if ((case ((opt_spc_matches_prefix stringappend_17930)) of + Some (stringappend_17940,stringappend_17950) => + (let stringappend_17960 = (string_drop stringappend_17930 stringappend_17950) in + if (((((string_startswith stringappend_17960 ('',''))) \<and> ((let stringappend_17970 = (string_drop stringappend_17960 ((string_length ('','')))) in + if ((case ((opt_spc_matches_prefix stringappend_17970)) of + Some (stringappend_17980,stringappend_17990) => + (case ((string_drop stringappend_17970 stringappend_17990)) of + s0 => True + ) + | None => False + )) then + True + else False))))) then + True + else False) + | None => False + )) then (case + (case ((opt_spc_matches_prefix stringappend_17930)) of + Some (stringappend_17940,stringappend_17950) => + (stringappend_17940, stringappend_17950) + ) of + (_, stringappend_17950) => + (let stringappend_17960 = (string_drop stringappend_17930 stringappend_17950) in + (let stringappend_17970 = (string_drop stringappend_17960 + ((string_length ('','')))) in + (case + (case ((opt_spc_matches_prefix stringappend_17970)) of + Some (stringappend_17980,stringappend_17990) => + (stringappend_17980, stringappend_17990) + ) of + (_, stringappend_17990) => + (case ((string_drop stringappend_17970 stringappend_17990)) of + s0 => Some (() , ((string_length arg0)) - ((string_length s0))) + ) + ))) + ) + else None))" -definition MEMr :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where - " MEMr addr width = ( (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" +(*val bool_bits_forwards : bool -> mword ty1*) -definition MEMr_acquire :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where - " MEMr_acquire addr width = ( - (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" +fun bool_bits_forwards :: " bool \<Rightarrow>(1)Word.word " where + " bool_bits_forwards True = ( (vec_of_bits [B1] :: 1 Word.word))" +|" bool_bits_forwards False = ( (vec_of_bits [B0] :: 1 Word.word))" -definition MEMr_strong_acquire :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where - " MEMr_strong_acquire addr width = ( - (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" +(*val bool_bits_backwards : mword ty1 -> bool*) +definition bool_bits_backwards :: "(1)Word.word \<Rightarrow> bool " where + " bool_bits_backwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B1] :: 1 Word.word)))) then True + else False))" -definition MEMr_reserved :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where - " MEMr_reserved addr width = ( - (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" +(*val bool_bits_forwards_matches : bool -> bool*) -definition MEMr_reserved_acquire :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where - " MEMr_reserved_acquire addr width = ( - (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" +fun bool_bits_forwards_matches :: " bool \<Rightarrow> bool " where + " bool_bits_forwards_matches True = ( True )" +|" bool_bits_forwards_matches False = ( True )" -definition MEMr_reserved_strong_acquire :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where - " MEMr_reserved_strong_acquire addr width = ( - (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" +(*val bool_bits_backwards_matches : mword ty1 -> bool*) +definition bool_bits_backwards_matches :: "(1)Word.word \<Rightarrow> bool " where + " bool_bits_backwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B1] :: 1 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0] :: 1 Word.word)))) then True + else False))" -(*val mem_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*) -definition mem_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where - " mem_read addr width aq rl res = ( - if ((((((aq \<or> res))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then - return (MemException E_Load_Addr_Align) - else - (case (aq, rl, res) of - (False, False, False) => (MEMr addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) - | (True, False, False) => (MEMr_acquire addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) - | (False, False, True) => - (MEMr_reserved addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) - | (True, False, True) => - (MEMr_reserved_acquire addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) - | (False, True, False) => throw (Error_not_implemented (''load.rl'')) - | (True, True, False) => - (MEMr_strong_acquire addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) - | (False, True, True) => throw (Error_not_implemented (''lr.rl'')) - | (True, True, True) => - (MEMr_reserved_strong_acquire addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) - ))" +(*val bool_not_bits_forwards : bool -> mword ty1*) +fun bool_not_bits_forwards :: " bool \<Rightarrow>(1)Word.word " where + " bool_not_bits_forwards True = ( (vec_of_bits [B0] :: 1 Word.word))" +|" bool_not_bits_forwards False = ( (vec_of_bits [B1] :: 1 Word.word))" -(*val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*) -definition mem_write_ea :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where - " mem_write_ea addr width aq rl con = ( - if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then - return (MemException E_SAMO_Addr_Align) - else - (case (aq, rl, con) of - (False, False, False) => MEMea addr width \<then> return (MemValue () ) - | (False, True, False) => MEMea_release addr width \<then> return (MemValue () ) - | (False, False, True) => MEMea_conditional addr width \<then> return (MemValue () ) - | (False, True, True) => MEMea_conditional_release addr width \<then> return (MemValue () ) - | (True, False, False) => throw (Error_not_implemented (''store.aq'')) - | (True, True, False) => MEMea_strong_release addr width \<then> return (MemValue () ) - | (True, False, True) => throw (Error_not_implemented (''sc.aq'')) - | (True, True, True) => MEMea_conditional_strong_release addr width \<then> return (MemValue () ) - ))" +(*val bool_not_bits_backwards : mword ty1 -> bool*) +definition bool_not_bits_backwards :: "(1)Word.word \<Rightarrow> bool " where + " bool_not_bits_backwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0] :: 1 Word.word)))) then True + else False))" -(*val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) -definition checked_mem_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where - " checked_mem_write (addr :: xlenbits) (width :: int) (data :: 'int8_times_n bits) = ( - RISCV_write addr width data \<bind> (\<lambda> (w__0 :: bool) . - return (if w__0 then MemValue () - else MemException E_SAMO_Access_Fault)))" +(*val bool_not_bits_forwards_matches : bool -> bool*) +fun bool_not_bits_forwards_matches :: " bool \<Rightarrow> bool " where + " bool_not_bits_forwards_matches True = ( True )" +|" bool_not_bits_forwards_matches False = ( True )" -(*val MEMval : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) -(*val MEMval_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) +(*val bool_not_bits_backwards_matches : mword ty1 -> bool*) -(*val MEMval_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) +definition bool_not_bits_backwards_matches :: "(1)Word.word \<Rightarrow> bool " where + " bool_not_bits_backwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0] :: 1 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1] :: 1 Word.word)))) then True + else False))" -(*val MEMval_conditional : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) -(*val MEMval_conditional_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) +(*val size_bits_forwards : word_width -> mword ty2*) -(*val MEMval_conditional_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) +fun size_bits_forwards :: " word_width \<Rightarrow>(2)Word.word " where + " size_bits_forwards BYTE = ( (vec_of_bits [B0,B0] :: 2 Word.word))" +|" size_bits_forwards HALF = ( (vec_of_bits [B0,B1] :: 2 Word.word))" +|" size_bits_forwards WORD = ( (vec_of_bits [B1,B0] :: 2 Word.word))" +|" size_bits_forwards DOUBLE = ( (vec_of_bits [B1,B1] :: 2 Word.word))" -definition MEMval :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where - " MEMval addr width data = ( checked_mem_write addr width data )" +(*val size_bits_backwards : mword ty2 -> word_width*) -definition MEMval_release :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where - " MEMval_release addr width data = ( checked_mem_write addr width data )" +definition size_bits_backwards :: "(2)Word.word \<Rightarrow> word_width " where + " size_bits_backwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then BYTE + else if (((p00 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then HALF + else if (((p00 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then WORD + else DOUBLE))" -definition MEMval_strong_release :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where - " MEMval_strong_release addr width data = ( checked_mem_write addr width data )" +(*val size_bits_forwards_matches : word_width -> bool*) +fun size_bits_forwards_matches :: " word_width \<Rightarrow> bool " where + " size_bits_forwards_matches BYTE = ( True )" +|" size_bits_forwards_matches HALF = ( True )" +|" size_bits_forwards_matches WORD = ( True )" +|" size_bits_forwards_matches DOUBLE = ( True )" -definition MEMval_conditional :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where - " MEMval_conditional addr width data = ( checked_mem_write addr width data )" +(*val size_bits_backwards_matches : mword ty2 -> bool*) -definition MEMval_conditional_release :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where - " MEMval_conditional_release addr width data = ( checked_mem_write addr width data )" +definition size_bits_backwards_matches :: "(2)Word.word \<Rightarrow> bool " where + " size_bits_backwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then True + else False))" -definition MEMval_conditional_strong_release :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where - " MEMval_conditional_strong_release addr width data = ( checked_mem_write addr width data )" +(*val size_mnemonic_forwards : word_width -> string*) + +fun size_mnemonic_forwards :: " word_width \<Rightarrow> string " where + " size_mnemonic_forwards BYTE = ( (''b''))" +|" size_mnemonic_forwards HALF = ( (''h''))" +|" size_mnemonic_forwards WORD = ( (''w''))" +|" size_mnemonic_forwards DOUBLE = ( (''d''))" + + +(*val size_mnemonic_backwards : string -> word_width*) + +definition size_mnemonic_backwards :: " string \<Rightarrow> word_width " where + " size_mnemonic_backwards arg0 = ( + if(arg0 = (''b'')) then BYTE else + ( + if(arg0 = (''h'')) then HALF else + ( + if(arg0 = (''w'')) then WORD else + (if(arg0 = (''d'')) then DOUBLE else undefined))) )" + + +(*val size_mnemonic_forwards_matches : word_width -> bool*) + +fun size_mnemonic_forwards_matches :: " word_width \<Rightarrow> bool " where + " size_mnemonic_forwards_matches BYTE = ( True )" +|" size_mnemonic_forwards_matches HALF = ( True )" +|" size_mnemonic_forwards_matches WORD = ( True )" +|" size_mnemonic_forwards_matches DOUBLE = ( True )" + + +(*val size_mnemonic_backwards_matches : string -> bool*) + +definition size_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where + " size_mnemonic_backwards_matches arg0 = ( + if(arg0 = (''b'')) then True else + ( + if(arg0 = (''h'')) then True else + ( + if(arg0 = (''w'')) then True else + (if(arg0 = (''d'')) then True else False))) )" + + +(*val size_mnemonic_matches_prefix : string -> maybe ((word_width * ii))*) + +definition size_mnemonic_matches_prefix :: " string \<Rightarrow>(word_width*int)option " where + " size_mnemonic_matches_prefix arg0 = ( + (let stringappend_17890 = arg0 in + if (((((string_startswith stringappend_17890 (''b''))) \<and> ( + (case ((string_drop stringappend_17890 ((string_length (''b''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17890 ((string_length (''b''))))) of + s0 => Some (BYTE, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17890 (''h''))) \<and> ( + (case ((string_drop stringappend_17890 ((string_length (''h''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17890 ((string_length (''h''))))) of + s0 => Some (HALF, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17890 (''w''))) \<and> ( + (case ((string_drop stringappend_17890 ((string_length (''w''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17890 ((string_length (''w''))))) of + s0 => Some (WORD, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17890 (''d''))) \<and> ( + (case ((string_drop stringappend_17890 ((string_length (''d''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17890 ((string_length (''d''))))) of + s0 => Some (DOUBLE, ((string_length arg0)) - ((string_length s0))) + ) + else None))" -(*val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult unit)*) +(*val Mk_Misa : mword ty64 -> Misa*) -definition mem_write_value :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where - " mem_write_value addr width value1 aq rl con = ( - if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then - return (MemException E_SAMO_Addr_Align) - else - (case (aq, rl, con) of - (False, False, False) => MEMval addr width value1 - | (False, True, False) => MEMval_release addr width value1 - | (False, False, True) => MEMval_conditional addr width value1 - | (False, True, True) => MEMval_conditional_release addr width value1 - | (True, False, False) => throw (Error_not_implemented (''store.aq'')) - | (True, True, False) => MEMval_strong_release addr width value1 - | (True, False, True) => throw (Error_not_implemented (''sc.aq'')) - | (True, True, True) => MEMval_conditional_strong_release addr width value1 - ))" +definition Mk_Misa :: "(64)Word.word \<Rightarrow> Misa " where + " Mk_Misa v = ( (| Misa_Misa_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -(*val _get_Misa : Misa -> mword ty64*) +(*val _get_Misa_bits : Misa -> mword ty64*) -fun get_Misa :: " Misa \<Rightarrow>(64)Word.word " where - " get_Misa (Mk_Misa (v)) = ( v )" +definition get_Misa_bits :: " Misa \<Rightarrow>(64)Word.word " where + " get_Misa_bits v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_Misa : register_ref regstate register_value Misa -> mword ty64 -> M unit*) +(*val _set_Misa_bits : register_ref regstate register_value Misa -> mword ty64 -> M unit*) -definition set_Misa :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_Misa r_ref v = ( +definition set_Misa_bits :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_Misa v) in + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" -(*val _get_SV39_PTE : SV39_PTE -> mword ty64*) +(*val _update_Misa_bits : Misa -> mword ty64 -> Misa*) + +definition update_Misa_bits :: " Misa \<Rightarrow>(64)Word.word \<Rightarrow> Misa " where + " update_Misa_bits v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + -(*val _set_SV39_PTE : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*) +(*val _update_SV39_PTE_bits : SV39_PTE -> mword ty64 -> SV39_PTE*) + +(*val _get_SV39_PTE_bits : SV39_PTE -> mword ty64*) + +(*val _set_SV39_PTE_bits : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*) (*val _get_Misa_MXL : Misa -> mword ty2*) -fun get_Misa_MXL :: " Misa \<Rightarrow>(2)Word.word " where - " get_Misa_MXL (Mk_Misa (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))" +definition get_Misa_MXL :: " Misa \<Rightarrow>(2)Word.word " where + " get_Misa_MXL v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))" (*val _set_Misa_MXL : register_ref regstate register_value Misa -> mword ty2 -> M unit*) definition set_Misa_MXL :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_MXL r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 63 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_MXL : Misa -> mword ty2 -> Misa*) -fun update_Misa_MXL :: " Misa \<Rightarrow>(2)Word.word \<Rightarrow> Misa " where - " update_Misa_MXL (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_MXL :: " Misa \<Rightarrow>(2)Word.word \<Rightarrow> Misa " where + " update_Misa_MXL v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 63 :: int)::ii) (( 62 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_Z : Misa -> mword ty1*) -fun get_Misa_Z :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_Z (Mk_Misa (v)) = ( (subrange_vec_dec v (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word))" +definition get_Misa_Z :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_Z v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_Z : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_Z :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_Z r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 25 :: int)::ii) (( 25 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 25 :: int)::ii) (( 25 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_Z : Misa -> mword ty1 -> Misa*) -fun update_Misa_Z :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_Z (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 25 :: int)::ii) (( 25 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_Z :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_Z v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 25 :: int)::ii) (( 25 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_Y : Misa -> mword ty1*) -fun get_Misa_Y :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_Y (Mk_Misa (v)) = ( (subrange_vec_dec v (( 24 :: int)::ii) (( 24 :: int)::ii) :: 1 Word.word))" +definition get_Misa_Y :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_Y v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 24 :: int)::ii) (( 24 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_Y : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_Y :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_Y r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 24 :: int)::ii) (( 24 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 24 :: int)::ii) (( 24 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_Y : Misa -> mword ty1 -> Misa*) -fun update_Misa_Y :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_Y (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 24 :: int)::ii) (( 24 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_Y :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_Y v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 24 :: int)::ii) (( 24 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_X : Misa -> mword ty1*) -fun get_Misa_X :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_X (Mk_Misa (v)) = ( (subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))" +definition get_Misa_X :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_X v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_X : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_X :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_X r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 23 :: int)::ii) (( 23 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 23 :: int)::ii) (( 23 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_X : Misa -> mword ty1 -> Misa*) -fun update_Misa_X :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_X (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_X :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_X v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 23 :: int)::ii) (( 23 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_PTE_Bits_X : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1177,25 +2201,33 @@ fun update_Misa_X :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " whe (*val _get_Misa_W : Misa -> mword ty1*) -fun get_Misa_W :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_W (Mk_Misa (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" +definition get_Misa_W :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_W v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_W : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_W :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_W r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 22 :: int)::ii) (( 22 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_W : Misa -> mword ty1 -> Misa*) -fun update_Misa_W :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_W (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_W :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_W v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_PTE_Bits_W : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1206,25 +2238,33 @@ fun update_Misa_W :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " whe (*val _get_Misa_V : Misa -> mword ty1*) -fun get_Misa_V :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_V (Mk_Misa (v)) = ( (subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word))" +definition get_Misa_V :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_V v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_V : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_V :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_V r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 21 :: int)::ii) (( 21 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 21 :: int)::ii) (( 21 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_V : Misa -> mword ty1 -> Misa*) -fun update_Misa_V :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_V (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_V :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_V v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 21 :: int)::ii) (( 21 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_PTE_Bits_V : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1235,25 +2275,33 @@ fun update_Misa_V :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " whe (*val _get_Misa_U : Misa -> mword ty1*) -fun get_Misa_U :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_U (Mk_Misa (v)) = ( (subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word))" +definition get_Misa_U :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_U v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_U : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_U :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_U r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 20 :: int)::ii) (( 20 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 20 :: int)::ii) (( 20 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_U : Misa -> mword ty1 -> Misa*) -fun update_Misa_U :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_U (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_U :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_U v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 20 :: int)::ii) (( 20 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_PTE_Bits_U : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1264,71 +2312,95 @@ fun update_Misa_U :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " whe (*val _get_Misa_T : Misa -> mword ty1*) -fun get_Misa_T :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_T (Mk_Misa (v)) = ( (subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))" +definition get_Misa_T :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_T v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_T : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_T :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_T r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 19 :: int)::ii) (( 19 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 19 :: int)::ii) (( 19 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_T : Misa -> mword ty1 -> Misa*) -fun update_Misa_T :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_T (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_T :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_T v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_S : Misa -> mword ty1*) -fun get_Misa_S :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_S (Mk_Misa (v)) = ( (subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))" +definition get_Misa_S :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_S v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_S : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_S :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_S r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 18 :: int)::ii) (( 18 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 18 :: int)::ii) (( 18 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_S : Misa -> mword ty1 -> Misa*) -fun update_Misa_S :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_S (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_S :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_S v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_R : Misa -> mword ty1*) -fun get_Misa_R :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_R (Mk_Misa (v)) = ( (subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) :: 1 Word.word))" +definition get_Misa_R :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_R v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 17 :: int)::ii) (( 17 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_R : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_R :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_R r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 17 :: int)::ii) (( 17 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 17 :: int)::ii) (( 17 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_R : Misa -> mword ty1 -> Misa*) -fun update_Misa_R :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_R (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_R :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_R v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 17 :: int)::ii) (( 17 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_PTE_Bits_R : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1339,255 +2411,343 @@ fun update_Misa_R :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " whe (*val _get_Misa_Q : Misa -> mword ty1*) -fun get_Misa_Q :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_Q (Mk_Misa (v)) = ( (subrange_vec_dec v (( 16 :: int)::ii) (( 16 :: int)::ii) :: 1 Word.word))" +definition get_Misa_Q :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_Q v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 16 :: int)::ii) (( 16 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_Q : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_Q :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_Q r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 16 :: int)::ii) (( 16 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 16 :: int)::ii) (( 16 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_Q : Misa -> mword ty1 -> Misa*) -fun update_Misa_Q :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_Q (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 16 :: int)::ii) (( 16 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_Q :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_Q v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 16 :: int)::ii) (( 16 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_P : Misa -> mword ty1*) -fun get_Misa_P :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_P (Mk_Misa (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word))" +definition get_Misa_P :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_P v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_P : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_P :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_P r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 15 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 15 :: int)::ii) (( 15 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_P : Misa -> mword ty1 -> Misa*) -fun update_Misa_P :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_P (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_P :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_P v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 15 :: int)::ii) (( 15 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_O : Misa -> mword ty1*) -fun get_Misa_O :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_O (Mk_Misa (v)) = ( (subrange_vec_dec v (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word))" +definition get_Misa_O :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_O v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_O : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_O :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_O r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 14 :: int)::ii) (( 14 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 14 :: int)::ii) (( 14 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_O : Misa -> mword ty1 -> Misa*) -fun update_Misa_O :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_O (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 14 :: int)::ii) (( 14 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_O :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_O v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 14 :: int)::ii) (( 14 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_N : Misa -> mword ty1*) -fun get_Misa_N :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_N (Mk_Misa (v)) = ( (subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) :: 1 Word.word))" +definition get_Misa_N :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_N v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 13 :: int)::ii) (( 13 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_N : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_N :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_N r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 13 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 13 :: int)::ii) (( 13 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_N : Misa -> mword ty1 -> Misa*) -fun update_Misa_N :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_N (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_N :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_N v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 13 :: int)::ii) (( 13 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_M : Misa -> mword ty1*) -fun get_Misa_M :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_M (Mk_Misa (v)) = ( (subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word))" +definition get_Misa_M :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_M v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_M : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_M :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_M r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 12 :: int)::ii) (( 12 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 12 :: int)::ii) (( 12 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_M : Misa -> mword ty1 -> Misa*) -fun update_Misa_M :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_M (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_M :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_M v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 12 :: int)::ii) (( 12 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_L : Misa -> mword ty1*) -fun get_Misa_L :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_L (Mk_Misa (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word))" +definition get_Misa_L :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_L v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_L : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_L :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_L r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 11 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 11 :: int)::ii) (( 11 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_L : Misa -> mword ty1 -> Misa*) -fun update_Misa_L :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_L (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_L :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_L v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 11 :: int)::ii) (( 11 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_K : Misa -> mword ty1*) -fun get_Misa_K :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_K (Mk_Misa (v)) = ( (subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word))" +definition get_Misa_K :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_K v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_K : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_K :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_K r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 10 :: int)::ii) (( 10 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 10 :: int)::ii) (( 10 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_K : Misa -> mword ty1 -> Misa*) -fun update_Misa_K :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_K (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_K :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_K v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 10 :: int)::ii) (( 10 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_J : Misa -> mword ty1*) -fun get_Misa_J :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_J (Mk_Misa (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" +definition get_Misa_J :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_J v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_J : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_J :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_J r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 9 :: int)::ii) (( 9 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_J : Misa -> mword ty1 -> Misa*) -fun update_Misa_J :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_J (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_J :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_J v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_I : Misa -> mword ty1*) -fun get_Misa_I :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_I (Mk_Misa (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" +definition get_Misa_I :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_I v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_I : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_I :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_I r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_I : Misa -> mword ty1 -> Misa*) -fun update_Misa_I :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_I (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_I :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_I v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_H : Misa -> mword ty1*) -fun get_Misa_H :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_H (Mk_Misa (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" +definition get_Misa_H :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_H v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_H : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_H :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_H r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_H : Misa -> mword ty1 -> Misa*) -fun update_Misa_H :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_H (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_H :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_H v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_G : Misa -> mword ty1*) -fun get_Misa_G :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_G (Mk_Misa (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" +definition get_Misa_G :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_G v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_G : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_G :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_G r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_G : Misa -> mword ty1 -> Misa*) -fun update_Misa_G :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_G (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_G :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_G v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_PTE_Bits_G : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1598,71 +2758,95 @@ fun update_Misa_G :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " whe (*val _get_Misa_F : Misa -> mword ty1*) -fun get_Misa_F :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_F (Mk_Misa (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" +definition get_Misa_F :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_F v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_F : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_F :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_F r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_F : Misa -> mword ty1 -> Misa*) -fun update_Misa_F :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_F (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_F :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_F v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_E : Misa -> mword ty1*) -fun get_Misa_E :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_E (Mk_Misa (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" +definition get_Misa_E :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_E v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_E : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_E :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_E r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_E : Misa -> mword ty1 -> Misa*) -fun update_Misa_E :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_E (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_E :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_E v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_D : Misa -> mword ty1*) -fun get_Misa_D :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_D (Mk_Misa (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" +definition get_Misa_D :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_D v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_D : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_D :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_D r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_D : Misa -> mword ty1 -> Misa*) -fun update_Misa_D :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_D (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_D :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_D v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_PTE_Bits_D : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1673,71 +2857,95 @@ fun update_Misa_D :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " whe (*val _get_Misa_C : Misa -> mword ty1*) -fun get_Misa_C :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_C (Mk_Misa (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" +definition get_Misa_C :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_C v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_C : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_C :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_C r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_C : Misa -> mword ty1 -> Misa*) -fun update_Misa_C :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_C (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_C :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_C v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_B : Misa -> mword ty1*) -fun get_Misa_B :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_B (Mk_Misa (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_Misa_B :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_B v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_B : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_B :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_B r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_B : Misa -> mword ty1 -> Misa*) -fun update_Misa_B :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_B (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_B :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_B v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Misa_A : Misa -> mword ty1*) -fun get_Misa_A :: " Misa \<Rightarrow>(1)Word.word " where - " get_Misa_A (Mk_Misa (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_Misa_A :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_A v = ( (subrange_vec_dec(Misa_Misa_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" (*val _set_Misa_A : register_ref regstate register_value Misa -> mword ty1 -> M unit*) definition set_Misa_A :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Misa_A r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . - (let r = ((get_Misa w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Misa r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Misa_A : Misa -> mword ty1 -> Misa*) -fun update_Misa_A :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where - " update_Misa_A (Mk_Misa (v)) x = ( - Mk_Misa ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_Misa_A :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_A v x = ( + (v (| + Misa_Misa_chunk_0 := + ((update_subrange_vec_dec(Misa_Misa_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_PTE_Bits_A : PTE_Bits -> mword ty1 -> PTE_Bits*) @@ -1746,48 +2954,85 @@ fun update_Misa_A :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " whe (*val _set_PTE_Bits_A : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) -(*val legalize_misa : Misa -> mword ty64 -> Misa*) +(*val legalize_misa : Misa -> mword ty64 -> M Misa*) + +definition legalize_misa :: " Misa \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(Misa),(exception))monad " where + " legalize_misa (m :: Misa) (v :: xlenbits) = ( + (let v = (Mk_Misa v) in + and_boolM (return (((((get_Misa_C v :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))) + ((read_reg nextPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: xlenbits) . + return (((((cast_unit_vec0 ((access_vec_dec w__0 (( 1 :: int)::ii))) :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) \<bind> (\<lambda> (w__1 :: bool) . + return (if w__1 then m + else update_Misa_C m ((get_Misa_C v :: 1 Word.word))))))" + + +(*val Mk_Mstatus : mword ty64 -> Mstatus*) -definition legalize_misa :: " Misa \<Rightarrow>(64)Word.word \<Rightarrow> Misa " where - " legalize_misa (m :: Misa) (v :: xlenbits) = ( m )" +definition Mk_Mstatus :: "(64)Word.word \<Rightarrow> Mstatus " where + " Mk_Mstatus v = ( + (| Mstatus_Mstatus_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -(*val _get_Mstatus : Mstatus -> mword ty64*) +(*val _get_Mstatus_bits : Mstatus -> mword ty64*) -fun get_Mstatus :: " Mstatus \<Rightarrow>(64)Word.word " where - " get_Mstatus (Mk_Mstatus (v)) = ( v )" +definition get_Mstatus_bits :: " Mstatus \<Rightarrow>(64)Word.word " where + " get_Mstatus_bits v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_Mstatus : register_ref regstate register_value Mstatus -> mword ty64 -> M unit*) +(*val _set_Mstatus_bits : register_ref regstate register_value Mstatus -> mword ty64 -> M unit*) -definition set_Mstatus :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_Mstatus r_ref v = ( +definition set_Mstatus_bits :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_Mstatus v) in + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_Mstatus_bits : Mstatus -> mword ty64 -> Mstatus*) + +definition update_Mstatus_bits :: " Mstatus \<Rightarrow>(64)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_bits v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_Mstatus_SD : Mstatus -> mword ty1*) -fun get_Mstatus_SD :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_SD (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_SD :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_SD v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_SD : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_SD :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_SD r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_SD : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_SD :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_SD (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_SD :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_SD v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sstatus_SD : Sstatus -> mword ty1 -> Sstatus*) @@ -1798,48 +3043,64 @@ fun update_Mstatus_SD :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Msta (*val _get_Mstatus_SXL : Mstatus -> mword ty2*) -fun get_Mstatus_SXL :: " Mstatus \<Rightarrow>(2)Word.word " where - " get_Mstatus_SXL (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 35 :: int)::ii) (( 34 :: int)::ii) :: 2 Word.word))" +definition get_Mstatus_SXL :: " Mstatus \<Rightarrow>(2)Word.word " where + " get_Mstatus_SXL v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 35 :: int)::ii) (( 34 :: int)::ii) :: 2 Word.word))" (*val _set_Mstatus_SXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) definition set_Mstatus_SXL :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_SXL r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 35 :: int)::ii) (( 34 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 35 :: int)::ii) (( 34 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_SXL : Mstatus -> mword ty2 -> Mstatus*) -fun update_Mstatus_SXL :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_SXL (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 35 :: int)::ii) (( 34 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_SXL :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_SXL v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 35 :: int)::ii) (( 34 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" (*val _get_Mstatus_UXL : Mstatus -> mword ty2*) -fun get_Mstatus_UXL :: " Mstatus \<Rightarrow>(2)Word.word " where - " get_Mstatus_UXL (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) :: 2 Word.word))" +definition get_Mstatus_UXL :: " Mstatus \<Rightarrow>(2)Word.word " where + " get_Mstatus_UXL v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 33 :: int)::ii) (( 32 :: int)::ii) :: 2 Word.word))" (*val _set_Mstatus_UXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) definition set_Mstatus_UXL :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_UXL r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 33 :: int)::ii) (( 32 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 33 :: int)::ii) (( 32 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_UXL : Mstatus -> mword ty2 -> Mstatus*) -fun update_Mstatus_UXL :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_UXL (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_UXL :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_UXL v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 33 :: int)::ii) (( 32 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sstatus_UXL : Sstatus -> mword ty2 -> Sstatus*) @@ -1850,94 +3111,126 @@ fun update_Mstatus_UXL :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mst (*val _get_Mstatus_TSR : Mstatus -> mword ty1*) -fun get_Mstatus_TSR :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_TSR (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_TSR :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_TSR v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_TSR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_TSR :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_TSR r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 22 :: int)::ii) (( 22 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_TSR : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_TSR :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_TSR (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_TSR :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_TSR v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 22 :: int)::ii) (( 22 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Mstatus_TW : Mstatus -> mword ty1*) -fun get_Mstatus_TW :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_TW (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_TW :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_TW v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_TW : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_TW :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_TW r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 21 :: int)::ii) (( 21 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 21 :: int)::ii) (( 21 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_TW : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_TW :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_TW (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_TW :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_TW v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 21 :: int)::ii) (( 21 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Mstatus_TVM : Mstatus -> mword ty1*) -fun get_Mstatus_TVM :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_TVM (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_TVM :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_TVM v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_TVM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_TVM :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_TVM r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 20 :: int)::ii) (( 20 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 20 :: int)::ii) (( 20 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_TVM : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_TVM :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_TVM (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_TVM :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_TVM v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 20 :: int)::ii) (( 20 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Mstatus_MXR : Mstatus -> mword ty1*) -fun get_Mstatus_MXR :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_MXR (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_MXR :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_MXR v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_MXR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_MXR :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_MXR r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 19 :: int)::ii) (( 19 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 19 :: int)::ii) (( 19 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_MXR : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_MXR :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_MXR (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_MXR :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_MXR v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sstatus_MXR : Sstatus -> mword ty1 -> Sstatus*) @@ -1948,25 +3241,33 @@ fun update_Mstatus_MXR :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mst (*val _get_Mstatus_SUM : Mstatus -> mword ty1*) -fun get_Mstatus_SUM :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_SUM (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_SUM :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_SUM v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_SUM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_SUM :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_SUM r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 18 :: int)::ii) (( 18 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 18 :: int)::ii) (( 18 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_SUM : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_SUM :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_SUM (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_SUM :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_SUM v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sstatus_SUM : Sstatus -> mword ty1 -> Sstatus*) @@ -1977,48 +3278,64 @@ fun update_Mstatus_SUM :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mst (*val _get_Mstatus_MPRV : Mstatus -> mword ty1*) -fun get_Mstatus_MPRV :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_MPRV (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_MPRV :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_MPRV v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 17 :: int)::ii) (( 17 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_MPRV : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_MPRV :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_MPRV r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 17 :: int)::ii) (( 17 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 17 :: int)::ii) (( 17 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_MPRV : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_MPRV :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_MPRV (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_MPRV :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_MPRV v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 17 :: int)::ii) (( 17 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Mstatus_XS : Mstatus -> mword ty2*) -fun get_Mstatus_XS :: " Mstatus \<Rightarrow>(2)Word.word " where - " get_Mstatus_XS (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word))" +definition get_Mstatus_XS :: " Mstatus \<Rightarrow>(2)Word.word " where + " get_Mstatus_XS v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word))" (*val _set_Mstatus_XS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) definition set_Mstatus_XS :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_XS r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 16 :: int)::ii) (( 15 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 16 :: int)::ii) (( 15 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_XS : Mstatus -> mword ty2 -> Mstatus*) -fun update_Mstatus_XS :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_XS (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_XS :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_XS v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 16 :: int)::ii) (( 15 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sstatus_XS : Sstatus -> mword ty2 -> Sstatus*) @@ -2029,25 +3346,33 @@ fun update_Mstatus_XS :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Msta (*val _get_Mstatus_FS : Mstatus -> mword ty2*) -fun get_Mstatus_FS :: " Mstatus \<Rightarrow>(2)Word.word " where - " get_Mstatus_FS (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word))" +definition get_Mstatus_FS :: " Mstatus \<Rightarrow>(2)Word.word " where + " get_Mstatus_FS v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word))" (*val _set_Mstatus_FS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) definition set_Mstatus_FS :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_FS r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 14 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 14 :: int)::ii) (( 13 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_FS : Mstatus -> mword ty2 -> Mstatus*) -fun update_Mstatus_FS :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_FS (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_FS :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_FS v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 14 :: int)::ii) (( 13 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sstatus_FS : Sstatus -> mword ty2 -> Sstatus*) @@ -2058,48 +3383,64 @@ fun update_Mstatus_FS :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Msta (*val _get_Mstatus_MPP : Mstatus -> mword ty2*) -fun get_Mstatus_MPP :: " Mstatus \<Rightarrow>(2)Word.word " where - " get_Mstatus_MPP (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word))" +definition get_Mstatus_MPP :: " Mstatus \<Rightarrow>(2)Word.word " where + " get_Mstatus_MPP v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word))" (*val _set_Mstatus_MPP : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) definition set_Mstatus_MPP :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_MPP r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 12 :: int)::ii) (( 11 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 12 :: int)::ii) (( 11 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_MPP : Mstatus -> mword ty2 -> Mstatus*) -fun update_Mstatus_MPP :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_MPP (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 12 :: int)::ii) (( 11 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_MPP :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_MPP v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 12 :: int)::ii) (( 11 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" (*val _get_Mstatus_SPP : Mstatus -> mword ty1*) -fun get_Mstatus_SPP :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_SPP (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_SPP :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_SPP v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_SPP : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_SPP :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_SPP r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_SPP : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_SPP :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_SPP (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_SPP :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_SPP v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sstatus_SPP : Sstatus -> mword ty1 -> Sstatus*) @@ -2110,48 +3451,64 @@ fun update_Mstatus_SPP :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mst (*val _get_Mstatus_MPIE : Mstatus -> mword ty1*) -fun get_Mstatus_MPIE :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_MPIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_MPIE :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_MPIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_MPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_MPIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_MPIE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_MPIE : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_MPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_MPIE (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_MPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_MPIE v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Mstatus_SPIE : Mstatus -> mword ty1*) -fun get_Mstatus_SPIE :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_SPIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_SPIE :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_SPIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_SPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_SPIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_SPIE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_SPIE : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_SPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_SPIE (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_SPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_SPIE v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sstatus_SPIE : Sstatus -> mword ty1 -> Sstatus*) @@ -2162,25 +3519,33 @@ fun update_Mstatus_SPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Ms (*val _get_Mstatus_UPIE : Mstatus -> mword ty1*) -fun get_Mstatus_UPIE :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_UPIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_UPIE :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_UPIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_UPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_UPIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_UPIE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_UPIE : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_UPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_UPIE (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_UPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_UPIE v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sstatus_UPIE : Sstatus -> mword ty1 -> Sstatus*) @@ -2191,48 +3556,64 @@ fun update_Mstatus_UPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Ms (*val _get_Mstatus_MIE : Mstatus -> mword ty1*) -fun get_Mstatus_MIE :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_MIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_MIE :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_MIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_MIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_MIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_MIE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_MIE : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_MIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_MIE (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_MIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_MIE v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Mstatus_SIE : Mstatus -> mword ty1*) -fun get_Mstatus_SIE :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_SIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_SIE :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_SIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_SIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_SIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_SIE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_SIE : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_SIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_SIE (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_SIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_SIE v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sstatus_SIE : Sstatus -> mword ty1 -> Sstatus*) @@ -2243,25 +3624,33 @@ fun update_Mstatus_SIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mst (*val _get_Mstatus_UIE : Mstatus -> mword ty1*) -fun get_Mstatus_UIE :: " Mstatus \<Rightarrow>(1)Word.word " where - " get_Mstatus_UIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_Mstatus_UIE :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_UIE v = ( (subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" (*val _set_Mstatus_UIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) definition set_Mstatus_UIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mstatus_UIE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - (let r = ((get_Mstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mstatus_UIE : Mstatus -> mword ty1 -> Mstatus*) -fun update_Mstatus_UIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where - " update_Mstatus_UIE (Mk_Mstatus (v)) x = ( - Mk_Mstatus ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_Mstatus_UIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_UIE v x = ( + (v (| + Mstatus_Mstatus_chunk_0 := + ((update_subrange_vec_dec(Mstatus_Mstatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sstatus_UIE : Sstatus -> mword ty1 -> Sstatus*) @@ -2349,65 +3738,122 @@ definition haveFP :: " unit \<Rightarrow>((register_value),(bool),(exception))m return (((((get_Misa_D w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))))" -(*val _get_Minterrupts : Minterrupts -> mword ty64*) +(*val pc_alignment_mask : unit -> M (mword ty64)*) + +definition pc_alignment_mask :: " unit \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " pc_alignment_mask _ = ( + read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) . + return ((not_vec + ((EXTZ (( 64 :: int)::ii) + (if (((((get_Misa_C w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + (vec_of_bits [B0,B0] :: 2 Word.word) + else (vec_of_bits [B1,B0] :: 2 Word.word)) + :: 64 Word.word)) + :: 64 Word.word))))" + + +(*val Mk_Minterrupts : mword ty64 -> Minterrupts*) + +definition Mk_Minterrupts :: "(64)Word.word \<Rightarrow> Minterrupts " where + " Mk_Minterrupts v = ( + (| Minterrupts_Minterrupts_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" + -fun get_Minterrupts :: " Minterrupts \<Rightarrow>(64)Word.word " where - " get_Minterrupts (Mk_Minterrupts (v)) = ( v )" +(*val _get_Minterrupts_bits : Minterrupts -> mword ty64*) +definition get_Minterrupts_bits :: " Minterrupts \<Rightarrow>(64)Word.word " where + " get_Minterrupts_bits v = ( + (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_Minterrupts : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit*) -definition set_Minterrupts :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_Minterrupts r_ref v = ( +(*val _set_Minterrupts_bits : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit*) + +definition set_Minterrupts_bits :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Minterrupts_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_Minterrupts v) in + (let r = + ((r (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_Minterrupts_bits : Minterrupts -> mword ty64 -> Minterrupts*) + +definition update_Minterrupts_bits :: " Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_bits v x = ( + (v (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_Minterrupts_MEI : Minterrupts -> mword ty1*) -fun get_Minterrupts_MEI :: " Minterrupts \<Rightarrow>(1)Word.word " where - " get_Minterrupts_MEI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word))" +definition get_Minterrupts_MEI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_MEI v = ( + (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word))" (*val _set_Minterrupts_MEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) definition set_Minterrupts_MEI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Minterrupts_MEI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . - (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 11 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Minterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 11 :: int)::ii) (( 11 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Minterrupts_MEI : Minterrupts -> mword ty1 -> Minterrupts*) -fun update_Minterrupts_MEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where - " update_Minterrupts_MEI (Mk_Minterrupts (v)) x = ( - Mk_Minterrupts ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) x :: 64 Word.word)))" +definition update_Minterrupts_MEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_MEI v x = ( + (v (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 11 :: int)::ii) (( 11 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Minterrupts_SEI : Minterrupts -> mword ty1*) -fun get_Minterrupts_SEI :: " Minterrupts \<Rightarrow>(1)Word.word " where - " get_Minterrupts_SEI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" +definition get_Minterrupts_SEI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_SEI v = ( + (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" (*val _set_Minterrupts_SEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) definition set_Minterrupts_SEI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Minterrupts_SEI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . - (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Minterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 9 :: int)::ii) (( 9 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Minterrupts_SEI : Minterrupts -> mword ty1 -> Minterrupts*) -fun update_Minterrupts_SEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where - " update_Minterrupts_SEI (Mk_Minterrupts (v)) x = ( - Mk_Minterrupts ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x :: 64 Word.word)))" +definition update_Minterrupts_SEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_SEI v x = ( + (v (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sinterrupts_SEI : Sinterrupts -> mword ty1 -> Sinterrupts*) @@ -2418,25 +3864,34 @@ fun update_Minterrupts_SEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightar (*val _get_Minterrupts_UEI : Minterrupts -> mword ty1*) -fun get_Minterrupts_UEI :: " Minterrupts \<Rightarrow>(1)Word.word " where - " get_Minterrupts_UEI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" +definition get_Minterrupts_UEI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_UEI v = ( + (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" (*val _set_Minterrupts_UEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) definition set_Minterrupts_UEI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Minterrupts_UEI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . - (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Minterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Minterrupts_UEI : Minterrupts -> mword ty1 -> Minterrupts*) -fun update_Minterrupts_UEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where - " update_Minterrupts_UEI (Mk_Minterrupts (v)) x = ( - Mk_Minterrupts ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" +definition update_Minterrupts_UEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_UEI v x = ( + (v (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sinterrupts_UEI : Sinterrupts -> mword ty1 -> Sinterrupts*) @@ -2447,48 +3902,66 @@ fun update_Minterrupts_UEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightar (*val _get_Minterrupts_MTI : Minterrupts -> mword ty1*) -fun get_Minterrupts_MTI :: " Minterrupts \<Rightarrow>(1)Word.word " where - " get_Minterrupts_MTI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" +definition get_Minterrupts_MTI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_MTI v = ( + (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" (*val _set_Minterrupts_MTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) definition set_Minterrupts_MTI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Minterrupts_MTI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . - (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Minterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Minterrupts_MTI : Minterrupts -> mword ty1 -> Minterrupts*) -fun update_Minterrupts_MTI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where - " update_Minterrupts_MTI (Mk_Minterrupts (v)) x = ( - Mk_Minterrupts ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" +definition update_Minterrupts_MTI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_MTI v x = ( + (v (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Minterrupts_STI : Minterrupts -> mword ty1*) -fun get_Minterrupts_STI :: " Minterrupts \<Rightarrow>(1)Word.word " where - " get_Minterrupts_STI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" +definition get_Minterrupts_STI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_STI v = ( + (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" (*val _set_Minterrupts_STI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) definition set_Minterrupts_STI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Minterrupts_STI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . - (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Minterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Minterrupts_STI : Minterrupts -> mword ty1 -> Minterrupts*) -fun update_Minterrupts_STI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where - " update_Minterrupts_STI (Mk_Minterrupts (v)) x = ( - Mk_Minterrupts ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" +definition update_Minterrupts_STI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_STI v x = ( + (v (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sinterrupts_STI : Sinterrupts -> mword ty1 -> Sinterrupts*) @@ -2499,25 +3972,34 @@ fun update_Minterrupts_STI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightar (*val _get_Minterrupts_UTI : Minterrupts -> mword ty1*) -fun get_Minterrupts_UTI :: " Minterrupts \<Rightarrow>(1)Word.word " where - " get_Minterrupts_UTI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" +definition get_Minterrupts_UTI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_UTI v = ( + (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" (*val _set_Minterrupts_UTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) definition set_Minterrupts_UTI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Minterrupts_UTI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . - (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Minterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Minterrupts_UTI : Minterrupts -> mword ty1 -> Minterrupts*) -fun update_Minterrupts_UTI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where - " update_Minterrupts_UTI (Mk_Minterrupts (v)) x = ( - Mk_Minterrupts ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" +definition update_Minterrupts_UTI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_UTI v x = ( + (v (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sinterrupts_UTI : Sinterrupts -> mword ty1 -> Sinterrupts*) @@ -2528,48 +4010,66 @@ fun update_Minterrupts_UTI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightar (*val _get_Minterrupts_MSI : Minterrupts -> mword ty1*) -fun get_Minterrupts_MSI :: " Minterrupts \<Rightarrow>(1)Word.word " where - " get_Minterrupts_MSI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" +definition get_Minterrupts_MSI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_MSI v = ( + (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" (*val _set_Minterrupts_MSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) definition set_Minterrupts_MSI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Minterrupts_MSI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . - (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Minterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Minterrupts_MSI : Minterrupts -> mword ty1 -> Minterrupts*) -fun update_Minterrupts_MSI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where - " update_Minterrupts_MSI (Mk_Minterrupts (v)) x = ( - Mk_Minterrupts ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" +definition update_Minterrupts_MSI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_MSI v x = ( + (v (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Minterrupts_SSI : Minterrupts -> mword ty1*) -fun get_Minterrupts_SSI :: " Minterrupts \<Rightarrow>(1)Word.word " where - " get_Minterrupts_SSI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_Minterrupts_SSI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_SSI v = ( + (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" (*val _set_Minterrupts_SSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) definition set_Minterrupts_SSI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Minterrupts_SSI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . - (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Minterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Minterrupts_SSI : Minterrupts -> mword ty1 -> Minterrupts*) -fun update_Minterrupts_SSI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where - " update_Minterrupts_SSI (Mk_Minterrupts (v)) x = ( - Mk_Minterrupts ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" +definition update_Minterrupts_SSI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_SSI v x = ( + (v (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sinterrupts_SSI : Sinterrupts -> mword ty1 -> Sinterrupts*) @@ -2580,25 +4080,34 @@ fun update_Minterrupts_SSI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightar (*val _get_Minterrupts_USI : Minterrupts -> mword ty1*) -fun get_Minterrupts_USI :: " Minterrupts \<Rightarrow>(1)Word.word " where - " get_Minterrupts_USI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_Minterrupts_USI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_USI v = ( + (subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" (*val _set_Minterrupts_USI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) definition set_Minterrupts_USI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Minterrupts_USI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . - (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Minterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Minterrupts_USI : Minterrupts -> mword ty1 -> Minterrupts*) -fun update_Minterrupts_USI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where - " update_Minterrupts_USI (Mk_Minterrupts (v)) x = ( - Mk_Minterrupts ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_Minterrupts_USI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_USI v x = ( + (v (| + Minterrupts_Minterrupts_chunk_0 := + ((update_subrange_vec_dec(Minterrupts_Minterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sinterrupts_USI : Sinterrupts -> mword ty1 -> Sinterrupts*) @@ -2640,160 +4149,234 @@ definition legalize_mideleg :: " Minterrupts \<Rightarrow>(64)Word.word \<Right update_Minterrupts_MSI m ((bool_to_bits False :: 1 Word.word))))))" -(*val _get_Medeleg : Medeleg -> mword ty64*) +(*val Mk_Medeleg : mword ty64 -> Medeleg*) -fun get_Medeleg :: " Medeleg \<Rightarrow>(64)Word.word " where - " get_Medeleg (Mk_Medeleg (v)) = ( v )" +definition Mk_Medeleg :: "(64)Word.word \<Rightarrow> Medeleg " where + " Mk_Medeleg v = ( + (| Medeleg_Medeleg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -(*val _set_Medeleg : register_ref regstate register_value Medeleg -> mword ty64 -> M unit*) +(*val _get_Medeleg_bits : Medeleg -> mword ty64*) -definition set_Medeleg :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_Medeleg r_ref v = ( +definition get_Medeleg_bits :: " Medeleg \<Rightarrow>(64)Word.word " where + " get_Medeleg_bits v = ( (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" + + +(*val _set_Medeleg_bits : register_ref regstate register_value Medeleg -> mword ty64 -> M unit*) + +definition set_Medeleg_bits :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_Medeleg v) in + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_Medeleg_bits : Medeleg -> mword ty64 -> Medeleg*) + +definition update_Medeleg_bits :: " Medeleg \<Rightarrow>(64)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_bits v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1*) -fun get_Medeleg_SAMO_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_SAMO_Page_Fault (Mk_Medeleg (v)) = ( - (subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_SAMO_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_SAMO_Page_Fault v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_SAMO_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_SAMO_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_SAMO_Page_Fault r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 15 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 15 :: int)::ii) (( 15 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_SAMO_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_SAMO_Page_Fault (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_SAMO_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_SAMO_Page_Fault v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 15 :: int)::ii) (( 15 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Medeleg_Load_Page_Fault : Medeleg -> mword ty1*) -fun get_Medeleg_Load_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_Load_Page_Fault (Mk_Medeleg (v)) = ( - (subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_Load_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Load_Page_Fault v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 13 :: int)::ii) (( 13 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_Load_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_Load_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_Load_Page_Fault r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 13 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 13 :: int)::ii) (( 13 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_Load_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_Load_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_Load_Page_Fault (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_Load_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Load_Page_Fault v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 13 :: int)::ii) (( 13 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1*) -fun get_Medeleg_Fetch_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_Fetch_Page_Fault (Mk_Medeleg (v)) = ( - (subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_Fetch_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Fetch_Page_Fault v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_Fetch_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_Fetch_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_Fetch_Page_Fault r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 12 :: int)::ii) (( 12 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 12 :: int)::ii) (( 12 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_Fetch_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_Fetch_Page_Fault (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_Fetch_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Fetch_Page_Fault v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 12 :: int)::ii) (( 12 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Medeleg_MEnvCall : Medeleg -> mword ty1*) -fun get_Medeleg_MEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_MEnvCall (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_MEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_MEnvCall v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_MEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_MEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_MEnvCall r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 10 :: int)::ii) (( 10 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 10 :: int)::ii) (( 10 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_MEnvCall : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_MEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_MEnvCall (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_MEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_MEnvCall v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 10 :: int)::ii) (( 10 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Medeleg_SEnvCall : Medeleg -> mword ty1*) -fun get_Medeleg_SEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_SEnvCall (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_SEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_SEnvCall v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_SEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_SEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_SEnvCall r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 9 :: int)::ii) (( 9 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_SEnvCall : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_SEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_SEnvCall (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_SEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_SEnvCall v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Medeleg_UEnvCall : Medeleg -> mword ty1*) -fun get_Medeleg_UEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_UEnvCall (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_UEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_UEnvCall v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_UEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_UEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_UEnvCall r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_UEnvCall : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_UEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_UEnvCall (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_UEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_UEnvCall v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sedeleg_UEnvCall : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2804,26 +4387,34 @@ fun update_Medeleg_UEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow (*val _get_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1*) -fun get_Medeleg_SAMO_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_SAMO_Access_Fault (Mk_Medeleg (v)) = ( - (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_SAMO_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_SAMO_Access_Fault v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_SAMO_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_SAMO_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_SAMO_Access_Fault r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_SAMO_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_SAMO_Access_Fault (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_SAMO_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_SAMO_Access_Fault v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2834,25 +4425,34 @@ fun update_Medeleg_SAMO_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<R (*val _get_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1*) -fun get_Medeleg_SAMO_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_SAMO_Addr_Align (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_SAMO_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_SAMO_Addr_Align v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_SAMO_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_SAMO_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_SAMO_Addr_Align r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_SAMO_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_SAMO_Addr_Align (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_SAMO_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_SAMO_Addr_Align v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2863,26 +4463,34 @@ fun update_Medeleg_SAMO_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rig (*val _get_Medeleg_Load_Access_Fault : Medeleg -> mword ty1*) -fun get_Medeleg_Load_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_Load_Access_Fault (Mk_Medeleg (v)) = ( - (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_Load_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Load_Access_Fault v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_Load_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_Load_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_Load_Access_Fault r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_Load_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_Load_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_Load_Access_Fault (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_Load_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Load_Access_Fault v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2893,25 +4501,34 @@ fun update_Medeleg_Load_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<R (*val _get_Medeleg_Load_Addr_Align : Medeleg -> mword ty1*) -fun get_Medeleg_Load_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_Load_Addr_Align (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_Load_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Load_Addr_Align v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_Load_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_Load_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_Load_Addr_Align r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_Load_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_Load_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_Load_Addr_Align (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_Load_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Load_Addr_Align v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2922,25 +4539,34 @@ fun update_Medeleg_Load_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rig (*val _get_Medeleg_Breakpoint : Medeleg -> mword ty1*) -fun get_Medeleg_Breakpoint :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_Breakpoint (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_Breakpoint :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Breakpoint v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_Breakpoint : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_Breakpoint :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_Breakpoint r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_Breakpoint : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_Breakpoint :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_Breakpoint (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_Breakpoint :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Breakpoint v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sedeleg_Breakpoint : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2951,25 +4577,34 @@ fun update_Medeleg_Breakpoint :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarr (*val _get_Medeleg_Illegal_Instr : Medeleg -> mword ty1*) -fun get_Medeleg_Illegal_Instr :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_Illegal_Instr (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_Illegal_Instr :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Illegal_Instr v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_Illegal_Instr : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_Illegal_Instr :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_Illegal_Instr r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_Illegal_Instr : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_Illegal_Instr :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_Illegal_Instr (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_Illegal_Instr :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Illegal_Instr v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1 -> Sedeleg*) @@ -2980,26 +4615,34 @@ fun update_Medeleg_Illegal_Instr :: " Medeleg \<Rightarrow>(1)Word.word \<Right (*val _get_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1*) -fun get_Medeleg_Fetch_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_Fetch_Access_Fault (Mk_Medeleg (v)) = ( - (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_Fetch_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Fetch_Access_Fault v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_Fetch_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_Fetch_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_Fetch_Access_Fault r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_Fetch_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_Fetch_Access_Fault (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_Fetch_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Fetch_Access_Fault v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) @@ -3010,25 +4653,34 @@ fun update_Medeleg_Fetch_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \< (*val _get_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1*) -fun get_Medeleg_Fetch_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where - " get_Medeleg_Fetch_Addr_Align (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_Medeleg_Fetch_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Fetch_Addr_Align v = ( + (subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" (*val _set_Medeleg_Fetch_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) definition set_Medeleg_Fetch_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Medeleg_Fetch_Addr_Align r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let r = ((get_Medeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Medeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) -fun update_Medeleg_Fetch_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where - " update_Medeleg_Fetch_Addr_Align (Mk_Medeleg (v)) x = ( - Mk_Medeleg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_Medeleg_Fetch_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Fetch_Addr_Align v x = ( + (v (| + Medeleg_Medeleg_chunk_0 := + ((update_subrange_vec_dec(Medeleg_Medeleg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _update_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) @@ -3045,65 +4697,103 @@ definition legalize_medeleg :: " Medeleg \<Rightarrow>(64)Word.word \<Rightarro update_Medeleg_MEnvCall m ((bool_to_bits False :: 1 Word.word))))" -(*val _get_Mtvec : Mtvec -> mword ty64*) +(*val Mk_Mtvec : mword ty64 -> Mtvec*) + +definition Mk_Mtvec :: "(64)Word.word \<Rightarrow> Mtvec " where + " Mk_Mtvec v = ( (| Mtvec_Mtvec_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" + -fun get_Mtvec :: " Mtvec \<Rightarrow>(64)Word.word " where - " get_Mtvec (Mk_Mtvec (v)) = ( v )" +(*val _get_Mtvec_bits : Mtvec -> mword ty64*) +definition get_Mtvec_bits :: " Mtvec \<Rightarrow>(64)Word.word " where + " get_Mtvec_bits v = ( (subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_Mtvec : register_ref regstate register_value Mtvec -> mword ty64 -> M unit*) -definition set_Mtvec :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_Mtvec r_ref v = ( +(*val _set_Mtvec_bits : register_ref regstate register_value Mtvec -> mword ty64 -> M unit*) + +definition set_Mtvec_bits :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mtvec_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_Mtvec v) in + (let r = + ((r (| + Mtvec_Mtvec_chunk_0 := + ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_Mtvec_bits : Mtvec -> mword ty64 -> Mtvec*) + +definition update_Mtvec_bits :: " Mtvec \<Rightarrow>(64)Word.word \<Rightarrow> Mtvec " where + " update_Mtvec_bits v x = ( + (v (| + Mtvec_Mtvec_chunk_0 := + ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_Mtvec_Base : Mtvec -> mword ty62*) -fun get_Mtvec_Base :: " Mtvec \<Rightarrow>(62)Word.word " where - " get_Mtvec_Base (Mk_Mtvec (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word))" +definition get_Mtvec_Base :: " Mtvec \<Rightarrow>(62)Word.word " where + " get_Mtvec_Base v = ( (subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word))" (*val _set_Mtvec_Base : register_ref regstate register_value Mtvec -> mword ty62 -> M unit*) definition set_Mtvec_Base :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(62)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mtvec_Base r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mtvec) . - (let r = ((get_Mtvec w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mtvec r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mtvec_Mtvec_chunk_0 := + ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 r) (( 63 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 61 :: int)::ii) (( 0 :: int)::ii) :: 62 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mtvec_Base : Mtvec -> mword ty62 -> Mtvec*) -fun update_Mtvec_Base :: " Mtvec \<Rightarrow>(62)Word.word \<Rightarrow> Mtvec " where - " update_Mtvec_Base (Mk_Mtvec (v)) x = ( - Mk_Mtvec ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" +definition update_Mtvec_Base :: " Mtvec \<Rightarrow>(62)Word.word \<Rightarrow> Mtvec " where + " update_Mtvec_Base v x = ( + (v (| + Mtvec_Mtvec_chunk_0 := + ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 63 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 61 :: int)::ii) (( 0 :: int)::ii) :: 62 Word.word)) + :: 64 Word.word))|)))" (*val _get_Mtvec_Mode : Mtvec -> mword ty2*) -fun get_Mtvec_Mode :: " Mtvec \<Rightarrow>(2)Word.word " where - " get_Mtvec_Mode (Mk_Mtvec (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))" +definition get_Mtvec_Mode :: " Mtvec \<Rightarrow>(2)Word.word " where + " get_Mtvec_Mode v = ( (subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))" (*val _set_Mtvec_Mode : register_ref regstate register_value Mtvec -> mword ty2 -> M unit*) definition set_Mtvec_Mode :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mtvec_Mode r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mtvec) . - (let r = ((get_Mtvec w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mtvec r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mtvec_Mtvec_chunk_0 := + ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 r) (( 1 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mtvec_Mode : Mtvec -> mword ty2 -> Mtvec*) -fun update_Mtvec_Mode :: " Mtvec \<Rightarrow>(2)Word.word \<Rightarrow> Mtvec " where - " update_Mtvec_Mode (Mk_Mtvec (v)) x = ( - Mk_Mtvec ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_Mtvec_Mode :: " Mtvec \<Rightarrow>(2)Word.word \<Rightarrow> Mtvec " where + " update_Mtvec_Mode v x = ( + (v (| + Mtvec_Mtvec_chunk_0 := + ((update_subrange_vec_dec(Mtvec_Mtvec_chunk_0 v) (( 1 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" (*val _update_Satp64_Mode : Satp64 -> mword ty4 -> Satp64*) @@ -3124,65 +4814,104 @@ definition legalize_tvec :: " Mtvec \<Rightarrow>(64)Word.word \<Rightarrow> Mt )))" -(*val _get_Mcause : Mcause -> mword ty64*) +(*val Mk_Mcause : mword ty64 -> Mcause*) + +definition Mk_Mcause :: "(64)Word.word \<Rightarrow> Mcause " where + " Mk_Mcause v = ( (| Mcause_Mcause_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" + -fun get_Mcause :: " Mcause \<Rightarrow>(64)Word.word " where - " get_Mcause (Mk_Mcause (v)) = ( v )" +(*val _get_Mcause_bits : Mcause -> mword ty64*) +definition get_Mcause_bits :: " Mcause \<Rightarrow>(64)Word.word " where + " get_Mcause_bits v = ( (subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_Mcause : register_ref regstate register_value Mcause -> mword ty64 -> M unit*) -definition set_Mcause :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_Mcause r_ref v = ( +(*val _set_Mcause_bits : register_ref regstate register_value Mcause -> mword ty64 -> M unit*) + +definition set_Mcause_bits :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mcause_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_Mcause v) in + (let r = + ((r (| + Mcause_Mcause_chunk_0 := + ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" +(*val _update_Mcause_bits : Mcause -> mword ty64 -> Mcause*) + +definition update_Mcause_bits :: " Mcause \<Rightarrow>(64)Word.word \<Rightarrow> Mcause " where + " update_Mcause_bits v x = ( + (v (| + Mcause_Mcause_chunk_0 := + ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + (*val _get_Mcause_IsInterrupt : Mcause -> mword ty1*) -fun get_Mcause_IsInterrupt :: " Mcause \<Rightarrow>(1)Word.word " where - " get_Mcause_IsInterrupt (Mk_Mcause (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" +definition get_Mcause_IsInterrupt :: " Mcause \<Rightarrow>(1)Word.word " where + " get_Mcause_IsInterrupt v = ( + (subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" (*val _set_Mcause_IsInterrupt : register_ref regstate register_value Mcause -> mword ty1 -> M unit*) definition set_Mcause_IsInterrupt :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mcause_IsInterrupt r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mcause) . - (let r = ((get_Mcause w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mcause r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mcause_Mcause_chunk_0 := + ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 r) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mcause_IsInterrupt : Mcause -> mword ty1 -> Mcause*) -fun update_Mcause_IsInterrupt :: " Mcause \<Rightarrow>(1)Word.word \<Rightarrow> Mcause " where - " update_Mcause_IsInterrupt (Mk_Mcause (v)) x = ( - Mk_Mcause ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" +definition update_Mcause_IsInterrupt :: " Mcause \<Rightarrow>(1)Word.word \<Rightarrow> Mcause " where + " update_Mcause_IsInterrupt v x = ( + (v (| + Mcause_Mcause_chunk_0 := + ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val _get_Mcause_Cause : Mcause -> mword ty63*) -fun get_Mcause_Cause :: " Mcause \<Rightarrow>(63)Word.word " where - " get_Mcause_Cause (Mk_Mcause (v)) = ( (subrange_vec_dec v (( 62 :: int)::ii) (( 0 :: int)::ii) :: 63 Word.word))" +definition get_Mcause_Cause :: " Mcause \<Rightarrow>(63)Word.word " where + " get_Mcause_Cause v = ( (subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 62 :: int)::ii) (( 0 :: int)::ii) :: 63 Word.word))" (*val _set_Mcause_Cause : register_ref regstate register_value Mcause -> mword ty63 -> M unit*) definition set_Mcause_Cause :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(63)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Mcause_Cause r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mcause) . - (let r = ((get_Mcause w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Mcause r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Mcause_Mcause_chunk_0 := + ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 r) (( 62 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 62 :: int)::ii) (( 0 :: int)::ii) :: 63 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Mcause_Cause : Mcause -> mword ty63 -> Mcause*) -fun update_Mcause_Cause :: " Mcause \<Rightarrow>(63)Word.word \<Rightarrow> Mcause " where - " update_Mcause_Cause (Mk_Mcause (v)) x = ( - Mk_Mcause ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_Mcause_Cause :: " Mcause \<Rightarrow>(63)Word.word \<Rightarrow> Mcause " where + " update_Mcause_Cause v x = ( + (v (| + Mcause_Mcause_chunk_0 := + ((update_subrange_vec_dec(Mcause_Mcause_chunk_0 v) (( 62 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 62 :: int)::ii) (( 0 :: int)::ii) :: 63 Word.word)) + :: 64 Word.word))|)))" (*val tvec_addr : Mtvec -> Mcause -> maybe (mword ty64)*) @@ -3221,206 +4950,514 @@ definition legalize_xepc :: "(64)Word.word \<Rightarrow>((register_value),((64) :: 64 Word.word))))" -(*val _get_Sstatus : Sstatus -> mword ty64*) +(*val Mk_Counteren : mword ty32 -> Counteren*) + +definition Mk_Counteren :: "(32)Word.word \<Rightarrow> Counteren " where + " Mk_Counteren v = ( + (| Counteren_Counteren_chunk_0 = ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) |) )" + + +(*val _get_Counteren_bits : Counteren -> mword ty32*) + +definition get_Counteren_bits :: " Counteren \<Rightarrow>(32)Word.word " where + " get_Counteren_bits v = ( + (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))" + + +(*val _set_Counteren_bits : register_ref regstate register_value Counteren -> mword ty32 -> M unit*) + +definition set_Counteren_bits :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Counteren_bits r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 31 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" + + +(*val _update_Counteren_bits : Counteren -> mword ty32 -> Counteren*) -fun get_Sstatus :: " Sstatus \<Rightarrow>(64)Word.word " where - " get_Sstatus (Mk_Sstatus (v)) = ( v )" +definition update_Counteren_bits :: " Counteren \<Rightarrow>(32)Word.word \<Rightarrow> Counteren " where + " update_Counteren_bits v x = ( + (v (| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 31 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word))|)))" -(*val _set_Sstatus : register_ref regstate register_value Sstatus -> mword ty64 -> M unit*) +(*val _get_Counteren_HPM : Counteren -> mword ty29*) -definition set_Sstatus :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_Sstatus r_ref v = ( +definition get_Counteren_HPM :: " Counteren \<Rightarrow>(29)Word.word " where + " get_Counteren_HPM v = ( + (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 31 :: int)::ii) (( 3 :: int)::ii) :: 29 Word.word))" + + +(*val _set_Counteren_HPM : register_ref regstate register_value Counteren -> mword ty29 -> M unit*) + +definition set_Counteren_HPM :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(29)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Counteren_HPM r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 31 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec v (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" + + +(*val _update_Counteren_HPM : Counteren -> mword ty29 -> Counteren*) + +definition update_Counteren_HPM :: " Counteren \<Rightarrow>(29)Word.word \<Rightarrow> Counteren " where + " update_Counteren_HPM v x = ( + (v (| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 31 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec x (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word)) + :: 32 Word.word))|)))" + + +(*val _get_Counteren_IR : Counteren -> mword ty1*) + +definition get_Counteren_IR :: " Counteren \<Rightarrow>(1)Word.word " where + " get_Counteren_IR v = ( + (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Counteren_IR : register_ref regstate register_value Counteren -> mword ty1 -> M unit*) + +definition set_Counteren_IR :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Counteren_IR r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" + + +(*val _update_Counteren_IR : Counteren -> mword ty1 -> Counteren*) + +definition update_Counteren_IR :: " Counteren \<Rightarrow>(1)Word.word \<Rightarrow> Counteren " where + " update_Counteren_IR v x = ( + (v (| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" + + +(*val _get_Counteren_TM : Counteren -> mword ty1*) + +definition get_Counteren_TM :: " Counteren \<Rightarrow>(1)Word.word " where + " get_Counteren_TM v = ( + (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Counteren_TM : register_ref regstate register_value Counteren -> mword ty1 -> M unit*) + +definition set_Counteren_TM :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Counteren_TM r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in + write_reg r_ref r)))" + + +(*val _update_Counteren_TM : Counteren -> mword ty1 -> Counteren*) + +definition update_Counteren_TM :: " Counteren \<Rightarrow>(1)Word.word \<Rightarrow> Counteren " where + " update_Counteren_TM v x = ( + (v (| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" + + +(*val _get_Counteren_CY : Counteren -> mword ty1*) + +definition get_Counteren_CY :: " Counteren \<Rightarrow>(1)Word.word " where + " get_Counteren_CY v = ( + (subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Counteren_CY : register_ref regstate register_value Counteren -> mword ty1 -> M unit*) + +definition set_Counteren_CY :: "((regstate),(register_value),(Counteren))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Counteren_CY r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_Sstatus v) in + (let r = + ((r (| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|))) in write_reg r_ref r)))" -fun get_Sstatus_SD :: " Sstatus \<Rightarrow>(1)Word.word " where - " get_Sstatus_SD (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" +(*val _update_Counteren_CY : Counteren -> mword ty1 -> Counteren*) + +definition update_Counteren_CY :: " Counteren \<Rightarrow>(1)Word.word \<Rightarrow> Counteren " where + " update_Counteren_CY v x = ( + (v (| + Counteren_Counteren_chunk_0 := + ((update_subrange_vec_dec(Counteren_Counteren_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 32 Word.word))|)))" + + +(*val legalize_mcounteren : Counteren -> mword ty64 -> Counteren*) + +definition legalize_mcounteren :: " Counteren \<Rightarrow>(64)Word.word \<Rightarrow> Counteren " where + " legalize_mcounteren (c :: Counteren) (v :: xlenbits) = ( + (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 :: int)::ii))) :: 1 Word.word))) in + (let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 :: int)::ii))) :: 1 Word.word))) in + update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 :: int)::ii))) :: 1 Word.word)))))" + + +(*val legalize_scounteren : Counteren -> mword ty64 -> Counteren*) + +definition legalize_scounteren :: " Counteren \<Rightarrow>(64)Word.word \<Rightarrow> Counteren " where + " legalize_scounteren (c :: Counteren) (v :: xlenbits) = ( + (let c = (update_Counteren_IR c ((cast_unit_vec0 ((access_vec_dec v (( 2 :: int)::ii))) :: 1 Word.word))) in + (let c = (update_Counteren_TM c ((cast_unit_vec0 ((access_vec_dec v (( 1 :: int)::ii))) :: 1 Word.word))) in + update_Counteren_CY c ((cast_unit_vec0 ((access_vec_dec v (( 0 :: int)::ii))) :: 1 Word.word)))))" + + +(*val retire_instruction : unit -> M unit*) + +definition retire_instruction :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " retire_instruction _ = ( + read_reg minstret_written_ref \<bind> (\<lambda> (w__0 :: bool) . + if (((((bool_to_bits w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + write_reg minstret_written_ref False + else + (read_reg minstret_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + write_reg minstret_ref ((add_vec_int w__1 (( 1 :: int)::ii) :: 64 Word.word)))))" + + +(*val Mk_Sstatus : mword ty64 -> Sstatus*) + +definition Mk_Sstatus :: "(64)Word.word \<Rightarrow> Sstatus " where + " Mk_Sstatus v = ( + (| Sstatus_Sstatus_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" + + +(*val _get_Sstatus_bits : Sstatus -> mword ty64*) + +definition get_Sstatus_bits :: " Sstatus \<Rightarrow>(64)Word.word " where + " get_Sstatus_bits v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" + + +(*val _set_Sstatus_bits : register_ref regstate register_value Sstatus -> mword ty64 -> M unit*) + +definition set_Sstatus_bits :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus_bits r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" + + +(*val _update_Sstatus_bits : Sstatus -> mword ty64 -> Sstatus*) + +definition update_Sstatus_bits :: " Sstatus \<Rightarrow>(64)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_bits v x = ( + (v (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + +definition get_Sstatus_SD :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_SD v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" definition set_Sstatus_SD :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sstatus_SD r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . - (let r = ((get_Sstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sstatus_SD :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where - " update_Sstatus_SD (Mk_Sstatus (v)) x = ( - Mk_Sstatus ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" +definition update_Sstatus_SD :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_SD v x = ( + (v (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 63 :: int)::ii) (( 63 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sstatus_UXL :: " Sstatus \<Rightarrow>(2)Word.word " where - " get_Sstatus_UXL (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) :: 2 Word.word))" +definition get_Sstatus_UXL :: " Sstatus \<Rightarrow>(2)Word.word " where + " get_Sstatus_UXL v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 33 :: int)::ii) (( 32 :: int)::ii) :: 2 Word.word))" definition set_Sstatus_UXL :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sstatus_UXL r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . - (let r = ((get_Sstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 33 :: int)::ii) (( 32 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 33 :: int)::ii) (( 32 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sstatus_UXL :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where - " update_Sstatus_UXL (Mk_Sstatus (v)) x = ( - Mk_Sstatus ((update_subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) x :: 64 Word.word)))" +definition update_Sstatus_UXL :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_UXL v x = ( + (v (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 33 :: int)::ii) (( 32 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" -fun get_Sstatus_MXR :: " Sstatus \<Rightarrow>(1)Word.word " where - " get_Sstatus_MXR (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))" +definition get_Sstatus_MXR :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_MXR v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))" definition set_Sstatus_MXR :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sstatus_MXR r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . - (let r = ((get_Sstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 19 :: int)::ii) (( 19 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 19 :: int)::ii) (( 19 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sstatus_MXR :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where - " update_Sstatus_MXR (Mk_Sstatus (v)) x = ( - Mk_Sstatus ((update_subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) x :: 64 Word.word)))" +definition update_Sstatus_MXR :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_MXR v x = ( + (v (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 19 :: int)::ii) (( 19 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sstatus_SUM :: " Sstatus \<Rightarrow>(1)Word.word " where - " get_Sstatus_SUM (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))" +definition get_Sstatus_SUM :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_SUM v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))" definition set_Sstatus_SUM :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sstatus_SUM r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . - (let r = ((get_Sstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 18 :: int)::ii) (( 18 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 18 :: int)::ii) (( 18 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sstatus_SUM :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where - " update_Sstatus_SUM (Mk_Sstatus (v)) x = ( - Mk_Sstatus ((update_subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) x :: 64 Word.word)))" +definition update_Sstatus_SUM :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_SUM v x = ( + (v (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 18 :: int)::ii) (( 18 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sstatus_XS :: " Sstatus \<Rightarrow>(2)Word.word " where - " get_Sstatus_XS (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word))" +definition get_Sstatus_XS :: " Sstatus \<Rightarrow>(2)Word.word " where + " get_Sstatus_XS v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word))" definition set_Sstatus_XS :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sstatus_XS r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . - (let r = ((get_Sstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 16 :: int)::ii) (( 15 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 16 :: int)::ii) (( 15 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sstatus_XS :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where - " update_Sstatus_XS (Mk_Sstatus (v)) x = ( - Mk_Sstatus ((update_subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) x :: 64 Word.word)))" +definition update_Sstatus_XS :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_XS v x = ( + (v (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 16 :: int)::ii) (( 15 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" -fun get_Sstatus_FS :: " Sstatus \<Rightarrow>(2)Word.word " where - " get_Sstatus_FS (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word))" +definition get_Sstatus_FS :: " Sstatus \<Rightarrow>(2)Word.word " where + " get_Sstatus_FS v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word))" definition set_Sstatus_FS :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sstatus_FS r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . - (let r = ((get_Sstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 14 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 14 :: int)::ii) (( 13 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sstatus_FS :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where - " update_Sstatus_FS (Mk_Sstatus (v)) x = ( - Mk_Sstatus ((update_subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" +definition update_Sstatus_FS :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_FS v x = ( + (v (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 14 :: int)::ii) (( 13 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" -fun get_Sstatus_SPP :: " Sstatus \<Rightarrow>(1)Word.word " where - " get_Sstatus_SPP (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" +definition get_Sstatus_SPP :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_SPP v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" definition set_Sstatus_SPP :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sstatus_SPP r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . - (let r = ((get_Sstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sstatus_SPP :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where - " update_Sstatus_SPP (Mk_Sstatus (v)) x = ( - Mk_Sstatus ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" +definition update_Sstatus_SPP :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_SPP v x = ( + (v (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sstatus_SPIE :: " Sstatus \<Rightarrow>(1)Word.word " where - " get_Sstatus_SPIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" +definition get_Sstatus_SPIE :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_SPIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" definition set_Sstatus_SPIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sstatus_SPIE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . - (let r = ((get_Sstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sstatus_SPIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where - " update_Sstatus_SPIE (Mk_Sstatus (v)) x = ( - Mk_Sstatus ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" +definition update_Sstatus_SPIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_SPIE v x = ( + (v (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sstatus_UPIE :: " Sstatus \<Rightarrow>(1)Word.word " where - " get_Sstatus_UPIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" +definition get_Sstatus_UPIE :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_UPIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" definition set_Sstatus_UPIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sstatus_UPIE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . - (let r = ((get_Sstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sstatus_UPIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where - " update_Sstatus_UPIE (Mk_Sstatus (v)) x = ( - Mk_Sstatus ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" +definition update_Sstatus_UPIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_UPIE v x = ( + (v (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sstatus_SIE :: " Sstatus \<Rightarrow>(1)Word.word " where - " get_Sstatus_SIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_Sstatus_SIE :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_SIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" definition set_Sstatus_SIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sstatus_SIE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . - (let r = ((get_Sstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sstatus_SIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where - " update_Sstatus_SIE (Mk_Sstatus (v)) x = ( - Mk_Sstatus ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" +definition update_Sstatus_SIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_SIE v x = ( + (v (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sstatus_UIE :: " Sstatus \<Rightarrow>(1)Word.word " where - " get_Sstatus_UIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_Sstatus_UIE :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_UIE v = ( (subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" definition set_Sstatus_UIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sstatus_UIE r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . - (let r = ((get_Sstatus w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sstatus r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sstatus_UIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where - " update_Sstatus_UIE (Mk_Sstatus (v)) x = ( - Mk_Sstatus ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_Sstatus_UIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_UIE v x = ( + (v (| + Sstatus_Sstatus_chunk_0 := + ((update_subrange_vec_dec(Sstatus_Sstatus_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val lower_mstatus : Mstatus -> Sstatus*) @@ -3446,7 +5483,6 @@ definition lower_mstatus :: " Mstatus \<Rightarrow> Sstatus " where definition lift_sstatus :: " Mstatus \<Rightarrow> Sstatus \<Rightarrow> Mstatus " where " lift_sstatus (m :: Mstatus) (s :: Sstatus) = ( (let m = (update_Mstatus_SD m ((get_Sstatus_SD s :: 1 Word.word))) in - (let m = (update_Mstatus_UXL m ((get_Sstatus_UXL s :: 2 Word.word))) in (let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s :: 1 Word.word))) in (let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s :: 1 Word.word))) in (let m = (update_Mstatus_XS m ((get_Sstatus_XS s :: 2 Word.word))) in @@ -3455,184 +5491,285 @@ definition lift_sstatus :: " Mstatus \<Rightarrow> Sstatus \<Rightarrow> Mstatu (let m = (update_Mstatus_SPIE m ((get_Sstatus_SPIE s :: 1 Word.word))) in (let m = (update_Mstatus_UPIE m ((get_Sstatus_UPIE s :: 1 Word.word))) in (let m = (update_Mstatus_SIE m ((get_Sstatus_SIE s :: 1 Word.word))) in - update_Mstatus_UIE m ((get_Sstatus_UIE s :: 1 Word.word)))))))))))))" + update_Mstatus_UIE m ((get_Sstatus_UIE s :: 1 Word.word))))))))))))" (*val legalize_sstatus : Mstatus -> mword ty64 -> Mstatus*) definition legalize_sstatus :: " Mstatus \<Rightarrow>(64)Word.word \<Rightarrow> Mstatus " where - " legalize_sstatus (m :: Mstatus) (v :: xlenbits) = ( lift_sstatus m (Mk_Sstatus v))" + " legalize_sstatus (m :: Mstatus) (v :: xlenbits) = ( lift_sstatus m ((Mk_Sstatus v)))" -(*val _get_Sedeleg : Sedeleg -> mword ty64*) +(*val Mk_Sedeleg : mword ty64 -> Sedeleg*) -fun get_Sedeleg :: " Sedeleg \<Rightarrow>(64)Word.word " where - " get_Sedeleg (Mk_Sedeleg (v)) = ( v )" +definition Mk_Sedeleg :: "(64)Word.word \<Rightarrow> Sedeleg " where + " Mk_Sedeleg v = ( + (| Sedeleg_Sedeleg_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -(*val _set_Sedeleg : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit*) +(*val _get_Sedeleg_bits : Sedeleg -> mword ty64*) -definition set_Sedeleg :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_Sedeleg r_ref v = ( +definition get_Sedeleg_bits :: " Sedeleg \<Rightarrow>(64)Word.word " where + " get_Sedeleg_bits v = ( (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" + + +(*val _set_Sedeleg_bits : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit*) + +definition set_Sedeleg_bits :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sedeleg_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_Sedeleg v) in + (let r = + ((r (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" -fun get_Sedeleg_UEnvCall :: " Sedeleg \<Rightarrow>(1)Word.word " where - " get_Sedeleg_UEnvCall (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" +(*val _update_Sedeleg_bits : Sedeleg -> mword ty64 -> Sedeleg*) + +definition update_Sedeleg_bits :: " Sedeleg \<Rightarrow>(64)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_bits v x = ( + (v (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + +definition get_Sedeleg_UEnvCall :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_UEnvCall v = ( + (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" definition set_Sedeleg_UEnvCall :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sedeleg_UEnvCall r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . - (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sedeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sedeleg_UEnvCall :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where - " update_Sedeleg_UEnvCall (Mk_Sedeleg (v)) x = ( - Mk_Sedeleg ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" +definition update_Sedeleg_UEnvCall :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_UEnvCall v x = ( + (v (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sedeleg_SAMO_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where - " get_Sedeleg_SAMO_Access_Fault (Mk_Sedeleg (v)) = ( - (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" +definition get_Sedeleg_SAMO_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_SAMO_Access_Fault v = ( + (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" definition set_Sedeleg_SAMO_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sedeleg_SAMO_Access_Fault r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . - (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sedeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sedeleg_SAMO_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where - " update_Sedeleg_SAMO_Access_Fault (Mk_Sedeleg (v)) x = ( - Mk_Sedeleg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" +definition update_Sedeleg_SAMO_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_SAMO_Access_Fault v x = ( + (v (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sedeleg_SAMO_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where - " get_Sedeleg_SAMO_Addr_Align (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" +definition get_Sedeleg_SAMO_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_SAMO_Addr_Align v = ( + (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" definition set_Sedeleg_SAMO_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sedeleg_SAMO_Addr_Align r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . - (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sedeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sedeleg_SAMO_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where - " update_Sedeleg_SAMO_Addr_Align (Mk_Sedeleg (v)) x = ( - Mk_Sedeleg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" +definition update_Sedeleg_SAMO_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_SAMO_Addr_Align v x = ( + (v (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sedeleg_Load_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where - " get_Sedeleg_Load_Access_Fault (Mk_Sedeleg (v)) = ( - (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" +definition get_Sedeleg_Load_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_Load_Access_Fault v = ( + (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" definition set_Sedeleg_Load_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sedeleg_Load_Access_Fault r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . - (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sedeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sedeleg_Load_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where - " update_Sedeleg_Load_Access_Fault (Mk_Sedeleg (v)) x = ( - Mk_Sedeleg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" +definition update_Sedeleg_Load_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_Load_Access_Fault v x = ( + (v (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sedeleg_Load_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where - " get_Sedeleg_Load_Addr_Align (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" +definition get_Sedeleg_Load_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_Load_Addr_Align v = ( + (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" definition set_Sedeleg_Load_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sedeleg_Load_Addr_Align r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . - (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sedeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sedeleg_Load_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where - " update_Sedeleg_Load_Addr_Align (Mk_Sedeleg (v)) x = ( - Mk_Sedeleg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" +definition update_Sedeleg_Load_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_Load_Addr_Align v x = ( + (v (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sedeleg_Breakpoint :: " Sedeleg \<Rightarrow>(1)Word.word " where - " get_Sedeleg_Breakpoint (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" +definition get_Sedeleg_Breakpoint :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_Breakpoint v = ( + (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" definition set_Sedeleg_Breakpoint :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sedeleg_Breakpoint r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . - (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sedeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sedeleg_Breakpoint :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where - " update_Sedeleg_Breakpoint (Mk_Sedeleg (v)) x = ( - Mk_Sedeleg ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" +definition update_Sedeleg_Breakpoint :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_Breakpoint v x = ( + (v (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sedeleg_Illegal_Instr :: " Sedeleg \<Rightarrow>(1)Word.word " where - " get_Sedeleg_Illegal_Instr (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" +definition get_Sedeleg_Illegal_Instr :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_Illegal_Instr v = ( + (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" definition set_Sedeleg_Illegal_Instr :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sedeleg_Illegal_Instr r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . - (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sedeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sedeleg_Illegal_Instr :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where - " update_Sedeleg_Illegal_Instr (Mk_Sedeleg (v)) x = ( - Mk_Sedeleg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" +definition update_Sedeleg_Illegal_Instr :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_Illegal_Instr v x = ( + (v (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sedeleg_Fetch_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where - " get_Sedeleg_Fetch_Access_Fault (Mk_Sedeleg (v)) = ( - (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_Sedeleg_Fetch_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_Fetch_Access_Fault v = ( + (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" definition set_Sedeleg_Fetch_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sedeleg_Fetch_Access_Fault r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . - (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sedeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sedeleg_Fetch_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where - " update_Sedeleg_Fetch_Access_Fault (Mk_Sedeleg (v)) x = ( - Mk_Sedeleg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" +definition update_Sedeleg_Fetch_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_Fetch_Access_Fault v x = ( + (v (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sedeleg_Fetch_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where - " get_Sedeleg_Fetch_Addr_Align (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_Sedeleg_Fetch_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_Fetch_Addr_Align v = ( + (subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" definition set_Sedeleg_Fetch_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sedeleg_Fetch_Addr_Align r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . - (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sedeleg r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sedeleg_Fetch_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where - " update_Sedeleg_Fetch_Addr_Align (Mk_Sedeleg (v)) x = ( - Mk_Sedeleg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_Sedeleg_Fetch_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_Fetch_Addr_Align v x = ( + (v (| + Sedeleg_Sedeleg_chunk_0 := + ((update_subrange_vec_dec(Sedeleg_Sedeleg_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val legalize_sedeleg : Sedeleg -> mword ty64 -> Sedeleg*) @@ -3642,121 +5779,199 @@ definition legalize_sedeleg :: " Sedeleg \<Rightarrow>(64)Word.word \<Rightarro Mk_Sedeleg ((EXTZ (( 64 :: int)::ii) ((subrange_vec_dec v (( 8 :: int)::ii) (( 0 :: int)::ii) :: 9 Word.word)) :: 64 Word.word)))" -(*val _get_Sinterrupts : Sinterrupts -> mword ty64*) +(*val Mk_Sinterrupts : mword ty64 -> Sinterrupts*) + +definition Mk_Sinterrupts :: "(64)Word.word \<Rightarrow> Sinterrupts " where + " Mk_Sinterrupts v = ( + (| Sinterrupts_Sinterrupts_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" + -fun get_Sinterrupts :: " Sinterrupts \<Rightarrow>(64)Word.word " where - " get_Sinterrupts (Mk_Sinterrupts (v)) = ( v )" +(*val _get_Sinterrupts_bits : Sinterrupts -> mword ty64*) +definition get_Sinterrupts_bits :: " Sinterrupts \<Rightarrow>(64)Word.word " where + " get_Sinterrupts_bits v = ( + (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_Sinterrupts : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit*) -definition set_Sinterrupts :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_Sinterrupts r_ref v = ( +(*val _set_Sinterrupts_bits : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit*) + +definition set_Sinterrupts_bits :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sinterrupts_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_Sinterrupts v) in + (let r = + ((r (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" -fun get_Sinterrupts_SEI :: " Sinterrupts \<Rightarrow>(1)Word.word " where - " get_Sinterrupts_SEI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" +(*val _update_Sinterrupts_bits : Sinterrupts -> mword ty64 -> Sinterrupts*) + +definition update_Sinterrupts_bits :: " Sinterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_bits v x = ( + (v (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + +definition get_Sinterrupts_SEI :: " Sinterrupts \<Rightarrow>(1)Word.word " where + " get_Sinterrupts_SEI v = ( + (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" definition set_Sinterrupts_SEI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sinterrupts_SEI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . - (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sinterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 9 :: int)::ii) (( 9 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sinterrupts_SEI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where - " update_Sinterrupts_SEI (Mk_Sinterrupts (v)) x = ( - Mk_Sinterrupts ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x :: 64 Word.word)))" +definition update_Sinterrupts_SEI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_SEI v x = ( + (v (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 9 :: int)::ii) (( 9 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sinterrupts_UEI :: " Sinterrupts \<Rightarrow>(1)Word.word " where - " get_Sinterrupts_UEI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" +definition get_Sinterrupts_UEI :: " Sinterrupts \<Rightarrow>(1)Word.word " where + " get_Sinterrupts_UEI v = ( + (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" definition set_Sinterrupts_UEI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sinterrupts_UEI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . - (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sinterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sinterrupts_UEI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where - " update_Sinterrupts_UEI (Mk_Sinterrupts (v)) x = ( - Mk_Sinterrupts ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" +definition update_Sinterrupts_UEI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_UEI v x = ( + (v (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 8 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sinterrupts_STI :: " Sinterrupts \<Rightarrow>(1)Word.word " where - " get_Sinterrupts_STI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" +definition get_Sinterrupts_STI :: " Sinterrupts \<Rightarrow>(1)Word.word " where + " get_Sinterrupts_STI v = ( + (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" definition set_Sinterrupts_STI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sinterrupts_STI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . - (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sinterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sinterrupts_STI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where - " update_Sinterrupts_STI (Mk_Sinterrupts (v)) x = ( - Mk_Sinterrupts ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" +definition update_Sinterrupts_STI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_STI v x = ( + (v (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sinterrupts_UTI :: " Sinterrupts \<Rightarrow>(1)Word.word " where - " get_Sinterrupts_UTI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" +definition get_Sinterrupts_UTI :: " Sinterrupts \<Rightarrow>(1)Word.word " where + " get_Sinterrupts_UTI v = ( + (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" definition set_Sinterrupts_UTI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sinterrupts_UTI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . - (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sinterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sinterrupts_UTI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where - " update_Sinterrupts_UTI (Mk_Sinterrupts (v)) x = ( - Mk_Sinterrupts ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" +definition update_Sinterrupts_UTI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_UTI v x = ( + (v (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sinterrupts_SSI :: " Sinterrupts \<Rightarrow>(1)Word.word " where - " get_Sinterrupts_SSI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_Sinterrupts_SSI :: " Sinterrupts \<Rightarrow>(1)Word.word " where + " get_Sinterrupts_SSI v = ( + (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" definition set_Sinterrupts_SSI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sinterrupts_SSI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . - (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sinterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sinterrupts_SSI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where - " update_Sinterrupts_SSI (Mk_Sinterrupts (v)) x = ( - Mk_Sinterrupts ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" +definition update_Sinterrupts_SSI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_SSI v x = ( + (v (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" -fun get_Sinterrupts_USI :: " Sinterrupts \<Rightarrow>(1)Word.word " where - " get_Sinterrupts_USI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_Sinterrupts_USI :: " Sinterrupts \<Rightarrow>(1)Word.word " where + " get_Sinterrupts_USI v = ( + (subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" definition set_Sinterrupts_USI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Sinterrupts_USI r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . - (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Sinterrupts r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Sinterrupts_USI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where - " update_Sinterrupts_USI (Mk_Sinterrupts (v)) x = ( - Mk_Sinterrupts ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_Sinterrupts_USI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_USI v x = ( + (v (| + Sinterrupts_Sinterrupts_chunk_0 := + ((update_subrange_vec_dec(Sinterrupts_Sinterrupts_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 64 Word.word))|)))" (*val lower_mip : Minterrupts -> Minterrupts -> Sinterrupts*) @@ -3843,7 +6058,7 @@ definition lift_sip :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Si definition legalize_sip :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts " where " legalize_sip (m :: Minterrupts) (d :: Minterrupts) (v :: xlenbits) = ( - lift_sip m d (Mk_Sinterrupts v))" + lift_sip m d ((Mk_Sinterrupts v)))" (*val lift_sie : Minterrupts -> Minterrupts -> Sinterrupts -> Minterrupts*) @@ -3880,85 +6095,131 @@ definition lift_sie :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Si definition legalize_sie :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts " where " legalize_sie (m :: Minterrupts) (d :: Minterrupts) (v :: xlenbits) = ( - lift_sie m d (Mk_Sinterrupts v))" + lift_sie m d ((Mk_Sinterrupts v)))" + + +(*val Mk_Satp64 : mword ty64 -> Satp64*) + +definition Mk_Satp64 :: "(64)Word.word \<Rightarrow> Satp64 " where + " Mk_Satp64 v = ( (| Satp64_Satp64_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -(*val _get_Satp64 : Satp64 -> mword ty64*) +(*val _get_Satp64_bits : Satp64 -> mword ty64*) -fun get_Satp64 :: " Satp64 \<Rightarrow>(64)Word.word " where - " get_Satp64 (Mk_Satp64 (v)) = ( v )" +definition get_Satp64_bits :: " Satp64 \<Rightarrow>(64)Word.word " where + " get_Satp64_bits v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" -(*val _set_Satp64 : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*) +(*val _set_Satp64_bits : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*) -definition set_Satp64 :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_Satp64 r_ref v = ( +definition set_Satp64_bits :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Satp64_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_Satp64 v) in + (let r = + ((r (| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" -fun get_Satp64_Mode :: " Satp64 \<Rightarrow>(4)Word.word " where - " get_Satp64_Mode (Mk_Satp64 (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 60 :: int)::ii) :: 4 Word.word))" +(*val _update_Satp64_bits : Satp64 -> mword ty64 -> Satp64*) + +definition update_Satp64_bits :: " Satp64 \<Rightarrow>(64)Word.word \<Rightarrow> Satp64 " where + " update_Satp64_bits v x = ( + (v (| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + +definition get_Satp64_Mode :: " Satp64 \<Rightarrow>(4)Word.word " where + " get_Satp64_Mode v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 63 :: int)::ii) (( 60 :: int)::ii) :: 4 Word.word))" definition set_Satp64_Mode :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Satp64_Mode r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Satp64) . - (let r = ((get_Satp64 w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 60 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Satp64 r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 r) (( 63 :: int)::ii) (( 60 :: int)::ii) + ((subrange_vec_dec v (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_Satp64_Mode :: " Satp64 \<Rightarrow>(4)Word.word \<Rightarrow> Satp64 " where - " update_Satp64_Mode (Mk_Satp64 (v)) x = ( - Mk_Satp64 ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 60 :: int)::ii) x :: 64 Word.word)))" +definition update_Satp64_Mode :: " Satp64 \<Rightarrow>(4)Word.word \<Rightarrow> Satp64 " where + " update_Satp64_Mode v x = ( + (v (| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 63 :: int)::ii) (( 60 :: int)::ii) + ((subrange_vec_dec x (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) + :: 64 Word.word))|)))" (*val _get_Satp64_Asid : Satp64 -> mword ty16*) -fun get_Satp64_Asid :: " Satp64 \<Rightarrow>(16)Word.word " where - " get_Satp64_Asid (Mk_Satp64 (v)) = ( (subrange_vec_dec v (( 59 :: int)::ii) (( 44 :: int)::ii) :: 16 Word.word))" +definition get_Satp64_Asid :: " Satp64 \<Rightarrow>(16)Word.word " where + " get_Satp64_Asid v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 59 :: int)::ii) (( 44 :: int)::ii) :: 16 Word.word))" (*val _set_Satp64_Asid : register_ref regstate register_value Satp64 -> mword ty16 -> M unit*) definition set_Satp64_Asid :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Satp64_Asid r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Satp64) . - (let r = ((get_Satp64 w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 59 :: int)::ii) (( 44 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Satp64 r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 r) (( 59 :: int)::ii) (( 44 :: int)::ii) + ((subrange_vec_dec v (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Satp64_Asid : Satp64 -> mword ty16 -> Satp64*) -fun update_Satp64_Asid :: " Satp64 \<Rightarrow>(16)Word.word \<Rightarrow> Satp64 " where - " update_Satp64_Asid (Mk_Satp64 (v)) x = ( - Mk_Satp64 ((update_subrange_vec_dec v (( 59 :: int)::ii) (( 44 :: int)::ii) x :: 64 Word.word)))" +definition update_Satp64_Asid :: " Satp64 \<Rightarrow>(16)Word.word \<Rightarrow> Satp64 " where + " update_Satp64_Asid v x = ( + (v (| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 59 :: int)::ii) (( 44 :: int)::ii) + ((subrange_vec_dec x (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 64 Word.word))|)))" (*val _get_Satp64_PPN : Satp64 -> mword ty44*) -fun get_Satp64_PPN :: " Satp64 \<Rightarrow>(44)Word.word " where - " get_Satp64_PPN (Mk_Satp64 (v)) = ( (subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))" +definition get_Satp64_PPN :: " Satp64 \<Rightarrow>(44)Word.word " where + " get_Satp64_PPN v = ( (subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))" (*val _set_Satp64_PPN : register_ref regstate register_value Satp64 -> mword ty44 -> M unit*) definition set_Satp64_PPN :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_Satp64_PPN r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: Satp64) . - (let r = ((get_Satp64 w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 43 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_Satp64 r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 r) (( 43 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_Satp64_PPN : Satp64 -> mword ty44 -> Satp64*) -fun update_Satp64_PPN :: " Satp64 \<Rightarrow>(44)Word.word \<Rightarrow> Satp64 " where - " update_Satp64_PPN (Mk_Satp64 (v)) x = ( - Mk_Satp64 ((update_subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_Satp64_PPN :: " Satp64 \<Rightarrow>(44)Word.word \<Rightarrow> Satp64 " where + " update_Satp64_PPN v x = ( + (v (| + Satp64_Satp64_chunk_0 := + ((update_subrange_vec_dec(Satp64_Satp64_chunk_0 v) (( 43 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word)) + :: 64 Word.word))|)))" (*val legalize_satp : Architecture -> mword ty64 -> mword ty64 -> mword ty64*) @@ -3969,7 +6230,7 @@ definition legalize_satp :: " Architecture \<Rightarrow>(64)Word.word \<Rightar (case ((satpMode_of_bits a ((get_Satp64_Mode s :: 4 Word.word)))) of None => o1 | Some (Sv32) => o1 - | Some (_) => (get_Satp64 s :: 64 Word.word) + | Some (_) => (get_Satp64_bits s :: 64 Word.word) )))" @@ -4058,6 +6319,10 @@ definition csr_name :: "(12)Word.word \<Rightarrow> string " where (''mtval'') else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then (''mip'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''pmpcfg0'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then + (''pmpaddr0'') else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then (''mcycle'') else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then @@ -4071,6 +6336,1874 @@ definition csr_name :: "(12)Word.word \<Rightarrow> string " where else (''UNKNOWN'')))" +(*val csr_name_map_forwards : mword ty12 -> string*) + +definition csr_name_map_forwards :: "(12)Word.word \<Rightarrow> string " where + " csr_name_map_forwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''ustatus'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''uie'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + (''utvec'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''uscratch'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''uepc'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''ucause'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''utval'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''uip'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''fflags'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''frm'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''fcsr'') + else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''cycle'') + else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''time'') + else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''instret'') + else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''cycleh'') + else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''timeh'') + else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''instreth'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''sstatus'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''sedeleg'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''sideleg'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''sie'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + (''stvec'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + (''scounteren'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''sscratch'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''sepc'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''scause'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''stval'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''sip'') + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''satp'') + else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then + (''mvendorid'') + else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then + (''marchid'') + else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then + (''mimpid'') + else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then + (''mhartid'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''mstatus'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''misa'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''medeleg'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''mideleg'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''mie'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + (''mtvec'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + (''mcounteren'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''mscratch'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''mepc'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''mcause'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''mtval'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''mip'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''pmpcfg0'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''pmpcfg1'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''pmpcfg2'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''pmpcfg3'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then + (''pmpaddr0'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)))) then + (''pmpaddr1'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)))) then + (''pmpaddr2'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)))) then + (''pmpaddr3'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)))) then + (''pmpaddr4'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)))) then + (''pmpaddr5'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)))) then + (''pmpaddr6'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)))) then + (''pmpaddr7'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)))) then + (''pmpaddr8'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)))) then + (''pmpaddr9'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)))) then + (''pmpaddr10'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)))) then + (''pmpaddr11'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)))) then + (''pmpaddr12'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)))) then + (''pmpaddr13'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)))) then + (''pmpaddr14'') + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)))) then + (''pmpaddr15'') + else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''mcycle'') + else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''minstret'') + else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''mcycleh'') + else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''minstreth'') + else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''tselect'') + else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''tdata1'') + else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''tdata2'') + else (''tdata3'')))" + + +(*val csr_name_map_backwards : string -> mword ty12*) + +definition csr_name_map_backwards :: " string \<Rightarrow>(12)Word.word " where + " csr_name_map_backwards arg0 = ( + if(arg0 = (''ustatus'')) then + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''uie'')) then + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''utvec'')) then + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)) + else + ( + if(arg0 = (''uscratch'')) then + ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''uepc'')) then + ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)) + else + ( + if(arg0 = (''ucause'')) then + ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''utval'')) then + ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)) + else + ( + if(arg0 = (''uip'')) then + ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''fflags'')) then + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)) + else + ( + if(arg0 = (''frm'')) then + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''fcsr'')) then + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)) + else + ( + if(arg0 = (''cycle'')) then + ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''time'')) then + ((vec_of_bits + [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)) + else + ( + if(arg0 = (''instret'')) then + ((vec_of_bits + [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''cycleh'')) then + ((vec_of_bits + [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''timeh'')) then + ((vec_of_bits + [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)) + else + ( + if(arg0 = (''instreth'')) then + ((vec_of_bits + [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''sstatus'')) then + ((vec_of_bits + [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''sedeleg'')) then + ((vec_of_bits + [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''sideleg'')) then + ((vec_of_bits + [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)) + else + ( + if(arg0 = (''sie'')) then + ((vec_of_bits + [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''stvec'')) then + ((vec_of_bits + [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)) + else + ( + if(arg0 = (''scounteren'')) then + ((vec_of_bits + [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''sscratch'')) then + ((vec_of_bits + [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''sepc'')) then + ((vec_of_bits + [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)) + else + ( + if(arg0 = (''scause'')) then + ((vec_of_bits + [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if(arg0 = (''stval'')) then + ((vec_of_bits + [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)) + else + ( + if(arg0 = (''sip'')) then + ((vec_of_bits + [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)) + else + ( + if(arg0 = + (''satp'')) then + ((vec_of_bits + [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if(arg0 = + (''mvendorid'')) then + ((vec_of_bits + [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)) + else + ( + if(arg0 = + (''marchid'')) then + ((vec_of_bits + [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if(arg0 = + (''mimpid'')) then + ((vec_of_bits + [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)) + else + ( + if( + arg0 = + (''mhartid'')) then + ( + ( + vec_of_bits + [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''mstatus'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''misa'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''medeleg'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''mideleg'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''mie'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''mtvec'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''mcounteren'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''mscratch'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''mepc'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''mcause'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''mtval'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''mip'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpcfg0'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpcfg1'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpcfg2'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpcfg3'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr0'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr1'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr2'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr3'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr4'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr5'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr6'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr7'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr8'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr9'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr10'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr11'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr12'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr13'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr14'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''pmpaddr15'')) then + ( + ( + vec_of_bits + [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''mcycle'')) then + ( + ( + vec_of_bits + [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''minstret'')) then + ( + ( + vec_of_bits + [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''mcycleh'')) then + ( + ( + vec_of_bits + [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''minstreth'')) then + ( + ( + vec_of_bits + [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''tselect'')) then + ( + ( + vec_of_bits + [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''tdata1'')) then + ( + ( + vec_of_bits + [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''tdata2'')) then + ( + ( + vec_of_bits + [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)) + else + ( + if + ( + arg0 = + (''tdata3'')) then + ( + ( + vec_of_bits + [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)) + else + undefined)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) )" + + +(*val csr_name_map_forwards_matches : mword ty12 -> bool*) + +definition csr_name_map_forwards_matches :: "(12)Word.word \<Rightarrow> bool " where + " csr_name_map_forwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + True + else if (((p00 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + True + else False))" + + +(*val csr_name_map_backwards_matches : string -> bool*) + +definition csr_name_map_backwards_matches :: " string \<Rightarrow> bool " where + " csr_name_map_backwards_matches arg0 = ( + if(arg0 = (''ustatus'')) then True else + ( + if(arg0 = (''uie'')) then True else + ( + if(arg0 = (''utvec'')) then True else + ( + if(arg0 = (''uscratch'')) then True else + ( + if(arg0 = (''uepc'')) then True else + ( + if(arg0 = (''ucause'')) then True else + ( + if(arg0 = (''utval'')) then True else + ( + if(arg0 = (''uip'')) then True else + ( + if(arg0 = (''fflags'')) then True else + ( + if(arg0 = (''frm'')) then True else + ( + if(arg0 = (''fcsr'')) then True else + ( + if(arg0 = (''cycle'')) then True else + ( + if(arg0 = (''time'')) then True else + ( + if(arg0 = (''instret'')) then True else + ( + if(arg0 = (''cycleh'')) then True else + ( + if(arg0 = (''timeh'')) then True else + ( + if(arg0 = (''instreth'')) then True else + ( + if(arg0 = (''sstatus'')) then True else + ( + if(arg0 = (''sedeleg'')) then True else + ( + if(arg0 = (''sideleg'')) then + True else + ( + if(arg0 = (''sie'')) then True else + ( + if(arg0 = (''stvec'')) then + True else + ( + if(arg0 = (''scounteren'')) then + True else + ( + if(arg0 = (''sscratch'')) then + True else + ( + if(arg0 = (''sepc'')) then + True else + ( + if(arg0 = (''scause'')) then + True else + ( + if(arg0 = (''stval'')) then + True else + ( + if(arg0 = (''sip'')) then + True else + ( + if(arg0 = + (''satp'')) then + True else + ( + if(arg0 = + (''mvendorid'')) then + True else + ( + if(arg0 = + (''marchid'')) then + True else + ( + if(arg0 = + (''mimpid'')) then + True else + ( + if( + arg0 = + (''mhartid'')) then + True else + ( + if + ( + arg0 = + (''mstatus'')) then + True else + ( + if + ( + arg0 = + (''misa'')) then + True else + ( + if + ( + arg0 = + (''medeleg'')) then + True else + ( + if + ( + arg0 = + (''mideleg'')) then + True else + ( + if + ( + arg0 = + (''mie'')) then + True else + ( + if + ( + arg0 = + (''mtvec'')) then + True else + ( + if + ( + arg0 = + (''mcounteren'')) then + True else + ( + if + ( + arg0 = + (''mscratch'')) then + True else + ( + if + ( + arg0 = + (''mepc'')) then + True else + ( + if + ( + arg0 = + (''mcause'')) then + True else + ( + if + ( + arg0 = + (''mtval'')) then + True else + ( + if + ( + arg0 = + (''mip'')) then + True else + ( + if + ( + arg0 = + (''pmpcfg0'')) then + True else + ( + if + ( + arg0 = + (''pmpcfg1'')) then + True else + ( + if + ( + arg0 = + (''pmpcfg2'')) then + True else + ( + if + ( + arg0 = + (''pmpcfg3'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr0'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr1'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr2'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr3'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr4'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr5'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr6'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr7'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr8'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr9'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr10'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr11'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr12'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr13'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr14'')) then + True else + ( + if + ( + arg0 = + (''pmpaddr15'')) then + True else + ( + if + ( + arg0 = + (''mcycle'')) then + True else + ( + if + ( + arg0 = + (''minstret'')) then + True else + ( + if + ( + arg0 = + (''mcycleh'')) then + True else + ( + if + ( + arg0 = + (''minstreth'')) then + True else + ( + if + ( + arg0 = + (''tselect'')) then + True else + ( + if + ( + arg0 = + (''tdata1'')) then + True else + ( + if + ( + arg0 = + (''tdata2'')) then + True else + ( + if + ( + arg0 = + (''tdata3'')) then + True else + False)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) )" + + +(*val csr_name_map_matches_prefix : string -> maybe ((mword ty12 * ii))*) + +definition csr_name_map_matches_prefix :: " string \<Rightarrow>((12)Word.word*int)option " where + " csr_name_map_matches_prefix arg0 = ( + (let stringappend_17160 = arg0 in + if (((((string_startswith stringappend_17160 (''ustatus''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''ustatus''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''ustatus''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''uie''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''uie''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''uie''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''utvec''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''utvec''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''utvec''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''uscratch''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''uscratch''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''uscratch''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''uepc''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''uepc''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''uepc''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''ucause''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''ucause''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''ucause''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''utval''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''utval''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''utval''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''uip''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''uip''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''uip''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''fflags''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''fflags''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''fflags''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''frm''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''frm''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''frm''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''fcsr''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''fcsr''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''fcsr''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''cycle''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''cycle''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''cycle''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''time''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''time''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''time''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''instret''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''instret''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''instret''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''cycleh''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''cycleh''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''cycleh''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''timeh''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''timeh''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''timeh''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''instreth''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''instreth''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''instreth''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''sstatus''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''sstatus''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''sstatus''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''sedeleg''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''sedeleg''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''sedeleg''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''sideleg''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''sideleg''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''sideleg''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''sie''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''sie''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''sie''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''stvec''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''stvec''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''stvec''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''scounteren''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''scounteren''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''scounteren''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''sscratch''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''sscratch''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''sscratch''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''sepc''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''sepc''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''sepc''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''scause''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''scause''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''scause''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''stval''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''stval''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''stval''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''sip''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''sip''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''sip''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''satp''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''satp''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''satp''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mvendorid''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mvendorid''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mvendorid''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''marchid''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''marchid''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''marchid''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mimpid''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mimpid''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mimpid''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mhartid''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mhartid''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mhartid''))))) of + s0 => + Some ((vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mstatus''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mstatus''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mstatus''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''misa''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''misa''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''misa''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''medeleg''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''medeleg''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''medeleg''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mideleg''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mideleg''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mideleg''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mie''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mie''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mie''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mtvec''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mtvec''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mtvec''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mcounteren''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mcounteren''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mcounteren''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mscratch''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mscratch''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mscratch''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mepc''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mepc''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mepc''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mcause''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mcause''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mcause''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mtval''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mtval''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mtval''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mip''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mip''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mip''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpcfg0''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpcfg0''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpcfg0''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpcfg1''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpcfg1''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpcfg1''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpcfg2''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpcfg2''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpcfg2''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpcfg3''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpcfg3''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpcfg3''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr0''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr0''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr0''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr1''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr1''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr1''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr2''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr2''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr2''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr3''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr3''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr3''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr4''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr4''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr4''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr5''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr5''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr5''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr6''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr6''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr6''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr7''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr7''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr7''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B1,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr8''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr8''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr8''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr9''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr9''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr9''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr10''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr10''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr10''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr11''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr11''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr11''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B0,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr12''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr12''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr12''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr13''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr13''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr13''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr14''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr14''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr14''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''pmpaddr15''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr15''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''pmpaddr15''))))) of + s0 => + Some ((vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mcycle''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mcycle''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mcycle''))))) of + s0 => + Some ((vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''minstret''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''minstret''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''minstret''))))) of + s0 => + Some ((vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''mcycleh''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''mcycleh''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''mcycleh''))))) of + s0 => + Some ((vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''minstreth''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''minstreth''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''minstreth''))))) of + s0 => + Some ((vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''tselect''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''tselect''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''tselect''))))) of + s0 => + Some ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''tdata1''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''tdata1''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''tdata1''))))) of + s0 => + Some ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''tdata2''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''tdata2''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''tdata2''))))) of + s0 => + Some ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B0] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17160 (''tdata3''))) \<and> ( + (case ((string_drop stringappend_17160 ((string_length (''tdata3''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17160 ((string_length (''tdata3''))))) of + s0 => + Some ((vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B1,B1] :: 12 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + (*val csrAccess : mword ty12 -> mword ty2*) definition csrAccess :: "(12)Word.word \<Rightarrow>(2)Word.word " where @@ -4120,6 +8253,10 @@ definition is_CSR_defined :: "(12)Word.word \<Rightarrow> Privilege \<Rightarro (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then + False else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then @@ -4170,6 +8307,58 @@ definition check_TVM_SATP :: "(12)Word.word \<Rightarrow> Privilege \<Rightarro return ((\<not> w__2))))" +(*val check_Counteren : mword ty12 -> Privilege -> M bool*) + +definition check_Counteren :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad " where + " check_Counteren (csr :: csreg) (p :: Privilege) = ( + (case (csr, p) of + (b__0, Supervisor) => + if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + read_reg mcounteren_ref \<bind> (\<lambda> (w__0 :: Counteren) . + return (((((get_Counteren_CY w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + read_reg mcounteren_ref \<bind> (\<lambda> (w__1 :: Counteren) . + return (((((get_Counteren_TM w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg mcounteren_ref \<bind> (\<lambda> (w__2 :: Counteren) . + return (((((get_Counteren_IR w__2 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))) + else + return ((case (b__0, Supervisor) of + (g__31, g__32) => + if (((((zopz0zIzJ_u (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word) + csr)) \<and> ((zopz0zIzJ_u csr + (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1] :: 12 Word.word)))))) then + False + else True + )) + | (b__3, User) => + if (((b__3 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + read_reg scounteren_ref \<bind> (\<lambda> (w__6 :: Counteren) . + return (((((get_Counteren_CY w__6 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))) + else if (((b__3 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + read_reg scounteren_ref \<bind> (\<lambda> (w__7 :: Counteren) . + return (((((get_Counteren_TM w__7 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))) + else if (((b__3 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg scounteren_ref \<bind> (\<lambda> (w__8 :: Counteren) . + return (((((get_Counteren_IR w__8 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))) + else + return ((case (b__3, User) of + (g__31, g__32) => + if (((((zopz0zIzJ_u (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word) + csr)) \<and> ((zopz0zIzJ_u csr + (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1] :: 12 Word.word)))))) then + False + else True + )) + | (g__31, g__32) => + return (if (((((zopz0zIzJ_u (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word) + csr)) \<and> ((zopz0zIzJ_u csr + (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1] :: 12 Word.word)))))) then + False + else True) + ))" + + (*val check_CSR : mword ty12 -> Privilege -> bool -> M bool*) definition check_CSR :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where @@ -4177,7 +8366,7 @@ definition check_CSR :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow> bo and_boolM (return ((is_CSR_defined csr p))) (and_boolM (return ((check_CSR_access ((csrAccess csr :: 2 Word.word)) ((csrPriv csr :: 2 Word.word)) p - isWrite))) ((check_TVM_SATP csr p))))" + isWrite))) (and_boolM ((check_TVM_SATP csr p)) ((check_Counteren csr p)))))" (*val exception_delegatee : ExceptionType -> Privilege -> M Privilege*) @@ -4186,9 +8375,9 @@ definition exception_delegatee :: " ExceptionType \<Rightarrow> Privilege \<Rig " exception_delegatee (e :: ExceptionType) (p :: Privilege) = ( (let idx = (num_of_ExceptionType e) in read_reg medeleg_ref \<bind> (\<lambda> (w__0 :: Medeleg) . - (let super = (access_vec_dec ((get_Medeleg w__0 :: 64 Word.word)) idx) in + (let super = (access_vec_dec ((get_Medeleg_bits w__0 :: 64 Word.word)) idx) in read_reg sedeleg_ref \<bind> (\<lambda> (w__1 :: Sedeleg) . - (let user = (access_vec_dec ((get_Sedeleg w__1 :: 64 Word.word)) idx) in + (let user = (access_vec_dec ((get_Sedeleg_bits w__1 :: 64 Word.word)) idx) in and_boolM (read_reg misa_ref \<bind> (\<lambda> (w__2 :: Misa) . return (((((get_Misa_S w__2 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) @@ -4234,51 +8423,98 @@ definition findPendingInterrupt :: "(64)Word.word \<Rightarrow>(InterruptType)o else None))" -(*val curInterrupt : Minterrupts -> Minterrupts -> Minterrupts -> M (maybe ((InterruptType * Privilege)))*) +(*val curInterrupt : Privilege -> Minterrupts -> Minterrupts -> Minterrupts -> M (maybe ((InterruptType * Privilege)))*) -definition curInterrupt :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>((register_value),((InterruptType*Privilege)option),(exception))monad " where - " curInterrupt (pend :: Minterrupts) (enbl :: Minterrupts) (delg :: Minterrupts) = ( +definition curInterrupt :: " Privilege \<Rightarrow> Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>((register_value),((InterruptType*Privilege)option),(exception))monad " where + " curInterrupt (priv :: Privilege) (pend :: Minterrupts) (enbl :: Minterrupts) (delg :: Minterrupts) = ( (let (en_mip :: xlenbits) = - ((and_vec ((get_Minterrupts pend :: 64 Word.word)) ((get_Minterrupts enbl :: 64 Word.word)) + ((and_vec ((get_Minterrupts_bits pend :: 64 Word.word)) + ((get_Minterrupts_bits enbl :: 64 Word.word)) :: 64 Word.word)) in if (((en_mip = ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))))) then return None else + or_boolM + (return (((((privLevel_to_bits priv :: 2 Word.word)) \<noteq> ((privLevel_to_bits Machine :: 2 Word.word)))))) + (and_boolM + (return (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word)))))) + (read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + return (((((get_Mstatus_MIE w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))) \<bind> (\<lambda> eff_mie . + or_boolM + (return (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word)))))) + (and_boolM + (return (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + (read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . + return (((((get_Mstatus_SIE w__2 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))) \<bind> (\<lambda> eff_sie . (let eff_mip = - ((and_vec en_mip ((not_vec ((get_Minterrupts delg :: 64 Word.word)) :: 64 Word.word)) + ((and_vec en_mip ((not_vec ((get_Minterrupts_bits delg :: 64 Word.word)) :: 64 Word.word)) :: 64 Word.word)) in - (let eff_sip = ((and_vec en_mip ((get_Minterrupts delg :: 64 Word.word)) :: 64 Word.word)) in - and_boolM - (read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) . - return (((((get_Mstatus_MIE w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) - (return (((eff_mip \<noteq> ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))) \<bind> (\<lambda> (w__1 :: - bool) . - if w__1 then - return ((case ((findPendingInterrupt eff_mip)) of + (let eff_sip = ((and_vec en_mip ((get_Minterrupts_bits delg :: 64 Word.word)) :: 64 Word.word)) in + if (((eff_mie \<and> (((eff_mip \<noteq> ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))))) then + (case ((findPendingInterrupt eff_mip)) of Some (i) => (let r = (i, Machine) in - Some r) - | None => None - )) + return (Some r)) + | None => + internal_error + (((op@) (''non-zero eff_mip='') + (((op@) ((string_of_bits eff_mip)) ('', but nothing pending''))))) + ) + else if (((eff_sie \<and> (((eff_sip \<noteq> ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))))) + then + (case ((findPendingInterrupt eff_sip)) of + Some (i) => + (let r = (i, Supervisor) in + return (Some r)) + | None => + internal_error + (((op@) (''non-zero eff_sip='') + (((op@) ((string_of_bits eff_sip)) ('', but nothing pending''))))) + ) else - and_boolM - (read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . - return (((((get_Mstatus_SIE w__2 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) - (and_boolM - (return (((eff_sip \<noteq> ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))) - (or_boolM - (read_reg cur_privilege_ref \<bind> (\<lambda> (w__3 :: Privilege) . - return (((((privLevel_to_bits w__3 :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word))))))) - (read_reg cur_privilege_ref \<bind> (\<lambda> (w__4 :: Privilege) . - return (((((privLevel_to_bits w__4 :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))))))) \<bind> (\<lambda> (w__7 :: bool) . - return (if w__7 then - (case ((findPendingInterrupt eff_sip)) of - Some (i) => - (let r = (i, Supervisor) in - Some r) - | None => None - ) - else None)))))))" + (let p = + (if (((((get_Minterrupts_MTI pend :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + (''1'') + else (''0'')) in + (let e = + (if (((((get_Minterrupts_MTI enbl :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + (''1'') + else (''0'')) in + (let d = + (if (((((get_Minterrupts_MTI delg :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + (''1'') + else (''0'')) in + (let (_ :: unit) = + (print_endline + (((op@) ('' MTI: pend='') + (((op@) p + (((op@) ('' enbl='') (((op@) e (((op@) ('' delg='') d))))))))))) in + (let eff_mip = + ((and_vec en_mip ((not_vec ((get_Minterrupts_bits delg :: 64 Word.word)) :: 64 Word.word)) + :: 64 Word.word)) in + (let eff_sip = ((and_vec en_mip ((get_Minterrupts_bits delg :: 64 Word.word)) :: 64 Word.word)) in + read_reg mstatus_ref \<bind> (\<lambda> (w__8 :: Mstatus) . + read_reg mstatus_ref \<bind> (\<lambda> (w__9 :: Mstatus) . + read_reg mstatus_ref \<bind> (\<lambda> (w__10 :: Mstatus) . + (let (_ :: unit) = + (print_endline + (((op@) (''mstatus='') + (((op@) ((string_of_bits ((get_Mstatus_bits w__8 :: 64 Word.word)))) + (((op@) ('' mie,sie='') + (((op@) ((string_of_bits ((get_Mstatus_MIE w__9 :: 1 Word.word)))) + (((op@) ('','') + (((op@) + ((string_of_bits ((get_Mstatus_SIE w__10 :: 1 Word.word)))) + (((op@) ('' en_mip='') + (((op@) ((string_of_bits en_mip)) + (((op@) ('' eff_mip='') + (((op@) ((string_of_bits eff_mip)) + (((op@) ('' eff_sip='') + ((string_of_bits eff_sip))))))))))))))))))))))))) in + return None))))))))))))))))" (*val tval : maybe (mword ty64) -> mword ty64*) @@ -4294,14 +8530,14 @@ definition handle_trap :: " Privilege \<Rightarrow> bool \<Rightarrow>(4)Word.w " handle_trap (del_priv :: Privilege) (intr :: bool) (c :: exc_code) (pc :: xlenbits) (info :: xlenbits option) = ( (let (_ :: unit) = - (prerr_endline + (print_endline (((op@) (''handling '') (((op@) (if intr then (''int#'') else (''exc#'')) - (((op@) ((string_of_vec c)) + (((op@) ((string_of_bits c)) (((op@) ('' at priv '') (((op@) ((privLevel_to_str del_priv)) (((op@) ('' with tval '') - ((string_of_vec ((tval info :: 64 Word.word))))))))))))))))) in + ((string_of_bits ((tval info :: 64 Word.word))))))))))))))))) in (case del_priv of Machine => ((set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr :: 1 Word.word)) \<then> @@ -4314,34 +8550,53 @@ definition handle_trap :: " Privilege \<Rightarrow> bool \<Rightarrow>(4)Word.w write_reg mtval_ref ((tval info :: 64 Word.word))) \<then> write_reg mepc_ref pc) \<then> write_reg cur_privilege_ref del_priv) \<then> - read_reg mtvec_ref) \<bind> (\<lambda> (w__2 :: Mtvec) . - read_reg mcause_ref \<bind> (\<lambda> (w__3 :: Mcause) . - (case ((tvec_addr w__2 w__3 :: ( 64 Word.word)option)) of + read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) . + read_reg mstatus_ref \<bind> (\<lambda> (w__3 :: Mstatus) . + (let (_ :: unit) = + (print_endline + (((op@) (''CSR mstatus <- '') + (((op@) ((string_of_bits ((get_Mstatus_bits w__2 :: 64 Word.word)))) + (((op@) ('' (input: '') + (((op@) ((string_of_bits ((get_Mstatus_bits w__3 :: 64 Word.word)))) ('')'')))))))))) in + (let (_ :: unit) = (cancel_reservation () ) in + read_reg mtvec_ref \<bind> (\<lambda> (w__4 :: Mtvec) . + read_reg mcause_ref \<bind> (\<lambda> (w__5 :: Mcause) . + (case ((tvec_addr w__4 w__5 :: ( 64 Word.word)option)) of Some (epc) => return epc | None => (internal_error (''Invalid mtvec mode'') :: ( 64 Word.word) M) - ))))) + ))))))))) | Supervisor => ((set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr :: 1 Word.word)) \<then> set_Mcause_Cause scause_ref ((EXTZ (( 63 :: int)::ii) c :: 63 Word.word))) \<then> - read_reg mstatus_ref) \<bind> (\<lambda> (w__6 :: Mstatus) . - ((set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6 :: 1 Word.word)) \<then> + read_reg mstatus_ref) \<bind> (\<lambda> (w__8 :: Mstatus) . + ((set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__8 :: 1 Word.word)) \<then> set_Mstatus_SIE mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then> - read_reg cur_privilege_ref) \<bind> (\<lambda> (w__7 :: Privilege) . - (case w__7 of + read_reg cur_privilege_ref) \<bind> (\<lambda> (w__9 :: Privilege) . + (case w__9 of User => return ((bool_to_bits False :: 1 Word.word)) | Supervisor => return ((bool_to_bits True :: 1 Word.word)) | Machine => (internal_error (''invalid privilege for s-mode trap'') :: ( 1 Word.word) M) - ) \<bind> (\<lambda> (w__9 :: 1 Word.word) . - ((((set_Mstatus_SPP mstatus_ref w__9 \<then> + ) \<bind> (\<lambda> (w__11 :: 1 Word.word) . + ((((set_Mstatus_SPP mstatus_ref w__11 \<then> write_reg stval_ref ((tval info :: 64 Word.word))) \<then> write_reg sepc_ref pc) \<then> write_reg cur_privilege_ref del_priv) \<then> - read_reg stvec_ref) \<bind> (\<lambda> (w__10 :: Mtvec) . - read_reg scause_ref \<bind> (\<lambda> (w__11 :: Mcause) . - (case ((tvec_addr w__10 w__11 :: ( 64 Word.word)option)) of + read_reg mstatus_ref) \<bind> (\<lambda> (w__12 :: Mstatus) . + read_reg mstatus_ref \<bind> (\<lambda> (w__13 :: Mstatus) . + (let (_ :: unit) = + (print_endline + (((op@) (''CSR mstatus <- '') + (((op@) ((string_of_bits ((get_Mstatus_bits w__12 :: 64 Word.word)))) + (((op@) ('' (input: '') + (((op@) ((string_of_bits ((get_Mstatus_bits w__13 :: 64 Word.word)))) + ('')'')))))))))) in + (let (_ :: unit) = (cancel_reservation () ) in + read_reg stvec_ref \<bind> (\<lambda> (w__14 :: Mtvec) . + read_reg scause_ref \<bind> (\<lambda> (w__15 :: Mcause) . + (case ((tvec_addr w__14 w__15 :: ( 64 Word.word)option)) of Some (epc) => return epc | None => (internal_error (''Invalid stvec mode'') :: ( 64 Word.word) M) - )))))) + )))))))))) | User => (internal_error (''the N extension is currently unsupported'') :: ( 64 Word.word) M) )))" @@ -4354,7 +8609,7 @@ definition handle_exception :: " Privilege \<Rightarrow> ctl_result \<Rightarro (_, CTL_TRAP (e)) => exception_delegatee(sync_exception_trap e) cur_priv \<bind> (\<lambda> del_priv . (let (_ :: unit) = - (prerr_endline + (print_endline (((op@) (''trapping from '') (((op@) ((privLevel_to_str cur_priv)) (((op@) ('' to '') @@ -4372,33 +8627,56 @@ definition handle_exception :: " Privilege \<Rightarrow> ctl_result \<Rightarro read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) . ((write_reg cur_privilege_ref ((privLevel_of_bits ((get_Mstatus_MPP w__2 :: 2 Word.word)))) \<then> set_Mstatus_MPP mstatus_ref ((privLevel_to_bits User :: 2 Word.word))) \<then> - read_reg cur_privilege_ref) \<bind> (\<lambda> (w__3 :: Privilege) . + read_reg mstatus_ref) \<bind> (\<lambda> (w__3 :: Mstatus) . + read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) . (let (_ :: unit) = - (prerr_endline + (print_endline + (((op@) (''CSR mstatus <- '') + (((op@) ((string_of_bits ((get_Mstatus_bits w__3 :: 64 Word.word)))) + (((op@) ('' (input: '') + (((op@) ((string_of_bits ((get_Mstatus_bits w__4 :: 64 Word.word)))) ('')'')))))))))) in + read_reg cur_privilege_ref \<bind> (\<lambda> (w__5 :: Privilege) . + (let (_ :: unit) = + (print_endline (((op@) (''ret-ing from '') (((op@) ((privLevel_to_str prev_priv)) - (((op@) ('' to '') ((privLevel_to_str w__3))))))))) in - (read_reg mepc_ref :: ( 64 Word.word) M)))))) + (((op@) ('' to '') ((privLevel_to_str w__5))))))))) in + (let (_ :: unit) = (cancel_reservation () ) in + (read_reg mepc_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 Word.word) . + (pc_alignment_mask () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 Word.word) . + return ((and_vec w__6 w__7 :: 64 Word.word))))))))))))) | (_, CTL_SRET (_)) => read_reg cur_privilege_ref \<bind> (\<lambda> prev_priv . - read_reg mstatus_ref \<bind> (\<lambda> (w__5 :: Mstatus) . - ((set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__5 :: 1 Word.word)) \<then> + read_reg mstatus_ref \<bind> (\<lambda> (w__8 :: Mstatus) . + ((set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__8 :: 1 Word.word)) \<then> set_Mstatus_SPIE mstatus_ref ((bool_to_bits True :: 1 Word.word))) \<then> - read_reg mstatus_ref) \<bind> (\<lambda> (w__6 :: Mstatus) . + read_reg mstatus_ref) \<bind> (\<lambda> (w__9 :: Mstatus) . ((write_reg cur_privilege_ref - (if (((((get_Mstatus_SPP w__6 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + (if (((((get_Mstatus_SPP w__9 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then Supervisor else User) \<then> set_Mstatus_SPP mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then> - read_reg cur_privilege_ref) \<bind> (\<lambda> (w__7 :: Privilege) . + read_reg mstatus_ref) \<bind> (\<lambda> (w__10 :: Mstatus) . + read_reg mstatus_ref \<bind> (\<lambda> (w__11 :: Mstatus) . + (let (_ :: unit) = + (print_endline + (((op@) (''CSR mstatus <- '') + (((op@) ((string_of_bits ((get_Mstatus_bits w__10 :: 64 Word.word)))) + (((op@) ('' (input: '') + (((op@) ((string_of_bits ((get_Mstatus_bits w__11 :: 64 Word.word)))) + ('')'')))))))))) in + read_reg cur_privilege_ref \<bind> (\<lambda> (w__12 :: Privilege) . (let (_ :: unit) = - (prerr_endline + (print_endline (((op@) (''ret-ing from '') (((op@) ((privLevel_to_str prev_priv)) - (((op@) ('' to '') ((privLevel_to_str w__7))))))))) in - (read_reg sepc_ref :: ( 64 Word.word) M)))))) + (((op@) ('' to '') ((privLevel_to_str w__12))))))))) in + (let (_ :: unit) = (cancel_reservation () ) in + (read_reg sepc_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 Word.word) . + (pc_alignment_mask () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64 Word.word) . + return ((and_vec w__13 w__14 :: 64 Word.word))))))))))))) ))" @@ -4453,17 +8731,211 @@ definition handle_illegal :: " unit \<Rightarrow>((register_value),(unit),(exce definition init_sys :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " init_sys _ = ( - (((((write_reg cur_privilege_ref Machine \<then> + (((((((((write_reg cur_privilege_ref Machine \<then> + write_reg mhartid_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> set_Misa_MXL misa_ref ((arch_to_bits RV64 :: 2 Word.word))) \<then> + set_Misa_A misa_ref ((bool_to_bits True :: 1 Word.word))) \<then> set_Misa_C misa_ref ((bool_to_bits True :: 1 Word.word))) \<then> + set_Misa_I misa_ref ((bool_to_bits True :: 1 Word.word))) \<then> + set_Misa_M misa_ref ((bool_to_bits True :: 1 Word.word))) \<then> set_Misa_U misa_ref ((bool_to_bits True :: 1 Word.word))) \<then> set_Misa_S misa_ref ((bool_to_bits True :: 1 Word.word))) \<then> read_reg misa_ref) \<bind> (\<lambda> (w__0 :: Misa) . (set_Mstatus_SXL mstatus_ref ((get_Misa_MXL w__0 :: 2 Word.word)) \<then> read_reg misa_ref) \<bind> (\<lambda> (w__1 :: Misa) . - (set_Mstatus_UXL mstatus_ref ((get_Misa_MXL w__1 :: 2 Word.word)) \<then> + ((((((((((((((((set_Mstatus_UXL mstatus_ref ((get_Misa_MXL w__1 :: 2 Word.word)) \<then> set_Mstatus_SD mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then> - write_reg mhartid_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))" + set_Minterrupts_bits mip_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> + set_Minterrupts_bits mie_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> + set_Minterrupts_bits mideleg_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> + set_Medeleg_bits medeleg_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> + set_Mtvec_bits mtvec_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> + set_Mcause_bits mcause_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> + write_reg mepc_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> + write_reg mtval_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> + write_reg mscratch_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> + write_reg mcycle_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> + write_reg mtime_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> + set_Counteren_bits mcounteren_ref ((EXTZ (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) \<then> + write_reg minstret_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) \<then> + write_reg minstret_written_ref False) \<then> + read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) . + return ((print_endline + (((op@) (''CSR mstatus <- '') + (((op@) ((string_of_bits ((get_Mstatus_bits w__2 :: 64 Word.word)))) + (((op@) ('' (input: '') + (((op@) + ((string_of_bits + ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))) + ('')'')))))))))))))))" + + +(*val phys_mem_segments : unit -> list ((mword ty64 * mword ty64))*) + +definition phys_mem_segments :: " unit \<Rightarrow>((64)Word.word*(64)Word.word)list " where + " phys_mem_segments _ = ( + ((plat_rom_base () :: 64 Word.word), (plat_rom_size () :: 64 Word.word)) # + (((plat_ram_base () :: 64 Word.word), (plat_ram_size () :: 64 Word.word)) # []))" + + +(*val within_phys_mem : mword ty64 -> integer -> bool*) + +definition within_phys_mem :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where + " within_phys_mem (addr :: xlenbits) (width :: int) = ( + if (((((zopz0zIzJ_u ((plat_ram_base () :: 64 Word.word)) addr)) \<and> ((zopz0zIzJ_u ((add_vec_int addr width :: 64 Word.word)) + ((add_vec ((plat_ram_base () :: 64 Word.word)) ((plat_ram_size () :: 64 Word.word)) + :: 64 Word.word))))))) then + True + else if (((((zopz0zIzJ_u ((plat_rom_base () :: 64 Word.word)) addr)) \<and> ((zopz0zIzJ_u ((add_vec_int addr width :: 64 Word.word)) + ((add_vec ((plat_rom_base () :: 64 Word.word)) ((plat_rom_size () :: 64 Word.word)) + :: 64 Word.word))))))) then + True + else False )" + + +(*val within_clint : mword ty64 -> integer -> bool*) + +definition within_clint :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where + " within_clint (addr :: xlenbits) (width :: int) = ( + (((zopz0zIzJ_u ((plat_clint_base () :: 64 Word.word)) addr)) \<and> ((zopz0zIzJ_u ((add_vec_int addr width :: 64 Word.word)) + ((add_vec ((plat_clint_base () :: 64 Word.word)) ((plat_clint_size () :: 64 Word.word)) + :: 64 Word.word))))))" + + +(*val within_htif_writable : mword ty64 -> integer -> bool*) + +definition within_htif_writable :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where + " within_htif_writable (addr :: xlenbits) (width :: int) = ( + (((plat_htif_tohost () :: 64 Word.word)) = addr))" + + +(*val within_htif_readable : mword ty64 -> integer -> bool*) + +definition within_htif_readable :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where + " within_htif_readable (addr :: xlenbits) (width :: int) = ( + (((plat_htif_tohost () :: 64 Word.word)) = addr))" + + +definition MSIP_BASE :: "(64)Word.word " where + " MSIP_BASE = ( + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word))" + + +definition MTIMECMP_BASE :: "(64)Word.word " where + " MTIMECMP_BASE = ( + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word))" + + +definition MTIME_BASE :: "(64)Word.word " where + " MTIME_BASE = ( + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B0,B0,B0] + :: 64 Word.word))" + + +(*val clint_load : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition clint_load :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " clint_load addr width = ( + (let addr = ((sub_vec addr ((plat_clint_base () :: 64 Word.word)) :: 64 Word.word)) in + if ((((((addr = MSIP_BASE))) \<and> ((((((width = (( 8 :: int)::ii)))) \<or> (((width = (( 4 :: int)::ii)))))))))) + then + read_reg mip_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . + (let (_ :: unit) = + (print_endline + (((op@) (''clint['') + (((op@) ((string_of_bits addr)) + (((op@) (''] -> '') + ((string_of_bits ((get_Minterrupts_MSI w__0 :: 1 Word.word))))))))))) in + read_reg mip_ref \<bind> (\<lambda> (w__1 :: Minterrupts) . + return (MemValue ((zero_extend ((get_Minterrupts_MSI w__1 :: 1 Word.word)) + (((( 8 :: int)::ii) * width)) + :: ( 'int8_times_n::len)Word.word)))))) + else if ((((((addr = MTIMECMP_BASE))) \<and> (((width = (( 8 :: int)::ii))))))) then + (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: xlenbits) . + (let (_ :: unit) = + (print_endline + (((op@) (''clint['') + (((op@) ((string_of_bits addr)) (((op@) (''] -> '') ((string_of_bits w__2))))))))) in + (read_reg mtimecmp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . + return (MemValue ((zero_extend w__3 (( 64 :: int)::ii) :: ( 'int8_times_n::len)Word.word)))))) + else if ((((((addr = MTIME_BASE))) \<and> (((width = (( 8 :: int)::ii))))))) then + (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: xlenbits) . + (let (_ :: unit) = + (print_endline + (((op@) (''clint['') + (((op@) ((string_of_bits addr)) (((op@) (''] -> '') ((string_of_bits w__4))))))))) in + (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: xlenbits) . + return (MemValue ((zero_extend w__5 (( 64 :: int)::ii) :: ( 'int8_times_n::len)Word.word)))))) + else + (let (_ :: unit) = + (print_endline + (((op@) (''clint['') (((op@) ((string_of_bits addr)) (''] -> <not-mapped>'')))))) in + return (MemException E_Load_Access_Fault))))" + + +(*val clint_dispatch : unit -> M unit*) + +definition clint_dispatch :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " clint_dispatch _ = ( + (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: xlenbits) . + (let (_ :: unit) = (print_endline (((op@) (''clint::tick mtime <- '') ((string_of_bits w__0))))) in + (set_Minterrupts_MTI mip_ref ((bool_to_bits False :: 1 Word.word)) \<then> + (read_reg mtimecmp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: xlenbits) . + (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + if ((zopz0zIzJ_u w__1 w__2)) then + (read_reg mtime_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . + (let (_ :: unit) = + (print_endline (((op@) ('' clint timer pending at mtime '') ((string_of_bits w__3))))) in + set_Minterrupts_MTI mip_ref ((bool_to_bits True :: 1 Word.word)))) + else return () )))))" + + +(*val clint_store : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +definition clint_store :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " clint_store addr width data = ( + (let addr = ((sub_vec addr ((plat_clint_base () :: 64 Word.word)) :: 64 Word.word)) in + if ((((((addr = MSIP_BASE))) \<and> ((((((width = (( 8 :: int)::ii)))) \<or> (((width = (( 4 :: int)::ii)))))))))) + then + (let (_ :: unit) = + (print_endline + (((op@) (''clint['') + (((op@) ((string_of_bits addr)) + (((op@) (''] <- '') + (((op@) ((string_of_bits data)) + (((op@) ('' (mip.MSI <- '') + (((op@) + ((string_of_bits + ((cast_unit_vec0 ((access_vec_dec data (( 0 :: int)::ii))) :: 1 Word.word)))) + ('')'')))))))))))))) in + (set_Minterrupts_MSI mip_ref + ((bool_to_bits + (((((cast_unit_vec0 ((access_vec_dec data (( 0 :: int)::ii))) :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) + :: 1 Word.word)) \<then> + clint_dispatch () ) \<then> return (MemValue () )) + else if ((((((addr = MTIMECMP_BASE))) \<and> (((width = (( 8 :: int)::ii))))))) then + (let (_ :: unit) = + (print_endline + (((op@) (''clint['') + (((op@) ((string_of_bits addr)) + (((op@) (''] <- '') (((op@) ((string_of_bits data)) ('' (mtimecmp)'')))))))))) in + (write_reg mtimecmp_ref ((zero_extend data (( 64 :: int)::ii) :: 64 Word.word)) \<then> + clint_dispatch () ) \<then> return (MemValue () )) + else + (let (_ :: unit) = + (print_endline + (((op@) (''clint['') + (((op@) ((string_of_bits addr)) + (((op@) (''] <- '') (((op@) ((string_of_bits data)) ('' (<unmapped>)'')))))))))) in + return (MemException E_SAMO_Access_Fault))))" (*val tick_clock : unit -> M unit*) @@ -4471,162 +8943,707 @@ definition init_sys :: " unit \<Rightarrow>((register_value),(unit),(exception) definition tick_clock :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " tick_clock _ = ( (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - write_reg mcycle_ref ((add_vec_int w__0 (( 1 :: int)::ii) :: 64 Word.word))))" + (write_reg mcycle_ref ((add_vec_int w__0 (( 1 :: int)::ii) :: 64 Word.word)) \<then> + (read_reg mtime_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + write_reg mtime_ref ((add_vec_int w__1 (( 1 :: int)::ii) :: 64 Word.word)) \<then> clint_dispatch () )))" + + +(*val Mk_htif_cmd : mword ty64 -> htif_cmd*) + +definition Mk_htif_cmd :: "(64)Word.word \<Rightarrow> htif_cmd " where + " Mk_htif_cmd v = ( + (| htif_cmd_htif_cmd_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" + + +(*val _get_htif_cmd_bits : htif_cmd -> mword ty64*) + +definition get_htif_cmd_bits :: " htif_cmd \<Rightarrow>(64)Word.word " where + " get_htif_cmd_bits v = ( + (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" + + +(*val _set_htif_cmd_bits : register_ref regstate register_value htif_cmd -> mword ty64 -> M unit*) + +definition set_htif_cmd_bits :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_htif_cmd_bits r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" + + +(*val _update_htif_cmd_bits : htif_cmd -> mword ty64 -> htif_cmd*) + +definition update_htif_cmd_bits :: " htif_cmd \<Rightarrow>(64)Word.word \<Rightarrow> htif_cmd " where + " update_htif_cmd_bits v x = ( + (v (| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + +(*val _get_htif_cmd_device : htif_cmd -> mword ty8*) + +definition get_htif_cmd_device :: " htif_cmd \<Rightarrow>(8)Word.word " where + " get_htif_cmd_device v = ( + (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word))" + + +(*val _set_htif_cmd_device : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit*) + +definition set_htif_cmd_device :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_htif_cmd_device r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 r) (( 63 :: int)::ii) (( 56 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" + + +(*val _update_htif_cmd_device : htif_cmd -> mword ty8 -> htif_cmd*) + +definition update_htif_cmd_device :: " htif_cmd \<Rightarrow>(8)Word.word \<Rightarrow> htif_cmd " where + " update_htif_cmd_device v x = ( + (v (| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 63 :: int)::ii) (( 56 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word))|)))" + + +(*val _get_htif_cmd_cmd : htif_cmd -> mword ty8*) + +definition get_htif_cmd_cmd :: " htif_cmd \<Rightarrow>(8)Word.word " where + " get_htif_cmd_cmd v = ( + (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 55 :: int)::ii) (( 48 :: int)::ii) :: 8 Word.word))" + + +(*val _set_htif_cmd_cmd : register_ref regstate register_value htif_cmd -> mword ty8 -> M unit*) + +definition set_htif_cmd_cmd :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_htif_cmd_cmd r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 r) (( 55 :: int)::ii) (( 48 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" + + +(*val _update_htif_cmd_cmd : htif_cmd -> mword ty8 -> htif_cmd*) + +definition update_htif_cmd_cmd :: " htif_cmd \<Rightarrow>(8)Word.word \<Rightarrow> htif_cmd " where + " update_htif_cmd_cmd v x = ( + (v (| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 55 :: int)::ii) (( 48 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word))|)))" + + +(*val _get_htif_cmd_payload : htif_cmd -> mword ty48*) + +definition get_htif_cmd_payload :: " htif_cmd \<Rightarrow>(48)Word.word " where + " get_htif_cmd_payload v = ( + (subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word))" + + +(*val _set_htif_cmd_payload : register_ref regstate register_value htif_cmd -> mword ty48 -> M unit*) + +definition set_htif_cmd_payload :: "((regstate),(register_value),(htif_cmd))register_ref \<Rightarrow>(48)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_htif_cmd_payload r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 r) (( 47 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" + + +(*val _update_htif_cmd_payload : htif_cmd -> mword ty48 -> htif_cmd*) + +definition update_htif_cmd_payload :: " htif_cmd \<Rightarrow>(48)Word.word \<Rightarrow> htif_cmd " where + " update_htif_cmd_payload v x = ( + (v (| + htif_cmd_htif_cmd_chunk_0 := + ((update_subrange_vec_dec(htif_cmd_htif_cmd_chunk_0 v) (( 47 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) + :: 64 Word.word))|)))" + + +(*val htif_load : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition htif_load :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " htif_load addr width = ( + (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: xlenbits) . + (let (_ :: unit) = + (print_endline + (((op@) (''htif['') + (((op@) ((string_of_bits addr)) (((op@) (''] -> '') ((string_of_bits w__0))))))))) in + if (((width = (( 8 :: int)::ii)))) then + (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: xlenbits) . + return (MemValue ((zero_extend w__1 (( 64 :: int)::ii) :: ( 'int8_times_n::len)Word.word)))) + else return (MemException E_Load_Access_Fault))))" + + +(*val htif_store : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +definition htif_store :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " htif_store addr width data = ( + (let (_ :: unit) = + (print_endline + (((op@) (''htif['') + (((op@) ((string_of_bits addr)) (((op@) (''] <- '') ((string_of_bits data))))))))) in + (let (cbits :: xlenbits) = ((EXTZ (( 64 :: int)::ii) data :: 64 Word.word)) in + write_reg htif_tohost_ref cbits \<then> + ((let cmd = (Mk_htif_cmd cbits) in + (let b__0 = ((get_htif_cmd_device cmd :: 8 Word.word)) in + (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then + (let (_ :: unit) = + (print_endline + (((op@) (''htif-syscall-proxy cmd: '') + ((string_of_bits ((get_htif_cmd_payload cmd :: 48 Word.word))))))) in + if (((((cast_unit_vec0 ((access_vec_dec ((get_htif_cmd_payload cmd :: 48 Word.word)) (( 0 :: int)::ii))) + :: 1 Word.word)) = (vec_of_bits [B1] :: 1 Word.word)))) then + write_reg htif_done_ref True \<then> + write_reg + htif_exit_code_ref + ((shift_bits_right + ((zero_extend ((get_htif_cmd_payload cmd :: 48 Word.word)) xlen :: 64 Word.word)) + (vec_of_bits [B0,B1] :: 2 Word.word) + :: 64 Word.word)) + else return () ) + else + return (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word)))) then + (let (_ :: unit) = + (print_endline + (((op@) (''htif-term cmd: '') + ((string_of_bits ((get_htif_cmd_payload cmd :: 48 Word.word))))))) in + (let b__2 = ((get_htif_cmd_cmd cmd :: 8 Word.word)) in + if (((b__2 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then () + else if (((b__2 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word)))) then + plat_term_write + ((subrange_vec_dec ((get_htif_cmd_payload cmd :: 48 Word.word)) (( 7 :: int)::ii) (( 0 :: int)::ii) + :: 8 Word.word)) + else print_endline (((op@) (''Unknown term cmd: '') ((string_of_bits b__2)))))) + else print_endline (((op@) (''htif-???? cmd: '') ((string_of_bits data)))))) \<then> + return (MemValue () )))))))" + + +(*val htif_tick : unit -> M unit*) + +definition htif_tick :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " htif_tick _ = ( + (read_reg htif_tohost_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: xlenbits) . + (let (_ :: unit) = (print_endline (((op@) (''htif::tick '') ((string_of_bits w__0))))) in + write_reg htif_tohost_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))" + + +(*val within_mmio_readable : mword ty64 -> integer -> bool*) + +definition within_mmio_readable :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where + " within_mmio_readable (addr :: xlenbits) (width :: int) = ( + (((within_clint addr width)) \<or> (((((within_htif_readable addr width)) \<and> (((( 1 :: int)::ii) \<le> width)))))))" + + +(*val within_mmio_writable : mword ty64 -> integer -> bool*) + +definition within_mmio_writable :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where + " within_mmio_writable (addr :: xlenbits) (width :: int) = ( + (((within_clint addr width)) \<or> (((((within_htif_writable addr width)) \<and> ((width \<le> (( 8 :: int)::ii))))))))" + + +(*val mmio_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition mmio_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " mmio_read (addr :: xlenbits) (width :: int) = ( + if ((within_clint addr width)) then + (clint_load addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + else if (((((within_htif_readable addr width)) \<and> (((( 1 :: int)::ii) \<le> width))))) then + (htif_load addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + else return (MemException E_Load_Access_Fault))" + + +(*val mmio_write : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +definition mmio_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " mmio_write (addr :: xlenbits) (width :: int) (data :: 'int8_times_n bits) = ( + if ((within_clint addr width)) then clint_store addr width data + else if (((((within_htif_writable addr width)) \<and> ((width \<le> (( 8 :: int)::ii)))))) then + htif_store addr width data + else return (MemException E_SAMO_Access_Fault))" + + +(*val init_platform : unit -> M unit*) + +definition init_platform :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " init_platform _ = ( + (write_reg htif_tohost_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) \<then> + write_reg htif_done_ref False) \<then> + write_reg htif_exit_code_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))" + + +(*val tick_platform : unit -> M unit*) + +definition tick_platform :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " tick_platform _ = ( + (let (_ :: unit) = (cancel_reservation () ) in + htif_tick () ))" + + +(*val is_aligned_addr : mword ty64 -> integer -> bool*) + +definition is_aligned_addr :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where + " is_aligned_addr (addr :: xlenbits) (width :: int) = ( + (((ex_int ((hardware_mod ((Word.uint addr)) width)))) = (( 0 :: int)::ii)))" + + +(*val phys_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition phys_mem_read :: " ReadType \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " phys_mem_read (t :: ReadType) (addr :: xlenbits) (width :: int) (aq :: bool) (rl :: bool) (res :: + bool) = ( + (RISCV_read addr width aq rl res :: ( (( 'int8_times_n::len)Word.word)option) M) \<bind> (\<lambda> (w__0 :: + (( 'int8_times_n::len)Word.word)option) . + return ((case (t, w__0) of + (Instruction, None) => MemException E_Fetch_Access_Fault + | (Data, None) => MemException E_Load_Access_Fault + | (_, Some (v)) => + (let (_ :: unit) = + (print_endline + (((op@) (''mem['') + (((op@) ((readType_to_str t)) + (((op@) ('','') + (((op@) ((string_of_bits addr)) + (((op@) (''] -> '') ((string_of_bits v))))))))))))) in + MemValue v) + ))))" + + +(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition checked_mem_read :: " ReadType \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " checked_mem_read (t :: ReadType) (addr :: xlenbits) (width :: int) = ( + if ((((((((readType_to_str t)) = ((readType_to_str Data))))) \<and> ((within_mmio_readable addr width))))) then + (mmio_read addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + else if ((within_phys_mem addr width)) then + (phys_mem_read t addr width False False False :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + else return (MemException E_Load_Access_Fault))" + + +(*val MEMr : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_strong_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved_strong_acquire : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition MEMr0 :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr0 addr width = ( (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_acquire0 :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_acquire0 addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_strong_acquire0 :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_strong_acquire0 addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_reserved0 :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_reserved0 addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_reserved_acquire0 :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_reserved_acquire0 addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_reserved_strong_acquire0 :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_reserved_strong_acquire0 addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +(*val mem_read : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition mem_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " mem_read addr width aq rl res = ( + if ((((((aq \<or> res))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then + return (MemException E_Load_Addr_Align) + else + (case (aq, rl, res) of + (False, False, False) => + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (True, False, False) => (MEMr_acquire0 addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (False, False, True) => + (MEMr_reserved0 addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (True, False, True) => + (MEMr_reserved_acquire0 addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (False, True, False) => throw (Error_not_implemented (''load.rl'')) + | (True, True, False) => + (MEMr_strong_acquire0 addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (False, True, True) => throw (Error_not_implemented (''lr.rl'')) + | (True, True, True) => + (MEMr_reserved_strong_acquire0 addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + ))" + + +(*val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*) + +definition mem_write_ea :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " mem_write_ea addr width aq rl con = ( + if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then + return (MemException E_SAMO_Addr_Align) + else + (case (aq, rl, con) of + (False, False, False) => MEMea addr width \<then> return (MemValue () ) + | (False, True, False) => MEMea_release addr width \<then> return (MemValue () ) + | (False, False, True) => MEMea_conditional addr width \<then> return (MemValue () ) + | (False, True, True) => MEMea_conditional_release addr width \<then> return (MemValue () ) + | (True, False, False) => throw (Error_not_implemented (''store.aq'')) + | (True, True, False) => MEMea_strong_release addr width \<then> return (MemValue () ) + | (True, False, True) => throw (Error_not_implemented (''sc.aq'')) + | (True, True, True) => MEMea_conditional_strong_release addr width \<then> return (MemValue () ) + ))" + + +(*val phys_mem_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +definition phys_mem_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " phys_mem_write (addr :: xlenbits) (width :: int) (data :: 'int8_times_n bits) = ( + (let (_ :: unit) = + (print_endline + (((op@) (''mem['') + (((op@) ((string_of_bits addr)) (((op@) (''] <- '') ((string_of_bits data))))))))) in + RISCV_write addr width data \<bind> (\<lambda> (w__0 :: bool) . + return (if w__0 then MemValue () + else MemException E_SAMO_Access_Fault))))" + + +(*val checked_mem_write : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +definition checked_mem_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " checked_mem_write (addr :: xlenbits) (width :: int) (data :: 'int8_times_n bits) = ( + if ((within_mmio_writable addr width)) then mmio_write addr width data + else if ((within_phys_mem addr width)) then phys_mem_write addr width data + else return (MemException E_SAMO_Access_Fault))" + + +(*val MEMval : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_strong_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional_strong_release : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +definition MEMval :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_release :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_release addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_strong_release :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_strong_release addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_conditional :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_conditional addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_conditional_release :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_conditional_release addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_conditional_strong_release :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_conditional_strong_release addr width data = ( checked_mem_write addr width data )" + + +(*val mem_write_value : forall 'int8_times_n . Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult unit)*) + +definition mem_write_value :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " mem_write_value addr width value1 aq rl con = ( + if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then + return (MemException E_SAMO_Addr_Align) + else + (case (aq, rl, con) of + (False, False, False) => checked_mem_write addr width value1 + | (False, True, False) => MEMval_release addr width value1 + | (False, False, True) => MEMval_conditional addr width value1 + | (False, True, True) => MEMval_conditional_release addr width value1 + | (True, False, False) => throw (Error_not_implemented (''store.aq'')) + | (True, True, False) => MEMval_strong_release addr width value1 + | (True, False, True) => throw (Error_not_implemented (''sc.aq'')) + | (True, True, True) => MEMval_conditional_strong_release addr width value1 + ))" definition PAGESIZE_BITS :: " int " where " PAGESIZE_BITS = ( (( 12 :: int)::ii))" -(*val _get_PTE_Bits : PTE_Bits -> mword ty8*) +(*val Mk_PTE_Bits : mword ty8 -> PTE_Bits*) -fun get_PTE_Bits :: " PTE_Bits \<Rightarrow>(8)Word.word " where - " get_PTE_Bits (Mk_PTE_Bits (v)) = ( v )" +definition Mk_PTE_Bits :: "(8)Word.word \<Rightarrow> PTE_Bits " where + " Mk_PTE_Bits v = ( + (| PTE_Bits_PTE_Bits_chunk_0 = ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) |) )" -(*val _set_PTE_Bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*) +(*val _get_PTE_Bits_bits : PTE_Bits -> mword ty8*) -definition set_PTE_Bits :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_PTE_Bits r_ref v = ( +definition get_PTE_Bits_bits :: " PTE_Bits \<Rightarrow>(8)Word.word " where + " get_PTE_Bits_bits v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" + + +(*val _set_PTE_Bits_bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*) + +definition set_PTE_Bits_bits :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_PTE_Bits_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_PTE_Bits v) in + (let r = + ((r (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 8 Word.word))|))) in write_reg r_ref r)))" -fun get_PTE_Bits_D :: " PTE_Bits \<Rightarrow>(1)Word.word " where - " get_PTE_Bits_D (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" +(*val _update_PTE_Bits_bits : PTE_Bits -> mword ty8 -> PTE_Bits*) + +definition update_PTE_Bits_bits :: " PTE_Bits \<Rightarrow>(8)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_bits v x = ( + (v (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 8 Word.word))|)))" + + +definition get_PTE_Bits_D :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_D v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" definition set_PTE_Bits_D :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_PTE_Bits_D r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . - (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 8 Word.word)) in - write_reg r_ref (Mk_PTE_Bits r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|))) in + write_reg r_ref r)))" -fun update_PTE_Bits_D :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where - " update_PTE_Bits_D (Mk_PTE_Bits (v)) x = ( - Mk_PTE_Bits ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 8 Word.word)))" +definition update_PTE_Bits_D :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_D v x = ( + (v (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 7 :: int)::ii) (( 7 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|)))" -fun get_PTE_Bits_A :: " PTE_Bits \<Rightarrow>(1)Word.word " where - " get_PTE_Bits_A (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" +definition get_PTE_Bits_A :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_A v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" definition set_PTE_Bits_A :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_PTE_Bits_A r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . - (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 8 Word.word)) in - write_reg r_ref (Mk_PTE_Bits r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 6 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|))) in + write_reg r_ref r)))" -fun update_PTE_Bits_A :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where - " update_PTE_Bits_A (Mk_PTE_Bits (v)) x = ( - Mk_PTE_Bits ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 8 Word.word)))" +definition update_PTE_Bits_A :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_A v x = ( + (v (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 6 :: int)::ii) (( 6 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|)))" -fun get_PTE_Bits_G :: " PTE_Bits \<Rightarrow>(1)Word.word " where - " get_PTE_Bits_G (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" +definition get_PTE_Bits_G :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_G v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" definition set_PTE_Bits_G :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_PTE_Bits_G r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . - (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 8 Word.word)) in - write_reg r_ref (Mk_PTE_Bits r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|))) in + write_reg r_ref r)))" -fun update_PTE_Bits_G :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where - " update_PTE_Bits_G (Mk_PTE_Bits (v)) x = ( - Mk_PTE_Bits ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 8 Word.word)))" +definition update_PTE_Bits_G :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_G v x = ( + (v (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 5 :: int)::ii) (( 5 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|)))" -fun get_PTE_Bits_U :: " PTE_Bits \<Rightarrow>(1)Word.word " where - " get_PTE_Bits_U (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" +definition get_PTE_Bits_U :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_U v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" definition set_PTE_Bits_U :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_PTE_Bits_U r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . - (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 8 Word.word)) in - write_reg r_ref (Mk_PTE_Bits r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|))) in + write_reg r_ref r)))" -fun update_PTE_Bits_U :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where - " update_PTE_Bits_U (Mk_PTE_Bits (v)) x = ( - Mk_PTE_Bits ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 8 Word.word)))" +definition update_PTE_Bits_U :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_U v x = ( + (v (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 4 :: int)::ii) (( 4 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|)))" -fun get_PTE_Bits_X :: " PTE_Bits \<Rightarrow>(1)Word.word " where - " get_PTE_Bits_X (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" +definition get_PTE_Bits_X :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_X v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" definition set_PTE_Bits_X :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_PTE_Bits_X r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . - (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 8 Word.word)) in - write_reg r_ref (Mk_PTE_Bits r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 3 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|))) in + write_reg r_ref r)))" -fun update_PTE_Bits_X :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where - " update_PTE_Bits_X (Mk_PTE_Bits (v)) x = ( - Mk_PTE_Bits ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 8 Word.word)))" +definition update_PTE_Bits_X :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_X v x = ( + (v (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 3 :: int)::ii) (( 3 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|)))" -fun get_PTE_Bits_W :: " PTE_Bits \<Rightarrow>(1)Word.word " where - " get_PTE_Bits_W (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" +definition get_PTE_Bits_W :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_W v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" definition set_PTE_Bits_W :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_PTE_Bits_W r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . - (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 8 Word.word)) in - write_reg r_ref (Mk_PTE_Bits r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|))) in + write_reg r_ref r)))" -fun update_PTE_Bits_W :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where - " update_PTE_Bits_W (Mk_PTE_Bits (v)) x = ( - Mk_PTE_Bits ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 8 Word.word)))" +definition update_PTE_Bits_W :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_W v x = ( + (v (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 2 :: int)::ii) (( 2 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|)))" -fun get_PTE_Bits_R :: " PTE_Bits \<Rightarrow>(1)Word.word " where - " get_PTE_Bits_R (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" +definition get_PTE_Bits_R :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_R v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" definition set_PTE_Bits_R :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_PTE_Bits_R r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . - (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 8 Word.word)) in - write_reg r_ref (Mk_PTE_Bits r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|))) in + write_reg r_ref r)))" -fun update_PTE_Bits_R :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where - " update_PTE_Bits_R (Mk_PTE_Bits (v)) x = ( - Mk_PTE_Bits ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 8 Word.word)))" +definition update_PTE_Bits_R :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_R v x = ( + (v (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 1 :: int)::ii) (( 1 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|)))" -fun get_PTE_Bits_V :: " PTE_Bits \<Rightarrow>(1)Word.word " where - " get_PTE_Bits_V (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" +definition get_PTE_Bits_V :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_V v = ( (subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" definition set_PTE_Bits_V :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_PTE_Bits_V r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . - (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 8 Word.word)) in - write_reg r_ref (Mk_PTE_Bits r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 r) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|))) in + write_reg r_ref r)))" -fun update_PTE_Bits_V :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where - " update_PTE_Bits_V (Mk_PTE_Bits (v)) x = ( - Mk_PTE_Bits ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 8 Word.word)))" +definition update_PTE_Bits_V :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_V v x = ( + (v (| + PTE_Bits_PTE_Bits_chunk_0 := + ((update_subrange_vec_dec(PTE_Bits_PTE_Bits_chunk_0 v) (( 0 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) + :: 8 Word.word))|)))" (*val isPTEPtr : mword ty8 -> bool*) @@ -4681,7 +9698,7 @@ fun checkPTEPermission :: " AccessType \<Rightarrow> Privilege \<Rightarrow> bo definition update_PTE_Bits :: " PTE_Bits \<Rightarrow> AccessType \<Rightarrow>(PTE_Bits)option " where " update_PTE_Bits (p :: PTE_Bits) (a :: AccessType) = ( (let update_d = - (((((((a = Write))) \<or> (((a = ReadWrite)))))) \<and> (((((get_PTE_Bits_D p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))) in + (((((((((accessType_to_str a)) = ((accessType_to_str Write))))) \<or> (((((accessType_to_str a)) = ((accessType_to_str ReadWrite)))))))) \<and> (((((get_PTE_Bits_D p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))) in (let update_a = (((get_PTE_Bits_A p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))) in if (((update_d \<or> update_a))) then (let np = (update_PTE_Bits_A p ((bool_to_bits True :: 1 Word.word))) in @@ -4694,11 +9711,11 @@ definition update_PTE_Bits :: " PTE_Bits \<Rightarrow> AccessType \<Rightarrow> definition PTW_Error_of_num :: " int \<Rightarrow> PTW_Error " where " PTW_Error_of_num arg0 = ( - (let l__0 = arg0 in - if (((l__0 = (( 0 :: int)::ii)))) then PTW_Access - else if (((l__0 = (( 1 :: int)::ii)))) then PTW_Invalid_PTE - else if (((l__0 = (( 2 :: int)::ii)))) then PTW_No_Permission - else if (((l__0 = (( 3 :: int)::ii)))) then PTW_Misaligned + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then PTW_Access + else if (((p00 = (( 1 :: int)::ii)))) then PTW_Invalid_PTE + else if (((p00 = (( 2 :: int)::ii)))) then PTW_No_Permission + else if (((p00 = (( 3 :: int)::ii)))) then PTW_Misaligned else PTW_PTE_Update))" @@ -4712,15 +9729,39 @@ fun num_of_PTW_Error :: " PTW_Error \<Rightarrow> int " where |" num_of_PTW_Error PTW_PTE_Update = ( (( 4 :: int)::ii))" +(*val ptw_error_to_str : PTW_Error -> string*) + +fun ptw_error_to_str :: " PTW_Error \<Rightarrow> string " where + " ptw_error_to_str PTW_Access = ( (''mem-access-error''))" +|" ptw_error_to_str PTW_Invalid_PTE = ( (''invalid-pte''))" +|" ptw_error_to_str PTW_No_Permission = ( (''no-permission''))" +|" ptw_error_to_str PTW_Misaligned = ( (''misaligned-superpage''))" +|" ptw_error_to_str PTW_PTE_Update = ( (''pte-update-needed''))" + + (*val translationException : AccessType -> PTW_Error -> ExceptionType*) -fun translationException :: " AccessType \<Rightarrow> PTW_Error \<Rightarrow> ExceptionType " where - " translationException (Read :: AccessType) (PTW_Access :: PTW_Error) = ( E_Load_Access_Fault )" -|" translationException (Read :: AccessType) (_ :: PTW_Error) = ( E_Load_Page_Fault )" -|" translationException (Write :: AccessType) (PTW_Access :: PTW_Error) = ( E_SAMO_Access_Fault )" -|" translationException (Write :: AccessType) (_ :: PTW_Error) = ( E_SAMO_Page_Fault )" -|" translationException (Fetch :: AccessType) (PTW_Access :: PTW_Error) = ( E_Fetch_Access_Fault )" -|" translationException (Fetch :: AccessType) (_ :: PTW_Error) = ( E_Fetch_Page_Fault )" +definition translationException :: " AccessType \<Rightarrow> PTW_Error \<Rightarrow> ExceptionType " where + " translationException (a :: AccessType) (f :: PTW_Error) = ( + (let (e :: ExceptionType) = + ((case (a, f) of + (ReadWrite, PTW_Access) => E_SAMO_Access_Fault + | (ReadWrite, _) => E_SAMO_Page_Fault + | (Read, PTW_Access) => E_Load_Access_Fault + | (Read, _) => E_Load_Page_Fault + | (Write, PTW_Access) => E_SAMO_Access_Fault + | (Write, _) => E_SAMO_Page_Fault + | (Fetch, PTW_Access) => E_Fetch_Access_Fault + | (Fetch, _) => E_Fetch_Page_Fault + )) in + (let (_ :: unit) = + (print_endline + (((op@) (''translationException('') + (((op@) ((accessType_to_str a)) + (((op@) ('', '') + (((op@) ((ptw_error_to_str f)) + (((op@) ('') -> '') ((exceptionType_to_str e))))))))))))) in + e)))" definition SV39_LEVEL_BITS :: " int " where @@ -4739,65 +9780,107 @@ definition PTE39_SIZE :: " int " where " PTE39_SIZE = ( (( 8 :: int)::ii))" -(*val _get_SV39_Vaddr : SV39_Vaddr -> mword ty39*) +(*val Mk_SV39_Vaddr : mword ty39 -> SV39_Vaddr*) + +definition Mk_SV39_Vaddr :: "(39)Word.word \<Rightarrow> SV39_Vaddr " where + " Mk_SV39_Vaddr v = ( + (| SV39_Vaddr_SV39_Vaddr_chunk_0 = ((subrange_vec_dec v (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word)) |) )" -fun get_SV39_Vaddr :: " SV39_Vaddr \<Rightarrow>(39)Word.word " where - " get_SV39_Vaddr (Mk_SV39_Vaddr (v)) = ( v )" +(*val _get_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39*) -(*val _set_SV39_Vaddr : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*) +definition get_SV39_Vaddr_bits :: " SV39_Vaddr \<Rightarrow>(39)Word.word " where + " get_SV39_Vaddr_bits v = ( + (subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word))" -definition set_SV39_Vaddr :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(39)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_SV39_Vaddr r_ref v = ( + +(*val _set_SV39_Vaddr_bits : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*) + +definition set_SV39_Vaddr_bits :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(39)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_Vaddr_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_SV39_Vaddr v) in + (let r = + ((r (| + SV39_Vaddr_SV39_Vaddr_chunk_0 := + ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 r) (( 38 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word)) + :: 39 Word.word))|))) in write_reg r_ref r)))" +(*val _update_SV39_Vaddr_bits : SV39_Vaddr -> mword ty39 -> SV39_Vaddr*) + +definition update_SV39_Vaddr_bits :: " SV39_Vaddr \<Rightarrow>(39)Word.word \<Rightarrow> SV39_Vaddr " where + " update_SV39_Vaddr_bits v x = ( + (v (| + SV39_Vaddr_SV39_Vaddr_chunk_0 := + ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word)) + :: 39 Word.word))|)))" + + (*val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27*) -fun get_SV39_Vaddr_VPNi :: " SV39_Vaddr \<Rightarrow>(27)Word.word " where - " get_SV39_Vaddr_VPNi (Mk_SV39_Vaddr (v)) = ( (subrange_vec_dec v (( 38 :: int)::ii) (( 12 :: int)::ii) :: 27 Word.word))" +definition get_SV39_Vaddr_VPNi :: " SV39_Vaddr \<Rightarrow>(27)Word.word " where + " get_SV39_Vaddr_VPNi v = ( + (subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 12 :: int)::ii) :: 27 Word.word))" (*val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit*) definition set_SV39_Vaddr_VPNi :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_SV39_Vaddr_VPNi r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_Vaddr) . - (let r = ((get_SV39_Vaddr w__0 :: 39 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 38 :: int)::ii) (( 12 :: int)::ii) v :: 39 Word.word)) in - write_reg r_ref (Mk_SV39_Vaddr r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + SV39_Vaddr_SV39_Vaddr_chunk_0 := + ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 r) (( 38 :: int)::ii) (( 12 :: int)::ii) + ((subrange_vec_dec v (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 39 Word.word))|))) in + write_reg r_ref r)))" (*val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr*) -fun update_SV39_Vaddr_VPNi :: " SV39_Vaddr \<Rightarrow>(27)Word.word \<Rightarrow> SV39_Vaddr " where - " update_SV39_Vaddr_VPNi (Mk_SV39_Vaddr (v)) x = ( - Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 38 :: int)::ii) (( 12 :: int)::ii) x :: 39 Word.word)))" +definition update_SV39_Vaddr_VPNi :: " SV39_Vaddr \<Rightarrow>(27)Word.word \<Rightarrow> SV39_Vaddr " where + " update_SV39_Vaddr_VPNi v x = ( + (v (| + SV39_Vaddr_SV39_Vaddr_chunk_0 := + ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 38 :: int)::ii) (( 12 :: int)::ii) + ((subrange_vec_dec x (( 26 :: int)::ii) (( 0 :: int)::ii) :: 27 Word.word)) + :: 39 Word.word))|)))" (*val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12*) -fun get_SV39_Vaddr_PgOfs :: " SV39_Vaddr \<Rightarrow>(12)Word.word " where - " get_SV39_Vaddr_PgOfs (Mk_SV39_Vaddr (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))" +definition get_SV39_Vaddr_PgOfs :: " SV39_Vaddr \<Rightarrow>(12)Word.word " where + " get_SV39_Vaddr_PgOfs v = ( + (subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))" (*val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit*) definition set_SV39_Vaddr_PgOfs :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_SV39_Vaddr_PgOfs r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_Vaddr) . - (let r = ((get_SV39_Vaddr w__0 :: 39 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 0 :: int)::ii) v :: 39 Word.word)) in - write_reg r_ref (Mk_SV39_Vaddr r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + SV39_Vaddr_SV39_Vaddr_chunk_0 := + ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word)) + :: 39 Word.word))|))) in + write_reg r_ref r)))" (*val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr*) -fun update_SV39_Vaddr_PgOfs :: " SV39_Vaddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Vaddr " where - " update_SV39_Vaddr_PgOfs (Mk_SV39_Vaddr (v)) x = ( - Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) x :: 39 Word.word)))" +definition update_SV39_Vaddr_PgOfs :: " SV39_Vaddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Vaddr " where + " update_SV39_Vaddr_PgOfs v x = ( + (v (| + SV39_Vaddr_SV39_Vaddr_chunk_0 := + ((update_subrange_vec_dec(SV39_Vaddr_SV39_Vaddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word)) + :: 39 Word.word))|)))" (*val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr*) @@ -4806,42 +9889,75 @@ fun update_SV39_Vaddr_PgOfs :: " SV39_Vaddr \<Rightarrow>(12)Word.word \<Righta (*val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit*) -(*val _get_SV39_Paddr : SV39_Paddr -> mword ty56*) +(*val Mk_SV39_Paddr : mword ty56 -> SV39_Paddr*) + +definition Mk_SV39_Paddr :: "(56)Word.word \<Rightarrow> SV39_Paddr " where + " Mk_SV39_Paddr v = ( + (| SV39_Paddr_SV39_Paddr_chunk_0 = ((subrange_vec_dec v (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) |) )" -fun get_SV39_Paddr :: " SV39_Paddr \<Rightarrow>(56)Word.word " where - " get_SV39_Paddr (Mk_SV39_Paddr (v)) = ( v )" +(*val _get_SV39_Paddr_bits : SV39_Paddr -> mword ty56*) -(*val _set_SV39_Paddr : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*) +definition get_SV39_Paddr_bits :: " SV39_Paddr \<Rightarrow>(56)Word.word " where + " get_SV39_Paddr_bits v = ( + (subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word))" -definition set_SV39_Paddr :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(56)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_SV39_Paddr r_ref v = ( + +(*val _set_SV39_Paddr_bits : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*) + +definition set_SV39_Paddr_bits :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(56)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_Paddr_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_SV39_Paddr v) in + (let r = + ((r (| + SV39_Paddr_SV39_Paddr_chunk_0 := + ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 r) (( 55 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) + :: 56 Word.word))|))) in write_reg r_ref r)))" +(*val _update_SV39_Paddr_bits : SV39_Paddr -> mword ty56 -> SV39_Paddr*) + +definition update_SV39_Paddr_bits :: " SV39_Paddr \<Rightarrow>(56)Word.word \<Rightarrow> SV39_Paddr " where + " update_SV39_Paddr_bits v x = ( + (v (| + SV39_Paddr_SV39_Paddr_chunk_0 := + ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) + :: 56 Word.word))|)))" + + (*val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44*) -fun get_SV39_Paddr_PPNi :: " SV39_Paddr \<Rightarrow>(44)Word.word " where - " get_SV39_Paddr_PPNi (Mk_SV39_Paddr (v)) = ( (subrange_vec_dec v (( 55 :: int)::ii) (( 12 :: int)::ii) :: 44 Word.word))" +definition get_SV39_Paddr_PPNi :: " SV39_Paddr \<Rightarrow>(44)Word.word " where + " get_SV39_Paddr_PPNi v = ( + (subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 12 :: int)::ii) :: 44 Word.word))" (*val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit*) definition set_SV39_Paddr_PPNi :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_SV39_Paddr_PPNi r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_Paddr) . - (let r = ((get_SV39_Paddr w__0 :: 56 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 55 :: int)::ii) (( 12 :: int)::ii) v :: 56 Word.word)) in - write_reg r_ref (Mk_SV39_Paddr r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + SV39_Paddr_SV39_Paddr_chunk_0 := + ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 r) (( 55 :: int)::ii) (( 12 :: int)::ii) + ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word)) + :: 56 Word.word))|))) in + write_reg r_ref r)))" (*val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr*) -fun update_SV39_Paddr_PPNi :: " SV39_Paddr \<Rightarrow>(44)Word.word \<Rightarrow> SV39_Paddr " where - " update_SV39_Paddr_PPNi (Mk_SV39_Paddr (v)) x = ( - Mk_SV39_Paddr ((update_subrange_vec_dec v (( 55 :: int)::ii) (( 12 :: int)::ii) x :: 56 Word.word)))" +definition update_SV39_Paddr_PPNi :: " SV39_Paddr \<Rightarrow>(44)Word.word \<Rightarrow> SV39_Paddr " where + " update_SV39_Paddr_PPNi v x = ( + (v (| + SV39_Paddr_SV39_Paddr_chunk_0 := + ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 55 :: int)::ii) (( 12 :: int)::ii) + ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word)) + :: 56 Word.word))|)))" (*val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE*) @@ -4850,95 +9966,151 @@ fun update_SV39_Paddr_PPNi :: " SV39_Paddr \<Rightarrow>(44)Word.word \<Rightar (*val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit*) -fun get_SV39_Paddr_PgOfs :: " SV39_Paddr \<Rightarrow>(12)Word.word " where - " get_SV39_Paddr_PgOfs (Mk_SV39_Paddr (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))" +definition get_SV39_Paddr_PgOfs :: " SV39_Paddr \<Rightarrow>(12)Word.word " where + " get_SV39_Paddr_PgOfs v = ( + (subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))" definition set_SV39_Paddr_PgOfs :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_SV39_Paddr_PgOfs r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_Paddr) . - (let r = ((get_SV39_Paddr w__0 :: 56 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 0 :: int)::ii) v :: 56 Word.word)) in - write_reg r_ref (Mk_SV39_Paddr r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + SV39_Paddr_SV39_Paddr_chunk_0 := + ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 r) (( 11 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word)) + :: 56 Word.word))|))) in + write_reg r_ref r)))" + +definition update_SV39_Paddr_PgOfs :: " SV39_Paddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Paddr " where + " update_SV39_Paddr_PgOfs v x = ( + (v (| + SV39_Paddr_SV39_Paddr_chunk_0 := + ((update_subrange_vec_dec(SV39_Paddr_SV39_Paddr_chunk_0 v) (( 11 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word)) + :: 56 Word.word))|)))" -fun update_SV39_Paddr_PgOfs :: " SV39_Paddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Paddr " where - " update_SV39_Paddr_PgOfs (Mk_SV39_Paddr (v)) x = ( - Mk_SV39_Paddr ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) x :: 56 Word.word)))" +(*val Mk_SV39_PTE : mword ty64 -> SV39_PTE*) -fun get_SV39_PTE :: " SV39_PTE \<Rightarrow>(64)Word.word " where - " get_SV39_PTE (Mk_SV39_PTE (v)) = ( v )" +definition Mk_SV39_PTE :: "(64)Word.word \<Rightarrow> SV39_PTE " where + " Mk_SV39_PTE v = ( + (| SV39_PTE_SV39_PTE_chunk_0 = ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" -definition set_SV39_PTE :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " set_SV39_PTE r_ref v = ( +definition get_SV39_PTE_bits :: " SV39_PTE \<Rightarrow>(64)Word.word " where + " get_SV39_PTE_bits v = ( + (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))" + + +definition set_SV39_PTE_bits :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_PTE_bits r_ref v = ( reg_deref r_ref \<bind> (\<lambda> r . - (let r = (Mk_SV39_PTE v) in + (let r = + ((r (| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 r) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|))) in write_reg r_ref r)))" -fun get_SV39_PTE_PPNi :: " SV39_PTE \<Rightarrow>(44)Word.word " where - " get_SV39_PTE_PPNi (Mk_SV39_PTE (v)) = ( (subrange_vec_dec v (( 53 :: int)::ii) (( 10 :: int)::ii) :: 44 Word.word))" +definition update_SV39_PTE_bits :: " SV39_PTE \<Rightarrow>(64)Word.word \<Rightarrow> SV39_PTE " where + " update_SV39_PTE_bits v x = ( + (v (| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 63 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + :: 64 Word.word))|)))" + + +definition get_SV39_PTE_PPNi :: " SV39_PTE \<Rightarrow>(44)Word.word " where + " get_SV39_PTE_PPNi v = ( + (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 53 :: int)::ii) (( 10 :: int)::ii) :: 44 Word.word))" definition set_SV39_PTE_PPNi :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_SV39_PTE_PPNi r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_PTE) . - (let r = ((get_SV39_PTE w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 53 :: int)::ii) (( 10 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_SV39_PTE r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 r) (( 53 :: int)::ii) (( 10 :: int)::ii) + ((subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" -fun update_SV39_PTE_PPNi :: " SV39_PTE \<Rightarrow>(44)Word.word \<Rightarrow> SV39_PTE " where - " update_SV39_PTE_PPNi (Mk_SV39_PTE (v)) x = ( - Mk_SV39_PTE ((update_subrange_vec_dec v (( 53 :: int)::ii) (( 10 :: int)::ii) x :: 64 Word.word)))" +definition update_SV39_PTE_PPNi :: " SV39_PTE \<Rightarrow>(44)Word.word \<Rightarrow> SV39_PTE " where + " update_SV39_PTE_PPNi v x = ( + (v (| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 53 :: int)::ii) (( 10 :: int)::ii) + ((subrange_vec_dec x (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word)) + :: 64 Word.word))|)))" (*val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2*) -fun get_SV39_PTE_RSW :: " SV39_PTE \<Rightarrow>(2)Word.word " where - " get_SV39_PTE_RSW (Mk_SV39_PTE (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))" +definition get_SV39_PTE_RSW :: " SV39_PTE \<Rightarrow>(2)Word.word " where + " get_SV39_PTE_RSW v = ( (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))" (*val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit*) definition set_SV39_PTE_RSW :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_SV39_PTE_RSW r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_PTE) . - (let r = ((get_SV39_PTE w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_SV39_PTE r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 r) (( 9 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE*) -fun update_SV39_PTE_RSW :: " SV39_PTE \<Rightarrow>(2)Word.word \<Rightarrow> SV39_PTE " where - " update_SV39_PTE_RSW (Mk_SV39_PTE (v)) x = ( - Mk_SV39_PTE ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" +definition update_SV39_PTE_RSW :: " SV39_PTE \<Rightarrow>(2)Word.word \<Rightarrow> SV39_PTE " where + " update_SV39_PTE_RSW v x = ( + (v (| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 9 :: int)::ii) (( 8 :: int)::ii) + ((subrange_vec_dec x (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) + :: 64 Word.word))|)))" (*val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8*) -fun get_SV39_PTE_BITS :: " SV39_PTE \<Rightarrow>(8)Word.word " where - " get_SV39_PTE_BITS (Mk_SV39_PTE (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" +definition get_SV39_PTE_BITS :: " SV39_PTE \<Rightarrow>(8)Word.word " where + " get_SV39_PTE_BITS v = ( (subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" (*val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit*) definition set_SV39_PTE_BITS :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " set_SV39_PTE_BITS r_ref v = ( - reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_PTE) . - (let r = ((get_SV39_PTE w__0 :: 64 Word.word)) in - (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in - write_reg r_ref (Mk_SV39_PTE r)))))" + reg_deref r_ref \<bind> (\<lambda> r . + (let r = + ((r (| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 r) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word))|))) in + write_reg r_ref r)))" (*val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE*) -fun update_SV39_PTE_BITS :: " SV39_PTE \<Rightarrow>(8)Word.word \<Rightarrow> SV39_PTE " where - " update_SV39_PTE_BITS (Mk_SV39_PTE (v)) x = ( - Mk_SV39_PTE ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" +definition update_SV39_PTE_BITS :: " SV39_PTE \<Rightarrow>(8)Word.word \<Rightarrow> SV39_PTE " where + " update_SV39_PTE_BITS v x = ( + (v (| + SV39_PTE_SV39_PTE_chunk_0 := + ((update_subrange_vec_dec(SV39_PTE_SV39_PTE_chunk_0 v) (( 7 :: int)::ii) (( 0 :: int)::ii) + ((subrange_vec_dec x (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word))|)))" (*val curAsid64 : unit -> M (mword ty16)*) @@ -4977,10 +10149,24 @@ function (sequential,domintros) walk39 :: "(39)Word.word \<Rightarrow> AccessT :: 56 Word.word)) PTE39_LOG_SIZE :: 56 Word.word)) in (let pte_addr = ((add_vec ptb pt_ofs :: 56 Word.word)) in - (checked_mem_read Data ((EXTZ (( 64 :: int)::ii) pte_addr :: 64 Word.word)) (( 8 :: int)::ii) + (phys_mem_read Data ((EXTZ (( 64 :: int)::ii) pte_addr :: 64 Word.word)) (( 8 :: int)::ii) False False False :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__0 :: ( 64 Word.word) MemoryOpResult) . (case w__0 of - MemException (_) => return (PTW_Failure PTW_Access) + MemException (_) => + (let (_ :: unit) = + (print_endline + (((op@) (''walk39(vaddr='') + (((op@) ((string_of_bits vaddr)) + (((op@) ('' level='') + (((op@) ((stringFromInteger level)) + (((op@) ('' pt_base='') + (((op@) ((string_of_bits ptb)) + (((op@) ('' pt_ofs='') + (((op@) ((string_of_bits pt_ofs)) + (((op@) ('' pte_addr='') + (((op@) ((string_of_bits pte_addr)) + ('': invalid pte address'')))))))))))))))))))))) in + return (PTW_Failure PTW_Access)) | MemValue (v) => (let pte = (Mk_SV39_PTE v) in (let pbits = ((get_SV39_PTE_BITS pte :: 8 Word.word)) in @@ -5114,10 +10300,6 @@ definition flushTLB :: "((16)Word.word)option \<Rightarrow>((39)Word.word)optio write_reg tlb39_ref ent)))" -definition enable_dirty_update :: " bool " where - " enable_dirty_update = ( False )" - - (*val translate39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> ii -> M TR39_Result*) definition translate39 :: "(39)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> int \<Rightarrow>((register_value),(TR39_Result),(exception))monad " where @@ -5138,16 +10320,17 @@ definition translate39 :: "(39)Word.word \<Rightarrow> AccessType \<Rightarrow> :: 56 Word.word)) :: 56 Word.word))) | Some (pbits) => - if ((\<not> enable_dirty_update)) then return (TR39_Failure PTW_PTE_Update) + if ((\<not> ((plat_enable_dirty_update () )))) then return (TR39_Failure PTW_PTE_Update) else (let (n_ent :: TLB39_Entry) = ent in (let n_ent = ((n_ent (| TLB39_Entry_pte := - ((update_SV39_PTE_BITS(TLB39_Entry_pte ent) ((get_PTE_Bits pbits :: 8 Word.word))))|))) in + ((update_SV39_PTE_BITS(TLB39_Entry_pte ent) + ((get_PTE_Bits_bits pbits :: 8 Word.word))))|))) in (writeTLB39 idx n_ent \<then> checked_mem_write ((EXTZ (( 64 :: int)::ii)(TLB39_Entry_pteAddr ent) :: 64 Word.word)) (( 8 :: int)::ii) - ((get_SV39_PTE(TLB39_Entry_pte ent) :: 64 Word.word))) \<bind> (\<lambda> (w__2 :: unit + ((get_SV39_PTE_bits(TLB39_Entry_pte ent) :: 64 Word.word))) \<bind> (\<lambda> (w__2 :: unit MemoryOpResult) . (case w__2 of MemValue (_) => return () @@ -5165,16 +10348,16 @@ definition translate39 :: "(39)Word.word \<Rightarrow> AccessType \<Rightarrow> (case w__7 of PTW_Failure (f) => return (TR39_Failure f) | PTW_Success (pAddr,pte,pteAddr,level,global1) => - (case ((update_PTE_Bits (Mk_PTE_Bits ((get_SV39_PTE_BITS pte :: 8 Word.word))) ac)) of + (case ((update_PTE_Bits ((Mk_PTE_Bits ((get_SV39_PTE_BITS pte :: 8 Word.word)))) ac)) of None => addToTLB39 asid vAddr pAddr pte pteAddr level global1 \<then> return (TR39_Address pAddr) | Some (pbits) => - if ((\<not> enable_dirty_update)) then return (TR39_Failure PTW_PTE_Update) + if ((\<not> ((plat_enable_dirty_update () )))) then return (TR39_Failure PTW_PTE_Update) else (let (w_pte :: SV39_PTE) = - (update_SV39_PTE_BITS pte ((get_PTE_Bits pbits :: 8 Word.word))) in + (update_SV39_PTE_BITS pte ((get_PTE_Bits_bits pbits :: 8 Word.word))) in checked_mem_write ((EXTZ (( 64 :: int)::ii) pteAddr :: 64 Word.word)) (( 8 :: int)::ii) - ((get_SV39_PTE w_pte :: 64 Word.word)) \<bind> (\<lambda> (w__8 :: unit MemoryOpResult) . + ((get_SV39_PTE_bits w_pte :: 64 Word.word)) \<bind> (\<lambda> (w__8 :: unit MemoryOpResult) . (case w__8 of MemValue (_) => addToTLB39 asid vAddr pAddr w_pte pteAddr level global1 \<then> @@ -5199,7 +10382,7 @@ definition translationMode :: " Privilege \<Rightarrow>((register_value),(SATPM (case arch of Some (RV64) => (read_reg satp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . - (let (mbits :: satp_mode) = ((get_Satp64_Mode (Mk_Satp64 w__1) :: 4 Word.word)) in + (let (mbits :: satp_mode) = ((get_Satp64_Mode ((Mk_Satp64 w__1)) :: 4 Word.word)) in (case ((satpMode_of_bits RV64 mbits)) of Some (m) => return m | None => internal_error (''invalid RV64 translation mode in satp'') @@ -5248,10 +10431,659 @@ definition translateAddr :: "(64)Word.word \<Rightarrow> AccessType \<Rightarro (*val decodeCompressed : mword ty16 -> maybe ast*) -(*val execute : ast -> M unit*) +(*val execute : ast -> M bool*) (*val print_insn : ast -> string*) +(*val encdec_uop_forwards : uop -> mword ty7*) + +fun encdec_uop_forwards :: " uop \<Rightarrow>(7)Word.word " where + " encdec_uop_forwards RISCV_LUI = ( (vec_of_bits [B0,B1,B1,B0,B1,B1,B1] :: 7 Word.word))" +|" encdec_uop_forwards RISCV_AUIPC = ( (vec_of_bits [B0,B0,B1,B0,B1,B1,B1] :: 7 Word.word))" + + +(*val encdec_uop_backwards : mword ty7 -> uop*) + +definition encdec_uop_backwards :: "(7)Word.word \<Rightarrow> uop " where + " encdec_uop_backwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1] :: 7 Word.word)))) then RISCV_LUI + else RISCV_AUIPC))" + + +(*val encdec_uop_forwards_matches : uop -> bool*) + +fun encdec_uop_forwards_matches :: " uop \<Rightarrow> bool " where + " encdec_uop_forwards_matches RISCV_LUI = ( True )" +|" encdec_uop_forwards_matches RISCV_AUIPC = ( True )" + + +(*val encdec_uop_backwards_matches : mword ty7 -> bool*) + +definition encdec_uop_backwards_matches :: "(7)Word.word \<Rightarrow> bool " where + " encdec_uop_backwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1] :: 7 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1] :: 7 Word.word)))) then True + else False))" + + +(*val utype_mnemonic_forwards : uop -> string*) + +fun utype_mnemonic_forwards :: " uop \<Rightarrow> string " where + " utype_mnemonic_forwards RISCV_LUI = ( (''lui''))" +|" utype_mnemonic_forwards RISCV_AUIPC = ( (''auipc''))" + + +(*val utype_mnemonic_backwards : string -> uop*) + +definition utype_mnemonic_backwards :: " string \<Rightarrow> uop " where + " utype_mnemonic_backwards arg0 = ( + if(arg0 = (''lui'')) then RISCV_LUI else + (if(arg0 = (''auipc'')) then RISCV_AUIPC else undefined) )" + + +(*val utype_mnemonic_forwards_matches : uop -> bool*) + +fun utype_mnemonic_forwards_matches :: " uop \<Rightarrow> bool " where + " utype_mnemonic_forwards_matches RISCV_LUI = ( True )" +|" utype_mnemonic_forwards_matches RISCV_AUIPC = ( True )" + + +(*val utype_mnemonic_backwards_matches : string -> bool*) + +definition utype_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where + " utype_mnemonic_backwards_matches arg0 = ( + if(arg0 = (''lui'')) then True else + (if(arg0 = (''auipc'')) then True else False) )" + + +(*val utype_mnemonic_matches_prefix : string -> maybe ((uop * ii))*) + +definition utype_mnemonic_matches_prefix :: " string \<Rightarrow>(uop*int)option " where + " utype_mnemonic_matches_prefix arg0 = ( + (let stringappend_17140 = arg0 in + if (((((string_startswith stringappend_17140 (''lui''))) \<and> ( + (case ((string_drop stringappend_17140 ((string_length (''lui''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17140 ((string_length (''lui''))))) of + s0 => Some (RISCV_LUI, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17140 (''auipc''))) \<and> ( + (case ((string_drop stringappend_17140 ((string_length (''auipc''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17140 ((string_length (''auipc''))))) of + s0 => Some (RISCV_AUIPC, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val encdec_bop_forwards : bop -> mword ty3*) + +fun encdec_bop_forwards :: " bop \<Rightarrow>(3)Word.word " where + " encdec_bop_forwards RISCV_BEQ = ( (vec_of_bits [B0,B0,B0] :: 3 Word.word))" +|" encdec_bop_forwards RISCV_BNE = ( (vec_of_bits [B0,B0,B1] :: 3 Word.word))" +|" encdec_bop_forwards RISCV_BLT = ( (vec_of_bits [B1,B0,B0] :: 3 Word.word))" +|" encdec_bop_forwards RISCV_BGE = ( (vec_of_bits [B1,B0,B1] :: 3 Word.word))" +|" encdec_bop_forwards RISCV_BLTU = ( (vec_of_bits [B1,B1,B0] :: 3 Word.word))" +|" encdec_bop_forwards RISCV_BGEU = ( (vec_of_bits [B1,B1,B1] :: 3 Word.word))" + + +(*val encdec_bop_backwards : mword ty3 -> bop*) + +definition encdec_bop_backwards :: "(3)Word.word \<Rightarrow> bop " where + " encdec_bop_backwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then RISCV_BEQ + else if (((p00 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then RISCV_BNE + else if (((p00 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then RISCV_BLT + else if (((p00 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then RISCV_BGE + else if (((p00 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then RISCV_BLTU + else RISCV_BGEU))" + + +(*val encdec_bop_forwards_matches : bop -> bool*) + +fun encdec_bop_forwards_matches :: " bop \<Rightarrow> bool " where + " encdec_bop_forwards_matches RISCV_BEQ = ( True )" +|" encdec_bop_forwards_matches RISCV_BNE = ( True )" +|" encdec_bop_forwards_matches RISCV_BLT = ( True )" +|" encdec_bop_forwards_matches RISCV_BGE = ( True )" +|" encdec_bop_forwards_matches RISCV_BLTU = ( True )" +|" encdec_bop_forwards_matches RISCV_BGEU = ( True )" + + +(*val encdec_bop_backwards_matches : mword ty3 -> bool*) + +definition encdec_bop_backwards_matches :: "(3)Word.word \<Rightarrow> bool " where + " encdec_bop_backwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then True + else False))" + + +(*val btype_mnemonic_forwards : bop -> string*) + +fun btype_mnemonic_forwards :: " bop \<Rightarrow> string " where + " btype_mnemonic_forwards RISCV_BEQ = ( (''beq''))" +|" btype_mnemonic_forwards RISCV_BNE = ( (''bne''))" +|" btype_mnemonic_forwards RISCV_BLT = ( (''blt''))" +|" btype_mnemonic_forwards RISCV_BGE = ( (''bge''))" +|" btype_mnemonic_forwards RISCV_BLTU = ( (''bltu''))" +|" btype_mnemonic_forwards RISCV_BGEU = ( (''bgeu''))" + + +(*val btype_mnemonic_backwards : string -> bop*) + +definition btype_mnemonic_backwards :: " string \<Rightarrow> bop " where + " btype_mnemonic_backwards arg0 = ( + if(arg0 = (''beq'')) then RISCV_BEQ else + ( + if(arg0 = (''bne'')) then RISCV_BNE else + ( + if(arg0 = (''blt'')) then RISCV_BLT else + ( + if(arg0 = (''bge'')) then RISCV_BGE else + ( + if(arg0 = (''bltu'')) then RISCV_BLTU else + (if(arg0 = (''bgeu'')) then RISCV_BGEU else undefined))))) )" + + +(*val btype_mnemonic_forwards_matches : bop -> bool*) + +fun btype_mnemonic_forwards_matches :: " bop \<Rightarrow> bool " where + " btype_mnemonic_forwards_matches RISCV_BEQ = ( True )" +|" btype_mnemonic_forwards_matches RISCV_BNE = ( True )" +|" btype_mnemonic_forwards_matches RISCV_BLT = ( True )" +|" btype_mnemonic_forwards_matches RISCV_BGE = ( True )" +|" btype_mnemonic_forwards_matches RISCV_BLTU = ( True )" +|" btype_mnemonic_forwards_matches RISCV_BGEU = ( True )" + + +(*val btype_mnemonic_backwards_matches : string -> bool*) + +definition btype_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where + " btype_mnemonic_backwards_matches arg0 = ( + if(arg0 = (''beq'')) then True else + ( + if(arg0 = (''bne'')) then True else + ( + if(arg0 = (''blt'')) then True else + ( + if(arg0 = (''bge'')) then True else + ( + if(arg0 = (''bltu'')) then True else + (if(arg0 = (''bgeu'')) then True else False))))) )" + + +(*val btype_mnemonic_matches_prefix : string -> maybe ((bop * ii))*) + +definition btype_mnemonic_matches_prefix :: " string \<Rightarrow>(bop*int)option " where + " btype_mnemonic_matches_prefix arg0 = ( + (let stringappend_17080 = arg0 in + if (((((string_startswith stringappend_17080 (''beq''))) \<and> ( + (case ((string_drop stringappend_17080 ((string_length (''beq''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17080 ((string_length (''beq''))))) of + s0 => Some (RISCV_BEQ, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17080 (''bne''))) \<and> ( + (case ((string_drop stringappend_17080 ((string_length (''bne''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17080 ((string_length (''bne''))))) of + s0 => Some (RISCV_BNE, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17080 (''blt''))) \<and> ( + (case ((string_drop stringappend_17080 ((string_length (''blt''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17080 ((string_length (''blt''))))) of + s0 => Some (RISCV_BLT, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17080 (''bge''))) \<and> ( + (case ((string_drop stringappend_17080 ((string_length (''bge''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17080 ((string_length (''bge''))))) of + s0 => Some (RISCV_BGE, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17080 (''bltu''))) \<and> ( + (case ((string_drop stringappend_17080 ((string_length (''bltu''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17080 ((string_length (''bltu''))))) of + s0 => Some (RISCV_BLTU, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17080 (''bgeu''))) \<and> ( + (case ((string_drop stringappend_17080 ((string_length (''bgeu''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17080 ((string_length (''bgeu''))))) of + s0 => Some (RISCV_BGEU, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val encdec_iop_forwards : iop -> mword ty3*) + +fun encdec_iop_forwards :: " iop \<Rightarrow>(3)Word.word " where + " encdec_iop_forwards RISCV_ADDI = ( (vec_of_bits [B0,B0,B0] :: 3 Word.word))" +|" encdec_iop_forwards RISCV_SLTI = ( (vec_of_bits [B0,B1,B0] :: 3 Word.word))" +|" encdec_iop_forwards RISCV_SLTIU = ( (vec_of_bits [B0,B1,B1] :: 3 Word.word))" +|" encdec_iop_forwards RISCV_XORI = ( (vec_of_bits [B1,B0,B0] :: 3 Word.word))" +|" encdec_iop_forwards RISCV_ORI = ( (vec_of_bits [B1,B1,B0] :: 3 Word.word))" +|" encdec_iop_forwards RISCV_ANDI = ( (vec_of_bits [B1,B1,B1] :: 3 Word.word))" + + +(*val encdec_iop_backwards : mword ty3 -> iop*) + +definition encdec_iop_backwards :: "(3)Word.word \<Rightarrow> iop " where + " encdec_iop_backwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then RISCV_ADDI + else if (((p00 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then RISCV_SLTI + else if (((p00 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then RISCV_SLTIU + else if (((p00 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then RISCV_XORI + else if (((p00 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then RISCV_ORI + else RISCV_ANDI))" + + +(*val encdec_iop_forwards_matches : iop -> bool*) + +fun encdec_iop_forwards_matches :: " iop \<Rightarrow> bool " where + " encdec_iop_forwards_matches RISCV_ADDI = ( True )" +|" encdec_iop_forwards_matches RISCV_SLTI = ( True )" +|" encdec_iop_forwards_matches RISCV_SLTIU = ( True )" +|" encdec_iop_forwards_matches RISCV_XORI = ( True )" +|" encdec_iop_forwards_matches RISCV_ORI = ( True )" +|" encdec_iop_forwards_matches RISCV_ANDI = ( True )" + + +(*val encdec_iop_backwards_matches : mword ty3 -> bool*) + +definition encdec_iop_backwards_matches :: "(3)Word.word \<Rightarrow> bool " where + " encdec_iop_backwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) then True + else False))" + + +(*val itype_mnemonic_forwards : iop -> string*) + +fun itype_mnemonic_forwards :: " iop \<Rightarrow> string " where + " itype_mnemonic_forwards RISCV_ADDI = ( (''addi''))" +|" itype_mnemonic_forwards RISCV_SLTI = ( (''slti''))" +|" itype_mnemonic_forwards RISCV_SLTIU = ( (''sltiu''))" +|" itype_mnemonic_forwards RISCV_XORI = ( (''xori''))" +|" itype_mnemonic_forwards RISCV_ORI = ( (''ori''))" +|" itype_mnemonic_forwards RISCV_ANDI = ( (''andi''))" + + +(*val itype_mnemonic_backwards : string -> iop*) + +definition itype_mnemonic_backwards :: " string \<Rightarrow> iop " where + " itype_mnemonic_backwards arg0 = ( + if(arg0 = (''addi'')) then RISCV_ADDI else + ( + if(arg0 = (''slti'')) then RISCV_SLTI else + ( + if(arg0 = (''sltiu'')) then RISCV_SLTIU else + ( + if(arg0 = (''xori'')) then RISCV_XORI else + ( + if(arg0 = (''ori'')) then RISCV_ORI else + (if(arg0 = (''andi'')) then RISCV_ANDI else undefined))))) )" + + +(*val itype_mnemonic_forwards_matches : iop -> bool*) + +fun itype_mnemonic_forwards_matches :: " iop \<Rightarrow> bool " where + " itype_mnemonic_forwards_matches RISCV_ADDI = ( True )" +|" itype_mnemonic_forwards_matches RISCV_SLTI = ( True )" +|" itype_mnemonic_forwards_matches RISCV_SLTIU = ( True )" +|" itype_mnemonic_forwards_matches RISCV_XORI = ( True )" +|" itype_mnemonic_forwards_matches RISCV_ORI = ( True )" +|" itype_mnemonic_forwards_matches RISCV_ANDI = ( True )" + + +(*val itype_mnemonic_backwards_matches : string -> bool*) + +definition itype_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where + " itype_mnemonic_backwards_matches arg0 = ( + if(arg0 = (''addi'')) then True else + ( + if(arg0 = (''slti'')) then True else + ( + if(arg0 = (''sltiu'')) then True else + ( + if(arg0 = (''xori'')) then True else + ( + if(arg0 = (''ori'')) then True else + (if(arg0 = (''andi'')) then True else False))))) )" + + +(*val itype_mnemonic_matches_prefix : string -> maybe ((iop * ii))*) + +definition itype_mnemonic_matches_prefix :: " string \<Rightarrow>(iop*int)option " where + " itype_mnemonic_matches_prefix arg0 = ( + (let stringappend_17020 = arg0 in + if (((((string_startswith stringappend_17020 (''addi''))) \<and> ( + (case ((string_drop stringappend_17020 ((string_length (''addi''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17020 ((string_length (''addi''))))) of + s0 => Some (RISCV_ADDI, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17020 (''slti''))) \<and> ( + (case ((string_drop stringappend_17020 ((string_length (''slti''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17020 ((string_length (''slti''))))) of + s0 => Some (RISCV_SLTI, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17020 (''sltiu''))) \<and> ( + (case ((string_drop stringappend_17020 ((string_length (''sltiu''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17020 ((string_length (''sltiu''))))) of + s0 => Some (RISCV_SLTIU, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17020 (''xori''))) \<and> ( + (case ((string_drop stringappend_17020 ((string_length (''xori''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17020 ((string_length (''xori''))))) of + s0 => Some (RISCV_XORI, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17020 (''ori''))) \<and> ( + (case ((string_drop stringappend_17020 ((string_length (''ori''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17020 ((string_length (''ori''))))) of + s0 => Some (RISCV_ORI, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_17020 (''andi''))) \<and> ( + (case ((string_drop stringappend_17020 ((string_length (''andi''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_17020 ((string_length (''andi''))))) of + s0 => Some (RISCV_ANDI, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val encdec_sop_forwards : sop -> mword ty3*) + +fun encdec_sop_forwards :: " sop \<Rightarrow>(3)Word.word " where + " encdec_sop_forwards RISCV_SLLI = ( (vec_of_bits [B0,B0,B1] :: 3 Word.word))" +|" encdec_sop_forwards RISCV_SRLI = ( (vec_of_bits [B1,B0,B1] :: 3 Word.word))" +|" encdec_sop_forwards RISCV_SRAI = ( (vec_of_bits [B1,B0,B1] :: 3 Word.word))" + + +(*val encdec_sop_backwards : mword ty3 -> sop*) + +definition encdec_sop_backwards :: "(3)Word.word \<Rightarrow> sop " where + " encdec_sop_backwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then RISCV_SLLI + else if (((p00 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then RISCV_SRLI + else RISCV_SRAI))" + + +(*val encdec_sop_forwards_matches : sop -> bool*) + +fun encdec_sop_forwards_matches :: " sop \<Rightarrow> bool " where + " encdec_sop_forwards_matches RISCV_SLLI = ( True )" +|" encdec_sop_forwards_matches RISCV_SRLI = ( True )" +|" encdec_sop_forwards_matches RISCV_SRAI = ( True )" + + +(*val encdec_sop_backwards_matches : mword ty3 -> bool*) + +definition encdec_sop_backwards_matches :: "(3)Word.word \<Rightarrow> bool " where + " encdec_sop_backwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then True + else False))" + + +(*val shiftiop_mnemonic_forwards : sop -> string*) + +fun shiftiop_mnemonic_forwards :: " sop \<Rightarrow> string " where + " shiftiop_mnemonic_forwards RISCV_SLLI = ( (''slli''))" +|" shiftiop_mnemonic_forwards RISCV_SRLI = ( (''srli''))" +|" shiftiop_mnemonic_forwards RISCV_SRAI = ( (''srai''))" + + +(*val shiftiop_mnemonic_backwards : string -> sop*) + +definition shiftiop_mnemonic_backwards :: " string \<Rightarrow> sop " where + " shiftiop_mnemonic_backwards arg0 = ( + if(arg0 = (''slli'')) then RISCV_SLLI else + ( + if(arg0 = (''srli'')) then RISCV_SRLI else + (if(arg0 = (''srai'')) then RISCV_SRAI else undefined)) )" + + +(*val shiftiop_mnemonic_forwards_matches : sop -> bool*) + +fun shiftiop_mnemonic_forwards_matches :: " sop \<Rightarrow> bool " where + " shiftiop_mnemonic_forwards_matches RISCV_SLLI = ( True )" +|" shiftiop_mnemonic_forwards_matches RISCV_SRLI = ( True )" +|" shiftiop_mnemonic_forwards_matches RISCV_SRAI = ( True )" + + +(*val shiftiop_mnemonic_backwards_matches : string -> bool*) + +definition shiftiop_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where + " shiftiop_mnemonic_backwards_matches arg0 = ( + if(arg0 = (''slli'')) then True else + ( + if(arg0 = (''srli'')) then True else + (if(arg0 = (''srai'')) then True else False)) )" + + +(*val shiftiop_mnemonic_matches_prefix : string -> maybe ((sop * ii))*) + +definition shiftiop_mnemonic_matches_prefix :: " string \<Rightarrow>(sop*int)option " where + " shiftiop_mnemonic_matches_prefix arg0 = ( + (let stringappend_16990 = arg0 in + if (((((string_startswith stringappend_16990 (''slli''))) \<and> ( + (case ((string_drop stringappend_16990 ((string_length (''slli''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16990 ((string_length (''slli''))))) of + s0 => Some (RISCV_SLLI, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16990 (''srli''))) \<and> ( + (case ((string_drop stringappend_16990 ((string_length (''srli''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16990 ((string_length (''srli''))))) of + s0 => Some (RISCV_SRLI, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16990 (''srai''))) \<and> ( + (case ((string_drop stringappend_16990 ((string_length (''srai''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16990 ((string_length (''srai''))))) of + s0 => Some (RISCV_SRAI, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val rtype_mnemonic_forwards : rop -> string*) + +fun rtype_mnemonic_forwards :: " rop \<Rightarrow> string " where + " rtype_mnemonic_forwards RISCV_ADD = ( (''add''))" +|" rtype_mnemonic_forwards RISCV_SUB = ( (''sub''))" +|" rtype_mnemonic_forwards RISCV_SLL = ( (''sll''))" +|" rtype_mnemonic_forwards RISCV_SLT = ( (''slt''))" +|" rtype_mnemonic_forwards RISCV_SLTU = ( (''sltu''))" +|" rtype_mnemonic_forwards RISCV_XOR = ( (''xor''))" +|" rtype_mnemonic_forwards RISCV_SRL = ( (''srl''))" +|" rtype_mnemonic_forwards RISCV_SRA = ( (''sra''))" +|" rtype_mnemonic_forwards RISCV_OR = ( (''or''))" +|" rtype_mnemonic_forwards RISCV_AND = ( (''and''))" + + +(*val rtype_mnemonic_backwards : string -> rop*) + +definition rtype_mnemonic_backwards :: " string \<Rightarrow> rop " where + " rtype_mnemonic_backwards arg0 = ( + if(arg0 = (''add'')) then RISCV_ADD else + ( + if(arg0 = (''sub'')) then RISCV_SUB else + ( + if(arg0 = (''sll'')) then RISCV_SLL else + ( + if(arg0 = (''slt'')) then RISCV_SLT else + ( + if(arg0 = (''sltu'')) then RISCV_SLTU else + ( + if(arg0 = (''xor'')) then RISCV_XOR else + ( + if(arg0 = (''srl'')) then RISCV_SRL else + ( + if(arg0 = (''sra'')) then RISCV_SRA else + ( + if(arg0 = (''or'')) then RISCV_OR else + (if(arg0 = (''and'')) then RISCV_AND else undefined))))))))) )" + + +(*val rtype_mnemonic_forwards_matches : rop -> bool*) + +fun rtype_mnemonic_forwards_matches :: " rop \<Rightarrow> bool " where + " rtype_mnemonic_forwards_matches RISCV_ADD = ( True )" +|" rtype_mnemonic_forwards_matches RISCV_SUB = ( True )" +|" rtype_mnemonic_forwards_matches RISCV_SLL = ( True )" +|" rtype_mnemonic_forwards_matches RISCV_SLT = ( True )" +|" rtype_mnemonic_forwards_matches RISCV_SLTU = ( True )" +|" rtype_mnemonic_forwards_matches RISCV_XOR = ( True )" +|" rtype_mnemonic_forwards_matches RISCV_SRL = ( True )" +|" rtype_mnemonic_forwards_matches RISCV_SRA = ( True )" +|" rtype_mnemonic_forwards_matches RISCV_OR = ( True )" +|" rtype_mnemonic_forwards_matches RISCV_AND = ( True )" + + +(*val rtype_mnemonic_backwards_matches : string -> bool*) + +definition rtype_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where + " rtype_mnemonic_backwards_matches arg0 = ( + if(arg0 = (''add'')) then True else + ( + if(arg0 = (''sub'')) then True else + ( + if(arg0 = (''sll'')) then True else + ( + if(arg0 = (''slt'')) then True else + ( + if(arg0 = (''sltu'')) then True else + ( + if(arg0 = (''xor'')) then True else + ( + if(arg0 = (''srl'')) then True else + ( + if(arg0 = (''sra'')) then True else + ( + if(arg0 = (''or'')) then True else + (if(arg0 = (''and'')) then True else False))))))))) )" + + +(*val rtype_mnemonic_matches_prefix : string -> maybe ((rop * ii))*) + +definition rtype_mnemonic_matches_prefix :: " string \<Rightarrow>(rop*int)option " where + " rtype_mnemonic_matches_prefix arg0 = ( + (let stringappend_16890 = arg0 in + if (((((string_startswith stringappend_16890 (''add''))) \<and> ( + (case ((string_drop stringappend_16890 ((string_length (''add''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16890 ((string_length (''add''))))) of + s0 => Some (RISCV_ADD, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16890 (''sub''))) \<and> ( + (case ((string_drop stringappend_16890 ((string_length (''sub''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16890 ((string_length (''sub''))))) of + s0 => Some (RISCV_SUB, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16890 (''sll''))) \<and> ( + (case ((string_drop stringappend_16890 ((string_length (''sll''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16890 ((string_length (''sll''))))) of + s0 => Some (RISCV_SLL, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16890 (''slt''))) \<and> ( + (case ((string_drop stringappend_16890 ((string_length (''slt''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16890 ((string_length (''slt''))))) of + s0 => Some (RISCV_SLT, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16890 (''sltu''))) \<and> ( + (case ((string_drop stringappend_16890 ((string_length (''sltu''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16890 ((string_length (''sltu''))))) of + s0 => Some (RISCV_SLTU, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16890 (''xor''))) \<and> ( + (case ((string_drop stringappend_16890 ((string_length (''xor''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16890 ((string_length (''xor''))))) of + s0 => Some (RISCV_XOR, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16890 (''srl''))) \<and> ( + (case ((string_drop stringappend_16890 ((string_length (''srl''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16890 ((string_length (''srl''))))) of + s0 => Some (RISCV_SRL, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16890 (''sra''))) \<and> ( + (case ((string_drop stringappend_16890 ((string_length (''sra''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16890 ((string_length (''sra''))))) of + s0 => Some (RISCV_SRA, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16890 (''or''))) \<and> ( + (case ((string_drop stringappend_16890 ((string_length (''or''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16890 ((string_length (''or''))))) of + s0 => Some (RISCV_OR, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16890 (''and''))) \<and> ( + (case ((string_drop stringappend_16890 ((string_length (''and''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16890 ((string_length (''and''))))) of + s0 => Some (RISCV_AND, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + (*val extend_value : forall 'int8_times_n . Size 'int8_times_n => bool -> MemoryOpResult (mword 'int8_times_n) -> MemoryOpResult (mword ty64)*) fun extend_value :: " bool \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow>((64)Word.word)MemoryOpResult " where @@ -5261,97 +11093,1344 @@ fun extend_value :: " bool \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOp |" extend_value is_unsigned (MemException (e)) = ( MemException e )" -(*val process_load : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M unit*) +(*val process_load : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M bool*) -definition process_load :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where +definition process_load :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where " process_load rd addr value1 is_unsigned = ( (case ((extend_value is_unsigned value1 :: ( 64 Word.word) MemoryOpResult)) of - MemValue (result) => wX ((regbits_to_regno rd)) result - | MemException (e) => handle_mem_exception addr e + MemValue (result) => wX ((regbits_to_regno rd)) result \<then> return True + | MemException (e) => handle_mem_exception addr e \<then> return False ))" -(*val process_loadres : forall 'int8_times_n . regbits -> xlenbits -> MemoryOpResult (bits 'int8_times_n) -> bool -> unit*) +(*val check_misaligned : mword ty64 -> word_width -> bool*) + +definition check_misaligned :: "(64)Word.word \<Rightarrow> word_width \<Rightarrow> bool " where + " check_misaligned (vaddr :: xlenbits) (width :: word_width) = ( + if ((plat_enable_misaligned_access () )) then False + else + (case width of + BYTE => False + | HALF => + (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii))) :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))) + | WORD => + ((((((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii))) :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> (((((cast_unit_vec0 ((access_vec_dec vaddr (( 1 :: int)::ii))) :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))) + | DOUBLE => + ((((((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii))) :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((cast_unit_vec0 ((access_vec_dec vaddr (( 1 :: int)::ii))) :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> (((((cast_unit_vec0 ((access_vec_dec vaddr (( 2 :: int)::ii))) :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))))) + ))" + + +(*val maybe_aq_forwards : bool -> string*) + +fun maybe_aq_forwards :: " bool \<Rightarrow> string " where + " maybe_aq_forwards True = ( (''.aq''))" +|" maybe_aq_forwards False = ( (''''))" + + +(*val maybe_aq_backwards : string -> bool*) + +definition maybe_aq_backwards :: " string \<Rightarrow> bool " where + " maybe_aq_backwards arg0 = ( + if(arg0 = (''.aq'')) then True else + (if(arg0 = ('''')) then False else undefined) )" + + +(*val maybe_aq_forwards_matches : bool -> bool*) + +fun maybe_aq_forwards_matches :: " bool \<Rightarrow> bool " where + " maybe_aq_forwards_matches True = ( True )" +|" maybe_aq_forwards_matches False = ( True )" + + +(*val maybe_aq_backwards_matches : string -> bool*) + +definition maybe_aq_backwards_matches :: " string \<Rightarrow> bool " where + " maybe_aq_backwards_matches arg0 = ( + if(arg0 = (''.aq'')) then True else (if(arg0 = ('''')) then True else False) )" + + +(*val maybe_aq_matches_prefix : string -> maybe ((bool * ii))*) + +definition maybe_aq_matches_prefix :: " string \<Rightarrow>(bool*int)option " where + " maybe_aq_matches_prefix arg0 = ( + (let stringappend_16870 = arg0 in + if (((((string_startswith stringappend_16870 (''.aq''))) \<and> ( + (case ((string_drop stringappend_16870 ((string_length (''.aq''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16870 ((string_length (''.aq''))))) of + s0 => Some (True, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16870 (''''))) \<and> ( + (case ((string_drop stringappend_16870 ((string_length (''''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16870 ((string_length (''''))))) of + s0 => Some (False, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val maybe_rl_forwards : bool -> string*) + +fun maybe_rl_forwards :: " bool \<Rightarrow> string " where + " maybe_rl_forwards True = ( (''.rl''))" +|" maybe_rl_forwards False = ( (''''))" + + +(*val maybe_rl_backwards : string -> bool*) + +definition maybe_rl_backwards :: " string \<Rightarrow> bool " where + " maybe_rl_backwards arg0 = ( + if(arg0 = (''.rl'')) then True else + (if(arg0 = ('''')) then False else undefined) )" + + +(*val maybe_rl_forwards_matches : bool -> bool*) + +fun maybe_rl_forwards_matches :: " bool \<Rightarrow> bool " where + " maybe_rl_forwards_matches True = ( True )" +|" maybe_rl_forwards_matches False = ( True )" + + +(*val maybe_rl_backwards_matches : string -> bool*) + +definition maybe_rl_backwards_matches :: " string \<Rightarrow> bool " where + " maybe_rl_backwards_matches arg0 = ( + if(arg0 = (''.rl'')) then True else (if(arg0 = ('''')) then True else False) )" + + +(*val maybe_rl_matches_prefix : string -> maybe ((bool * ii))*) + +definition maybe_rl_matches_prefix :: " string \<Rightarrow>(bool*int)option " where + " maybe_rl_matches_prefix arg0 = ( + (let stringappend_16850 = arg0 in + if (((((string_startswith stringappend_16850 (''.rl''))) \<and> ( + (case ((string_drop stringappend_16850 ((string_length (''.rl''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16850 ((string_length (''.rl''))))) of + s0 => Some (True, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16850 (''''))) \<and> ( + (case ((string_drop stringappend_16850 ((string_length (''''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16850 ((string_length (''''))))) of + s0 => Some (False, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val maybe_u_forwards : bool -> string*) + +fun maybe_u_forwards :: " bool \<Rightarrow> string " where + " maybe_u_forwards True = ( (''u''))" +|" maybe_u_forwards False = ( (''''))" + + +(*val maybe_u_backwards : string -> bool*) + +definition maybe_u_backwards :: " string \<Rightarrow> bool " where + " maybe_u_backwards arg0 = ( + if(arg0 = (''u'')) then True else + (if(arg0 = ('''')) then False else undefined) )" + + +(*val maybe_u_forwards_matches : bool -> bool*) + +fun maybe_u_forwards_matches :: " bool \<Rightarrow> bool " where + " maybe_u_forwards_matches True = ( True )" +|" maybe_u_forwards_matches False = ( True )" + + +(*val maybe_u_backwards_matches : string -> bool*) + +definition maybe_u_backwards_matches :: " string \<Rightarrow> bool " where + " maybe_u_backwards_matches arg0 = ( + if(arg0 = (''u'')) then True else (if(arg0 = ('''')) then True else False) )" + + +(*val maybe_u_matches_prefix : string -> maybe ((bool * ii))*) + +definition maybe_u_matches_prefix :: " string \<Rightarrow>(bool*int)option " where + " maybe_u_matches_prefix arg0 = ( + (let stringappend_16830 = arg0 in + if (((((string_startswith stringappend_16830 (''u''))) \<and> ( + (case ((string_drop stringappend_16830 ((string_length (''u''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16830 ((string_length (''u''))))) of + s0 => Some (True, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16830 (''''))) \<and> ( + (case ((string_drop stringappend_16830 ((string_length (''''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16830 ((string_length (''''))))) of + s0 => Some (False, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val shiftw_mnemonic_forwards : sop -> string*) + +fun shiftw_mnemonic_forwards :: " sop \<Rightarrow> string " where + " shiftw_mnemonic_forwards RISCV_SLLI = ( (''slli''))" +|" shiftw_mnemonic_forwards RISCV_SRLI = ( (''srli''))" +|" shiftw_mnemonic_forwards RISCV_SRAI = ( (''srai''))" + + +(*val shiftw_mnemonic_backwards : string -> sop*) + +definition shiftw_mnemonic_backwards :: " string \<Rightarrow> sop " where + " shiftw_mnemonic_backwards arg0 = ( + if(arg0 = (''slli'')) then RISCV_SLLI else + ( + if(arg0 = (''srli'')) then RISCV_SRLI else + (if(arg0 = (''srai'')) then RISCV_SRAI else undefined)) )" + + +(*val shiftw_mnemonic_forwards_matches : sop -> bool*) + +fun shiftw_mnemonic_forwards_matches :: " sop \<Rightarrow> bool " where + " shiftw_mnemonic_forwards_matches RISCV_SLLI = ( True )" +|" shiftw_mnemonic_forwards_matches RISCV_SRLI = ( True )" +|" shiftw_mnemonic_forwards_matches RISCV_SRAI = ( True )" + + +(*val shiftw_mnemonic_backwards_matches : string -> bool*) + +definition shiftw_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where + " shiftw_mnemonic_backwards_matches arg0 = ( + if(arg0 = (''slli'')) then True else + ( + if(arg0 = (''srli'')) then True else + (if(arg0 = (''srai'')) then True else False)) )" + + +(*val shiftw_mnemonic_matches_prefix : string -> maybe ((sop * ii))*) + +definition shiftw_mnemonic_matches_prefix :: " string \<Rightarrow>(sop*int)option " where + " shiftw_mnemonic_matches_prefix arg0 = ( + (let stringappend_16800 = arg0 in + if (((((string_startswith stringappend_16800 (''slli''))) \<and> ( + (case ((string_drop stringappend_16800 ((string_length (''slli''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16800 ((string_length (''slli''))))) of + s0 => Some (RISCV_SLLI, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16800 (''srli''))) \<and> ( + (case ((string_drop stringappend_16800 ((string_length (''srli''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16800 ((string_length (''srli''))))) of + s0 => Some (RISCV_SRLI, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16800 (''srai''))) \<and> ( + (case ((string_drop stringappend_16800 ((string_length (''srai''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16800 ((string_length (''srai''))))) of + s0 => Some (RISCV_SRAI, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val rtypew_mnemonic_forwards : ropw -> string*) + +fun rtypew_mnemonic_forwards :: " ropw \<Rightarrow> string " where + " rtypew_mnemonic_forwards RISCV_ADDW = ( (''addw''))" +|" rtypew_mnemonic_forwards RISCV_SUBW = ( (''subw''))" +|" rtypew_mnemonic_forwards RISCV_SLLW = ( (''sllw''))" +|" rtypew_mnemonic_forwards RISCV_SRLW = ( (''srlw''))" +|" rtypew_mnemonic_forwards RISCV_SRAW = ( (''sraw''))" + + +(*val rtypew_mnemonic_backwards : string -> ropw*) + +definition rtypew_mnemonic_backwards :: " string \<Rightarrow> ropw " where + " rtypew_mnemonic_backwards arg0 = ( + if(arg0 = (''addw'')) then RISCV_ADDW else + ( + if(arg0 = (''subw'')) then RISCV_SUBW else + ( + if(arg0 = (''sllw'')) then RISCV_SLLW else + ( + if(arg0 = (''srlw'')) then RISCV_SRLW else + (if(arg0 = (''sraw'')) then RISCV_SRAW else undefined)))) )" + + +(*val rtypew_mnemonic_forwards_matches : ropw -> bool*) + +fun rtypew_mnemonic_forwards_matches :: " ropw \<Rightarrow> bool " where + " rtypew_mnemonic_forwards_matches RISCV_ADDW = ( True )" +|" rtypew_mnemonic_forwards_matches RISCV_SUBW = ( True )" +|" rtypew_mnemonic_forwards_matches RISCV_SLLW = ( True )" +|" rtypew_mnemonic_forwards_matches RISCV_SRLW = ( True )" +|" rtypew_mnemonic_forwards_matches RISCV_SRAW = ( True )" + + +(*val rtypew_mnemonic_backwards_matches : string -> bool*) + +definition rtypew_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where + " rtypew_mnemonic_backwards_matches arg0 = ( + if(arg0 = (''addw'')) then True else + ( + if(arg0 = (''subw'')) then True else + ( + if(arg0 = (''sllw'')) then True else + ( + if(arg0 = (''srlw'')) then True else + (if(arg0 = (''sraw'')) then True else False)))) )" + + +(*val rtypew_mnemonic_matches_prefix : string -> maybe ((ropw * ii))*) + +definition rtypew_mnemonic_matches_prefix :: " string \<Rightarrow>(ropw*int)option " where + " rtypew_mnemonic_matches_prefix arg0 = ( + (let stringappend_16750 = arg0 in + if (((((string_startswith stringappend_16750 (''addw''))) \<and> ( + (case ((string_drop stringappend_16750 ((string_length (''addw''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16750 ((string_length (''addw''))))) of + s0 => Some (RISCV_ADDW, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16750 (''subw''))) \<and> ( + (case ((string_drop stringappend_16750 ((string_length (''subw''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16750 ((string_length (''subw''))))) of + s0 => Some (RISCV_SUBW, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16750 (''sllw''))) \<and> ( + (case ((string_drop stringappend_16750 ((string_length (''sllw''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16750 ((string_length (''sllw''))))) of + s0 => Some (RISCV_SLLW, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16750 (''srlw''))) \<and> ( + (case ((string_drop stringappend_16750 ((string_length (''srlw''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16750 ((string_length (''srlw''))))) of + s0 => Some (RISCV_SRLW, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16750 (''sraw''))) \<and> ( + (case ((string_drop stringappend_16750 ((string_length (''sraw''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16750 ((string_length (''sraw''))))) of + s0 => Some (RISCV_SRAW, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val encdec_mul_op_forwards : bool -> bool -> bool -> mword ty3*) + +definition encdec_mul_op_forwards :: " bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(3)Word.word " where + " encdec_mul_op_forwards arg0 arg1 arg2 = ( + (let arg0 = (arg0, arg1, arg2) in + (case arg0 of + (False, True, True) => (vec_of_bits [B0,B0,B0] :: 3 Word.word) + | (True, True, True) => (vec_of_bits [B0,B0,B1] :: 3 Word.word) + | (True, True, False) => (vec_of_bits [B0,B1,B0] :: 3 Word.word) + | (True, False, False) => (vec_of_bits [B0,B1,B1] :: 3 Word.word) + )))" + + +(*val encdec_mul_op_backwards : mword ty3 -> (bool * bool * bool)*) + +definition encdec_mul_op_backwards :: "(3)Word.word \<Rightarrow> bool*bool*bool " where + " encdec_mul_op_backwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then (False, True, True) + else if (((p00 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then (True, True, True) + else if (((p00 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then (True, True, False) + else (True, False, False)))" + + +(*val encdec_mul_op_forwards_matches : bool -> bool -> bool -> bool*) + +definition encdec_mul_op_forwards_matches :: " bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool " where + " encdec_mul_op_forwards_matches arg0 arg1 arg2 = ( + (let arg0 = (arg0, arg1, arg2) in + (case arg0 of + (False, True, True) => True + | (True, True, True) => True + | (True, True, False) => True + | (True, False, False) => True + | _ => False + )))" + + +(*val encdec_mul_op_backwards_matches : mword ty3 -> bool*) + +definition encdec_mul_op_backwards_matches :: "(3)Word.word \<Rightarrow> bool " where + " encdec_mul_op_backwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then True + else False))" + + +(*val mul_mnemonic_forwards : bool -> bool -> bool -> string*) + +definition mul_mnemonic_forwards :: " bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> string " where + " mul_mnemonic_forwards arg0 arg1 arg2 = ( + (let arg0 = (arg0, arg1, arg2) in + (case arg0 of + (False, True, True) => (''mul'') + | (True, True, True) => (''mulh'') + | (True, True, False) => (''mulhsu'') + | (True, False, False) => (''mulhu'') + )))" + + +(*val mul_mnemonic_backwards : string -> (bool * bool * bool)*) + +definition mul_mnemonic_backwards :: " string \<Rightarrow> bool*bool*bool " where + " mul_mnemonic_backwards arg0 = ( + if(arg0 = (''mul'')) then (False, True, True) else + ( + if(arg0 = (''mulh'')) then (True, True, True) else + ( + if(arg0 = (''mulhsu'')) then (True, True, False) else + (if(arg0 = (''mulhu'')) then (True, False, False) else undefined))) )" + + +(*val mul_mnemonic_forwards_matches : bool -> bool -> bool -> bool*) + +definition mul_mnemonic_forwards_matches :: " bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool " where + " mul_mnemonic_forwards_matches arg0 arg1 arg2 = ( + (let arg0 = (arg0, arg1, arg2) in + (case arg0 of + (False, True, True) => True + | (True, True, True) => True + | (True, True, False) => True + | (True, False, False) => True + | _ => False + )))" + + +(*val mul_mnemonic_backwards_matches : string -> bool*) + +definition mul_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where + " mul_mnemonic_backwards_matches arg0 = ( + if(arg0 = (''mul'')) then True else + ( + if(arg0 = (''mulh'')) then True else + ( + if(arg0 = (''mulhsu'')) then True else + (if(arg0 = (''mulhu'')) then True else False))) )" + + +(*val mul_mnemonic_matches_prefix : string -> maybe (((bool * bool * bool) * ii))*) + +definition mul_mnemonic_matches_prefix :: " string \<Rightarrow>((bool*bool*bool)*int)option " where + " mul_mnemonic_matches_prefix arg0 = ( + (let stringappend_16710 = arg0 in + if (((((string_startswith stringappend_16710 (''mul''))) \<and> ( + (case ((string_drop stringappend_16710 ((string_length (''mul''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16710 ((string_length (''mul''))))) of + s0 => Some ((False, True, True), ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16710 (''mulh''))) \<and> ( + (case ((string_drop stringappend_16710 ((string_length (''mulh''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16710 ((string_length (''mulh''))))) of + s0 => Some ((True, True, True), ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16710 (''mulhsu''))) \<and> ( + (case ((string_drop stringappend_16710 ((string_length (''mulhsu''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16710 ((string_length (''mulhsu''))))) of + s0 => Some ((True, True, False), ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16710 (''mulhu''))) \<and> ( + (case ((string_drop stringappend_16710 ((string_length (''mulhu''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16710 ((string_length (''mulhu''))))) of + s0 => Some ((True, False, False), ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val maybe_not_u_forwards : bool -> string*) + +fun maybe_not_u_forwards :: " bool \<Rightarrow> string " where + " maybe_not_u_forwards False = ( (''u''))" +|" maybe_not_u_forwards True = ( (''''))" + + +(*val maybe_not_u_backwards : string -> bool*) + +definition maybe_not_u_backwards :: " string \<Rightarrow> bool " where + " maybe_not_u_backwards arg0 = ( + if(arg0 = (''u'')) then False else + (if(arg0 = ('''')) then True else undefined) )" + + +(*val maybe_not_u_forwards_matches : bool -> bool*) + +fun maybe_not_u_forwards_matches :: " bool \<Rightarrow> bool " where + " maybe_not_u_forwards_matches False = ( True )" +|" maybe_not_u_forwards_matches True = ( True )" + + +(*val maybe_not_u_backwards_matches : string -> bool*) + +definition maybe_not_u_backwards_matches :: " string \<Rightarrow> bool " where + " maybe_not_u_backwards_matches arg0 = ( + if(arg0 = (''u'')) then True else (if(arg0 = ('''')) then True else False) )" + + +(*val maybe_not_u_matches_prefix : string -> maybe ((bool * ii))*) + +definition maybe_not_u_matches_prefix :: " string \<Rightarrow>(bool*int)option " where + " maybe_not_u_matches_prefix arg0 = ( + (let stringappend_16690 = arg0 in + if (((((string_startswith stringappend_16690 (''u''))) \<and> ( + (case ((string_drop stringappend_16690 ((string_length (''u''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16690 ((string_length (''u''))))) of + s0 => Some (False, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16690 (''''))) \<and> ( + (case ((string_drop stringappend_16690 ((string_length (''''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16690 ((string_length (''''))))) of + s0 => Some (True, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val bit_maybe_r_forwards : mword ty1 -> string*) + +definition bit_maybe_r_forwards :: "(1)Word.word \<Rightarrow> string " where + " bit_maybe_r_forwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B1] :: 1 Word.word)))) then (''r'') + else ('''')))" + + +(*val bit_maybe_r_backwards : string -> mword ty1*) + +definition bit_maybe_r_backwards :: " string \<Rightarrow>(1)Word.word " where + " bit_maybe_r_backwards arg0 = ( + if(arg0 = (''r'')) then ((vec_of_bits [B1] :: 1 Word.word)) else + ( + if(arg0 = ('''')) then ((vec_of_bits [B0] :: 1 Word.word)) else undefined) )" + + +(*val bit_maybe_r_forwards_matches : mword ty1 -> bool*) + +definition bit_maybe_r_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where + " bit_maybe_r_forwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B1] :: 1 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0] :: 1 Word.word)))) then True + else False))" + + +(*val bit_maybe_r_backwards_matches : string -> bool*) + +definition bit_maybe_r_backwards_matches :: " string \<Rightarrow> bool " where + " bit_maybe_r_backwards_matches arg0 = ( + if(arg0 = (''r'')) then True else (if(arg0 = ('''')) then True else False) )" + + +(*val bit_maybe_r_matches_prefix : string -> maybe ((mword ty1 * ii))*) + +definition bit_maybe_r_matches_prefix :: " string \<Rightarrow>((1)Word.word*int)option " where + " bit_maybe_r_matches_prefix arg0 = ( + (let stringappend_16670 = arg0 in + if (((((string_startswith stringappend_16670 (''r''))) \<and> ( + (case ((string_drop stringappend_16670 ((string_length (''r''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16670 ((string_length (''r''))))) of + s0 => + Some ((vec_of_bits [B1] :: 1 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16670 (''''))) \<and> ( + (case ((string_drop stringappend_16670 ((string_length (''''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16670 ((string_length (''''))))) of + s0 => + Some ((vec_of_bits [B0] :: 1 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val bit_maybe_w_forwards : mword ty1 -> string*) + +definition bit_maybe_w_forwards :: "(1)Word.word \<Rightarrow> string " where + " bit_maybe_w_forwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B1] :: 1 Word.word)))) then (''w'') + else ('''')))" + + +(*val bit_maybe_w_backwards : string -> mword ty1*) + +definition bit_maybe_w_backwards :: " string \<Rightarrow>(1)Word.word " where + " bit_maybe_w_backwards arg0 = ( + if(arg0 = (''w'')) then ((vec_of_bits [B1] :: 1 Word.word)) else + ( + if(arg0 = ('''')) then ((vec_of_bits [B0] :: 1 Word.word)) else undefined) )" + + +(*val bit_maybe_w_forwards_matches : mword ty1 -> bool*) + +definition bit_maybe_w_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where + " bit_maybe_w_forwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B1] :: 1 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0] :: 1 Word.word)))) then True + else False))" + + +(*val bit_maybe_w_backwards_matches : string -> bool*) + +definition bit_maybe_w_backwards_matches :: " string \<Rightarrow> bool " where + " bit_maybe_w_backwards_matches arg0 = ( + if(arg0 = (''w'')) then True else (if(arg0 = ('''')) then True else False) )" + + +(*val bit_maybe_w_matches_prefix : string -> maybe ((mword ty1 * ii))*) + +definition bit_maybe_w_matches_prefix :: " string \<Rightarrow>((1)Word.word*int)option " where + " bit_maybe_w_matches_prefix arg0 = ( + (let stringappend_16650 = arg0 in + if (((((string_startswith stringappend_16650 (''w''))) \<and> ( + (case ((string_drop stringappend_16650 ((string_length (''w''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16650 ((string_length (''w''))))) of + s0 => + Some ((vec_of_bits [B1] :: 1 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16650 (''''))) \<and> ( + (case ((string_drop stringappend_16650 ((string_length (''''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16650 ((string_length (''''))))) of + s0 => + Some ((vec_of_bits [B0] :: 1 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val bit_maybe_i_forwards : mword ty1 -> string*) + +definition bit_maybe_i_forwards :: "(1)Word.word \<Rightarrow> string " where + " bit_maybe_i_forwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B1] :: 1 Word.word)))) then (''i'') + else ('''')))" + + +(*val bit_maybe_i_backwards : string -> mword ty1*) + +definition bit_maybe_i_backwards :: " string \<Rightarrow>(1)Word.word " where + " bit_maybe_i_backwards arg0 = ( + if(arg0 = (''i'')) then ((vec_of_bits [B1] :: 1 Word.word)) else + ( + if(arg0 = ('''')) then ((vec_of_bits [B0] :: 1 Word.word)) else undefined) )" + + +(*val bit_maybe_i_forwards_matches : mword ty1 -> bool*) + +definition bit_maybe_i_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where + " bit_maybe_i_forwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B1] :: 1 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0] :: 1 Word.word)))) then True + else False))" + + +(*val bit_maybe_i_backwards_matches : string -> bool*) + +definition bit_maybe_i_backwards_matches :: " string \<Rightarrow> bool " where + " bit_maybe_i_backwards_matches arg0 = ( + if(arg0 = (''i'')) then True else (if(arg0 = ('''')) then True else False) )" + + +(*val bit_maybe_i_matches_prefix : string -> maybe ((mword ty1 * ii))*) + +definition bit_maybe_i_matches_prefix :: " string \<Rightarrow>((1)Word.word*int)option " where + " bit_maybe_i_matches_prefix arg0 = ( + (let stringappend_16630 = arg0 in + if (((((string_startswith stringappend_16630 (''i''))) \<and> ( + (case ((string_drop stringappend_16630 ((string_length (''i''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16630 ((string_length (''i''))))) of + s0 => + Some ((vec_of_bits [B1] :: 1 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16630 (''''))) \<and> ( + (case ((string_drop stringappend_16630 ((string_length (''''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16630 ((string_length (''''))))) of + s0 => + Some ((vec_of_bits [B0] :: 1 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val bit_maybe_o_forwards : mword ty1 -> string*) + +definition bit_maybe_o_forwards :: "(1)Word.word \<Rightarrow> string " where + " bit_maybe_o_forwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B1] :: 1 Word.word)))) then (''o'') + else ('''')))" + + +(*val bit_maybe_o_backwards : string -> mword ty1*) + +definition bit_maybe_o_backwards :: " string \<Rightarrow>(1)Word.word " where + " bit_maybe_o_backwards arg0 = ( + if(arg0 = (''o'')) then ((vec_of_bits [B1] :: 1 Word.word)) else + ( + if(arg0 = ('''')) then ((vec_of_bits [B0] :: 1 Word.word)) else undefined) )" + + +(*val bit_maybe_o_forwards_matches : mword ty1 -> bool*) + +definition bit_maybe_o_forwards_matches :: "(1)Word.word \<Rightarrow> bool " where + " bit_maybe_o_forwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B1] :: 1 Word.word)))) then True + else if (((p00 = (vec_of_bits [B0] :: 1 Word.word)))) then True + else False))" + + +(*val bit_maybe_o_backwards_matches : string -> bool*) + +definition bit_maybe_o_backwards_matches :: " string \<Rightarrow> bool " where + " bit_maybe_o_backwards_matches arg0 = ( + if(arg0 = (''o'')) then True else (if(arg0 = ('''')) then True else False) )" + + +(*val bit_maybe_o_matches_prefix : string -> maybe ((mword ty1 * ii))*) + +definition bit_maybe_o_matches_prefix :: " string \<Rightarrow>((1)Word.word*int)option " where + " bit_maybe_o_matches_prefix arg0 = ( + (let stringappend_16610 = arg0 in + if (((((string_startswith stringappend_16610 (''o''))) \<and> ( + (case ((string_drop stringappend_16610 ((string_length (''o''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16610 ((string_length (''o''))))) of + s0 => + Some ((vec_of_bits [B1] :: 1 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16610 (''''))) \<and> ( + (case ((string_drop stringappend_16610 ((string_length (''''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16610 ((string_length (''''))))) of + s0 => + Some ((vec_of_bits [B0] :: 1 Word.word), + ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val fence_bits_forwards : mword ty4 -> string*) + +definition fence_bits_forwards :: "(4)Word.word \<Rightarrow> string " where + " fence_bits_forwards v__0 = ( + (let (r :: 1 bits) = ((subrange_vec_dec v__0 (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word)) in + (let (w :: 1 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + (let (i :: 1 bits) = ((subrange_vec_dec v__0 (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word)) in + (let (o1 :: 1 bits) = ((subrange_vec_dec v__0 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + string_append ((bit_maybe_r_forwards r)) + ((string_append ((bit_maybe_w_forwards w)) + ((string_append ((bit_maybe_i_forwards i)) + ((string_append ((bit_maybe_o_forwards o1)) (''''))))))))))))" + + +(*val fence_bits_backwards : string -> mword ty4*) + +definition fence_bits_backwards :: " string \<Rightarrow>(4)Word.word " where + " fence_bits_backwards arg0 = ( + (let stringappend_16490 = arg0 in + (let (r, stringappend_16510) = + ((case ((bit_maybe_r_matches_prefix stringappend_16490 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16500,stringappend_16510) => (stringappend_16500, stringappend_16510) + )) in + (let stringappend_16520 = (string_drop stringappend_16490 stringappend_16510) in + (let (w, stringappend_16540) = + ((case ((bit_maybe_w_matches_prefix stringappend_16520 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16530,stringappend_16540) => (stringappend_16530, stringappend_16540) + )) in + (let stringappend_16550 = (string_drop stringappend_16520 stringappend_16540) in + (let (i, stringappend_16570) = + ((case ((bit_maybe_i_matches_prefix stringappend_16550 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16560,stringappend_16570) => (stringappend_16560, stringappend_16570) + )) in + (let stringappend_16580 = (string_drop stringappend_16550 stringappend_16570) in + (let (o1, stringappend_16600) = + ((case ((bit_maybe_o_matches_prefix stringappend_16580 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16590,stringappend_16600) => (stringappend_16590, stringappend_16600) + )) in if(((string_drop stringappend_16580 stringappend_16600)) = ('''')) then + ((concat_vec r + ((concat_vec w ((concat_vec i o1 :: 2 Word.word)) :: 3 Word.word)) :: 4 Word.word)) + else undefined)))))))))" + + +(*val fence_bits_forwards_matches : mword ty4 -> bool*) + +definition fence_bits_forwards_matches :: "(4)Word.word \<Rightarrow> bool " where + " fence_bits_forwards_matches v__1 = ( True )" + + +(*val fence_bits_backwards_matches : string -> bool*) + +definition fence_bits_backwards_matches :: " string \<Rightarrow> bool " where + " fence_bits_backwards_matches arg0 = ( + (let stringappend_16370 = arg0 in + if ((case ((bit_maybe_r_matches_prefix stringappend_16370 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16380,stringappend_16390) => + (let stringappend_16400 = (string_drop stringappend_16370 stringappend_16390) in + if ((case ((bit_maybe_w_matches_prefix stringappend_16400 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16410,stringappend_16420) => + (let stringappend_16430 = (string_drop stringappend_16400 stringappend_16420) in + if ((case ((bit_maybe_i_matches_prefix stringappend_16430 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16440,stringappend_16450) => + (let stringappend_16460 = (string_drop stringappend_16430 stringappend_16450) in + if ((case ((bit_maybe_o_matches_prefix stringappend_16460 + :: (( 1 Word.word * ii))option)) of + Some (stringappend_16470,stringappend_16480) => + if(((string_drop stringappend_16460 stringappend_16480)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (r, stringappend_16390) = + ((case ((bit_maybe_r_matches_prefix stringappend_16370 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16380,stringappend_16390) => + (stringappend_16380, stringappend_16390) + )) in + (let stringappend_16400 = (string_drop stringappend_16370 stringappend_16390) in + (let (w, stringappend_16420) = + ((case ((bit_maybe_w_matches_prefix stringappend_16400 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16410,stringappend_16420) => + (stringappend_16410, stringappend_16420) + )) in + (let stringappend_16430 = (string_drop stringappend_16400 stringappend_16420) in + (let (i, stringappend_16450) = + ((case ((bit_maybe_i_matches_prefix stringappend_16430 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16440,stringappend_16450) => + (stringappend_16440, stringappend_16450) + )) in + (let stringappend_16460 = (string_drop stringappend_16430 stringappend_16450) in + (let (o1, stringappend_16480) = + ((case ((bit_maybe_o_matches_prefix stringappend_16460 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16470,stringappend_16480) => + (stringappend_16470, stringappend_16480) + )) in if(((string_drop stringappend_16460 stringappend_16480)) = ('''')) then + True else undefined))))))) + else False))" + + +(*val fence_bits_matches_prefix : string -> maybe ((mword ty4 * ii))*) + +definition fence_bits_matches_prefix :: " string \<Rightarrow>((4)Word.word*int)option " where + " fence_bits_matches_prefix arg0 = ( + (let stringappend_16250 = arg0 in + if ((case ((bit_maybe_r_matches_prefix stringappend_16250 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16260,stringappend_16270) => + (let stringappend_16280 = (string_drop stringappend_16250 stringappend_16270) in + if ((case ((bit_maybe_w_matches_prefix stringappend_16280 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16290,stringappend_16300) => + (let stringappend_16310 = (string_drop stringappend_16280 stringappend_16300) in + if ((case ((bit_maybe_i_matches_prefix stringappend_16310 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16320,stringappend_16330) => + (let stringappend_16340 = (string_drop stringappend_16310 stringappend_16330) in + if ((case ((bit_maybe_o_matches_prefix stringappend_16340 + :: (( 1 Word.word * ii))option)) of + Some (stringappend_16350,stringappend_16360) => + (case ((string_drop stringappend_16340 stringappend_16360)) of + s0 => True + ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (r, stringappend_16270) = + ((case ((bit_maybe_r_matches_prefix stringappend_16250 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16260,stringappend_16270) => + (stringappend_16260, stringappend_16270) + )) in + (let stringappend_16280 = (string_drop stringappend_16250 stringappend_16270) in + (let (w, stringappend_16300) = + ((case ((bit_maybe_w_matches_prefix stringappend_16280 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16290,stringappend_16300) => + (stringappend_16290, stringappend_16300) + )) in + (let stringappend_16310 = (string_drop stringappend_16280 stringappend_16300) in + (let (i, stringappend_16330) = + ((case ((bit_maybe_i_matches_prefix stringappend_16310 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16320,stringappend_16330) => + (stringappend_16320, stringappend_16330) + )) in + (let stringappend_16340 = (string_drop stringappend_16310 stringappend_16330) in + (let (o1, stringappend_16360) = + ((case ((bit_maybe_o_matches_prefix stringappend_16340 :: (( 1 Word.word * ii))option)) of + Some (stringappend_16350,stringappend_16360) => + (stringappend_16350, stringappend_16360) + )) in + (case ((string_drop stringappend_16340 stringappend_16360)) of + s0 => + Some ((concat_vec r ((concat_vec w ((concat_vec i o1 :: 2 Word.word)) :: 3 Word.word)) + :: 4 Word.word), + ((string_length arg0)) - ((string_length s0))) + )))))))) + else None))" + + +(*val aqrl_str : bool -> bool -> string*) + +fun aqrl_str :: " bool \<Rightarrow> bool \<Rightarrow> string " where + " aqrl_str (False :: bool) (False :: bool) = ( (''''))" +|" aqrl_str (False :: bool) (True :: bool) = ( (''.rl''))" +|" aqrl_str (True :: bool) (False :: bool) = ( (''.aq''))" +|" aqrl_str (True :: bool) (True :: bool) = ( (''.aqrl''))" + + +(*val lrsc_width_str : word_width -> string*) + +fun lrsc_width_str :: " word_width \<Rightarrow> string " where + " lrsc_width_str BYTE = ( (''.b''))" +|" lrsc_width_str HALF = ( (''.h''))" +|" lrsc_width_str WORD = ( (''.w''))" +|" lrsc_width_str DOUBLE = ( (''.d''))" + + +(*val process_loadres : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M bool*) + +definition process_loadres :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where + " process_loadres rd addr value1 is_unsigned = ( + (case ((extend_value is_unsigned value1 :: ( 64 Word.word) MemoryOpResult)) of + MemValue (result) => + (let (_ :: unit) = (load_reservation addr) in + wX ((regbits_to_regno rd)) result \<then> return True) + | MemException (e) => handle_mem_exception addr e \<then> return False + ))" + + +(*val encdec_amoop_forwards : amoop -> mword ty5*) + +fun encdec_amoop_forwards :: " amoop \<Rightarrow>(5)Word.word " where + " encdec_amoop_forwards AMOSWAP = ( (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))" +|" encdec_amoop_forwards AMOADD = ( (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))" +|" encdec_amoop_forwards AMOXOR = ( (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word))" +|" encdec_amoop_forwards AMOAND = ( (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word))" +|" encdec_amoop_forwards AMOOR = ( (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word))" +|" encdec_amoop_forwards AMOMIN = ( (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word))" +|" encdec_amoop_forwards AMOMAX = ( (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word))" +|" encdec_amoop_forwards AMOMINU = ( (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word))" +|" encdec_amoop_forwards AMOMAXU = ( (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word))" + + +(*val encdec_amoop_backwards : mword ty5 -> amoop*) + +definition encdec_amoop_backwards :: "(5)Word.word \<Rightarrow> amoop " where + " encdec_amoop_backwards arg0 = ( + (let p00 = arg0 in + if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) + then + AMOSWAP + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) then + AMOADD + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then + AMOXOR + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then + AMOAND + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then + AMOOR + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then + AMOMIN + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then + AMOMAX + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then + AMOMINU + else AMOMAXU))" + + +(*val encdec_amoop_forwards_matches : amoop -> bool*) + +fun encdec_amoop_forwards_matches :: " amoop \<Rightarrow> bool " where + " encdec_amoop_forwards_matches AMOSWAP = ( True )" +|" encdec_amoop_forwards_matches AMOADD = ( True )" +|" encdec_amoop_forwards_matches AMOXOR = ( True )" +|" encdec_amoop_forwards_matches AMOAND = ( True )" +|" encdec_amoop_forwards_matches AMOOR = ( True )" +|" encdec_amoop_forwards_matches AMOMIN = ( True )" +|" encdec_amoop_forwards_matches AMOMAX = ( True )" +|" encdec_amoop_forwards_matches AMOMINU = ( True )" +|" encdec_amoop_forwards_matches AMOMAXU = ( True )" + + +(*val encdec_amoop_backwards_matches : mword ty5 -> bool*) + +definition encdec_amoop_backwards_matches :: "(5)Word.word \<Rightarrow> bool " where + " encdec_amoop_backwards_matches arg0 = ( + (let p00 = arg0 in + if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) + then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then + True + else if (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then + True + else False))" + + +(*val amo_mnemonic_forwards : amoop -> string*) + +fun amo_mnemonic_forwards :: " amoop \<Rightarrow> string " where + " amo_mnemonic_forwards AMOSWAP = ( (''amoswap''))" +|" amo_mnemonic_forwards AMOADD = ( (''amoadd''))" +|" amo_mnemonic_forwards AMOXOR = ( (''amoxor''))" +|" amo_mnemonic_forwards AMOAND = ( (''amoand''))" +|" amo_mnemonic_forwards AMOOR = ( (''amoor''))" +|" amo_mnemonic_forwards AMOMIN = ( (''amomin''))" +|" amo_mnemonic_forwards AMOMAX = ( (''amomax''))" +|" amo_mnemonic_forwards AMOMINU = ( (''amominu''))" +|" amo_mnemonic_forwards AMOMAXU = ( (''amomaxu''))" + + +(*val amo_mnemonic_backwards : string -> amoop*) + +definition amo_mnemonic_backwards :: " string \<Rightarrow> amoop " where + " amo_mnemonic_backwards arg0 = ( + if(arg0 = (''amoswap'')) then AMOSWAP else + ( + if(arg0 = (''amoadd'')) then AMOADD else + ( + if(arg0 = (''amoxor'')) then AMOXOR else + ( + if(arg0 = (''amoand'')) then AMOAND else + ( + if(arg0 = (''amoor'')) then AMOOR else + ( + if(arg0 = (''amomin'')) then AMOMIN else + ( + if(arg0 = (''amomax'')) then AMOMAX else + ( + if(arg0 = (''amominu'')) then AMOMINU else + (if(arg0 = (''amomaxu'')) then AMOMAXU else undefined)))))))) )" + + +(*val amo_mnemonic_forwards_matches : amoop -> bool*) + +fun amo_mnemonic_forwards_matches :: " amoop \<Rightarrow> bool " where + " amo_mnemonic_forwards_matches AMOSWAP = ( True )" +|" amo_mnemonic_forwards_matches AMOADD = ( True )" +|" amo_mnemonic_forwards_matches AMOXOR = ( True )" +|" amo_mnemonic_forwards_matches AMOAND = ( True )" +|" amo_mnemonic_forwards_matches AMOOR = ( True )" +|" amo_mnemonic_forwards_matches AMOMIN = ( True )" +|" amo_mnemonic_forwards_matches AMOMAX = ( True )" +|" amo_mnemonic_forwards_matches AMOMINU = ( True )" +|" amo_mnemonic_forwards_matches AMOMAXU = ( True )" + + +(*val amo_mnemonic_backwards_matches : string -> bool*) + +definition amo_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where + " amo_mnemonic_backwards_matches arg0 = ( + if(arg0 = (''amoswap'')) then True else + ( + if(arg0 = (''amoadd'')) then True else + ( + if(arg0 = (''amoxor'')) then True else + ( + if(arg0 = (''amoand'')) then True else + ( + if(arg0 = (''amoor'')) then True else + ( + if(arg0 = (''amomin'')) then True else + ( + if(arg0 = (''amomax'')) then True else + ( + if(arg0 = (''amominu'')) then True else + (if(arg0 = (''amomaxu'')) then True else False)))))))) )" + + +(*val amo_mnemonic_matches_prefix : string -> maybe ((amoop * ii))*) + +definition amo_mnemonic_matches_prefix :: " string \<Rightarrow>(amoop*int)option " where + " amo_mnemonic_matches_prefix arg0 = ( + (let stringappend_16160 = arg0 in + if (((((string_startswith stringappend_16160 (''amoswap''))) \<and> ( + (case ((string_drop stringappend_16160 ((string_length (''amoswap''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16160 ((string_length (''amoswap''))))) of + s0 => Some (AMOSWAP, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16160 (''amoadd''))) \<and> ( + (case ((string_drop stringappend_16160 ((string_length (''amoadd''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16160 ((string_length (''amoadd''))))) of + s0 => Some (AMOADD, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16160 (''amoxor''))) \<and> ( + (case ((string_drop stringappend_16160 ((string_length (''amoxor''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16160 ((string_length (''amoxor''))))) of + s0 => Some (AMOXOR, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16160 (''amoand''))) \<and> ( + (case ((string_drop stringappend_16160 ((string_length (''amoand''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16160 ((string_length (''amoand''))))) of + s0 => Some (AMOAND, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16160 (''amoor''))) \<and> ( + (case ((string_drop stringappend_16160 ((string_length (''amoor''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16160 ((string_length (''amoor''))))) of + s0 => Some (AMOOR, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16160 (''amomin''))) \<and> ( + (case ((string_drop stringappend_16160 ((string_length (''amomin''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16160 ((string_length (''amomin''))))) of + s0 => Some (AMOMIN, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16160 (''amomax''))) \<and> ( + (case ((string_drop stringappend_16160 ((string_length (''amomax''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16160 ((string_length (''amomax''))))) of + s0 => Some (AMOMAX, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16160 (''amominu''))) \<and> ( + (case ((string_drop stringappend_16160 ((string_length (''amominu''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16160 ((string_length (''amominu''))))) of + s0 => Some (AMOMINU, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16160 (''amomaxu''))) \<and> ( + (case ((string_drop stringappend_16160 ((string_length (''amomaxu''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16160 ((string_length (''amomaxu''))))) of + s0 => Some (AMOMAXU, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val encdec_csrop_forwards : csrop -> mword ty2*) + +fun encdec_csrop_forwards :: " csrop \<Rightarrow>(2)Word.word " where + " encdec_csrop_forwards CSRRW = ( (vec_of_bits [B0,B1] :: 2 Word.word))" +|" encdec_csrop_forwards CSRRS = ( (vec_of_bits [B1,B0] :: 2 Word.word))" +|" encdec_csrop_forwards CSRRC = ( (vec_of_bits [B1,B1] :: 2 Word.word))" + + +(*val encdec_csrop_backwards : mword ty2 -> csrop*) + +definition encdec_csrop_backwards :: "(2)Word.word \<Rightarrow> csrop " where + " encdec_csrop_backwards arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then CSRRW + else if (((p00 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then CSRRS + else CSRRC))" + + +(*val encdec_csrop_forwards_matches : csrop -> bool*) + +fun encdec_csrop_forwards_matches :: " csrop \<Rightarrow> bool " where + " encdec_csrop_forwards_matches CSRRW = ( True )" +|" encdec_csrop_forwards_matches CSRRS = ( True )" +|" encdec_csrop_forwards_matches CSRRC = ( True )" + + +(*val encdec_csrop_backwards_matches : mword ty2 -> bool*) + +definition encdec_csrop_backwards_matches :: "(2)Word.word \<Rightarrow> bool " where + " encdec_csrop_backwards_matches arg0 = ( + (let p00 = arg0 in + if (((p00 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then True + else if (((p00 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then True + else False))" + (*val readCSR : mword ty12 -> M (mword ty64)*) definition readCSR :: "(12)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where " readCSR csr = ( (let b__0 = csr in - if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then - (read_reg mvendorid_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then - (read_reg marchid_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then - (read_reg mimpid_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then - (read_reg mhartid_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then - read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) . return ((get_Mstatus w__4 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then - read_reg misa_ref \<bind> (\<lambda> (w__5 :: Misa) . return ((get_Misa w__5 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then - read_reg medeleg_ref \<bind> (\<lambda> (w__6 :: Medeleg) . return ((get_Medeleg w__6 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then - read_reg mideleg_ref \<bind> (\<lambda> (w__7 :: Minterrupts) . - return ((get_Minterrupts w__7 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then - read_reg mie_ref \<bind> (\<lambda> (w__8 :: Minterrupts) . return ((get_Minterrupts w__8 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then - read_reg mtvec_ref \<bind> (\<lambda> (w__9 :: Mtvec) . return ((get_Mtvec w__9 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then - (read_reg mscratch_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then - (read_reg mepc_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then - read_reg mcause_ref \<bind> (\<lambda> (w__12 :: Mcause) . return ((get_Mcause w__12 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then - (read_reg mtval_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then - read_reg mip_ref \<bind> (\<lambda> (w__14 :: Minterrupts) . - return ((get_Minterrupts w__14 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then - read_reg mstatus_ref \<bind> (\<lambda> (w__15 :: Mstatus) . return ((get_Mstatus w__15 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then - read_reg sedeleg_ref \<bind> (\<lambda> (w__16 :: Sedeleg) . return ((get_Sedeleg w__16 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then - read_reg sideleg_ref \<bind> (\<lambda> (w__17 :: Sinterrupts) . - return ((get_Sinterrupts w__17 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then - read_reg mie_ref \<bind> (\<lambda> (w__18 :: Minterrupts) . - read_reg mideleg_ref \<bind> (\<lambda> (w__19 :: Minterrupts) . - return ((get_Sinterrupts ((lower_mie w__18 w__19)) :: 64 Word.word)))) - else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then - read_reg stvec_ref \<bind> (\<lambda> (w__20 :: Mtvec) . return ((get_Mtvec w__20 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then - (read_reg sscratch_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then - (read_reg sepc_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then - read_reg scause_ref \<bind> (\<lambda> (w__23 :: Mcause) . return ((get_Mcause w__23 :: 64 Word.word))) - else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then - (read_reg stval_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then - read_reg mip_ref \<bind> (\<lambda> (w__25 :: Minterrupts) . - read_reg mideleg_ref \<bind> (\<lambda> (w__26 :: Minterrupts) . - return ((get_Sinterrupts ((lower_mip w__25 w__26)) :: 64 Word.word)))) - else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then - (read_reg satp_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then - (read_reg mcycle_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then - (read_reg mtime_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then - (read_reg minstret_ref :: ( 64 Word.word) M) - else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then - (read_reg tselect_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__31 :: 64 Word.word) . - return ((not_vec w__31 :: 64 Word.word))) - else - (let (_ :: unit) = (print_bits (''unhandled read to CSR '') csr) in - return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word))))" + (if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then + (read_reg mvendorid_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then + (read_reg marchid_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then + (read_reg mimpid_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then + (read_reg mhartid_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) . + return ((get_Mstatus_bits w__4 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + read_reg misa_ref \<bind> (\<lambda> (w__5 :: Misa) . return ((get_Misa_bits w__5 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg medeleg_ref \<bind> (\<lambda> (w__6 :: Medeleg) . + return ((get_Medeleg_bits w__6 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + read_reg mideleg_ref \<bind> (\<lambda> (w__7 :: Minterrupts) . + return ((get_Minterrupts_bits w__7 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mie_ref \<bind> (\<lambda> (w__8 :: Minterrupts) . + return ((get_Minterrupts_bits w__8 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + read_reg mtvec_ref \<bind> (\<lambda> (w__9 :: Mtvec) . return ((get_Mtvec_bits w__9 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + read_reg mcounteren_ref \<bind> (\<lambda> (w__10 :: Counteren) . + return ((EXTZ (( 64 :: int)::ii) ((get_Counteren_bits w__10 :: 32 Word.word)) :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg mscratch_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (read_reg mepc_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 :: 64 Word.word) . + (pc_alignment_mask () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 Word.word) . + return ((and_vec w__12 w__13 :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg mcause_ref \<bind> (\<lambda> (w__14 :: Mcause) . + return ((get_Mcause_bits w__14 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (read_reg mtval_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mip_ref \<bind> (\<lambda> (w__16 :: Minterrupts) . + return ((get_Minterrupts_bits w__16 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg pmpcfg0_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg pmpaddr0_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + read_reg mstatus_ref \<bind> (\<lambda> (w__19 :: Mstatus) . + return ((get_Sstatus_bits ((lower_mstatus w__19)) :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg sedeleg_ref \<bind> (\<lambda> (w__20 :: Sedeleg) . + return ((get_Sedeleg_bits w__20 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + read_reg sideleg_ref \<bind> (\<lambda> (w__21 :: Sinterrupts) . + return ((get_Sinterrupts_bits w__21 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mie_ref \<bind> (\<lambda> (w__22 :: Minterrupts) . + read_reg mideleg_ref \<bind> (\<lambda> (w__23 :: Minterrupts) . + return ((get_Sinterrupts_bits ((lower_mie w__22 w__23)) :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + read_reg stvec_ref \<bind> (\<lambda> (w__24 :: Mtvec) . return ((get_Mtvec_bits w__24 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + read_reg scounteren_ref \<bind> (\<lambda> (w__25 :: Counteren) . + return ((EXTZ (( 64 :: int)::ii) ((get_Counteren_bits w__25 :: 32 Word.word)) :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg sscratch_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (read_reg sepc_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__27 :: 64 Word.word) . + (pc_alignment_mask () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: 64 Word.word) . + return ((and_vec w__27 w__28 :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg scause_ref \<bind> (\<lambda> (w__29 :: Mcause) . + return ((get_Mcause_bits w__29 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (read_reg stval_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mip_ref \<bind> (\<lambda> (w__31 :: Minterrupts) . + read_reg mideleg_ref \<bind> (\<lambda> (w__32 :: Minterrupts) . + return ((get_Sinterrupts_bits ((lower_mip w__31 w__32)) :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg satp_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg mcycle_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (read_reg mtime_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (read_reg minstret_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg tselect_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__37 :: 64 Word.word) . + return ((not_vec w__37 :: 64 Word.word))) + else + (let (_ :: unit) = (print_bits (''unhandled read to CSR '') csr) in + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word))) \<bind> (\<lambda> (res :: xlenbits) . + (let (_ :: unit) = + (print_endline + (((op@) (''CSR '') + (((op@) ((csr_name csr)) (((op@) ('' -> '') ((string_of_bits res))))))))) in + return res))))" (*val writeCSR : mword ty12 -> mword ty64 -> M unit*) @@ -5363,784 +12442,330 @@ definition writeCSR :: "(12)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>( read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) . (write_reg mstatus_ref ((legalize_mstatus w__0 value1)) \<then> read_reg mstatus_ref) \<bind> (\<lambda> (w__1 :: Mstatus) . - return (Some ((get_Mstatus w__1 :: 64 Word.word))))) + return (Some ((get_Mstatus_bits w__1 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + read_reg misa_ref \<bind> (\<lambda> (w__2 :: Misa) . + legalize_misa w__2 value1 \<bind> (\<lambda> (w__3 :: Misa) . + (write_reg misa_ref w__3 \<then> + read_reg misa_ref) \<bind> (\<lambda> (w__4 :: Misa) . return (Some ((get_Misa_bits w__4 :: 64 Word.word)))))) else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then - read_reg medeleg_ref \<bind> (\<lambda> (w__2 :: Medeleg) . - (write_reg medeleg_ref ((legalize_medeleg w__2 value1)) \<then> - read_reg medeleg_ref) \<bind> (\<lambda> (w__3 :: Medeleg) . - return (Some ((get_Medeleg w__3 :: 64 Word.word))))) + read_reg medeleg_ref \<bind> (\<lambda> (w__5 :: Medeleg) . + (write_reg medeleg_ref ((legalize_medeleg w__5 value1)) \<then> + read_reg medeleg_ref) \<bind> (\<lambda> (w__6 :: Medeleg) . + return (Some ((get_Medeleg_bits w__6 :: 64 Word.word))))) else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then - read_reg mideleg_ref \<bind> (\<lambda> (w__4 :: Minterrupts) . - (write_reg mideleg_ref ((legalize_mideleg w__4 value1)) \<then> - read_reg mideleg_ref) \<bind> (\<lambda> (w__5 :: Minterrupts) . - return (Some ((get_Minterrupts w__5 :: 64 Word.word))))) + read_reg mideleg_ref \<bind> (\<lambda> (w__7 :: Minterrupts) . + (write_reg mideleg_ref ((legalize_mideleg w__7 value1)) \<then> + read_reg mideleg_ref) \<bind> (\<lambda> (w__8 :: Minterrupts) . + return (Some ((get_Minterrupts_bits w__8 :: 64 Word.word))))) else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then - read_reg mie_ref \<bind> (\<lambda> (w__6 :: Minterrupts) . - (write_reg mie_ref ((legalize_mie w__6 value1)) \<then> - read_reg mie_ref) \<bind> (\<lambda> (w__7 :: Minterrupts) . - return (Some ((get_Minterrupts w__7 :: 64 Word.word))))) + read_reg mie_ref \<bind> (\<lambda> (w__9 :: Minterrupts) . + (write_reg mie_ref ((legalize_mie w__9 value1)) \<then> + read_reg mie_ref) \<bind> (\<lambda> (w__10 :: Minterrupts) . + return (Some ((get_Minterrupts_bits w__10 :: 64 Word.word))))) else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then - read_reg mtvec_ref \<bind> (\<lambda> (w__8 :: Mtvec) . - (write_reg mtvec_ref ((legalize_tvec w__8 value1)) \<then> - read_reg mtvec_ref) \<bind> (\<lambda> (w__9 :: Mtvec) . return (Some ((get_Mtvec w__9 :: 64 Word.word))))) + read_reg mtvec_ref \<bind> (\<lambda> (w__11 :: Mtvec) . + (write_reg mtvec_ref ((legalize_tvec w__11 value1)) \<then> + read_reg mtvec_ref) \<bind> (\<lambda> (w__12 :: Mtvec) . + return (Some ((get_Mtvec_bits w__12 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + read_reg mcounteren_ref \<bind> (\<lambda> (w__13 :: Counteren) . + (write_reg mcounteren_ref ((legalize_mcounteren w__13 value1)) \<then> + read_reg mcounteren_ref) \<bind> (\<lambda> (w__14 :: Counteren) . + return (Some ((EXTZ (( 64 :: int)::ii) ((get_Counteren_bits w__14 :: 32 Word.word)) :: 64 Word.word))))) else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then (write_reg mscratch_ref value1 \<then> - (read_reg mscratch_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__10 :: 64 Word.word) . return (Some w__10)) + (read_reg mscratch_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__15 :: 64 Word.word) . return (Some w__15)) else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then - (legalize_xepc value1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: xlenbits) . - (write_reg mepc_ref w__11 \<then> - (read_reg mepc_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__12 :: 64 Word.word) . return (Some w__12))) + (legalize_xepc value1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__16 :: xlenbits) . + (write_reg mepc_ref w__16 \<then> + (read_reg mepc_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__17 :: 64 Word.word) . return (Some w__17))) else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then - (set_Mcause mcause_ref value1 \<then> - read_reg mcause_ref) \<bind> (\<lambda> (w__13 :: Mcause) . - return (Some ((get_Mcause w__13 :: 64 Word.word)))) + (set_Mcause_bits mcause_ref value1 \<then> + read_reg mcause_ref) \<bind> (\<lambda> (w__18 :: Mcause) . + return (Some ((get_Mcause_bits w__18 :: 64 Word.word)))) else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then (write_reg mtval_ref value1 \<then> - (read_reg mtval_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__14 :: 64 Word.word) . return (Some w__14)) + (read_reg mtval_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__19 :: 64 Word.word) . return (Some w__19)) else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then - read_reg mip_ref \<bind> (\<lambda> (w__15 :: Minterrupts) . - (write_reg mip_ref ((legalize_mip w__15 value1)) \<then> - read_reg mip_ref) \<bind> (\<lambda> (w__16 :: Minterrupts) . - return (Some ((get_Minterrupts w__16 :: 64 Word.word))))) + read_reg mip_ref \<bind> (\<lambda> (w__20 :: Minterrupts) . + (write_reg mip_ref ((legalize_mip w__20 value1)) \<then> + read_reg mip_ref) \<bind> (\<lambda> (w__21 :: Minterrupts) . + return (Some ((get_Minterrupts_bits w__21 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (write_reg pmpcfg0_ref value1 \<then> + (read_reg pmpcfg0_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__22 :: 64 Word.word) . return (Some w__22)) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B0,B1,B1,B0,B0,B0,B0] :: 12 Word.word)))) then + (write_reg pmpaddr0_ref value1 \<then> + (read_reg pmpaddr0_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__23 :: 64 Word.word) . return (Some w__23)) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then - read_reg mstatus_ref \<bind> (\<lambda> (w__17 :: Mstatus) . - (write_reg mstatus_ref ((legalize_sstatus w__17 value1)) \<then> - read_reg mstatus_ref) \<bind> (\<lambda> (w__18 :: Mstatus) . - return (Some ((get_Mstatus w__18 :: 64 Word.word))))) + read_reg mstatus_ref \<bind> (\<lambda> (w__24 :: Mstatus) . + (write_reg mstatus_ref ((legalize_sstatus w__24 value1)) \<then> + read_reg mstatus_ref) \<bind> (\<lambda> (w__25 :: Mstatus) . + return (Some ((get_Mstatus_bits w__25 :: 64 Word.word))))) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then - read_reg sedeleg_ref \<bind> (\<lambda> (w__19 :: Sedeleg) . - (write_reg sedeleg_ref ((legalize_sedeleg w__19 value1)) \<then> - read_reg sedeleg_ref) \<bind> (\<lambda> (w__20 :: Sedeleg) . - return (Some ((get_Sedeleg w__20 :: 64 Word.word))))) + read_reg sedeleg_ref \<bind> (\<lambda> (w__26 :: Sedeleg) . + (write_reg sedeleg_ref ((legalize_sedeleg w__26 value1)) \<then> + read_reg sedeleg_ref) \<bind> (\<lambda> (w__27 :: Sedeleg) . + return (Some ((get_Sedeleg_bits w__27 :: 64 Word.word))))) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then - (set_Sinterrupts sideleg_ref value1 \<then> - read_reg sideleg_ref) \<bind> (\<lambda> (w__21 :: Sinterrupts) . - return (Some ((get_Sinterrupts w__21 :: 64 Word.word)))) + (set_Sinterrupts_bits sideleg_ref value1 \<then> + read_reg sideleg_ref) \<bind> (\<lambda> (w__28 :: Sinterrupts) . + return (Some ((get_Sinterrupts_bits w__28 :: 64 Word.word)))) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then - read_reg mie_ref \<bind> (\<lambda> (w__22 :: Minterrupts) . - read_reg mideleg_ref \<bind> (\<lambda> (w__23 :: Minterrupts) . - (write_reg mie_ref ((legalize_sie w__22 w__23 value1)) \<then> - read_reg mie_ref) \<bind> (\<lambda> (w__24 :: Minterrupts) . - return (Some ((get_Minterrupts w__24 :: 64 Word.word)))))) + read_reg mie_ref \<bind> (\<lambda> (w__29 :: Minterrupts) . + read_reg mideleg_ref \<bind> (\<lambda> (w__30 :: Minterrupts) . + (write_reg mie_ref ((legalize_sie w__29 w__30 value1)) \<then> + read_reg mie_ref) \<bind> (\<lambda> (w__31 :: Minterrupts) . + return (Some ((get_Minterrupts_bits w__31 :: 64 Word.word)))))) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then - read_reg stvec_ref \<bind> (\<lambda> (w__25 :: Mtvec) . - (write_reg stvec_ref ((legalize_tvec w__25 value1)) \<then> - read_reg stvec_ref) \<bind> (\<lambda> (w__26 :: Mtvec) . return (Some ((get_Mtvec w__26 :: 64 Word.word))))) + read_reg stvec_ref \<bind> (\<lambda> (w__32 :: Mtvec) . + (write_reg stvec_ref ((legalize_tvec w__32 value1)) \<then> + read_reg stvec_ref) \<bind> (\<lambda> (w__33 :: Mtvec) . + return (Some ((get_Mtvec_bits w__33 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + read_reg scounteren_ref \<bind> (\<lambda> (w__34 :: Counteren) . + (write_reg scounteren_ref ((legalize_scounteren w__34 value1)) \<then> + read_reg scounteren_ref) \<bind> (\<lambda> (w__35 :: Counteren) . + return (Some ((EXTZ (( 64 :: int)::ii) ((get_Counteren_bits w__35 :: 32 Word.word)) :: 64 Word.word))))) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then (write_reg sscratch_ref value1 \<then> - (read_reg sscratch_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__27 :: 64 Word.word) . return (Some w__27)) + (read_reg sscratch_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__36 :: 64 Word.word) . return (Some w__36)) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then - (legalize_xepc value1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: xlenbits) . - (write_reg sepc_ref w__28 \<then> - (read_reg sepc_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__29 :: 64 Word.word) . return (Some w__29))) + (legalize_xepc value1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__37 :: xlenbits) . + (write_reg sepc_ref w__37 \<then> + (read_reg sepc_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__38 :: 64 Word.word) . return (Some w__38))) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then - (set_Mcause scause_ref value1 \<then> - read_reg scause_ref) \<bind> (\<lambda> (w__30 :: Mcause) . - return (Some ((get_Mcause w__30 :: 64 Word.word)))) + (set_Mcause_bits scause_ref value1 \<then> + read_reg scause_ref) \<bind> (\<lambda> (w__39 :: Mcause) . + return (Some ((get_Mcause_bits w__39 :: 64 Word.word)))) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then (write_reg stval_ref value1 \<then> - (read_reg stval_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__31 :: 64 Word.word) . return (Some w__31)) + (read_reg stval_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__40 :: 64 Word.word) . return (Some w__40)) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then - read_reg mip_ref \<bind> (\<lambda> (w__32 :: Minterrupts) . - read_reg mideleg_ref \<bind> (\<lambda> (w__33 :: Minterrupts) . - (write_reg mip_ref ((legalize_sip w__32 w__33 value1)) \<then> - read_reg mip_ref) \<bind> (\<lambda> (w__34 :: Minterrupts) . - return (Some ((get_Minterrupts w__34 :: 64 Word.word)))))) + read_reg mip_ref \<bind> (\<lambda> (w__41 :: Minterrupts) . + read_reg mideleg_ref \<bind> (\<lambda> (w__42 :: Minterrupts) . + (write_reg mip_ref ((legalize_sip w__41 w__42 value1)) \<then> + read_reg mip_ref) \<bind> (\<lambda> (w__43 :: Minterrupts) . + return (Some ((get_Minterrupts_bits w__43 :: 64 Word.word)))))) else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then - cur_Architecture () \<bind> (\<lambda> (w__35 :: Architecture) . - (read_reg satp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__36 :: 64 Word.word) . - (write_reg satp_ref ((legalize_satp w__35 w__36 value1 :: 64 Word.word)) \<then> - (read_reg satp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__37 :: 64 Word.word) . return (Some w__37)))) + cur_Architecture () \<bind> (\<lambda> (w__44 :: Architecture) . + (read_reg satp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__45 :: 64 Word.word) . + (write_reg satp_ref ((legalize_satp w__44 w__45 value1 :: 64 Word.word)) \<then> + (read_reg satp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__46 :: 64 Word.word) . return (Some w__46)))) else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then (write_reg tselect_ref value1 \<then> - (read_reg tselect_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__38 :: 64 Word.word) . return (Some w__38)) + (read_reg tselect_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__47 :: 64 Word.word) . return (Some w__47)) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (write_reg mcycle_ref value1 \<then> + (read_reg mcycle_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__48 :: 64 Word.word) . return (Some w__48)) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + ((write_reg minstret_ref value1 \<then> + write_reg minstret_written_ref True) \<then> + (read_reg minstret_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__49 :: 64 Word.word) . return (Some w__49)) else return None) \<bind> (\<lambda> (res :: xlenbits option) . return ((case res of Some (v) => - prerr_endline + print_endline (((op@) (''CSR '') (((op@) ((csr_name csr)) (((op@) ('' <- '') - (((op@) ((string_of_vec v)) - (((op@) ('' (input: '') (((op@) ((string_of_vec value1)) ('')''))))))))))))) + (((op@) ((string_of_bits v)) + (((op@) ('' (input: '') (((op@) ((string_of_bits value1)) ('')''))))))))))))) | None => print_bits (''unhandled write to CSR '') csr )))))" -definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where - " decode v__0 = ( - if (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1] :: 7 Word.word)))) then - (let (imm :: 20 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (UTYPE (imm,rd,RISCV_LUI)))) - else if (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1] :: 7 Word.word)))) then - (let (imm :: 20 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (UTYPE (imm,rd,RISCV_AUIPC)))) - else if (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))) then - (let (imm :: 20 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RISCV_JAL ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm (( 19 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((subrange_vec_dec imm (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) - ((concat_vec - ((cast_unit_vec0 ((access_vec_dec imm (( 8 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((subrange_vec_dec imm (( 18 :: int)::ii) (( 13 :: int)::ii) :: 6 Word.word)) - ((concat_vec - ((subrange_vec_dec imm (( 12 :: int)::ii) (( 9 :: int)::ii) :: 4 Word.word)) - (vec_of_bits [B0] :: 1 Word.word) - :: 5 Word.word)) - :: 11 Word.word)) - :: 12 Word.word)) - :: 20 Word.word)) - :: 21 Word.word),rd)))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RISCV_JALR (imm,rs1,rd))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) - (vec_of_bits [B0] :: 1 Word.word) - :: 5 Word.word)) - :: 11 Word.word)) - :: 12 Word.word)) - :: 13 Word.word),rs2,rs1,RISCV_BEQ)))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) - (vec_of_bits [B0] :: 1 Word.word) - :: 5 Word.word)) - :: 11 Word.word)) - :: 12 Word.word)) - :: 13 Word.word),rs2,rs1,RISCV_BNE)))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) - (vec_of_bits [B0] :: 1 Word.word) - :: 5 Word.word)) - :: 11 Word.word)) - :: 12 Word.word)) - :: 13 Word.word),rs2,rs1,RISCV_BLT)))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) - (vec_of_bits [B0] :: 1 Word.word) - :: 5 Word.word)) - :: 11 Word.word)) - :: 12 Word.word)) - :: 13 Word.word),rs2,rs1,RISCV_BGE)))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) - (vec_of_bits [B0] :: 1 Word.word) - :: 5 Word.word)) - :: 11 Word.word)) - :: 12 Word.word)) - :: 13 Word.word),rs2,rs1,RISCV_BLTU)))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) - ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) - ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) - (vec_of_bits [B0] :: 1 Word.word) - :: 5 Word.word)) - :: 11 Word.word)) - :: 12 Word.word)) - :: 13 Word.word),rs2,rs1,RISCV_BGEU)))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (ITYPE (imm,rs1,rd,RISCV_ADDI))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (ITYPE (imm,rs1,rd,RISCV_SLTI))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (ITYPE (imm,rs1,rd,RISCV_SLTIU))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (ITYPE (imm,rs1,rd,RISCV_XORI))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (ITYPE (imm,rs1,rd,RISCV_ORI))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (ITYPE (imm,rs1,rd,RISCV_ANDI))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (shamt :: 6 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (shamt :: 6 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (shamt :: 6 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPE (rs2,rs1,rd,RISCV_ADD))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPE (rs2,rs1,rd,RISCV_SUB))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPE (rs2,rs1,rd,RISCV_SLL))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPE (rs2,rs1,rd,RISCV_SLT))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPE (rs2,rs1,rd,RISCV_SLTU))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPE (rs2,rs1,rd,RISCV_XOR))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPE (rs2,rs1,rd,RISCV_SRL))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPE (rs2,rs1,rd,RISCV_SRA))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPE (rs2,rs1,rd,RISCV_OR))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPE (rs2,rs1,rd,RISCV_AND))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (LOAD (imm,rs1,rd,False,BYTE,False,False))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (LOAD (imm,rs1,rd,False,HALF,False,False))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (LOAD (imm,rs1,rd,False,WORD,False,False))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (LOAD (imm,rs1,rd,False,DOUBLE,False,False))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (LOAD (imm,rs1,rd,True,BYTE,False,False))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (LOAD (imm,rs1,rd,True,HALF,False,False))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (LOAD (imm,rs1,rd,True,WORD,False,False))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,BYTE,False,False)))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,HALF,False,False)))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,WORD,False,False)))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,DOUBLE,False,False)))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (ADDIW (imm,rs1,rd))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (shamt :: 5 bits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (SHIFTW (shamt,rs1,rd,RISCV_SLLI))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (shamt :: 5 bits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (SHIFTW (shamt,rs1,rd,RISCV_SRLI))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (shamt :: 5 bits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (SHIFTW (shamt,rs1,rd,RISCV_SRAI))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPEW (rs2,rs1,rd,RISCV_ADDW))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPEW (rs2,rs1,rd,RISCV_SUBW))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPEW (rs2,rs1,rd,RISCV_SLLW))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPEW (rs2,rs1,rd,RISCV_SRLW))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (RTYPEW (rs2,rs1,rd,RISCV_SRAW))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (MUL (rs2,rs1,rd,False,True,True))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (MUL (rs2,rs1,rd,True,True,True))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (MUL (rs2,rs1,rd,True,True,False))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (MUL (rs2,rs1,rd,True,False,False))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (DIV (rs2,rs1,rd,True))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (DIV (rs2,rs1,rd,False))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (REM (rs2,rs1,rd,True))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (REM (rs2,rs1,rd,False))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (MULW (rs2,rs1,rd))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (DIVW (rs2,rs1,rd,True))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (DIVW (rs2,rs1,rd,False))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (REMW (rs2,rs1,rd,True))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (REMW (rs2,rs1,rd,False))))) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] - :: 20 Word.word))))))) then - (let (pred :: 4 bits) = ((subrange_vec_dec v__0 (( 27 :: int)::ii) (( 24 :: int)::ii) :: 4 Word.word)) in - (let (succ :: 4 bits) = ((subrange_vec_dec v__0 (( 23 :: int)::ii) (( 20 :: int)::ii) :: 4 Word.word)) in - Some (FENCE (pred,succ)))) - else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0, - B0,B0,B0,B0,B1,B1,B1,B1] - :: 32 Word.word)))) then - Some (FENCEI () ) - else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B1,B1,B1,B0,B0,B1,B1] - :: 32 Word.word)))) then - Some (ECALL () ) - else if (((v__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B1,B1,B1,B0,B0,B1,B1] - :: 32 Word.word)))) then - Some (MRET () ) - else if (((v__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B1,B1,B1,B0,B0,B1,B1] - :: 32 Word.word)))) then - Some (SRET () ) - else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B1,B1,B1,B0,B0,B1,B1] - :: 32 Word.word)))) then - Some (EBREAK () ) - else if (((v__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B1,B1,B1,B0,B0,B1,B1] - :: 32 Word.word)))) then - Some (WFI () ) - else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0,B1] :: 7 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 0 :: int)::ii) :: 15 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1] :: 15 Word.word))))))) - then - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - Some (SFENCE_VMA (rs1,rs2)))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,WORD,rd)))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,DOUBLE,rd)))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) - else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then - (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in - (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (CSR (csr,rs1,rd,False,CSRRW))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (CSR (csr,rs1,rd,False,CSRRS))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (CSR (csr,rs1,rd,False,CSRRC))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (CSR (csr,rs1,rd,True,CSRRW))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (CSR (csr,rs1,rd,True,CSRRS))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (CSR (csr,rs1,rd,True,CSRRC))))) - else None )" +(*val maybe_i_forwards : bool -> string*) + +fun maybe_i_forwards :: " bool \<Rightarrow> string " where + " maybe_i_forwards True = ( (''i''))" +|" maybe_i_forwards False = ( (''''))" + + +(*val maybe_i_backwards : string -> bool*) + +definition maybe_i_backwards :: " string \<Rightarrow> bool " where + " maybe_i_backwards arg0 = ( + if(arg0 = (''i'')) then True else + (if(arg0 = ('''')) then False else undefined) )" + + +(*val maybe_i_forwards_matches : bool -> bool*) + +fun maybe_i_forwards_matches :: " bool \<Rightarrow> bool " where + " maybe_i_forwards_matches True = ( True )" +|" maybe_i_forwards_matches False = ( True )" + + +(*val maybe_i_backwards_matches : string -> bool*) + +definition maybe_i_backwards_matches :: " string \<Rightarrow> bool " where + " maybe_i_backwards_matches arg0 = ( + if(arg0 = (''i'')) then True else (if(arg0 = ('''')) then True else False) )" + + +(*val maybe_i_matches_prefix : string -> maybe ((bool * ii))*) + +definition maybe_i_matches_prefix :: " string \<Rightarrow>(bool*int)option " where + " maybe_i_matches_prefix arg0 = ( + (let stringappend_16140 = arg0 in + if (((((string_startswith stringappend_16140 (''i''))) \<and> ( + (case ((string_drop stringappend_16140 ((string_length (''i''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16140 ((string_length (''i''))))) of + s0 => Some (True, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16140 (''''))) \<and> ( + (case ((string_drop stringappend_16140 ((string_length (''''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16140 ((string_length (''''))))) of + s0 => Some (False, ((string_length arg0)) - ((string_length s0))) + ) + else None))" + + +(*val csr_mnemonic_forwards : csrop -> string*) + +fun csr_mnemonic_forwards :: " csrop \<Rightarrow> string " where + " csr_mnemonic_forwards CSRRW = ( (''csrrw''))" +|" csr_mnemonic_forwards CSRRS = ( (''csrrs''))" +|" csr_mnemonic_forwards CSRRC = ( (''csrrc''))" + + +(*val csr_mnemonic_backwards : string -> csrop*) + +definition csr_mnemonic_backwards :: " string \<Rightarrow> csrop " where + " csr_mnemonic_backwards arg0 = ( + if(arg0 = (''csrrw'')) then CSRRW else + ( + if(arg0 = (''csrrs'')) then CSRRS else + (if(arg0 = (''csrrc'')) then CSRRC else undefined)) )" + + +(*val csr_mnemonic_forwards_matches : csrop -> bool*) + +fun csr_mnemonic_forwards_matches :: " csrop \<Rightarrow> bool " where + " csr_mnemonic_forwards_matches CSRRW = ( True )" +|" csr_mnemonic_forwards_matches CSRRS = ( True )" +|" csr_mnemonic_forwards_matches CSRRC = ( True )" + + +(*val csr_mnemonic_backwards_matches : string -> bool*) + +definition csr_mnemonic_backwards_matches :: " string \<Rightarrow> bool " where + " csr_mnemonic_backwards_matches arg0 = ( + if(arg0 = (''csrrw'')) then True else + ( + if(arg0 = (''csrrs'')) then True else + (if(arg0 = (''csrrc'')) then True else False)) )" + + +(*val csr_mnemonic_matches_prefix : string -> maybe ((csrop * ii))*) + +definition csr_mnemonic_matches_prefix :: " string \<Rightarrow>(csrop*int)option " where + " csr_mnemonic_matches_prefix arg0 = ( + (let stringappend_16110 = arg0 in + if (((((string_startswith stringappend_16110 (''csrrw''))) \<and> ( + (case ((string_drop stringappend_16110 ((string_length (''csrrw''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16110 ((string_length (''csrrw''))))) of + s0 => Some (CSRRW, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16110 (''csrrs''))) \<and> ( + (case ((string_drop stringappend_16110 ((string_length (''csrrs''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16110 ((string_length (''csrrs''))))) of + s0 => Some (CSRRS, ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_16110 (''csrrc''))) \<and> ( + (case ((string_drop stringappend_16110 ((string_length (''csrrc''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_16110 ((string_length (''csrrc''))))) of + s0 => Some (CSRRC, ((string_length arg0)) - ((string_length s0))) + ) + else None))" definition decodeCompressed :: "(16)Word.word \<Rightarrow>(ast)option " where - " decodeCompressed v__418 = ( - if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then - (let (nzi1 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (nzi0 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + " decodeCompressed v__2 = ( + if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (nzi1 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (nzi0 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in if ((((((nzi1 = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((regbits_to_regno nzi0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) then Some (NOP () ) else None)) - else if (((v__418 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) then - Some (ILLEGAL () ) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then - (let (nz54 :: 2 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word)) in - (let (nz96 :: 4 bits) = ((subrange_vec_dec v__418 (( 10 :: int)::ii) (( 7 :: int)::ii) :: 4 Word.word)) in - (let (nz2 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in - (let (nz3 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in - (let (rd :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (nz54 :: 2 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word)) in + (let (nz96 :: 4 bits) = ((subrange_vec_dec v__2 (( 10 :: int)::ii) (( 7 :: int)::ii) :: 4 Word.word)) in + (let (nz2 :: 1 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (nz3 :: 1 bits) = ((subrange_vec_dec v__2 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in + (let (rd :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in (let nzimm = ((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word)) :: 8 Word.word)) in if (((nzimm = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then None else Some (C_ADDI4SPN (rd,nzimm)))))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then - (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in - (let (rs1 :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (ui2 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in - (let (ui6 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in - (let (rd :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (rs1 :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (ui2 :: 1 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (ui6 :: 1 bits) = ((subrange_vec_dec v__2 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in + (let (rd :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in (let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 :: 4 Word.word)) :: 5 Word.word)) in Some (C_LW (uimm,rs1,rd)))))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then - (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in - (let (rs1 :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in - (let (rd :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (rs1 :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (ui76 :: 2 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (rd :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in (let uimm = ((concat_vec ui76 ui53 :: 5 Word.word)) in Some (C_LD (uimm,rs1,rd))))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then - (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in - (let (rs1 :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (ui2 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in - (let (ui6 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in - (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (rs1 :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (ui2 :: 1 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (ui6 :: 1 bits) = ((subrange_vec_dec v__2 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in (let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 :: 4 Word.word)) :: 5 Word.word)) in Some (C_SW (uimm,rs1,rs2)))))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then - (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in - (let (rs1 :: 3 bits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in - (let (rs2 :: 3 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (rs1 :: 3 bits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (ui76 :: 2 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (rs2 :: 3 bits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in (let uimm = ((concat_vec ui76 ui53 :: 5 Word.word)) in Some (C_SD (uimm,rs1,rs2))))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then - (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in (let nzi = ((concat_vec nzi5 nzi40 :: 6 Word.word)) in if ((((((nzi = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<or> (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then None else Some (C_ADDI (nzi,rsd)))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then - (let (imm5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - (let (imm40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (imm5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (imm40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in Some (C_ADDIW ((concat_vec imm5 imm40 :: 6 Word.word),rsd))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then - (let (imm5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - (let (imm40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (imm5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (imm40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then None else Some (C_LI ((concat_vec imm5 imm40 :: 6 Word.word),rd))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then - (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in - (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in - (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in - (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__2 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in + (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in + (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__2 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in (let nzimm = ((concat_vec nzi9 ((concat_vec nzi87 ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word)) @@ -6148,65 +12773,65 @@ definition decodeCompressed :: "(16)Word.word \<Rightarrow>(ast)option " where :: 6 Word.word)) in if (((nzimm = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then None else Some (C_ADDI16SP nzimm))))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then - (let (imm17 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (imm17 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in if ((((((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) \<or> (((((regbits_to_regno rd)) = ((regbits_to_regno sp)))))))) then None else Some (C_LUI ((concat_vec imm17 imm1612 :: 6 Word.word),rd))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then - (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in (let (shamt :: 6 bits) = ((concat_vec nzui5 nzui40 :: 6 Word.word)) in if (((shamt = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then None else Some (C_SRLI (shamt,rsd)))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then - (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in (let (shamt :: 6 bits) = ((concat_vec nzui5 nzui40 :: 6 Word.word)) in if (((shamt = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then None else Some (C_SRAI (shamt,rsd)))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then - (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (i40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (i5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (i40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in Some (C_ANDI ((concat_vec i5 i40 :: 6 Word.word),rsd))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then - (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in Some (C_SUB (rsd,rs2)))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then - (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in Some (C_XOR (rsd,rs2)))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then - (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in Some (C_OR (rsd,rs2)))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then - (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in Some (C_AND (rsd,rs2)))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then - (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in Some (C_SUBW (rsd,rs2)))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then - (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in Some (C_ADDW (rsd,rs2)))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then - (let (i11 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (i4 :: 1 bits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in - (let (i98 :: 2 bits) = ((subrange_vec_dec v__418 (( 10 :: int)::ii) (( 9 :: int)::ii) :: 2 Word.word)) in - (let (i10 :: 1 bits) = ((subrange_vec_dec v__418 (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word)) in - (let (i6 :: 1 bits) = ((subrange_vec_dec v__418 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in - (let (i7 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in - (let (i31 :: 3 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in - (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (i11 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (i4 :: 1 bits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in + (let (i98 :: 2 bits) = ((subrange_vec_dec v__2 (( 10 :: int)::ii) (( 9 :: int)::ii) :: 2 Word.word)) in + (let (i10 :: 1 bits) = ((subrange_vec_dec v__2 (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word)) in + (let (i6 :: 1 bits) = ((subrange_vec_dec v__2 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in + (let (i7 :: 1 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (i31 :: 3 bits) = ((subrange_vec_dec v__2 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let (i5 :: 1 bits) = ((subrange_vec_dec v__2 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in Some (C_J ((concat_vec i11 ((concat_vec i10 ((concat_vec i98 @@ -6218,108 +12843,110 @@ definition decodeCompressed :: "(16)Word.word \<Rightarrow>(ast)option " where :: 9 Word.word)) :: 10 Word.word)) :: 11 Word.word))))))))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then - (let (i8 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (i43 :: 2 bits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in - (let (rs :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (i76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in - (let (i21 :: 2 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in - (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (i8 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (i43 :: 2 bits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (rs :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (i76 :: 2 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (i21 :: 2 bits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in + (let (i5 :: 1 bits) = ((subrange_vec_dec v__2 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in Some (C_BEQZ ((concat_vec i8 ((concat_vec i76 ((concat_vec i5 ((concat_vec i43 i21 :: 4 Word.word)) :: 5 Word.word)) :: 7 Word.word)) :: 8 Word.word),rs)))))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then - (let (i8 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (i43 :: 2 bits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in - (let (rs :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (i76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in - (let (i21 :: 2 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in - (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (i8 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (i43 :: 2 bits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (rs :: cregbits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (i76 :: 2 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (i21 :: 2 bits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in + (let (i5 :: 1 bits) = ((subrange_vec_dec v__2 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in Some (C_BNEZ ((concat_vec i8 ((concat_vec i76 ((concat_vec i5 ((concat_vec i43 i21 :: 4 Word.word)) :: 5 Word.word)) :: 7 Word.word)) :: 8 Word.word),rs)))))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then - (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in (let (shamt :: 6 bits) = ((concat_vec nzui5 nzui40 :: 6 Word.word)) in if ((((((shamt = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<or> (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then None else Some (C_SLLI (shamt,rsd)))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then - (let (ui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - (let (ui42 :: 3 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 4 :: int)::ii) :: 3 Word.word)) in - (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (ui5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (ui42 :: 3 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 4 :: int)::ii) :: 3 Word.word)) in + (let (ui76 :: 2 bits) = ((subrange_vec_dec v__2 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in (let (uimm :: 6 bits) = ((concat_vec ui76 ((concat_vec ui5 ui42 :: 4 Word.word)) :: 6 Word.word)) in if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then None else Some (C_LWSP (uimm,rd))))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then - (let (ui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - (let (ui43 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in - (let (ui86 :: 3 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (ui5 :: 1 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (ui43 :: 2 bits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (ui86 :: 3 bits) = ((subrange_vec_dec v__2 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in (let (uimm :: 6 bits) = ((concat_vec ui86 ((concat_vec ui5 ui43 :: 3 Word.word)) :: 6 Word.word)) in if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then None else Some (C_LDSP (uimm,rd))))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then - (let (ui52 :: 4 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 9 :: int)::ii) :: 4 Word.word)) in - (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 8 :: int)::ii) (( 7 :: int)::ii) :: 2 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (ui52 :: 4 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 9 :: int)::ii) :: 4 Word.word)) in + (let (ui76 :: 2 bits) = ((subrange_vec_dec v__2 (( 8 :: int)::ii) (( 7 :: int)::ii) :: 2 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in (let (uimm :: 6 bits) = ((concat_vec ui76 ui52 :: 6 Word.word)) in Some (C_SWSP (uimm,rs2)))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then - (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in - (let (ui86 :: 3 bits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__2 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (ui86 :: 3 bits) = ((subrange_vec_dec v__2 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in (let (uimm :: 6 bits) = ((concat_vec ui86 ui53 :: 6 Word.word)) in Some (C_SDSP (uimm,rs2)))))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word))))))) then - (let (rs1 :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word))))))) then + (let (rs1 :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then None else Some (C_JR rs1)) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word))))))) then - (let (rs1 :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word))))))) then + (let (rs1 :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then None else Some (C_JALR rs1)) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then - (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (rd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in if ((((((((regbits_to_regno rs2)) = ((regbits_to_regno zreg))))) \<or> (((((regbits_to_regno rd)) = ((regbits_to_regno zreg)))))))) then None else Some (C_MV (rd,rs2)))) - else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then - (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + else if ((((((((subrange_vec_dec v__2 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__2 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (rsd :: regbits) = ((subrange_vec_dec v__2 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__2 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in if ((((((((regbits_to_regno rsd)) = ((regbits_to_regno zreg))))) \<or> (((((regbits_to_regno rs2)) = ((regbits_to_regno zreg)))))))) then None else Some (C_ADD (rsd,rs2)))) + else if (((v__2 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) then + Some (C_ILLEGAL () ) else None )" -(*val execute_WFI : unit -> M unit*) +(*val execute_WFI : unit -> M bool*) -fun execute_WFI :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_WFI g__110 = ( +fun execute_WFI :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " execute_WFI g__26 = ( read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . (case w__0 of - Machine => return () + Machine => return True | Supervisor => read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) . if (((((get_Mstatus_TW w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then - handle_illegal () - else return () ) - | User => handle_illegal () + handle_illegal () \<then> return False + else return True) + | User => handle_illegal () \<then> return False )))" -(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M unit*) +(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M bool*) -fun execute_UTYPE :: "(20)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> uop \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_UTYPE :: "(20)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> uop \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_UTYPE imm rd op1 = ( (let (off :: xlenbits) = ((EXTS (( 64 :: int)::ii) @@ -6332,93 +12959,122 @@ fun execute_UTYPE :: "(20)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> uo (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . return ((add_vec w__0 off :: 64 Word.word))) ) \<bind> (\<lambda> (ret :: xlenbits) . - wX ((regbits_to_regno rd)) ret)))" + wX ((regbits_to_regno rd)) ret \<then> return True)))" + +(*val execute_THREAD_START : unit -> bool*) -(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*) +fun execute_THREAD_START :: " unit \<Rightarrow> bool " where + " execute_THREAD_START g__29 = ( True )" -fun execute_STORECON :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + +(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M bool*) + +fun execute_STORECON :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_STORECON aq rl rs2 rs1 width rd = ( - speculate_conditional_success () \<bind> (\<lambda> (w__0 :: bool) . - (let (status :: 1 bits) = - (if w__0 then (vec_of_bits [B0] :: 1 Word.word) - else (vec_of_bits [B1] :: 1 Word.word)) in - wX ((regbits_to_regno rd)) ((EXTZ (( 64 :: int)::ii) status :: 64 Word.word)) \<then> - (if (((status = (vec_of_bits [B1] :: 1 Word.word)))) then return () + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (vaddr :: xlenbits) . + (let (aligned :: bool) = + ((case width of + BYTE => True + | HALF => + (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii))) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)) + | WORD => + (((subrange_vec_dec vaddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)) + | DOUBLE => + (((subrange_vec_dec vaddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)) + )) in + if ((\<not> aligned)) then handle_mem_exception vaddr E_SAMO_Addr_Align \<then> return False + else + speculate_conditional_success vaddr \<bind> (\<lambda> (w__0 :: bool) . + if (((((bool_to_bits w__0 :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) then + wX ((regbits_to_regno rd)) ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) \<then> + return True + else + translateAddr vaddr Write Data \<bind> (\<lambda> (w__1 :: TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e \<then> return False + | TR_Address (addr) => + (case width of + WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl True + | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl True + | _ => internal_error (''STORECON expected word or double'') + ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e \<then> return False + | MemValue (_) => + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . + (case width of + WORD => + mem_write_value addr (( 4 :: int)::ii) + ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) aq rl True + | DOUBLE => mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl True + | _ => internal_error (''STORECON expected word or double'') + ) \<bind> (\<lambda> (res :: unit MemoryOpResult) . + (case res of + MemValue (_) => + wX ((regbits_to_regno rd)) + ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) \<then> + ((let (_ :: unit) = (cancel_reservation () ) in + return True)) + | MemException (e) => handle_mem_exception addr e \<then> return False + ))) + )) + ))))))" + + +(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M bool*) + +fun execute_STORE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where + " execute_STORE imm rs2 rs1 width aq rl = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let (vaddr :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in + if ((check_misaligned vaddr width)) then + handle_mem_exception vaddr E_SAMO_Addr_Align \<then> return False else - (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (vaddr :: xlenbits) . translateAddr vaddr Write Data \<bind> (\<lambda> (w__1 :: TR_Result) . (case w__1 of - TR_Failure (e) => handle_mem_exception vaddr e + TR_Failure (e) => handle_mem_exception vaddr e \<then> return False | TR_Address (addr) => (case width of - WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl True - | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl True - | _ => internal_error (''STORECON expected word or double'') + BYTE => mem_write_ea addr (( 1 :: int)::ii) aq rl False + | HALF => mem_write_ea addr (( 2 :: int)::ii) aq rl False + | WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl False + | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl False ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) . (case eares of - MemException (e) => handle_mem_exception addr e + MemException (e) => handle_mem_exception addr e \<then> return False | MemValue (_) => (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . (case width of - WORD => + BYTE => + mem_write_value addr (( 1 :: int)::ii) ((subrange_vec_dec rs2_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) aq + rl False + | HALF => + mem_write_value addr (( 2 :: int)::ii) ((subrange_vec_dec rs2_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + aq rl False + | WORD => mem_write_value addr (( 4 :: int)::ii) ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) - aq rl True - | DOUBLE => mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl True - | _ => internal_error (''STORECON expected word or double'') + aq rl False + | DOUBLE => mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl False ) \<bind> (\<lambda> (res :: unit MemoryOpResult) . (case res of - MemValue (_) => return () - | MemException (e) => handle_mem_exception addr e + MemValue (_) => return True + | MemException (e) => handle_mem_exception addr e \<then> return False ))) )) - )))))))" + )))))" -(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M unit*) +(*val execute_STOP_FETCHING : unit -> bool*) -fun execute_STORE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_STORE imm rs2 rs1 width aq rl = ( - (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (let (vaddr :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in - translateAddr vaddr Write Data \<bind> (\<lambda> (w__1 :: TR_Result) . - (case w__1 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => - (case width of - BYTE => mem_write_ea addr (( 1 :: int)::ii) aq rl False - | HALF => mem_write_ea addr (( 2 :: int)::ii) aq rl False - | WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl False - | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl False - ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) . - (case eares of - MemException (e) => handle_mem_exception addr e - | MemValue (_) => - (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . - (case width of - BYTE => - mem_write_value addr (( 1 :: int)::ii) ((subrange_vec_dec rs2_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) aq - rl False - | HALF => - mem_write_value addr (( 2 :: int)::ii) ((subrange_vec_dec rs2_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) aq - rl False - | WORD => - mem_write_value addr (( 4 :: int)::ii) ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) aq - rl False - | DOUBLE => mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl False - ) \<bind> (\<lambda> (res :: unit MemoryOpResult) . - (case res of - MemValue (_) => return () - | MemException (e) => handle_mem_exception addr e - ))) - )) - )))))" +fun execute_STOP_FETCHING :: " unit \<Rightarrow> bool " where + " execute_STOP_FETCHING g__28 = ( True )" -(*val execute_SRET : unit -> M unit*) +(*val execute_SRET : unit -> M bool*) -fun execute_SRET :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_SRET g__108 = ( +fun execute_SRET :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " execute_SRET g__24 = ( read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . (case w__0 of User => handle_illegal () @@ -6436,12 +13092,13 @@ fun execute_SRET :: " unit \<Rightarrow>((register_value),(unit),(exception))m (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 Word.word) . (handle_exception w__5 (CTL_SRET () ) w__6 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: xlenbits) . write_reg nextPC_ref w__7))) - )))" + ) \<then> + return False))" -(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M unit*) +(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M bool*) -fun execute_SHIFTW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_SHIFTW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_SHIFTW shamt rs1 rd op1 = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in @@ -6451,12 +13108,12 @@ fun execute_SHIFTW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5) | RISCV_SRLI => (shift_bits_right rs1_val shamt :: 32 Word.word) | RISCV_SRAI => (shift_right_arith32 rs1_val shamt :: 32 Word.word) )) in - wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) result :: 64 Word.word))))))" + wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) result :: 64 Word.word)) \<then> return True))))" -(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M unit*) +(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M bool*) -fun execute_SHIFTIOP :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_SHIFTIOP :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_SHIFTIOP shamt rs1 rd op1 = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . (let (result :: xlenbits) = @@ -6465,26 +13122,26 @@ fun execute_SHIFTIOP :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>( | RISCV_SRLI => (shift_bits_right rs1_val shamt :: 64 Word.word) | RISCV_SRAI => (shift_right_arith64 rs1_val shamt :: 64 Word.word) )) in - wX ((regbits_to_regno rd)) result)))" + wX ((regbits_to_regno rd)) result \<then> return True)))" -(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M unit*) +(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M bool*) -fun execute_SFENCE_VMA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_SFENCE_VMA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_SFENCE_VMA rs1 rs2 = ( read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . if (((((privLevel_to_bits w__0 :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))) then - handle_illegal () + handle_illegal () \<then> return False else read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) . read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . - (let p__104 = + (let p__20 = (architecture ((get_Mstatus_SXL w__1 :: 2 Word.word)), (get_Mstatus_TVM w__2 :: 1 Word.word)) in - (case p__104 of + (case p__20 of (Some (RV64), v_0) => - if (((v_0 = ((bool_to_bits True :: 1 Word.word))))) then handle_illegal () - else + if (((v_0 = ((bool_to_bits True :: 1 Word.word))))) then handle_illegal () \<then> return False + else if (((v_0 = ((bool_to_bits False :: 1 Word.word))))) then (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then return None else (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . @@ -6495,14 +13152,18 @@ fun execute_SFENCE_VMA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . return (Some ((subrange_vec_dec w__4 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word))))) \<bind> (\<lambda> (asid :: asid64 option) . - flushTLB asid addr)) - | (g__102, g__103) => internal_error (''unimplemented sfence architecture'') + flushTLB asid addr \<then> return True)) + else + (case (Some RV64, v_0) of + (g__18, g__19) => internal_error (''unimplemented sfence architecture'') + ) + | (g__18, g__19) => internal_error (''unimplemented sfence architecture'') ))))))" -(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M unit*) +(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M bool*) -fun execute_RTYPEW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> ropw \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_RTYPEW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> ropw \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_RTYPEW rs2 rs1 rd op1 = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in @@ -6522,12 +13183,12 @@ fun execute_RTYPEW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5) (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) :: 32 Word.word) )) in - wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) result :: 64 Word.word))))))))" + wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) result :: 64 Word.word)) \<then> return True))))))" -(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M unit*) +(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M bool*) -fun execute_RTYPE :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> rop \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_RTYPE :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> rop \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_RTYPE rs2 rs1 rd op1 = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . @@ -6552,12 +13213,12 @@ fun execute_RTYPE :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)W | RISCV_OR => (or_vec rs1_val rs2_val :: 64 Word.word) | RISCV_AND => (and_vec rs1_val rs2_val :: 64 Word.word) )) in - wX ((regbits_to_regno rd)) result))))" + wX ((regbits_to_regno rd)) result \<then> return True))))" -(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) +(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M bool*) -fun execute_RISCV_JALR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_RISCV_JALR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_RISCV_JALR imm rs1 rd = ( (read_reg nextPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (wX ((regbits_to_regno rd)) w__0 \<then> @@ -6567,23 +13228,24 @@ fun execute_RISCV_JALR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarro nextPC_ref ((concat_vec ((subrange_vec_dec newPC (( 63 :: int)::ii) (( 1 :: int)::ii) :: 63 Word.word)) (vec_of_bits [B0] :: 1 Word.word) - :: 64 Word.word))))))" + :: 64 Word.word)) \<then> + return True))))" -(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M unit*) +(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M bool*) -fun execute_RISCV_JAL :: "(21)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_RISCV_JAL :: "(21)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_RISCV_JAL imm rd = ( (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (pc :: xlenbits) . (read_reg nextPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wX ((regbits_to_regno rd)) w__0 \<then> ((let (offset :: xlenbits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in - write_reg nextPC_ref ((add_vec pc offset :: 64 Word.word)))))))" + write_reg nextPC_ref ((add_vec pc offset :: 64 Word.word)) \<then> return True)))))" -(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) +(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*) -fun execute_REMW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_REMW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_REMW rs2 rs1 rd s = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in @@ -6592,30 +13254,31 @@ fun execute_REMW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wo (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in (let (r :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in - wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) r :: 32 Word.word)) :: 64 Word.word))))))))))" + wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) r :: 32 Word.word)) :: 64 Word.word)) \<then> + return True))))))))" -(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) +(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*) -fun execute_REM :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_REM :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_REM rs2 rs1 rd s = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in (let (r :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in - wX ((regbits_to_regno rd)) ((to_bits xlen r :: 64 Word.word))))))))" + wX ((regbits_to_regno rd)) ((to_bits xlen r :: 64 Word.word)) \<then> return True))))))" -(*val execute_NOP : unit -> unit*) +(*val execute_NOP : unit -> bool*) -fun execute_NOP :: " unit \<Rightarrow> unit " where - " execute_NOP g__111 = ( () )" +fun execute_NOP :: " unit \<Rightarrow> bool " where + " execute_NOP g__27 = ( True )" -(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) +(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M bool*) -fun execute_MULW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_MULW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_MULW rs2 rs1 rd = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in @@ -6628,12 +13291,12 @@ fun execute_MULW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wo (( 0 :: int)::ii) :: 32 Word.word)) in (let (result :: xlenbits) = ((EXTS (( 64 :: int)::ii) result32 :: 64 Word.word)) in - wX ((regbits_to_regno rd)) result)))))))))" + wX ((regbits_to_regno rd)) result \<then> return True)))))))))" -(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M unit*) +(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M bool*) -fun execute_MUL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_MUL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_MUL rs2 rs1 rd high signed1 signed2 = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . @@ -6643,80 +13306,96 @@ fun execute_MUL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wor (let result = (if high then (subrange_vec_dec result128 (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word) else (subrange_vec_dec result128 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) in - wX ((regbits_to_regno rd)) result)))))))" + wX ((regbits_to_regno rd)) result \<then> return True)))))))" -(*val execute_MRET : unit -> M unit*) +(*val execute_MRET : unit -> M bool*) -fun execute_MRET :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_MRET g__107 = ( +fun execute_MRET :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " execute_MRET g__23 = ( read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . - if (((((privLevel_to_bits w__0 :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) - then - read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) . - (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . - (handle_exception w__1 (CTL_MRET () ) w__2 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . - write_reg nextPC_ref w__3))) - else handle_illegal () ))" + (if (((((privLevel_to_bits w__0 :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) + then + read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + (handle_exception w__1 (CTL_MRET () ) w__2 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . + write_reg nextPC_ref w__3))) + else handle_illegal () ) \<then> + return False))" -(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M unit*) +(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M bool*) -fun execute_LOADRES :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_LOADRES :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_LOADRES aq rl rs1 width rd = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (vaddr :: xlenbits) . - translateAddr vaddr Read Data \<bind> (\<lambda> (w__0 :: TR_Result) . - (case w__0 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => - (case width of - WORD => - (mem_read addr (( 4 :: int)::ii) aq rl True :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__1 :: ( 32 Word.word) - MemoryOpResult) . - process_load rd addr w__1 False) - | DOUBLE => - (mem_read addr (( 8 :: int)::ii) aq rl True :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__2 :: ( 64 Word.word) - MemoryOpResult) . - process_load rd addr w__2 False) - | _ => internal_error (''LOADRES expected WORD or DOUBLE'') - ) - ))))" + (let (aligned :: bool) = + ((case width of + BYTE => True + | HALF => + (((cast_unit_vec0 ((access_vec_dec vaddr (( 0 :: int)::ii))) :: 1 Word.word)) = (vec_of_bits [B0] :: 1 Word.word)) + | WORD => + (((subrange_vec_dec vaddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)) + | DOUBLE => + (((subrange_vec_dec vaddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)) + )) in + if ((\<not> aligned)) then handle_mem_exception vaddr E_SAMO_Addr_Align \<then> return False + else + translateAddr vaddr Read Data \<bind> (\<lambda> (w__0 :: TR_Result) . + (case w__0 of + TR_Failure (e) => handle_mem_exception vaddr e \<then> return False + | TR_Address (addr) => + (case width of + WORD => + (mem_read addr (( 4 :: int)::ii) aq rl True :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__1 :: ( 32 Word.word) + MemoryOpResult) . + process_loadres rd vaddr w__1 False) + | DOUBLE => + (mem_read addr (( 8 :: int)::ii) aq rl True :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__3 :: ( 64 Word.word) + MemoryOpResult) . + process_loadres rd vaddr w__3 False) + | _ => internal_error (''LOADRES expected WORD or DOUBLE'') + ) + )))))" -(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M unit*) +(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M bool*) -fun execute_LOAD :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_LOAD :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_LOAD imm rs1 rd is_unsigned width aq rl = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let (vaddr :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in - translateAddr vaddr Read Data \<bind> (\<lambda> (w__1 :: TR_Result) . - (case w__1 of - TR_Failure (e) => handle_mem_exception vaddr e - | TR_Address (addr) => - (case width of - BYTE => - (mem_read addr (( 1 :: int)::ii) aq rl False :: ( ( 8 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__2 :: ( 8 Word.word) - MemoryOpResult) . - process_load rd vaddr w__2 is_unsigned) - | HALF => - (mem_read addr (( 2 :: int)::ii) aq rl False :: ( ( 16 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__3 :: ( 16 Word.word) - MemoryOpResult) . - process_load rd vaddr w__3 is_unsigned) - | WORD => - (mem_read addr (( 4 :: int)::ii) aq rl False :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__4 :: ( 32 Word.word) - MemoryOpResult) . - process_load rd vaddr w__4 is_unsigned) - | DOUBLE => - (mem_read addr (( 8 :: int)::ii) aq rl False :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__5 :: ( 64 Word.word) - MemoryOpResult) . - process_load rd vaddr w__5 is_unsigned) - ) - )))))" + if ((check_misaligned vaddr width)) then + handle_mem_exception vaddr E_Load_Addr_Align \<then> return False + else + translateAddr vaddr Read Data \<bind> (\<lambda> (w__1 :: TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e \<then> return False + | TR_Address (addr) => + (case width of + BYTE => + (mem_read addr (( 1 :: int)::ii) aq rl False :: ( ( 8 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__2 :: ( 8 Word.word) + MemoryOpResult) . + process_load rd vaddr w__2 is_unsigned) + | HALF => + (mem_read addr (( 2 :: int)::ii) aq rl False :: ( ( 16 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__4 :: ( 16 Word.word) + MemoryOpResult) . + process_load rd vaddr w__4 is_unsigned) + | WORD => + (mem_read addr (( 4 :: int)::ii) aq rl False :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__6 :: ( 32 Word.word) + MemoryOpResult) . + process_load rd vaddr w__6 is_unsigned) + | DOUBLE => + (mem_read addr (( 8 :: int)::ii) aq rl False :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__8 :: ( 64 Word.word) + MemoryOpResult) . + process_load rd vaddr w__8 is_unsigned) + ) + )))))" -(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M unit*) +(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M bool*) -fun execute_ITYPE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> iop \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_ITYPE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> iop \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_ITYPE imm rs1 rd op1 = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . (let (immext :: xlenbits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in @@ -6731,40 +13410,59 @@ fun execute_ITYPE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5) | RISCV_ORI => (or_vec rs1_val immext :: 64 Word.word) | RISCV_ANDI => (and_vec rs1_val immext :: 64 Word.word) )) in - wX ((regbits_to_regno rd)) result))))" + wX ((regbits_to_regno rd)) result \<then> return True))))" -(*val execute_ILLEGAL : unit -> M unit*) +(*val execute_ILLEGAL : mword ty32 -> M bool*) -fun execute_ILLEGAL :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_ILLEGAL g__112 = ( handle_illegal () )" +fun execute_ILLEGAL :: "(32)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where + " execute_ILLEGAL s = ( handle_illegal () \<then> return False )" -(*val execute_FENCEI : unit -> M unit*) +(*val execute_FENCEI : unit -> M bool*) -fun execute_FENCEI :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_FENCEI g__105 = ( MEM_fence_i () )" +fun execute_FENCEI :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " execute_FENCEI g__21 = ( MEM_fence_i () \<then> return True )" -(*val execute_FENCE : mword ty4 -> mword ty4 -> M unit*) +(*val execute_FENCE : mword ty4 -> mword ty4 -> M bool*) -fun execute_FENCE :: "(4)Word.word \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_FENCE b__0 b__1 = ( - if ((((((b__0 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) \<and> (((b__1 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word))))))) then +fun execute_FENCE :: "(4)Word.word \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where + " execute_FENCE pred succ = ( + (case (pred, succ) of + (v__132, v__133) => + if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then MEM_fence_rw_rw () - else if ((((((b__0 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) \<and> (((b__1 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word))))))) then + else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then MEM_fence_r_rw () - else if ((((((b__0 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) \<and> (((b__1 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word))))))) then + else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then MEM_fence_r_r () - else if ((((((b__0 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) \<and> (((b__1 = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word))))))) then + else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then MEM_fence_rw_w () - else MEM_fence_w_w () )" + else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + MEM_fence_w_w () + else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + MEM_fence_w_rw () + else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + MEM_fence_rw_r () + else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + MEM_fence_r_w () + else if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + MEM_fence_w_r () + else + return (if ((((((((subrange_vec_dec v__132 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__133 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + () + else + (let (_ :: unit) = (print_endline (''FIXME: unsupported fence'')) in + () )) + ) \<then> + return True )" -(*val execute_ECALL : unit -> M unit*) +(*val execute_ECALL : unit -> M bool*) -fun execute_ECALL :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_ECALL g__106 = ( +fun execute_ECALL :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " execute_ECALL g__22 = ( read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . (let (t :: sync_exception) = ((| sync_exception_trap = @@ -6777,18 +13475,20 @@ fun execute_ECALL :: " unit \<Rightarrow>((register_value),(unit),(exception)) read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) . (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . (handle_exception w__1 (CTL_TRAP t) w__2 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . - write_reg nextPC_ref w__3))))))" + write_reg nextPC_ref w__3 \<then> return False))))))" -(*val execute_EBREAK : unit -> M unit*) +(*val execute_EBREAK : unit -> M bool*) -fun execute_EBREAK :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where - " execute_EBREAK g__109 = ( throw (Error_EBREAK () ))" +fun execute_EBREAK :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " execute_EBREAK g__25 = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + handle_mem_exception w__0 E_Breakpoint \<then> return False))" -(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) +(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*) -fun execute_DIVW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_DIVW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_DIVW rs2 rs1 rd s = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in @@ -6801,12 +13501,13 @@ fun execute_DIVW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wo (if (((s \<and> ((q > ((((pow2 (( 31 :: int)::ii))) - (( 1 :: int)::ii)))))))) then (( 0 :: int)::ii) - ((ex_int ((pow (( 2 :: int)::ii) (( 31 :: int)::ii))))) else q) in - wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) q' :: 32 Word.word)) :: 64 Word.word)))))))))))" + wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) q' :: 32 Word.word)) :: 64 Word.word)) \<then> + return True)))))))))" -(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) +(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M bool*) -fun execute_DIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_DIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_DIV rs2 rs1 rd s = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . @@ -6814,23 +13515,29 @@ fun execute_DIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wor (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in (let (q :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then ((( 0 :: int)-( 1 :: int))::ii) else hardware_quot rs1_int rs2_int) in (let (q' :: ii) = (if (((s \<and> ((q > xlen_max_signed))))) then xlen_min_signed else q) in - wX ((regbits_to_regno rd)) ((to_bits xlen q' :: 64 Word.word)))))))))" + wX ((regbits_to_regno rd)) ((to_bits xlen q' :: 64 Word.word)) \<then> return True)))))))" -(*val execute_C_ADDIW : mword ty6 -> mword ty5 -> M unit*) +(*val execute_C_ILLEGAL : unit -> M bool*) -fun execute_C_ADDIW :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_C_ILLEGAL :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " execute_C_ILLEGAL g__30 = ( handle_illegal () \<then> return False )" + + +(*val execute_C_ADDIW : mword ty6 -> mword ty5 -> M bool*) + +fun execute_C_ADDIW :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_C_ADDIW imm rsd = ( (let (imm :: 32 bits) = ((EXTS (( 32 :: int)::ii) imm :: 32 Word.word)) in (rX ((regbits_to_regno rsd)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . (let (res :: 32 bits) = ((add_vec ((subrange_vec_dec rs_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) imm :: 32 Word.word)) in - wX ((regbits_to_regno rsd)) ((EXTS (( 64 :: int)::ii) res :: 64 Word.word))))))" + wX ((regbits_to_regno rsd)) ((EXTS (( 64 :: int)::ii) res :: 64 Word.word)) \<then> return True))))" -(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M unit*) +(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M bool*) -fun execute_CSR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> csrop \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_CSR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> csrop \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_CSR csr rs1 rd is_imm op1 = ( (if is_imm then return ((EXTZ (( 64 :: int)::ii) rs1 :: 64 Word.word)) else (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M)) \<bind> (\<lambda> (rs1_val :: xlenbits) . @@ -6841,10 +13548,10 @@ fun execute_CSR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wo )) in read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) . check_CSR csr w__1 isWrite \<bind> (\<lambda> (w__2 :: bool) . - if ((\<not> w__2)) then handle_illegal () + if ((\<not> w__2)) then handle_illegal () \<then> return False else (readCSR csr :: ( 64 Word.word) M) \<bind> (\<lambda> csr_val . - (if isWrite then + ((if isWrite then (let (new_val :: xlenbits) = ((case op1 of CSRRW => rs1_val @@ -6853,12 +13560,12 @@ fun execute_CSR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Wo )) in writeCSR csr new_val) else return () ) \<then> - wX ((regbits_to_regno rd)) csr_val))))))" + wX ((regbits_to_regno rd)) csr_val) \<then> return True))))))" -(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M unit*) +(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M bool*) -fun execute_BTYPE :: "(13)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bop \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_BTYPE :: "(13)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bop \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_BTYPE imm rs2 rs1 op1 = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . @@ -6871,20 +13578,21 @@ fun execute_BTYPE :: "(13)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5) | RISCV_BLTU => zopz0zI_u rs1_val rs2_val | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val )) in - if taken then - (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - write_reg nextPC_ref ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))) - else return () ))))" + (if taken then + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + write_reg nextPC_ref ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))) + else return () ) \<then> + return True))))" -(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*) +(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M bool*) -fun execute_AMO :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_AMO :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_AMO op1 aq rl rs2 rs1 width rd = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (vaddr :: xlenbits) . translateAddr vaddr ReadWrite Data \<bind> (\<lambda> (w__0 :: TR_Result) . (case w__0 of - TR_Failure (e) => handle_mem_exception vaddr e + TR_Failure (e) => handle_mem_exception vaddr e \<then> return False | TR_Address (addr) => (case width of WORD => mem_write_ea addr (( 4 :: int)::ii) (((aq \<and> rl))) rl True @@ -6892,7 +13600,7 @@ fun execute_AMO :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> | _ => internal_error (''AMO expected WORD or DOUBLE'') ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) . (case eares of - MemException (e) => handle_mem_exception addr e + MemException (e) => handle_mem_exception addr e \<then> return False | MemValue (_) => (case width of WORD => @@ -6906,7 +13614,7 @@ fun execute_AMO :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> | _ => (internal_error (''AMO expected WORD or DOUBLE'') :: ( ( 64 Word.word)MemoryOpResult) M) ) \<bind> (\<lambda> (rval :: xlenbits MemoryOpResult) . (case rval of - MemException (e) => handle_mem_exception addr e + MemException (e) => handle_mem_exception addr e \<then> return False | MemValue (loaded) => (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (rs2_val :: xlenbits) . (let (result :: xlenbits) = @@ -6929,25 +13637,26 @@ fun execute_AMO :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> | _ => internal_error (''AMO expected WORD or DOUBLE'') ) \<bind> (\<lambda> (wval :: unit MemoryOpResult) . (case wval of - MemValue (_) => wX ((regbits_to_regno rd)) loaded - | MemException (e) => handle_mem_exception addr e + MemValue (_) => wX ((regbits_to_regno rd)) loaded \<then> return True + | MemException (e) => handle_mem_exception addr e \<then> return False )))) )) )) ))))" -(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) +(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M bool*) -fun execute_ADDIW :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where +fun execute_ADDIW :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where " execute_ADDIW imm rs1 rd = ( (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let (result :: xlenbits) = ((add_vec ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) w__0 :: 64 Word.word)) in wX ((regbits_to_regno rd)) - ((EXTS (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))" + ((EXTS (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + return True)))" -function (sequential,domintros) execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " where +function (sequential,domintros) execute :: " ast \<Rightarrow>((register_value),(bool),(exception))monad " where " execute (C_ADDI4SPN (rdc,nzimm)) = ( (let (imm :: 12 bits) = ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word) @@ -7092,307 +13801,10037 @@ function (sequential,domintros) execute :: " ast \<Rightarrow>((register_value |" execute (DIVW (rs2,rs1,rd,s)) = ( execute_DIVW rs2 rs1 rd s )" |" execute (REMW (rs2,rs1,rd,s)) = ( execute_REMW rs2 rs1 rd s )" |" execute (FENCE (pred,succ)) = ( execute_FENCE pred succ )" -|" execute (FENCEI (g__105)) = ( execute_FENCEI g__105 )" -|" execute (ECALL (g__106)) = ( execute_ECALL g__106 )" -|" execute (MRET (g__107)) = ( execute_MRET g__107 )" -|" execute (SRET (g__108)) = ( execute_SRET g__108 )" -|" execute (EBREAK (g__109)) = ( execute_EBREAK g__109 )" -|" execute (WFI (g__110)) = ( execute_WFI g__110 )" +|" execute (FENCEI (g__21)) = ( execute_FENCEI g__21 )" +|" execute (ECALL (g__22)) = ( execute_ECALL g__22 )" +|" execute (MRET (g__23)) = ( execute_MRET g__23 )" +|" execute (SRET (g__24)) = ( execute_SRET g__24 )" +|" execute (EBREAK (g__25)) = ( execute_EBREAK g__25 )" +|" execute (WFI (g__26)) = ( execute_WFI g__26 )" |" execute (SFENCE_VMA (rs1,rs2)) = ( execute_SFENCE_VMA rs1 rs2 )" |" execute (LOADRES (aq,rl,rs1,width,rd)) = ( execute_LOADRES aq rl rs1 width rd )" |" execute (STORECON (aq,rl,rs2,rs1,width,rd)) = ( execute_STORECON aq rl rs2 rs1 width rd )" |" execute (AMO (op1,aq,rl,rs2,rs1,width,rd)) = ( execute_AMO op1 aq rl rs2 rs1 width rd )" |" execute (CSR (csr,rs1,rd,is_imm,op1)) = ( execute_CSR csr rs1 rd is_imm op1 )" -|" execute (NOP (g__111)) = ( return ((execute_NOP g__111)))" -|" execute (ILLEGAL (g__112)) = ( execute_ILLEGAL g__112 )" -|" execute (C_ADDIW (imm,rsd)) = ( execute_C_ADDIW imm rsd )" +|" execute (NOP (g__27)) = ( return ((execute_NOP g__27)))" +|" execute (C_ADDIW (imm,rsd)) = ( execute_C_ADDIW imm rsd )" +|" execute (STOP_FETCHING (g__28)) = ( return ((execute_STOP_FETCHING g__28)))" +|" execute (THREAD_START (g__29)) = ( return ((execute_THREAD_START g__29)))" +|" execute (ILLEGAL (s)) = ( execute_ILLEGAL s )" +|" execute (C_ILLEGAL (g__30)) = ( execute_C_ILLEGAL g__30 )" by pat_completeness auto +(*val assembly_forwards : ast -> string*) + +fun assembly_forwards :: " ast \<Rightarrow> string " where + " assembly_forwards (UTYPE (imm,rd,op1)) = ( + string_append ((utype_mnemonic_forwards op1)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) ((string_append ((string_of_bits imm)) (''''))))))))))" +|" assembly_forwards (RISCV_JAL (imm,rd)) = ( + string_append (''jal'') + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) ((string_append ((string_of_bits imm)) (''''))))))))))" +|" assembly_forwards (RISCV_JALR (imm,rs1,rd)) = ( + string_append (''jalr'') + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits imm)) (''''))))))))))))))" +|" assembly_forwards (BTYPE (imm,rs2,rs1,op1)) = ( + string_append ((btype_mnemonic_forwards op1)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits imm)) (''''))))))))))))))" +|" assembly_forwards (ITYPE (imm,rs1,rd,op1)) = ( + string_append ((itype_mnemonic_forwards op1)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits imm)) (''''))))))))))))))" +|" assembly_forwards (SHIFTIOP (shamt,rs1,rd,op1)) = ( + string_append ((shiftiop_mnemonic_forwards op1)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((string_of_bits shamt)) (''''))))))))))))" +|" assembly_forwards (RTYPE (rs2,rs1,rd,op1)) = ( + string_append ((rtype_mnemonic_forwards op1)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))" +|" assembly_forwards (LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl)) = ( + string_append (''l'') + ((string_append ((size_mnemonic_forwards size1)) + ((string_append ((maybe_u_forwards is_unsigned)) + ((string_append ((maybe_aq_forwards aq)) + ((string_append ((maybe_rl_forwards rl)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits imm)) (''''))))))))))))))))))))))" +|" assembly_forwards (STORE (imm,rs1,rd,size1,aq,rl)) = ( + string_append (''s'') + ((string_append ((size_mnemonic_forwards size1)) + ((string_append ((maybe_aq_forwards aq)) + ((string_append ((maybe_rl_forwards rl)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits imm)) (''''))))))))))))))))))))" +|" assembly_forwards (ADDIW (imm,rs1,rd)) = ( + string_append (''addiw'') + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits imm)) (''''))))))))))))))" +|" assembly_forwards (SHIFTW (shamt,rs1,rd,op1)) = ( + string_append ((shiftw_mnemonic_forwards op1)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits shamt)) (''''))))))))))))))" +|" assembly_forwards (RTYPEW (rs2,rs1,rd,op1)) = ( + string_append ((rtypew_mnemonic_forwards op1)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))" +|" assembly_forwards (MUL (rs2,rs1,rd,high,signed1,signed2)) = ( + string_append ((mul_mnemonic_forwards high signed1 signed2)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))" +|" assembly_forwards (DIV (rs2,rs1,rd,s)) = ( + string_append (''div'') + ((string_append ((maybe_not_u_forwards s)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))))" +|" assembly_forwards (REM (rs2,rs1,rd,s)) = ( + string_append (''rem'') + ((string_append ((maybe_not_u_forwards s)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))))" +|" assembly_forwards (MULW (rs2,rs1,rd)) = ( + string_append (''mulw'') + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))" +|" assembly_forwards (DIVW (rs2,rs1,rd,s)) = ( + string_append (''div'') + ((string_append ((maybe_not_u_forwards s)) + ((string_append (''w'') + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))))))" +|" assembly_forwards (REMW (rs2,rs1,rd,s)) = ( + string_append (''rem'') + ((string_append ((maybe_not_u_forwards s)) + ((string_append (''w'') + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))))))" +|" assembly_forwards (FENCE (pred,succ)) = ( + string_append (''fence'') + ((string_append ((spc_forwards () )) + ((string_append ((fence_bits_forwards pred)) + ((string_append ((sep_forwards () )) + ((string_append ((fence_bits_forwards succ)) (''''))))))))))" +|" assembly_forwards (FENCEI (_)) = ( (''fence.i''))" +|" assembly_forwards (ECALL (_)) = ( (''ecall''))" +|" assembly_forwards (MRET (_)) = ( (''mret''))" +|" assembly_forwards (SRET (_)) = ( (''sret''))" +|" assembly_forwards (EBREAK (_)) = ( (''ebreak''))" +|" assembly_forwards (WFI (_)) = ( (''wfi''))" +|" assembly_forwards (SFENCE_VMA (rs1,rs2)) = ( + string_append (''sfence.vma'') + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) ((string_append ((reg_name_forwards rs2)) (''''))))))))))" +|" assembly_forwards (LOADRES (aq,rl,rs1,size1,rd)) = ( + string_append (''lr.'') + ((string_append ((maybe_aq_forwards aq)) + ((string_append ((maybe_rl_forwards rl)) + ((string_append ((size_mnemonic_forwards size1)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) (''''))))))))))))))))" +|" assembly_forwards (STORECON (aq,rl,rs2,rs1,size1,rd)) = ( + string_append (''sc.'') + ((string_append ((maybe_aq_forwards aq)) + ((string_append ((maybe_rl_forwards rl)) + ((string_append ((size_mnemonic_forwards size1)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))))))))" +|" assembly_forwards (AMO (op1,aq,rl,rs2,rs1,width,rd)) = ( + string_append ((amo_mnemonic_forwards op1)) + ((string_append (''.'') + ((string_append ((size_mnemonic_forwards width)) + ((string_append ((maybe_aq_forwards aq)) + ((string_append ((maybe_rl_forwards rl)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs2)) (''''))))))))))))))))))))))" +|" assembly_forwards (CSR (csr,rs1,rd,True,op1)) = ( + string_append ((csr_mnemonic_forwards op1)) + ((string_append (''i'') + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((string_of_bits rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((csr_name_map_forwards csr)) (''''))))))))))))))))" +|" assembly_forwards (CSR (csr,rs1,rd,False,op1)) = ( + string_append ((csr_mnemonic_forwards op1)) + ((string_append ((spc_forwards () )) + ((string_append ((reg_name_forwards rd)) + ((string_append ((sep_forwards () )) + ((string_append ((reg_name_forwards rs1)) + ((string_append ((sep_forwards () )) + ((string_append ((csr_name_map_forwards csr)) (''''))))))))))))))" +|" assembly_forwards (ILLEGAL (s)) = ( + string_append (''illegal'') + ((string_append ((spc_forwards () )) ((string_append ((string_of_bits s)) (''''))))))" + + +(*val assembly_backwards : string -> ast*) + +definition assembly_backwards :: " string \<Rightarrow> ast " where + " assembly_backwards arg0 = ( + (let stringappend_10760 = arg0 in + if ((case ((utype_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_10770,stringappend_10780) => + (let stringappend_10790 = (string_drop stringappend_10760 stringappend_10780) in + if ((case ((spc_matches_prefix stringappend_10790)) of + Some (stringappend_10800,stringappend_10810) => + (let stringappend_10820 = (string_drop stringappend_10790 stringappend_10810) in + if ((case ((reg_name_matches_prefix stringappend_10820 :: (( 5 Word.word * ii))option)) of + Some (stringappend_10830,stringappend_10840) => + (let stringappend_10850 = (string_drop stringappend_10820 stringappend_10840) in + if ((case ((sep_matches_prefix stringappend_10850)) of + Some (stringappend_10860,stringappend_10870) => + (let stringappend_10880 = (string_drop stringappend_10850 stringappend_10870) in + if ((case ((hex_bits_20_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_10880 + :: (( 20 Word.word * ii))option)) of + Some (stringappend_10890,stringappend_10900) => + if(((string_drop stringappend_10880 stringappend_10900)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_10780) = + ((case ((utype_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_10770,stringappend_10780) => + (stringappend_10770, stringappend_10780) + )) in + (let stringappend_10790 = (string_drop stringappend_10760 stringappend_10780) in + (case + (case ((spc_matches_prefix stringappend_10790)) of + Some (stringappend_10800,stringappend_10810) => + (stringappend_10800, stringappend_10810) + ) of + (_, stringappend_10810) => + (let stringappend_10820 = (string_drop stringappend_10790 + stringappend_10810) in + (let (rd, stringappend_10840) = + ((case ((reg_name_matches_prefix stringappend_10820 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10830,stringappend_10840) => + (stringappend_10830, stringappend_10840) + )) in + (let stringappend_10850 = (string_drop stringappend_10820 + stringappend_10840) in + (case + (case ((sep_matches_prefix stringappend_10850)) of + Some (stringappend_10860,stringappend_10870) => + (stringappend_10860, stringappend_10870) + ) of + (_, stringappend_10870) => + (let stringappend_10880 = (string_drop stringappend_10850 + stringappend_10870) in + (let (imm, stringappend_10900) = + ((case ((hex_bits_20_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_10880 :: (( 20 Word.word * ii)) option)) of + Some (stringappend_10890,stringappend_10900) => + (stringappend_10890, stringappend_10900) + )) in + if(((string_drop stringappend_10880 stringappend_10900)) = ('''')) then + (UTYPE (imm,rd,op1)) else undefined)) + )))) + ))) + else if (((((string_startswith stringappend_10760 (''jal''))) \<and> ((let stringappend_10920 = (string_drop stringappend_10760 ((string_length (''jal'')))) in + if ((case ((spc_matches_prefix stringappend_10920)) of + Some (stringappend_10930,stringappend_10940) => + (let stringappend_10950 = (string_drop stringappend_10920 stringappend_10940) in + if ((case ((reg_name_matches_prefix stringappend_10950 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_10960,stringappend_10970) => + (let stringappend_10980 = + (string_drop stringappend_10950 stringappend_10970) in + if ((case ((sep_matches_prefix stringappend_10980)) of + Some (stringappend_10990,stringappend_11000) => + (let stringappend_11010 = + (string_drop stringappend_10980 stringappend_11000) in + if ((case ((hex_bits_21_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_11010 + :: (( 21 Word.word * ii))option)) of + Some (stringappend_11020,stringappend_11030) => + if(((string_drop stringappend_11010 stringappend_11030)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_10920 = (string_drop stringappend_10760 ((string_length (''jal'')))) in + (case + (case ((spc_matches_prefix stringappend_10920)) of + Some (stringappend_10930,stringappend_10940) => + (stringappend_10930, stringappend_10940) + ) of + (_, stringappend_10940) => + (let stringappend_10950 = (string_drop stringappend_10920 + stringappend_10940) in + (let (rd, stringappend_10970) = + ((case ((reg_name_matches_prefix stringappend_10950 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10960,stringappend_10970) => + (stringappend_10960, stringappend_10970) + )) in + (let stringappend_10980 = (string_drop stringappend_10950 + stringappend_10970) in + (case + (case ((sep_matches_prefix stringappend_10980)) of + Some (stringappend_10990,stringappend_11000) => + (stringappend_10990, stringappend_11000) + ) of + (_, stringappend_11000) => + (let stringappend_11010 = (string_drop stringappend_10980 + stringappend_11000) in + (let (imm, stringappend_11030) = + ((case ((hex_bits_21_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_11010 :: (( 21 Word.word * ii)) option)) of + Some (stringappend_11020,stringappend_11030) => + (stringappend_11020, stringappend_11030) + )) in + if(((string_drop stringappend_11010 stringappend_11030)) = ('''')) then + (RISCV_JAL (imm,rd)) else undefined)) + )))) + )) + else if (((((string_startswith stringappend_10760 (''jalr''))) \<and> ((let stringappend_11050 = (string_drop stringappend_10760 ((string_length (''jalr'')))) in + if ((case ((spc_matches_prefix stringappend_11050)) of + Some (stringappend_11060,stringappend_11070) => + (let stringappend_11080 = (string_drop stringappend_11050 stringappend_11070) in + if ((case ((reg_name_matches_prefix stringappend_11080 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_11090,stringappend_11100) => + (let stringappend_11110 = + (string_drop stringappend_11080 stringappend_11100) in + if ((case ((sep_matches_prefix stringappend_11110)) of + Some (stringappend_11120,stringappend_11130) => + (let stringappend_11140 = + (string_drop stringappend_11110 stringappend_11130) in + if ((case ((reg_name_matches_prefix stringappend_11140 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_11150,stringappend_11160) => + (let stringappend_11170 = + (string_drop stringappend_11140 stringappend_11160) in + if ((case ((sep_matches_prefix stringappend_11170)) of + Some (stringappend_11180,stringappend_11190) => + (let stringappend_11200 = + (string_drop stringappend_11170 stringappend_11190) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_11200 + :: (( 12 Word.word * ii))option)) of + Some (stringappend_11210,stringappend_11220) => + if(((string_drop stringappend_11200 stringappend_11220)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_11050 = (string_drop stringappend_10760 ((string_length (''jalr'')))) in + (case + (case ((spc_matches_prefix stringappend_11050)) of + Some (stringappend_11060,stringappend_11070) => + (stringappend_11060, stringappend_11070) + ) of + (_, stringappend_11070) => + (let stringappend_11080 = (string_drop stringappend_11050 + stringappend_11070) in + (let (rd, stringappend_11100) = + ((case ((reg_name_matches_prefix stringappend_11080 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_11090,stringappend_11100) => + (stringappend_11090, stringappend_11100) + )) in + (let stringappend_11110 = (string_drop stringappend_11080 + stringappend_11100) in + (case + (case ((sep_matches_prefix stringappend_11110)) of + Some (stringappend_11120,stringappend_11130) => + (stringappend_11120, stringappend_11130) + ) of + (_, stringappend_11130) => + (let stringappend_11140 = (string_drop stringappend_11110 + stringappend_11130) in + (let (rs1, stringappend_11160) = + ((case ((reg_name_matches_prefix stringappend_11140 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_11150,stringappend_11160) => + (stringappend_11150, stringappend_11160) + )) in + (let stringappend_11170 = (string_drop stringappend_11140 + stringappend_11160) in + (case + (case ((sep_matches_prefix stringappend_11170)) of + Some (stringappend_11180,stringappend_11190) => + (stringappend_11180, stringappend_11190) + ) of + (_, stringappend_11190) => + (let stringappend_11200 = (string_drop stringappend_11170 + stringappend_11190) in + (let (imm, stringappend_11220) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_11200 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_11210,stringappend_11220) => + (stringappend_11210, stringappend_11220) + )) in + if(((string_drop stringappend_11200 stringappend_11220)) = ('''')) then + (RISCV_JALR (imm,rs1,rd)) else undefined)) + )))) + )))) + )) + else if ((case ((btype_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_11240,stringappend_11250) => + (let stringappend_11260 = (string_drop stringappend_10760 stringappend_11250) in + if ((case ((spc_matches_prefix stringappend_11260)) of + Some (stringappend_11270,stringappend_11280) => + (let stringappend_11290 = (string_drop stringappend_11260 stringappend_11280) in + if ((case ((reg_name_matches_prefix stringappend_11290 :: (( 5 Word.word * ii))option)) of + Some (stringappend_11300,stringappend_11310) => + (let stringappend_11320 = (string_drop stringappend_11290 stringappend_11310) in + if ((case ((sep_matches_prefix stringappend_11320)) of + Some (stringappend_11330,stringappend_11340) => + (let stringappend_11350 = (string_drop stringappend_11320 stringappend_11340) in + if ((case ((reg_name_matches_prefix stringappend_11350 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_11360,stringappend_11370) => + (let stringappend_11380 = + (string_drop stringappend_11350 stringappend_11370) in + if ((case ((sep_matches_prefix stringappend_11380)) of + Some (stringappend_11390,stringappend_11400) => + (let stringappend_11410 = + (string_drop stringappend_11380 stringappend_11400) in + if ((case ((hex_bits_13_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_11410 + :: (( 13 Word.word * ii))option)) of + Some (stringappend_11420,stringappend_11430) => + if(((string_drop stringappend_11410 stringappend_11430)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_11250) = + ((case ((btype_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_11240,stringappend_11250) => + (stringappend_11240, stringappend_11250) + )) in + (let stringappend_11260 = (string_drop stringappend_10760 stringappend_11250) in + (case + (case ((spc_matches_prefix stringappend_11260)) of + Some (stringappend_11270,stringappend_11280) => + (stringappend_11270, stringappend_11280) + ) of + (_, stringappend_11280) => + (let stringappend_11290 = (string_drop stringappend_11260 + stringappend_11280) in + (let (rs1, stringappend_11310) = + ((case ((reg_name_matches_prefix stringappend_11290 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_11300,stringappend_11310) => + (stringappend_11300, stringappend_11310) + )) in + (let stringappend_11320 = (string_drop stringappend_11290 + stringappend_11310) in + (case + (case ((sep_matches_prefix stringappend_11320)) of + Some (stringappend_11330,stringappend_11340) => + (stringappend_11330, stringappend_11340) + ) of + (_, stringappend_11340) => + (let stringappend_11350 = (string_drop stringappend_11320 + stringappend_11340) in + (let (rs2, stringappend_11370) = + ((case ((reg_name_matches_prefix stringappend_11350 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_11360,stringappend_11370) => + (stringappend_11360, stringappend_11370) + )) in + (let stringappend_11380 = (string_drop stringappend_11350 + stringappend_11370) in + (case + (case ((sep_matches_prefix stringappend_11380)) of + Some (stringappend_11390,stringappend_11400) => + (stringappend_11390, stringappend_11400) + ) of + (_, stringappend_11400) => + (let stringappend_11410 = (string_drop stringappend_11380 + stringappend_11400) in + (let (imm, stringappend_11430) = + ((case ((hex_bits_13_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_11410 :: (( 13 Word.word * ii)) option)) of + Some (stringappend_11420,stringappend_11430) => + (stringappend_11420, stringappend_11430) + )) in + if(((string_drop stringappend_11410 stringappend_11430)) = ('''')) then + (BTYPE (imm,rs2,rs1,op1)) else undefined)) + )))) + )))) + ))) + else if ((case ((itype_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_11450,stringappend_11460) => + (let stringappend_11470 = (string_drop stringappend_10760 stringappend_11460) in + if ((case ((spc_matches_prefix stringappend_11470)) of + Some (stringappend_11480,stringappend_11490) => + (let stringappend_11500 = (string_drop stringappend_11470 stringappend_11490) in + if ((case ((reg_name_matches_prefix stringappend_11500 :: (( 5 Word.word * ii))option)) of + Some (stringappend_11510,stringappend_11520) => + (let stringappend_11530 = (string_drop stringappend_11500 stringappend_11520) in + if ((case ((sep_matches_prefix stringappend_11530)) of + Some (stringappend_11540,stringappend_11550) => + (let stringappend_11560 = (string_drop stringappend_11530 stringappend_11550) in + if ((case ((reg_name_matches_prefix stringappend_11560 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_11570,stringappend_11580) => + (let stringappend_11590 = + (string_drop stringappend_11560 stringappend_11580) in + if ((case ((sep_matches_prefix stringappend_11590)) of + Some (stringappend_11600,stringappend_11610) => + (let stringappend_11620 = + (string_drop stringappend_11590 stringappend_11610) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_11620 + :: (( 12 Word.word * ii))option)) of + Some (stringappend_11630,stringappend_11640) => + if(((string_drop stringappend_11620 stringappend_11640)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_11460) = + ((case ((itype_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_11450,stringappend_11460) => + (stringappend_11450, stringappend_11460) + )) in + (let stringappend_11470 = (string_drop stringappend_10760 stringappend_11460) in + (case + (case ((spc_matches_prefix stringappend_11470)) of + Some (stringappend_11480,stringappend_11490) => + (stringappend_11480, stringappend_11490) + ) of + (_, stringappend_11490) => + (let stringappend_11500 = (string_drop stringappend_11470 + stringappend_11490) in + (let (rd, stringappend_11520) = + ((case ((reg_name_matches_prefix stringappend_11500 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_11510,stringappend_11520) => + (stringappend_11510, stringappend_11520) + )) in + (let stringappend_11530 = (string_drop stringappend_11500 + stringappend_11520) in + (case + (case ((sep_matches_prefix stringappend_11530)) of + Some (stringappend_11540,stringappend_11550) => + (stringappend_11540, stringappend_11550) + ) of + (_, stringappend_11550) => + (let stringappend_11560 = (string_drop stringappend_11530 + stringappend_11550) in + (let (rs1, stringappend_11580) = + ((case ((reg_name_matches_prefix stringappend_11560 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_11570,stringappend_11580) => + (stringappend_11570, stringappend_11580) + )) in + (let stringappend_11590 = (string_drop stringappend_11560 + stringappend_11580) in + (case + (case ((sep_matches_prefix stringappend_11590)) of + Some (stringappend_11600,stringappend_11610) => + (stringappend_11600, stringappend_11610) + ) of + (_, stringappend_11610) => + (let stringappend_11620 = (string_drop stringappend_11590 + stringappend_11610) in + (let (imm, stringappend_11640) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_11620 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_11630,stringappend_11640) => + (stringappend_11630, stringappend_11640) + )) in + if(((string_drop stringappend_11620 stringappend_11640)) = ('''')) then + (ITYPE (imm,rs1,rd,op1)) else undefined)) + )))) + )))) + ))) + else if ((case ((shiftiop_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_11660,stringappend_11670) => + (let stringappend_11680 = (string_drop stringappend_10760 stringappend_11670) in + if ((case ((spc_matches_prefix stringappend_11680)) of + Some (stringappend_11690,stringappend_11700) => + (let stringappend_11710 = (string_drop stringappend_11680 stringappend_11700) in + if ((case ((reg_name_matches_prefix stringappend_11710 :: (( 5 Word.word * ii))option)) of + Some (stringappend_11720,stringappend_11730) => + (let stringappend_11740 = (string_drop stringappend_11710 stringappend_11730) in + if ((case ((sep_matches_prefix stringappend_11740)) of + Some (stringappend_11750,stringappend_11760) => + (let stringappend_11770 = (string_drop stringappend_11740 stringappend_11760) in + if ((case ((reg_name_matches_prefix stringappend_11770 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_11780,stringappend_11790) => + (let stringappend_11800 = + (string_drop stringappend_11770 stringappend_11790) in + if ((case ((hex_bits_6_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_11800 + :: (( 6 Word.word * ii))option)) of + Some (stringappend_11810,stringappend_11820) => + if(((string_drop stringappend_11800 stringappend_11820)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_11670) = + ((case ((shiftiop_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_11660,stringappend_11670) => + (stringappend_11660, stringappend_11670) + )) in + (let stringappend_11680 = (string_drop stringappend_10760 stringappend_11670) in + (case + (case ((spc_matches_prefix stringappend_11680)) of + Some (stringappend_11690,stringappend_11700) => + (stringappend_11690, stringappend_11700) + ) of + (_, stringappend_11700) => + (let stringappend_11710 = (string_drop stringappend_11680 + stringappend_11700) in + (let (rd, stringappend_11730) = + ((case ((reg_name_matches_prefix stringappend_11710 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_11720,stringappend_11730) => + (stringappend_11720, stringappend_11730) + )) in + (let stringappend_11740 = (string_drop stringappend_11710 + stringappend_11730) in + (case + (case ((sep_matches_prefix stringappend_11740)) of + Some (stringappend_11750,stringappend_11760) => + (stringappend_11750, stringappend_11760) + ) of + (_, stringappend_11760) => + (let stringappend_11770 = (string_drop stringappend_11740 + stringappend_11760) in + (let (rs1, stringappend_11790) = + ((case ((reg_name_matches_prefix stringappend_11770 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_11780,stringappend_11790) => + (stringappend_11780, stringappend_11790) + )) in + (let stringappend_11800 = (string_drop stringappend_11770 + stringappend_11790) in + (let (shamt, stringappend_11820) = + ((case ((hex_bits_6_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_11800 :: (( 6 Word.word * ii)) option)) of + Some (stringappend_11810,stringappend_11820) => + (stringappend_11810, stringappend_11820) + )) in + if(((string_drop stringappend_11800 stringappend_11820)) = ('''')) then + (SHIFTIOP (shamt,rs1,rd,op1)) else undefined)))) + )))) + ))) + else if ((case ((rtype_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_11840,stringappend_11850) => + (let stringappend_11860 = (string_drop stringappend_10760 stringappend_11850) in + if ((case ((spc_matches_prefix stringappend_11860)) of + Some (stringappend_11870,stringappend_11880) => + (let stringappend_11890 = (string_drop stringappend_11860 stringappend_11880) in + if ((case ((reg_name_matches_prefix stringappend_11890 :: (( 5 Word.word * ii))option)) of + Some (stringappend_11900,stringappend_11910) => + (let stringappend_11920 = (string_drop stringappend_11890 stringappend_11910) in + if ((case ((sep_matches_prefix stringappend_11920)) of + Some (stringappend_11930,stringappend_11940) => + (let stringappend_11950 = (string_drop stringappend_11920 stringappend_11940) in + if ((case ((reg_name_matches_prefix stringappend_11950 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_11960,stringappend_11970) => + (let stringappend_11980 = + (string_drop stringappend_11950 stringappend_11970) in + if ((case ((sep_matches_prefix stringappend_11980)) of + Some (stringappend_11990,stringappend_12000) => + (let stringappend_12010 = + (string_drop stringappend_11980 stringappend_12000) in + if ((case ((reg_name_matches_prefix stringappend_12010 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_12020,stringappend_12030) => + if(((string_drop stringappend_12010 stringappend_12030)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_11850) = + ((case ((rtype_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_11840,stringappend_11850) => + (stringappend_11840, stringappend_11850) + )) in + (let stringappend_11860 = (string_drop stringappend_10760 stringappend_11850) in + (case + (case ((spc_matches_prefix stringappend_11860)) of + Some (stringappend_11870,stringappend_11880) => + (stringappend_11870, stringappend_11880) + ) of + (_, stringappend_11880) => + (let stringappend_11890 = (string_drop stringappend_11860 + stringappend_11880) in + (let (rd, stringappend_11910) = + ((case ((reg_name_matches_prefix stringappend_11890 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_11900,stringappend_11910) => + (stringappend_11900, stringappend_11910) + )) in + (let stringappend_11920 = (string_drop stringappend_11890 + stringappend_11910) in + (case + (case ((sep_matches_prefix stringappend_11920)) of + Some (stringappend_11930,stringappend_11940) => + (stringappend_11930, stringappend_11940) + ) of + (_, stringappend_11940) => + (let stringappend_11950 = (string_drop stringappend_11920 + stringappend_11940) in + (let (rs1, stringappend_11970) = + ((case ((reg_name_matches_prefix stringappend_11950 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_11960,stringappend_11970) => + (stringappend_11960, stringappend_11970) + )) in + (let stringappend_11980 = (string_drop stringappend_11950 + stringappend_11970) in + (case + (case ((sep_matches_prefix stringappend_11980)) of + Some (stringappend_11990,stringappend_12000) => + (stringappend_11990, stringappend_12000) + ) of + (_, stringappend_12000) => + (let stringappend_12010 = (string_drop stringappend_11980 + stringappend_12000) in + (let (rs2, stringappend_12030) = + ((case ((reg_name_matches_prefix stringappend_12010 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_12020,stringappend_12030) => + (stringappend_12020, stringappend_12030) + )) in + if(((string_drop stringappend_12010 stringappend_12030)) = ('''')) then + (RTYPE (rs2,rs1,rd,op1)) else undefined)) + )))) + )))) + ))) + else if (((((string_startswith stringappend_10760 (''l''))) \<and> ((let stringappend_12050 = (string_drop stringappend_10760 ((string_length (''l'')))) in + if ((case ((size_mnemonic_matches_prefix stringappend_12050)) of + Some (stringappend_12060,stringappend_12070) => + (let stringappend_12080 = (string_drop stringappend_12050 stringappend_12070) in + if ((case ((maybe_u_matches_prefix stringappend_12080)) of + Some (stringappend_12090,stringappend_12100) => + (let stringappend_12110 = + (string_drop stringappend_12080 stringappend_12100) in + if ((case ((maybe_aq_matches_prefix stringappend_12110)) of + Some (stringappend_12120,stringappend_12130) => + (let stringappend_12140 = + (string_drop stringappend_12110 stringappend_12130) in + if ((case ((maybe_rl_matches_prefix stringappend_12140)) of + Some (stringappend_12150,stringappend_12160) => + (let stringappend_12170 = + (string_drop stringappend_12140 stringappend_12160) in + if ((case ((spc_matches_prefix stringappend_12170)) of + Some (stringappend_12180,stringappend_12190) => + (let stringappend_12200 = + (string_drop stringappend_12170 stringappend_12190) in + if ((case ((reg_name_matches_prefix stringappend_12200 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_12210,stringappend_12220) => + (let stringappend_12230 = + (string_drop stringappend_12200 stringappend_12220) in + if ((case ((sep_matches_prefix stringappend_12230)) of + Some (stringappend_12240,stringappend_12250) => + (let stringappend_12260 = + (string_drop stringappend_12230 + stringappend_12250) in + if ((case ((reg_name_matches_prefix + stringappend_12260 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_12270,stringappend_12280) => + (let stringappend_12290 = + (string_drop stringappend_12260 + stringappend_12280) in + if ((case ((sep_matches_prefix + stringappend_12290)) of + Some + (stringappend_12300,stringappend_12310) => + (let stringappend_12320 = + (string_drop stringappend_12290 + stringappend_12310) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_12320 + :: (( 12 Word.word * ii))option)) of + Some + (stringappend_12330,stringappend_12340) => + if(((string_drop stringappend_12320 stringappend_12340)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_12050 = (string_drop stringappend_10760 ((string_length (''l'')))) in + (let (size1, stringappend_12070) = + ((case ((size_mnemonic_matches_prefix stringappend_12050)) of + Some (stringappend_12060,stringappend_12070) => + (stringappend_12060, stringappend_12070) + )) in + (let stringappend_12080 = (string_drop stringappend_12050 stringappend_12070) in + (let (is_unsigned, stringappend_12100) = + ((case ((maybe_u_matches_prefix stringappend_12080)) of + Some (stringappend_12090,stringappend_12100) => + (stringappend_12090, stringappend_12100) + )) in + (let stringappend_12110 = (string_drop stringappend_12080 stringappend_12100) in + (let (aq, stringappend_12130) = + ((case ((maybe_aq_matches_prefix stringappend_12110)) of + Some (stringappend_12120,stringappend_12130) => + (stringappend_12120, stringappend_12130) + )) in + (let stringappend_12140 = (string_drop stringappend_12110 stringappend_12130) in + (let (rl, stringappend_12160) = + ((case ((maybe_rl_matches_prefix stringappend_12140)) of + Some (stringappend_12150,stringappend_12160) => + (stringappend_12150, stringappend_12160) + )) in + (let stringappend_12170 = (string_drop stringappend_12140 stringappend_12160) in + (case + (case ((spc_matches_prefix stringappend_12170)) of + Some (stringappend_12180,stringappend_12190) => + (stringappend_12180, stringappend_12190) + ) of + (_, stringappend_12190) => + (let stringappend_12200 = (string_drop stringappend_12170 + stringappend_12190) in + (let (rd, stringappend_12220) = + ((case ((reg_name_matches_prefix stringappend_12200 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_12210,stringappend_12220) => + (stringappend_12210, stringappend_12220) + )) in + (let stringappend_12230 = (string_drop stringappend_12200 + stringappend_12220) in + (case + (case ((sep_matches_prefix stringappend_12230)) of + Some (stringappend_12240,stringappend_12250) => + (stringappend_12240, stringappend_12250) + ) of + (_, stringappend_12250) => + (let stringappend_12260 = (string_drop stringappend_12230 + stringappend_12250) in + (let (rs1, stringappend_12280) = + ((case ((reg_name_matches_prefix stringappend_12260 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_12270,stringappend_12280) => + (stringappend_12270, stringappend_12280) + )) in + (let stringappend_12290 = (string_drop stringappend_12260 + stringappend_12280) in + (case + (case ((sep_matches_prefix stringappend_12290)) of + Some (stringappend_12300,stringappend_12310) => + (stringappend_12300, stringappend_12310) + ) of + (_, stringappend_12310) => + (let stringappend_12320 = (string_drop stringappend_12290 + stringappend_12310) in + (let (imm, stringappend_12340) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_12320 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_12330,stringappend_12340) => + (stringappend_12330, stringappend_12340) + )) in + if(((string_drop stringappend_12320 stringappend_12340)) = ('''')) then + (LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl)) else undefined)) + )))) + )))) + )))))))))) + else if (((((string_startswith stringappend_10760 (''s''))) \<and> ((let stringappend_12360 = (string_drop stringappend_10760 ((string_length (''s'')))) in + if ((case ((size_mnemonic_matches_prefix stringappend_12360)) of + Some (stringappend_12370,stringappend_12380) => + (let stringappend_12390 = (string_drop stringappend_12360 stringappend_12380) in + if ((case ((maybe_aq_matches_prefix stringappend_12390)) of + Some (stringappend_12400,stringappend_12410) => + (let stringappend_12420 = + (string_drop stringappend_12390 stringappend_12410) in + if ((case ((maybe_rl_matches_prefix stringappend_12420)) of + Some (stringappend_12430,stringappend_12440) => + (let stringappend_12450 = + (string_drop stringappend_12420 stringappend_12440) in + if ((case ((spc_matches_prefix stringappend_12450)) of + Some (stringappend_12460,stringappend_12470) => + (let stringappend_12480 = + (string_drop stringappend_12450 stringappend_12470) in + if ((case ((reg_name_matches_prefix stringappend_12480 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_12490,stringappend_12500) => + (let stringappend_12510 = + (string_drop stringappend_12480 stringappend_12500) in + if ((case ((sep_matches_prefix stringappend_12510)) of + Some (stringappend_12520,stringappend_12530) => + (let stringappend_12540 = + (string_drop stringappend_12510 stringappend_12530) in + if ((case ((reg_name_matches_prefix stringappend_12540 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_12550,stringappend_12560) => + (let stringappend_12570 = + (string_drop stringappend_12540 + stringappend_12560) in + if ((case ((sep_matches_prefix stringappend_12570)) of + Some (stringappend_12580,stringappend_12590) => + (let stringappend_12600 = + (string_drop stringappend_12570 + stringappend_12590) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_12600 + :: (( 12 Word.word * ii))option)) of + Some + (stringappend_12610,stringappend_12620) => + if(((string_drop stringappend_12600 stringappend_12620)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_12360 = (string_drop stringappend_10760 ((string_length (''s'')))) in + (let (size1, stringappend_12380) = + ((case ((size_mnemonic_matches_prefix stringappend_12360)) of + Some (stringappend_12370,stringappend_12380) => + (stringappend_12370, stringappend_12380) + )) in + (let stringappend_12390 = (string_drop stringappend_12360 stringappend_12380) in + (let (aq, stringappend_12410) = + ((case ((maybe_aq_matches_prefix stringappend_12390)) of + Some (stringappend_12400,stringappend_12410) => + (stringappend_12400, stringappend_12410) + )) in + (let stringappend_12420 = (string_drop stringappend_12390 stringappend_12410) in + (let (rl, stringappend_12440) = + ((case ((maybe_rl_matches_prefix stringappend_12420)) of + Some (stringappend_12430,stringappend_12440) => + (stringappend_12430, stringappend_12440) + )) in + (let stringappend_12450 = (string_drop stringappend_12420 stringappend_12440) in + (case + (case ((spc_matches_prefix stringappend_12450)) of + Some (stringappend_12460,stringappend_12470) => + (stringappend_12460, stringappend_12470) + ) of + (_, stringappend_12470) => + (let stringappend_12480 = (string_drop stringappend_12450 + stringappend_12470) in + (let (rd, stringappend_12500) = + ((case ((reg_name_matches_prefix stringappend_12480 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_12490,stringappend_12500) => + (stringappend_12490, stringappend_12500) + )) in + (let stringappend_12510 = (string_drop stringappend_12480 + stringappend_12500) in + (case + (case ((sep_matches_prefix stringappend_12510)) of + Some (stringappend_12520,stringappend_12530) => + (stringappend_12520, stringappend_12530) + ) of + (_, stringappend_12530) => + (let stringappend_12540 = (string_drop stringappend_12510 + stringappend_12530) in + (let (rs1, stringappend_12560) = + ((case ((reg_name_matches_prefix stringappend_12540 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_12550,stringappend_12560) => + (stringappend_12550, stringappend_12560) + )) in + (let stringappend_12570 = (string_drop stringappend_12540 + stringappend_12560) in + (case + (case ((sep_matches_prefix stringappend_12570)) of + Some (stringappend_12580,stringappend_12590) => + (stringappend_12580, stringappend_12590) + ) of + (_, stringappend_12590) => + (let stringappend_12600 = (string_drop stringappend_12570 + stringappend_12590) in + (let (imm, stringappend_12620) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_12600 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_12610,stringappend_12620) => + (stringappend_12610, stringappend_12620) + )) in + if(((string_drop stringappend_12600 stringappend_12620)) = ('''')) then + (STORE (imm,rs1,rd,size1,aq,rl)) else undefined)) + )))) + )))) + )))))))) + else if (((((string_startswith stringappend_10760 (''addiw''))) \<and> ((let stringappend_12640 = (string_drop stringappend_10760 ((string_length (''addiw'')))) in + if ((case ((spc_matches_prefix stringappend_12640)) of + Some (stringappend_12650,stringappend_12660) => + (let stringappend_12670 = (string_drop stringappend_12640 stringappend_12660) in + if ((case ((reg_name_matches_prefix stringappend_12670 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_12680,stringappend_12690) => + (let stringappend_12700 = + (string_drop stringappend_12670 stringappend_12690) in + if ((case ((sep_matches_prefix stringappend_12700)) of + Some (stringappend_12710,stringappend_12720) => + (let stringappend_12730 = + (string_drop stringappend_12700 stringappend_12720) in + if ((case ((reg_name_matches_prefix stringappend_12730 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_12740,stringappend_12750) => + (let stringappend_12760 = + (string_drop stringappend_12730 stringappend_12750) in + if ((case ((sep_matches_prefix stringappend_12760)) of + Some (stringappend_12770,stringappend_12780) => + (let stringappend_12790 = + (string_drop stringappend_12760 stringappend_12780) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_12790 + :: (( 12 Word.word * ii))option)) of + Some (stringappend_12800,stringappend_12810) => + if(((string_drop stringappend_12790 stringappend_12810)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_12640 = (string_drop stringappend_10760 ((string_length (''addiw'')))) in + (case + (case ((spc_matches_prefix stringappend_12640)) of + Some (stringappend_12650,stringappend_12660) => + (stringappend_12650, stringappend_12660) + ) of + (_, stringappend_12660) => + (let stringappend_12670 = (string_drop stringappend_12640 + stringappend_12660) in + (let (rd, stringappend_12690) = + ((case ((reg_name_matches_prefix stringappend_12670 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_12680,stringappend_12690) => + (stringappend_12680, stringappend_12690) + )) in + (let stringappend_12700 = (string_drop stringappend_12670 + stringappend_12690) in + (case + (case ((sep_matches_prefix stringappend_12700)) of + Some (stringappend_12710,stringappend_12720) => + (stringappend_12710, stringappend_12720) + ) of + (_, stringappend_12720) => + (let stringappend_12730 = (string_drop stringappend_12700 + stringappend_12720) in + (let (rs1, stringappend_12750) = + ((case ((reg_name_matches_prefix stringappend_12730 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_12740,stringappend_12750) => + (stringappend_12740, stringappend_12750) + )) in + (let stringappend_12760 = (string_drop stringappend_12730 + stringappend_12750) in + (case + (case ((sep_matches_prefix stringappend_12760)) of + Some (stringappend_12770,stringappend_12780) => + (stringappend_12770, stringappend_12780) + ) of + (_, stringappend_12780) => + (let stringappend_12790 = (string_drop stringappend_12760 + stringappend_12780) in + (let (imm, stringappend_12810) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_12790 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_12800,stringappend_12810) => + (stringappend_12800, stringappend_12810) + )) in + if(((string_drop stringappend_12790 stringappend_12810)) = ('''')) then + (ADDIW (imm,rs1,rd)) else undefined)) + )))) + )))) + )) + else if ((case ((shiftw_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_12830,stringappend_12840) => + (let stringappend_12850 = (string_drop stringappend_10760 stringappend_12840) in + if ((case ((spc_matches_prefix stringappend_12850)) of + Some (stringappend_12860,stringappend_12870) => + (let stringappend_12880 = (string_drop stringappend_12850 stringappend_12870) in + if ((case ((reg_name_matches_prefix stringappend_12880 :: (( 5 Word.word * ii))option)) of + Some (stringappend_12890,stringappend_12900) => + (let stringappend_12910 = (string_drop stringappend_12880 stringappend_12900) in + if ((case ((sep_matches_prefix stringappend_12910)) of + Some (stringappend_12920,stringappend_12930) => + (let stringappend_12940 = (string_drop stringappend_12910 stringappend_12930) in + if ((case ((reg_name_matches_prefix stringappend_12940 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_12950,stringappend_12960) => + (let stringappend_12970 = + (string_drop stringappend_12940 stringappend_12960) in + if ((case ((sep_matches_prefix stringappend_12970)) of + Some (stringappend_12980,stringappend_12990) => + (let stringappend_13000 = + (string_drop stringappend_12970 stringappend_12990) in + if ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_13000 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_13010,stringappend_13020) => + if(((string_drop stringappend_13000 stringappend_13020)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_12840) = + ((case ((shiftw_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_12830,stringappend_12840) => + (stringappend_12830, stringappend_12840) + )) in + (let stringappend_12850 = (string_drop stringappend_10760 stringappend_12840) in + (case + (case ((spc_matches_prefix stringappend_12850)) of + Some (stringappend_12860,stringappend_12870) => + (stringappend_12860, stringappend_12870) + ) of + (_, stringappend_12870) => + (let stringappend_12880 = (string_drop stringappend_12850 + stringappend_12870) in + (let (rd, stringappend_12900) = + ((case ((reg_name_matches_prefix stringappend_12880 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_12890,stringappend_12900) => + (stringappend_12890, stringappend_12900) + )) in + (let stringappend_12910 = (string_drop stringappend_12880 + stringappend_12900) in + (case + (case ((sep_matches_prefix stringappend_12910)) of + Some (stringappend_12920,stringappend_12930) => + (stringappend_12920, stringappend_12930) + ) of + (_, stringappend_12930) => + (let stringappend_12940 = (string_drop stringappend_12910 + stringappend_12930) in + (let (rs1, stringappend_12960) = + ((case ((reg_name_matches_prefix stringappend_12940 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_12950,stringappend_12960) => + (stringappend_12950, stringappend_12960) + )) in + (let stringappend_12970 = (string_drop stringappend_12940 + stringappend_12960) in + (case + (case ((sep_matches_prefix stringappend_12970)) of + Some (stringappend_12980,stringappend_12990) => + (stringappend_12980, stringappend_12990) + ) of + (_, stringappend_12990) => + (let stringappend_13000 = (string_drop stringappend_12970 + stringappend_12990) in + (let (shamt, stringappend_13020) = + ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_13000 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13010,stringappend_13020) => + (stringappend_13010, stringappend_13020) + )) in + if(((string_drop stringappend_13000 stringappend_13020)) = ('''')) then + (SHIFTW (shamt,rs1,rd,op1)) else undefined)) + )))) + )))) + ))) + else if ((case ((rtypew_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_13040,stringappend_13050) => + (let stringappend_13060 = (string_drop stringappend_10760 stringappend_13050) in + if ((case ((spc_matches_prefix stringappend_13060)) of + Some (stringappend_13070,stringappend_13080) => + (let stringappend_13090 = (string_drop stringappend_13060 stringappend_13080) in + if ((case ((reg_name_matches_prefix stringappend_13090 :: (( 5 Word.word * ii))option)) of + Some (stringappend_13100,stringappend_13110) => + (let stringappend_13120 = (string_drop stringappend_13090 stringappend_13110) in + if ((case ((sep_matches_prefix stringappend_13120)) of + Some (stringappend_13130,stringappend_13140) => + (let stringappend_13150 = (string_drop stringappend_13120 stringappend_13140) in + if ((case ((reg_name_matches_prefix stringappend_13150 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_13160,stringappend_13170) => + (let stringappend_13180 = + (string_drop stringappend_13150 stringappend_13170) in + if ((case ((sep_matches_prefix stringappend_13180)) of + Some (stringappend_13190,stringappend_13200) => + (let stringappend_13210 = + (string_drop stringappend_13180 stringappend_13200) in + if ((case ((reg_name_matches_prefix stringappend_13210 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_13220,stringappend_13230) => + if(((string_drop stringappend_13210 stringappend_13230)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_13050) = + ((case ((rtypew_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_13040,stringappend_13050) => + (stringappend_13040, stringappend_13050) + )) in + (let stringappend_13060 = (string_drop stringappend_10760 stringappend_13050) in + (case + (case ((spc_matches_prefix stringappend_13060)) of + Some (stringappend_13070,stringappend_13080) => + (stringappend_13070, stringappend_13080) + ) of + (_, stringappend_13080) => + (let stringappend_13090 = (string_drop stringappend_13060 + stringappend_13080) in + (let (rd, stringappend_13110) = + ((case ((reg_name_matches_prefix stringappend_13090 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13100,stringappend_13110) => + (stringappend_13100, stringappend_13110) + )) in + (let stringappend_13120 = (string_drop stringappend_13090 + stringappend_13110) in + (case + (case ((sep_matches_prefix stringappend_13120)) of + Some (stringappend_13130,stringappend_13140) => + (stringappend_13130, stringappend_13140) + ) of + (_, stringappend_13140) => + (let stringappend_13150 = (string_drop stringappend_13120 + stringappend_13140) in + (let (rs1, stringappend_13170) = + ((case ((reg_name_matches_prefix stringappend_13150 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13160,stringappend_13170) => + (stringappend_13160, stringappend_13170) + )) in + (let stringappend_13180 = (string_drop stringappend_13150 + stringappend_13170) in + (case + (case ((sep_matches_prefix stringappend_13180)) of + Some (stringappend_13190,stringappend_13200) => + (stringappend_13190, stringappend_13200) + ) of + (_, stringappend_13200) => + (let stringappend_13210 = (string_drop stringappend_13180 + stringappend_13200) in + (let (rs2, stringappend_13230) = + ((case ((reg_name_matches_prefix stringappend_13210 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13220,stringappend_13230) => + (stringappend_13220, stringappend_13230) + )) in + if(((string_drop stringappend_13210 stringappend_13230)) = ('''')) then + (RTYPEW (rs2,rs1,rd,op1)) else undefined)) + )))) + )))) + ))) + else if ((case ((mul_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_13250,stringappend_13260) => + (let stringappend_13270 = (string_drop stringappend_10760 stringappend_13260) in + if ((case ((spc_matches_prefix stringappend_13270)) of + Some (stringappend_13280,stringappend_13290) => + (let stringappend_13300 = (string_drop stringappend_13270 stringappend_13290) in + if ((case ((reg_name_matches_prefix stringappend_13300 :: (( 5 Word.word * ii))option)) of + Some (stringappend_13310,stringappend_13320) => + (let stringappend_13330 = (string_drop stringappend_13300 stringappend_13320) in + if ((case ((sep_matches_prefix stringappend_13330)) of + Some (stringappend_13340,stringappend_13350) => + (let stringappend_13360 = (string_drop stringappend_13330 stringappend_13350) in + if ((case ((reg_name_matches_prefix stringappend_13360 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_13370,stringappend_13380) => + (let stringappend_13390 = + (string_drop stringappend_13360 stringappend_13380) in + if ((case ((sep_matches_prefix stringappend_13390)) of + Some (stringappend_13400,stringappend_13410) => + (let stringappend_13420 = + (string_drop stringappend_13390 stringappend_13410) in + if ((case ((reg_name_matches_prefix stringappend_13420 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_13430,stringappend_13440) => + if(((string_drop stringappend_13420 stringappend_13440)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let ((high, signed1, signed2), stringappend_13260) = + ((case ((mul_mnemonic_matches_prefix stringappend_10760)) of + Some (stringappend_13250,stringappend_13260) => + (stringappend_13250, stringappend_13260) + )) in + (let stringappend_13270 = (string_drop stringappend_10760 stringappend_13260) in + (case + (case ((spc_matches_prefix stringappend_13270)) of + Some (stringappend_13280,stringappend_13290) => + (stringappend_13280, stringappend_13290) + ) of + (_, stringappend_13290) => + (let stringappend_13300 = (string_drop stringappend_13270 + stringappend_13290) in + (let (rd, stringappend_13320) = + ((case ((reg_name_matches_prefix stringappend_13300 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13310,stringappend_13320) => + (stringappend_13310, stringappend_13320) + )) in + (let stringappend_13330 = (string_drop stringappend_13300 + stringappend_13320) in + (case + (case ((sep_matches_prefix stringappend_13330)) of + Some (stringappend_13340,stringappend_13350) => + (stringappend_13340, stringappend_13350) + ) of + (_, stringappend_13350) => + (let stringappend_13360 = (string_drop stringappend_13330 + stringappend_13350) in + (let (rs1, stringappend_13380) = + ((case ((reg_name_matches_prefix stringappend_13360 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13370,stringappend_13380) => + (stringappend_13370, stringappend_13380) + )) in + (let stringappend_13390 = (string_drop stringappend_13360 + stringappend_13380) in + (case + (case ((sep_matches_prefix stringappend_13390)) of + Some (stringappend_13400,stringappend_13410) => + (stringappend_13400, stringappend_13410) + ) of + (_, stringappend_13410) => + (let stringappend_13420 = (string_drop stringappend_13390 + stringappend_13410) in + (let (rs2, stringappend_13440) = + ((case ((reg_name_matches_prefix stringappend_13420 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13430,stringappend_13440) => + (stringappend_13430, stringappend_13440) + )) in + if(((string_drop stringappend_13420 stringappend_13440)) = ('''')) then + (MUL (rs2,rs1,rd,high,signed1,signed2)) else undefined)) + )))) + )))) + ))) + else if (((((string_startswith stringappend_10760 (''div''))) \<and> ((let stringappend_13460 = (string_drop stringappend_10760 ((string_length (''div'')))) in + if ((case ((maybe_not_u_matches_prefix stringappend_13460)) of + Some (stringappend_13470,stringappend_13480) => + (let stringappend_13490 = (string_drop stringappend_13460 stringappend_13480) in + if ((case ((spc_matches_prefix stringappend_13490)) of + Some (stringappend_13500,stringappend_13510) => + (let stringappend_13520 = + (string_drop stringappend_13490 stringappend_13510) in + if ((case ((reg_name_matches_prefix stringappend_13520 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_13530,stringappend_13540) => + (let stringappend_13550 = + (string_drop stringappend_13520 stringappend_13540) in + if ((case ((sep_matches_prefix stringappend_13550)) of + Some (stringappend_13560,stringappend_13570) => + (let stringappend_13580 = + (string_drop stringappend_13550 stringappend_13570) in + if ((case ((reg_name_matches_prefix stringappend_13580 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_13590,stringappend_13600) => + (let stringappend_13610 = + (string_drop stringappend_13580 stringappend_13600) in + if ((case ((sep_matches_prefix stringappend_13610)) of + Some (stringappend_13620,stringappend_13630) => + (let stringappend_13640 = + (string_drop stringappend_13610 stringappend_13630) in + if ((case ((reg_name_matches_prefix stringappend_13640 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_13650,stringappend_13660) => + if(((string_drop stringappend_13640 stringappend_13660)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_13460 = (string_drop stringappend_10760 ((string_length (''div'')))) in + (let (s, stringappend_13480) = + ((case ((maybe_not_u_matches_prefix stringappend_13460)) of + Some (stringappend_13470,stringappend_13480) => + (stringappend_13470, stringappend_13480) + )) in + (let stringappend_13490 = (string_drop stringappend_13460 stringappend_13480) in + (case + (case ((spc_matches_prefix stringappend_13490)) of + Some (stringappend_13500,stringappend_13510) => + (stringappend_13500, stringappend_13510) + ) of + (_, stringappend_13510) => + (let stringappend_13520 = (string_drop stringappend_13490 + stringappend_13510) in + (let (rd, stringappend_13540) = + ((case ((reg_name_matches_prefix stringappend_13520 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13530,stringappend_13540) => + (stringappend_13530, stringappend_13540) + )) in + (let stringappend_13550 = (string_drop stringappend_13520 + stringappend_13540) in + (case + (case ((sep_matches_prefix stringappend_13550)) of + Some (stringappend_13560,stringappend_13570) => + (stringappend_13560, stringappend_13570) + ) of + (_, stringappend_13570) => + (let stringappend_13580 = (string_drop stringappend_13550 + stringappend_13570) in + (let (rs1, stringappend_13600) = + ((case ((reg_name_matches_prefix stringappend_13580 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13590,stringappend_13600) => + (stringappend_13590, stringappend_13600) + )) in + (let stringappend_13610 = (string_drop stringappend_13580 + stringappend_13600) in + (case + (case ((sep_matches_prefix stringappend_13610)) of + Some (stringappend_13620,stringappend_13630) => + (stringappend_13620, stringappend_13630) + ) of + (_, stringappend_13630) => + (let stringappend_13640 = (string_drop stringappend_13610 + stringappend_13630) in + (let (rs2, stringappend_13660) = + ((case ((reg_name_matches_prefix stringappend_13640 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13650,stringappend_13660) => + (stringappend_13650, stringappend_13660) + )) in + if(((string_drop stringappend_13640 stringappend_13660)) = ('''')) then + (DIV (rs2,rs1,rd,s)) else undefined)) + )))) + )))) + )))) + else if (((((string_startswith stringappend_10760 (''rem''))) \<and> ((let stringappend_13680 = (string_drop stringappend_10760 ((string_length (''rem'')))) in + if ((case ((maybe_not_u_matches_prefix stringappend_13680)) of + Some (stringappend_13690,stringappend_13700) => + (let stringappend_13710 = (string_drop stringappend_13680 stringappend_13700) in + if ((case ((spc_matches_prefix stringappend_13710)) of + Some (stringappend_13720,stringappend_13730) => + (let stringappend_13740 = + (string_drop stringappend_13710 stringappend_13730) in + if ((case ((reg_name_matches_prefix stringappend_13740 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_13750,stringappend_13760) => + (let stringappend_13770 = + (string_drop stringappend_13740 stringappend_13760) in + if ((case ((sep_matches_prefix stringappend_13770)) of + Some (stringappend_13780,stringappend_13790) => + (let stringappend_13800 = + (string_drop stringappend_13770 stringappend_13790) in + if ((case ((reg_name_matches_prefix stringappend_13800 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_13810,stringappend_13820) => + (let stringappend_13830 = + (string_drop stringappend_13800 stringappend_13820) in + if ((case ((sep_matches_prefix stringappend_13830)) of + Some (stringappend_13840,stringappend_13850) => + (let stringappend_13860 = + (string_drop stringappend_13830 stringappend_13850) in + if ((case ((reg_name_matches_prefix stringappend_13860 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_13870,stringappend_13880) => + if(((string_drop stringappend_13860 stringappend_13880)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_13680 = (string_drop stringappend_10760 ((string_length (''rem'')))) in + (let (s, stringappend_13700) = + ((case ((maybe_not_u_matches_prefix stringappend_13680)) of + Some (stringappend_13690,stringappend_13700) => + (stringappend_13690, stringappend_13700) + )) in + (let stringappend_13710 = (string_drop stringappend_13680 stringappend_13700) in + (case + (case ((spc_matches_prefix stringappend_13710)) of + Some (stringappend_13720,stringappend_13730) => + (stringappend_13720, stringappend_13730) + ) of + (_, stringappend_13730) => + (let stringappend_13740 = (string_drop stringappend_13710 + stringappend_13730) in + (let (rd, stringappend_13760) = + ((case ((reg_name_matches_prefix stringappend_13740 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13750,stringappend_13760) => + (stringappend_13750, stringappend_13760) + )) in + (let stringappend_13770 = (string_drop stringappend_13740 + stringappend_13760) in + (case + (case ((sep_matches_prefix stringappend_13770)) of + Some (stringappend_13780,stringappend_13790) => + (stringappend_13780, stringappend_13790) + ) of + (_, stringappend_13790) => + (let stringappend_13800 = (string_drop stringappend_13770 + stringappend_13790) in + (let (rs1, stringappend_13820) = + ((case ((reg_name_matches_prefix stringappend_13800 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13810,stringappend_13820) => + (stringappend_13810, stringappend_13820) + )) in + (let stringappend_13830 = (string_drop stringappend_13800 + stringappend_13820) in + (case + (case ((sep_matches_prefix stringappend_13830)) of + Some (stringappend_13840,stringappend_13850) => + (stringappend_13840, stringappend_13850) + ) of + (_, stringappend_13850) => + (let stringappend_13860 = (string_drop stringappend_13830 + stringappend_13850) in + (let (rs2, stringappend_13880) = + ((case ((reg_name_matches_prefix stringappend_13860 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13870,stringappend_13880) => + (stringappend_13870, stringappend_13880) + )) in + if(((string_drop stringappend_13860 stringappend_13880)) = ('''')) then + (REM (rs2,rs1,rd,s)) else undefined)) + )))) + )))) + )))) + else if (((((string_startswith stringappend_10760 (''mulw''))) \<and> ((let stringappend_13900 = (string_drop stringappend_10760 ((string_length (''mulw'')))) in + if ((case ((spc_matches_prefix stringappend_13900)) of + Some (stringappend_13910,stringappend_13920) => + (let stringappend_13930 = (string_drop stringappend_13900 stringappend_13920) in + if ((case ((reg_name_matches_prefix stringappend_13930 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_13940,stringappend_13950) => + (let stringappend_13960 = + (string_drop stringappend_13930 stringappend_13950) in + if ((case ((sep_matches_prefix stringappend_13960)) of + Some (stringappend_13970,stringappend_13980) => + (let stringappend_13990 = + (string_drop stringappend_13960 stringappend_13980) in + if ((case ((reg_name_matches_prefix stringappend_13990 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_14000,stringappend_14010) => + (let stringappend_14020 = + (string_drop stringappend_13990 stringappend_14010) in + if ((case ((sep_matches_prefix stringappend_14020)) of + Some (stringappend_14030,stringappend_14040) => + (let stringappend_14050 = + (string_drop stringappend_14020 stringappend_14040) in + if ((case ((reg_name_matches_prefix stringappend_14050 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_14060,stringappend_14070) => + if(((string_drop stringappend_14050 stringappend_14070)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_13900 = (string_drop stringappend_10760 ((string_length (''mulw'')))) in + (case + (case ((spc_matches_prefix stringappend_13900)) of + Some (stringappend_13910,stringappend_13920) => + (stringappend_13910, stringappend_13920) + ) of + (_, stringappend_13920) => + (let stringappend_13930 = (string_drop stringappend_13900 + stringappend_13920) in + (let (rd, stringappend_13950) = + ((case ((reg_name_matches_prefix stringappend_13930 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_13940,stringappend_13950) => + (stringappend_13940, stringappend_13950) + )) in + (let stringappend_13960 = (string_drop stringappend_13930 + stringappend_13950) in + (case + (case ((sep_matches_prefix stringappend_13960)) of + Some (stringappend_13970,stringappend_13980) => + (stringappend_13970, stringappend_13980) + ) of + (_, stringappend_13980) => + (let stringappend_13990 = (string_drop stringappend_13960 + stringappend_13980) in + (let (rs1, stringappend_14010) = + ((case ((reg_name_matches_prefix stringappend_13990 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14000,stringappend_14010) => + (stringappend_14000, stringappend_14010) + )) in + (let stringappend_14020 = (string_drop stringappend_13990 + stringappend_14010) in + (case + (case ((sep_matches_prefix stringappend_14020)) of + Some (stringappend_14030,stringappend_14040) => + (stringappend_14030, stringappend_14040) + ) of + (_, stringappend_14040) => + (let stringappend_14050 = (string_drop stringappend_14020 + stringappend_14040) in + (let (rs2, stringappend_14070) = + ((case ((reg_name_matches_prefix stringappend_14050 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14060,stringappend_14070) => + (stringappend_14060, stringappend_14070) + )) in + if(((string_drop stringappend_14050 stringappend_14070)) = ('''')) then + (MULW (rs2,rs1,rd)) else undefined)) + )))) + )))) + )) + else if (((((string_startswith stringappend_10760 (''div''))) \<and> ((let stringappend_14090 = (string_drop stringappend_10760 ((string_length (''div'')))) in + if ((case ((maybe_not_u_matches_prefix stringappend_14090)) of + Some (stringappend_14100,stringappend_14110) => + (let stringappend_14120 = (string_drop stringappend_14090 stringappend_14110) in + if (((((string_startswith stringappend_14120 (''w''))) \<and> ((let stringappend_14130 = + (string_drop stringappend_14120 ((string_length (''w'')))) in + if ((case ((spc_matches_prefix stringappend_14130)) of + Some (stringappend_14140,stringappend_14150) => + (let stringappend_14160 = + (string_drop stringappend_14130 stringappend_14150) in + if ((case ((reg_name_matches_prefix stringappend_14160 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_14170,stringappend_14180) => + (let stringappend_14190 = + (string_drop stringappend_14160 stringappend_14180) in + if ((case ((sep_matches_prefix stringappend_14190)) of + Some (stringappend_14200,stringappend_14210) => + (let stringappend_14220 = + (string_drop stringappend_14190 stringappend_14210) in + if ((case ((reg_name_matches_prefix stringappend_14220 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_14230,stringappend_14240) => + (let stringappend_14250 = + (string_drop stringappend_14220 stringappend_14240) in + if ((case ((sep_matches_prefix stringappend_14250)) of + Some (stringappend_14260,stringappend_14270) => + (let stringappend_14280 = + (string_drop stringappend_14250 + stringappend_14270) in + if ((case ((reg_name_matches_prefix + stringappend_14280 + :: (( 5 Word.word * ii))option)) of + Some + (stringappend_14290,stringappend_14300) => + if(((string_drop stringappend_14280 stringappend_14300)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_14090 = (string_drop stringappend_10760 ((string_length (''div'')))) in + (let (s, stringappend_14110) = + ((case ((maybe_not_u_matches_prefix stringappend_14090)) of + Some (stringappend_14100,stringappend_14110) => + (stringappend_14100, stringappend_14110) + )) in + (let stringappend_14120 = (string_drop stringappend_14090 stringappend_14110) in + (let stringappend_14130 = (string_drop stringappend_14120 ((string_length (''w'')))) in + (case + (case ((spc_matches_prefix stringappend_14130)) of + Some (stringappend_14140,stringappend_14150) => + (stringappend_14140, stringappend_14150) + ) of + (_, stringappend_14150) => + (let stringappend_14160 = (string_drop stringappend_14130 + stringappend_14150) in + (let (rd, stringappend_14180) = + ((case ((reg_name_matches_prefix stringappend_14160 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14170,stringappend_14180) => + (stringappend_14170, stringappend_14180) + )) in + (let stringappend_14190 = (string_drop stringappend_14160 + stringappend_14180) in + (case + (case ((sep_matches_prefix stringappend_14190)) of + Some (stringappend_14200,stringappend_14210) => + (stringappend_14200, stringappend_14210) + ) of + (_, stringappend_14210) => + (let stringappend_14220 = (string_drop stringappend_14190 + stringappend_14210) in + (let (rs1, stringappend_14240) = + ((case ((reg_name_matches_prefix stringappend_14220 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14230,stringappend_14240) => + (stringappend_14230, stringappend_14240) + )) in + (let stringappend_14250 = (string_drop stringappend_14220 + stringappend_14240) in + (case + (case ((sep_matches_prefix stringappend_14250)) of + Some (stringappend_14260,stringappend_14270) => + (stringappend_14260, stringappend_14270) + ) of + (_, stringappend_14270) => + (let stringappend_14280 = (string_drop stringappend_14250 + stringappend_14270) in + (let (rs2, stringappend_14300) = + ((case ((reg_name_matches_prefix stringappend_14280 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14290,stringappend_14300) => + (stringappend_14290, stringappend_14300) + )) in + if(((string_drop stringappend_14280 stringappend_14300)) = ('''')) then + (DIVW (rs2,rs1,rd,s)) else undefined)) + )))) + )))) + ))))) + else if (((((string_startswith stringappend_10760 (''rem''))) \<and> ((let stringappend_14320 = (string_drop stringappend_10760 ((string_length (''rem'')))) in + if ((case ((maybe_not_u_matches_prefix stringappend_14320)) of + Some (stringappend_14330,stringappend_14340) => + (let stringappend_14350 = (string_drop stringappend_14320 stringappend_14340) in + if (((((string_startswith stringappend_14350 (''w''))) \<and> ((let stringappend_14360 = + (string_drop stringappend_14350 ((string_length (''w'')))) in + if ((case ((spc_matches_prefix stringappend_14360)) of + Some (stringappend_14370,stringappend_14380) => + (let stringappend_14390 = + (string_drop stringappend_14360 stringappend_14380) in + if ((case ((reg_name_matches_prefix stringappend_14390 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_14400,stringappend_14410) => + (let stringappend_14420 = + (string_drop stringappend_14390 stringappend_14410) in + if ((case ((sep_matches_prefix stringappend_14420)) of + Some (stringappend_14430,stringappend_14440) => + (let stringappend_14450 = + (string_drop stringappend_14420 stringappend_14440) in + if ((case ((reg_name_matches_prefix stringappend_14450 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_14460,stringappend_14470) => + (let stringappend_14480 = + (string_drop stringappend_14450 stringappend_14470) in + if ((case ((sep_matches_prefix stringappend_14480)) of + Some (stringappend_14490,stringappend_14500) => + (let stringappend_14510 = + (string_drop stringappend_14480 + stringappend_14500) in + if ((case ((reg_name_matches_prefix + stringappend_14510 + :: (( 5 Word.word * ii))option)) of + Some + (stringappend_14520,stringappend_14530) => + if(((string_drop stringappend_14510 stringappend_14530)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_14320 = (string_drop stringappend_10760 ((string_length (''rem'')))) in + (let (s, stringappend_14340) = + ((case ((maybe_not_u_matches_prefix stringappend_14320)) of + Some (stringappend_14330,stringappend_14340) => + (stringappend_14330, stringappend_14340) + )) in + (let stringappend_14350 = (string_drop stringappend_14320 stringappend_14340) in + (let stringappend_14360 = (string_drop stringappend_14350 ((string_length (''w'')))) in + (case + (case ((spc_matches_prefix stringappend_14360)) of + Some (stringappend_14370,stringappend_14380) => + (stringappend_14370, stringappend_14380) + ) of + (_, stringappend_14380) => + (let stringappend_14390 = (string_drop stringappend_14360 + stringappend_14380) in + (let (rd, stringappend_14410) = + ((case ((reg_name_matches_prefix stringappend_14390 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14400,stringappend_14410) => + (stringappend_14400, stringappend_14410) + )) in + (let stringappend_14420 = (string_drop stringappend_14390 + stringappend_14410) in + (case + (case ((sep_matches_prefix stringappend_14420)) of + Some (stringappend_14430,stringappend_14440) => + (stringappend_14430, stringappend_14440) + ) of + (_, stringappend_14440) => + (let stringappend_14450 = (string_drop stringappend_14420 + stringappend_14440) in + (let (rs1, stringappend_14470) = + ((case ((reg_name_matches_prefix stringappend_14450 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14460,stringappend_14470) => + (stringappend_14460, stringappend_14470) + )) in + (let stringappend_14480 = (string_drop stringappend_14450 + stringappend_14470) in + (case + (case ((sep_matches_prefix stringappend_14480)) of + Some (stringappend_14490,stringappend_14500) => + (stringappend_14490, stringappend_14500) + ) of + (_, stringappend_14500) => + (let stringappend_14510 = (string_drop stringappend_14480 + stringappend_14500) in + (let (rs2, stringappend_14530) = + ((case ((reg_name_matches_prefix stringappend_14510 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14520,stringappend_14530) => + (stringappend_14520, stringappend_14530) + )) in + if(((string_drop stringappend_14510 stringappend_14530)) = ('''')) then + (REMW (rs2,rs1,rd,s)) else undefined)) + )))) + )))) + ))))) + else if (((((string_startswith stringappend_10760 (''fence''))) \<and> ((let stringappend_14550 = (string_drop stringappend_10760 ((string_length (''fence'')))) in + if ((case ((spc_matches_prefix stringappend_14550)) of + Some (stringappend_14560,stringappend_14570) => + (let stringappend_14580 = (string_drop stringappend_14550 stringappend_14570) in + if ((case ((fence_bits_matches_prefix stringappend_14580 + :: (( 4 Word.word * ii))option)) of + Some (stringappend_14590,stringappend_14600) => + (let stringappend_14610 = + (string_drop stringappend_14580 stringappend_14600) in + if ((case ((sep_matches_prefix stringappend_14610)) of + Some (stringappend_14620,stringappend_14630) => + (let stringappend_14640 = + (string_drop stringappend_14610 stringappend_14630) in + if ((case ((fence_bits_matches_prefix stringappend_14640 + :: (( 4 Word.word * ii))option)) of + Some (stringappend_14650,stringappend_14660) => + if(((string_drop stringappend_14640 stringappend_14660)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_14550 = (string_drop stringappend_10760 ((string_length (''fence'')))) in + (case + (case ((spc_matches_prefix stringappend_14550)) of + Some (stringappend_14560,stringappend_14570) => + (stringappend_14560, stringappend_14570) + ) of + (_, stringappend_14570) => + (let stringappend_14580 = (string_drop stringappend_14550 + stringappend_14570) in + (let (pred, stringappend_14600) = + ((case ((fence_bits_matches_prefix stringappend_14580 :: (( 4 Word.word * ii)) option)) of + Some (stringappend_14590,stringappend_14600) => + (stringappend_14590, stringappend_14600) + )) in + (let stringappend_14610 = (string_drop stringappend_14580 + stringappend_14600) in + (case + (case ((sep_matches_prefix stringappend_14610)) of + Some (stringappend_14620,stringappend_14630) => + (stringappend_14620, stringappend_14630) + ) of + (_, stringappend_14630) => + (let stringappend_14640 = (string_drop stringappend_14610 + stringappend_14630) in + (let (succ, stringappend_14660) = + ((case ((fence_bits_matches_prefix stringappend_14640 :: (( 4 Word.word * ii)) option)) of + Some (stringappend_14650,stringappend_14660) => + (stringappend_14650, stringappend_14660) + )) in + if(((string_drop stringappend_14640 stringappend_14660)) = ('''')) then + (FENCE (pred,succ)) else undefined)) + )))) + )) + else if(stringappend_10760 = (''fence.i'')) then (FENCEI () ) else + ( + if(stringappend_10760 = (''ecall'')) then (ECALL () ) else + ( + if(stringappend_10760 = (''mret'')) then (MRET () ) else + ( + if(stringappend_10760 = (''sret'')) then (SRET () ) else + ( + if(stringappend_10760 = (''ebreak'')) then (EBREAK () ) else + ( + if(stringappend_10760 = (''wfi'')) then (WFI () ) else + ( + if (((((string_startswith stringappend_10760 (''sfence.vma''))) + \<and> + ((let stringappend_14680 = + (string_drop stringappend_10760 + ((string_length (''sfence.vma'')))) in + if ((case ((spc_matches_prefix stringappend_14680)) of + Some (stringappend_14690,stringappend_14700) => + (let stringappend_14710 = (string_drop + stringappend_14680 + stringappend_14700) in + if ((case ((reg_name_matches_prefix + stringappend_14710 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14720,stringappend_14730) => + (let stringappend_14740 = + (string_drop stringappend_14710 + stringappend_14730) in + if ((case ((sep_matches_prefix + stringappend_14740)) of + Some (stringappend_14750,stringappend_14760) => + (let stringappend_14770 = + (string_drop stringappend_14740 + stringappend_14760) in + if ((case ((reg_name_matches_prefix + stringappend_14770 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14780,stringappend_14790) => + if(((string_drop stringappend_14770 + stringappend_14790)) = ('''')) then + True else False + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False))))) then + (let stringappend_14680 = (string_drop stringappend_10760 + ((string_length (''sfence.vma'')))) in + (case + (case ((spc_matches_prefix stringappend_14680)) of + Some (stringappend_14690,stringappend_14700) => + (stringappend_14690, stringappend_14700) + ) of + (_, stringappend_14700) => + (let stringappend_14710 = (string_drop stringappend_14680 + stringappend_14700) in + (let (rs1, stringappend_14730) = + ((case ((reg_name_matches_prefix stringappend_14710 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14720,stringappend_14730) => + (stringappend_14720, stringappend_14730) + )) in + (let stringappend_14740 = (string_drop stringappend_14710 + stringappend_14730) in + (case + (case ((sep_matches_prefix stringappend_14740)) of + Some (stringappend_14750,stringappend_14760) => + (stringappend_14750, stringappend_14760) + ) of + (_, stringappend_14760) => + (let stringappend_14770 = (string_drop stringappend_14740 + stringappend_14760) in + (let (rs2, stringappend_14790) = + ((case ((reg_name_matches_prefix stringappend_14770 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14780,stringappend_14790) => + (stringappend_14780, stringappend_14790) + )) in + if(((string_drop stringappend_14770 stringappend_14790)) = + ('''')) then (SFENCE_VMA (rs1,rs2)) else undefined)) + )))) + )) else + if (((((string_startswith stringappend_10760 (''lr.''))) + \<and> + ((let stringappend_14810 = + (string_drop stringappend_10760 + ((string_length (''lr.'')))) in + if ((case ((maybe_aq_matches_prefix + stringappend_14810)) of + Some (stringappend_14820,stringappend_14830) => + (let stringappend_14840 = + (string_drop stringappend_14810 + stringappend_14830) in + if ((case ((maybe_rl_matches_prefix + stringappend_14840)) of + Some (stringappend_14850,stringappend_14860) => + (let stringappend_14870 = + (string_drop stringappend_14840 + stringappend_14860) in + if ((case ((size_mnemonic_matches_prefix + stringappend_14870)) of + Some (stringappend_14880,stringappend_14890) => + (let stringappend_14900 = + (string_drop stringappend_14870 + stringappend_14890) in + if ((case ((spc_matches_prefix + stringappend_14900)) of + Some (stringappend_14910,stringappend_14920) => + (let stringappend_14930 = + (string_drop stringappend_14900 + stringappend_14920) in + if ((case ((reg_name_matches_prefix + stringappend_14930 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14940,stringappend_14950) => + (let stringappend_14960 = + (string_drop + stringappend_14930 + stringappend_14950) in + if ((case ((sep_matches_prefix + stringappend_14960)) of + Some (stringappend_14970,stringappend_14980) => + (let stringappend_14990 = + (string_drop + stringappend_14960 + stringappend_14980) in + if ((case ((reg_name_matches_prefix + stringappend_14990 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15000,stringappend_15010) => + if(((string_drop + stringappend_14990 + stringappend_15010)) + = ('''')) then + True else False + | None => False + )) then True else + False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False))))) then + (let stringappend_14810 = (string_drop stringappend_10760 + ((string_length (''lr.'')))) in + (let (aq, stringappend_14830) = + ((case ((maybe_aq_matches_prefix stringappend_14810)) of + Some (stringappend_14820,stringappend_14830) => + (stringappend_14820, stringappend_14830) + )) in + (let stringappend_14840 = (string_drop stringappend_14810 + stringappend_14830) in + (let (rl, stringappend_14860) = + ((case ((maybe_rl_matches_prefix stringappend_14840)) of + Some (stringappend_14850,stringappend_14860) => + (stringappend_14850, stringappend_14860) + )) in + (let stringappend_14870 = (string_drop stringappend_14840 + stringappend_14860) in + (let (size1, stringappend_14890) = + ((case ((size_mnemonic_matches_prefix + stringappend_14870)) of + Some (stringappend_14880,stringappend_14890) => + (stringappend_14880, stringappend_14890) + )) in + (let stringappend_14900 = (string_drop stringappend_14870 + stringappend_14890) in + (case + (case ((spc_matches_prefix stringappend_14900)) of + Some (stringappend_14910,stringappend_14920) => + (stringappend_14910, stringappend_14920) + ) of + (_, stringappend_14920) => + (let stringappend_14930 = (string_drop stringappend_14900 + stringappend_14920) in + (let (rd, stringappend_14950) = + ((case ((reg_name_matches_prefix stringappend_14930 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_14940,stringappend_14950) => + (stringappend_14940, stringappend_14950) + )) in + (let stringappend_14960 = (string_drop stringappend_14930 + stringappend_14950) in + (case + (case ((sep_matches_prefix stringappend_14960)) of + Some (stringappend_14970,stringappend_14980) => + (stringappend_14970, stringappend_14980) + ) of + (_, stringappend_14980) => + (let stringappend_14990 = (string_drop stringappend_14960 + stringappend_14980) in + (let (rs1, stringappend_15010) = + ((case ((reg_name_matches_prefix stringappend_14990 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15000,stringappend_15010) => + (stringappend_15000, stringappend_15010) + )) in + if(((string_drop stringappend_14990 stringappend_15010)) = + ('''')) then (LOADRES (aq,rl,rs1,size1,rd)) else + undefined)) + )))) + )))))))) else + if (((((string_startswith stringappend_10760 (''sc.''))) + \<and> + ((let stringappend_15030 = + (string_drop stringappend_10760 + ((string_length (''sc.'')))) in + if ((case ((maybe_aq_matches_prefix + stringappend_15030)) of + Some (stringappend_15040,stringappend_15050) => + (let stringappend_15060 = + (string_drop stringappend_15030 + stringappend_15050) in + if ((case ((maybe_rl_matches_prefix + stringappend_15060)) of + Some (stringappend_15070,stringappend_15080) => + (let stringappend_15090 = + (string_drop stringappend_15060 + stringappend_15080) in + if ((case ((size_mnemonic_matches_prefix + stringappend_15090)) of + Some (stringappend_15100,stringappend_15110) => + (let stringappend_15120 = + (string_drop stringappend_15090 + stringappend_15110) in + if ((case ((spc_matches_prefix + stringappend_15120)) of + Some (stringappend_15130,stringappend_15140) => + (let stringappend_15150 = + (string_drop + stringappend_15120 + stringappend_15140) in + if ((case ((reg_name_matches_prefix + stringappend_15150 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15160,stringappend_15170) => + (let stringappend_15180 = + (string_drop + stringappend_15150 + stringappend_15170) in + if ((case ((sep_matches_prefix + stringappend_15180)) of + Some (stringappend_15190,stringappend_15200) => + (let stringappend_15210 = + (string_drop + stringappend_15180 + stringappend_15200) in + if ((case ((reg_name_matches_prefix + stringappend_15210 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15220,stringappend_15230) => + (let stringappend_15240 = + (string_drop + stringappend_15210 + stringappend_15230) in + if ((case ((sep_matches_prefix + stringappend_15240)) of + Some + (stringappend_15250,stringappend_15260) => + (let stringappend_15270 = + (string_drop + stringappend_15240 + stringappend_15260) in + if ((case + ((reg_name_matches_prefix + stringappend_15270 + :: (( 5 Word.word * ii)) option)) of + Some + (stringappend_15280,stringappend_15290) => + if(((string_drop + stringappend_15270 + stringappend_15290)) + = + ('''')) then + True else + False + | None => + False + )) then + True else False) + | None => + False + )) then True else + False) + | None => False + )) then True else + False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False))))) then + (let stringappend_15030 = (string_drop stringappend_10760 + ((string_length (''sc.'')))) in + (let (aq, stringappend_15050) = + ((case ((maybe_aq_matches_prefix stringappend_15030)) of + Some (stringappend_15040,stringappend_15050) => + (stringappend_15040, stringappend_15050) + )) in + (let stringappend_15060 = (string_drop stringappend_15030 + stringappend_15050) in + (let (rl, stringappend_15080) = + ((case ((maybe_rl_matches_prefix stringappend_15060)) of + Some (stringappend_15070,stringappend_15080) => + (stringappend_15070, stringappend_15080) + )) in + (let stringappend_15090 = (string_drop stringappend_15060 + stringappend_15080) in + (let (size1, stringappend_15110) = + ((case ((size_mnemonic_matches_prefix + stringappend_15090)) of + Some (stringappend_15100,stringappend_15110) => + (stringappend_15100, stringappend_15110) + )) in + (let stringappend_15120 = (string_drop stringappend_15090 + stringappend_15110) in + (case + (case ((spc_matches_prefix stringappend_15120)) of + Some (stringappend_15130,stringappend_15140) => + (stringappend_15130, stringappend_15140) + ) of + (_, stringappend_15140) => + (let stringappend_15150 = (string_drop stringappend_15120 + stringappend_15140) in + (let (rd, stringappend_15170) = + ((case ((reg_name_matches_prefix stringappend_15150 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15160,stringappend_15170) => + (stringappend_15160, stringappend_15170) + )) in + (let stringappend_15180 = (string_drop stringappend_15150 + stringappend_15170) in + (case + (case ((sep_matches_prefix stringappend_15180)) of + Some (stringappend_15190,stringappend_15200) => + (stringappend_15190, stringappend_15200) + ) of + (_, stringappend_15200) => + (let stringappend_15210 = (string_drop stringappend_15180 + stringappend_15200) in + (let (rs1, stringappend_15230) = + ((case ((reg_name_matches_prefix stringappend_15210 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15220,stringappend_15230) => + (stringappend_15220, stringappend_15230) + )) in + (let stringappend_15240 = (string_drop stringappend_15210 + stringappend_15230) in + (case + (case ((sep_matches_prefix stringappend_15240)) of + Some (stringappend_15250,stringappend_15260) => + (stringappend_15250, stringappend_15260) + ) of + (_, stringappend_15260) => + (let stringappend_15270 = (string_drop stringappend_15240 + stringappend_15260) in + (let (rs2, stringappend_15290) = + ((case ((reg_name_matches_prefix stringappend_15270 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15280,stringappend_15290) => + (stringappend_15280, stringappend_15290) + )) in + if(((string_drop stringappend_15270 stringappend_15290)) = + ('''')) then (STORECON (aq,rl,rs2,rs1,size1,rd)) else + undefined)) + )))) + )))) + )))))))) else + if ((case ((amo_mnemonic_matches_prefix + stringappend_10760)) of + Some (stringappend_15310,stringappend_15320) => + (let stringappend_15330 = (string_drop + stringappend_10760 + stringappend_15320) in + if (((((string_startswith stringappend_15330 (''.''))) + \<and> + ((let stringappend_15340 = (string_drop + stringappend_15330 + ((string_length + (''.'')))) in + if ((case ((size_mnemonic_matches_prefix + stringappend_15340)) of + Some (stringappend_15350,stringappend_15360) => + (let stringappend_15370 = + (string_drop stringappend_15340 + stringappend_15360) in + if ((case ((maybe_aq_matches_prefix + stringappend_15370)) of + Some (stringappend_15380,stringappend_15390) => + (let stringappend_15400 = + (string_drop stringappend_15370 + stringappend_15390) in + if ((case ((maybe_rl_matches_prefix + stringappend_15400)) of + Some (stringappend_15410,stringappend_15420) => + (let stringappend_15430 = + (string_drop + stringappend_15400 + stringappend_15420) in + if ((case ((spc_matches_prefix + stringappend_15430)) of + Some (stringappend_15440,stringappend_15450) => + (let stringappend_15460 = + (string_drop + stringappend_15430 + stringappend_15450) in + if ((case ((reg_name_matches_prefix + stringappend_15460 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15470,stringappend_15480) => + (let stringappend_15490 = + (string_drop + stringappend_15460 + stringappend_15480) in + if ((case ((sep_matches_prefix + stringappend_15490)) of + Some (stringappend_15500,stringappend_15510) => + (let stringappend_15520 = + (string_drop + stringappend_15490 + stringappend_15510) in + if ((case (( + reg_name_matches_prefix + stringappend_15520 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15530,stringappend_15540) => + (let stringappend_15550 = + (string_drop + stringappend_15520 + stringappend_15540) in + if ((case + ((sep_matches_prefix + stringappend_15550)) of + Some + (stringappend_15560,stringappend_15570) => + (let + stringappend_15580 = + (string_drop + stringappend_15550 + stringappend_15570) in + if ((case + ( + ( + reg_name_matches_prefix + stringappend_15580 + :: (( 5 Word.word * ii)) option)) of + Some + (stringappend_15590,stringappend_15600) => + if + ( + ( + ( + string_drop + stringappend_15580 + stringappend_15600)) + = + ('''')) then + True else + False + | None => + False + )) then + True else + False) + | None => + False + )) then + True else + False) + | None => + False + )) then True else + False) + | None => False + )) then True else + False) + | None => False + )) then True else + False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False))))) then + True else False) + | None => False + )) then + (let (op1, stringappend_15320) = + ((case ((amo_mnemonic_matches_prefix + stringappend_10760)) of + Some (stringappend_15310,stringappend_15320) => + (stringappend_15310, stringappend_15320) + )) in + (let stringappend_15330 = (string_drop + stringappend_10760 + stringappend_15320) in + (let stringappend_15340 = (string_drop + stringappend_15330 + ((string_length (''.'')))) in + (let (width, stringappend_15360) = + ((case ((size_mnemonic_matches_prefix + stringappend_15340)) of + Some (stringappend_15350,stringappend_15360) => + (stringappend_15350, stringappend_15360) + )) in + (let stringappend_15370 = (string_drop + stringappend_15340 + stringappend_15360) in + (let (aq, stringappend_15390) = + ((case ((maybe_aq_matches_prefix + stringappend_15370)) of + Some (stringappend_15380,stringappend_15390) => + (stringappend_15380, stringappend_15390) + )) in + (let stringappend_15400 = (string_drop + stringappend_15370 + stringappend_15390) in + (let (rl, stringappend_15420) = + ((case ((maybe_rl_matches_prefix + stringappend_15400)) of + Some (stringappend_15410,stringappend_15420) => + (stringappend_15410, stringappend_15420) + )) in + (let stringappend_15430 = (string_drop + stringappend_15400 + stringappend_15420) in + (case + (case ((spc_matches_prefix stringappend_15430)) of + Some (stringappend_15440,stringappend_15450) => + (stringappend_15440, stringappend_15450) + ) of + (_, stringappend_15450) => + (let stringappend_15460 = (string_drop + stringappend_15430 + stringappend_15450) in + (let (rd, stringappend_15480) = + ((case ((reg_name_matches_prefix + stringappend_15460 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15470,stringappend_15480) => + (stringappend_15470, stringappend_15480) + )) in + (let stringappend_15490 = (string_drop + stringappend_15460 + stringappend_15480) in + (case + (case ((sep_matches_prefix stringappend_15490)) of + Some (stringappend_15500,stringappend_15510) => + (stringappend_15500, stringappend_15510) + ) of + (_, stringappend_15510) => + (let stringappend_15520 = (string_drop + stringappend_15490 + stringappend_15510) in + (let (rs1, stringappend_15540) = + ((case ((reg_name_matches_prefix + stringappend_15520 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15530,stringappend_15540) => + (stringappend_15530, stringappend_15540) + )) in + (let stringappend_15550 = (string_drop + stringappend_15520 + stringappend_15540) in + (case + (case ((sep_matches_prefix stringappend_15550)) of + Some (stringappend_15560,stringappend_15570) => + (stringappend_15560, stringappend_15570) + ) of + (_, stringappend_15570) => + (let stringappend_15580 = (string_drop + stringappend_15550 + stringappend_15570) in + (let (rs2, stringappend_15600) = + ((case ((reg_name_matches_prefix + stringappend_15580 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15590,stringappend_15600) => + (stringappend_15590, stringappend_15600) + )) in + if(((string_drop stringappend_15580 stringappend_15600)) + = ('''')) then (AMO (op1,aq,rl,rs2,rs1,width,rd)) + else undefined)) + )))) + )))) + )))))))))) else + if ((case ((csr_mnemonic_matches_prefix + stringappend_10760)) of + Some (stringappend_15620,stringappend_15630) => + (let stringappend_15640 = (string_drop + stringappend_10760 + stringappend_15630) in + if (((((string_startswith stringappend_15640 (''i''))) + \<and> + ((let stringappend_15650 = (string_drop + stringappend_15640 + ((string_length + (''i'')))) in + if ((case ((spc_matches_prefix + stringappend_15650)) of + Some (stringappend_15660,stringappend_15670) => + (let stringappend_15680 = + (string_drop stringappend_15650 + stringappend_15670) in + if ((case ((reg_name_matches_prefix + stringappend_15680 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15690,stringappend_15700) => + (let stringappend_15710 = + (string_drop + stringappend_15680 + stringappend_15700) in + if ((case ((sep_matches_prefix + stringappend_15710)) of + Some (stringappend_15720,stringappend_15730) => + (let stringappend_15740 = + (string_drop + stringappend_15710 + stringappend_15730) in + if ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_15740 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15750,stringappend_15760) => + (let stringappend_15770 = + (string_drop + stringappend_15740 + stringappend_15760) in + if ((case ((sep_matches_prefix + stringappend_15770)) of + Some (stringappend_15780,stringappend_15790) => + (let stringappend_15800 = + (string_drop + stringappend_15770 + stringappend_15790) in + if ((case ((csr_name_map_matches_prefix + stringappend_15800 + :: (( 12 Word.word * ii)) option)) of + Some (stringappend_15810,stringappend_15820) => + if(((string_drop + stringappend_15800 + stringappend_15820)) + = ('''')) then + True else + False + | None => + False + )) then True else + False) + | None => False + )) then True else + False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False))))) then + True else False) + | None => False + )) then + (let (op1, stringappend_15630) = + ((case ((csr_mnemonic_matches_prefix + stringappend_10760)) of + Some (stringappend_15620,stringappend_15630) => + (stringappend_15620, stringappend_15630) + )) in + (let stringappend_15640 = (string_drop + stringappend_10760 + stringappend_15630) in + (let stringappend_15650 = (string_drop + stringappend_15640 + ((string_length (''i'')))) in + (case + (case ((spc_matches_prefix stringappend_15650)) of + Some (stringappend_15660,stringappend_15670) => + (stringappend_15660, stringappend_15670) + ) of + (_, stringappend_15670) => + (let stringappend_15680 = (string_drop + stringappend_15650 + stringappend_15670) in + (let (rd, stringappend_15700) = + ((case ((reg_name_matches_prefix + stringappend_15680 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15690,stringappend_15700) => + (stringappend_15690, stringappend_15700) + )) in + (let stringappend_15710 = (string_drop + stringappend_15680 + stringappend_15700) in + (case + (case ((sep_matches_prefix stringappend_15710)) of + Some (stringappend_15720,stringappend_15730) => + (stringappend_15720, stringappend_15730) + ) of + (_, stringappend_15730) => + (let stringappend_15740 = (string_drop + stringappend_15710 + stringappend_15730) in + (let (rs1, stringappend_15760) = + ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_15740 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15750,stringappend_15760) => + (stringappend_15750, stringappend_15760) + )) in + (let stringappend_15770 = (string_drop + stringappend_15740 + stringappend_15760) in + (case + (case ((sep_matches_prefix stringappend_15770)) of + Some (stringappend_15780,stringappend_15790) => + (stringappend_15780, stringappend_15790) + ) of + (_, stringappend_15790) => + (let stringappend_15800 = (string_drop + stringappend_15770 + stringappend_15790) in + (let (csr, stringappend_15820) = + ((case ((csr_name_map_matches_prefix + stringappend_15800 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_15810,stringappend_15820) => + (stringappend_15810, stringappend_15820) + )) in + if(((string_drop stringappend_15800 stringappend_15820)) + = ('''')) then (CSR (csr,rs1,rd,True,op1)) else + undefined)) + )))) + )))) + )))) else + if ((case ((csr_mnemonic_matches_prefix + stringappend_10760)) of + Some (stringappend_15840,stringappend_15850) => + (let stringappend_15860 = (string_drop + stringappend_10760 + stringappend_15850) in + if ((case ((spc_matches_prefix stringappend_15860)) of + Some (stringappend_15870,stringappend_15880) => + (let stringappend_15890 = (string_drop + stringappend_15860 + stringappend_15880) in + if ((case ((reg_name_matches_prefix + stringappend_15890 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15900,stringappend_15910) => + (let stringappend_15920 = (string_drop + stringappend_15890 + stringappend_15910) in + if ((case ((sep_matches_prefix + stringappend_15920)) of + Some (stringappend_15930,stringappend_15940) => + (let stringappend_15950 = + (string_drop stringappend_15920 + stringappend_15940) in + if ((case ((reg_name_matches_prefix + stringappend_15950 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15960,stringappend_15970) => + (let stringappend_15980 = + (string_drop + stringappend_15950 + stringappend_15970) in + if ((case ((sep_matches_prefix + stringappend_15980)) of + Some (stringappend_15990,stringappend_16000) => + (let stringappend_16010 = + (string_drop + stringappend_15980 + stringappend_16000) in + if ((case ((csr_name_map_matches_prefix + stringappend_16010 + :: (( 12 Word.word * ii)) option)) of + Some (stringappend_16020,stringappend_16030) => + if(((string_drop + stringappend_16010 + stringappend_16030)) + = ('''')) then + True else False + | None => False + )) then True else + False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then + (let (op1, stringappend_15850) = + ((case ((csr_mnemonic_matches_prefix + stringappend_10760)) of + Some (stringappend_15840,stringappend_15850) => + (stringappend_15840, stringappend_15850) + )) in + (let stringappend_15860 = (string_drop + stringappend_10760 + stringappend_15850) in + (case + (case ((spc_matches_prefix stringappend_15860)) of + Some (stringappend_15870,stringappend_15880) => + (stringappend_15870, stringappend_15880) + ) of + (_, stringappend_15880) => + (let stringappend_15890 = (string_drop + stringappend_15860 + stringappend_15880) in + (let (rd, stringappend_15910) = + ((case ((reg_name_matches_prefix + stringappend_15890 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15900,stringappend_15910) => + (stringappend_15900, stringappend_15910) + )) in + (let stringappend_15920 = (string_drop + stringappend_15890 + stringappend_15910) in + (case + (case ((sep_matches_prefix stringappend_15920)) of + Some (stringappend_15930,stringappend_15940) => + (stringappend_15930, stringappend_15940) + ) of + (_, stringappend_15940) => + (let stringappend_15950 = (string_drop + stringappend_15920 + stringappend_15940) in + (let (rs1, stringappend_15970) = + ((case ((reg_name_matches_prefix + stringappend_15950 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_15960,stringappend_15970) => + (stringappend_15960, stringappend_15970) + )) in + (let stringappend_15980 = (string_drop + stringappend_15950 + stringappend_15970) in + (case + (case ((sep_matches_prefix stringappend_15980)) of + Some (stringappend_15990,stringappend_16000) => + (stringappend_15990, stringappend_16000) + ) of + (_, stringappend_16000) => + (let stringappend_16010 = (string_drop + stringappend_15980 + stringappend_16000) in + (let (csr, stringappend_16030) = + ((case ((csr_name_map_matches_prefix + stringappend_16010 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_16020,stringappend_16030) => + (stringappend_16020, stringappend_16030) + )) in + if(((string_drop stringappend_16010 + stringappend_16030)) = ('''')) then + (CSR (csr,rs1,rd,False,op1)) else undefined)) + )))) + )))) + ))) else + (let stringappend_16050 = (string_drop + stringappend_10760 + ((string_length + (''illegal'')))) in + (case + (case ((spc_matches_prefix stringappend_16050)) of + Some (stringappend_16060,stringappend_16070) => + (stringappend_16060, stringappend_16070) + ) of + (_, stringappend_16070) => + (let stringappend_16080 = (string_drop + stringappend_16050 + stringappend_16070) in + (let (s, stringappend_16100) = + ((case ((hex_bits_32_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_16080 :: (( 32 Word.word * ii)) option)) of + Some (stringappend_16090,stringappend_16100) => + (stringappend_16090, stringappend_16100) + )) in + if(((string_drop stringappend_16080 + stringappend_16100)) = ('''')) then + (ILLEGAL s) else undefined)) + ))))))))))" + + +(*val assembly_forwards_matches : ast -> bool*) + +fun assembly_forwards_matches :: " ast \<Rightarrow> bool " where + " assembly_forwards_matches (UTYPE (imm,rd,op1)) = ( True )" +|" assembly_forwards_matches (RISCV_JAL (imm,rd)) = ( True )" +|" assembly_forwards_matches (RISCV_JALR (imm,rs1,rd)) = ( True )" +|" assembly_forwards_matches (BTYPE (imm,rs2,rs1,op1)) = ( True )" +|" assembly_forwards_matches (ITYPE (imm,rs1,rd,op1)) = ( True )" +|" assembly_forwards_matches (SHIFTIOP (shamt,rs1,rd,op1)) = ( True )" +|" assembly_forwards_matches (RTYPE (rs2,rs1,rd,op1)) = ( True )" +|" assembly_forwards_matches (LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl)) = ( True )" +|" assembly_forwards_matches (STORE (imm,rs1,rd,size1,aq,rl)) = ( True )" +|" assembly_forwards_matches (ADDIW (imm,rs1,rd)) = ( True )" +|" assembly_forwards_matches (SHIFTW (shamt,rs1,rd,op1)) = ( True )" +|" assembly_forwards_matches (RTYPEW (rs2,rs1,rd,op1)) = ( True )" +|" assembly_forwards_matches (MUL (rs2,rs1,rd,high,signed1,signed2)) = ( True )" +|" assembly_forwards_matches (DIV (rs2,rs1,rd,s)) = ( True )" +|" assembly_forwards_matches (REM (rs2,rs1,rd,s)) = ( True )" +|" assembly_forwards_matches (MULW (rs2,rs1,rd)) = ( True )" +|" assembly_forwards_matches (DIVW (rs2,rs1,rd,s)) = ( True )" +|" assembly_forwards_matches (REMW (rs2,rs1,rd,s)) = ( True )" +|" assembly_forwards_matches (FENCE (pred,succ)) = ( True )" +|" assembly_forwards_matches (FENCEI (_)) = ( True )" +|" assembly_forwards_matches (ECALL (_)) = ( True )" +|" assembly_forwards_matches (MRET (_)) = ( True )" +|" assembly_forwards_matches (SRET (_)) = ( True )" +|" assembly_forwards_matches (EBREAK (_)) = ( True )" +|" assembly_forwards_matches (WFI (_)) = ( True )" +|" assembly_forwards_matches (SFENCE_VMA (rs1,rs2)) = ( True )" +|" assembly_forwards_matches (LOADRES (aq,rl,rs1,size1,rd)) = ( True )" +|" assembly_forwards_matches (STORECON (aq,rl,rs2,rs1,size1,rd)) = ( True )" +|" assembly_forwards_matches (AMO (op1,aq,rl,rs2,rs1,width,rd)) = ( True )" +|" assembly_forwards_matches (CSR (csr,rs1,rd,True,op1)) = ( True )" +|" assembly_forwards_matches (CSR (csr,rs1,rd,False,op1)) = ( True )" +|" assembly_forwards_matches (ILLEGAL (s)) = ( True )" +|" assembly_forwards_matches _ = ( False )" + + +(*val assembly_backwards_matches : string -> bool*) + +definition assembly_backwards_matches :: " string \<Rightarrow> bool " where + " assembly_backwards_matches arg0 = ( + (let stringappend_5410 = arg0 in + if ((case ((utype_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_5420,stringappend_5430) => + (let stringappend_5440 = (string_drop stringappend_5410 stringappend_5430) in + if ((case ((spc_matches_prefix stringappend_5440)) of + Some (stringappend_5450,stringappend_5460) => + (let stringappend_5470 = (string_drop stringappend_5440 stringappend_5460) in + if ((case ((reg_name_matches_prefix stringappend_5470 :: (( 5 Word.word * ii))option)) of + Some (stringappend_5480,stringappend_5490) => + (let stringappend_5500 = (string_drop stringappend_5470 stringappend_5490) in + if ((case ((sep_matches_prefix stringappend_5500)) of + Some (stringappend_5510,stringappend_5520) => + (let stringappend_5530 = (string_drop stringappend_5500 stringappend_5520) in + if ((case ((hex_bits_20_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_5530 + :: (( 20 Word.word * ii))option)) of + Some (stringappend_5540,stringappend_5550) => + if(((string_drop stringappend_5530 stringappend_5550)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_5430) = + ((case ((utype_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_5420,stringappend_5430) => (stringappend_5420, stringappend_5430) + )) in + (let stringappend_5440 = (string_drop stringappend_5410 stringappend_5430) in + (case + (case ((spc_matches_prefix stringappend_5440)) of + Some (stringappend_5450,stringappend_5460) => (stringappend_5450, stringappend_5460) + ) of + (_, stringappend_5460) => + (let stringappend_5470 = (string_drop stringappend_5440 stringappend_5460) in + (let (rd, stringappend_5490) = + ((case ((reg_name_matches_prefix stringappend_5470 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_5480,stringappend_5490) => (stringappend_5480, stringappend_5490) + )) in + (let stringappend_5500 = (string_drop stringappend_5470 stringappend_5490) in + (case + (case ((sep_matches_prefix stringappend_5500)) of + Some (stringappend_5510,stringappend_5520) => (stringappend_5510, stringappend_5520) + ) of + (_, stringappend_5520) => + (let stringappend_5530 = (string_drop stringappend_5500 stringappend_5520) in + (let (imm, stringappend_5550) = + ((case ((hex_bits_20_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_5530 :: (( 20 Word.word * ii)) option)) of + Some (stringappend_5540,stringappend_5550) => (stringappend_5540, stringappend_5550) + )) in + if(((string_drop stringappend_5530 stringappend_5550)) = ('''')) then + True else undefined)) + )))) + ))) + else if (((((string_startswith stringappend_5410 (''jal''))) \<and> ((let stringappend_5570 = (string_drop stringappend_5410 ((string_length (''jal'')))) in + if ((case ((spc_matches_prefix stringappend_5570)) of + Some (stringappend_5580,stringappend_5590) => + (let stringappend_5600 = (string_drop stringappend_5570 stringappend_5590) in + if ((case ((reg_name_matches_prefix stringappend_5600 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_5610,stringappend_5620) => + (let stringappend_5630 = (string_drop stringappend_5600 stringappend_5620) in + if ((case ((sep_matches_prefix stringappend_5630)) of + Some (stringappend_5640,stringappend_5650) => + (let stringappend_5660 = + (string_drop stringappend_5630 stringappend_5650) in + if ((case ((hex_bits_21_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_5660 + :: (( 21 Word.word * ii))option)) of + Some (stringappend_5670,stringappend_5680) => + if(((string_drop stringappend_5660 stringappend_5680)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_5570 = (string_drop stringappend_5410 ((string_length (''jal'')))) in + (case + (case ((spc_matches_prefix stringappend_5570)) of + Some (stringappend_5580,stringappend_5590) => (stringappend_5580, stringappend_5590) + ) of + (_, stringappend_5590) => + (let stringappend_5600 = (string_drop stringappend_5570 stringappend_5590) in + (let (rd, stringappend_5620) = + ((case ((reg_name_matches_prefix stringappend_5600 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_5610,stringappend_5620) => (stringappend_5610, stringappend_5620) + )) in + (let stringappend_5630 = (string_drop stringappend_5600 stringappend_5620) in + (case + (case ((sep_matches_prefix stringappend_5630)) of + Some (stringappend_5640,stringappend_5650) => (stringappend_5640, stringappend_5650) + ) of + (_, stringappend_5650) => + (let stringappend_5660 = (string_drop stringappend_5630 stringappend_5650) in + (let (imm, stringappend_5680) = + ((case ((hex_bits_21_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_5660 :: (( 21 Word.word * ii)) option)) of + Some (stringappend_5670,stringappend_5680) => (stringappend_5670, stringappend_5680) + )) in + if(((string_drop stringappend_5660 stringappend_5680)) = ('''')) then + True else undefined)) + )))) + )) + else if (((((string_startswith stringappend_5410 (''jalr''))) \<and> ((let stringappend_5700 = (string_drop stringappend_5410 ((string_length (''jalr'')))) in + if ((case ((spc_matches_prefix stringappend_5700)) of + Some (stringappend_5710,stringappend_5720) => + (let stringappend_5730 = (string_drop stringappend_5700 stringappend_5720) in + if ((case ((reg_name_matches_prefix stringappend_5730 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_5740,stringappend_5750) => + (let stringappend_5760 = (string_drop stringappend_5730 stringappend_5750) in + if ((case ((sep_matches_prefix stringappend_5760)) of + Some (stringappend_5770,stringappend_5780) => + (let stringappend_5790 = + (string_drop stringappend_5760 stringappend_5780) in + if ((case ((reg_name_matches_prefix stringappend_5790 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_5800,stringappend_5810) => + (let stringappend_5820 = + (string_drop stringappend_5790 stringappend_5810) in + if ((case ((sep_matches_prefix stringappend_5820)) of + Some (stringappend_5830,stringappend_5840) => + (let stringappend_5850 = + (string_drop stringappend_5820 stringappend_5840) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_5850 + :: (( 12 Word.word * ii))option)) of + Some (stringappend_5860,stringappend_5870) => + if(((string_drop stringappend_5850 stringappend_5870)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_5700 = (string_drop stringappend_5410 ((string_length (''jalr'')))) in + (case + (case ((spc_matches_prefix stringappend_5700)) of + Some (stringappend_5710,stringappend_5720) => (stringappend_5710, stringappend_5720) + ) of + (_, stringappend_5720) => + (let stringappend_5730 = (string_drop stringappend_5700 stringappend_5720) in + (let (rd, stringappend_5750) = + ((case ((reg_name_matches_prefix stringappend_5730 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_5740,stringappend_5750) => (stringappend_5740, stringappend_5750) + )) in + (let stringappend_5760 = (string_drop stringappend_5730 stringappend_5750) in + (case + (case ((sep_matches_prefix stringappend_5760)) of + Some (stringappend_5770,stringappend_5780) => (stringappend_5770, stringappend_5780) + ) of + (_, stringappend_5780) => + (let stringappend_5790 = (string_drop stringappend_5760 stringappend_5780) in + (let (rs1, stringappend_5810) = + ((case ((reg_name_matches_prefix stringappend_5790 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_5800,stringappend_5810) => (stringappend_5800, stringappend_5810) + )) in + (let stringappend_5820 = (string_drop stringappend_5790 stringappend_5810) in + (case + (case ((sep_matches_prefix stringappend_5820)) of + Some (stringappend_5830,stringappend_5840) => (stringappend_5830, stringappend_5840) + ) of + (_, stringappend_5840) => + (let stringappend_5850 = (string_drop stringappend_5820 stringappend_5840) in + (let (imm, stringappend_5870) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_5850 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_5860,stringappend_5870) => (stringappend_5860, stringappend_5870) + )) in + if(((string_drop stringappend_5850 stringappend_5870)) = ('''')) then + True else undefined)) + )))) + )))) + )) + else if ((case ((btype_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_5890,stringappend_5900) => + (let stringappend_5910 = (string_drop stringappend_5410 stringappend_5900) in + if ((case ((spc_matches_prefix stringappend_5910)) of + Some (stringappend_5920,stringappend_5930) => + (let stringappend_5940 = (string_drop stringappend_5910 stringappend_5930) in + if ((case ((reg_name_matches_prefix stringappend_5940 :: (( 5 Word.word * ii))option)) of + Some (stringappend_5950,stringappend_5960) => + (let stringappend_5970 = (string_drop stringappend_5940 stringappend_5960) in + if ((case ((sep_matches_prefix stringappend_5970)) of + Some (stringappend_5980,stringappend_5990) => + (let stringappend_6000 = (string_drop stringappend_5970 stringappend_5990) in + if ((case ((reg_name_matches_prefix stringappend_6000 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_6010,stringappend_6020) => + (let stringappend_6030 = + (string_drop stringappend_6000 stringappend_6020) in + if ((case ((sep_matches_prefix stringappend_6030)) of + Some (stringappend_6040,stringappend_6050) => + (let stringappend_6060 = + (string_drop stringappend_6030 stringappend_6050) in + if ((case ((hex_bits_13_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_6060 + :: (( 13 Word.word * ii))option)) of + Some (stringappend_6070,stringappend_6080) => + if(((string_drop stringappend_6060 stringappend_6080)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_5900) = + ((case ((btype_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_5890,stringappend_5900) => (stringappend_5890, stringappend_5900) + )) in + (let stringappend_5910 = (string_drop stringappend_5410 stringappend_5900) in + (case + (case ((spc_matches_prefix stringappend_5910)) of + Some (stringappend_5920,stringappend_5930) => (stringappend_5920, stringappend_5930) + ) of + (_, stringappend_5930) => + (let stringappend_5940 = (string_drop stringappend_5910 stringappend_5930) in + (let (rs1, stringappend_5960) = + ((case ((reg_name_matches_prefix stringappend_5940 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_5950,stringappend_5960) => (stringappend_5950, stringappend_5960) + )) in + (let stringappend_5970 = (string_drop stringappend_5940 stringappend_5960) in + (case + (case ((sep_matches_prefix stringappend_5970)) of + Some (stringappend_5980,stringappend_5990) => (stringappend_5980, stringappend_5990) + ) of + (_, stringappend_5990) => + (let stringappend_6000 = (string_drop stringappend_5970 stringappend_5990) in + (let (rs2, stringappend_6020) = + ((case ((reg_name_matches_prefix stringappend_6000 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_6010,stringappend_6020) => (stringappend_6010, stringappend_6020) + )) in + (let stringappend_6030 = (string_drop stringappend_6000 stringappend_6020) in + (case + (case ((sep_matches_prefix stringappend_6030)) of + Some (stringappend_6040,stringappend_6050) => (stringappend_6040, stringappend_6050) + ) of + (_, stringappend_6050) => + (let stringappend_6060 = (string_drop stringappend_6030 stringappend_6050) in + (let (imm, stringappend_6080) = + ((case ((hex_bits_13_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_6060 :: (( 13 Word.word * ii)) option)) of + Some (stringappend_6070,stringappend_6080) => (stringappend_6070, stringappend_6080) + )) in + if(((string_drop stringappend_6060 stringappend_6080)) = ('''')) then + True else undefined)) + )))) + )))) + ))) + else if ((case ((itype_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_6100,stringappend_6110) => + (let stringappend_6120 = (string_drop stringappend_5410 stringappend_6110) in + if ((case ((spc_matches_prefix stringappend_6120)) of + Some (stringappend_6130,stringappend_6140) => + (let stringappend_6150 = (string_drop stringappend_6120 stringappend_6140) in + if ((case ((reg_name_matches_prefix stringappend_6150 :: (( 5 Word.word * ii))option)) of + Some (stringappend_6160,stringappend_6170) => + (let stringappend_6180 = (string_drop stringappend_6150 stringappend_6170) in + if ((case ((sep_matches_prefix stringappend_6180)) of + Some (stringappend_6190,stringappend_6200) => + (let stringappend_6210 = (string_drop stringappend_6180 stringappend_6200) in + if ((case ((reg_name_matches_prefix stringappend_6210 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_6220,stringappend_6230) => + (let stringappend_6240 = + (string_drop stringappend_6210 stringappend_6230) in + if ((case ((sep_matches_prefix stringappend_6240)) of + Some (stringappend_6250,stringappend_6260) => + (let stringappend_6270 = + (string_drop stringappend_6240 stringappend_6260) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_6270 + :: (( 12 Word.word * ii))option)) of + Some (stringappend_6280,stringappend_6290) => + if(((string_drop stringappend_6270 stringappend_6290)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_6110) = + ((case ((itype_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_6100,stringappend_6110) => (stringappend_6100, stringappend_6110) + )) in + (let stringappend_6120 = (string_drop stringappend_5410 stringappend_6110) in + (case + (case ((spc_matches_prefix stringappend_6120)) of + Some (stringappend_6130,stringappend_6140) => (stringappend_6130, stringappend_6140) + ) of + (_, stringappend_6140) => + (let stringappend_6150 = (string_drop stringappend_6120 stringappend_6140) in + (let (rd, stringappend_6170) = + ((case ((reg_name_matches_prefix stringappend_6150 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_6160,stringappend_6170) => (stringappend_6160, stringappend_6170) + )) in + (let stringappend_6180 = (string_drop stringappend_6150 stringappend_6170) in + (case + (case ((sep_matches_prefix stringappend_6180)) of + Some (stringappend_6190,stringappend_6200) => (stringappend_6190, stringappend_6200) + ) of + (_, stringappend_6200) => + (let stringappend_6210 = (string_drop stringappend_6180 stringappend_6200) in + (let (rs1, stringappend_6230) = + ((case ((reg_name_matches_prefix stringappend_6210 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_6220,stringappend_6230) => (stringappend_6220, stringappend_6230) + )) in + (let stringappend_6240 = (string_drop stringappend_6210 stringappend_6230) in + (case + (case ((sep_matches_prefix stringappend_6240)) of + Some (stringappend_6250,stringappend_6260) => (stringappend_6250, stringappend_6260) + ) of + (_, stringappend_6260) => + (let stringappend_6270 = (string_drop stringappend_6240 stringappend_6260) in + (let (imm, stringappend_6290) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_6270 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_6280,stringappend_6290) => (stringappend_6280, stringappend_6290) + )) in + if(((string_drop stringappend_6270 stringappend_6290)) = ('''')) then + True else undefined)) + )))) + )))) + ))) + else if ((case ((shiftiop_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_6310,stringappend_6320) => + (let stringappend_6330 = (string_drop stringappend_5410 stringappend_6320) in + if ((case ((spc_matches_prefix stringappend_6330)) of + Some (stringappend_6340,stringappend_6350) => + (let stringappend_6360 = (string_drop stringappend_6330 stringappend_6350) in + if ((case ((reg_name_matches_prefix stringappend_6360 :: (( 5 Word.word * ii))option)) of + Some (stringappend_6370,stringappend_6380) => + (let stringappend_6390 = (string_drop stringappend_6360 stringappend_6380) in + if ((case ((sep_matches_prefix stringappend_6390)) of + Some (stringappend_6400,stringappend_6410) => + (let stringappend_6420 = (string_drop stringappend_6390 stringappend_6410) in + if ((case ((reg_name_matches_prefix stringappend_6420 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_6430,stringappend_6440) => + (let stringappend_6450 = + (string_drop stringappend_6420 stringappend_6440) in + if ((case ((hex_bits_6_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_6450 + :: (( 6 Word.word * ii))option)) of + Some (stringappend_6460,stringappend_6470) => + if(((string_drop stringappend_6450 stringappend_6470)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_6320) = + ((case ((shiftiop_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_6310,stringappend_6320) => (stringappend_6310, stringappend_6320) + )) in + (let stringappend_6330 = (string_drop stringappend_5410 stringappend_6320) in + (case + (case ((spc_matches_prefix stringappend_6330)) of + Some (stringappend_6340,stringappend_6350) => (stringappend_6340, stringappend_6350) + ) of + (_, stringappend_6350) => + (let stringappend_6360 = (string_drop stringappend_6330 stringappend_6350) in + (let (rd, stringappend_6380) = + ((case ((reg_name_matches_prefix stringappend_6360 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_6370,stringappend_6380) => (stringappend_6370, stringappend_6380) + )) in + (let stringappend_6390 = (string_drop stringappend_6360 stringappend_6380) in + (case + (case ((sep_matches_prefix stringappend_6390)) of + Some (stringappend_6400,stringappend_6410) => (stringappend_6400, stringappend_6410) + ) of + (_, stringappend_6410) => + (let stringappend_6420 = (string_drop stringappend_6390 stringappend_6410) in + (let (rs1, stringappend_6440) = + ((case ((reg_name_matches_prefix stringappend_6420 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_6430,stringappend_6440) => (stringappend_6430, stringappend_6440) + )) in + (let stringappend_6450 = (string_drop stringappend_6420 stringappend_6440) in + (let (shamt, stringappend_6470) = + ((case ((hex_bits_6_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_6450 :: (( 6 Word.word * ii)) option)) of + Some (stringappend_6460,stringappend_6470) => (stringappend_6460, stringappend_6470) + )) in + if(((string_drop stringappend_6450 stringappend_6470)) = ('''')) then + True else undefined)))) + )))) + ))) + else if ((case ((rtype_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_6490,stringappend_6500) => + (let stringappend_6510 = (string_drop stringappend_5410 stringappend_6500) in + if ((case ((spc_matches_prefix stringappend_6510)) of + Some (stringappend_6520,stringappend_6530) => + (let stringappend_6540 = (string_drop stringappend_6510 stringappend_6530) in + if ((case ((reg_name_matches_prefix stringappend_6540 :: (( 5 Word.word * ii))option)) of + Some (stringappend_6550,stringappend_6560) => + (let stringappend_6570 = (string_drop stringappend_6540 stringappend_6560) in + if ((case ((sep_matches_prefix stringappend_6570)) of + Some (stringappend_6580,stringappend_6590) => + (let stringappend_6600 = (string_drop stringappend_6570 stringappend_6590) in + if ((case ((reg_name_matches_prefix stringappend_6600 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_6610,stringappend_6620) => + (let stringappend_6630 = + (string_drop stringappend_6600 stringappend_6620) in + if ((case ((sep_matches_prefix stringappend_6630)) of + Some (stringappend_6640,stringappend_6650) => + (let stringappend_6660 = + (string_drop stringappend_6630 stringappend_6650) in + if ((case ((reg_name_matches_prefix stringappend_6660 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_6670,stringappend_6680) => + if(((string_drop stringappend_6660 stringappend_6680)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_6500) = + ((case ((rtype_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_6490,stringappend_6500) => (stringappend_6490, stringappend_6500) + )) in + (let stringappend_6510 = (string_drop stringappend_5410 stringappend_6500) in + (case + (case ((spc_matches_prefix stringappend_6510)) of + Some (stringappend_6520,stringappend_6530) => (stringappend_6520, stringappend_6530) + ) of + (_, stringappend_6530) => + (let stringappend_6540 = (string_drop stringappend_6510 stringappend_6530) in + (let (rd, stringappend_6560) = + ((case ((reg_name_matches_prefix stringappend_6540 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_6550,stringappend_6560) => (stringappend_6550, stringappend_6560) + )) in + (let stringappend_6570 = (string_drop stringappend_6540 stringappend_6560) in + (case + (case ((sep_matches_prefix stringappend_6570)) of + Some (stringappend_6580,stringappend_6590) => (stringappend_6580, stringappend_6590) + ) of + (_, stringappend_6590) => + (let stringappend_6600 = (string_drop stringappend_6570 stringappend_6590) in + (let (rs1, stringappend_6620) = + ((case ((reg_name_matches_prefix stringappend_6600 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_6610,stringappend_6620) => (stringappend_6610, stringappend_6620) + )) in + (let stringappend_6630 = (string_drop stringappend_6600 stringappend_6620) in + (case + (case ((sep_matches_prefix stringappend_6630)) of + Some (stringappend_6640,stringappend_6650) => (stringappend_6640, stringappend_6650) + ) of + (_, stringappend_6650) => + (let stringappend_6660 = (string_drop stringappend_6630 stringappend_6650) in + (let (rs2, stringappend_6680) = + ((case ((reg_name_matches_prefix stringappend_6660 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_6670,stringappend_6680) => (stringappend_6670, stringappend_6680) + )) in + if(((string_drop stringappend_6660 stringappend_6680)) = ('''')) then + True else undefined)) + )))) + )))) + ))) + else if (((((string_startswith stringappend_5410 (''l''))) \<and> ((let stringappend_6700 = (string_drop stringappend_5410 ((string_length (''l'')))) in + if ((case ((size_mnemonic_matches_prefix stringappend_6700)) of + Some (stringappend_6710,stringappend_6720) => + (let stringappend_6730 = (string_drop stringappend_6700 stringappend_6720) in + if ((case ((maybe_u_matches_prefix stringappend_6730)) of + Some (stringappend_6740,stringappend_6750) => + (let stringappend_6760 = (string_drop stringappend_6730 stringappend_6750) in + if ((case ((maybe_aq_matches_prefix stringappend_6760)) of + Some (stringappend_6770,stringappend_6780) => + (let stringappend_6790 = + (string_drop stringappend_6760 stringappend_6780) in + if ((case ((maybe_rl_matches_prefix stringappend_6790)) of + Some (stringappend_6800,stringappend_6810) => + (let stringappend_6820 = + (string_drop stringappend_6790 stringappend_6810) in + if ((case ((spc_matches_prefix stringappend_6820)) of + Some (stringappend_6830,stringappend_6840) => + (let stringappend_6850 = + (string_drop stringappend_6820 stringappend_6840) in + if ((case ((reg_name_matches_prefix stringappend_6850 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_6860,stringappend_6870) => + (let stringappend_6880 = + (string_drop stringappend_6850 stringappend_6870) in + if ((case ((sep_matches_prefix stringappend_6880)) of + Some (stringappend_6890,stringappend_6900) => + (let stringappend_6910 = + (string_drop stringappend_6880 + stringappend_6900) in + if ((case ((reg_name_matches_prefix + stringappend_6910 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_6920,stringappend_6930) => + (let stringappend_6940 = + (string_drop stringappend_6910 + stringappend_6930) in + if ((case ((sep_matches_prefix + stringappend_6940)) of + Some + (stringappend_6950,stringappend_6960) => + (let stringappend_6970 = + (string_drop stringappend_6940 + stringappend_6960) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_6970 + :: (( 12 Word.word * ii))option)) of + Some + (stringappend_6980,stringappend_6990) => + if(((string_drop stringappend_6970 stringappend_6990)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_6700 = (string_drop stringappend_5410 ((string_length (''l'')))) in + (let (size1, stringappend_6720) = + ((case ((size_mnemonic_matches_prefix stringappend_6700)) of + Some (stringappend_6710,stringappend_6720) => (stringappend_6710, stringappend_6720) + )) in + (let stringappend_6730 = (string_drop stringappend_6700 stringappend_6720) in + (let (is_unsigned, stringappend_6750) = + ((case ((maybe_u_matches_prefix stringappend_6730)) of + Some (stringappend_6740,stringappend_6750) => (stringappend_6740, stringappend_6750) + )) in + (let stringappend_6760 = (string_drop stringappend_6730 stringappend_6750) in + (let (aq, stringappend_6780) = + ((case ((maybe_aq_matches_prefix stringappend_6760)) of + Some (stringappend_6770,stringappend_6780) => (stringappend_6770, stringappend_6780) + )) in + (let stringappend_6790 = (string_drop stringappend_6760 stringappend_6780) in + (let (rl, stringappend_6810) = + ((case ((maybe_rl_matches_prefix stringappend_6790)) of + Some (stringappend_6800,stringappend_6810) => (stringappend_6800, stringappend_6810) + )) in + (let stringappend_6820 = (string_drop stringappend_6790 stringappend_6810) in + (case + (case ((spc_matches_prefix stringappend_6820)) of + Some (stringappend_6830,stringappend_6840) => (stringappend_6830, stringappend_6840) + ) of + (_, stringappend_6840) => + (let stringappend_6850 = (string_drop stringappend_6820 stringappend_6840) in + (let (rd, stringappend_6870) = + ((case ((reg_name_matches_prefix stringappend_6850 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_6860,stringappend_6870) => (stringappend_6860, stringappend_6870) + )) in + (let stringappend_6880 = (string_drop stringappend_6850 stringappend_6870) in + (case + (case ((sep_matches_prefix stringappend_6880)) of + Some (stringappend_6890,stringappend_6900) => (stringappend_6890, stringappend_6900) + ) of + (_, stringappend_6900) => + (let stringappend_6910 = (string_drop stringappend_6880 stringappend_6900) in + (let (rs1, stringappend_6930) = + ((case ((reg_name_matches_prefix stringappend_6910 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_6920,stringappend_6930) => (stringappend_6920, stringappend_6930) + )) in + (let stringappend_6940 = (string_drop stringappend_6910 stringappend_6930) in + (case + (case ((sep_matches_prefix stringappend_6940)) of + Some (stringappend_6950,stringappend_6960) => (stringappend_6950, stringappend_6960) + ) of + (_, stringappend_6960) => + (let stringappend_6970 = (string_drop stringappend_6940 stringappend_6960) in + (let (imm, stringappend_6990) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_6970 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_6980,stringappend_6990) => (stringappend_6980, stringappend_6990) + )) in + if(((string_drop stringappend_6970 stringappend_6990)) = ('''')) then + True else undefined)) + )))) + )))) + )))))))))) + else if (((((string_startswith stringappend_5410 (''s''))) \<and> ((let stringappend_7010 = (string_drop stringappend_5410 ((string_length (''s'')))) in + if ((case ((size_mnemonic_matches_prefix stringappend_7010)) of + Some (stringappend_7020,stringappend_7030) => + (let stringappend_7040 = (string_drop stringappend_7010 stringappend_7030) in + if ((case ((maybe_aq_matches_prefix stringappend_7040)) of + Some (stringappend_7050,stringappend_7060) => + (let stringappend_7070 = (string_drop stringappend_7040 stringappend_7060) in + if ((case ((maybe_rl_matches_prefix stringappend_7070)) of + Some (stringappend_7080,stringappend_7090) => + (let stringappend_7100 = + (string_drop stringappend_7070 stringappend_7090) in + if ((case ((spc_matches_prefix stringappend_7100)) of + Some (stringappend_7110,stringappend_7120) => + (let stringappend_7130 = + (string_drop stringappend_7100 stringappend_7120) in + if ((case ((reg_name_matches_prefix stringappend_7130 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_7140,stringappend_7150) => + (let stringappend_7160 = + (string_drop stringappend_7130 stringappend_7150) in + if ((case ((sep_matches_prefix stringappend_7160)) of + Some (stringappend_7170,stringappend_7180) => + (let stringappend_7190 = + (string_drop stringappend_7160 stringappend_7180) in + if ((case ((reg_name_matches_prefix stringappend_7190 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_7200,stringappend_7210) => + (let stringappend_7220 = + (string_drop stringappend_7190 + stringappend_7210) in + if ((case ((sep_matches_prefix stringappend_7220)) of + Some (stringappend_7230,stringappend_7240) => + (let stringappend_7250 = + (string_drop stringappend_7220 + stringappend_7240) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_7250 + :: (( 12 Word.word * ii))option)) of + Some + (stringappend_7260,stringappend_7270) => + if(((string_drop stringappend_7250 stringappend_7270)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_7010 = (string_drop stringappend_5410 ((string_length (''s'')))) in + (let (size1, stringappend_7030) = + ((case ((size_mnemonic_matches_prefix stringappend_7010)) of + Some (stringappend_7020,stringappend_7030) => (stringappend_7020, stringappend_7030) + )) in + (let stringappend_7040 = (string_drop stringappend_7010 stringappend_7030) in + (let (aq, stringappend_7060) = + ((case ((maybe_aq_matches_prefix stringappend_7040)) of + Some (stringappend_7050,stringappend_7060) => (stringappend_7050, stringappend_7060) + )) in + (let stringappend_7070 = (string_drop stringappend_7040 stringappend_7060) in + (let (rl, stringappend_7090) = + ((case ((maybe_rl_matches_prefix stringappend_7070)) of + Some (stringappend_7080,stringappend_7090) => (stringappend_7080, stringappend_7090) + )) in + (let stringappend_7100 = (string_drop stringappend_7070 stringappend_7090) in + (case + (case ((spc_matches_prefix stringappend_7100)) of + Some (stringappend_7110,stringappend_7120) => (stringappend_7110, stringappend_7120) + ) of + (_, stringappend_7120) => + (let stringappend_7130 = (string_drop stringappend_7100 stringappend_7120) in + (let (rd, stringappend_7150) = + ((case ((reg_name_matches_prefix stringappend_7130 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_7140,stringappend_7150) => (stringappend_7140, stringappend_7150) + )) in + (let stringappend_7160 = (string_drop stringappend_7130 stringappend_7150) in + (case + (case ((sep_matches_prefix stringappend_7160)) of + Some (stringappend_7170,stringappend_7180) => (stringappend_7170, stringappend_7180) + ) of + (_, stringappend_7180) => + (let stringappend_7190 = (string_drop stringappend_7160 stringappend_7180) in + (let (rs1, stringappend_7210) = + ((case ((reg_name_matches_prefix stringappend_7190 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_7200,stringappend_7210) => (stringappend_7200, stringappend_7210) + )) in + (let stringappend_7220 = (string_drop stringappend_7190 stringappend_7210) in + (case + (case ((sep_matches_prefix stringappend_7220)) of + Some (stringappend_7230,stringappend_7240) => (stringappend_7230, stringappend_7240) + ) of + (_, stringappend_7240) => + (let stringappend_7250 = (string_drop stringappend_7220 stringappend_7240) in + (let (imm, stringappend_7270) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_7250 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_7260,stringappend_7270) => (stringappend_7260, stringappend_7270) + )) in + if(((string_drop stringappend_7250 stringappend_7270)) = ('''')) then + True else undefined)) + )))) + )))) + )))))))) + else if (((((string_startswith stringappend_5410 (''addiw''))) \<and> ((let stringappend_7290 = (string_drop stringappend_5410 ((string_length (''addiw'')))) in + if ((case ((spc_matches_prefix stringappend_7290)) of + Some (stringappend_7300,stringappend_7310) => + (let stringappend_7320 = (string_drop stringappend_7290 stringappend_7310) in + if ((case ((reg_name_matches_prefix stringappend_7320 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_7330,stringappend_7340) => + (let stringappend_7350 = (string_drop stringappend_7320 stringappend_7340) in + if ((case ((sep_matches_prefix stringappend_7350)) of + Some (stringappend_7360,stringappend_7370) => + (let stringappend_7380 = + (string_drop stringappend_7350 stringappend_7370) in + if ((case ((reg_name_matches_prefix stringappend_7380 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_7390,stringappend_7400) => + (let stringappend_7410 = + (string_drop stringappend_7380 stringappend_7400) in + if ((case ((sep_matches_prefix stringappend_7410)) of + Some (stringappend_7420,stringappend_7430) => + (let stringappend_7440 = + (string_drop stringappend_7410 stringappend_7430) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_7440 + :: (( 12 Word.word * ii))option)) of + Some (stringappend_7450,stringappend_7460) => + if(((string_drop stringappend_7440 stringappend_7460)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_7290 = (string_drop stringappend_5410 ((string_length (''addiw'')))) in + (case + (case ((spc_matches_prefix stringappend_7290)) of + Some (stringappend_7300,stringappend_7310) => (stringappend_7300, stringappend_7310) + ) of + (_, stringappend_7310) => + (let stringappend_7320 = (string_drop stringappend_7290 stringappend_7310) in + (let (rd, stringappend_7340) = + ((case ((reg_name_matches_prefix stringappend_7320 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_7330,stringappend_7340) => (stringappend_7330, stringappend_7340) + )) in + (let stringappend_7350 = (string_drop stringappend_7320 stringappend_7340) in + (case + (case ((sep_matches_prefix stringappend_7350)) of + Some (stringappend_7360,stringappend_7370) => (stringappend_7360, stringappend_7370) + ) of + (_, stringappend_7370) => + (let stringappend_7380 = (string_drop stringappend_7350 stringappend_7370) in + (let (rs1, stringappend_7400) = + ((case ((reg_name_matches_prefix stringappend_7380 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_7390,stringappend_7400) => (stringappend_7390, stringappend_7400) + )) in + (let stringappend_7410 = (string_drop stringappend_7380 stringappend_7400) in + (case + (case ((sep_matches_prefix stringappend_7410)) of + Some (stringappend_7420,stringappend_7430) => (stringappend_7420, stringappend_7430) + ) of + (_, stringappend_7430) => + (let stringappend_7440 = (string_drop stringappend_7410 stringappend_7430) in + (let (imm, stringappend_7460) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_7440 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_7450,stringappend_7460) => (stringappend_7450, stringappend_7460) + )) in + if(((string_drop stringappend_7440 stringappend_7460)) = ('''')) then + True else undefined)) + )))) + )))) + )) + else if ((case ((shiftw_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_7480,stringappend_7490) => + (let stringappend_7500 = (string_drop stringappend_5410 stringappend_7490) in + if ((case ((spc_matches_prefix stringappend_7500)) of + Some (stringappend_7510,stringappend_7520) => + (let stringappend_7530 = (string_drop stringappend_7500 stringappend_7520) in + if ((case ((reg_name_matches_prefix stringappend_7530 :: (( 5 Word.word * ii))option)) of + Some (stringappend_7540,stringappend_7550) => + (let stringappend_7560 = (string_drop stringappend_7530 stringappend_7550) in + if ((case ((sep_matches_prefix stringappend_7560)) of + Some (stringappend_7570,stringappend_7580) => + (let stringappend_7590 = (string_drop stringappend_7560 stringappend_7580) in + if ((case ((reg_name_matches_prefix stringappend_7590 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_7600,stringappend_7610) => + (let stringappend_7620 = + (string_drop stringappend_7590 stringappend_7610) in + if ((case ((sep_matches_prefix stringappend_7620)) of + Some (stringappend_7630,stringappend_7640) => + (let stringappend_7650 = + (string_drop stringappend_7620 stringappend_7640) in + if ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_7650 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_7660,stringappend_7670) => + if(((string_drop stringappend_7650 stringappend_7670)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_7490) = + ((case ((shiftw_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_7480,stringappend_7490) => (stringappend_7480, stringappend_7490) + )) in + (let stringappend_7500 = (string_drop stringappend_5410 stringappend_7490) in + (case + (case ((spc_matches_prefix stringappend_7500)) of + Some (stringappend_7510,stringappend_7520) => (stringappend_7510, stringappend_7520) + ) of + (_, stringappend_7520) => + (let stringappend_7530 = (string_drop stringappend_7500 stringappend_7520) in + (let (rd, stringappend_7550) = + ((case ((reg_name_matches_prefix stringappend_7530 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_7540,stringappend_7550) => (stringappend_7540, stringappend_7550) + )) in + (let stringappend_7560 = (string_drop stringappend_7530 stringappend_7550) in + (case + (case ((sep_matches_prefix stringappend_7560)) of + Some (stringappend_7570,stringappend_7580) => (stringappend_7570, stringappend_7580) + ) of + (_, stringappend_7580) => + (let stringappend_7590 = (string_drop stringappend_7560 stringappend_7580) in + (let (rs1, stringappend_7610) = + ((case ((reg_name_matches_prefix stringappend_7590 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_7600,stringappend_7610) => (stringappend_7600, stringappend_7610) + )) in + (let stringappend_7620 = (string_drop stringappend_7590 stringappend_7610) in + (case + (case ((sep_matches_prefix stringappend_7620)) of + Some (stringappend_7630,stringappend_7640) => (stringappend_7630, stringappend_7640) + ) of + (_, stringappend_7640) => + (let stringappend_7650 = (string_drop stringappend_7620 stringappend_7640) in + (let (shamt, stringappend_7670) = + ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_7650 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_7660,stringappend_7670) => (stringappend_7660, stringappend_7670) + )) in + if(((string_drop stringappend_7650 stringappend_7670)) = ('''')) then + True else undefined)) + )))) + )))) + ))) + else if ((case ((rtypew_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_7690,stringappend_7700) => + (let stringappend_7710 = (string_drop stringappend_5410 stringappend_7700) in + if ((case ((spc_matches_prefix stringappend_7710)) of + Some (stringappend_7720,stringappend_7730) => + (let stringappend_7740 = (string_drop stringappend_7710 stringappend_7730) in + if ((case ((reg_name_matches_prefix stringappend_7740 :: (( 5 Word.word * ii))option)) of + Some (stringappend_7750,stringappend_7760) => + (let stringappend_7770 = (string_drop stringappend_7740 stringappend_7760) in + if ((case ((sep_matches_prefix stringappend_7770)) of + Some (stringappend_7780,stringappend_7790) => + (let stringappend_7800 = (string_drop stringappend_7770 stringappend_7790) in + if ((case ((reg_name_matches_prefix stringappend_7800 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_7810,stringappend_7820) => + (let stringappend_7830 = + (string_drop stringappend_7800 stringappend_7820) in + if ((case ((sep_matches_prefix stringappend_7830)) of + Some (stringappend_7840,stringappend_7850) => + (let stringappend_7860 = + (string_drop stringappend_7830 stringappend_7850) in + if ((case ((reg_name_matches_prefix stringappend_7860 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_7870,stringappend_7880) => + if(((string_drop stringappend_7860 stringappend_7880)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_7700) = + ((case ((rtypew_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_7690,stringappend_7700) => (stringappend_7690, stringappend_7700) + )) in + (let stringappend_7710 = (string_drop stringappend_5410 stringappend_7700) in + (case + (case ((spc_matches_prefix stringappend_7710)) of + Some (stringappend_7720,stringappend_7730) => (stringappend_7720, stringappend_7730) + ) of + (_, stringappend_7730) => + (let stringappend_7740 = (string_drop stringappend_7710 stringappend_7730) in + (let (rd, stringappend_7760) = + ((case ((reg_name_matches_prefix stringappend_7740 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_7750,stringappend_7760) => (stringappend_7750, stringappend_7760) + )) in + (let stringappend_7770 = (string_drop stringappend_7740 stringappend_7760) in + (case + (case ((sep_matches_prefix stringappend_7770)) of + Some (stringappend_7780,stringappend_7790) => (stringappend_7780, stringappend_7790) + ) of + (_, stringappend_7790) => + (let stringappend_7800 = (string_drop stringappend_7770 stringappend_7790) in + (let (rs1, stringappend_7820) = + ((case ((reg_name_matches_prefix stringappend_7800 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_7810,stringappend_7820) => (stringappend_7810, stringappend_7820) + )) in + (let stringappend_7830 = (string_drop stringappend_7800 stringappend_7820) in + (case + (case ((sep_matches_prefix stringappend_7830)) of + Some (stringappend_7840,stringappend_7850) => (stringappend_7840, stringappend_7850) + ) of + (_, stringappend_7850) => + (let stringappend_7860 = (string_drop stringappend_7830 stringappend_7850) in + (let (rs2, stringappend_7880) = + ((case ((reg_name_matches_prefix stringappend_7860 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_7870,stringappend_7880) => (stringappend_7870, stringappend_7880) + )) in + if(((string_drop stringappend_7860 stringappend_7880)) = ('''')) then + True else undefined)) + )))) + )))) + ))) + else if ((case ((mul_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_7900,stringappend_7910) => + (let stringappend_7920 = (string_drop stringappend_5410 stringappend_7910) in + if ((case ((spc_matches_prefix stringappend_7920)) of + Some (stringappend_7930,stringappend_7940) => + (let stringappend_7950 = (string_drop stringappend_7920 stringappend_7940) in + if ((case ((reg_name_matches_prefix stringappend_7950 :: (( 5 Word.word * ii))option)) of + Some (stringappend_7960,stringappend_7970) => + (let stringappend_7980 = (string_drop stringappend_7950 stringappend_7970) in + if ((case ((sep_matches_prefix stringappend_7980)) of + Some (stringappend_7990,stringappend_8000) => + (let stringappend_8010 = (string_drop stringappend_7980 stringappend_8000) in + if ((case ((reg_name_matches_prefix stringappend_8010 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8020,stringappend_8030) => + (let stringappend_8040 = + (string_drop stringappend_8010 stringappend_8030) in + if ((case ((sep_matches_prefix stringappend_8040)) of + Some (stringappend_8050,stringappend_8060) => + (let stringappend_8070 = + (string_drop stringappend_8040 stringappend_8060) in + if ((case ((reg_name_matches_prefix stringappend_8070 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8080,stringappend_8090) => + if(((string_drop stringappend_8070 stringappend_8090)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let ((high, signed1, signed2), stringappend_7910) = + ((case ((mul_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_7900,stringappend_7910) => (stringappend_7900, stringappend_7910) + )) in + (let stringappend_7920 = (string_drop stringappend_5410 stringappend_7910) in + (case + (case ((spc_matches_prefix stringappend_7920)) of + Some (stringappend_7930,stringappend_7940) => (stringappend_7930, stringappend_7940) + ) of + (_, stringappend_7940) => + (let stringappend_7950 = (string_drop stringappend_7920 stringappend_7940) in + (let (rd, stringappend_7970) = + ((case ((reg_name_matches_prefix stringappend_7950 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_7960,stringappend_7970) => (stringappend_7960, stringappend_7970) + )) in + (let stringappend_7980 = (string_drop stringappend_7950 stringappend_7970) in + (case + (case ((sep_matches_prefix stringappend_7980)) of + Some (stringappend_7990,stringappend_8000) => (stringappend_7990, stringappend_8000) + ) of + (_, stringappend_8000) => + (let stringappend_8010 = (string_drop stringappend_7980 stringappend_8000) in + (let (rs1, stringappend_8030) = + ((case ((reg_name_matches_prefix stringappend_8010 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8020,stringappend_8030) => (stringappend_8020, stringappend_8030) + )) in + (let stringappend_8040 = (string_drop stringappend_8010 stringappend_8030) in + (case + (case ((sep_matches_prefix stringappend_8040)) of + Some (stringappend_8050,stringappend_8060) => (stringappend_8050, stringappend_8060) + ) of + (_, stringappend_8060) => + (let stringappend_8070 = (string_drop stringappend_8040 stringappend_8060) in + (let (rs2, stringappend_8090) = + ((case ((reg_name_matches_prefix stringappend_8070 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8080,stringappend_8090) => (stringappend_8080, stringappend_8090) + )) in + if(((string_drop stringappend_8070 stringappend_8090)) = ('''')) then + True else undefined)) + )))) + )))) + ))) + else if (((((string_startswith stringappend_5410 (''div''))) \<and> ((let stringappend_8110 = (string_drop stringappend_5410 ((string_length (''div'')))) in + if ((case ((maybe_not_u_matches_prefix stringappend_8110)) of + Some (stringappend_8120,stringappend_8130) => + (let stringappend_8140 = (string_drop stringappend_8110 stringappend_8130) in + if ((case ((spc_matches_prefix stringappend_8140)) of + Some (stringappend_8150,stringappend_8160) => + (let stringappend_8170 = (string_drop stringappend_8140 stringappend_8160) in + if ((case ((reg_name_matches_prefix stringappend_8170 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8180,stringappend_8190) => + (let stringappend_8200 = + (string_drop stringappend_8170 stringappend_8190) in + if ((case ((sep_matches_prefix stringappend_8200)) of + Some (stringappend_8210,stringappend_8220) => + (let stringappend_8230 = + (string_drop stringappend_8200 stringappend_8220) in + if ((case ((reg_name_matches_prefix stringappend_8230 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8240,stringappend_8250) => + (let stringappend_8260 = + (string_drop stringappend_8230 stringappend_8250) in + if ((case ((sep_matches_prefix stringappend_8260)) of + Some (stringappend_8270,stringappend_8280) => + (let stringappend_8290 = + (string_drop stringappend_8260 stringappend_8280) in + if ((case ((reg_name_matches_prefix stringappend_8290 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8300,stringappend_8310) => + if(((string_drop stringappend_8290 stringappend_8310)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_8110 = (string_drop stringappend_5410 ((string_length (''div'')))) in + (let (s, stringappend_8130) = + ((case ((maybe_not_u_matches_prefix stringappend_8110)) of + Some (stringappend_8120,stringappend_8130) => (stringappend_8120, stringappend_8130) + )) in + (let stringappend_8140 = (string_drop stringappend_8110 stringappend_8130) in + (case + (case ((spc_matches_prefix stringappend_8140)) of + Some (stringappend_8150,stringappend_8160) => (stringappend_8150, stringappend_8160) + ) of + (_, stringappend_8160) => + (let stringappend_8170 = (string_drop stringappend_8140 stringappend_8160) in + (let (rd, stringappend_8190) = + ((case ((reg_name_matches_prefix stringappend_8170 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8180,stringappend_8190) => (stringappend_8180, stringappend_8190) + )) in + (let stringappend_8200 = (string_drop stringappend_8170 stringappend_8190) in + (case + (case ((sep_matches_prefix stringappend_8200)) of + Some (stringappend_8210,stringappend_8220) => (stringappend_8210, stringappend_8220) + ) of + (_, stringappend_8220) => + (let stringappend_8230 = (string_drop stringappend_8200 stringappend_8220) in + (let (rs1, stringappend_8250) = + ((case ((reg_name_matches_prefix stringappend_8230 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8240,stringappend_8250) => (stringappend_8240, stringappend_8250) + )) in + (let stringappend_8260 = (string_drop stringappend_8230 stringappend_8250) in + (case + (case ((sep_matches_prefix stringappend_8260)) of + Some (stringappend_8270,stringappend_8280) => (stringappend_8270, stringappend_8280) + ) of + (_, stringappend_8280) => + (let stringappend_8290 = (string_drop stringappend_8260 stringappend_8280) in + (let (rs2, stringappend_8310) = + ((case ((reg_name_matches_prefix stringappend_8290 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8300,stringappend_8310) => (stringappend_8300, stringappend_8310) + )) in + if(((string_drop stringappend_8290 stringappend_8310)) = ('''')) then + True else undefined)) + )))) + )))) + )))) + else if (((((string_startswith stringappend_5410 (''rem''))) \<and> ((let stringappend_8330 = (string_drop stringappend_5410 ((string_length (''rem'')))) in + if ((case ((maybe_not_u_matches_prefix stringappend_8330)) of + Some (stringappend_8340,stringappend_8350) => + (let stringappend_8360 = (string_drop stringappend_8330 stringappend_8350) in + if ((case ((spc_matches_prefix stringappend_8360)) of + Some (stringappend_8370,stringappend_8380) => + (let stringappend_8390 = (string_drop stringappend_8360 stringappend_8380) in + if ((case ((reg_name_matches_prefix stringappend_8390 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8400,stringappend_8410) => + (let stringappend_8420 = + (string_drop stringappend_8390 stringappend_8410) in + if ((case ((sep_matches_prefix stringappend_8420)) of + Some (stringappend_8430,stringappend_8440) => + (let stringappend_8450 = + (string_drop stringappend_8420 stringappend_8440) in + if ((case ((reg_name_matches_prefix stringappend_8450 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8460,stringappend_8470) => + (let stringappend_8480 = + (string_drop stringappend_8450 stringappend_8470) in + if ((case ((sep_matches_prefix stringappend_8480)) of + Some (stringappend_8490,stringappend_8500) => + (let stringappend_8510 = + (string_drop stringappend_8480 stringappend_8500) in + if ((case ((reg_name_matches_prefix stringappend_8510 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8520,stringappend_8530) => + if(((string_drop stringappend_8510 stringappend_8530)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_8330 = (string_drop stringappend_5410 ((string_length (''rem'')))) in + (let (s, stringappend_8350) = + ((case ((maybe_not_u_matches_prefix stringappend_8330)) of + Some (stringappend_8340,stringappend_8350) => (stringappend_8340, stringappend_8350) + )) in + (let stringappend_8360 = (string_drop stringappend_8330 stringappend_8350) in + (case + (case ((spc_matches_prefix stringappend_8360)) of + Some (stringappend_8370,stringappend_8380) => (stringappend_8370, stringappend_8380) + ) of + (_, stringappend_8380) => + (let stringappend_8390 = (string_drop stringappend_8360 stringappend_8380) in + (let (rd, stringappend_8410) = + ((case ((reg_name_matches_prefix stringappend_8390 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8400,stringappend_8410) => (stringappend_8400, stringappend_8410) + )) in + (let stringappend_8420 = (string_drop stringappend_8390 stringappend_8410) in + (case + (case ((sep_matches_prefix stringappend_8420)) of + Some (stringappend_8430,stringappend_8440) => (stringappend_8430, stringappend_8440) + ) of + (_, stringappend_8440) => + (let stringappend_8450 = (string_drop stringappend_8420 stringappend_8440) in + (let (rs1, stringappend_8470) = + ((case ((reg_name_matches_prefix stringappend_8450 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8460,stringappend_8470) => (stringappend_8460, stringappend_8470) + )) in + (let stringappend_8480 = (string_drop stringappend_8450 stringappend_8470) in + (case + (case ((sep_matches_prefix stringappend_8480)) of + Some (stringappend_8490,stringappend_8500) => (stringappend_8490, stringappend_8500) + ) of + (_, stringappend_8500) => + (let stringappend_8510 = (string_drop stringappend_8480 stringappend_8500) in + (let (rs2, stringappend_8530) = + ((case ((reg_name_matches_prefix stringappend_8510 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8520,stringappend_8530) => (stringappend_8520, stringappend_8530) + )) in + if(((string_drop stringappend_8510 stringappend_8530)) = ('''')) then + True else undefined)) + )))) + )))) + )))) + else if (((((string_startswith stringappend_5410 (''mulw''))) \<and> ((let stringappend_8550 = (string_drop stringappend_5410 ((string_length (''mulw'')))) in + if ((case ((spc_matches_prefix stringappend_8550)) of + Some (stringappend_8560,stringappend_8570) => + (let stringappend_8580 = (string_drop stringappend_8550 stringappend_8570) in + if ((case ((reg_name_matches_prefix stringappend_8580 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8590,stringappend_8600) => + (let stringappend_8610 = (string_drop stringappend_8580 stringappend_8600) in + if ((case ((sep_matches_prefix stringappend_8610)) of + Some (stringappend_8620,stringappend_8630) => + (let stringappend_8640 = + (string_drop stringappend_8610 stringappend_8630) in + if ((case ((reg_name_matches_prefix stringappend_8640 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8650,stringappend_8660) => + (let stringappend_8670 = + (string_drop stringappend_8640 stringappend_8660) in + if ((case ((sep_matches_prefix stringappend_8670)) of + Some (stringappend_8680,stringappend_8690) => + (let stringappend_8700 = + (string_drop stringappend_8670 stringappend_8690) in + if ((case ((reg_name_matches_prefix stringappend_8700 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8710,stringappend_8720) => + if(((string_drop stringappend_8700 stringappend_8720)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_8550 = (string_drop stringappend_5410 ((string_length (''mulw'')))) in + (case + (case ((spc_matches_prefix stringappend_8550)) of + Some (stringappend_8560,stringappend_8570) => (stringappend_8560, stringappend_8570) + ) of + (_, stringappend_8570) => + (let stringappend_8580 = (string_drop stringappend_8550 stringappend_8570) in + (let (rd, stringappend_8600) = + ((case ((reg_name_matches_prefix stringappend_8580 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8590,stringappend_8600) => (stringappend_8590, stringappend_8600) + )) in + (let stringappend_8610 = (string_drop stringappend_8580 stringappend_8600) in + (case + (case ((sep_matches_prefix stringappend_8610)) of + Some (stringappend_8620,stringappend_8630) => (stringappend_8620, stringappend_8630) + ) of + (_, stringappend_8630) => + (let stringappend_8640 = (string_drop stringappend_8610 stringappend_8630) in + (let (rs1, stringappend_8660) = + ((case ((reg_name_matches_prefix stringappend_8640 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8650,stringappend_8660) => (stringappend_8650, stringappend_8660) + )) in + (let stringappend_8670 = (string_drop stringappend_8640 stringappend_8660) in + (case + (case ((sep_matches_prefix stringappend_8670)) of + Some (stringappend_8680,stringappend_8690) => (stringappend_8680, stringappend_8690) + ) of + (_, stringappend_8690) => + (let stringappend_8700 = (string_drop stringappend_8670 stringappend_8690) in + (let (rs2, stringappend_8720) = + ((case ((reg_name_matches_prefix stringappend_8700 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8710,stringappend_8720) => (stringappend_8710, stringappend_8720) + )) in + if(((string_drop stringappend_8700 stringappend_8720)) = ('''')) then + True else undefined)) + )))) + )))) + )) + else if (((((string_startswith stringappend_5410 (''div''))) \<and> ((let stringappend_8740 = (string_drop stringappend_5410 ((string_length (''div'')))) in + if ((case ((maybe_not_u_matches_prefix stringappend_8740)) of + Some (stringappend_8750,stringappend_8760) => + (let stringappend_8770 = (string_drop stringappend_8740 stringappend_8760) in + if (((((string_startswith stringappend_8770 (''w''))) \<and> ((let stringappend_8780 = + (string_drop stringappend_8770 ((string_length (''w'')))) in + if ((case ((spc_matches_prefix stringappend_8780)) of + Some (stringappend_8790,stringappend_8800) => + (let stringappend_8810 = + (string_drop stringappend_8780 stringappend_8800) in + if ((case ((reg_name_matches_prefix stringappend_8810 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8820,stringappend_8830) => + (let stringappend_8840 = + (string_drop stringappend_8810 stringappend_8830) in + if ((case ((sep_matches_prefix stringappend_8840)) of + Some (stringappend_8850,stringappend_8860) => + (let stringappend_8870 = + (string_drop stringappend_8840 stringappend_8860) in + if ((case ((reg_name_matches_prefix stringappend_8870 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8880,stringappend_8890) => + (let stringappend_8900 = + (string_drop stringappend_8870 stringappend_8890) in + if ((case ((sep_matches_prefix stringappend_8900)) of + Some (stringappend_8910,stringappend_8920) => + (let stringappend_8930 = + (string_drop stringappend_8900 + stringappend_8920) in + if ((case ((reg_name_matches_prefix + stringappend_8930 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_8940,stringappend_8950) => + if(((string_drop stringappend_8930 stringappend_8950)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_8740 = (string_drop stringappend_5410 ((string_length (''div'')))) in + (let (s, stringappend_8760) = + ((case ((maybe_not_u_matches_prefix stringappend_8740)) of + Some (stringappend_8750,stringappend_8760) => (stringappend_8750, stringappend_8760) + )) in + (let stringappend_8770 = (string_drop stringappend_8740 stringappend_8760) in + (let stringappend_8780 = (string_drop stringappend_8770 ((string_length (''w'')))) in + (case + (case ((spc_matches_prefix stringappend_8780)) of + Some (stringappend_8790,stringappend_8800) => (stringappend_8790, stringappend_8800) + ) of + (_, stringappend_8800) => + (let stringappend_8810 = (string_drop stringappend_8780 stringappend_8800) in + (let (rd, stringappend_8830) = + ((case ((reg_name_matches_prefix stringappend_8810 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8820,stringappend_8830) => (stringappend_8820, stringappend_8830) + )) in + (let stringappend_8840 = (string_drop stringappend_8810 stringappend_8830) in + (case + (case ((sep_matches_prefix stringappend_8840)) of + Some (stringappend_8850,stringappend_8860) => (stringappend_8850, stringappend_8860) + ) of + (_, stringappend_8860) => + (let stringappend_8870 = (string_drop stringappend_8840 stringappend_8860) in + (let (rs1, stringappend_8890) = + ((case ((reg_name_matches_prefix stringappend_8870 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8880,stringappend_8890) => (stringappend_8880, stringappend_8890) + )) in + (let stringappend_8900 = (string_drop stringappend_8870 stringappend_8890) in + (case + (case ((sep_matches_prefix stringappend_8900)) of + Some (stringappend_8910,stringappend_8920) => (stringappend_8910, stringappend_8920) + ) of + (_, stringappend_8920) => + (let stringappend_8930 = (string_drop stringappend_8900 stringappend_8920) in + (let (rs2, stringappend_8950) = + ((case ((reg_name_matches_prefix stringappend_8930 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_8940,stringappend_8950) => (stringappend_8940, stringappend_8950) + )) in + if(((string_drop stringappend_8930 stringappend_8950)) = ('''')) then + True else undefined)) + )))) + )))) + ))))) + else if (((((string_startswith stringappend_5410 (''rem''))) \<and> ((let stringappend_8970 = (string_drop stringappend_5410 ((string_length (''rem'')))) in + if ((case ((maybe_not_u_matches_prefix stringappend_8970)) of + Some (stringappend_8980,stringappend_8990) => + (let stringappend_9000 = (string_drop stringappend_8970 stringappend_8990) in + if (((((string_startswith stringappend_9000 (''w''))) \<and> ((let stringappend_9010 = + (string_drop stringappend_9000 ((string_length (''w'')))) in + if ((case ((spc_matches_prefix stringappend_9010)) of + Some (stringappend_9020,stringappend_9030) => + (let stringappend_9040 = + (string_drop stringappend_9010 stringappend_9030) in + if ((case ((reg_name_matches_prefix stringappend_9040 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_9050,stringappend_9060) => + (let stringappend_9070 = + (string_drop stringappend_9040 stringappend_9060) in + if ((case ((sep_matches_prefix stringappend_9070)) of + Some (stringappend_9080,stringappend_9090) => + (let stringappend_9100 = + (string_drop stringappend_9070 stringappend_9090) in + if ((case ((reg_name_matches_prefix stringappend_9100 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_9110,stringappend_9120) => + (let stringappend_9130 = + (string_drop stringappend_9100 stringappend_9120) in + if ((case ((sep_matches_prefix stringappend_9130)) of + Some (stringappend_9140,stringappend_9150) => + (let stringappend_9160 = + (string_drop stringappend_9130 + stringappend_9150) in + if ((case ((reg_name_matches_prefix + stringappend_9160 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_9170,stringappend_9180) => + if(((string_drop stringappend_9160 stringappend_9180)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_8970 = (string_drop stringappend_5410 ((string_length (''rem'')))) in + (let (s, stringappend_8990) = + ((case ((maybe_not_u_matches_prefix stringappend_8970)) of + Some (stringappend_8980,stringappend_8990) => (stringappend_8980, stringappend_8990) + )) in + (let stringappend_9000 = (string_drop stringappend_8970 stringappend_8990) in + (let stringappend_9010 = (string_drop stringappend_9000 ((string_length (''w'')))) in + (case + (case ((spc_matches_prefix stringappend_9010)) of + Some (stringappend_9020,stringappend_9030) => (stringappend_9020, stringappend_9030) + ) of + (_, stringappend_9030) => + (let stringappend_9040 = (string_drop stringappend_9010 stringappend_9030) in + (let (rd, stringappend_9060) = + ((case ((reg_name_matches_prefix stringappend_9040 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9050,stringappend_9060) => (stringappend_9050, stringappend_9060) + )) in + (let stringappend_9070 = (string_drop stringappend_9040 stringappend_9060) in + (case + (case ((sep_matches_prefix stringappend_9070)) of + Some (stringappend_9080,stringappend_9090) => (stringappend_9080, stringappend_9090) + ) of + (_, stringappend_9090) => + (let stringappend_9100 = (string_drop stringappend_9070 stringappend_9090) in + (let (rs1, stringappend_9120) = + ((case ((reg_name_matches_prefix stringappend_9100 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9110,stringappend_9120) => (stringappend_9110, stringappend_9120) + )) in + (let stringappend_9130 = (string_drop stringappend_9100 stringappend_9120) in + (case + (case ((sep_matches_prefix stringappend_9130)) of + Some (stringappend_9140,stringappend_9150) => (stringappend_9140, stringappend_9150) + ) of + (_, stringappend_9150) => + (let stringappend_9160 = (string_drop stringappend_9130 stringappend_9150) in + (let (rs2, stringappend_9180) = + ((case ((reg_name_matches_prefix stringappend_9160 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9170,stringappend_9180) => (stringappend_9170, stringappend_9180) + )) in + if(((string_drop stringappend_9160 stringappend_9180)) = ('''')) then + True else undefined)) + )))) + )))) + ))))) + else if (((((string_startswith stringappend_5410 (''fence''))) \<and> ((let stringappend_9200 = (string_drop stringappend_5410 ((string_length (''fence'')))) in + if ((case ((spc_matches_prefix stringappend_9200)) of + Some (stringappend_9210,stringappend_9220) => + (let stringappend_9230 = (string_drop stringappend_9200 stringappend_9220) in + if ((case ((fence_bits_matches_prefix stringappend_9230 + :: (( 4 Word.word * ii))option)) of + Some (stringappend_9240,stringappend_9250) => + (let stringappend_9260 = (string_drop stringappend_9230 stringappend_9250) in + if ((case ((sep_matches_prefix stringappend_9260)) of + Some (stringappend_9270,stringappend_9280) => + (let stringappend_9290 = + (string_drop stringappend_9260 stringappend_9280) in + if ((case ((fence_bits_matches_prefix stringappend_9290 + :: (( 4 Word.word * ii))option)) of + Some (stringappend_9300,stringappend_9310) => + if(((string_drop stringappend_9290 stringappend_9310)) = ('''')) then + True else False + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_9200 = (string_drop stringappend_5410 ((string_length (''fence'')))) in + (case + (case ((spc_matches_prefix stringappend_9200)) of + Some (stringappend_9210,stringappend_9220) => (stringappend_9210, stringappend_9220) + ) of + (_, stringappend_9220) => + (let stringappend_9230 = (string_drop stringappend_9200 stringappend_9220) in + (let (pred, stringappend_9250) = + ((case ((fence_bits_matches_prefix stringappend_9230 :: (( 4 Word.word * ii)) option)) of + Some (stringappend_9240,stringappend_9250) => (stringappend_9240, stringappend_9250) + )) in + (let stringappend_9260 = (string_drop stringappend_9230 stringappend_9250) in + (case + (case ((sep_matches_prefix stringappend_9260)) of + Some (stringappend_9270,stringappend_9280) => (stringappend_9270, stringappend_9280) + ) of + (_, stringappend_9280) => + (let stringappend_9290 = (string_drop stringappend_9260 stringappend_9280) in + (let (succ, stringappend_9310) = + ((case ((fence_bits_matches_prefix stringappend_9290 :: (( 4 Word.word * ii)) option)) of + Some (stringappend_9300,stringappend_9310) => (stringappend_9300, stringappend_9310) + )) in + if(((string_drop stringappend_9290 stringappend_9310)) = ('''')) then + True else undefined)) + )))) + )) + else if(stringappend_5410 = (''fence.i'')) then True else + ( + if(stringappend_5410 = (''ecall'')) then True else + ( + if(stringappend_5410 = (''mret'')) then True else + ( + if(stringappend_5410 = (''sret'')) then True else + ( + if(stringappend_5410 = (''ebreak'')) then True else + ( + if(stringappend_5410 = (''wfi'')) then True else + ( + if (((((string_startswith stringappend_5410 (''sfence.vma''))) + \<and> + ((let stringappend_9330 = + (string_drop stringappend_5410 + ((string_length (''sfence.vma'')))) in + if ((case ((spc_matches_prefix stringappend_9330)) of + Some (stringappend_9340,stringappend_9350) => + (let stringappend_9360 = (string_drop + stringappend_9330 + stringappend_9350) in + if ((case ((reg_name_matches_prefix + stringappend_9360 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9370,stringappend_9380) => + (let stringappend_9390 = (string_drop + stringappend_9360 + stringappend_9380) in + if ((case ((sep_matches_prefix + stringappend_9390)) of + Some (stringappend_9400,stringappend_9410) => + (let stringappend_9420 = + (string_drop stringappend_9390 + stringappend_9410) in + if ((case ((reg_name_matches_prefix + stringappend_9420 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9430,stringappend_9440) => + if(((string_drop stringappend_9420 + stringappend_9440)) = ('''')) then + True else False + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False))))) then + (let stringappend_9330 = (string_drop stringappend_5410 + ((string_length (''sfence.vma'')))) in + (case + (case ((spc_matches_prefix stringappend_9330)) of + Some (stringappend_9340,stringappend_9350) => + (stringappend_9340, stringappend_9350) + ) of + (_, stringappend_9350) => + (let stringappend_9360 = (string_drop stringappend_9330 + stringappend_9350) in + (let (rs1, stringappend_9380) = + ((case ((reg_name_matches_prefix stringappend_9360 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9370,stringappend_9380) => + (stringappend_9370, stringappend_9380) + )) in + (let stringappend_9390 = (string_drop stringappend_9360 + stringappend_9380) in + (case + (case ((sep_matches_prefix stringappend_9390)) of + Some (stringappend_9400,stringappend_9410) => + (stringappend_9400, stringappend_9410) + ) of + (_, stringappend_9410) => + (let stringappend_9420 = (string_drop stringappend_9390 + stringappend_9410) in + (let (rs2, stringappend_9440) = + ((case ((reg_name_matches_prefix stringappend_9420 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9430,stringappend_9440) => + (stringappend_9430, stringappend_9440) + )) in + if(((string_drop stringappend_9420 stringappend_9440)) = + ('''')) then True else undefined)) + )))) + )) else + if (((((string_startswith stringappend_5410 (''lr.''))) \<and> + ((let stringappend_9460 = (string_drop + stringappend_5410 + ((string_length (''lr.'')))) in + if ((case ((maybe_aq_matches_prefix + stringappend_9460)) of + Some (stringappend_9470,stringappend_9480) => + (let stringappend_9490 = (string_drop + stringappend_9460 + stringappend_9480) in + if ((case ((maybe_rl_matches_prefix + stringappend_9490)) of + Some (stringappend_9500,stringappend_9510) => + (let stringappend_9520 = + (string_drop stringappend_9490 + stringappend_9510) in + if ((case ((size_mnemonic_matches_prefix + stringappend_9520)) of + Some (stringappend_9530,stringappend_9540) => + (let stringappend_9550 = + (string_drop stringappend_9520 + stringappend_9540) in + if ((case ((spc_matches_prefix + stringappend_9550)) of + Some (stringappend_9560,stringappend_9570) => + (let stringappend_9580 = + (string_drop stringappend_9550 + stringappend_9570) in + if ((case ((reg_name_matches_prefix + stringappend_9580 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9590,stringappend_9600) => + (let stringappend_9610 = + (string_drop + stringappend_9580 + stringappend_9600) in + if ((case ((sep_matches_prefix + stringappend_9610)) of + Some (stringappend_9620,stringappend_9630) => + (let stringappend_9640 = + (string_drop + stringappend_9610 + stringappend_9630) in + if ((case ((reg_name_matches_prefix + stringappend_9640 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9650,stringappend_9660) => + if(((string_drop + stringappend_9640 + stringappend_9660)) + = ('''')) then + True else False + | None => False + )) then True else + False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False))))) then + (let stringappend_9460 = (string_drop stringappend_5410 + ((string_length (''lr.'')))) in + (let (aq, stringappend_9480) = + ((case ((maybe_aq_matches_prefix stringappend_9460)) of + Some (stringappend_9470,stringappend_9480) => + (stringappend_9470, stringappend_9480) + )) in + (let stringappend_9490 = (string_drop stringappend_9460 + stringappend_9480) in + (let (rl, stringappend_9510) = + ((case ((maybe_rl_matches_prefix stringappend_9490)) of + Some (stringappend_9500,stringappend_9510) => + (stringappend_9500, stringappend_9510) + )) in + (let stringappend_9520 = (string_drop stringappend_9490 + stringappend_9510) in + (let (size1, stringappend_9540) = + ((case ((size_mnemonic_matches_prefix + stringappend_9520)) of + Some (stringappend_9530,stringappend_9540) => + (stringappend_9530, stringappend_9540) + )) in + (let stringappend_9550 = (string_drop stringappend_9520 + stringappend_9540) in + (case + (case ((spc_matches_prefix stringappend_9550)) of + Some (stringappend_9560,stringappend_9570) => + (stringappend_9560, stringappend_9570) + ) of + (_, stringappend_9570) => + (let stringappend_9580 = (string_drop stringappend_9550 + stringappend_9570) in + (let (rd, stringappend_9600) = + ((case ((reg_name_matches_prefix stringappend_9580 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9590,stringappend_9600) => + (stringappend_9590, stringappend_9600) + )) in + (let stringappend_9610 = (string_drop stringappend_9580 + stringappend_9600) in + (case + (case ((sep_matches_prefix stringappend_9610)) of + Some (stringappend_9620,stringappend_9630) => + (stringappend_9620, stringappend_9630) + ) of + (_, stringappend_9630) => + (let stringappend_9640 = (string_drop stringappend_9610 + stringappend_9630) in + (let (rs1, stringappend_9660) = + ((case ((reg_name_matches_prefix stringappend_9640 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9650,stringappend_9660) => + (stringappend_9650, stringappend_9660) + )) in + if(((string_drop stringappend_9640 stringappend_9660)) = + ('''')) then True else undefined)) + )))) + )))))))) else + if (((((string_startswith stringappend_5410 (''sc.''))) + \<and> + ((let stringappend_9680 = (string_drop + stringappend_5410 + ((string_length + (''sc.'')))) in + if ((case ((maybe_aq_matches_prefix + stringappend_9680)) of + Some (stringappend_9690,stringappend_9700) => + (let stringappend_9710 = (string_drop + stringappend_9680 + stringappend_9700) in + if ((case ((maybe_rl_matches_prefix + stringappend_9710)) of + Some (stringappend_9720,stringappend_9730) => + (let stringappend_9740 = + (string_drop stringappend_9710 + stringappend_9730) in + if ((case ((size_mnemonic_matches_prefix + stringappend_9740)) of + Some (stringappend_9750,stringappend_9760) => + (let stringappend_9770 = + (string_drop stringappend_9740 + stringappend_9760) in + if ((case ((spc_matches_prefix + stringappend_9770)) of + Some (stringappend_9780,stringappend_9790) => + (let stringappend_9800 = + (string_drop stringappend_9770 + stringappend_9790) in + if ((case ((reg_name_matches_prefix + stringappend_9800 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9810,stringappend_9820) => + (let stringappend_9830 = + (string_drop + stringappend_9800 + stringappend_9820) in + if ((case ((sep_matches_prefix + stringappend_9830)) of + Some (stringappend_9840,stringappend_9850) => + (let stringappend_9860 = + (string_drop + stringappend_9830 + stringappend_9850) in + if ((case ((reg_name_matches_prefix + stringappend_9860 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9870,stringappend_9880) => + (let stringappend_9890 = + (string_drop + stringappend_9860 + stringappend_9880) in + if ((case ((sep_matches_prefix + stringappend_9890)) of + Some + (stringappend_9900,stringappend_9910) => + (let stringappend_9920 = + (string_drop + stringappend_9890 + stringappend_9910) in + if ((case + ((reg_name_matches_prefix + stringappend_9920 + :: (( 5 Word.word * ii)) option)) of + Some + (stringappend_9930,stringappend_9940) => + if(((string_drop + stringappend_9920 + stringappend_9940)) + = + ('''')) then + True else + False + | None => + False + )) then + True else False) + | None => + False + )) then True else + False) + | None => False + )) then True else + False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False))))) then + (let stringappend_9680 = (string_drop stringappend_5410 + ((string_length (''sc.'')))) in + (let (aq, stringappend_9700) = + ((case ((maybe_aq_matches_prefix stringappend_9680)) of + Some (stringappend_9690,stringappend_9700) => + (stringappend_9690, stringappend_9700) + )) in + (let stringappend_9710 = (string_drop stringappend_9680 + stringappend_9700) in + (let (rl, stringappend_9730) = + ((case ((maybe_rl_matches_prefix stringappend_9710)) of + Some (stringappend_9720,stringappend_9730) => + (stringappend_9720, stringappend_9730) + )) in + (let stringappend_9740 = (string_drop stringappend_9710 + stringappend_9730) in + (let (size1, stringappend_9760) = + ((case ((size_mnemonic_matches_prefix + stringappend_9740)) of + Some (stringappend_9750,stringappend_9760) => + (stringappend_9750, stringappend_9760) + )) in + (let stringappend_9770 = (string_drop stringappend_9740 + stringappend_9760) in + (case + (case ((spc_matches_prefix stringappend_9770)) of + Some (stringappend_9780,stringappend_9790) => + (stringappend_9780, stringappend_9790) + ) of + (_, stringappend_9790) => + (let stringappend_9800 = (string_drop stringappend_9770 + stringappend_9790) in + (let (rd, stringappend_9820) = + ((case ((reg_name_matches_prefix stringappend_9800 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9810,stringappend_9820) => + (stringappend_9810, stringappend_9820) + )) in + (let stringappend_9830 = (string_drop stringappend_9800 + stringappend_9820) in + (case + (case ((sep_matches_prefix stringappend_9830)) of + Some (stringappend_9840,stringappend_9850) => + (stringappend_9840, stringappend_9850) + ) of + (_, stringappend_9850) => + (let stringappend_9860 = (string_drop stringappend_9830 + stringappend_9850) in + (let (rs1, stringappend_9880) = + ((case ((reg_name_matches_prefix stringappend_9860 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9870,stringappend_9880) => + (stringappend_9870, stringappend_9880) + )) in + (let stringappend_9890 = (string_drop stringappend_9860 + stringappend_9880) in + (case + (case ((sep_matches_prefix stringappend_9890)) of + Some (stringappend_9900,stringappend_9910) => + (stringappend_9900, stringappend_9910) + ) of + (_, stringappend_9910) => + (let stringappend_9920 = (string_drop stringappend_9890 + stringappend_9910) in + (let (rs2, stringappend_9940) = + ((case ((reg_name_matches_prefix stringappend_9920 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_9930,stringappend_9940) => + (stringappend_9930, stringappend_9940) + )) in + if(((string_drop stringappend_9920 stringappend_9940)) = + ('''')) then True else undefined)) + )))) + )))) + )))))))) else + if ((case ((amo_mnemonic_matches_prefix stringappend_5410)) of + Some (stringappend_9960,stringappend_9970) => + (let stringappend_9980 = (string_drop + stringappend_5410 + stringappend_9970) in + if (((((string_startswith stringappend_9980 (''.''))) + \<and> + ((let stringappend_9990 = (string_drop + stringappend_9980 + ((string_length + (''.'')))) in + if ((case ((size_mnemonic_matches_prefix + stringappend_9990)) of + Some (stringappend_10000,stringappend_10010) => + (let stringappend_10020 = + (string_drop stringappend_9990 + stringappend_10010) in + if ((case ((maybe_aq_matches_prefix + stringappend_10020)) of + Some (stringappend_10030,stringappend_10040) => + (let stringappend_10050 = + (string_drop stringappend_10020 + stringappend_10040) in + if ((case ((maybe_rl_matches_prefix + stringappend_10050)) of + Some (stringappend_10060,stringappend_10070) => + (let stringappend_10080 = + (string_drop + stringappend_10050 + stringappend_10070) in + if ((case ((spc_matches_prefix + stringappend_10080)) of + Some (stringappend_10090,stringappend_10100) => + (let stringappend_10110 = + (string_drop + stringappend_10080 + stringappend_10100) in + if ((case ((reg_name_matches_prefix + stringappend_10110 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10120,stringappend_10130) => + (let stringappend_10140 = + (string_drop + stringappend_10110 + stringappend_10130) in + if ((case ((sep_matches_prefix + stringappend_10140)) of + Some (stringappend_10150,stringappend_10160) => + (let stringappend_10170 = + (string_drop + stringappend_10140 + stringappend_10160) in + if ((case (( + reg_name_matches_prefix + stringappend_10170 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10180,stringappend_10190) => + (let stringappend_10200 = + (string_drop + stringappend_10170 + stringappend_10190) in + if ((case + ((sep_matches_prefix + stringappend_10200)) of + Some + (stringappend_10210,stringappend_10220) => + (let + stringappend_10230 = + (string_drop + stringappend_10200 + stringappend_10220) in + if ((case + ( + ( + reg_name_matches_prefix + stringappend_10230 + :: (( 5 Word.word * ii)) option)) of + Some + (stringappend_10240,stringappend_10250) => + if + ( + ( + ( + string_drop + stringappend_10230 + stringappend_10250)) + = + ('''')) then + True else + False + | None => + False + )) then + True else + False) + | None => + False + )) then + True else + False) + | None => + False + )) then True else + False) + | None => False + )) then True else + False) + | None => False + )) then True else + False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False))))) then + True else False) + | None => False + )) then + (let (op1, stringappend_9970) = + ((case ((amo_mnemonic_matches_prefix + stringappend_5410)) of + Some (stringappend_9960,stringappend_9970) => + (stringappend_9960, stringappend_9970) + )) in + (let stringappend_9980 = (string_drop stringappend_5410 + stringappend_9970) in + (let stringappend_9990 = (string_drop stringappend_9980 + ((string_length (''.'')))) in + (let (width, stringappend_10010) = + ((case ((size_mnemonic_matches_prefix + stringappend_9990)) of + Some (stringappend_10000,stringappend_10010) => + (stringappend_10000, stringappend_10010) + )) in + (let stringappend_10020 = (string_drop stringappend_9990 + stringappend_10010) in + (let (aq, stringappend_10040) = + ((case ((maybe_aq_matches_prefix + stringappend_10020)) of + Some (stringappend_10030,stringappend_10040) => + (stringappend_10030, stringappend_10040) + )) in + (let stringappend_10050 = (string_drop + stringappend_10020 + stringappend_10040) in + (let (rl, stringappend_10070) = + ((case ((maybe_rl_matches_prefix + stringappend_10050)) of + Some (stringappend_10060,stringappend_10070) => + (stringappend_10060, stringappend_10070) + )) in + (let stringappend_10080 = (string_drop + stringappend_10050 + stringappend_10070) in + (case + (case ((spc_matches_prefix stringappend_10080)) of + Some (stringappend_10090,stringappend_10100) => + (stringappend_10090, stringappend_10100) + ) of + (_, stringappend_10100) => + (let stringappend_10110 = (string_drop + stringappend_10080 + stringappend_10100) in + (let (rd, stringappend_10130) = + ((case ((reg_name_matches_prefix + stringappend_10110 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10120,stringappend_10130) => + (stringappend_10120, stringappend_10130) + )) in + (let stringappend_10140 = (string_drop + stringappend_10110 + stringappend_10130) in + (case + (case ((sep_matches_prefix stringappend_10140)) of + Some (stringappend_10150,stringappend_10160) => + (stringappend_10150, stringappend_10160) + ) of + (_, stringappend_10160) => + (let stringappend_10170 = (string_drop + stringappend_10140 + stringappend_10160) in + (let (rs1, stringappend_10190) = + ((case ((reg_name_matches_prefix + stringappend_10170 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10180,stringappend_10190) => + (stringappend_10180, stringappend_10190) + )) in + (let stringappend_10200 = (string_drop + stringappend_10170 + stringappend_10190) in + (case + (case ((sep_matches_prefix stringappend_10200)) of + Some (stringappend_10210,stringappend_10220) => + (stringappend_10210, stringappend_10220) + ) of + (_, stringappend_10220) => + (let stringappend_10230 = (string_drop + stringappend_10200 + stringappend_10220) in + (let (rs2, stringappend_10250) = + ((case ((reg_name_matches_prefix + stringappend_10230 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10240,stringappend_10250) => + (stringappend_10240, stringappend_10250) + )) in + if(((string_drop stringappend_10230 stringappend_10250)) + = ('''')) then True else undefined)) + )))) + )))) + )))))))))) else + if ((case ((csr_mnemonic_matches_prefix + stringappend_5410)) of + Some (stringappend_10270,stringappend_10280) => + (let stringappend_10290 = (string_drop + stringappend_5410 + stringappend_10280) in + if (((((string_startswith stringappend_10290 (''i''))) + \<and> + ((let stringappend_10300 = (string_drop + stringappend_10290 + ((string_length + (''i'')))) in + if ((case ((spc_matches_prefix + stringappend_10300)) of + Some (stringappend_10310,stringappend_10320) => + (let stringappend_10330 = + (string_drop stringappend_10300 + stringappend_10320) in + if ((case ((reg_name_matches_prefix + stringappend_10330 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10340,stringappend_10350) => + (let stringappend_10360 = + (string_drop + stringappend_10330 + stringappend_10350) in + if ((case ((sep_matches_prefix + stringappend_10360)) of + Some (stringappend_10370,stringappend_10380) => + (let stringappend_10390 = + (string_drop + stringappend_10360 + stringappend_10380) in + if ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_10390 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10400,stringappend_10410) => + (let stringappend_10420 = + (string_drop + stringappend_10390 + stringappend_10410) in + if ((case ((sep_matches_prefix + stringappend_10420)) of + Some (stringappend_10430,stringappend_10440) => + (let stringappend_10450 = + (string_drop + stringappend_10420 + stringappend_10440) in + if ((case ((csr_name_map_matches_prefix + stringappend_10450 + :: (( 12 Word.word * ii)) option)) of + Some (stringappend_10460,stringappend_10470) => + if(((string_drop + stringappend_10450 + stringappend_10470)) + = ('''')) then + True else + False + | None => + False + )) then True else + False) + | None => False + )) then True else + False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False))))) then + True else False) + | None => False + )) then + (let (op1, stringappend_10280) = + ((case ((csr_mnemonic_matches_prefix + stringappend_5410)) of + Some (stringappend_10270,stringappend_10280) => + (stringappend_10270, stringappend_10280) + )) in + (let stringappend_10290 = (string_drop + stringappend_5410 + stringappend_10280) in + (let stringappend_10300 = (string_drop + stringappend_10290 + ((string_length (''i'')))) in + (case + (case ((spc_matches_prefix stringappend_10300)) of + Some (stringappend_10310,stringappend_10320) => + (stringappend_10310, stringappend_10320) + ) of + (_, stringappend_10320) => + (let stringappend_10330 = (string_drop + stringappend_10300 + stringappend_10320) in + (let (rd, stringappend_10350) = + ((case ((reg_name_matches_prefix + stringappend_10330 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10340,stringappend_10350) => + (stringappend_10340, stringappend_10350) + )) in + (let stringappend_10360 = (string_drop + stringappend_10330 + stringappend_10350) in + (case + (case ((sep_matches_prefix stringappend_10360)) of + Some (stringappend_10370,stringappend_10380) => + (stringappend_10370, stringappend_10380) + ) of + (_, stringappend_10380) => + (let stringappend_10390 = (string_drop + stringappend_10360 + stringappend_10380) in + (let (rs1, stringappend_10410) = + ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_10390 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10400,stringappend_10410) => + (stringappend_10400, stringappend_10410) + )) in + (let stringappend_10420 = (string_drop + stringappend_10390 + stringappend_10410) in + (case + (case ((sep_matches_prefix stringappend_10420)) of + Some (stringappend_10430,stringappend_10440) => + (stringappend_10430, stringappend_10440) + ) of + (_, stringappend_10440) => + (let stringappend_10450 = (string_drop + stringappend_10420 + stringappend_10440) in + (let (csr, stringappend_10470) = + ((case ((csr_name_map_matches_prefix + stringappend_10450 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_10460,stringappend_10470) => + (stringappend_10460, stringappend_10470) + )) in + if(((string_drop stringappend_10450 stringappend_10470)) + = ('''')) then True else undefined)) + )))) + )))) + )))) else + if ((case ((csr_mnemonic_matches_prefix + stringappend_5410)) of + Some (stringappend_10490,stringappend_10500) => + (let stringappend_10510 = (string_drop + stringappend_5410 + stringappend_10500) in + if ((case ((spc_matches_prefix stringappend_10510)) of + Some (stringappend_10520,stringappend_10530) => + (let stringappend_10540 = (string_drop + stringappend_10510 + stringappend_10530) in + if ((case ((reg_name_matches_prefix + stringappend_10540 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10550,stringappend_10560) => + (let stringappend_10570 = (string_drop + stringappend_10540 + stringappend_10560) in + if ((case ((sep_matches_prefix + stringappend_10570)) of + Some (stringappend_10580,stringappend_10590) => + (let stringappend_10600 = + (string_drop stringappend_10570 + stringappend_10590) in + if ((case ((reg_name_matches_prefix + stringappend_10600 + :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10610,stringappend_10620) => + (let stringappend_10630 = + (string_drop + stringappend_10600 + stringappend_10620) in + if ((case ((sep_matches_prefix + stringappend_10630)) of + Some (stringappend_10640,stringappend_10650) => + (let stringappend_10660 = + (string_drop + stringappend_10630 + stringappend_10650) in + if ((case ((csr_name_map_matches_prefix + stringappend_10660 + :: (( 12 Word.word * ii)) option)) of + Some (stringappend_10670,stringappend_10680) => + if(((string_drop + stringappend_10660 + stringappend_10680)) + = ('''')) then + True else False + | None => False + )) then True else + False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then True else False) + | None => False + )) then + (let (op1, stringappend_10500) = + ((case ((csr_mnemonic_matches_prefix + stringappend_5410)) of + Some (stringappend_10490,stringappend_10500) => + (stringappend_10490, stringappend_10500) + )) in + (let stringappend_10510 = (string_drop + stringappend_5410 + stringappend_10500) in + (case + (case ((spc_matches_prefix stringappend_10510)) of + Some (stringappend_10520,stringappend_10530) => + (stringappend_10520, stringappend_10530) + ) of + (_, stringappend_10530) => + (let stringappend_10540 = (string_drop + stringappend_10510 + stringappend_10530) in + (let (rd, stringappend_10560) = + ((case ((reg_name_matches_prefix + stringappend_10540 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10550,stringappend_10560) => + (stringappend_10550, stringappend_10560) + )) in + (let stringappend_10570 = (string_drop + stringappend_10540 + stringappend_10560) in + (case + (case ((sep_matches_prefix stringappend_10570)) of + Some (stringappend_10580,stringappend_10590) => + (stringappend_10580, stringappend_10590) + ) of + (_, stringappend_10590) => + (let stringappend_10600 = (string_drop + stringappend_10570 + stringappend_10590) in + (let (rs1, stringappend_10620) = + ((case ((reg_name_matches_prefix + stringappend_10600 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_10610,stringappend_10620) => + (stringappend_10610, stringappend_10620) + )) in + (let stringappend_10630 = (string_drop + stringappend_10600 + stringappend_10620) in + (case + (case ((sep_matches_prefix stringappend_10630)) of + Some (stringappend_10640,stringappend_10650) => + (stringappend_10640, stringappend_10650) + ) of + (_, stringappend_10650) => + (let stringappend_10660 = (string_drop + stringappend_10630 + stringappend_10650) in + (let (csr, stringappend_10680) = + ((case ((csr_name_map_matches_prefix + stringappend_10660 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_10670,stringappend_10680) => + (stringappend_10670, stringappend_10680) + )) in + if(((string_drop stringappend_10660 + stringappend_10680)) = ('''')) then True else + undefined)) + )))) + )))) + ))) else + if (((((string_startswith stringappend_5410 + (''illegal''))) \<and> + ((let stringappend_10700 = + (string_drop stringappend_5410 + ((string_length (''illegal'')))) in + if ((case ((spc_matches_prefix + stringappend_10700)) of + Some (stringappend_10710,stringappend_10720) => + (let stringappend_10730 = + (string_drop stringappend_10700 + stringappend_10720) in + if ((case ((hex_bits_32_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_10730 + :: (( 32 Word.word * ii)) option)) of + Some (stringappend_10740,stringappend_10750) => + if(((string_drop stringappend_10730 + stringappend_10750)) = + ('''')) then True else + False + | None => False + )) then True else False) + | None => False + )) then True else False))))) then + (let stringappend_10700 = (string_drop + stringappend_5410 + ((string_length + (''illegal'')))) in + (case + (case ((spc_matches_prefix stringappend_10700)) of + Some (stringappend_10710,stringappend_10720) => + (stringappend_10710, stringappend_10720) + ) of + (_, stringappend_10720) => + (let stringappend_10730 = (string_drop + stringappend_10700 + stringappend_10720) in + (let (s, stringappend_10750) = + ((case ((hex_bits_32_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_10730 :: (( 32 Word.word * ii)) option)) of + Some (stringappend_10740,stringappend_10750) => + (stringappend_10740, stringappend_10750) + )) in + if(((string_drop stringappend_10730 + stringappend_10750)) = ('''')) then + True else undefined)) + )) else False))))))))" + + +(*val assembly_matches_prefix : string -> maybe ((ast * ii))*) + +definition assembly_matches_prefix :: " string \<Rightarrow>(ast*int)option " where + " assembly_matches_prefix arg0 = ( + (let stringappend_00 = arg0 in + if ((case ((utype_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_10,stringappend_20) => + (let stringappend_30 = (string_drop stringappend_00 stringappend_20) in + if ((case ((spc_matches_prefix stringappend_30)) of + Some (stringappend_40,stringappend_50) => + (let stringappend_60 = (string_drop stringappend_30 stringappend_50) in + if ((case ((reg_name_matches_prefix stringappend_60 :: (( 5 Word.word * ii))option)) of + Some (stringappend_70,stringappend_80) => + (let stringappend_90 = (string_drop stringappend_60 stringappend_80) in + if ((case ((sep_matches_prefix stringappend_90)) of + Some (stringappend_100,stringappend_110) => + (let stringappend_120 = (string_drop stringappend_90 stringappend_110) in + if ((case ((hex_bits_20_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_120 + :: (( 20 Word.word * ii))option)) of + Some (stringappend_130,stringappend_140) => + (case ((string_drop stringappend_120 stringappend_140)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_20) = + ((case ((utype_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_10,stringappend_20) => (stringappend_10, stringappend_20) + )) in + (let stringappend_30 = (string_drop stringappend_00 stringappend_20) in + (case + (case ((spc_matches_prefix stringappend_30)) of + Some (stringappend_40,stringappend_50) => (stringappend_40, stringappend_50) + ) of + (_, stringappend_50) => + (let stringappend_60 = (string_drop stringappend_30 stringappend_50) in + (let (rd, stringappend_80) = + ((case ((reg_name_matches_prefix stringappend_60 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_70,stringappend_80) => (stringappend_70, stringappend_80) + )) in + (let stringappend_90 = (string_drop stringappend_60 stringappend_80) in + (case + (case ((sep_matches_prefix stringappend_90)) of + Some (stringappend_100,stringappend_110) => (stringappend_100, stringappend_110) + ) of + (_, stringappend_110) => + (let stringappend_120 = (string_drop stringappend_90 stringappend_110) in + (let (imm, stringappend_140) = + ((case ((hex_bits_20_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_120 :: (( 20 Word.word * ii)) option)) of + Some (stringappend_130,stringappend_140) => (stringappend_130, stringappend_140) + )) in + (case ((string_drop stringappend_120 stringappend_140)) of + s0 => Some + (UTYPE (imm,rd,op1), ((string_length arg0)) - + ((string_length s0))) + ))) + )))) + ))) + else if (((((string_startswith stringappend_00 (''jal''))) \<and> ((let stringappend_160 = (string_drop stringappend_00 ((string_length (''jal'')))) in + if ((case ((spc_matches_prefix stringappend_160)) of + Some (stringappend_170,stringappend_180) => + (let stringappend_190 = (string_drop stringappend_160 stringappend_180) in + if ((case ((reg_name_matches_prefix stringappend_190 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_200,stringappend_210) => + (let stringappend_220 = (string_drop stringappend_190 stringappend_210) in + if ((case ((sep_matches_prefix stringappend_220)) of + Some (stringappend_230,stringappend_240) => + (let stringappend_250 = + (string_drop stringappend_220 stringappend_240) in + if ((case ((hex_bits_21_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_250 + :: (( 21 Word.word * ii))option)) of + Some (stringappend_260,stringappend_270) => + (case ((string_drop stringappend_250 stringappend_270)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_160 = (string_drop stringappend_00 ((string_length (''jal'')))) in + (case + (case ((spc_matches_prefix stringappend_160)) of + Some (stringappend_170,stringappend_180) => (stringappend_170, stringappend_180) + ) of + (_, stringappend_180) => + (let stringappend_190 = (string_drop stringappend_160 stringappend_180) in + (let (rd, stringappend_210) = + ((case ((reg_name_matches_prefix stringappend_190 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_200,stringappend_210) => (stringappend_200, stringappend_210) + )) in + (let stringappend_220 = (string_drop stringappend_190 stringappend_210) in + (case + (case ((sep_matches_prefix stringappend_220)) of + Some (stringappend_230,stringappend_240) => (stringappend_230, stringappend_240) + ) of + (_, stringappend_240) => + (let stringappend_250 = (string_drop stringappend_220 stringappend_240) in + (let (imm, stringappend_270) = + ((case ((hex_bits_21_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_250 :: (( 21 Word.word * ii)) option)) of + Some (stringappend_260,stringappend_270) => (stringappend_260, stringappend_270) + )) in + (case ((string_drop stringappend_250 stringappend_270)) of + s0 => Some + (RISCV_JAL (imm,rd), ((string_length arg0)) - + ((string_length s0))) + ))) + )))) + )) + else if (((((string_startswith stringappend_00 (''jalr''))) \<and> ((let stringappend_290 = (string_drop stringappend_00 ((string_length (''jalr'')))) in + if ((case ((spc_matches_prefix stringappend_290)) of + Some (stringappend_300,stringappend_310) => + (let stringappend_320 = (string_drop stringappend_290 stringappend_310) in + if ((case ((reg_name_matches_prefix stringappend_320 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_330,stringappend_340) => + (let stringappend_350 = (string_drop stringappend_320 stringappend_340) in + if ((case ((sep_matches_prefix stringappend_350)) of + Some (stringappend_360,stringappend_370) => + (let stringappend_380 = + (string_drop stringappend_350 stringappend_370) in + if ((case ((reg_name_matches_prefix stringappend_380 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_390,stringappend_400) => + (let stringappend_410 = + (string_drop stringappend_380 stringappend_400) in + if ((case ((sep_matches_prefix stringappend_410)) of + Some (stringappend_420,stringappend_430) => + (let stringappend_440 = + (string_drop stringappend_410 stringappend_430) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_440 + :: (( 12 Word.word * ii))option)) of + Some (stringappend_450,stringappend_460) => + (case ((string_drop stringappend_440 stringappend_460)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_290 = (string_drop stringappend_00 ((string_length (''jalr'')))) in + (case + (case ((spc_matches_prefix stringappend_290)) of + Some (stringappend_300,stringappend_310) => (stringappend_300, stringappend_310) + ) of + (_, stringappend_310) => + (let stringappend_320 = (string_drop stringappend_290 stringappend_310) in + (let (rd, stringappend_340) = + ((case ((reg_name_matches_prefix stringappend_320 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_330,stringappend_340) => (stringappend_330, stringappend_340) + )) in + (let stringappend_350 = (string_drop stringappend_320 stringappend_340) in + (case + (case ((sep_matches_prefix stringappend_350)) of + Some (stringappend_360,stringappend_370) => (stringappend_360, stringappend_370) + ) of + (_, stringappend_370) => + (let stringappend_380 = (string_drop stringappend_350 stringappend_370) in + (let (rs1, stringappend_400) = + ((case ((reg_name_matches_prefix stringappend_380 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_390,stringappend_400) => (stringappend_390, stringappend_400) + )) in + (let stringappend_410 = (string_drop stringappend_380 stringappend_400) in + (case + (case ((sep_matches_prefix stringappend_410)) of + Some (stringappend_420,stringappend_430) => (stringappend_420, stringappend_430) + ) of + (_, stringappend_430) => + (let stringappend_440 = (string_drop stringappend_410 stringappend_430) in + (let (imm, stringappend_460) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_440 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_450,stringappend_460) => (stringappend_450, stringappend_460) + )) in + (case ((string_drop stringappend_440 stringappend_460)) of + s0 => + Some + (RISCV_JALR (imm,rs1,rd), ((string_length arg0)) - ((string_length s0))) + ))) + )))) + )))) + )) + else if ((case ((btype_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_480,stringappend_490) => + (let stringappend_500 = (string_drop stringappend_00 stringappend_490) in + if ((case ((spc_matches_prefix stringappend_500)) of + Some (stringappend_510,stringappend_520) => + (let stringappend_530 = (string_drop stringappend_500 stringappend_520) in + if ((case ((reg_name_matches_prefix stringappend_530 :: (( 5 Word.word * ii))option)) of + Some (stringappend_540,stringappend_550) => + (let stringappend_560 = (string_drop stringappend_530 stringappend_550) in + if ((case ((sep_matches_prefix stringappend_560)) of + Some (stringappend_570,stringappend_580) => + (let stringappend_590 = (string_drop stringappend_560 stringappend_580) in + if ((case ((reg_name_matches_prefix stringappend_590 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_600,stringappend_610) => + (let stringappend_620 = (string_drop stringappend_590 stringappend_610) in + if ((case ((sep_matches_prefix stringappend_620)) of + Some (stringappend_630,stringappend_640) => + (let stringappend_650 = + (string_drop stringappend_620 stringappend_640) in + if ((case ((hex_bits_13_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_650 + :: (( 13 Word.word * ii))option)) of + Some (stringappend_660,stringappend_670) => + (case ((string_drop stringappend_650 stringappend_670)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_490) = + ((case ((btype_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_480,stringappend_490) => (stringappend_480, stringappend_490) + )) in + (let stringappend_500 = (string_drop stringappend_00 stringappend_490) in + (case + (case ((spc_matches_prefix stringappend_500)) of + Some (stringappend_510,stringappend_520) => (stringappend_510, stringappend_520) + ) of + (_, stringappend_520) => + (let stringappend_530 = (string_drop stringappend_500 stringappend_520) in + (let (rs1, stringappend_550) = + ((case ((reg_name_matches_prefix stringappend_530 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_540,stringappend_550) => (stringappend_540, stringappend_550) + )) in + (let stringappend_560 = (string_drop stringappend_530 stringappend_550) in + (case + (case ((sep_matches_prefix stringappend_560)) of + Some (stringappend_570,stringappend_580) => (stringappend_570, stringappend_580) + ) of + (_, stringappend_580) => + (let stringappend_590 = (string_drop stringappend_560 stringappend_580) in + (let (rs2, stringappend_610) = + ((case ((reg_name_matches_prefix stringappend_590 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_600,stringappend_610) => (stringappend_600, stringappend_610) + )) in + (let stringappend_620 = (string_drop stringappend_590 stringappend_610) in + (case + (case ((sep_matches_prefix stringappend_620)) of + Some (stringappend_630,stringappend_640) => (stringappend_630, stringappend_640) + ) of + (_, stringappend_640) => + (let stringappend_650 = (string_drop stringappend_620 stringappend_640) in + (let (imm, stringappend_670) = + ((case ((hex_bits_13_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_650 :: (( 13 Word.word * ii)) option)) of + Some (stringappend_660,stringappend_670) => (stringappend_660, stringappend_670) + )) in + (case ((string_drop stringappend_650 stringappend_670)) of + s0 => Some + (BTYPE (imm,rs2,rs1,op1), ((string_length arg0)) - + ((string_length s0))) + ))) + )))) + )))) + ))) + else if ((case ((itype_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_690,stringappend_700) => + (let stringappend_710 = (string_drop stringappend_00 stringappend_700) in + if ((case ((spc_matches_prefix stringappend_710)) of + Some (stringappend_720,stringappend_730) => + (let stringappend_740 = (string_drop stringappend_710 stringappend_730) in + if ((case ((reg_name_matches_prefix stringappend_740 :: (( 5 Word.word * ii))option)) of + Some (stringappend_750,stringappend_760) => + (let stringappend_770 = (string_drop stringappend_740 stringappend_760) in + if ((case ((sep_matches_prefix stringappend_770)) of + Some (stringappend_780,stringappend_790) => + (let stringappend_800 = (string_drop stringappend_770 stringappend_790) in + if ((case ((reg_name_matches_prefix stringappend_800 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_810,stringappend_820) => + (let stringappend_830 = (string_drop stringappend_800 stringappend_820) in + if ((case ((sep_matches_prefix stringappend_830)) of + Some (stringappend_840,stringappend_850) => + (let stringappend_860 = + (string_drop stringappend_830 stringappend_850) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_860 + :: (( 12 Word.word * ii))option)) of + Some (stringappend_870,stringappend_880) => + (case ((string_drop stringappend_860 stringappend_880)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_700) = + ((case ((itype_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_690,stringappend_700) => (stringappend_690, stringappend_700) + )) in + (let stringappend_710 = (string_drop stringappend_00 stringappend_700) in + (case + (case ((spc_matches_prefix stringappend_710)) of + Some (stringappend_720,stringappend_730) => (stringappend_720, stringappend_730) + ) of + (_, stringappend_730) => + (let stringappend_740 = (string_drop stringappend_710 stringappend_730) in + (let (rd, stringappend_760) = + ((case ((reg_name_matches_prefix stringappend_740 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_750,stringappend_760) => (stringappend_750, stringappend_760) + )) in + (let stringappend_770 = (string_drop stringappend_740 stringappend_760) in + (case + (case ((sep_matches_prefix stringappend_770)) of + Some (stringappend_780,stringappend_790) => (stringappend_780, stringappend_790) + ) of + (_, stringappend_790) => + (let stringappend_800 = (string_drop stringappend_770 stringappend_790) in + (let (rs1, stringappend_820) = + ((case ((reg_name_matches_prefix stringappend_800 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_810,stringappend_820) => (stringappend_810, stringappend_820) + )) in + (let stringappend_830 = (string_drop stringappend_800 stringappend_820) in + (case + (case ((sep_matches_prefix stringappend_830)) of + Some (stringappend_840,stringappend_850) => (stringappend_840, stringappend_850) + ) of + (_, stringappend_850) => + (let stringappend_860 = (string_drop stringappend_830 stringappend_850) in + (let (imm, stringappend_880) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_860 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_870,stringappend_880) => (stringappend_870, stringappend_880) + )) in + (case ((string_drop stringappend_860 stringappend_880)) of + s0 => Some + (ITYPE (imm,rs1,rd,op1), ((string_length arg0)) - + ((string_length s0))) + ))) + )))) + )))) + ))) + else if ((case ((shiftiop_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_900,stringappend_910) => + (let stringappend_920 = (string_drop stringappend_00 stringappend_910) in + if ((case ((spc_matches_prefix stringappend_920)) of + Some (stringappend_930,stringappend_940) => + (let stringappend_950 = (string_drop stringappend_920 stringappend_940) in + if ((case ((reg_name_matches_prefix stringappend_950 :: (( 5 Word.word * ii))option)) of + Some (stringappend_960,stringappend_970) => + (let stringappend_980 = (string_drop stringappend_950 stringappend_970) in + if ((case ((sep_matches_prefix stringappend_980)) of + Some (stringappend_990,stringappend_1000) => + (let stringappend_1010 = (string_drop stringappend_980 stringappend_1000) in + if ((case ((reg_name_matches_prefix stringappend_1010 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_1020,stringappend_1030) => + (let stringappend_1040 = + (string_drop stringappend_1010 stringappend_1030) in + if ((case ((hex_bits_6_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_1040 + :: (( 6 Word.word * ii))option)) of + Some (stringappend_1050,stringappend_1060) => + (case ((string_drop stringappend_1040 stringappend_1060)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_910) = + ((case ((shiftiop_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_900,stringappend_910) => (stringappend_900, stringappend_910) + )) in + (let stringappend_920 = (string_drop stringappend_00 stringappend_910) in + (case + (case ((spc_matches_prefix stringappend_920)) of + Some (stringappend_930,stringappend_940) => (stringappend_930, stringappend_940) + ) of + (_, stringappend_940) => + (let stringappend_950 = (string_drop stringappend_920 stringappend_940) in + (let (rd, stringappend_970) = + ((case ((reg_name_matches_prefix stringappend_950 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_960,stringappend_970) => (stringappend_960, stringappend_970) + )) in + (let stringappend_980 = (string_drop stringappend_950 stringappend_970) in + (case + (case ((sep_matches_prefix stringappend_980)) of + Some (stringappend_990,stringappend_1000) => (stringappend_990, stringappend_1000) + ) of + (_, stringappend_1000) => + (let stringappend_1010 = (string_drop stringappend_980 stringappend_1000) in + (let (rs1, stringappend_1030) = + ((case ((reg_name_matches_prefix stringappend_1010 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_1020,stringappend_1030) => (stringappend_1020, stringappend_1030) + )) in + (let stringappend_1040 = (string_drop stringappend_1010 stringappend_1030) in + (let (shamt, stringappend_1060) = + ((case ((hex_bits_6_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1040 :: (( 6 Word.word * ii)) option)) of + Some (stringappend_1050,stringappend_1060) => (stringappend_1050, stringappend_1060) + )) in + (case ((string_drop stringappend_1040 stringappend_1060)) of + s0 => + Some + (SHIFTIOP (shamt,rs1,rd,op1), ((string_length arg0)) - + ((string_length s0))) + ))))) + )))) + ))) + else if ((case ((rtype_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_1080,stringappend_1090) => + (let stringappend_1100 = (string_drop stringappend_00 stringappend_1090) in + if ((case ((spc_matches_prefix stringappend_1100)) of + Some (stringappend_1110,stringappend_1120) => + (let stringappend_1130 = (string_drop stringappend_1100 stringappend_1120) in + if ((case ((reg_name_matches_prefix stringappend_1130 :: (( 5 Word.word * ii))option)) of + Some (stringappend_1140,stringappend_1150) => + (let stringappend_1160 = (string_drop stringappend_1130 stringappend_1150) in + if ((case ((sep_matches_prefix stringappend_1160)) of + Some (stringappend_1170,stringappend_1180) => + (let stringappend_1190 = (string_drop stringappend_1160 stringappend_1180) in + if ((case ((reg_name_matches_prefix stringappend_1190 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_1200,stringappend_1210) => + (let stringappend_1220 = + (string_drop stringappend_1190 stringappend_1210) in + if ((case ((sep_matches_prefix stringappend_1220)) of + Some (stringappend_1230,stringappend_1240) => + (let stringappend_1250 = + (string_drop stringappend_1220 stringappend_1240) in + if ((case ((reg_name_matches_prefix stringappend_1250 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_1260,stringappend_1270) => + (case ((string_drop stringappend_1250 stringappend_1270)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_1090) = + ((case ((rtype_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_1080,stringappend_1090) => (stringappend_1080, stringappend_1090) + )) in + (let stringappend_1100 = (string_drop stringappend_00 stringappend_1090) in + (case + (case ((spc_matches_prefix stringappend_1100)) of + Some (stringappend_1110,stringappend_1120) => (stringappend_1110, stringappend_1120) + ) of + (_, stringappend_1120) => + (let stringappend_1130 = (string_drop stringappend_1100 stringappend_1120) in + (let (rd, stringappend_1150) = + ((case ((reg_name_matches_prefix stringappend_1130 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_1140,stringappend_1150) => (stringappend_1140, stringappend_1150) + )) in + (let stringappend_1160 = (string_drop stringappend_1130 stringappend_1150) in + (case + (case ((sep_matches_prefix stringappend_1160)) of + Some (stringappend_1170,stringappend_1180) => (stringappend_1170, stringappend_1180) + ) of + (_, stringappend_1180) => + (let stringappend_1190 = (string_drop stringappend_1160 stringappend_1180) in + (let (rs1, stringappend_1210) = + ((case ((reg_name_matches_prefix stringappend_1190 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_1200,stringappend_1210) => (stringappend_1200, stringappend_1210) + )) in + (let stringappend_1220 = (string_drop stringappend_1190 stringappend_1210) in + (case + (case ((sep_matches_prefix stringappend_1220)) of + Some (stringappend_1230,stringappend_1240) => (stringappend_1230, stringappend_1240) + ) of + (_, stringappend_1240) => + (let stringappend_1250 = (string_drop stringappend_1220 stringappend_1240) in + (let (rs2, stringappend_1270) = + ((case ((reg_name_matches_prefix stringappend_1250 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_1260,stringappend_1270) => (stringappend_1260, stringappend_1270) + )) in + (case ((string_drop stringappend_1250 stringappend_1270)) of + s0 => Some + (RTYPE (rs2,rs1,rd,op1), ((string_length arg0)) - + ((string_length s0))) + ))) + )))) + )))) + ))) + else if (((((string_startswith stringappend_00 (''l''))) \<and> ((let stringappend_1290 = (string_drop stringappend_00 ((string_length (''l'')))) in + if ((case ((size_mnemonic_matches_prefix stringappend_1290)) of + Some (stringappend_1300,stringappend_1310) => + (let stringappend_1320 = (string_drop stringappend_1290 stringappend_1310) in + if ((case ((maybe_u_matches_prefix stringappend_1320)) of + Some (stringappend_1330,stringappend_1340) => + (let stringappend_1350 = (string_drop stringappend_1320 stringappend_1340) in + if ((case ((maybe_aq_matches_prefix stringappend_1350)) of + Some (stringappend_1360,stringappend_1370) => + (let stringappend_1380 = + (string_drop stringappend_1350 stringappend_1370) in + if ((case ((maybe_rl_matches_prefix stringappend_1380)) of + Some (stringappend_1390,stringappend_1400) => + (let stringappend_1410 = + (string_drop stringappend_1380 stringappend_1400) in + if ((case ((spc_matches_prefix stringappend_1410)) of + Some (stringappend_1420,stringappend_1430) => + (let stringappend_1440 = + (string_drop stringappend_1410 stringappend_1430) in + if ((case ((reg_name_matches_prefix stringappend_1440 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_1450,stringappend_1460) => + (let stringappend_1470 = + (string_drop stringappend_1440 stringappend_1460) in + if ((case ((sep_matches_prefix stringappend_1470)) of + Some (stringappend_1480,stringappend_1490) => + (let stringappend_1500 = + (string_drop stringappend_1470 + stringappend_1490) in + if ((case ((reg_name_matches_prefix + stringappend_1500 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_1510,stringappend_1520) => + (let stringappend_1530 = + (string_drop stringappend_1500 + stringappend_1520) in + if ((case ((sep_matches_prefix + stringappend_1530)) of + Some + (stringappend_1540,stringappend_1550) => + (let stringappend_1560 = + (string_drop stringappend_1530 + stringappend_1550) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1560 + :: (( 12 Word.word * ii))option)) of + Some + (stringappend_1570,stringappend_1580) => + (case ((string_drop stringappend_1560 stringappend_1580)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_1290 = (string_drop stringappend_00 ((string_length (''l'')))) in + (let (size1, stringappend_1310) = + ((case ((size_mnemonic_matches_prefix stringappend_1290)) of + Some (stringappend_1300,stringappend_1310) => (stringappend_1300, stringappend_1310) + )) in + (let stringappend_1320 = (string_drop stringappend_1290 stringappend_1310) in + (let (is_unsigned, stringappend_1340) = + ((case ((maybe_u_matches_prefix stringappend_1320)) of + Some (stringappend_1330,stringappend_1340) => (stringappend_1330, stringappend_1340) + )) in + (let stringappend_1350 = (string_drop stringappend_1320 stringappend_1340) in + (let (aq, stringappend_1370) = + ((case ((maybe_aq_matches_prefix stringappend_1350)) of + Some (stringappend_1360,stringappend_1370) => (stringappend_1360, stringappend_1370) + )) in + (let stringappend_1380 = (string_drop stringappend_1350 stringappend_1370) in + (let (rl, stringappend_1400) = + ((case ((maybe_rl_matches_prefix stringappend_1380)) of + Some (stringappend_1390,stringappend_1400) => (stringappend_1390, stringappend_1400) + )) in + (let stringappend_1410 = (string_drop stringappend_1380 stringappend_1400) in + (case + (case ((spc_matches_prefix stringappend_1410)) of + Some (stringappend_1420,stringappend_1430) => (stringappend_1420, stringappend_1430) + ) of + (_, stringappend_1430) => + (let stringappend_1440 = (string_drop stringappend_1410 stringappend_1430) in + (let (rd, stringappend_1460) = + ((case ((reg_name_matches_prefix stringappend_1440 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_1450,stringappend_1460) => (stringappend_1450, stringappend_1460) + )) in + (let stringappend_1470 = (string_drop stringappend_1440 stringappend_1460) in + (case + (case ((sep_matches_prefix stringappend_1470)) of + Some (stringappend_1480,stringappend_1490) => (stringappend_1480, stringappend_1490) + ) of + (_, stringappend_1490) => + (let stringappend_1500 = (string_drop stringappend_1470 stringappend_1490) in + (let (rs1, stringappend_1520) = + ((case ((reg_name_matches_prefix stringappend_1500 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_1510,stringappend_1520) => (stringappend_1510, stringappend_1520) + )) in + (let stringappend_1530 = (string_drop stringappend_1500 stringappend_1520) in + (case + (case ((sep_matches_prefix stringappend_1530)) of + Some (stringappend_1540,stringappend_1550) => (stringappend_1540, stringappend_1550) + ) of + (_, stringappend_1550) => + (let stringappend_1560 = (string_drop stringappend_1530 stringappend_1550) in + (let (imm, stringappend_1580) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1560 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_1570,stringappend_1580) => (stringappend_1570, stringappend_1580) + )) in + (case ((string_drop stringappend_1560 stringappend_1580)) of + s0 => + Some + (LOAD (imm,rs1,rd,is_unsigned,size1,aq,rl), + ((string_length arg0)) - ((string_length s0))) + ))) + )))) + )))) + )))))))))) + else if (((((string_startswith stringappend_00 (''s''))) \<and> ((let stringappend_1600 = (string_drop stringappend_00 ((string_length (''s'')))) in + if ((case ((size_mnemonic_matches_prefix stringappend_1600)) of + Some (stringappend_1610,stringappend_1620) => + (let stringappend_1630 = (string_drop stringappend_1600 stringappend_1620) in + if ((case ((maybe_aq_matches_prefix stringappend_1630)) of + Some (stringappend_1640,stringappend_1650) => + (let stringappend_1660 = (string_drop stringappend_1630 stringappend_1650) in + if ((case ((maybe_rl_matches_prefix stringappend_1660)) of + Some (stringappend_1670,stringappend_1680) => + (let stringappend_1690 = + (string_drop stringappend_1660 stringappend_1680) in + if ((case ((spc_matches_prefix stringappend_1690)) of + Some (stringappend_1700,stringappend_1710) => + (let stringappend_1720 = + (string_drop stringappend_1690 stringappend_1710) in + if ((case ((reg_name_matches_prefix stringappend_1720 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_1730,stringappend_1740) => + (let stringappend_1750 = + (string_drop stringappend_1720 stringappend_1740) in + if ((case ((sep_matches_prefix stringappend_1750)) of + Some (stringappend_1760,stringappend_1770) => + (let stringappend_1780 = + (string_drop stringappend_1750 stringappend_1770) in + if ((case ((reg_name_matches_prefix stringappend_1780 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_1790,stringappend_1800) => + (let stringappend_1810 = + (string_drop stringappend_1780 + stringappend_1800) in + if ((case ((sep_matches_prefix stringappend_1810)) of + Some (stringappend_1820,stringappend_1830) => + (let stringappend_1840 = + (string_drop stringappend_1810 + stringappend_1830) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1840 + :: (( 12 Word.word * ii))option)) of + Some + (stringappend_1850,stringappend_1860) => + (case ((string_drop stringappend_1840 stringappend_1860)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_1600 = (string_drop stringappend_00 ((string_length (''s'')))) in + (let (size1, stringappend_1620) = + ((case ((size_mnemonic_matches_prefix stringappend_1600)) of + Some (stringappend_1610,stringappend_1620) => (stringappend_1610, stringappend_1620) + )) in + (let stringappend_1630 = (string_drop stringappend_1600 stringappend_1620) in + (let (aq, stringappend_1650) = + ((case ((maybe_aq_matches_prefix stringappend_1630)) of + Some (stringappend_1640,stringappend_1650) => (stringappend_1640, stringappend_1650) + )) in + (let stringappend_1660 = (string_drop stringappend_1630 stringappend_1650) in + (let (rl, stringappend_1680) = + ((case ((maybe_rl_matches_prefix stringappend_1660)) of + Some (stringappend_1670,stringappend_1680) => (stringappend_1670, stringappend_1680) + )) in + (let stringappend_1690 = (string_drop stringappend_1660 stringappend_1680) in + (case + (case ((spc_matches_prefix stringappend_1690)) of + Some (stringappend_1700,stringappend_1710) => (stringappend_1700, stringappend_1710) + ) of + (_, stringappend_1710) => + (let stringappend_1720 = (string_drop stringappend_1690 stringappend_1710) in + (let (rd, stringappend_1740) = + ((case ((reg_name_matches_prefix stringappend_1720 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_1730,stringappend_1740) => (stringappend_1730, stringappend_1740) + )) in + (let stringappend_1750 = (string_drop stringappend_1720 stringappend_1740) in + (case + (case ((sep_matches_prefix stringappend_1750)) of + Some (stringappend_1760,stringappend_1770) => (stringappend_1760, stringappend_1770) + ) of + (_, stringappend_1770) => + (let stringappend_1780 = (string_drop stringappend_1750 stringappend_1770) in + (let (rs1, stringappend_1800) = + ((case ((reg_name_matches_prefix stringappend_1780 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_1790,stringappend_1800) => (stringappend_1790, stringappend_1800) + )) in + (let stringappend_1810 = (string_drop stringappend_1780 stringappend_1800) in + (case + (case ((sep_matches_prefix stringappend_1810)) of + Some (stringappend_1820,stringappend_1830) => (stringappend_1820, stringappend_1830) + ) of + (_, stringappend_1830) => + (let stringappend_1840 = (string_drop stringappend_1810 stringappend_1830) in + (let (imm, stringappend_1860) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_1840 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_1850,stringappend_1860) => (stringappend_1850, stringappend_1860) + )) in + (case ((string_drop stringappend_1840 stringappend_1860)) of + s0 => + Some + (STORE (imm,rs1,rd,size1,aq,rl), + ((string_length arg0)) - ((string_length s0))) + ))) + )))) + )))) + )))))))) + else if (((((string_startswith stringappend_00 (''addiw''))) \<and> ((let stringappend_1880 = (string_drop stringappend_00 ((string_length (''addiw'')))) in + if ((case ((spc_matches_prefix stringappend_1880)) of + Some (stringappend_1890,stringappend_1900) => + (let stringappend_1910 = (string_drop stringappend_1880 stringappend_1900) in + if ((case ((reg_name_matches_prefix stringappend_1910 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_1920,stringappend_1930) => + (let stringappend_1940 = (string_drop stringappend_1910 stringappend_1930) in + if ((case ((sep_matches_prefix stringappend_1940)) of + Some (stringappend_1950,stringappend_1960) => + (let stringappend_1970 = + (string_drop stringappend_1940 stringappend_1960) in + if ((case ((reg_name_matches_prefix stringappend_1970 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_1980,stringappend_1990) => + (let stringappend_2000 = + (string_drop stringappend_1970 stringappend_1990) in + if ((case ((sep_matches_prefix stringappend_2000)) of + Some (stringappend_2010,stringappend_2020) => + (let stringappend_2030 = + (string_drop stringappend_2000 stringappend_2020) in + if ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_2030 + :: (( 12 Word.word * ii))option)) of + Some (stringappend_2040,stringappend_2050) => + (case ((string_drop stringappend_2030 stringappend_2050)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_1880 = (string_drop stringappend_00 ((string_length (''addiw'')))) in + (case + (case ((spc_matches_prefix stringappend_1880)) of + Some (stringappend_1890,stringappend_1900) => (stringappend_1890, stringappend_1900) + ) of + (_, stringappend_1900) => + (let stringappend_1910 = (string_drop stringappend_1880 stringappend_1900) in + (let (rd, stringappend_1930) = + ((case ((reg_name_matches_prefix stringappend_1910 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_1920,stringappend_1930) => (stringappend_1920, stringappend_1930) + )) in + (let stringappend_1940 = (string_drop stringappend_1910 stringappend_1930) in + (case + (case ((sep_matches_prefix stringappend_1940)) of + Some (stringappend_1950,stringappend_1960) => (stringappend_1950, stringappend_1960) + ) of + (_, stringappend_1960) => + (let stringappend_1970 = (string_drop stringappend_1940 stringappend_1960) in + (let (rs1, stringappend_1990) = + ((case ((reg_name_matches_prefix stringappend_1970 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_1980,stringappend_1990) => (stringappend_1980, stringappend_1990) + )) in + (let stringappend_2000 = (string_drop stringappend_1970 stringappend_1990) in + (case + (case ((sep_matches_prefix stringappend_2000)) of + Some (stringappend_2010,stringappend_2020) => (stringappend_2010, stringappend_2020) + ) of + (_, stringappend_2020) => + (let stringappend_2030 = (string_drop stringappend_2000 stringappend_2020) in + (let (imm, stringappend_2050) = + ((case ((hex_bits_12_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_2030 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_2040,stringappend_2050) => (stringappend_2040, stringappend_2050) + )) in + (case ((string_drop stringappend_2030 stringappend_2050)) of + s0 => Some + (ADDIW (imm,rs1,rd), ((string_length arg0)) - + ((string_length s0))) + ))) + )))) + )))) + )) + else if ((case ((shiftw_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_2070,stringappend_2080) => + (let stringappend_2090 = (string_drop stringappend_00 stringappend_2080) in + if ((case ((spc_matches_prefix stringappend_2090)) of + Some (stringappend_2100,stringappend_2110) => + (let stringappend_2120 = (string_drop stringappend_2090 stringappend_2110) in + if ((case ((reg_name_matches_prefix stringappend_2120 :: (( 5 Word.word * ii))option)) of + Some (stringappend_2130,stringappend_2140) => + (let stringappend_2150 = (string_drop stringappend_2120 stringappend_2140) in + if ((case ((sep_matches_prefix stringappend_2150)) of + Some (stringappend_2160,stringappend_2170) => + (let stringappend_2180 = (string_drop stringappend_2150 stringappend_2170) in + if ((case ((reg_name_matches_prefix stringappend_2180 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_2190,stringappend_2200) => + (let stringappend_2210 = + (string_drop stringappend_2180 stringappend_2200) in + if ((case ((sep_matches_prefix stringappend_2210)) of + Some (stringappend_2220,stringappend_2230) => + (let stringappend_2240 = + (string_drop stringappend_2210 stringappend_2230) in + if ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_2240 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_2250,stringappend_2260) => + (case ((string_drop stringappend_2240 stringappend_2260)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_2080) = + ((case ((shiftw_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_2070,stringappend_2080) => (stringappend_2070, stringappend_2080) + )) in + (let stringappend_2090 = (string_drop stringappend_00 stringappend_2080) in + (case + (case ((spc_matches_prefix stringappend_2090)) of + Some (stringappend_2100,stringappend_2110) => (stringappend_2100, stringappend_2110) + ) of + (_, stringappend_2110) => + (let stringappend_2120 = (string_drop stringappend_2090 stringappend_2110) in + (let (rd, stringappend_2140) = + ((case ((reg_name_matches_prefix stringappend_2120 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2130,stringappend_2140) => (stringappend_2130, stringappend_2140) + )) in + (let stringappend_2150 = (string_drop stringappend_2120 stringappend_2140) in + (case + (case ((sep_matches_prefix stringappend_2150)) of + Some (stringappend_2160,stringappend_2170) => (stringappend_2160, stringappend_2170) + ) of + (_, stringappend_2170) => + (let stringappend_2180 = (string_drop stringappend_2150 stringappend_2170) in + (let (rs1, stringappend_2200) = + ((case ((reg_name_matches_prefix stringappend_2180 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2190,stringappend_2200) => (stringappend_2190, stringappend_2200) + )) in + (let stringappend_2210 = (string_drop stringappend_2180 stringappend_2200) in + (case + (case ((sep_matches_prefix stringappend_2210)) of + Some (stringappend_2220,stringappend_2230) => (stringappend_2220, stringappend_2230) + ) of + (_, stringappend_2230) => + (let stringappend_2240 = (string_drop stringappend_2210 stringappend_2230) in + (let (shamt, stringappend_2260) = + ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_2240 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2250,stringappend_2260) => (stringappend_2250, stringappend_2260) + )) in + (case ((string_drop stringappend_2240 stringappend_2260)) of + s0 => + Some + (SHIFTW (shamt,rs1,rd,op1), ((string_length arg0)) - ((string_length s0))) + ))) + )))) + )))) + ))) + else if ((case ((rtypew_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_2280,stringappend_2290) => + (let stringappend_2300 = (string_drop stringappend_00 stringappend_2290) in + if ((case ((spc_matches_prefix stringappend_2300)) of + Some (stringappend_2310,stringappend_2320) => + (let stringappend_2330 = (string_drop stringappend_2300 stringappend_2320) in + if ((case ((reg_name_matches_prefix stringappend_2330 :: (( 5 Word.word * ii))option)) of + Some (stringappend_2340,stringappend_2350) => + (let stringappend_2360 = (string_drop stringappend_2330 stringappend_2350) in + if ((case ((sep_matches_prefix stringappend_2360)) of + Some (stringappend_2370,stringappend_2380) => + (let stringappend_2390 = (string_drop stringappend_2360 stringappend_2380) in + if ((case ((reg_name_matches_prefix stringappend_2390 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_2400,stringappend_2410) => + (let stringappend_2420 = + (string_drop stringappend_2390 stringappend_2410) in + if ((case ((sep_matches_prefix stringappend_2420)) of + Some (stringappend_2430,stringappend_2440) => + (let stringappend_2450 = + (string_drop stringappend_2420 stringappend_2440) in + if ((case ((reg_name_matches_prefix stringappend_2450 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_2460,stringappend_2470) => + (case ((string_drop stringappend_2450 stringappend_2470)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_2290) = + ((case ((rtypew_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_2280,stringappend_2290) => (stringappend_2280, stringappend_2290) + )) in + (let stringappend_2300 = (string_drop stringappend_00 stringappend_2290) in + (case + (case ((spc_matches_prefix stringappend_2300)) of + Some (stringappend_2310,stringappend_2320) => (stringappend_2310, stringappend_2320) + ) of + (_, stringappend_2320) => + (let stringappend_2330 = (string_drop stringappend_2300 stringappend_2320) in + (let (rd, stringappend_2350) = + ((case ((reg_name_matches_prefix stringappend_2330 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2340,stringappend_2350) => (stringappend_2340, stringappend_2350) + )) in + (let stringappend_2360 = (string_drop stringappend_2330 stringappend_2350) in + (case + (case ((sep_matches_prefix stringappend_2360)) of + Some (stringappend_2370,stringappend_2380) => (stringappend_2370, stringappend_2380) + ) of + (_, stringappend_2380) => + (let stringappend_2390 = (string_drop stringappend_2360 stringappend_2380) in + (let (rs1, stringappend_2410) = + ((case ((reg_name_matches_prefix stringappend_2390 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2400,stringappend_2410) => (stringappend_2400, stringappend_2410) + )) in + (let stringappend_2420 = (string_drop stringappend_2390 stringappend_2410) in + (case + (case ((sep_matches_prefix stringappend_2420)) of + Some (stringappend_2430,stringappend_2440) => (stringappend_2430, stringappend_2440) + ) of + (_, stringappend_2440) => + (let stringappend_2450 = (string_drop stringappend_2420 stringappend_2440) in + (let (rs2, stringappend_2470) = + ((case ((reg_name_matches_prefix stringappend_2450 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2460,stringappend_2470) => (stringappend_2460, stringappend_2470) + )) in + (case ((string_drop stringappend_2450 stringappend_2470)) of + s0 => Some + (RTYPEW (rs2,rs1,rd,op1), ((string_length arg0)) - + ((string_length s0))) + ))) + )))) + )))) + ))) + else if ((case ((mul_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_2490,stringappend_2500) => + (let stringappend_2510 = (string_drop stringappend_00 stringappend_2500) in + if ((case ((spc_matches_prefix stringappend_2510)) of + Some (stringappend_2520,stringappend_2530) => + (let stringappend_2540 = (string_drop stringappend_2510 stringappend_2530) in + if ((case ((reg_name_matches_prefix stringappend_2540 :: (( 5 Word.word * ii))option)) of + Some (stringappend_2550,stringappend_2560) => + (let stringappend_2570 = (string_drop stringappend_2540 stringappend_2560) in + if ((case ((sep_matches_prefix stringappend_2570)) of + Some (stringappend_2580,stringappend_2590) => + (let stringappend_2600 = (string_drop stringappend_2570 stringappend_2590) in + if ((case ((reg_name_matches_prefix stringappend_2600 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_2610,stringappend_2620) => + (let stringappend_2630 = + (string_drop stringappend_2600 stringappend_2620) in + if ((case ((sep_matches_prefix stringappend_2630)) of + Some (stringappend_2640,stringappend_2650) => + (let stringappend_2660 = + (string_drop stringappend_2630 stringappend_2650) in + if ((case ((reg_name_matches_prefix stringappend_2660 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_2670,stringappend_2680) => + (case ((string_drop stringappend_2660 stringappend_2680)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let ((high, signed1, signed2), stringappend_2500) = + ((case ((mul_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_2490,stringappend_2500) => (stringappend_2490, stringappend_2500) + )) in + (let stringappend_2510 = (string_drop stringappend_00 stringappend_2500) in + (case + (case ((spc_matches_prefix stringappend_2510)) of + Some (stringappend_2520,stringappend_2530) => (stringappend_2520, stringappend_2530) + ) of + (_, stringappend_2530) => + (let stringappend_2540 = (string_drop stringappend_2510 stringappend_2530) in + (let (rd, stringappend_2560) = + ((case ((reg_name_matches_prefix stringappend_2540 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2550,stringappend_2560) => (stringappend_2550, stringappend_2560) + )) in + (let stringappend_2570 = (string_drop stringappend_2540 stringappend_2560) in + (case + (case ((sep_matches_prefix stringappend_2570)) of + Some (stringappend_2580,stringappend_2590) => (stringappend_2580, stringappend_2590) + ) of + (_, stringappend_2590) => + (let stringappend_2600 = (string_drop stringappend_2570 stringappend_2590) in + (let (rs1, stringappend_2620) = + ((case ((reg_name_matches_prefix stringappend_2600 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2610,stringappend_2620) => (stringappend_2610, stringappend_2620) + )) in + (let stringappend_2630 = (string_drop stringappend_2600 stringappend_2620) in + (case + (case ((sep_matches_prefix stringappend_2630)) of + Some (stringappend_2640,stringappend_2650) => (stringappend_2640, stringappend_2650) + ) of + (_, stringappend_2650) => + (let stringappend_2660 = (string_drop stringappend_2630 stringappend_2650) in + (let (rs2, stringappend_2680) = + ((case ((reg_name_matches_prefix stringappend_2660 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2670,stringappend_2680) => (stringappend_2670, stringappend_2680) + )) in + (case ((string_drop stringappend_2660 stringappend_2680)) of + s0 => + Some + (MUL (rs2,rs1,rd,high,signed1,signed2), + ((string_length arg0)) - ((string_length s0))) + ))) + )))) + )))) + ))) + else if (((((string_startswith stringappend_00 (''div''))) \<and> ((let stringappend_2700 = (string_drop stringappend_00 ((string_length (''div'')))) in + if ((case ((maybe_not_u_matches_prefix stringappend_2700)) of + Some (stringappend_2710,stringappend_2720) => + (let stringappend_2730 = (string_drop stringappend_2700 stringappend_2720) in + if ((case ((spc_matches_prefix stringappend_2730)) of + Some (stringappend_2740,stringappend_2750) => + (let stringappend_2760 = (string_drop stringappend_2730 stringappend_2750) in + if ((case ((reg_name_matches_prefix stringappend_2760 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_2770,stringappend_2780) => + (let stringappend_2790 = + (string_drop stringappend_2760 stringappend_2780) in + if ((case ((sep_matches_prefix stringappend_2790)) of + Some (stringappend_2800,stringappend_2810) => + (let stringappend_2820 = + (string_drop stringappend_2790 stringappend_2810) in + if ((case ((reg_name_matches_prefix stringappend_2820 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_2830,stringappend_2840) => + (let stringappend_2850 = + (string_drop stringappend_2820 stringappend_2840) in + if ((case ((sep_matches_prefix stringappend_2850)) of + Some (stringappend_2860,stringappend_2870) => + (let stringappend_2880 = + (string_drop stringappend_2850 stringappend_2870) in + if ((case ((reg_name_matches_prefix stringappend_2880 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_2890,stringappend_2900) => + (case ((string_drop stringappend_2880 stringappend_2900)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_2700 = (string_drop stringappend_00 ((string_length (''div'')))) in + (let (s, stringappend_2720) = + ((case ((maybe_not_u_matches_prefix stringappend_2700)) of + Some (stringappend_2710,stringappend_2720) => (stringappend_2710, stringappend_2720) + )) in + (let stringappend_2730 = (string_drop stringappend_2700 stringappend_2720) in + (case + (case ((spc_matches_prefix stringappend_2730)) of + Some (stringappend_2740,stringappend_2750) => (stringappend_2740, stringappend_2750) + ) of + (_, stringappend_2750) => + (let stringappend_2760 = (string_drop stringappend_2730 stringappend_2750) in + (let (rd, stringappend_2780) = + ((case ((reg_name_matches_prefix stringappend_2760 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2770,stringappend_2780) => (stringappend_2770, stringappend_2780) + )) in + (let stringappend_2790 = (string_drop stringappend_2760 stringappend_2780) in + (case + (case ((sep_matches_prefix stringappend_2790)) of + Some (stringappend_2800,stringappend_2810) => (stringappend_2800, stringappend_2810) + ) of + (_, stringappend_2810) => + (let stringappend_2820 = (string_drop stringappend_2790 stringappend_2810) in + (let (rs1, stringappend_2840) = + ((case ((reg_name_matches_prefix stringappend_2820 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2830,stringappend_2840) => (stringappend_2830, stringappend_2840) + )) in + (let stringappend_2850 = (string_drop stringappend_2820 stringappend_2840) in + (case + (case ((sep_matches_prefix stringappend_2850)) of + Some (stringappend_2860,stringappend_2870) => (stringappend_2860, stringappend_2870) + ) of + (_, stringappend_2870) => + (let stringappend_2880 = (string_drop stringappend_2850 stringappend_2870) in + (let (rs2, stringappend_2900) = + ((case ((reg_name_matches_prefix stringappend_2880 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2890,stringappend_2900) => (stringappend_2890, stringappend_2900) + )) in + (case ((string_drop stringappend_2880 stringappend_2900)) of + s1 => Some + (DIV (rs2,rs1,rd,s), ((string_length arg0)) - + ((string_length s1))) + ))) + )))) + )))) + )))) + else if (((((string_startswith stringappend_00 (''rem''))) \<and> ((let stringappend_2920 = (string_drop stringappend_00 ((string_length (''rem'')))) in + if ((case ((maybe_not_u_matches_prefix stringappend_2920)) of + Some (stringappend_2930,stringappend_2940) => + (let stringappend_2950 = (string_drop stringappend_2920 stringappend_2940) in + if ((case ((spc_matches_prefix stringappend_2950)) of + Some (stringappend_2960,stringappend_2970) => + (let stringappend_2980 = (string_drop stringappend_2950 stringappend_2970) in + if ((case ((reg_name_matches_prefix stringappend_2980 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_2990,stringappend_3000) => + (let stringappend_3010 = + (string_drop stringappend_2980 stringappend_3000) in + if ((case ((sep_matches_prefix stringappend_3010)) of + Some (stringappend_3020,stringappend_3030) => + (let stringappend_3040 = + (string_drop stringappend_3010 stringappend_3030) in + if ((case ((reg_name_matches_prefix stringappend_3040 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_3050,stringappend_3060) => + (let stringappend_3070 = + (string_drop stringappend_3040 stringappend_3060) in + if ((case ((sep_matches_prefix stringappend_3070)) of + Some (stringappend_3080,stringappend_3090) => + (let stringappend_3100 = + (string_drop stringappend_3070 stringappend_3090) in + if ((case ((reg_name_matches_prefix stringappend_3100 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_3110,stringappend_3120) => + (case ((string_drop stringappend_3100 stringappend_3120)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_2920 = (string_drop stringappend_00 ((string_length (''rem'')))) in + (let (s, stringappend_2940) = + ((case ((maybe_not_u_matches_prefix stringappend_2920)) of + Some (stringappend_2930,stringappend_2940) => (stringappend_2930, stringappend_2940) + )) in + (let stringappend_2950 = (string_drop stringappend_2920 stringappend_2940) in + (case + (case ((spc_matches_prefix stringappend_2950)) of + Some (stringappend_2960,stringappend_2970) => (stringappend_2960, stringappend_2970) + ) of + (_, stringappend_2970) => + (let stringappend_2980 = (string_drop stringappend_2950 stringappend_2970) in + (let (rd, stringappend_3000) = + ((case ((reg_name_matches_prefix stringappend_2980 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_2990,stringappend_3000) => (stringappend_2990, stringappend_3000) + )) in + (let stringappend_3010 = (string_drop stringappend_2980 stringappend_3000) in + (case + (case ((sep_matches_prefix stringappend_3010)) of + Some (stringappend_3020,stringappend_3030) => (stringappend_3020, stringappend_3030) + ) of + (_, stringappend_3030) => + (let stringappend_3040 = (string_drop stringappend_3010 stringappend_3030) in + (let (rs1, stringappend_3060) = + ((case ((reg_name_matches_prefix stringappend_3040 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_3050,stringappend_3060) => (stringappend_3050, stringappend_3060) + )) in + (let stringappend_3070 = (string_drop stringappend_3040 stringappend_3060) in + (case + (case ((sep_matches_prefix stringappend_3070)) of + Some (stringappend_3080,stringappend_3090) => (stringappend_3080, stringappend_3090) + ) of + (_, stringappend_3090) => + (let stringappend_3100 = (string_drop stringappend_3070 stringappend_3090) in + (let (rs2, stringappend_3120) = + ((case ((reg_name_matches_prefix stringappend_3100 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_3110,stringappend_3120) => (stringappend_3110, stringappend_3120) + )) in + (case ((string_drop stringappend_3100 stringappend_3120)) of + s1 => Some + (REM (rs2,rs1,rd,s), ((string_length arg0)) - + ((string_length s1))) + ))) + )))) + )))) + )))) + else if (((((string_startswith stringappend_00 (''mulw''))) \<and> ((let stringappend_3140 = (string_drop stringappend_00 ((string_length (''mulw'')))) in + if ((case ((spc_matches_prefix stringappend_3140)) of + Some (stringappend_3150,stringappend_3160) => + (let stringappend_3170 = (string_drop stringappend_3140 stringappend_3160) in + if ((case ((reg_name_matches_prefix stringappend_3170 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_3180,stringappend_3190) => + (let stringappend_3200 = (string_drop stringappend_3170 stringappend_3190) in + if ((case ((sep_matches_prefix stringappend_3200)) of + Some (stringappend_3210,stringappend_3220) => + (let stringappend_3230 = + (string_drop stringappend_3200 stringappend_3220) in + if ((case ((reg_name_matches_prefix stringappend_3230 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_3240,stringappend_3250) => + (let stringappend_3260 = + (string_drop stringappend_3230 stringappend_3250) in + if ((case ((sep_matches_prefix stringappend_3260)) of + Some (stringappend_3270,stringappend_3280) => + (let stringappend_3290 = + (string_drop stringappend_3260 stringappend_3280) in + if ((case ((reg_name_matches_prefix stringappend_3290 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_3300,stringappend_3310) => + (case ((string_drop stringappend_3290 stringappend_3310)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_3140 = (string_drop stringappend_00 ((string_length (''mulw'')))) in + (case + (case ((spc_matches_prefix stringappend_3140)) of + Some (stringappend_3150,stringappend_3160) => (stringappend_3150, stringappend_3160) + ) of + (_, stringappend_3160) => + (let stringappend_3170 = (string_drop stringappend_3140 stringappend_3160) in + (let (rd, stringappend_3190) = + ((case ((reg_name_matches_prefix stringappend_3170 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_3180,stringappend_3190) => (stringappend_3180, stringappend_3190) + )) in + (let stringappend_3200 = (string_drop stringappend_3170 stringappend_3190) in + (case + (case ((sep_matches_prefix stringappend_3200)) of + Some (stringappend_3210,stringappend_3220) => (stringappend_3210, stringappend_3220) + ) of + (_, stringappend_3220) => + (let stringappend_3230 = (string_drop stringappend_3200 stringappend_3220) in + (let (rs1, stringappend_3250) = + ((case ((reg_name_matches_prefix stringappend_3230 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_3240,stringappend_3250) => (stringappend_3240, stringappend_3250) + )) in + (let stringappend_3260 = (string_drop stringappend_3230 stringappend_3250) in + (case + (case ((sep_matches_prefix stringappend_3260)) of + Some (stringappend_3270,stringappend_3280) => (stringappend_3270, stringappend_3280) + ) of + (_, stringappend_3280) => + (let stringappend_3290 = (string_drop stringappend_3260 stringappend_3280) in + (let (rs2, stringappend_3310) = + ((case ((reg_name_matches_prefix stringappend_3290 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_3300,stringappend_3310) => (stringappend_3300, stringappend_3310) + )) in + (case ((string_drop stringappend_3290 stringappend_3310)) of + s0 => Some + (MULW (rs2,rs1,rd), ((string_length arg0)) - + ((string_length s0))) + ))) + )))) + )))) + )) + else if (((((string_startswith stringappend_00 (''div''))) \<and> ((let stringappend_3330 = (string_drop stringappend_00 ((string_length (''div'')))) in + if ((case ((maybe_not_u_matches_prefix stringappend_3330)) of + Some (stringappend_3340,stringappend_3350) => + (let stringappend_3360 = (string_drop stringappend_3330 stringappend_3350) in + if (((((string_startswith stringappend_3360 (''w''))) \<and> ((let stringappend_3370 = + (string_drop stringappend_3360 ((string_length (''w'')))) in + if ((case ((spc_matches_prefix stringappend_3370)) of + Some (stringappend_3380,stringappend_3390) => + (let stringappend_3400 = + (string_drop stringappend_3370 stringappend_3390) in + if ((case ((reg_name_matches_prefix stringappend_3400 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_3410,stringappend_3420) => + (let stringappend_3430 = + (string_drop stringappend_3400 stringappend_3420) in + if ((case ((sep_matches_prefix stringappend_3430)) of + Some (stringappend_3440,stringappend_3450) => + (let stringappend_3460 = + (string_drop stringappend_3430 stringappend_3450) in + if ((case ((reg_name_matches_prefix stringappend_3460 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_3470,stringappend_3480) => + (let stringappend_3490 = + (string_drop stringappend_3460 stringappend_3480) in + if ((case ((sep_matches_prefix stringappend_3490)) of + Some (stringappend_3500,stringappend_3510) => + (let stringappend_3520 = + (string_drop stringappend_3490 + stringappend_3510) in + if ((case ((reg_name_matches_prefix + stringappend_3520 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_3530,stringappend_3540) => + (case ((string_drop stringappend_3520 stringappend_3540)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_3330 = (string_drop stringappend_00 ((string_length (''div'')))) in + (let (s, stringappend_3350) = + ((case ((maybe_not_u_matches_prefix stringappend_3330)) of + Some (stringappend_3340,stringappend_3350) => (stringappend_3340, stringappend_3350) + )) in + (let stringappend_3360 = (string_drop stringappend_3330 stringappend_3350) in + (let stringappend_3370 = (string_drop stringappend_3360 ((string_length (''w'')))) in + (case + (case ((spc_matches_prefix stringappend_3370)) of + Some (stringappend_3380,stringappend_3390) => (stringappend_3380, stringappend_3390) + ) of + (_, stringappend_3390) => + (let stringappend_3400 = (string_drop stringappend_3370 stringappend_3390) in + (let (rd, stringappend_3420) = + ((case ((reg_name_matches_prefix stringappend_3400 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_3410,stringappend_3420) => (stringappend_3410, stringappend_3420) + )) in + (let stringappend_3430 = (string_drop stringappend_3400 stringappend_3420) in + (case + (case ((sep_matches_prefix stringappend_3430)) of + Some (stringappend_3440,stringappend_3450) => (stringappend_3440, stringappend_3450) + ) of + (_, stringappend_3450) => + (let stringappend_3460 = (string_drop stringappend_3430 stringappend_3450) in + (let (rs1, stringappend_3480) = + ((case ((reg_name_matches_prefix stringappend_3460 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_3470,stringappend_3480) => (stringappend_3470, stringappend_3480) + )) in + (let stringappend_3490 = (string_drop stringappend_3460 stringappend_3480) in + (case + (case ((sep_matches_prefix stringappend_3490)) of + Some (stringappend_3500,stringappend_3510) => (stringappend_3500, stringappend_3510) + ) of + (_, stringappend_3510) => + (let stringappend_3520 = (string_drop stringappend_3490 stringappend_3510) in + (let (rs2, stringappend_3540) = + ((case ((reg_name_matches_prefix stringappend_3520 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_3530,stringappend_3540) => (stringappend_3530, stringappend_3540) + )) in + (case ((string_drop stringappend_3520 stringappend_3540)) of + s1 => Some + (DIVW (rs2,rs1,rd,s), ((string_length arg0)) - + ((string_length s1))) + ))) + )))) + )))) + ))))) + else if (((((string_startswith stringappend_00 (''rem''))) \<and> ((let stringappend_3560 = (string_drop stringappend_00 ((string_length (''rem'')))) in + if ((case ((maybe_not_u_matches_prefix stringappend_3560)) of + Some (stringappend_3570,stringappend_3580) => + (let stringappend_3590 = (string_drop stringappend_3560 stringappend_3580) in + if (((((string_startswith stringappend_3590 (''w''))) \<and> ((let stringappend_3600 = + (string_drop stringappend_3590 ((string_length (''w'')))) in + if ((case ((spc_matches_prefix stringappend_3600)) of + Some (stringappend_3610,stringappend_3620) => + (let stringappend_3630 = + (string_drop stringappend_3600 stringappend_3620) in + if ((case ((reg_name_matches_prefix stringappend_3630 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_3640,stringappend_3650) => + (let stringappend_3660 = + (string_drop stringappend_3630 stringappend_3650) in + if ((case ((sep_matches_prefix stringappend_3660)) of + Some (stringappend_3670,stringappend_3680) => + (let stringappend_3690 = + (string_drop stringappend_3660 stringappend_3680) in + if ((case ((reg_name_matches_prefix stringappend_3690 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_3700,stringappend_3710) => + (let stringappend_3720 = + (string_drop stringappend_3690 stringappend_3710) in + if ((case ((sep_matches_prefix stringappend_3720)) of + Some (stringappend_3730,stringappend_3740) => + (let stringappend_3750 = + (string_drop stringappend_3720 + stringappend_3740) in + if ((case ((reg_name_matches_prefix + stringappend_3750 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_3760,stringappend_3770) => + (case ((string_drop stringappend_3750 stringappend_3770)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_3560 = (string_drop stringappend_00 ((string_length (''rem'')))) in + (let (s, stringappend_3580) = + ((case ((maybe_not_u_matches_prefix stringappend_3560)) of + Some (stringappend_3570,stringappend_3580) => (stringappend_3570, stringappend_3580) + )) in + (let stringappend_3590 = (string_drop stringappend_3560 stringappend_3580) in + (let stringappend_3600 = (string_drop stringappend_3590 ((string_length (''w'')))) in + (case + (case ((spc_matches_prefix stringappend_3600)) of + Some (stringappend_3610,stringappend_3620) => (stringappend_3610, stringappend_3620) + ) of + (_, stringappend_3620) => + (let stringappend_3630 = (string_drop stringappend_3600 stringappend_3620) in + (let (rd, stringappend_3650) = + ((case ((reg_name_matches_prefix stringappend_3630 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_3640,stringappend_3650) => (stringappend_3640, stringappend_3650) + )) in + (let stringappend_3660 = (string_drop stringappend_3630 stringappend_3650) in + (case + (case ((sep_matches_prefix stringappend_3660)) of + Some (stringappend_3670,stringappend_3680) => (stringappend_3670, stringappend_3680) + ) of + (_, stringappend_3680) => + (let stringappend_3690 = (string_drop stringappend_3660 stringappend_3680) in + (let (rs1, stringappend_3710) = + ((case ((reg_name_matches_prefix stringappend_3690 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_3700,stringappend_3710) => (stringappend_3700, stringappend_3710) + )) in + (let stringappend_3720 = (string_drop stringappend_3690 stringappend_3710) in + (case + (case ((sep_matches_prefix stringappend_3720)) of + Some (stringappend_3730,stringappend_3740) => (stringappend_3730, stringappend_3740) + ) of + (_, stringappend_3740) => + (let stringappend_3750 = (string_drop stringappend_3720 stringappend_3740) in + (let (rs2, stringappend_3770) = + ((case ((reg_name_matches_prefix stringappend_3750 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_3760,stringappend_3770) => (stringappend_3760, stringappend_3770) + )) in + (case ((string_drop stringappend_3750 stringappend_3770)) of + s1 => Some + (REMW (rs2,rs1,rd,s), ((string_length arg0)) - + ((string_length s1))) + ))) + )))) + )))) + ))))) + else if (((((string_startswith stringappend_00 (''fence''))) \<and> ((let stringappend_3790 = (string_drop stringappend_00 ((string_length (''fence'')))) in + if ((case ((spc_matches_prefix stringappend_3790)) of + Some (stringappend_3800,stringappend_3810) => + (let stringappend_3820 = (string_drop stringappend_3790 stringappend_3810) in + if ((case ((fence_bits_matches_prefix stringappend_3820 + :: (( 4 Word.word * ii))option)) of + Some (stringappend_3830,stringappend_3840) => + (let stringappend_3850 = (string_drop stringappend_3820 stringappend_3840) in + if ((case ((sep_matches_prefix stringappend_3850)) of + Some (stringappend_3860,stringappend_3870) => + (let stringappend_3880 = + (string_drop stringappend_3850 stringappend_3870) in + if ((case ((fence_bits_matches_prefix stringappend_3880 + :: (( 4 Word.word * ii))option)) of + Some (stringappend_3890,stringappend_3900) => + (case ((string_drop stringappend_3880 stringappend_3900)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_3790 = (string_drop stringappend_00 ((string_length (''fence'')))) in + (case + (case ((spc_matches_prefix stringappend_3790)) of + Some (stringappend_3800,stringappend_3810) => (stringappend_3800, stringappend_3810) + ) of + (_, stringappend_3810) => + (let stringappend_3820 = (string_drop stringappend_3790 stringappend_3810) in + (let (pred, stringappend_3840) = + ((case ((fence_bits_matches_prefix stringappend_3820 :: (( 4 Word.word * ii)) option)) of + Some (stringappend_3830,stringappend_3840) => (stringappend_3830, stringappend_3840) + )) in + (let stringappend_3850 = (string_drop stringappend_3820 stringappend_3840) in + (case + (case ((sep_matches_prefix stringappend_3850)) of + Some (stringappend_3860,stringappend_3870) => (stringappend_3860, stringappend_3870) + ) of + (_, stringappend_3870) => + (let stringappend_3880 = (string_drop stringappend_3850 stringappend_3870) in + (let (succ, stringappend_3900) = + ((case ((fence_bits_matches_prefix stringappend_3880 :: (( 4 Word.word * ii)) option)) of + Some (stringappend_3890,stringappend_3900) => (stringappend_3890, stringappend_3900) + )) in + (case ((string_drop stringappend_3880 stringappend_3900)) of + s0 => Some + (FENCE (pred,succ), ((string_length arg0)) - + ((string_length s0))) + ))) + )))) + )) + else if (((((string_startswith stringappend_00 (''fence.i''))) \<and> ( + (case ((string_drop stringappend_00 ((string_length (''fence.i''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_00 ((string_length (''fence.i''))))) of + s0 => Some (FENCEI () , ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_00 (''ecall''))) \<and> ( + (case ((string_drop stringappend_00 ((string_length (''ecall''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_00 ((string_length (''ecall''))))) of + s0 => Some (ECALL () , ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_00 (''mret''))) \<and> ( + (case ((string_drop stringappend_00 ((string_length (''mret''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_00 ((string_length (''mret''))))) of + s0 => Some (MRET () , ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_00 (''sret''))) \<and> ( + (case ((string_drop stringappend_00 ((string_length (''sret''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_00 ((string_length (''sret''))))) of + s0 => Some (SRET () , ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_00 (''ebreak''))) \<and> ( + (case ((string_drop stringappend_00 ((string_length (''ebreak''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_00 ((string_length (''ebreak''))))) of + s0 => Some (EBREAK () , ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_00 (''wfi''))) \<and> ( + (case ((string_drop stringappend_00 ((string_length (''wfi''))))) of + s0 => True + ))))) then + (case ((string_drop stringappend_00 ((string_length (''wfi''))))) of + s0 => Some (WFI () , ((string_length arg0)) - ((string_length s0))) + ) + else if (((((string_startswith stringappend_00 (''sfence.vma''))) \<and> ((let stringappend_3980 = (string_drop stringappend_00 ((string_length (''sfence.vma'')))) in + if ((case ((spc_matches_prefix stringappend_3980)) of + Some (stringappend_3990,stringappend_4000) => + (let stringappend_4010 = (string_drop stringappend_3980 stringappend_4000) in + if ((case ((reg_name_matches_prefix stringappend_4010 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_4020,stringappend_4030) => + (let stringappend_4040 = (string_drop stringappend_4010 stringappend_4030) in + if ((case ((sep_matches_prefix stringappend_4040)) of + Some (stringappend_4050,stringappend_4060) => + (let stringappend_4070 = + (string_drop stringappend_4040 stringappend_4060) in + if ((case ((reg_name_matches_prefix stringappend_4070 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_4080,stringappend_4090) => + (case ((string_drop stringappend_4070 stringappend_4090)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_3980 = (string_drop stringappend_00 ((string_length (''sfence.vma'')))) in + (case + (case ((spc_matches_prefix stringappend_3980)) of + Some (stringappend_3990,stringappend_4000) => (stringappend_3990, stringappend_4000) + ) of + (_, stringappend_4000) => + (let stringappend_4010 = (string_drop stringappend_3980 stringappend_4000) in + (let (rs1, stringappend_4030) = + ((case ((reg_name_matches_prefix stringappend_4010 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_4020,stringappend_4030) => (stringappend_4020, stringappend_4030) + )) in + (let stringappend_4040 = (string_drop stringappend_4010 stringappend_4030) in + (case + (case ((sep_matches_prefix stringappend_4040)) of + Some (stringappend_4050,stringappend_4060) => (stringappend_4050, stringappend_4060) + ) of + (_, stringappend_4060) => + (let stringappend_4070 = (string_drop stringappend_4040 stringappend_4060) in + (let (rs2, stringappend_4090) = + ((case ((reg_name_matches_prefix stringappend_4070 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_4080,stringappend_4090) => (stringappend_4080, stringappend_4090) + )) in + (case ((string_drop stringappend_4070 stringappend_4090)) of + s0 => Some + (SFENCE_VMA (rs1,rs2), ((string_length arg0)) - + ((string_length s0))) + ))) + )))) + )) + else if (((((string_startswith stringappend_00 (''lr.''))) \<and> ((let stringappend_4110 = (string_drop stringappend_00 ((string_length (''lr.'')))) in + if ((case ((maybe_aq_matches_prefix stringappend_4110)) of + Some (stringappend_4120,stringappend_4130) => + (let stringappend_4140 = (string_drop stringappend_4110 stringappend_4130) in + if ((case ((maybe_rl_matches_prefix stringappend_4140)) of + Some (stringappend_4150,stringappend_4160) => + (let stringappend_4170 = (string_drop stringappend_4140 stringappend_4160) in + if ((case ((size_mnemonic_matches_prefix stringappend_4170)) of + Some (stringappend_4180,stringappend_4190) => + (let stringappend_4200 = + (string_drop stringappend_4170 stringappend_4190) in + if ((case ((spc_matches_prefix stringappend_4200)) of + Some (stringappend_4210,stringappend_4220) => + (let stringappend_4230 = + (string_drop stringappend_4200 stringappend_4220) in + if ((case ((reg_name_matches_prefix stringappend_4230 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_4240,stringappend_4250) => + (let stringappend_4260 = + (string_drop stringappend_4230 stringappend_4250) in + if ((case ((sep_matches_prefix stringappend_4260)) of + Some (stringappend_4270,stringappend_4280) => + (let stringappend_4290 = + (string_drop stringappend_4260 stringappend_4280) in + if ((case ((reg_name_matches_prefix stringappend_4290 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_4300,stringappend_4310) => + (case ((string_drop stringappend_4290 stringappend_4310)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_4110 = (string_drop stringappend_00 ((string_length (''lr.'')))) in + (let (aq, stringappend_4130) = + ((case ((maybe_aq_matches_prefix stringappend_4110)) of + Some (stringappend_4120,stringappend_4130) => (stringappend_4120, stringappend_4130) + )) in + (let stringappend_4140 = (string_drop stringappend_4110 stringappend_4130) in + (let (rl, stringappend_4160) = + ((case ((maybe_rl_matches_prefix stringappend_4140)) of + Some (stringappend_4150,stringappend_4160) => (stringappend_4150, stringappend_4160) + )) in + (let stringappend_4170 = (string_drop stringappend_4140 stringappend_4160) in + (let (size1, stringappend_4190) = + ((case ((size_mnemonic_matches_prefix stringappend_4170)) of + Some (stringappend_4180,stringappend_4190) => (stringappend_4180, stringappend_4190) + )) in + (let stringappend_4200 = (string_drop stringappend_4170 stringappend_4190) in + (case + (case ((spc_matches_prefix stringappend_4200)) of + Some (stringappend_4210,stringappend_4220) => (stringappend_4210, stringappend_4220) + ) of + (_, stringappend_4220) => + (let stringappend_4230 = (string_drop stringappend_4200 stringappend_4220) in + (let (rd, stringappend_4250) = + ((case ((reg_name_matches_prefix stringappend_4230 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_4240,stringappend_4250) => (stringappend_4240, stringappend_4250) + )) in + (let stringappend_4260 = (string_drop stringappend_4230 stringappend_4250) in + (case + (case ((sep_matches_prefix stringappend_4260)) of + Some (stringappend_4270,stringappend_4280) => (stringappend_4270, stringappend_4280) + ) of + (_, stringappend_4280) => + (let stringappend_4290 = (string_drop stringappend_4260 stringappend_4280) in + (let (rs1, stringappend_4310) = + ((case ((reg_name_matches_prefix stringappend_4290 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_4300,stringappend_4310) => (stringappend_4300, stringappend_4310) + )) in + (case ((string_drop stringappend_4290 stringappend_4310)) of + s0 => + Some + (LOADRES (aq,rl,rs1,size1,rd), ((string_length arg0)) - + ((string_length s0))) + ))) + )))) + )))))))) + else if (((((string_startswith stringappend_00 (''sc.''))) \<and> ((let stringappend_4330 = (string_drop stringappend_00 ((string_length (''sc.'')))) in + if ((case ((maybe_aq_matches_prefix stringappend_4330)) of + Some (stringappend_4340,stringappend_4350) => + (let stringappend_4360 = (string_drop stringappend_4330 stringappend_4350) in + if ((case ((maybe_rl_matches_prefix stringappend_4360)) of + Some (stringappend_4370,stringappend_4380) => + (let stringappend_4390 = (string_drop stringappend_4360 stringappend_4380) in + if ((case ((size_mnemonic_matches_prefix stringappend_4390)) of + Some (stringappend_4400,stringappend_4410) => + (let stringappend_4420 = + (string_drop stringappend_4390 stringappend_4410) in + if ((case ((spc_matches_prefix stringappend_4420)) of + Some (stringappend_4430,stringappend_4440) => + (let stringappend_4450 = + (string_drop stringappend_4420 stringappend_4440) in + if ((case ((reg_name_matches_prefix stringappend_4450 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_4460,stringappend_4470) => + (let stringappend_4480 = + (string_drop stringappend_4450 stringappend_4470) in + if ((case ((sep_matches_prefix stringappend_4480)) of + Some (stringappend_4490,stringappend_4500) => + (let stringappend_4510 = + (string_drop stringappend_4480 stringappend_4500) in + if ((case ((reg_name_matches_prefix stringappend_4510 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_4520,stringappend_4530) => + (let stringappend_4540 = + (string_drop stringappend_4510 + stringappend_4530) in + if ((case ((sep_matches_prefix stringappend_4540)) of + Some (stringappend_4550,stringappend_4560) => + (let stringappend_4570 = + (string_drop stringappend_4540 + stringappend_4560) in + if ((case ((reg_name_matches_prefix + stringappend_4570 + :: (( 5 Word.word * ii))option)) of + Some + (stringappend_4580,stringappend_4590) => + (case ((string_drop stringappend_4570 stringappend_4590)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_4330 = (string_drop stringappend_00 ((string_length (''sc.'')))) in + (let (aq, stringappend_4350) = + ((case ((maybe_aq_matches_prefix stringappend_4330)) of + Some (stringappend_4340,stringappend_4350) => (stringappend_4340, stringappend_4350) + )) in + (let stringappend_4360 = (string_drop stringappend_4330 stringappend_4350) in + (let (rl, stringappend_4380) = + ((case ((maybe_rl_matches_prefix stringappend_4360)) of + Some (stringappend_4370,stringappend_4380) => (stringappend_4370, stringappend_4380) + )) in + (let stringappend_4390 = (string_drop stringappend_4360 stringappend_4380) in + (let (size1, stringappend_4410) = + ((case ((size_mnemonic_matches_prefix stringappend_4390)) of + Some (stringappend_4400,stringappend_4410) => (stringappend_4400, stringappend_4410) + )) in + (let stringappend_4420 = (string_drop stringappend_4390 stringappend_4410) in + (case + (case ((spc_matches_prefix stringappend_4420)) of + Some (stringappend_4430,stringappend_4440) => (stringappend_4430, stringappend_4440) + ) of + (_, stringappend_4440) => + (let stringappend_4450 = (string_drop stringappend_4420 stringappend_4440) in + (let (rd, stringappend_4470) = + ((case ((reg_name_matches_prefix stringappend_4450 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_4460,stringappend_4470) => (stringappend_4460, stringappend_4470) + )) in + (let stringappend_4480 = (string_drop stringappend_4450 stringappend_4470) in + (case + (case ((sep_matches_prefix stringappend_4480)) of + Some (stringappend_4490,stringappend_4500) => (stringappend_4490, stringappend_4500) + ) of + (_, stringappend_4500) => + (let stringappend_4510 = (string_drop stringappend_4480 stringappend_4500) in + (let (rs1, stringappend_4530) = + ((case ((reg_name_matches_prefix stringappend_4510 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_4520,stringappend_4530) => (stringappend_4520, stringappend_4530) + )) in + (let stringappend_4540 = (string_drop stringappend_4510 stringappend_4530) in + (case + (case ((sep_matches_prefix stringappend_4540)) of + Some (stringappend_4550,stringappend_4560) => (stringappend_4550, stringappend_4560) + ) of + (_, stringappend_4560) => + (let stringappend_4570 = (string_drop stringappend_4540 stringappend_4560) in + (let (rs2, stringappend_4590) = + ((case ((reg_name_matches_prefix stringappend_4570 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_4580,stringappend_4590) => (stringappend_4580, stringappend_4590) + )) in + (case ((string_drop stringappend_4570 stringappend_4590)) of + s0 => + Some + (STORECON (aq,rl,rs2,rs1,size1,rd), + ((string_length arg0)) - ((string_length s0))) + ))) + )))) + )))) + )))))))) + else if ((case ((amo_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_4610,stringappend_4620) => + (let stringappend_4630 = (string_drop stringappend_00 stringappend_4620) in + if (((((string_startswith stringappend_4630 (''.''))) \<and> ((let stringappend_4640 = (string_drop stringappend_4630 ((string_length (''.'')))) in + if ((case ((size_mnemonic_matches_prefix stringappend_4640)) of + Some (stringappend_4650,stringappend_4660) => + (let stringappend_4670 = (string_drop stringappend_4640 stringappend_4660) in + if ((case ((maybe_aq_matches_prefix stringappend_4670)) of + Some (stringappend_4680,stringappend_4690) => + (let stringappend_4700 = (string_drop stringappend_4670 stringappend_4690) in + if ((case ((maybe_rl_matches_prefix stringappend_4700)) of + Some (stringappend_4710,stringappend_4720) => + (let stringappend_4730 = + (string_drop stringappend_4700 stringappend_4720) in + if ((case ((spc_matches_prefix stringappend_4730)) of + Some (stringappend_4740,stringappend_4750) => + (let stringappend_4760 = + (string_drop stringappend_4730 stringappend_4750) in + if ((case ((reg_name_matches_prefix stringappend_4760 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_4770,stringappend_4780) => + (let stringappend_4790 = + (string_drop stringappend_4760 stringappend_4780) in + if ((case ((sep_matches_prefix stringappend_4790)) of + Some (stringappend_4800,stringappend_4810) => + (let stringappend_4820 = + (string_drop stringappend_4790 stringappend_4810) in + if ((case ((reg_name_matches_prefix stringappend_4820 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_4830,stringappend_4840) => + (let stringappend_4850 = + (string_drop stringappend_4820 + stringappend_4840) in + if ((case ((sep_matches_prefix stringappend_4850)) of + Some (stringappend_4860,stringappend_4870) => + (let stringappend_4880 = + (string_drop stringappend_4850 + stringappend_4870) in + if ((case ((reg_name_matches_prefix + stringappend_4880 + :: (( 5 Word.word * ii))option)) of + Some + (stringappend_4890,stringappend_4900) => + (case ((string_drop stringappend_4880 stringappend_4900)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + True + else False) + | None => False + )) then + (let (op1, stringappend_4620) = + ((case ((amo_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_4610,stringappend_4620) => (stringappend_4610, stringappend_4620) + )) in + (let stringappend_4630 = (string_drop stringappend_00 stringappend_4620) in + (let stringappend_4640 = (string_drop stringappend_4630 ((string_length (''.'')))) in + (let (width, stringappend_4660) = + ((case ((size_mnemonic_matches_prefix stringappend_4640)) of + Some (stringappend_4650,stringappend_4660) => (stringappend_4650, stringappend_4660) + )) in + (let stringappend_4670 = (string_drop stringappend_4640 stringappend_4660) in + (let (aq, stringappend_4690) = + ((case ((maybe_aq_matches_prefix stringappend_4670)) of + Some (stringappend_4680,stringappend_4690) => (stringappend_4680, stringappend_4690) + )) in + (let stringappend_4700 = (string_drop stringappend_4670 stringappend_4690) in + (let (rl, stringappend_4720) = + ((case ((maybe_rl_matches_prefix stringappend_4700)) of + Some (stringappend_4710,stringappend_4720) => (stringappend_4710, stringappend_4720) + )) in + (let stringappend_4730 = (string_drop stringappend_4700 stringappend_4720) in + (case + (case ((spc_matches_prefix stringappend_4730)) of + Some (stringappend_4740,stringappend_4750) => (stringappend_4740, stringappend_4750) + ) of + (_, stringappend_4750) => + (let stringappend_4760 = (string_drop stringappend_4730 stringappend_4750) in + (let (rd, stringappend_4780) = + ((case ((reg_name_matches_prefix stringappend_4760 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_4770,stringappend_4780) => (stringappend_4770, stringappend_4780) + )) in + (let stringappend_4790 = (string_drop stringappend_4760 stringappend_4780) in + (case + (case ((sep_matches_prefix stringappend_4790)) of + Some (stringappend_4800,stringappend_4810) => (stringappend_4800, stringappend_4810) + ) of + (_, stringappend_4810) => + (let stringappend_4820 = (string_drop stringappend_4790 stringappend_4810) in + (let (rs1, stringappend_4840) = + ((case ((reg_name_matches_prefix stringappend_4820 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_4830,stringappend_4840) => (stringappend_4830, stringappend_4840) + )) in + (let stringappend_4850 = (string_drop stringappend_4820 stringappend_4840) in + (case + (case ((sep_matches_prefix stringappend_4850)) of + Some (stringappend_4860,stringappend_4870) => (stringappend_4860, stringappend_4870) + ) of + (_, stringappend_4870) => + (let stringappend_4880 = (string_drop stringappend_4850 stringappend_4870) in + (let (rs2, stringappend_4900) = + ((case ((reg_name_matches_prefix stringappend_4880 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_4890,stringappend_4900) => (stringappend_4890, stringappend_4900) + )) in + (case ((string_drop stringappend_4880 stringappend_4900)) of + s0 => + Some + (AMO (op1,aq,rl,rs2,rs1,width,rd), + ((string_length arg0)) - ((string_length s0))) + ))) + )))) + )))) + )))))))))) + else if ((case ((csr_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_4920,stringappend_4930) => + (let stringappend_4940 = (string_drop stringappend_00 stringappend_4930) in + if (((((string_startswith stringappend_4940 (''i''))) \<and> ((let stringappend_4950 = (string_drop stringappend_4940 ((string_length (''i'')))) in + if ((case ((spc_matches_prefix stringappend_4950)) of + Some (stringappend_4960,stringappend_4970) => + (let stringappend_4980 = (string_drop stringappend_4950 stringappend_4970) in + if ((case ((reg_name_matches_prefix stringappend_4980 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_4990,stringappend_5000) => + (let stringappend_5010 = (string_drop stringappend_4980 stringappend_5000) in + if ((case ((sep_matches_prefix stringappend_5010)) of + Some (stringappend_5020,stringappend_5030) => + (let stringappend_5040 = + (string_drop stringappend_5010 stringappend_5030) in + if ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_5040 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_5050,stringappend_5060) => + (let stringappend_5070 = + (string_drop stringappend_5040 stringappend_5060) in + if ((case ((sep_matches_prefix stringappend_5070)) of + Some (stringappend_5080,stringappend_5090) => + (let stringappend_5100 = + (string_drop stringappend_5070 stringappend_5090) in + if ((case ((csr_name_map_matches_prefix stringappend_5100 + :: (( 12 Word.word * ii))option)) of + Some (stringappend_5110,stringappend_5120) => + (case ((string_drop stringappend_5100 stringappend_5120)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + True + else False) + | None => False + )) then + (let (op1, stringappend_4930) = + ((case ((csr_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_4920,stringappend_4930) => (stringappend_4920, stringappend_4930) + )) in + (let stringappend_4940 = (string_drop stringappend_00 stringappend_4930) in + (let stringappend_4950 = (string_drop stringappend_4940 ((string_length (''i'')))) in + (case + (case ((spc_matches_prefix stringappend_4950)) of + Some (stringappend_4960,stringappend_4970) => (stringappend_4960, stringappend_4970) + ) of + (_, stringappend_4970) => + (let stringappend_4980 = (string_drop stringappend_4950 stringappend_4970) in + (let (rd, stringappend_5000) = + ((case ((reg_name_matches_prefix stringappend_4980 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_4990,stringappend_5000) => (stringappend_4990, stringappend_5000) + )) in + (let stringappend_5010 = (string_drop stringappend_4980 stringappend_5000) in + (case + (case ((sep_matches_prefix stringappend_5010)) of + Some (stringappend_5020,stringappend_5030) => (stringappend_5020, stringappend_5030) + ) of + (_, stringappend_5030) => + (let stringappend_5040 = (string_drop stringappend_5010 stringappend_5030) in + (let (rs1, stringappend_5060) = + ((case ((hex_bits_5_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_5040 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_5050,stringappend_5060) => (stringappend_5050, stringappend_5060) + )) in + (let stringappend_5070 = (string_drop stringappend_5040 stringappend_5060) in + (case + (case ((sep_matches_prefix stringappend_5070)) of + Some (stringappend_5080,stringappend_5090) => (stringappend_5080, stringappend_5090) + ) of + (_, stringappend_5090) => + (let stringappend_5100 = (string_drop stringappend_5070 stringappend_5090) in + (let (csr, stringappend_5120) = + ((case ((csr_name_map_matches_prefix stringappend_5100 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_5110,stringappend_5120) => (stringappend_5110, stringappend_5120) + )) in + (case ((string_drop stringappend_5100 stringappend_5120)) of + s0 => + Some + (CSR (csr,rs1,rd,True,op1), ((string_length arg0)) - ((string_length s0))) + ))) + )))) + )))) + )))) + else if ((case ((csr_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_5140,stringappend_5150) => + (let stringappend_5160 = (string_drop stringappend_00 stringappend_5150) in + if ((case ((spc_matches_prefix stringappend_5160)) of + Some (stringappend_5170,stringappend_5180) => + (let stringappend_5190 = (string_drop stringappend_5160 stringappend_5180) in + if ((case ((reg_name_matches_prefix stringappend_5190 :: (( 5 Word.word * ii))option)) of + Some (stringappend_5200,stringappend_5210) => + (let stringappend_5220 = (string_drop stringappend_5190 stringappend_5210) in + if ((case ((sep_matches_prefix stringappend_5220)) of + Some (stringappend_5230,stringappend_5240) => + (let stringappend_5250 = (string_drop stringappend_5220 stringappend_5240) in + if ((case ((reg_name_matches_prefix stringappend_5250 + :: (( 5 Word.word * ii))option)) of + Some (stringappend_5260,stringappend_5270) => + (let stringappend_5280 = + (string_drop stringappend_5250 stringappend_5270) in + if ((case ((sep_matches_prefix stringappend_5280)) of + Some (stringappend_5290,stringappend_5300) => + (let stringappend_5310 = + (string_drop stringappend_5280 stringappend_5300) in + if ((case ((csr_name_map_matches_prefix stringappend_5310 + :: (( 12 Word.word * ii))option)) of + Some (stringappend_5320,stringappend_5330) => + (case ((string_drop stringappend_5310 stringappend_5330)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False) + | None => False + )) then + (let (op1, stringappend_5150) = + ((case ((csr_mnemonic_matches_prefix stringappend_00)) of + Some (stringappend_5140,stringappend_5150) => (stringappend_5140, stringappend_5150) + )) in + (let stringappend_5160 = (string_drop stringappend_00 stringappend_5150) in + (case + (case ((spc_matches_prefix stringappend_5160)) of + Some (stringappend_5170,stringappend_5180) => (stringappend_5170, stringappend_5180) + ) of + (_, stringappend_5180) => + (let stringappend_5190 = (string_drop stringappend_5160 stringappend_5180) in + (let (rd, stringappend_5210) = + ((case ((reg_name_matches_prefix stringappend_5190 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_5200,stringappend_5210) => (stringappend_5200, stringappend_5210) + )) in + (let stringappend_5220 = (string_drop stringappend_5190 stringappend_5210) in + (case + (case ((sep_matches_prefix stringappend_5220)) of + Some (stringappend_5230,stringappend_5240) => (stringappend_5230, stringappend_5240) + ) of + (_, stringappend_5240) => + (let stringappend_5250 = (string_drop stringappend_5220 stringappend_5240) in + (let (rs1, stringappend_5270) = + ((case ((reg_name_matches_prefix stringappend_5250 :: (( 5 Word.word * ii)) option)) of + Some (stringappend_5260,stringappend_5270) => (stringappend_5260, stringappend_5270) + )) in + (let stringappend_5280 = (string_drop stringappend_5250 stringappend_5270) in + (case + (case ((sep_matches_prefix stringappend_5280)) of + Some (stringappend_5290,stringappend_5300) => (stringappend_5290, stringappend_5300) + ) of + (_, stringappend_5300) => + (let stringappend_5310 = (string_drop stringappend_5280 stringappend_5300) in + (let (csr, stringappend_5330) = + ((case ((csr_name_map_matches_prefix stringappend_5310 :: (( 12 Word.word * ii)) option)) of + Some (stringappend_5320,stringappend_5330) => (stringappend_5320, stringappend_5330) + )) in + (case ((string_drop stringappend_5310 stringappend_5330)) of + s0 => + Some + (CSR (csr,rs1,rd,False,op1), ((string_length arg0)) - + ((string_length s0))) + ))) + )))) + )))) + ))) + else if (((((string_startswith stringappend_00 (''illegal''))) \<and> ((let stringappend_5350 = (string_drop stringappend_00 ((string_length (''illegal'')))) in + if ((case ((spc_matches_prefix stringappend_5350)) of + Some (stringappend_5360,stringappend_5370) => + (let stringappend_5380 = (string_drop stringappend_5350 stringappend_5370) in + if ((case ((hex_bits_32_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict stringappend_5380 + :: (( 32 Word.word * ii))option)) of + Some (stringappend_5390,stringappend_5400) => + (case ((string_drop stringappend_5380 stringappend_5400)) of s0 => True ) + | None => False + )) then + True + else False) + | None => False + )) then + True + else False))))) then + (let stringappend_5350 = (string_drop stringappend_00 ((string_length (''illegal'')))) in + (case + (case ((spc_matches_prefix stringappend_5350)) of + Some (stringappend_5360,stringappend_5370) => (stringappend_5360, stringappend_5370) + ) of + (_, stringappend_5370) => + (let stringappend_5380 = (string_drop stringappend_5350 stringappend_5370) in + (let (s, stringappend_5400) = + ((case ((hex_bits_32_matches_prefix + instance_Sail2_values_Bitvector_Machine_word_mword_dict + stringappend_5380 :: (( 32 Word.word * ii)) option)) of + Some (stringappend_5390,stringappend_5400) => (stringappend_5390, stringappend_5400) + )) in + (case ((string_drop stringappend_5380 stringappend_5400)) of + s1 => Some (ILLEGAL s, ((string_length arg0)) - ((string_length s1))) + ))) + )) + else None))" + + +(*val encdec_forwards : ast -> mword ty32*) + +fun encdec_forwards :: " ast \<Rightarrow>(32)Word.word " where + " encdec_forwards (UTYPE (imm,rd,op1)) = ( + (concat_vec imm ((concat_vec rd ((encdec_uop_forwards op1 :: 7 Word.word)) :: 12 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RISCV_JAL (v__172,rd)) = ( + (let (imm_19 :: 1 bits) = ((subrange_vec_dec v__172 (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word)) in + (let (imm_7_0 :: 8 bits) = ((subrange_vec_dec v__172 (( 19 :: int)::ii) (( 12 :: int)::ii) :: 8 Word.word)) in + (let (imm_8 :: 1 bits) = ((subrange_vec_dec v__172 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in + (let (imm_18_13 :: 6 bits) = ((subrange_vec_dec v__172 (( 10 :: int)::ii) (( 5 :: int)::ii) :: 6 Word.word)) in + (let (imm_12_9 :: 4 bits) = ((subrange_vec_dec v__172 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) in + (concat_vec imm_19 + ((concat_vec imm_18_13 + ((concat_vec imm_12_9 + ((concat_vec imm_8 + ((concat_vec imm_7_0 + ((concat_vec rd (vec_of_bits [B1,B1,B0,B1,B1,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 20 Word.word)) + :: 21 Word.word)) + :: 25 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)))))))" +|" encdec_forwards (RISCV_JALR (imm,rs1,rd)) = ( + (concat_vec imm + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B1,B1,B0,B0,B1,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (BTYPE (v__173,rs2,rs1,op1)) = ( + (let (imm7_6 :: 1 bits) = ((subrange_vec_dec v__173 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (imm5_0 :: 1 bits) = ((subrange_vec_dec v__173 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in + (let (imm7_5_0 :: 6 bits) = ((subrange_vec_dec v__173 (( 10 :: int)::ii) (( 5 :: int)::ii) :: 6 Word.word)) in + (let (imm5_4_1 :: 4 bits) = ((subrange_vec_dec v__173 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) in + (concat_vec imm7_6 + ((concat_vec imm7_5_0 + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec ((encdec_bop_forwards op1 :: 3 Word.word)) + ((concat_vec imm5_4_1 + ((concat_vec imm5_0 (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word) + :: 8 Word.word)) + :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 31 Word.word)) + :: 32 Word.word))))))" +|" encdec_forwards (ITYPE (imm,rs1,rd,op1)) = ( + (concat_vec imm + ((concat_vec rs1 + ((concat_vec ((encdec_iop_forwards op1 :: 3 Word.word)) + ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word) + ((concat_vec shamt + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 26 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word) + ((concat_vec shamt + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 26 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI)) = ( + (concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word) + ((concat_vec shamt + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 26 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_ADD)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_SUB)) = ( + (concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_SLL)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_SLT)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B1,B0] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_SLTU)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B1,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_XOR)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B0,B0] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_SRL)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_SRA)) = ( + (concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_OR)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B1,B0] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPE (rs2,rs1,rd,RISCV_AND)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B1,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (LOAD (imm,rs1,rd,is_unsigned,size1,False,False)) = ( + (concat_vec imm + ((concat_vec rs1 + ((concat_vec ((bool_bits_forwards is_unsigned :: 1 Word.word)) + ((concat_vec ((size_bits_forwards size1 :: 2 Word.word)) + ((concat_vec rd (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 14 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (STORE (v__174,rs2,rs1,size1,False,False)) = ( + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__174 (( 11 :: int)::ii) (( 5 :: int)::ii) :: 7 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__174 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + (concat_vec imm7 + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((concat_vec ((size_bits_forwards size1 :: 2 Word.word)) + ((concat_vec imm5 (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 14 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))))" +|" encdec_forwards (ADDIW (imm,rs1,rd)) = ( + (concat_vec imm + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (SHIFTW (shamt,rs1,rd,RISCV_SLLI)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec shamt + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (SHIFTW (shamt,rs1,rd,RISCV_SRLI)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec shamt + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (SHIFTW (shamt,rs1,rd,RISCV_SRAI)) = ( + (concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec shamt + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPEW (rs2,rs1,rd,RISCV_ADDW)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPEW (rs2,rs1,rd,RISCV_SUBW)) = ( + (concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPEW (rs2,rs1,rd,RISCV_SLLW)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPEW (rs2,rs1,rd,RISCV_SRLW)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (RTYPEW (rs2,rs1,rd,RISCV_SRAW)) = ( + (concat_vec (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B0,B1] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (MUL (rs2,rs1,rd,high,signed1,signed2)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec ((encdec_mul_op_forwards high signed1 signed2 :: 3 Word.word)) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (DIV (rs2,rs1,rd,s)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B0] :: 2 Word.word) + ((concat_vec ((bool_not_bits_forwards s :: 1 Word.word)) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 13 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (REM (rs2,rs1,rd,s)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word) + ((concat_vec ((bool_not_bits_forwards s :: 1 Word.word)) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 13 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (MULW (rs2,rs1,rd)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (DIVW (rs2,rs1,rd,s)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B0] :: 2 Word.word) + ((concat_vec ((bool_not_bits_forwards s :: 1 Word.word)) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 13 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (REMW (rs2,rs1,rd,s)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B1,B1] :: 2 Word.word) + ((concat_vec ((bool_not_bits_forwards s :: 1 Word.word)) + ((concat_vec rd (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 13 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (FENCE (pred,succ)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec pred + ((concat_vec succ + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + (vec_of_bits [B0,B0,B0,B1,B1,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 24 Word.word)) + :: 28 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (FENCEI (_)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B1] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + (vec_of_bits [B0,B0,B0,B1,B1,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (ECALL (_)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (MRET (_)) = ( + (concat_vec (vec_of_bits [B0,B0,B1,B1,B0,B0,B0] :: 7 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (SRET (_)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B1,B0,B0,B0] :: 7 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (EBREAK (_)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (WFI (_)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (SFENCE_VMA (rs1,rs2)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B1,B0,B0,B1] :: 7 Word.word) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (LOADRES (aq,rl,rs1,size1,rd)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word) + ((concat_vec ((bool_bits_forwards aq :: 1 Word.word)) + ((concat_vec ((bool_bits_forwards rl :: 1 Word.word)) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((concat_vec ((size_bits_forwards size1 :: 2 Word.word)) + ((concat_vec rd (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 14 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 26 Word.word)) + :: 27 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (STORECON (aq,rl,rs2,rs1,size1,rd)) = ( + (concat_vec (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word) + ((concat_vec ((bool_bits_forwards aq :: 1 Word.word)) + ((concat_vec ((bool_bits_forwards rl :: 1 Word.word)) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((concat_vec ((size_bits_forwards size1 :: 2 Word.word)) + ((concat_vec rd (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 14 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 26 Word.word)) + :: 27 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (AMO (op1,aq,rl,rs2,rs1,size1,rd)) = ( + (concat_vec ((encdec_amoop_forwards op1 :: 5 Word.word)) + ((concat_vec ((bool_bits_forwards aq :: 1 Word.word)) + ((concat_vec ((bool_bits_forwards rl :: 1 Word.word)) + ((concat_vec rs2 + ((concat_vec rs1 + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((concat_vec ((size_bits_forwards size1 :: 2 Word.word)) + ((concat_vec rd (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word) + :: 12 Word.word)) + :: 14 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 25 Word.word)) + :: 26 Word.word)) + :: 27 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (CSR (csr,rs1,rd,is_imm,op1)) = ( + (concat_vec csr + ((concat_vec rs1 + ((concat_vec ((bool_bits_forwards is_imm :: 1 Word.word)) + ((concat_vec ((encdec_csrop_forwards op1 :: 2 Word.word)) + ((concat_vec rd (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word) :: 12 Word.word)) + :: 14 Word.word)) + :: 15 Word.word)) + :: 20 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (STOP_FETCHING (_)) = ( + (concat_vec (vec_of_bits [B1,B1,B1,B1,B1,B0,B1,B0,B1,B1,B0,B1,B1,B1,B1,B0] :: 16 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word) + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word) + ((concat_vec (vec_of_bits [B0,B1,B0] :: 3 Word.word) + (vec_of_bits [B1,B1] :: 2 Word.word) + :: 5 Word.word)) + :: 7 Word.word)) + :: 8 Word.word)) + :: 16 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (THREAD_START (_)) = ( + (concat_vec (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1,B1,B1,B1,B0] :: 16 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word) + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word) + ((concat_vec (vec_of_bits [B0,B1,B0] :: 3 Word.word) + (vec_of_bits [B1,B1] :: 2 Word.word) + :: 5 Word.word)) + :: 7 Word.word)) + :: 8 Word.word)) + :: 16 Word.word)) + :: 32 Word.word))" +|" encdec_forwards (ILLEGAL (s)) = ( s )" + + +(*val encdec_backwards : mword ty32 -> ast*) + +definition encdec_backwards :: "(32)Word.word \<Rightarrow> ast " where + " encdec_backwards arg0 = ( + (let v__175 = arg0 in + if ((let mappingpatterns_230 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + encdec_uop_backwards_matches mappingpatterns_230)) then + (let (imm :: 20 Word.word) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_230 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (let op1 = (encdec_uop_backwards mappingpatterns_230) in + UTYPE (imm,rd,op1))))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (p00 = (vec_of_bits [B1,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))) then + (let (imm_19 :: 1 bits) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) in + (let (imm_18_13 :: 6 bits) = ((subrange_vec_dec v__175 (( 30 :: int)::ii) (( 25 :: int)::ii) :: 6 Word.word)) in + (let (imm_12_9 :: 4 bits) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 21 :: int)::ii) :: 4 Word.word)) in + (let (imm_8 :: 1 bits) = ((subrange_vec_dec v__175 (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word)) in + (let (imm_7_0 :: 8 bits) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 12 :: int)::ii) :: 8 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RISCV_JAL ((concat_vec imm_19 + ((concat_vec imm_7_0 + ((concat_vec imm_8 + ((concat_vec imm_18_13 + ((concat_vec imm_12_9 (vec_of_bits [B0] :: 1 Word.word) :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 20 Word.word)) + :: 21 Word.word),rd))))))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((p10 = (vec_of_bits [B1,B1,B0,B0,B1,B1,B1] :: 7 Word.word)))) \<and> (((p00 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))))))) then + (let (imm :: 12 Word.word) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RISCV_JALR (imm,rs1,rd)))) + else if ((let mappingpatterns_240 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p00 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((encdec_bop_backwards_matches mappingpatterns_240)) \<and> (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word)))))))) then + (let (imm7_6 :: 1 bits) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word)) in + (let (imm7_5_0 :: 6 bits) = ((subrange_vec_dec v__175 (( 30 :: int)::ii) (( 25 :: int)::ii) :: 6 Word.word)) in + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_240 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let (imm5_4_1 :: 4 bits) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 8 :: int)::ii) :: 4 Word.word)) in + (let (imm5_0 :: 1 bits) = ((subrange_vec_dec v__175 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in + (let op1 = (encdec_bop_backwards mappingpatterns_240) in + BTYPE ((concat_vec imm7_6 + ((concat_vec imm5_0 + ((concat_vec imm7_5_0 + ((concat_vec imm5_4_1 (vec_of_bits [B0] :: 1 Word.word) :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,op1))))))))) + else if ((let mappingpatterns_250 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p00 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((encdec_iop_backwards_matches mappingpatterns_250)) \<and> (((p00 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))))))) then + (let (imm :: 12 Word.word) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_250 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let op1 = (encdec_iop_backwards mappingpatterns_250) in + ITYPE (imm,rs1,rd,op1)))))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))) then + (let (shamt :: 6 Word.word) = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + SHIFTIOP (shamt,rs1,rd,RISCV_SLLI)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))) then + (let (shamt :: 6 Word.word) = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + SHIFTIOP (shamt,rs1,rd,RISCV_SRLI)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word))))))))) then + (let (shamt :: 6 Word.word) = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + SHIFTIOP (shamt,rs1,rd,RISCV_SRAI)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPE (rs2,rs1,rd,RISCV_ADD)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPE (rs2,rs1,rd,RISCV_SUB)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPE (rs2,rs1,rd,RISCV_SLL)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPE (rs2,rs1,rd,RISCV_SLT)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B1,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPE (rs2,rs1,rd,RISCV_SLTU)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPE (rs2,rs1,rd,RISCV_XOR)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPE (rs2,rs1,rd,RISCV_SRL)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPE (rs2,rs1,rd,RISCV_SRA)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPE (rs2,rs1,rd,RISCV_OR)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPE (rs2,rs1,rd,RISCV_AND)))) + else if ((let mappingpatterns_260 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_270 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let p00 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((size_bits_backwards_matches mappingpatterns_270)) \<and> ((bool_bits_backwards_matches mappingpatterns_260))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))))) then + (let (imm :: 12 Word.word) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_260 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_270 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let size1 = (size_bits_backwards mappingpatterns_270) in + (let is_unsigned = (bool_bits_backwards mappingpatterns_260) in + LOAD (imm,rs1,rd,is_unsigned,size1,False,False)))))))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_280 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((size_bits_backwards_matches mappingpatterns_280)) \<and> (((p10 = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0] :: 1 Word.word))))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_280 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let size1 = (size_bits_backwards mappingpatterns_280) in + STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,size1,False,False))))))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((p10 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p00 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))))))) then + (let (imm :: 12 Word.word) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + ADDIW (imm,rs1,rd)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + SHIFTW (shamt,rs1,rd,RISCV_SLLI)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + SHIFTW (shamt,rs1,rd,RISCV_SRLI)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (shamt :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + SHIFTW (shamt,rs1,rd,RISCV_SRAI)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPEW (rs2,rs1,rd,RISCV_ADDW)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPEW (rs2,rs1,rd,RISCV_SUBW)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPEW (rs2,rs1,rd,RISCV_SLLW)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPEW (rs2,rs1,rd,RISCV_SRLW)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + RTYPEW (rs2,rs1,rd,RISCV_SRAW)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (mappingpatterns_290 :: 3 bits) = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((encdec_mul_op_backwards_matches mappingpatterns_290)) \<and> (((p10 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (mappingpatterns_290 :: 3 bits) = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (high, signed1, signed2) = (encdec_mul_op_backwards mappingpatterns_290) in + MUL (rs2,rs1,rd,high,signed1,signed2)))))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) in + (let mappingpatterns_300 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_300)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_300 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let s = (bool_not_bits_backwards mappingpatterns_300) in + DIV (rs2,rs1,rd,s)))))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) in + (let mappingpatterns_310 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_310)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_310 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let s = (bool_not_bits_backwards mappingpatterns_310) in + REM (rs2,rs1,rd,s)))))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + MULW (rs2,rs1,rd)))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) in + (let mappingpatterns_320 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_320)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_320 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let s = (bool_not_bits_backwards mappingpatterns_320) in + DIVW (rs2,rs1,rd,s)))))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) in + (let mappingpatterns_330 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_330)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_330 = ((subrange_vec_dec v__175 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let s = (bool_not_bits_backwards mappingpatterns_330) in + REMW (rs2,rs1,rd,s)))))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p30 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p40 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((p40 = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word))))))))))) then + (let (pred :: 4 Word.word) = ((subrange_vec_dec v__175 (( 27 :: int)::ii) (( 24 :: int)::ii) :: 4 Word.word)) in + (let (succ :: 4 Word.word) = ((subrange_vec_dec v__175 (( 23 :: int)::ii) (( 20 :: int)::ii) :: 4 Word.word)) in + FENCE (pred,succ))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p30 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p40 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((p40 = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))))))))))) then + FENCEI () + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p30 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p40 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((p40 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))))))))))) then + ECALL () + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p30 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p40 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p50 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((((((((((((p50 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p40)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p30 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p20)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0] :: 7 Word.word)))))))))))) then + MRET () + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p30 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p40 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p50 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((((((((((((p50 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p40)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p30 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p20)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0] :: 7 Word.word)))))))))))) then + SRET () + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p30 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p40 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((p40 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word))))))))))) then + EBREAK () + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p30 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p40 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((p40 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word))))))))))) then + WFI () + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p30 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((((((p30 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p20)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + SFENCE_VMA (rs1,rs2))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_340 = ((subrange_vec_dec v__175 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_350 = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_360 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let p30 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((((((((((((((size_bits_backwards_matches mappingpatterns_360)) \<and> ((bool_bits_backwards_matches mappingpatterns_350))))) \<and> ((bool_bits_backwards_matches mappingpatterns_340))))) \<and> (((p30 = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))) \<and> (((p20 = (vec_of_bits [B0] :: 1 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))))))))))))))) then + (let mappingpatterns_340 = ((subrange_vec_dec v__175 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_350 = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_360 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let size1 = (size_bits_backwards mappingpatterns_360) in + (let rl = (bool_bits_backwards mappingpatterns_350) in + (let aq = (bool_bits_backwards mappingpatterns_340) in + LOADRES (aq,rl,rs1,size1,rd))))))))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_370 = ((subrange_vec_dec v__175 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_380 = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_390 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((((size_bits_backwards_matches mappingpatterns_390)) \<and> ((bool_bits_backwards_matches mappingpatterns_380))))) \<and> ((bool_bits_backwards_matches mappingpatterns_370))))) \<and> (((p20 = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B0] :: 1 Word.word))))))) \<and> (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))))))))))) then + (let mappingpatterns_370 = ((subrange_vec_dec v__175 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_380 = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_390 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let size1 = (size_bits_backwards mappingpatterns_390) in + (let rl = (bool_bits_backwards mappingpatterns_380) in + (let aq = (bool_bits_backwards mappingpatterns_370) in + STORECON (aq,rl,rs2,rs1,size1,rd)))))))))) + else if ((let mappingpatterns_400 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_410 = ((subrange_vec_dec v__175 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_420 = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in + (let p00 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_430 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((((size_bits_backwards_matches mappingpatterns_430)) \<and> ((bool_bits_backwards_matches mappingpatterns_420))))) \<and> ((bool_bits_backwards_matches mappingpatterns_410))))) \<and> ((encdec_amoop_backwards_matches mappingpatterns_400))))) \<and> (((p10 = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0] :: 1 Word.word)))))))))))) then + (let mappingpatterns_400 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_410 = ((subrange_vec_dec v__175 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_420 = ((subrange_vec_dec v__175 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in + (let (rs2 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_430 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let size1 = (size_bits_backwards mappingpatterns_430) in + (let rl = (bool_bits_backwards mappingpatterns_420) in + (let aq = (bool_bits_backwards mappingpatterns_410) in + (let op1 = (encdec_amoop_backwards mappingpatterns_400) in + AMO (op1,aq,rl,rs2,rs1,size1,rd)))))))))))) + else if ((let mappingpatterns_440 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_450 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let p00 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((encdec_csrop_backwards_matches mappingpatterns_450)) \<and> ((bool_bits_backwards_matches mappingpatterns_440))))) \<and> (((p00 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))))) then + (let (csr :: 12 Word.word) = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: 5 Word.word) = ((subrange_vec_dec v__175 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_440 = ((subrange_vec_dec v__175 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_450 = ((subrange_vec_dec v__175 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let (rd :: 5 Word.word) = ((subrange_vec_dec v__175 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let op1 = (encdec_csrop_backwards mappingpatterns_450) in + (let is_imm = (bool_bits_backwards mappingpatterns_440) in + CSR (csr,rs1,rd,is_imm,op1)))))))) + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in + (let p30 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let p40 = ((subrange_vec_dec v__175 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let p50 = ((subrange_vec_dec v__175 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + ((((((((((((((((p50 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((p40 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) \<and> (((p30 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) \<and> (((p20 = (vec_of_bits [B0] :: 1 Word.word))))))) \<and> (((p10 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) \<and> (((p00 = (vec_of_bits [B1,B1,B1,B1,B1,B0,B1,B0,B1,B1,B0,B1,B1,B1,B1,B0] :: 16 Word.word)))))))))))) + then + STOP_FETCHING () + else if ((let p00 = ((subrange_vec_dec v__175 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) in + (let p10 = ((subrange_vec_dec v__175 (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) in + (let p20 = ((subrange_vec_dec v__175 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in + (let p30 = ((subrange_vec_dec v__175 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let p40 = ((subrange_vec_dec v__175 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let p50 = ((subrange_vec_dec v__175 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + ((((((((((((((((p50 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((p40 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) \<and> (((p30 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) \<and> (((p20 = (vec_of_bits [B0] :: 1 Word.word))))))) \<and> (((p10 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) \<and> (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1,B1,B1,B1,B0] :: 16 Word.word)))))))))))) + then + THREAD_START () + else ILLEGAL v__175))" + + +(*val encdec_forwards_matches : ast -> bool*) + +fun encdec_forwards_matches :: " ast \<Rightarrow> bool " where + " encdec_forwards_matches (UTYPE (imm,rd,op1)) = ( True )" +|" encdec_forwards_matches (RISCV_JAL (v__224,rd)) = ( + if ((let p00 = ((subrange_vec_dec v__224 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + (p00 = (vec_of_bits [B0] :: 1 Word.word)))) then + True + else + (let g__17 = (RISCV_JAL (v__224,rd)) in + False))" +|" encdec_forwards_matches (RISCV_JALR (imm,rs1,rd)) = ( True )" +|" encdec_forwards_matches (BTYPE (v__225,rs2,rs1,op1)) = ( + if ((let p00 = ((subrange_vec_dec v__225 (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word)) in + (p00 = (vec_of_bits [B0] :: 1 Word.word)))) then + True + else + (let g__17 = (BTYPE (v__225,rs2,rs1,op1)) in + False))" +|" encdec_forwards_matches (ITYPE (imm,rs1,rd,op1)) = ( True )" +|" encdec_forwards_matches (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI)) = ( True )" +|" encdec_forwards_matches (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI)) = ( True )" +|" encdec_forwards_matches (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI)) = ( True )" +|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_ADD)) = ( True )" +|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_SUB)) = ( True )" +|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_SLL)) = ( True )" +|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_SLT)) = ( True )" +|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_SLTU)) = ( True )" +|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_XOR)) = ( True )" +|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_SRL)) = ( True )" +|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_SRA)) = ( True )" +|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_OR)) = ( True )" +|" encdec_forwards_matches (RTYPE (rs2,rs1,rd,RISCV_AND)) = ( True )" +|" encdec_forwards_matches (LOAD (imm,rs1,rd,is_unsigned,size1,False,False)) = ( True )" +|" encdec_forwards_matches (STORE (v__226,rs2,rs1,size1,False,False)) = ( True )" +|" encdec_forwards_matches (ADDIW (imm,rs1,rd)) = ( True )" +|" encdec_forwards_matches (SHIFTW (shamt,rs1,rd,RISCV_SLLI)) = ( True )" +|" encdec_forwards_matches (SHIFTW (shamt,rs1,rd,RISCV_SRLI)) = ( True )" +|" encdec_forwards_matches (SHIFTW (shamt,rs1,rd,RISCV_SRAI)) = ( True )" +|" encdec_forwards_matches (RTYPEW (rs2,rs1,rd,RISCV_ADDW)) = ( True )" +|" encdec_forwards_matches (RTYPEW (rs2,rs1,rd,RISCV_SUBW)) = ( True )" +|" encdec_forwards_matches (RTYPEW (rs2,rs1,rd,RISCV_SLLW)) = ( True )" +|" encdec_forwards_matches (RTYPEW (rs2,rs1,rd,RISCV_SRLW)) = ( True )" +|" encdec_forwards_matches (RTYPEW (rs2,rs1,rd,RISCV_SRAW)) = ( True )" +|" encdec_forwards_matches (MUL (rs2,rs1,rd,high,signed1,signed2)) = ( True )" +|" encdec_forwards_matches (DIV (rs2,rs1,rd,s)) = ( True )" +|" encdec_forwards_matches (REM (rs2,rs1,rd,s)) = ( True )" +|" encdec_forwards_matches (MULW (rs2,rs1,rd)) = ( True )" +|" encdec_forwards_matches (DIVW (rs2,rs1,rd,s)) = ( True )" +|" encdec_forwards_matches (REMW (rs2,rs1,rd,s)) = ( True )" +|" encdec_forwards_matches (FENCE (pred,succ)) = ( True )" +|" encdec_forwards_matches (FENCEI (_)) = ( True )" +|" encdec_forwards_matches (ECALL (_)) = ( True )" +|" encdec_forwards_matches (MRET (_)) = ( True )" +|" encdec_forwards_matches (SRET (_)) = ( True )" +|" encdec_forwards_matches (EBREAK (_)) = ( True )" +|" encdec_forwards_matches (WFI (_)) = ( True )" +|" encdec_forwards_matches (SFENCE_VMA (rs1,rs2)) = ( True )" +|" encdec_forwards_matches (LOADRES (aq,rl,rs1,size1,rd)) = ( True )" +|" encdec_forwards_matches (STORECON (aq,rl,rs2,rs1,size1,rd)) = ( True )" +|" encdec_forwards_matches (AMO (op1,aq,rl,rs2,rs1,size1,rd)) = ( True )" +|" encdec_forwards_matches (CSR (csr,rs1,rd,is_imm,op1)) = ( True )" +|" encdec_forwards_matches (STOP_FETCHING (_)) = ( True )" +|" encdec_forwards_matches (THREAD_START (_)) = ( True )" +|" encdec_forwards_matches (ILLEGAL (s)) = ( True )" +|" encdec_forwards_matches g__17 = ( False )" + + +(*val encdec_backwards_matches : mword ty32 -> bool*) + +definition encdec_backwards_matches :: "(32)Word.word \<Rightarrow> bool " where + " encdec_backwards_matches arg0 = ( + (let v__227 = arg0 in + if ((let mappingpatterns_00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + encdec_uop_backwards_matches mappingpatterns_00)) then + (let mappingpatterns_00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (let op1 = (encdec_uop_backwards mappingpatterns_00) in + True)) + else if ((let p00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (p00 = (vec_of_bits [B1,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((p10 = (vec_of_bits [B1,B1,B0,B0,B1,B1,B1] :: 7 Word.word)))) \<and> (((p00 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))))))) then + True + else if ((let mappingpatterns_10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((encdec_bop_backwards_matches mappingpatterns_10)) \<and> (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word)))))))) then + (let mappingpatterns_10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let op1 = (encdec_bop_backwards mappingpatterns_10) in + True)) + else if ((let mappingpatterns_20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((encdec_iop_backwards_matches mappingpatterns_20)) \<and> (((p00 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))))))) then + (let mappingpatterns_20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let op1 = (encdec_iop_backwards mappingpatterns_20) in + True)) + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B1,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let mappingpatterns_30 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_40 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let p00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((size_bits_backwards_matches mappingpatterns_40)) \<and> ((bool_bits_backwards_matches mappingpatterns_30))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))))) then + (let mappingpatterns_30 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_40 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let size1 = (size_bits_backwards mappingpatterns_40) in + (let is_unsigned = (bool_bits_backwards mappingpatterns_30) in + True)))) + else if ((let p00 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_50 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((size_bits_backwards_matches mappingpatterns_50)) \<and> (((p10 = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0] :: 1 Word.word))))))))) then + (let mappingpatterns_50 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let size1 = (size_bits_backwards mappingpatterns_50) in + True)) + else if ((let p00 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((p10 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p00 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (mappingpatterns_60 :: 3 bits) = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((encdec_mul_op_backwards_matches mappingpatterns_60)) \<and> (((p10 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word))))))))) then + (let (mappingpatterns_60 :: 3 bits) = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let (high, signed1, signed2) = (encdec_mul_op_backwards mappingpatterns_60) in + True)) + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) in + (let mappingpatterns_70 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_70)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))))))))) then + (let mappingpatterns_70 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let s = (bool_not_bits_backwards mappingpatterns_70) in + True)) + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) in + (let mappingpatterns_80 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_80)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))))))))) then + (let mappingpatterns_80 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let s = (bool_not_bits_backwards mappingpatterns_80) in + True)) + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))) \<and> (((p10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) in + (let mappingpatterns_90 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_90)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B0] :: 2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))))))))) then + (let mappingpatterns_90 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let s = (bool_not_bits_backwards mappingpatterns_90) in + True)) + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word)) in + (let mappingpatterns_100 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((bool_not_bits_backwards_matches mappingpatterns_100)) \<and> (((p20 = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B1,B1] :: 2 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))))))))) then + (let mappingpatterns_100 = ((subrange_vec_dec v__227 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let s = (bool_not_bits_backwards mappingpatterns_100) in + True)) + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p30 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p40 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((p40 = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word))))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p30 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p40 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((p40 = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p30 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p40 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((p40 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p30 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p40 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p50 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((((((((((((p50 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p40)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p30 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p20)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0] :: 7 Word.word)))))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p30 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p40 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p50 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((((((((((((p50 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p40)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p30 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p20)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0] :: 7 Word.word)))))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p30 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p40 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((p40 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word))))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p30 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p40 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((p40 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p30)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p20 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word))))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let p30 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((((((p30 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))) \<and> (((((regbits_to_regno p20)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((p10 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B1] :: 7 Word.word)))))))))) then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_110 = ((subrange_vec_dec v__227 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_120 = ((subrange_vec_dec v__227 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_130 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let p30 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((((((((((((((size_bits_backwards_matches mappingpatterns_130)) \<and> ((bool_bits_backwards_matches mappingpatterns_120))))) \<and> ((bool_bits_backwards_matches mappingpatterns_110))))) \<and> (((p30 = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))) \<and> (((p20 = (vec_of_bits [B0] :: 1 Word.word))))))) \<and> (((((regbits_to_regno p10)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) \<and> (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))))))))))))))) then + (let mappingpatterns_110 = ((subrange_vec_dec v__227 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_120 = ((subrange_vec_dec v__227 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_130 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let size1 = (size_bits_backwards mappingpatterns_130) in + (let rl = (bool_bits_backwards mappingpatterns_120) in + (let aq = (bool_bits_backwards mappingpatterns_110) in + True)))))) + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_140 = ((subrange_vec_dec v__227 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_150 = ((subrange_vec_dec v__227 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_160 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((((size_bits_backwards_matches mappingpatterns_160)) \<and> ((bool_bits_backwards_matches mappingpatterns_150))))) \<and> ((bool_bits_backwards_matches mappingpatterns_140))))) \<and> (((p20 = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))) \<and> (((p10 = (vec_of_bits [B0] :: 1 Word.word))))))) \<and> (((((regbits_to_regno p00)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))))))))))) then + (let mappingpatterns_140 = ((subrange_vec_dec v__227 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_150 = ((subrange_vec_dec v__227 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_160 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let size1 = (size_bits_backwards mappingpatterns_160) in + (let rl = (bool_bits_backwards mappingpatterns_150) in + (let aq = (bool_bits_backwards mappingpatterns_140) in + True)))))) + else if ((let mappingpatterns_170 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_180 = ((subrange_vec_dec v__227 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_190 = ((subrange_vec_dec v__227 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in + (let p00 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_200 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + (((((((((((((((size_bits_backwards_matches mappingpatterns_200)) \<and> ((bool_bits_backwards_matches mappingpatterns_190))))) \<and> ((bool_bits_backwards_matches mappingpatterns_180))))) \<and> ((encdec_amoop_backwards_matches mappingpatterns_170))))) \<and> (((p10 = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))) \<and> (((p00 = (vec_of_bits [B0] :: 1 Word.word)))))))))))) then + (let mappingpatterns_170 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)) in + (let mappingpatterns_180 = ((subrange_vec_dec v__227 (( 26 :: int)::ii) (( 26 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_190 = ((subrange_vec_dec v__227 (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_200 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let size1 = (size_bits_backwards mappingpatterns_200) in + (let rl = (bool_bits_backwards mappingpatterns_190) in + (let aq = (bool_bits_backwards mappingpatterns_180) in + (let op1 = (encdec_amoop_backwards mappingpatterns_170) in + True)))))))) + else if ((let mappingpatterns_210 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_220 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let p00 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) in + ((((((encdec_csrop_backwards_matches mappingpatterns_220)) \<and> ((bool_bits_backwards_matches mappingpatterns_210))))) \<and> (((p00 = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))))) then + (let mappingpatterns_210 = ((subrange_vec_dec v__227 (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word)) in + (let mappingpatterns_220 = ((subrange_vec_dec v__227 (( 13 :: int)::ii) (( 12 :: int)::ii) :: 2 Word.word)) in + (let op1 = (encdec_csrop_backwards mappingpatterns_220) in + (let is_imm = (bool_bits_backwards mappingpatterns_210) in + True)))) + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in + (let p30 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let p40 = ((subrange_vec_dec v__227 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let p50 = ((subrange_vec_dec v__227 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + ((((((((((((((((p50 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((p40 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) \<and> (((p30 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) \<and> (((p20 = (vec_of_bits [B0] :: 1 Word.word))))))) \<and> (((p10 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) \<and> (((p00 = (vec_of_bits [B1,B1,B1,B1,B1,B0,B1,B0,B1,B1,B0,B1,B1,B1,B1,B0] :: 16 Word.word)))))))))))) + then + True + else if ((let p00 = ((subrange_vec_dec v__227 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) in + (let p10 = ((subrange_vec_dec v__227 (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) in + (let p20 = ((subrange_vec_dec v__227 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in + (let p30 = ((subrange_vec_dec v__227 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let p40 = ((subrange_vec_dec v__227 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let p50 = ((subrange_vec_dec v__227 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + ((((((((((((((((p50 = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((p40 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) \<and> (((p30 = (vec_of_bits [B0,B0] :: 2 Word.word))))))) \<and> (((p20 = (vec_of_bits [B0] :: 1 Word.word))))))) \<and> (((p10 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) \<and> (((p00 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1,B1,B1,B1,B0] :: 16 Word.word)))))))))))) + then + True + else True))" + + fun print_insn :: " ast \<Rightarrow> string " where - " print_insn (UTYPE (imm,rd,op1)) = ( - (case op1 of - RISCV_LUI => - (op@) (''lui '') - (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))) - | RISCV_AUIPC => - (op@) (''auipc '') - (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))) - ))" -|" print_insn (RISCV_JAL (imm,rd)) = ( - (op@) (''jal '') - (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))))" -|" print_insn (RISCV_JALR (imm,rs1,rd)) = ( - (op@) (''jalr '') - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm)))))))))))" -|" print_insn (BTYPE (imm,rs2,rs1,op1)) = ( - (let (insn :: string) = - ((case op1 of - RISCV_BEQ => (''beq '') - | RISCV_BNE => (''bne '') - | RISCV_BLT => (''blt '') - | RISCV_BGE => (''bge '') - | RISCV_BLTU => (''bltu '') - | RISCV_BGEU => (''bgeu '') - )) in - (op@) insn - (((op@) ((reg_name_abi rs1)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs2)) (((op@) ('', '') ((string_of_vec imm))))))))))))" -|" print_insn (ITYPE (imm,rs1,rd,op1)) = ( - (let (insn :: string) = - ((case op1 of - RISCV_ADDI => (''addi '') - | RISCV_SLTI => (''slti '') - | RISCV_SLTIU => (''sltiu '') - | RISCV_XORI => (''xori '') - | RISCV_ORI => (''ori '') - | RISCV_ANDI => (''andi '') - )) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm))))))))))))" -|" print_insn (SHIFTIOP (shamt,rs1,rd,op1)) = ( - (let (insn :: string) = - ((case op1 of RISCV_SLLI => (''slli '') | RISCV_SRLI => (''srli '') | RISCV_SRAI => (''srai '') )) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec shamt))))))))))))" -|" print_insn (RTYPE (rs2,rs1,rd,op1)) = ( - (let (insn :: string) = - ((case op1 of - RISCV_ADD => (''add '') - | RISCV_SUB => (''sub '') - | RISCV_SLL => (''sll '') - | RISCV_SLT => (''slt '') - | RISCV_SLTU => (''sltu '') - | RISCV_XOR => (''xor '') - | RISCV_SRL => (''srl '') - | RISCV_SRA => (''sra '') - | RISCV_OR => (''or '') - | RISCV_AND => (''and '') - )) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" -|" print_insn (LOAD (imm,rs1,rd,is_unsigned,width,aq,rl)) = ( - (let (insn :: string) = - ((case (width, is_unsigned) of - (BYTE, False) => (''lb '') - | (BYTE, True) => (''lbu '') - | (HALF, False) => (''lh '') - | (HALF, True) => (''lhu '') - | (WORD, False) => (''lw '') - | (WORD, True) => (''lwu '') - | (DOUBLE, False) => (''ld '') - | (DOUBLE, True) => (''ldu '') - )) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm))))))))))))" -|" print_insn (STORE (imm,rs2,rs1,width,aq,rl)) = ( - (let (insn :: string) = - ((case width of - BYTE => (''sb '') - | HALF => (''sh '') - | WORD => (''sw '') - | DOUBLE => (''sd '') - )) in - (op@) insn - (((op@) ((reg_name_abi rs2)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm))))))))))))" -|" print_insn (ADDIW (imm,rs1,rd)) = ( - (op@) (''addiw '') - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm)))))))))))" -|" print_insn (SHIFTW (shamt,rs1,rd,op1)) = ( - (let (insn :: string) = - ((case op1 of RISCV_SLLI => (''slli '') | RISCV_SRLI => (''srli '') | RISCV_SRAI => (''srai '') )) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec shamt))))))))))))" -|" print_insn (RTYPEW (rs2,rs1,rd,op1)) = ( - (let (insn :: string) = - ((case op1 of - RISCV_ADDW => (''addw '') - | RISCV_SUBW => (''subw '') - | RISCV_SLLW => (''sllw '') - | RISCV_SRLW => (''srlw '') - | RISCV_SRAW => (''sraw '') - )) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" -|" print_insn (MUL (rs2,rs1,rd,high,signed1,signed2)) = ( - (let (insn :: string) = - ((case (high, signed1, signed2) of - (False, True, True) => (''mul '') - | (True, True, True) => (''mulh '') - | (True, True, False) => (''mulhsu '') - | (True, False, False) => (''mulhu'') - )) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" -|" print_insn (DIV (rs2,rs1,rd,s)) = ( - (let (insn :: string) = (if s then (''div '') else (''divu '')) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" -|" print_insn (REM (rs2,rs1,rd,s)) = ( - (let (insn :: string) = (if s then (''rem '') else (''remu '')) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" -|" print_insn (MULW (rs2,rs1,rd)) = ( - (op@) (''mulw '') - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2)))))))))))" -|" print_insn (DIVW (rs2,rs1,rd,s)) = ( - (let (insn :: string) = (if s then (''divw '') else (''divuw '')) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" -|" print_insn (REMW (rs2,rs1,rd,s)) = ( - (let (insn :: string) = (if s then (''remw '') else (''remuw '')) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" -|" print_insn (FENCE (pred,succ)) = ( (''fence''))" -|" print_insn (FENCEI (g__93)) = ( (''fence.i''))" -|" print_insn (ECALL (g__94)) = ( (''ecall''))" -|" print_insn (MRET (g__95)) = ( (''mret''))" -|" print_insn (SRET (g__96)) = ( (''sret''))" -|" print_insn (EBREAK (g__97)) = ( (''ebreak''))" -|" print_insn (WFI (g__98)) = ( (''wfi''))" -|" print_insn (SFENCE_VMA (rs1,rs2)) = ( - (op@) (''sfence.vma '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2)))))))" -|" print_insn (LOADRES (aq,rl,rs1,width,rd)) = ( - (let (insn :: string) = - ((case width of WORD => (''lr.w '') | DOUBLE => (''lr.d '') | _ => (''lr.bad '') )) in - (op@) insn - (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((reg_name_abi rs1))))))))" -|" print_insn (STORECON (aq,rl,rs2,rs1,width,rd)) = ( - (let (insn :: string) = - ((case width of WORD => (''sc.w '') | DOUBLE => (''sc.d '') | _ => (''sc.bad '') )) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" -|" print_insn (AMO (op1,aq,rl,rs2,rs1,width,rd)) = ( - (let (insn :: string) = - ((case (op1, width) of - (AMOSWAP, WORD) => (''amoswap.w '') - | (AMOADD, WORD) => (''amoadd.w '') - | (AMOXOR, WORD) => (''amoxor.w '') - | (AMOAND, WORD) => (''amoand.w '') - | (AMOOR, WORD) => (''amoor.w '') - | (AMOMIN, WORD) => (''amomin.w '') - | (AMOMAX, WORD) => (''amomax.w '') - | (AMOMINU, WORD) => (''amominu.w '') - | (AMOMAXU, WORD) => (''amomaxu.w '') - | (AMOSWAP, DOUBLE) => (''amoswap.d '') - | (AMOADD, DOUBLE) => (''amoadd.d '') - | (AMOXOR, DOUBLE) => (''amoxor.d '') - | (AMOAND, DOUBLE) => (''amoand.d '') - | (AMOOR, DOUBLE) => (''amoor.d '') - | (AMOMIN, DOUBLE) => (''amomin.d '') - | (AMOMAX, DOUBLE) => (''amomax.d '') - | (AMOMINU, DOUBLE) => (''amominu.d '') - | (AMOMAXU, DOUBLE) => (''amomaxu.d '') - | (_, _) => (''amo.bad '') - )) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') - (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" -|" print_insn (CSR (csr,rs1,rd,is_imm,op1)) = ( - (let (insn :: string) = - ((case (op1, is_imm) of - (CSRRW, True) => (''csrrwi '') - | (CSRRW, False) => (''csrrw '') - | (CSRRS, True) => (''csrrsi '') - | (CSRRS, False) => (''csrrs '') - | (CSRRC, True) => (''csrrci '') - | (CSRRC, False) => (''csrrc '') - )) in - (let (rs1_str :: string) = (if is_imm then string_of_vec rs1 else reg_name_abi rs1) in - (op@) insn - (((op@) ((reg_name_abi rd)) - (((op@) ('', '') (((op@) rs1_str (((op@) ('', '') ((csr_name csr)))))))))))))" -|" print_insn (NOP (g__99)) = ( (''nop''))" -|" print_insn (ILLEGAL (g__100)) = ( (''illegal''))" + " print_insn (NOP (g__13)) = ( (''nop''))" |" print_insn (C_ADDI4SPN (rdc,nzimm)) = ( (op@) (''c.addi4spn '') (((op@) ((reg_name_abi ((creg2reg_bits rdc :: 5 Word.word)))) - (((op@) ('', '') ((string_of_vec nzimm)))))))" + (((op@) ('', '') ((string_of_bits nzimm)))))))" |" print_insn (C_LW (uimm,rsc,rdc)) = ( (op@) (''c.lw '') (((op@) ((reg_name_abi ((creg2reg_bits rdc :: 5 Word.word)))) (((op@) ('', '') (((op@) ((reg_name_abi ((creg2reg_bits rsc :: 5 Word.word)))) - (((op@) ('', '') ((string_of_vec uimm)))))))))))" + (((op@) ('', '') ((string_of_bits uimm)))))))))))" |" print_insn (C_LD (uimm,rsc,rdc)) = ( (op@) (''c.ld '') (((op@) ((reg_name_abi ((creg2reg_bits rdc :: 5 Word.word)))) (((op@) ('', '') (((op@) ((reg_name_abi ((creg2reg_bits rsc :: 5 Word.word)))) - (((op@) ('', '') ((string_of_vec uimm)))))))))))" + (((op@) ('', '') ((string_of_bits uimm)))))))))))" |" print_insn (C_SW (uimm,rsc1,rsc2)) = ( (op@) (''c.sw '') (((op@) ((reg_name_abi ((creg2reg_bits rsc1 :: 5 Word.word)))) (((op@) ('', '') (((op@) ((reg_name_abi ((creg2reg_bits rsc2 :: 5 Word.word)))) - (((op@) ('', '') ((string_of_vec uimm)))))))))))" + (((op@) ('', '') ((string_of_bits uimm)))))))))))" |" print_insn (C_SD (uimm,rsc1,rsc2)) = ( (op@) (''c.sd '') (((op@) ((reg_name_abi ((creg2reg_bits rsc1 :: 5 Word.word)))) (((op@) ('', '') (((op@) ((reg_name_abi ((creg2reg_bits rsc2 :: 5 Word.word)))) - (((op@) ('', '') ((string_of_vec uimm)))))))))))" + (((op@) ('', '') ((string_of_bits uimm)))))))))))" |" print_insn (C_ADDI (nzi,rsd)) = ( (op@) (''c.addi '') - (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_vec nzi)))))))" -|" print_insn (C_JAL (imm)) = ( (op@) (''c.jal '') ((string_of_vec imm)))" + (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_bits nzi)))))))" +|" print_insn (C_JAL (imm)) = ( (op@) (''c.jal '') ((string_of_bits imm)))" |" print_insn (C_ADDIW (imm,rsd)) = ( (op@) (''c.addiw '') - (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_vec imm)))))))" + (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_bits imm)))))))" |" print_insn (C_LI (imm,rd)) = ( (op@) (''c.li '') - (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))))" -|" print_insn (C_ADDI16SP (imm)) = ( (op@) (''c.addi16sp '') ((string_of_vec imm)))" + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_bits imm)))))))" +|" print_insn (C_ADDI16SP (imm)) = ( (op@) (''c.addi16sp '') ((string_of_bits imm)))" |" print_insn (C_LUI (imm,rd)) = ( (op@) (''c.lui '') - (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))))" + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_bits imm)))))))" |" print_insn (C_SRLI (shamt,rsd)) = ( (op@) (''c.srli '') (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) - (((op@) ('', '') ((string_of_vec shamt)))))))" + (((op@) ('', '') ((string_of_bits shamt)))))))" |" print_insn (C_SRAI (shamt,rsd)) = ( (op@) (''c.srai '') (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) - (((op@) ('', '') ((string_of_vec shamt)))))))" + (((op@) ('', '') ((string_of_bits shamt)))))))" |" print_insn (C_ANDI (imm,rsd)) = ( (op@) (''c.andi '') (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) - (((op@) ('', '') ((string_of_vec imm)))))))" + (((op@) ('', '') ((string_of_bits imm)))))))" |" print_insn (C_SUB (rsd,rs2)) = ( (op@) (''c.sub '') (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) @@ -7417,30 +23856,30 @@ fun print_insn :: " ast \<Rightarrow> string " where (op@) (''c.addw '') (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" -|" print_insn (C_J (imm)) = ( (op@) (''c.j '') ((string_of_vec imm)))" +|" print_insn (C_J (imm)) = ( (op@) (''c.j '') ((string_of_bits imm)))" |" print_insn (C_BEQZ (imm,rs)) = ( (op@) (''c.beqz '') (((op@) ((reg_name_abi ((creg2reg_bits rs :: 5 Word.word)))) - (((op@) ('', '') ((string_of_vec imm)))))))" + (((op@) ('', '') ((string_of_bits imm)))))))" |" print_insn (C_BNEZ (imm,rs)) = ( (op@) (''c.bnez '') (((op@) ((reg_name_abi ((creg2reg_bits rs :: 5 Word.word)))) - (((op@) ('', '') ((string_of_vec imm)))))))" + (((op@) ('', '') ((string_of_bits imm)))))))" |" print_insn (C_SLLI (shamt,rsd)) = ( (op@) (''c.slli '') - (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_vec shamt)))))))" + (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_bits shamt)))))))" |" print_insn (C_LWSP (uimm,rd)) = ( (op@) (''c.lwsp '') - (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))" + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_bits uimm)))))))" |" print_insn (C_LDSP (uimm,rd)) = ( (op@) (''c.ldsp '') - (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))" + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_bits uimm)))))))" |" print_insn (C_SWSP (uimm,rd)) = ( (op@) (''c.swsp '') - (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))" + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_bits uimm)))))))" |" print_insn (C_SDSP (uimm,rd)) = ( (op@) (''c.sdsp '') - (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))" + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_bits uimm)))))))" |" print_insn (C_JR (rs1)) = ( (op@) (''c.jr '') ((reg_name_abi rs1)))" |" print_insn (C_JALR (rs1)) = ( (op@) (''c.jalr '') ((reg_name_abi rs1)))" |" print_insn (C_MV (rd,rs2)) = ( @@ -7449,6 +23888,15 @@ fun print_insn :: " ast \<Rightarrow> string " where |" print_insn (C_ADD (rsd,rs2)) = ( (op@) (''c.add '') (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((reg_name_abi rs2)))))))" +|" print_insn (STOP_FETCHING (g__14)) = ( (''stop_fetching''))" +|" print_insn (THREAD_START (g__15)) = ( (''thread_start''))" +|" print_insn (ILLEGAL (s)) = ( (op@) (''illegal '') ((string_of_bits s)))" +|" print_insn (C_ILLEGAL (g__16)) = ( (''c.illegal''))" +|" print_insn insn = ( assembly_forwards insn )" + + +definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where + " decode bv = ( Some ((encdec_backwards bv)))" (*val isRVC : mword ty16 -> bool*) @@ -7505,77 +23953,554 @@ definition fetch :: " unit \<Rightarrow>((register_value),(FetchResult),(except )))))" -(*val step : unit -> M bool*) +(*val step : ii -> M (bool * bool)*) -definition step :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where - " step _ = ( - read_reg mip_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . - read_reg mie_ref \<bind> (\<lambda> (w__1 :: Minterrupts) . - read_reg mideleg_ref \<bind> (\<lambda> (w__2 :: Minterrupts) . - curInterrupt w__0 w__1 w__2 \<bind> (\<lambda> (w__3 :: ((InterruptType * Privilege))option) . - (case w__3 of +definition step :: " int \<Rightarrow>((register_value),(bool*bool),(exception))monad " where + " step step_no = ( + read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . + read_reg mip_ref \<bind> (\<lambda> (w__1 :: Minterrupts) . + read_reg mie_ref \<bind> (\<lambda> (w__2 :: Minterrupts) . + read_reg mideleg_ref \<bind> (\<lambda> (w__3 :: Minterrupts) . + curInterrupt w__0 w__1 w__2 w__3 \<bind> (\<lambda> (w__4 :: ((InterruptType * Privilege))option) . + (case w__4 of Some (intr,priv) => (let (_ :: unit) = (print_bits (''Handling interrupt: '') ((interruptType_to_bits intr :: 4 Word.word))) in - handle_interrupt intr priv \<then> return False) + handle_interrupt intr priv \<then> return (False, False)) | None => - fetch () \<bind> (\<lambda> (w__4 :: FetchResult) . - (case w__4 of - F_Error (e,addr) => handle_mem_exception addr e \<then> return False + fetch () \<bind> (\<lambda> (w__5 :: FetchResult) . + (case w__5 of + F_Error (e,addr) => handle_mem_exception addr e \<then> return (False, False) | F_RVC (h) => (case ((decodeCompressed h)) of None => - (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: xlenbits) . + read_reg cur_privilege_ref \<bind> (\<lambda> (w__6 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: xlenbits) . (let (_ :: unit) = - (prerr_endline - (((op@) (''PC: '') - (((op@) ((string_of_vec w__5)) - (((op@) ('' instr: '') - (((op@) ((string_of_vec h)) ('' : <no-decode>'')))))))))) in - handle_decode_exception ((EXTZ (( 64 :: int)::ii) h :: 64 Word.word)) \<then> return False)) + (print_endline + (((op@) (''['') + (((op@) ((stringFromInteger step_no)) + (((op@) (''] ['') + (((op@) ((privLevel_to_str w__6)) + (((op@) ('']: '') + (((op@) ((string_of_bits w__7)) + (((op@) ('' ('') + (((op@) ((string_of_bits h)) ('') <no-decode>'')))))))))))))))))) in + handle_decode_exception ((EXTZ (( 64 :: int)::ii) h :: 64 Word.word)) \<then> return (False, True)))) | Some (ast) => - (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: xlenbits) . + read_reg cur_privilege_ref \<bind> (\<lambda> (w__8 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: xlenbits) . (let (_ :: unit) = - (prerr_endline - (((op@) (''PC: '') - (((op@) ((string_of_vec w__6)) - (((op@) ('' instr: '') - (((op@) ((string_of_vec h)) - (((op@) ('' : '') ((print_insn ast))))))))))))) in - (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 Word.word) . - (write_reg nextPC_ref ((add_vec_int w__7 (( 2 :: int)::ii) :: 64 Word.word)) \<then> - execute ast) \<then> return True))) + (print_endline + (((op@) (''['') + (((op@) ((stringFromInteger step_no)) + (((op@) (''] ['') + (((op@) ((privLevel_to_str w__8)) + (((op@) ('']: '') + (((op@) ((string_of_bits w__9)) + (((op@) ('' ('') + (((op@) ((string_of_bits h)) + (((op@) ('') '') ((print_insn ast))))))))))))))))))))) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: 64 Word.word) . + (write_reg nextPC_ref ((add_vec_int w__10 (( 2 :: int)::ii) :: 64 Word.word)) \<then> + execute ast) \<bind> (\<lambda> (w__11 :: bool) . return (w__11, True)))))) ) | F_Base (w) => (case ((decode w)) of None => - (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: xlenbits) . + read_reg cur_privilege_ref \<bind> (\<lambda> (w__13 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: xlenbits) . (let (_ :: unit) = - (prerr_endline - (((op@) (''PC: '') - (((op@) ((string_of_vec w__9)) - (((op@) ('' instr: '') - (((op@) ((string_of_vec w)) ('' : <no-decode>'')))))))))) in - handle_decode_exception ((EXTZ (( 64 :: int)::ii) w :: 64 Word.word)) \<then> return False)) + (print_endline + (((op@) (''['') + (((op@) ((stringFromInteger step_no)) + (((op@) (''] ['') + (((op@) ((privLevel_to_str w__13)) + (((op@) ('']: '') + (((op@) ((string_of_bits w__14)) + (((op@) ('' ('') + (((op@) ((string_of_bits w)) ('') <no-decode>'')))))))))))))))))) in + handle_decode_exception ((EXTZ (( 64 :: int)::ii) w :: 64 Word.word)) \<then> return (False, True)))) | Some (ast) => - (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: xlenbits) . + read_reg cur_privilege_ref \<bind> (\<lambda> (w__15 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__16 :: xlenbits) . (let (_ :: unit) = - (prerr_endline - (((op@) (''PC: '') - (((op@) ((string_of_vec w__10)) - (((op@) ('' instr: '') - (((op@) ((string_of_vec w)) - (((op@) ('' : '') ((print_insn ast))))))))))))) in - (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 Word.word) . - (write_reg nextPC_ref ((add_vec_int w__11 (( 4 :: int)::ii) :: 64 Word.word)) \<then> - execute ast) \<then> return True))) + (print_endline + (((op@) (''['') + (((op@) ((stringFromInteger step_no)) + (((op@) (''] ['') + (((op@) ((privLevel_to_str w__15)) + (((op@) ('']: '') + (((op@) ((string_of_bits w__16)) + (((op@) ('' ('') + (((op@) ((string_of_bits w)) + (((op@) ('') '') ((print_insn ast))))))))))))))))))))) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 Word.word) . + (write_reg nextPC_ref ((add_vec_int w__17 (( 4 :: int)::ii) :: 64 Word.word)) \<then> + execute ast) \<bind> (\<lambda> (w__18 :: bool) . return (w__18, True)))))) ) )) - ))))))" + )))))))" + + +(*val loop : unit -> M unit*) + +definition loop :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " loop _ = ( + (let insns_per_tick = (plat_insns_per_tick () ) in + (let (i :: ii) = ((( 0 :: int)::ii)) in + (let (step_no :: ii) = ((( 0 :: int)::ii)) in + (whileM (i, step_no) + (\<lambda> varstup . (let (i, step_no) = varstup in + read_reg htif_done_ref \<bind> (\<lambda> (w__0 :: bool) . return ((\<not> w__0))))) + (\<lambda> varstup . (let (i, step_no) = varstup in + (write_reg minstret_written_ref False \<then> + step step_no) \<bind> (\<lambda> varstup . (let (retired, stepped) = varstup in + (read_reg nextPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: xlenbits) . + (write_reg PC_ref w__1 \<then> + (if retired then retire_instruction () + else return () )) \<then> + ((let (step_no :: ii) = (if stepped then ((ex_int step_no)) + (( 1 :: int)::ii) else step_no) in + read_reg htif_done_ref \<bind> (\<lambda> (w__2 :: bool) . + (if w__2 then + (read_reg htif_exit_code_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . + (let exit_val = (Word.uint w__3) in + return ((let _ = + (if (((exit_val = (( 0 :: int)::ii)))) then print_endline (''SUCCESS'') + else print_int (''FAILURE: '') exit_val) in + i)))) + else + (let i = (((ex_int i)) + (( 1 :: int)::ii)) in + if (((((ex_int i)) = insns_per_tick))) then + (tick_clock () \<then> tick_platform () ) \<then> return (( 0 :: int)::ii) + else return i)) \<bind> (\<lambda> (i :: ii) . + return (i, step_no))))))))))) \<bind> (\<lambda> varstup . (let ((i :: ii), (step_no :: ii)) = varstup in + return () ))))))" + + +(*val read_kind_of_num : integer -> read_kind*) + +definition read_kind_of_num :: " int \<Rightarrow> read_kind " where + " read_kind_of_num arg0 = ( + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Read_plain + else if (((p00 = (( 1 :: int)::ii)))) then Read_reserve + else if (((p00 = (( 2 :: int)::ii)))) then Read_acquire + else if (((p00 = (( 3 :: int)::ii)))) then Read_exclusive + else if (((p00 = (( 4 :: int)::ii)))) then Read_exclusive_acquire + else if (((p00 = (( 5 :: int)::ii)))) then Read_stream + else if (((p00 = (( 6 :: int)::ii)))) then Read_RISCV_acquire + else if (((p00 = (( 7 :: int)::ii)))) then Read_RISCV_strong_acquire + else if (((p00 = (( 8 :: int)::ii)))) then Read_RISCV_reserved + else if (((p00 = (( 9 :: int)::ii)))) then Read_RISCV_reserved_acquire + else if (((p00 = (( 10 :: int)::ii)))) then Read_RISCV_reserved_strong_acquire + else Read_X86_locked))" + + +(*val num_of_read_kind : read_kind -> integer*) + +fun num_of_read_kind :: " read_kind \<Rightarrow> int " where + " num_of_read_kind Read_plain = ( (( 0 :: int)::ii))" +|" num_of_read_kind Read_reserve = ( (( 1 :: int)::ii))" +|" num_of_read_kind Read_acquire = ( (( 2 :: int)::ii))" +|" num_of_read_kind Read_exclusive = ( (( 3 :: int)::ii))" +|" num_of_read_kind Read_exclusive_acquire = ( (( 4 :: int)::ii))" +|" num_of_read_kind Read_stream = ( (( 5 :: int)::ii))" +|" num_of_read_kind Read_RISCV_acquire = ( (( 6 :: int)::ii))" +|" num_of_read_kind Read_RISCV_strong_acquire = ( (( 7 :: int)::ii))" +|" num_of_read_kind Read_RISCV_reserved = ( (( 8 :: int)::ii))" +|" num_of_read_kind Read_RISCV_reserved_acquire = ( (( 9 :: int)::ii))" +|" num_of_read_kind Read_RISCV_reserved_strong_acquire = ( (( 10 :: int)::ii))" +|" num_of_read_kind Read_X86_locked = ( (( 11 :: int)::ii))" + + +(*val write_kind_of_num : integer -> write_kind*) + +definition write_kind_of_num :: " int \<Rightarrow> write_kind " where + " write_kind_of_num arg0 = ( + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Write_plain + else if (((p00 = (( 1 :: int)::ii)))) then Write_conditional + else if (((p00 = (( 2 :: int)::ii)))) then Write_release + else if (((p00 = (( 3 :: int)::ii)))) then Write_exclusive + else if (((p00 = (( 4 :: int)::ii)))) then Write_exclusive_release + else if (((p00 = (( 5 :: int)::ii)))) then Write_RISCV_release + else if (((p00 = (( 6 :: int)::ii)))) then Write_RISCV_strong_release + else if (((p00 = (( 7 :: int)::ii)))) then Write_RISCV_conditional + else if (((p00 = (( 8 :: int)::ii)))) then Write_RISCV_conditional_release + else if (((p00 = (( 9 :: int)::ii)))) then Write_RISCV_conditional_strong_release + else Write_X86_locked))" + + +(*val num_of_write_kind : write_kind -> integer*) + +fun num_of_write_kind :: " write_kind \<Rightarrow> int " where + " num_of_write_kind Write_plain = ( (( 0 :: int)::ii))" +|" num_of_write_kind Write_conditional = ( (( 1 :: int)::ii))" +|" num_of_write_kind Write_release = ( (( 2 :: int)::ii))" +|" num_of_write_kind Write_exclusive = ( (( 3 :: int)::ii))" +|" num_of_write_kind Write_exclusive_release = ( (( 4 :: int)::ii))" +|" num_of_write_kind Write_RISCV_release = ( (( 5 :: int)::ii))" +|" num_of_write_kind Write_RISCV_strong_release = ( (( 6 :: int)::ii))" +|" num_of_write_kind Write_RISCV_conditional = ( (( 7 :: int)::ii))" +|" num_of_write_kind Write_RISCV_conditional_release = ( (( 8 :: int)::ii))" +|" num_of_write_kind Write_RISCV_conditional_strong_release = ( (( 9 :: int)::ii))" +|" num_of_write_kind Write_X86_locked = ( (( 10 :: int)::ii))" + + +(*val barrier_kind_of_num : integer -> barrier_kind*) + +definition barrier_kind_of_num :: " int \<Rightarrow> barrier_kind " where + " barrier_kind_of_num arg0 = ( + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Barrier_Sync + else if (((p00 = (( 1 :: int)::ii)))) then Barrier_LwSync + else if (((p00 = (( 2 :: int)::ii)))) then Barrier_Eieio + else if (((p00 = (( 3 :: int)::ii)))) then Barrier_Isync + else if (((p00 = (( 4 :: int)::ii)))) then Barrier_DMB + else if (((p00 = (( 5 :: int)::ii)))) then Barrier_DMB_ST + else if (((p00 = (( 6 :: int)::ii)))) then Barrier_DMB_LD + else if (((p00 = (( 7 :: int)::ii)))) then Barrier_DSB + else if (((p00 = (( 8 :: int)::ii)))) then Barrier_DSB_ST + else if (((p00 = (( 9 :: int)::ii)))) then Barrier_DSB_LD + else if (((p00 = (( 10 :: int)::ii)))) then Barrier_ISB + else if (((p00 = (( 11 :: int)::ii)))) then Barrier_MIPS_SYNC + else if (((p00 = (( 12 :: int)::ii)))) then Barrier_RISCV_rw_rw + else if (((p00 = (( 13 :: int)::ii)))) then Barrier_RISCV_r_rw + else if (((p00 = (( 14 :: int)::ii)))) then Barrier_RISCV_r_r + else if (((p00 = (( 15 :: int)::ii)))) then Barrier_RISCV_rw_w + else if (((p00 = (( 16 :: int)::ii)))) then Barrier_RISCV_w_w + else if (((p00 = (( 17 :: int)::ii)))) then Barrier_RISCV_w_rw + else if (((p00 = (( 18 :: int)::ii)))) then Barrier_RISCV_rw_r + else if (((p00 = (( 19 :: int)::ii)))) then Barrier_RISCV_r_w + else if (((p00 = (( 20 :: int)::ii)))) then Barrier_RISCV_w_r + else if (((p00 = (( 21 :: int)::ii)))) then Barrier_RISCV_i + else Barrier_x86_MFENCE))" + + +(*val num_of_barrier_kind : barrier_kind -> integer*) + +fun num_of_barrier_kind :: " barrier_kind \<Rightarrow> int " where + " num_of_barrier_kind Barrier_Sync = ( (( 0 :: int)::ii))" +|" num_of_barrier_kind Barrier_LwSync = ( (( 1 :: int)::ii))" +|" num_of_barrier_kind Barrier_Eieio = ( (( 2 :: int)::ii))" +|" num_of_barrier_kind Barrier_Isync = ( (( 3 :: int)::ii))" +|" num_of_barrier_kind Barrier_DMB = ( (( 4 :: int)::ii))" +|" num_of_barrier_kind Barrier_DMB_ST = ( (( 5 :: int)::ii))" +|" num_of_barrier_kind Barrier_DMB_LD = ( (( 6 :: int)::ii))" +|" num_of_barrier_kind Barrier_DSB = ( (( 7 :: int)::ii))" +|" num_of_barrier_kind Barrier_DSB_ST = ( (( 8 :: int)::ii))" +|" num_of_barrier_kind Barrier_DSB_LD = ( (( 9 :: int)::ii))" +|" num_of_barrier_kind Barrier_ISB = ( (( 10 :: int)::ii))" +|" num_of_barrier_kind Barrier_MIPS_SYNC = ( (( 11 :: int)::ii))" +|" num_of_barrier_kind Barrier_RISCV_rw_rw = ( (( 12 :: int)::ii))" +|" num_of_barrier_kind Barrier_RISCV_r_rw = ( (( 13 :: int)::ii))" +|" num_of_barrier_kind Barrier_RISCV_r_r = ( (( 14 :: int)::ii))" +|" num_of_barrier_kind Barrier_RISCV_rw_w = ( (( 15 :: int)::ii))" +|" num_of_barrier_kind Barrier_RISCV_w_w = ( (( 16 :: int)::ii))" +|" num_of_barrier_kind Barrier_RISCV_w_rw = ( (( 17 :: int)::ii))" +|" num_of_barrier_kind Barrier_RISCV_rw_r = ( (( 18 :: int)::ii))" +|" num_of_barrier_kind Barrier_RISCV_r_w = ( (( 19 :: int)::ii))" +|" num_of_barrier_kind Barrier_RISCV_w_r = ( (( 20 :: int)::ii))" +|" num_of_barrier_kind Barrier_RISCV_i = ( (( 21 :: int)::ii))" +|" num_of_barrier_kind Barrier_x86_MFENCE = ( (( 22 :: int)::ii))" + + +(*val trans_kind_of_num : integer -> trans_kind*) + +definition trans_kind_of_num :: " int \<Rightarrow> trans_kind " where + " trans_kind_of_num arg0 = ( + (let p00 = arg0 in + if (((p00 = (( 0 :: int)::ii)))) then Transaction_start + else if (((p00 = (( 1 :: int)::ii)))) then Transaction_commit + else Transaction_abort))" + + +(*val num_of_trans_kind : trans_kind -> integer*) + +fun num_of_trans_kind :: " trans_kind \<Rightarrow> int " where + " num_of_trans_kind Transaction_start = ( (( 0 :: int)::ii))" +|" num_of_trans_kind Transaction_commit = ( (( 1 :: int)::ii))" +|" num_of_trans_kind Transaction_abort = ( (( 2 :: int)::ii))" + + +definition GPRstr :: "(string)list " where + " GPRstr = ( + [(''x31''),(''x30''),(''x29''),(''x28''),(''x27''),(''x26''),(''x25''),(''x24''),(''x23''),(''x22''),(''x21''),(''x20''),(''x19''),(''x18''),(''x17''),(''x16''), + (''x15''),(''x14''),(''x13''),(''x12''),(''x21''),(''x10''),(''x9''),(''x8''),(''x7''),(''x6''),(''x5''),(''x4''),(''x3''),(''x2''),(''x1''),(''x0'')])" + + +definition CIA_fp :: " regfp " where + " CIA_fp = ( RFull (''CIA''))" + + +definition NIA_fp :: " regfp " where + " NIA_fp = ( RFull (''NIA''))" + + +(*val initial_analysis : ast -> M (list regfp * list regfp * list regfp * list niafp * diafp * instruction_kind)*) + +definition initial_analysis :: " ast \<Rightarrow>((register_value),((regfp)list*(regfp)list*(regfp)list*(niafp)list*diafp*instruction_kind),(exception))monad " where + " initial_analysis instr = ( + (let iR = ([]) in + (let oR = ([]) in + (let aR = ([]) in + (let ik = (IK_simple () ) in + (let Nias = ([NIAFP_successor () ]) in + (let Dia = (DIAFP_none () ) in + (case instr of + EBREAK (_) => return (Nias, aR, iR, ik, oR) + | UTYPE (imm,rd,op1) => + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + return (Nias, aR, iR, ik, oR)) + | RISCV_JAL (imm,rd) => + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + (let (offset :: 64 bits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let (Nias :: niafps) = ([NIAFP_concrete_address ((add_vec w__0 offset :: 64 Word.word))]) in + (let (ik :: instruction_kind) = (IK_branch () ) in + return (Nias, aR, iR, ik, oR)))))) + | RISCV_JALR (imm,rs,rd) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) # iR) in + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + (let (offset :: 64 bits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let (Nias :: niafps) = ([NIAFP_indirect_address () ]) in + (let (ik :: instruction_kind) = (IK_branch () ) in + return (Nias, aR, iR, ik, oR)))))) + | BTYPE (imm,rs2,rs1,op1) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) # iR) in + (let (iR :: regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in + (let ik = (IK_branch () ) in + (let (offset :: 64 bits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let (Nias :: niafps) = + ([NIAFP_concrete_address ((add_vec w__1 offset :: 64 Word.word)),NIAFP_successor () ]) in + return (Nias, aR, iR, ik, oR))))))) + | ITYPE (imm,rs,rd,op1) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) # iR) in + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + return (Nias, aR, iR, ik, oR))) + | SHIFTIOP (imm,rs,rd,op1) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) # iR) in + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + return (Nias, aR, iR, ik, oR))) + | RTYPE (rs2,rs1,rd,op1) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) # iR) in + (let (iR :: regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + return (Nias, aR, iR, ik, oR)))) + | CSR (csr,rs1,rd,is_imm,op1) => + (let (isWrite :: bool) = + ((case op1 of + CSRRW => True + | _ => if is_imm then (((Word.uint rs1)) \<noteq> (( 0 :: int)::ii)) else (((Word.uint rs1)) \<noteq> (( 0 :: int)::ii)) + )) in + (let (iR :: regfps) = ((RFull ((csr_name csr))) # iR) in + (let (iR :: regfps) = + (if ((\<not> is_imm)) then (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR + else iR) in + (let (oR :: regfps) = (if isWrite then (RFull ((csr_name csr))) # oR else oR) in + (let (oR :: regfps) = ((RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + return (Nias, aR, iR, ik, oR)))))) + | LOAD (imm,rs,rd,unsign,width,aq,rl) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) # iR) in + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + (let aR = iR in + (case (aq, rl) of + (False, False) => return (IK_mem_read Read_plain) + | (True, False) => return (IK_mem_read Read_RISCV_acquire) + | (True, True) => return (IK_mem_read Read_RISCV_strong_acquire) + | _ => internal_error (''LOAD type not implemented in initial_analysis'') + ) \<bind> (\<lambda> (w__3 :: instruction_kind) . + (let (ik :: instruction_kind) = w__3 in + return (Nias, aR, iR, ik, oR)))))) + | STORE (imm,rs2,rs1,width,aq,rl) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) # iR) in + (let (iR :: regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in + (let (aR :: regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then aR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # aR) in + (case (aq, rl) of + (False, False) => return (IK_mem_write Write_plain) + | (False, True) => return (IK_mem_write Write_RISCV_release) + | (True, True) => return (IK_mem_write Write_RISCV_strong_release) + | _ => internal_error (''STORE type not implemented in initial_analysis'') + ) \<bind> (\<lambda> (w__5 :: instruction_kind) . + (let (ik :: instruction_kind) = w__5 in + return (Nias, aR, iR, ik, oR)))))) + | ADDIW (imm,rs,rd) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) # iR) in + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + return (Nias, aR, iR, ik, oR))) + | SHIFTW (imm,rs,rd,op1) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs))))) # iR) in + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + return (Nias, aR, iR, ik, oR))) + | RTYPEW (rs2,rs1,rd,op1) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) # iR) in + (let (iR :: regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + return (Nias, aR, iR, ik, oR)))) + | FENCE (pred,succ) => + (case (pred, succ) of + (v__276, v__277) => + if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + return (IK_barrier Barrier_RISCV_rw_rw) + else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + return (IK_barrier Barrier_RISCV_r_rw) + else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + return (IK_barrier Barrier_RISCV_r_r) + else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + return (IK_barrier Barrier_RISCV_rw_w) + else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + return (IK_barrier Barrier_RISCV_w_w) + else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word))))))) then + return (IK_barrier Barrier_RISCV_w_rw) + else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + return (IK_barrier Barrier_RISCV_rw_r) + else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + return (IK_barrier Barrier_RISCV_r_w) + else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + return (IK_barrier Barrier_RISCV_w_r) + else if ((((((((subrange_vec_dec v__276 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__277 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + return (IK_simple () ) + else internal_error (''barrier type not implemented in initial_analysis'') + ) \<bind> (\<lambda> (w__17 :: instruction_kind) . + (let (ik :: instruction_kind) = w__17 in + return (Nias, aR, iR, ik, oR))) + | FENCEI (_) => + (let (ik :: instruction_kind) = (IK_barrier Barrier_RISCV_i) in + return (Nias, aR, iR, ik, oR)) + | LOADRES (aq,rl,rs1,width,rd) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + (let aR = iR in + (case (aq, rl) of + (False, False) => return (IK_mem_read Read_RISCV_reserved) + | (True, False) => return (IK_mem_read Read_RISCV_reserved_acquire) + | (True, True) => return (IK_mem_read Read_RISCV_reserved_strong_acquire) + | (False, True) => internal_error (''LOADRES type not implemented in initial_analysis'') + ) \<bind> (\<lambda> (w__19 :: instruction_kind) . + (let (ik :: instruction_kind) = w__19 in + return (Nias, aR, iR, ik, oR)))))) + | STORECON (aq,rl,rs2,rs1,width,rd) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) # iR) in + (let (iR :: regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in + (let (aR :: regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then aR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # aR) in + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + (case (aq, rl) of + (False, False) => return (IK_mem_write Write_RISCV_conditional) + | (False, True) => return (IK_mem_write Write_RISCV_conditional_release) + | (True, True) => return (IK_mem_write Write_RISCV_conditional_strong_release) + | (True, False) => internal_error (''STORECON type not implemented in initial_analysis'') + ) \<bind> (\<lambda> (w__21 :: instruction_kind) . + (let (ik :: instruction_kind) = w__21 in + return (Nias, aR, iR, ik, oR))))))) + | AMO (op1,aq,rl,rs2,rs1,width,rd) => + (let (iR :: regfps) = + (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs2))))) # iR) in + (let (iR :: regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then iR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # iR) in + (let (aR :: regfps) = + (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then aR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rs1))))) # aR) in + (let (oR :: regfps) = + (if (((((regbits_to_regno rd)) = (( 0 :: int)::ii)))) then oR + else (RFull ((access_list_dec GPRstr ((regbits_to_regno rd))))) # oR) in + (let (ik :: instruction_kind) = + ((case (aq, rl) of + (False, False) => IK_mem_rmw (Read_RISCV_reserved,Write_RISCV_conditional) + | (False, True) => IK_mem_rmw (Read_RISCV_reserved,Write_RISCV_conditional_release) + | (True, False) => IK_mem_rmw (Read_RISCV_reserved_acquire,Write_RISCV_conditional) + | (True, True) => IK_mem_rmw (Read_RISCV_reserved_acquire,Write_RISCV_conditional_release) + )) in + return (Nias, aR, iR, ik, oR)))))) + | _ => return (Nias, aR, iR, ik, oR) + ) \<bind> (\<lambda> varstup . (let ((Nias :: niafps), (aR :: regfps), (iR :: regfps), (ik :: instruction_kind), (oR :: + regfps)) = varstup in + return (iR, oR, aR, Nias, Dia, ik))))))))))" definition initial_regstate :: " regstate " where " initial_regstate = ( (| tlb39 = None, + htif_exit_code = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + htif_done = False, + htif_tohost = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mtimecmp = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), tselect = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -7587,10 +24512,11 @@ definition initial_regstate :: " regstate " where B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)), scause = - (Mk_Mcause (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word)), + ((| Mcause_Mcause_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), sepc = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -7602,26 +24528,28 @@ definition initial_regstate :: " regstate " where B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)), stvec = - (Mk_Mtvec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word)), + ((| Mtvec_Mtvec_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), satp = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)), sideleg = - (Mk_Sinterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0] - :: 64 Word.word)), + ((| Sinterrupts_Sinterrupts_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), sedeleg = - (Mk_Sedeleg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word)), + ((| Sedeleg_Sedeleg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), pmpcfg0 = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -7652,6 +24580,7 @@ definition initial_regstate :: " regstate " where B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)), + minstret_written = False, minstret = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -7667,6 +24596,16 @@ definition initial_regstate :: " regstate " where B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)), + scounteren = + ((| Counteren_Counteren_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)) |)), + mcounteren = + ((| Counteren_Counteren_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)) |)), mscratch = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, @@ -7683,54 +24622,214 @@ definition initial_regstate :: " regstate " where B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)), mcause = - (Mk_Mcause (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word)), + ((| Mcause_Mcause_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), mtvec = - (Mk_Mtvec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word)), + ((| Mtvec_Mtvec_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), medeleg = - (Mk_Medeleg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word)), + ((| Medeleg_Medeleg_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), mideleg = - (Mk_Minterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0] - :: 64 Word.word)), + ((| Minterrupts_Minterrupts_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), mie = - (Mk_Minterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0] - :: 64 Word.word)), + ((| Minterrupts_Minterrupts_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), mip = - (Mk_Minterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0] - :: 64 Word.word)), + ((| Minterrupts_Minterrupts_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), mstatus = - (Mk_Mstatus (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word)), + ((| Mstatus_Mstatus_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), misa = - (Mk_Misa (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word)), + ((| Misa_Misa_chunk_0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |)), cur_inst = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 64 Word.word)), cur_privilege = User, + x31 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x30 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x29 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x28 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x27 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x26 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x25 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x24 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x23 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x22 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x21 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x20 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x19 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x18 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x17 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x16 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x15 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x14 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x13 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x12 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x11 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x10 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x9 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x8 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x7 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x6 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x5 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x4 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x3 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x2 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + x1 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), Xs = ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, diff --git a/snapshots/isabelle/riscv/Riscv_duopod.thy b/snapshots/isabelle/riscv/Riscv_duopod.thy deleted file mode 100644 index 9087ec9c..00000000 --- a/snapshots/isabelle/riscv/Riscv_duopod.thy +++ /dev/null @@ -1,461 +0,0 @@ -chapter \<open>Generated by Lem from riscv_duopod.lem.\<close> - -theory "Riscv_duopod" - -imports - Main - "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" - "Sail_operators_mwords" - "Prompt_monad" - "Prompt" - "State" - "Riscv_duopod_types" - "Riscv_extras" - -begin - -(*Generated by Sail from riscv_duopod.*) -(*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) -(*open import State*) -(*open import Riscv_duopod_types*) -(*open import Riscv_extras*) - - - - - - - - - -(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) - - - -(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) - - - -(*val __raw_SetSlice_int : forall 'w. integer -> ii -> ii -> bits 'w -> ii*) - -(*val __GetSlice_int : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*) - -definition GetSlice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where - " GetSlice_int n m o1 = ( (get_slice_int0 n m o1 :: ( 'n::len)Word.word))" - - -(*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*) - -(*val __raw_GetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w*) - -(*val cast_unit_vec : bitU -> mword ty1*) - -fun cast_unit_vec0 :: " bitU \<Rightarrow>(1)Word.word " where - " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))" -|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))" - - -(*val DecStr : ii -> string*) - -(*val HexStr : ii -> string*) - -(*val __RISCV_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M bool*) - -definition RISCV_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),(bool),(unit))monad " where - " RISCV_write addr width data = ( - write_ram (( 64 :: int)::ii) width - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word) addr data \<then> - return True )" - - -(*val __TraceMemoryWrite : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) - -(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (maybe (mword 'int8_times_n))*) - -definition RISCV_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)option),(unit))monad " where - " RISCV_read addr width = ( - (read_ram (( 64 :: int)::ii) width - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word) addr - :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'int8_times_n::len)Word.word) . - return (Some w__0)))" - - -(*val __TraceMemoryRead : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) - -(*val ex_nat : ii -> integer*) - -definition ex_nat :: " int \<Rightarrow> int " where - " ex_nat n = ( n )" - - -(*val ex_int : ii -> integer*) - -definition ex_int :: " int \<Rightarrow> int " where - " ex_int n = ( n )" - - -(*val coerce_int_nat : ii -> M ii*) - -definition coerce_int_nat :: " int \<Rightarrow>((register_value),(int),(unit))monad " where - " coerce_int_nat x = ( assert_exp True ('''') \<then> return x )" - - -(*val EXTS : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) - -(*val EXTZ : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) - -definition EXTS :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where - " EXTS (m__tv :: int) v = ( (sign_extend v m__tv :: ( 'm::len)Word.word))" - - -definition EXTZ :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where - " EXTZ (m__tv :: int) v = ( (zero_extend v m__tv :: ( 'm::len)Word.word))" - - -(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) - -(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) - -(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) - -(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) - -(*val zopz0zIzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) - -definition zopz0zI_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where - " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))" - - -definition zopz0zKzJ_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where - " zopz0zKzJ_s x y = ( ((Word.sint x)) \<ge> ((Word.sint y)))" - - -definition zopz0zI_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where - " zopz0zI_u x y = ( ((Word.uint x)) < ((Word.uint y)))" - - -definition zopz0zKzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where - " zopz0zKzJ_u x y = ( ((Word.uint x)) \<ge> ((Word.uint y)))" - - -definition zopz0zIzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where - " zopz0zIzJ_u x y = ( ((Word.uint x)) \<le> ((Word.uint y)))" - - -(*val bool_to_bits : bool -> mword ty1*) - -definition bool_to_bits :: " bool \<Rightarrow>(1)Word.word " where - " bool_to_bits x = ( if x then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word))" - - -(*val bit_to_bool : bitU -> bool*) - -fun bit_to_bool :: " bitU \<Rightarrow> bool " where - " bit_to_bool B1 = ( True )" -|" bit_to_bool B0 = ( False )" - - -(*val vector64 : ii -> mword ty64*) - -definition vector64 :: " int \<Rightarrow>(64)Word.word " where - " vector64 n = ( (get_slice_int0 (( 64 :: int)::ii) n (( 0 :: int)::ii) :: 64 Word.word))" - - -(*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*) - -definition to_bits :: " int \<Rightarrow> int \<Rightarrow>('l::len)Word.word " where - " to_bits l n = ( (get_slice_int0 l n (( 0 :: int)::ii) :: ( 'l::len)Word.word))" - - -(*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*) - -definition shift_right_arith64 :: "(64)Word.word \<Rightarrow>(6)Word.word \<Rightarrow>(64)Word.word " where - " shift_right_arith64 (v :: 64 bits) (shift :: 6 bits) = ( - (let (v128 :: 128 bits) = ((EXTS (( 128 :: int)::ii) v :: 128 Word.word)) in - (subrange_vec_dec ((shift_bits_right v128 shift :: 128 Word.word)) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))" - - -(*val shift_right_arith32 : mword ty32 -> mword ty5 -> mword ty32*) - -definition shift_right_arith32 :: "(32)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(32)Word.word " where - " shift_right_arith32 (v :: 32 bits) (shift :: 5 bits) = ( - (let (v64 :: 64 bits) = ((EXTS (( 64 :: int)::ii) v :: 64 Word.word)) in - (subrange_vec_dec ((shift_bits_right v64 shift :: 64 Word.word)) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)))" - - -(*val zeros : forall 'n. Size 'n => integer -> mword 'n*) - -definition zeros0 :: " int \<Rightarrow>('n::len)Word.word " where - " zeros0 n = ( (replicate_bits (vec_of_bits [B0] :: 1 Word.word) n :: ( 'n::len)Word.word))" - - -(*val regbits_to_regno : mword ty5 -> integer*) - -definition regbits_to_regno :: "(5)Word.word \<Rightarrow> int " where - " regbits_to_regno b = ( - (let r = (Word.uint b) in - r))" - - -(*val rX : integer -> M (mword ty64)*) - -definition rX :: " int \<Rightarrow>((register_value),((64)Word.word),(unit))monad " where - " rX l__5 = ( - if (((l__5 = (( 0 :: int)::ii)))) then - return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word) - else - read_reg Xs_ref \<bind> (\<lambda> (w__0 :: xlen_t list) . - return ((access_list_dec w__0 l__5 :: 64 Word.word))))" - - -(*val wX : integer -> mword ty64 -> M unit*) - -definition wX :: " int \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(unit))monad " where - " wX r v = ( - if (((r \<noteq> (( 0 :: int)::ii)))) then - read_reg Xs_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . - write_reg Xs_ref ((update_list_dec w__0 r v :: ( 64 Word.word) list))) - else return () )" - - -(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (mword 'int8_times_n)*) - -definition MEMr :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('int8_times_n::len)Word.word),(unit))monad " where - " MEMr addr width = ( - (RISCV_read addr width :: ( (( 'int8_times_n::len)Word.word)option) M) \<bind> (\<lambda> (w__0 :: - (( 'int8_times_n::len)Word.word)option) . - return ((case w__0 of - Some (v) => v - | None => (zeros0 (((( 8 :: int)::ii) * width)) :: ( 'int8_times_n::len)Word.word) - ))))" - - -(*val iop_of_num : integer -> iop*) - -definition iop_of_num :: " int \<Rightarrow> iop " where - " iop_of_num arg0 = ( - (let l__0 = arg0 in - if (((l__0 = (( 0 :: int)::ii)))) then RISCV_ADDI - else if (((l__0 = (( 1 :: int)::ii)))) then RISCV_SLTI - else if (((l__0 = (( 2 :: int)::ii)))) then RISCV_SLTIU - else if (((l__0 = (( 3 :: int)::ii)))) then RISCV_XORI - else if (((l__0 = (( 4 :: int)::ii)))) then RISCV_ORI - else RISCV_ANDI))" - - -(*val num_of_iop : iop -> integer*) - -fun num_of_iop :: " iop \<Rightarrow> int " where - " num_of_iop RISCV_ADDI = ( (( 0 :: int)::ii))" -|" num_of_iop RISCV_SLTI = ( (( 1 :: int)::ii))" -|" num_of_iop RISCV_SLTIU = ( (( 2 :: int)::ii))" -|" num_of_iop RISCV_XORI = ( (( 3 :: int)::ii))" -|" num_of_iop RISCV_ORI = ( (( 4 :: int)::ii))" -|" num_of_iop RISCV_ANDI = ( (( 5 :: int)::ii))" - - -(*val decode : mword ty32 -> maybe ast*) - -(*val execute : ast -> M unit*) - -definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where - " decode v__0 = ( - if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (ITYPE (imm,rs1,rd,RISCV_ADDI))))) - else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then - (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in - (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in - (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in - Some (LOAD (imm,rs1,rd))))) - else None )" - - -(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) - -definition execute_LOAD :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(unit))monad " where - " execute_LOAD imm rs1 rd = ( - (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . - (let (addr :: xlen_t) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in - (MEMr addr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (result :: xlen_t) . - wX ((regbits_to_regno rd)) result))))" - - -(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M unit*) - -fun execute_ITYPE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> iop \<Rightarrow>((register_value),(unit),(unit))monad " where - " execute_ITYPE imm rs1 rd RISCV_ADDI = ( - (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . - (let (imm_ext :: xlen_t) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in - (let result = ((add_vec rs1_val imm_ext :: 64 Word.word)) in - wX ((regbits_to_regno rd)) result))))" - - -fun execute :: " ast \<Rightarrow>((register_value),(unit),(unit))monad " where - " execute (ITYPE (imm,rs1,rd,arg3)) = ( execute_ITYPE imm rs1 rd arg3 )" -|" execute (LOAD (imm,rs1,rd)) = ( execute_LOAD imm rs1 rd )" - - -definition initial_regstate :: " regstate " where - " initial_regstate = ( - (| Xs = - ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word), - (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word)]), - nextPC = - ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word)), - PC = - ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, - B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] - :: 64 Word.word)) |) )" - - - -end diff --git a/snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy b/snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy deleted file mode 100644 index d6ca4d7d..00000000 --- a/snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy +++ /dev/null @@ -1,48 +0,0 @@ -theory Riscv_duopod_lemmas - imports - Sail.Sail_values_lemmas - Sail.State_lemmas - Riscv_duopod -begin - -abbreviation "liftS \<equiv> liftState (get_regval, set_regval)" - -lemmas register_defs = get_regval_def set_regval_def Xs_ref_def nextPC_ref_def PC_ref_def - -lemma regval_vector_64_dec_bit[simp]: - "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v" - by (auto simp: regval_of_vector_64_dec_bit_def) - -lemma vector_of_rv_rv_of_vector[simp]: - assumes "\<And>v. of_rv (rv_of v) = Some v" - shows "vector_of_regval of_rv (regval_of_vector rv_of len is_inc v) = Some v" -proof - - from assms have "of_rv \<circ> rv_of = Some" by auto - then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def) -qed - -lemma liftS_read_reg_Xs[simp]: - "liftS (read_reg Xs_ref) = readS (Xs \<circ> regstate)" - by (auto simp: liftState_read_reg_readS register_defs) - -lemma liftS_write_reg_Xs[simp]: - "liftS (write_reg Xs_ref v) = updateS (regstate_update (Xs_update (\<lambda>_. v)))" - by (auto simp: liftState_write_reg_updateS register_defs) - -lemma liftS_read_reg_nextPC[simp]: - "liftS (read_reg nextPC_ref) = readS (nextPC \<circ> regstate)" - by (auto simp: liftState_read_reg_readS register_defs) - -lemma liftS_write_reg_nextPC[simp]: - "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\<lambda>_. v)))" - by (auto simp: liftState_write_reg_updateS register_defs) - -lemma liftS_read_reg_PC[simp]: - "liftS (read_reg PC_ref) = readS (PC \<circ> regstate)" - by (auto simp: liftState_read_reg_readS register_defs) - -lemma liftS_write_reg_PC[simp]: - "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\<lambda>_. v)))" - by (auto simp: liftState_write_reg_updateS register_defs) - -end diff --git a/snapshots/isabelle/riscv/Riscv_duopod_types.thy b/snapshots/isabelle/riscv/Riscv_duopod_types.thy deleted file mode 100644 index 8e92ede0..00000000 --- a/snapshots/isabelle/riscv/Riscv_duopod_types.thy +++ /dev/null @@ -1,170 +0,0 @@ -chapter \<open>Generated by Lem from riscv_duopod_types.lem.\<close> - -theory "Riscv_duopod_types" - -imports - Main - "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" - "Sail_operators_mwords" - "Prompt_monad" - "Prompt" - "State" - -begin - -(*Generated by Sail from riscv_duopod.*) -(*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) -(*open import State*) -type_synonym 'n bits =" ( 'n::len)Word.word " - - - -type_synonym xlen =" int " - -type_synonym xlen_t =" 64 bits " - -type_synonym 'n regno =" int " - -type_synonym regbits =" 5 bits " - -datatype iop = RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI - - - -datatype ast = - ITYPE " (( 12 bits * regbits * regbits * iop))" | LOAD " (( 12 bits * regbits * regbits))" - - - -datatype register_value = - Regval_vector " ((ii * bool * register_value list))" - | Regval_list " ( register_value list)" - | Regval_option " ( register_value option)" - | Regval_vector_64_dec_bit " ( 64 Word.word)" - - - -record regstate = - Xs ::" ( 64 Word.word) list " - nextPC ::" 64 Word.word " - PC ::" 64 Word.word " - - - - - -(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) - -fun vector_64_dec_bit_of_regval :: " register_value \<Rightarrow>((64)Word.word)option " where - " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )" -|" vector_64_dec_bit_of_regval g__6 = ( None )" - - -(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) - -definition regval_of_vector_64_dec_bit :: "(64)Word.word \<Rightarrow> register_value " where - " regval_of_vector_64_dec_bit v = ( Regval_vector_64_dec_bit v )" - - - - -(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) -definition vector_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where - " vector_of_regval of_regval1 = ( \<lambda>x . - (case x of - Regval_vector (_, _, v) => just_list (List.map of_regval1 v) - | _ => None - ) )" - - -(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) -definition regval_of_vector :: "('a \<Rightarrow> register_value)\<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'a list \<Rightarrow> register_value " where - " regval_of_vector regval_of1 size1 is_inc xs = ( Regval_vector (size1, is_inc, List.map regval_of1 xs))" - - -(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) -definition list_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where - " list_of_regval of_regval1 = ( \<lambda>x . - (case x of - Regval_list v => just_list (List.map of_regval1 v) - | _ => None - ) )" - - -(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) -definition regval_of_list :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a list \<Rightarrow> register_value " where - " regval_of_list regval_of1 xs = ( Regval_list (List.map regval_of1 xs))" - - -(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) -definition option_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a option)option " where - " option_of_regval of_regval1 = ( \<lambda>x . - (case x of Regval_option v => map_option of_regval1 v | _ => None ) )" - - -(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) -definition regval_of_option :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a option \<Rightarrow> register_value " where - " regval_of_option regval_of1 v = ( Regval_option (map_option regval_of1 v))" - - - -definition Xs_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where - " Xs_ref = ( (| - name = (''Xs''), - read_from = (\<lambda> s . (Xs s)), - write_to = (\<lambda> v s . (( s (| Xs := v |)))), - of_regval = (\<lambda> v . vector_of_regval (\<lambda> v . vector_64_dec_bit_of_regval v) v), - regval_of = (\<lambda> v . regval_of_vector (\<lambda> v . regval_of_vector_64_dec_bit v)(( 32 :: int)) False v) |) )" - - -definition nextPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where - " nextPC_ref = ( (| - name = (''nextPC''), - read_from = (\<lambda> s . (nextPC s)), - write_to = (\<lambda> v s . (( s (| nextPC := v |)))), - of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), - regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" - - -definition PC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where - " PC_ref = ( (| - name = (''PC''), - read_from = (\<lambda> s . (PC s)), - write_to = (\<lambda> v s . (( s (| PC := v |)))), - of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), - regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" - - -(*val get_regval : string -> regstate -> maybe register_value*) -definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register_value)option " where - " get_regval reg_name s = ( - if reg_name = (''Xs'') then Some ((regval_of Xs_ref) ((read_from Xs_ref) s)) else - if reg_name = (''nextPC'') then Some ((regval_of nextPC_ref) ((read_from nextPC_ref) s)) else - if reg_name = (''PC'') then Some ((regval_of PC_ref) ((read_from PC_ref) s)) else - None )" - - -(*val set_regval : string -> register_value -> regstate -> maybe regstate*) -definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option " where - " set_regval reg_name v s = ( - if reg_name = (''Xs'') then map_option (\<lambda> v . (write_to Xs_ref) v s) ((of_regval Xs_ref) v) else - if reg_name = (''nextPC'') then map_option (\<lambda> v . (write_to nextPC_ref) v s) ((of_regval nextPC_ref) v) else - if reg_name = (''PC'') then map_option (\<lambda> v . (write_to PC_ref) v s) ((of_regval PC_ref) v) else - None )" - - -definition register_accessors :: "(string \<Rightarrow> regstate \<Rightarrow>(register_value)option)*(string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option)" where - " register_accessors = ( (get_regval, set_regval))" - - - -type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, unit) monadR " -type_synonym 'a M =" (register_value, 'a, unit) monad " -end diff --git a/snapshots/isabelle/riscv/Riscv_extras.thy b/snapshots/isabelle/riscv/Riscv_extras.thy index fc83385b..8e371170 100644 --- a/snapshots/isabelle/riscv/Riscv_extras.thy +++ b/snapshots/isabelle/riscv/Riscv_extras.thy @@ -6,21 +6,21 @@ imports Main "Lem_pervasives" "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" - "Sail_operators_mwords" - "Prompt_monad" - "Prompt" + "Sail2_instr_kinds" + "Sail2_values" + "Sail2_operators_mwords" + "Sail2_prompt_monad" + "Sail2_prompt" begin (*open import Pervasives*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) type_synonym 'a bitvector =" ( 'a::len)Word.word " @@ -39,6 +39,18 @@ definition MEM_fence_rw_w :: " unit \<Rightarrow>('b,(unit),'a)monad " where definition MEM_fence_w_w :: " unit \<Rightarrow>('b,(unit),'a)monad " where " MEM_fence_w_w _ = ( barrier Barrier_RISCV_w_w )" +definition MEM_fence_w_rw :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " MEM_fence_w_rw _ = ( barrier Barrier_RISCV_w_rw )" + +definition MEM_fence_rw_r :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " MEM_fence_rw_r _ = ( barrier Barrier_RISCV_rw_r )" + +definition MEM_fence_r_w :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " MEM_fence_r_w _ = ( barrier Barrier_RISCV_r_w )" + +definition MEM_fence_w_r :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " MEM_fence_w_r _ = ( barrier Barrier_RISCV_w_r )" + definition MEM_fence_i :: " unit \<Rightarrow>('b,(unit),'a)monad " where " MEM_fence_i _ = ( barrier Barrier_RISCV_i )" @@ -52,57 +64,148 @@ definition MEM_fence_i :: " unit \<Rightarrow>('b,(unit),'a)monad " where definition MEMea :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where " MEMea addr size1 = ( write_mem_ea - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain addr size1 )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_plain addr size1 )" definition MEMea_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where " MEMea_release addr size1 = ( write_mem_ea - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr size1 )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr size1 )" definition MEMea_strong_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where " MEMea_strong_release addr size1 = ( write_mem_ea - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr size1 )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr size1 )" definition MEMea_conditional :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where " MEMea_conditional addr size1 = ( write_mem_ea - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr size1 )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr size1 )" definition MEMea_conditional_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where " MEMea_conditional_release addr size1 = ( write_mem_ea - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr size1 )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr size1 )" definition MEMea_conditional_strong_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where " MEMea_conditional_strong_release addr size1 = ( write_mem_ea - instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr size1 )" + instance_Sail2_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr size1 )" + + +(*val MEMr : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) +(*val MEMr_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) +(*val MEMr_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) +(*val MEMr_reserved : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) +(*val MEMr_reserved_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) +(*val MEMr_reserved_strong_acquire : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) + +definition MEMr :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where + " MEMr addrsize size1 hexRAM addr = ( read_mem + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain addr size1 )" + +definition MEMr_acquire :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where + " MEMr_acquire addrsize size1 hexRAM addr = ( read_mem + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_acquire addr size1 )" + +definition MEMr_strong_acquire :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where + " MEMr_strong_acquire addrsize size1 hexRAM addr = ( read_mem + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_strong_acquire addr size1 )" + +definition MEMr_reserved :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where + " MEMr_reserved addrsize size1 hexRAM addr = ( read_mem + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved addr size1 )" + +definition MEMr_reserved_acquire :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where + " MEMr_reserved_acquire addrsize size1 hexRAM addr = ( read_mem + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_acquire addr size1 )" + +definition MEMr_reserved_strong_acquire :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where + " MEMr_reserved_strong_acquire addrsize size1 hexRAM addr = ( read_mem + instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_RISCV_reserved_strong_acquire addr size1 )" (*val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv unit 'e*) definition write_ram :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(unit),'e)monad " where " write_ram addrsize size1 hexRAM address value1 = ( - (write_mem_ea instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain address size1 \<then> - write_mem_val instance_Sail_values_Bitvector_Machine_word_mword_dict value1) \<bind> (\<lambda>x . (case x of _ => return () )) )" + write_mem_val instance_Sail2_values_Bitvector_Machine_word_mword_dict value1 \<bind> (\<lambda>x . (case x of _ => return () )) )" (*val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) definition read_ram :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where " read_ram addrsize size1 hexRAM address = ( - read_mem instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict Read_plain address size1 )" + read_mem instance_Sail2_values_Bitvector_Machine_word_mword_dict instance_Sail2_values_Bitvector_Machine_word_mword_dict Read_plain address size1 )" + + +(*val load_reservation : forall 'a. Size 'a => bitvector 'a -> unit*) +definition load_reservation :: "('a::len)Word.word \<Rightarrow> unit " where + " load_reservation addr = ( () )" -definition speculate_conditional_success :: " unit \<Rightarrow>('b,(bool),'a)monad " where +definition speculate_conditional_success :: " 'c \<Rightarrow>('b,(bool),'a)monad " where " speculate_conditional_success _ = ( excl_result () )" -(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> bitvector 'a*) -definition get_slice_int0 :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where - " get_slice_int0 len n lo = ( - (* TODO: Is this the intended behaviour? *) - (let hi = ((lo + len) -( 1 :: int)) in - (let bits = (bits_of_int (hi +( 1 :: int)) n) in - of_bits_failwith instance_Sail_values_Bitvector_Machine_word_mword_dict (subrange_list False bits hi lo))))" +definition cancel_reservation :: " unit \<Rightarrow> unit " where + " cancel_reservation _ = ( () )" + + +(*val plat_ram_base : forall 'a. Size 'a => unit -> bitvector 'a*) +definition plat_ram_base :: " unit \<Rightarrow>('a::len)Word.word " where + " plat_ram_base _ = ( Word.word_of_int(( 0 :: int)))" + + +(*val plat_ram_size : forall 'a. Size 'a => unit -> bitvector 'a*) +definition plat_ram_size :: " unit \<Rightarrow>('a::len)Word.word " where + " plat_ram_size _ = ( Word.word_of_int(( 0 :: int)))" + + +(*val plat_rom_base : forall 'a. Size 'a => unit -> bitvector 'a*) +definition plat_rom_base :: " unit \<Rightarrow>('a::len)Word.word " where + " plat_rom_base _ = ( Word.word_of_int(( 0 :: int)))" + + +(*val plat_rom_size : forall 'a. Size 'a => unit -> bitvector 'a*) +definition plat_rom_size :: " unit \<Rightarrow>('a::len)Word.word " where + " plat_rom_size _ = ( Word.word_of_int(( 0 :: int)))" + + +(*val plat_clint_base : forall 'a. Size 'a => unit -> bitvector 'a*) +definition plat_clint_base :: " unit \<Rightarrow>('a::len)Word.word " where + " plat_clint_base _ = ( Word.word_of_int(( 0 :: int)))" + + +(*val plat_clint_size : forall 'a. Size 'a => unit -> bitvector 'a*) +definition plat_clint_size :: " unit \<Rightarrow>('a::len)Word.word " where + " plat_clint_size _ = ( Word.word_of_int(( 0 :: int)))" + + +(*val plat_enable_dirty_update : unit -> bool*) +definition plat_enable_dirty_update :: " unit \<Rightarrow> bool " where + " plat_enable_dirty_update _ = ( False )" + + +(*val plat_enable_misaligned_access : unit -> bool*) +definition plat_enable_misaligned_access :: " unit \<Rightarrow> bool " where + " plat_enable_misaligned_access _ = ( False )" + + +(*val plat_insns_per_tick : unit -> integer*) +definition plat_insns_per_tick :: " unit \<Rightarrow> int " where + " plat_insns_per_tick _ = (( 1 :: int))" + + +(*val plat_htif_tohost : forall 'a. Size 'a => unit -> bitvector 'a*) +definition plat_htif_tohost :: " unit \<Rightarrow>('a::len)Word.word " where + " plat_htif_tohost _ = ( Word.word_of_int(( 0 :: int)))" + + +(*val plat_term_write : forall 'a. Size 'a => bitvector 'a -> unit*) +definition plat_term_write :: "('a::len)Word.word \<Rightarrow> unit " where + " plat_term_write _ = ( () )" + + +(*val plat_term_read : forall 'a. Size 'a => unit -> bitvector 'a*) +definition plat_term_read :: " unit \<Rightarrow>('a::len)Word.word " where + " plat_term_read _ = ( Word.word_of_int(( 0 :: int)))" (*val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*) @@ -116,11 +219,21 @@ definition shift_bits_left :: "('a::len)Word.word \<Rightarrow>('b::len)Word.wo (*val print_string : string -> string -> unit*) definition print_string :: " string \<Rightarrow> string \<Rightarrow> unit " where - " print_string msg s = ( prerr_endline (msg @ s))" + " print_string msg s = ( () )" + (* print_endline (msg ^ s) *) + +(*val prerr_string : string -> string -> unit*) +definition prerr_string :: " string \<Rightarrow> string \<Rightarrow> unit " where + " prerr_string msg s = ( prerr_endline (msg @ s))" + + +(*val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*) +definition prerr_bits :: " string \<Rightarrow>('a::len)Word.word \<Rightarrow> unit " where + " prerr_bits msg bs = ( prerr_endline (msg @ (show_bitlist (List.map bitU_of_bool (Word.to_bl bs)))))" (*val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*) definition print_bits :: " string \<Rightarrow>('a::len)Word.word \<Rightarrow> unit " where - " print_bits msg bs = ( prerr_endline (msg @ (show_bitlist (List.map bitU_of_bool (Word.to_bl bs)))))" - + " print_bits msg bs = ( () )" + (* print_endline (msg ^ (show_bitlist (bits_of bs))) *) end diff --git a/snapshots/isabelle/riscv/Riscv_lemmas.thy b/snapshots/isabelle/riscv/Riscv_lemmas.thy index 108208ca..cb159d68 100644 --- a/snapshots/isabelle/riscv/Riscv_lemmas.thy +++ b/snapshots/isabelle/riscv/Riscv_lemmas.thy @@ -1,19 +1,28 @@ theory Riscv_lemmas imports - Sail.Sail_values_lemmas - Sail.State_lemmas + Sail.Sail2_values_lemmas + Sail.Sail2_state_lemmas Riscv begin -abbreviation "liftS \<equiv> liftState (get_regval, set_regval)" +abbreviation liftS ("\<lbrakk>_\<rbrakk>\<^sub>S") where "liftS \<equiv> liftState (get_regval, set_regval)" -lemmas register_defs = get_regval_def set_regval_def tlb39_ref_def tselect_ref_def stval_ref_def +lemmas register_defs = get_regval_def set_regval_def tlb39_ref_def htif_exit_code_ref_def + htif_done_ref_def htif_tohost_ref_def mtimecmp_ref_def tselect_ref_def stval_ref_def scause_ref_def sepc_ref_def sscratch_ref_def stvec_ref_def satp_ref_def sideleg_ref_def sedeleg_ref_def pmpcfg0_ref_def pmpaddr0_ref_def mhartid_ref_def marchid_ref_def mimpid_ref_def - mvendorid_ref_def minstret_ref_def mtime_ref_def mcycle_ref_def mscratch_ref_def mtval_ref_def - mepc_ref_def mcause_ref_def mtvec_ref_def medeleg_ref_def mideleg_ref_def mie_ref_def mip_ref_def - mstatus_ref_def misa_ref_def cur_inst_ref_def cur_privilege_ref_def Xs_ref_def nextPC_ref_def - PC_ref_def + mvendorid_ref_def minstret_written_ref_def minstret_ref_def mtime_ref_def mcycle_ref_def + scounteren_ref_def mcounteren_ref_def mscratch_ref_def mtval_ref_def mepc_ref_def mcause_ref_def + mtvec_ref_def medeleg_ref_def mideleg_ref_def mie_ref_def mip_ref_def mstatus_ref_def misa_ref_def + cur_inst_ref_def cur_privilege_ref_def x31_ref_def x30_ref_def x29_ref_def x28_ref_def x27_ref_def + x26_ref_def x25_ref_def x24_ref_def x23_ref_def x22_ref_def x21_ref_def x20_ref_def x19_ref_def + x18_ref_def x17_ref_def x16_ref_def x15_ref_def x14_ref_def x13_ref_def x12_ref_def x11_ref_def + x10_ref_def x9_ref_def x8_ref_def x7_ref_def x6_ref_def x5_ref_def x4_ref_def x3_ref_def + x2_ref_def x1_ref_def Xs_ref_def nextPC_ref_def PC_ref_def + +lemma regval_Counteren[simp]: + "Counteren_of_regval (regval_of_Counteren v) = Some v" + by (auto simp: regval_of_Counteren_def) lemma regval_Mcause[simp]: "Mcause_of_regval (regval_of_Mcause v) = Some v" @@ -55,6 +64,10 @@ lemma regval_TLB39_Entry[simp]: "TLB39_Entry_of_regval (regval_of_TLB39_Entry v) = Some v" by (auto simp: regval_of_TLB39_Entry_def) +lemma regval_bool[simp]: + "bool_of_regval (regval_of_bool v) = Some v" + by (auto simp: regval_of_bool_def) + lemma regval_vector_64_dec_bit[simp]: "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v" by (auto simp: regval_of_vector_64_dec_bit_def) @@ -80,284 +93,588 @@ proof - with assms show ?thesis by (induction v) (auto simp: list_of_regval_def regval_of_list_def) qed -lemma liftS_read_reg_tlb39[simp]: - "liftS (read_reg tlb39_ref) = readS (tlb39 \<circ> regstate)" +lemma liftS_read_reg_tlb39[liftState_simp]: + "\<lbrakk>read_reg tlb39_ref\<rbrakk>\<^sub>S = readS (tlb39 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_tlb39[liftState_simp]: + "\<lbrakk>write_reg tlb39_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (tlb39_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_htif_exit_code[liftState_simp]: + "\<lbrakk>read_reg htif_exit_code_ref\<rbrakk>\<^sub>S = readS (htif_exit_code \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_htif_exit_code[liftState_simp]: + "\<lbrakk>write_reg htif_exit_code_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (htif_exit_code_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_htif_done[liftState_simp]: + "\<lbrakk>read_reg htif_done_ref\<rbrakk>\<^sub>S = readS (htif_done \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_htif_done[liftState_simp]: + "\<lbrakk>write_reg htif_done_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (htif_done_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_htif_tohost[liftState_simp]: + "\<lbrakk>read_reg htif_tohost_ref\<rbrakk>\<^sub>S = readS (htif_tohost \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_htif_tohost[liftState_simp]: + "\<lbrakk>write_reg htif_tohost_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (htif_tohost_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mtimecmp[liftState_simp]: + "\<lbrakk>read_reg mtimecmp_ref\<rbrakk>\<^sub>S = readS (mtimecmp \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mtimecmp[liftState_simp]: + "\<lbrakk>write_reg mtimecmp_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtimecmp_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_tselect[liftState_simp]: + "\<lbrakk>read_reg tselect_ref\<rbrakk>\<^sub>S = readS (tselect \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_tselect[liftState_simp]: + "\<lbrakk>write_reg tselect_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (tselect_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_stval[liftState_simp]: + "\<lbrakk>read_reg stval_ref\<rbrakk>\<^sub>S = readS (stval \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_stval[liftState_simp]: + "\<lbrakk>write_reg stval_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (stval_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_scause[liftState_simp]: + "\<lbrakk>read_reg scause_ref\<rbrakk>\<^sub>S = readS (scause \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_scause[liftState_simp]: + "\<lbrakk>write_reg scause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (scause_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_sepc[liftState_simp]: + "\<lbrakk>read_reg sepc_ref\<rbrakk>\<^sub>S = readS (sepc \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_sepc[liftState_simp]: + "\<lbrakk>write_reg sepc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sepc_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_sscratch[liftState_simp]: + "\<lbrakk>read_reg sscratch_ref\<rbrakk>\<^sub>S = readS (sscratch \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_sscratch[liftState_simp]: + "\<lbrakk>write_reg sscratch_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sscratch_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_stvec[liftState_simp]: + "\<lbrakk>read_reg stvec_ref\<rbrakk>\<^sub>S = readS (stvec \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_stvec[liftState_simp]: + "\<lbrakk>write_reg stvec_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (stvec_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_satp[liftState_simp]: + "\<lbrakk>read_reg satp_ref\<rbrakk>\<^sub>S = readS (satp \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_satp[liftState_simp]: + "\<lbrakk>write_reg satp_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (satp_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_sideleg[liftState_simp]: + "\<lbrakk>read_reg sideleg_ref\<rbrakk>\<^sub>S = readS (sideleg \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_sideleg[liftState_simp]: + "\<lbrakk>write_reg sideleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sideleg_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_sedeleg[liftState_simp]: + "\<lbrakk>read_reg sedeleg_ref\<rbrakk>\<^sub>S = readS (sedeleg \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_sedeleg[liftState_simp]: + "\<lbrakk>write_reg sedeleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (sedeleg_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_pmpcfg0[liftState_simp]: + "\<lbrakk>read_reg pmpcfg0_ref\<rbrakk>\<^sub>S = readS (pmpcfg0 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_pmpcfg0[liftState_simp]: + "\<lbrakk>write_reg pmpcfg0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpcfg0_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_pmpaddr0[liftState_simp]: + "\<lbrakk>read_reg pmpaddr0_ref\<rbrakk>\<^sub>S = readS (pmpaddr0 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_pmpaddr0[liftState_simp]: + "\<lbrakk>write_reg pmpaddr0_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (pmpaddr0_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mhartid[liftState_simp]: + "\<lbrakk>read_reg mhartid_ref\<rbrakk>\<^sub>S = readS (mhartid \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mhartid[liftState_simp]: + "\<lbrakk>write_reg mhartid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mhartid_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_marchid[liftState_simp]: + "\<lbrakk>read_reg marchid_ref\<rbrakk>\<^sub>S = readS (marchid \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_marchid[liftState_simp]: + "\<lbrakk>write_reg marchid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (marchid_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mimpid[liftState_simp]: + "\<lbrakk>read_reg mimpid_ref\<rbrakk>\<^sub>S = readS (mimpid \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mimpid[liftState_simp]: + "\<lbrakk>write_reg mimpid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mimpid_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mvendorid[liftState_simp]: + "\<lbrakk>read_reg mvendorid_ref\<rbrakk>\<^sub>S = readS (mvendorid \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mvendorid[liftState_simp]: + "\<lbrakk>write_reg mvendorid_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mvendorid_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_minstret_written[liftState_simp]: + "\<lbrakk>read_reg minstret_written_ref\<rbrakk>\<^sub>S = readS (minstret_written \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_minstret_written[liftState_simp]: + "\<lbrakk>write_reg minstret_written_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (minstret_written_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_minstret[liftState_simp]: + "\<lbrakk>read_reg minstret_ref\<rbrakk>\<^sub>S = readS (minstret \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_minstret[liftState_simp]: + "\<lbrakk>write_reg minstret_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (minstret_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mtime[liftState_simp]: + "\<lbrakk>read_reg mtime_ref\<rbrakk>\<^sub>S = readS (mtime \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mtime[liftState_simp]: + "\<lbrakk>write_reg mtime_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtime_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mcycle[liftState_simp]: + "\<lbrakk>read_reg mcycle_ref\<rbrakk>\<^sub>S = readS (mcycle \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mcycle[liftState_simp]: + "\<lbrakk>write_reg mcycle_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mcycle_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_scounteren[liftState_simp]: + "\<lbrakk>read_reg scounteren_ref\<rbrakk>\<^sub>S = readS (scounteren \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_scounteren[liftState_simp]: + "\<lbrakk>write_reg scounteren_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (scounteren_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mcounteren[liftState_simp]: + "\<lbrakk>read_reg mcounteren_ref\<rbrakk>\<^sub>S = readS (mcounteren \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mcounteren[liftState_simp]: + "\<lbrakk>write_reg mcounteren_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mcounteren_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mscratch[liftState_simp]: + "\<lbrakk>read_reg mscratch_ref\<rbrakk>\<^sub>S = readS (mscratch \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mscratch[liftState_simp]: + "\<lbrakk>write_reg mscratch_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mscratch_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mtval[liftState_simp]: + "\<lbrakk>read_reg mtval_ref\<rbrakk>\<^sub>S = readS (mtval \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mtval[liftState_simp]: + "\<lbrakk>write_reg mtval_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtval_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mepc[liftState_simp]: + "\<lbrakk>read_reg mepc_ref\<rbrakk>\<^sub>S = readS (mepc \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mepc[liftState_simp]: + "\<lbrakk>write_reg mepc_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mepc_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mcause[liftState_simp]: + "\<lbrakk>read_reg mcause_ref\<rbrakk>\<^sub>S = readS (mcause \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mcause[liftState_simp]: + "\<lbrakk>write_reg mcause_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mcause_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mtvec[liftState_simp]: + "\<lbrakk>read_reg mtvec_ref\<rbrakk>\<^sub>S = readS (mtvec \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mtvec[liftState_simp]: + "\<lbrakk>write_reg mtvec_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mtvec_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_medeleg[liftState_simp]: + "\<lbrakk>read_reg medeleg_ref\<rbrakk>\<^sub>S = readS (medeleg \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_medeleg[liftState_simp]: + "\<lbrakk>write_reg medeleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (medeleg_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mideleg[liftState_simp]: + "\<lbrakk>read_reg mideleg_ref\<rbrakk>\<^sub>S = readS (mideleg \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mideleg[liftState_simp]: + "\<lbrakk>write_reg mideleg_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mideleg_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mie[liftState_simp]: + "\<lbrakk>read_reg mie_ref\<rbrakk>\<^sub>S = readS (mie \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mie[liftState_simp]: + "\<lbrakk>write_reg mie_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mie_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mip[liftState_simp]: + "\<lbrakk>read_reg mip_ref\<rbrakk>\<^sub>S = readS (mip \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mip[liftState_simp]: + "\<lbrakk>write_reg mip_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mip_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mstatus[liftState_simp]: + "\<lbrakk>read_reg mstatus_ref\<rbrakk>\<^sub>S = readS (mstatus \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mstatus[liftState_simp]: + "\<lbrakk>write_reg mstatus_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (mstatus_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_misa[liftState_simp]: + "\<lbrakk>read_reg misa_ref\<rbrakk>\<^sub>S = readS (misa \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_misa[liftState_simp]: + "\<lbrakk>write_reg misa_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (misa_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_cur_inst[liftState_simp]: + "\<lbrakk>read_reg cur_inst_ref\<rbrakk>\<^sub>S = readS (cur_inst \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_cur_inst[liftState_simp]: + "\<lbrakk>write_reg cur_inst_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (cur_inst_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_cur_privilege[liftState_simp]: + "\<lbrakk>read_reg cur_privilege_ref\<rbrakk>\<^sub>S = readS (cur_privilege \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_tlb39[simp]: - "liftS (write_reg tlb39_ref v) = updateS (regstate_update (tlb39_update (\<lambda>_. v)))" +lemma liftS_write_reg_cur_privilege[liftState_simp]: + "\<lbrakk>write_reg cur_privilege_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (cur_privilege_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_tselect[simp]: - "liftS (read_reg tselect_ref) = readS (tselect \<circ> regstate)" +lemma liftS_read_reg_x31[liftState_simp]: + "\<lbrakk>read_reg x31_ref\<rbrakk>\<^sub>S = readS (x31 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_tselect[simp]: - "liftS (write_reg tselect_ref v) = updateS (regstate_update (tselect_update (\<lambda>_. v)))" +lemma liftS_write_reg_x31[liftState_simp]: + "\<lbrakk>write_reg x31_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x31_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_stval[simp]: - "liftS (read_reg stval_ref) = readS (stval \<circ> regstate)" +lemma liftS_read_reg_x30[liftState_simp]: + "\<lbrakk>read_reg x30_ref\<rbrakk>\<^sub>S = readS (x30 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_stval[simp]: - "liftS (write_reg stval_ref v) = updateS (regstate_update (stval_update (\<lambda>_. v)))" +lemma liftS_write_reg_x30[liftState_simp]: + "\<lbrakk>write_reg x30_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x30_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_scause[simp]: - "liftS (read_reg scause_ref) = readS (scause \<circ> regstate)" +lemma liftS_read_reg_x29[liftState_simp]: + "\<lbrakk>read_reg x29_ref\<rbrakk>\<^sub>S = readS (x29 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_scause[simp]: - "liftS (write_reg scause_ref v) = updateS (regstate_update (scause_update (\<lambda>_. v)))" +lemma liftS_write_reg_x29[liftState_simp]: + "\<lbrakk>write_reg x29_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x29_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_sepc[simp]: - "liftS (read_reg sepc_ref) = readS (sepc \<circ> regstate)" +lemma liftS_read_reg_x28[liftState_simp]: + "\<lbrakk>read_reg x28_ref\<rbrakk>\<^sub>S = readS (x28 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_sepc[simp]: - "liftS (write_reg sepc_ref v) = updateS (regstate_update (sepc_update (\<lambda>_. v)))" +lemma liftS_write_reg_x28[liftState_simp]: + "\<lbrakk>write_reg x28_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x28_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_sscratch[simp]: - "liftS (read_reg sscratch_ref) = readS (sscratch \<circ> regstate)" +lemma liftS_read_reg_x27[liftState_simp]: + "\<lbrakk>read_reg x27_ref\<rbrakk>\<^sub>S = readS (x27 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_sscratch[simp]: - "liftS (write_reg sscratch_ref v) = updateS (regstate_update (sscratch_update (\<lambda>_. v)))" +lemma liftS_write_reg_x27[liftState_simp]: + "\<lbrakk>write_reg x27_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x27_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_stvec[simp]: - "liftS (read_reg stvec_ref) = readS (stvec \<circ> regstate)" +lemma liftS_read_reg_x26[liftState_simp]: + "\<lbrakk>read_reg x26_ref\<rbrakk>\<^sub>S = readS (x26 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_stvec[simp]: - "liftS (write_reg stvec_ref v) = updateS (regstate_update (stvec_update (\<lambda>_. v)))" +lemma liftS_write_reg_x26[liftState_simp]: + "\<lbrakk>write_reg x26_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x26_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_satp[simp]: - "liftS (read_reg satp_ref) = readS (satp \<circ> regstate)" +lemma liftS_read_reg_x25[liftState_simp]: + "\<lbrakk>read_reg x25_ref\<rbrakk>\<^sub>S = readS (x25 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_satp[simp]: - "liftS (write_reg satp_ref v) = updateS (regstate_update (satp_update (\<lambda>_. v)))" +lemma liftS_write_reg_x25[liftState_simp]: + "\<lbrakk>write_reg x25_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x25_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_sideleg[simp]: - "liftS (read_reg sideleg_ref) = readS (sideleg \<circ> regstate)" +lemma liftS_read_reg_x24[liftState_simp]: + "\<lbrakk>read_reg x24_ref\<rbrakk>\<^sub>S = readS (x24 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_sideleg[simp]: - "liftS (write_reg sideleg_ref v) = updateS (regstate_update (sideleg_update (\<lambda>_. v)))" +lemma liftS_write_reg_x24[liftState_simp]: + "\<lbrakk>write_reg x24_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x24_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_sedeleg[simp]: - "liftS (read_reg sedeleg_ref) = readS (sedeleg \<circ> regstate)" +lemma liftS_read_reg_x23[liftState_simp]: + "\<lbrakk>read_reg x23_ref\<rbrakk>\<^sub>S = readS (x23 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_sedeleg[simp]: - "liftS (write_reg sedeleg_ref v) = updateS (regstate_update (sedeleg_update (\<lambda>_. v)))" +lemma liftS_write_reg_x23[liftState_simp]: + "\<lbrakk>write_reg x23_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x23_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_pmpcfg0[simp]: - "liftS (read_reg pmpcfg0_ref) = readS (pmpcfg0 \<circ> regstate)" +lemma liftS_read_reg_x22[liftState_simp]: + "\<lbrakk>read_reg x22_ref\<rbrakk>\<^sub>S = readS (x22 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_pmpcfg0[simp]: - "liftS (write_reg pmpcfg0_ref v) = updateS (regstate_update (pmpcfg0_update (\<lambda>_. v)))" +lemma liftS_write_reg_x22[liftState_simp]: + "\<lbrakk>write_reg x22_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x22_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_pmpaddr0[simp]: - "liftS (read_reg pmpaddr0_ref) = readS (pmpaddr0 \<circ> regstate)" +lemma liftS_read_reg_x21[liftState_simp]: + "\<lbrakk>read_reg x21_ref\<rbrakk>\<^sub>S = readS (x21 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_pmpaddr0[simp]: - "liftS (write_reg pmpaddr0_ref v) = updateS (regstate_update (pmpaddr0_update (\<lambda>_. v)))" +lemma liftS_write_reg_x21[liftState_simp]: + "\<lbrakk>write_reg x21_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x21_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mhartid[simp]: - "liftS (read_reg mhartid_ref) = readS (mhartid \<circ> regstate)" +lemma liftS_read_reg_x20[liftState_simp]: + "\<lbrakk>read_reg x20_ref\<rbrakk>\<^sub>S = readS (x20 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mhartid[simp]: - "liftS (write_reg mhartid_ref v) = updateS (regstate_update (mhartid_update (\<lambda>_. v)))" +lemma liftS_write_reg_x20[liftState_simp]: + "\<lbrakk>write_reg x20_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x20_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_marchid[simp]: - "liftS (read_reg marchid_ref) = readS (marchid \<circ> regstate)" +lemma liftS_read_reg_x19[liftState_simp]: + "\<lbrakk>read_reg x19_ref\<rbrakk>\<^sub>S = readS (x19 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_marchid[simp]: - "liftS (write_reg marchid_ref v) = updateS (regstate_update (marchid_update (\<lambda>_. v)))" +lemma liftS_write_reg_x19[liftState_simp]: + "\<lbrakk>write_reg x19_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x19_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mimpid[simp]: - "liftS (read_reg mimpid_ref) = readS (mimpid \<circ> regstate)" +lemma liftS_read_reg_x18[liftState_simp]: + "\<lbrakk>read_reg x18_ref\<rbrakk>\<^sub>S = readS (x18 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mimpid[simp]: - "liftS (write_reg mimpid_ref v) = updateS (regstate_update (mimpid_update (\<lambda>_. v)))" +lemma liftS_write_reg_x18[liftState_simp]: + "\<lbrakk>write_reg x18_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x18_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mvendorid[simp]: - "liftS (read_reg mvendorid_ref) = readS (mvendorid \<circ> regstate)" +lemma liftS_read_reg_x17[liftState_simp]: + "\<lbrakk>read_reg x17_ref\<rbrakk>\<^sub>S = readS (x17 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mvendorid[simp]: - "liftS (write_reg mvendorid_ref v) = updateS (regstate_update (mvendorid_update (\<lambda>_. v)))" +lemma liftS_write_reg_x17[liftState_simp]: + "\<lbrakk>write_reg x17_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x17_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_minstret[simp]: - "liftS (read_reg minstret_ref) = readS (minstret \<circ> regstate)" +lemma liftS_read_reg_x16[liftState_simp]: + "\<lbrakk>read_reg x16_ref\<rbrakk>\<^sub>S = readS (x16 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_minstret[simp]: - "liftS (write_reg minstret_ref v) = updateS (regstate_update (minstret_update (\<lambda>_. v)))" +lemma liftS_write_reg_x16[liftState_simp]: + "\<lbrakk>write_reg x16_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x16_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mtime[simp]: - "liftS (read_reg mtime_ref) = readS (mtime \<circ> regstate)" +lemma liftS_read_reg_x15[liftState_simp]: + "\<lbrakk>read_reg x15_ref\<rbrakk>\<^sub>S = readS (x15 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mtime[simp]: - "liftS (write_reg mtime_ref v) = updateS (regstate_update (mtime_update (\<lambda>_. v)))" +lemma liftS_write_reg_x15[liftState_simp]: + "\<lbrakk>write_reg x15_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x15_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mcycle[simp]: - "liftS (read_reg mcycle_ref) = readS (mcycle \<circ> regstate)" +lemma liftS_read_reg_x14[liftState_simp]: + "\<lbrakk>read_reg x14_ref\<rbrakk>\<^sub>S = readS (x14 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mcycle[simp]: - "liftS (write_reg mcycle_ref v) = updateS (regstate_update (mcycle_update (\<lambda>_. v)))" +lemma liftS_write_reg_x14[liftState_simp]: + "\<lbrakk>write_reg x14_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x14_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mscratch[simp]: - "liftS (read_reg mscratch_ref) = readS (mscratch \<circ> regstate)" +lemma liftS_read_reg_x13[liftState_simp]: + "\<lbrakk>read_reg x13_ref\<rbrakk>\<^sub>S = readS (x13 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mscratch[simp]: - "liftS (write_reg mscratch_ref v) = updateS (regstate_update (mscratch_update (\<lambda>_. v)))" +lemma liftS_write_reg_x13[liftState_simp]: + "\<lbrakk>write_reg x13_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x13_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mtval[simp]: - "liftS (read_reg mtval_ref) = readS (mtval \<circ> regstate)" +lemma liftS_read_reg_x12[liftState_simp]: + "\<lbrakk>read_reg x12_ref\<rbrakk>\<^sub>S = readS (x12 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mtval[simp]: - "liftS (write_reg mtval_ref v) = updateS (regstate_update (mtval_update (\<lambda>_. v)))" +lemma liftS_write_reg_x12[liftState_simp]: + "\<lbrakk>write_reg x12_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x12_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mepc[simp]: - "liftS (read_reg mepc_ref) = readS (mepc \<circ> regstate)" +lemma liftS_read_reg_x11[liftState_simp]: + "\<lbrakk>read_reg x11_ref\<rbrakk>\<^sub>S = readS (x11 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mepc[simp]: - "liftS (write_reg mepc_ref v) = updateS (regstate_update (mepc_update (\<lambda>_. v)))" +lemma liftS_write_reg_x11[liftState_simp]: + "\<lbrakk>write_reg x11_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x11_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mcause[simp]: - "liftS (read_reg mcause_ref) = readS (mcause \<circ> regstate)" +lemma liftS_read_reg_x10[liftState_simp]: + "\<lbrakk>read_reg x10_ref\<rbrakk>\<^sub>S = readS (x10 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mcause[simp]: - "liftS (write_reg mcause_ref v) = updateS (regstate_update (mcause_update (\<lambda>_. v)))" +lemma liftS_write_reg_x10[liftState_simp]: + "\<lbrakk>write_reg x10_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x10_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mtvec[simp]: - "liftS (read_reg mtvec_ref) = readS (mtvec \<circ> regstate)" +lemma liftS_read_reg_x9[liftState_simp]: + "\<lbrakk>read_reg x9_ref\<rbrakk>\<^sub>S = readS (x9 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mtvec[simp]: - "liftS (write_reg mtvec_ref v) = updateS (regstate_update (mtvec_update (\<lambda>_. v)))" +lemma liftS_write_reg_x9[liftState_simp]: + "\<lbrakk>write_reg x9_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x9_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_medeleg[simp]: - "liftS (read_reg medeleg_ref) = readS (medeleg \<circ> regstate)" +lemma liftS_read_reg_x8[liftState_simp]: + "\<lbrakk>read_reg x8_ref\<rbrakk>\<^sub>S = readS (x8 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_medeleg[simp]: - "liftS (write_reg medeleg_ref v) = updateS (regstate_update (medeleg_update (\<lambda>_. v)))" +lemma liftS_write_reg_x8[liftState_simp]: + "\<lbrakk>write_reg x8_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x8_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mideleg[simp]: - "liftS (read_reg mideleg_ref) = readS (mideleg \<circ> regstate)" +lemma liftS_read_reg_x7[liftState_simp]: + "\<lbrakk>read_reg x7_ref\<rbrakk>\<^sub>S = readS (x7 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mideleg[simp]: - "liftS (write_reg mideleg_ref v) = updateS (regstate_update (mideleg_update (\<lambda>_. v)))" +lemma liftS_write_reg_x7[liftState_simp]: + "\<lbrakk>write_reg x7_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x7_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mie[simp]: - "liftS (read_reg mie_ref) = readS (mie \<circ> regstate)" +lemma liftS_read_reg_x6[liftState_simp]: + "\<lbrakk>read_reg x6_ref\<rbrakk>\<^sub>S = readS (x6 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mie[simp]: - "liftS (write_reg mie_ref v) = updateS (regstate_update (mie_update (\<lambda>_. v)))" +lemma liftS_write_reg_x6[liftState_simp]: + "\<lbrakk>write_reg x6_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x6_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mip[simp]: - "liftS (read_reg mip_ref) = readS (mip \<circ> regstate)" +lemma liftS_read_reg_x5[liftState_simp]: + "\<lbrakk>read_reg x5_ref\<rbrakk>\<^sub>S = readS (x5 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mip[simp]: - "liftS (write_reg mip_ref v) = updateS (regstate_update (mip_update (\<lambda>_. v)))" +lemma liftS_write_reg_x5[liftState_simp]: + "\<lbrakk>write_reg x5_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x5_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_mstatus[simp]: - "liftS (read_reg mstatus_ref) = readS (mstatus \<circ> regstate)" +lemma liftS_read_reg_x4[liftState_simp]: + "\<lbrakk>read_reg x4_ref\<rbrakk>\<^sub>S = readS (x4 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_mstatus[simp]: - "liftS (write_reg mstatus_ref v) = updateS (regstate_update (mstatus_update (\<lambda>_. v)))" +lemma liftS_write_reg_x4[liftState_simp]: + "\<lbrakk>write_reg x4_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x4_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_misa[simp]: - "liftS (read_reg misa_ref) = readS (misa \<circ> regstate)" +lemma liftS_read_reg_x3[liftState_simp]: + "\<lbrakk>read_reg x3_ref\<rbrakk>\<^sub>S = readS (x3 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_misa[simp]: - "liftS (write_reg misa_ref v) = updateS (regstate_update (misa_update (\<lambda>_. v)))" +lemma liftS_write_reg_x3[liftState_simp]: + "\<lbrakk>write_reg x3_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x3_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_cur_inst[simp]: - "liftS (read_reg cur_inst_ref) = readS (cur_inst \<circ> regstate)" +lemma liftS_read_reg_x2[liftState_simp]: + "\<lbrakk>read_reg x2_ref\<rbrakk>\<^sub>S = readS (x2 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_cur_inst[simp]: - "liftS (write_reg cur_inst_ref v) = updateS (regstate_update (cur_inst_update (\<lambda>_. v)))" +lemma liftS_write_reg_x2[liftState_simp]: + "\<lbrakk>write_reg x2_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x2_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_cur_privilege[simp]: - "liftS (read_reg cur_privilege_ref) = readS (cur_privilege \<circ> regstate)" +lemma liftS_read_reg_x1[liftState_simp]: + "\<lbrakk>read_reg x1_ref\<rbrakk>\<^sub>S = readS (x1 \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_cur_privilege[simp]: - "liftS (write_reg cur_privilege_ref v) = updateS (regstate_update (cur_privilege_update (\<lambda>_. v)))" +lemma liftS_write_reg_x1[liftState_simp]: + "\<lbrakk>write_reg x1_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (x1_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_Xs[simp]: - "liftS (read_reg Xs_ref) = readS (Xs \<circ> regstate)" +lemma liftS_read_reg_Xs[liftState_simp]: + "\<lbrakk>read_reg Xs_ref\<rbrakk>\<^sub>S = readS (Xs \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_Xs[simp]: - "liftS (write_reg Xs_ref v) = updateS (regstate_update (Xs_update (\<lambda>_. v)))" +lemma liftS_write_reg_Xs[liftState_simp]: + "\<lbrakk>write_reg Xs_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (Xs_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_nextPC[simp]: - "liftS (read_reg nextPC_ref) = readS (nextPC \<circ> regstate)" +lemma liftS_read_reg_nextPC[liftState_simp]: + "\<lbrakk>read_reg nextPC_ref\<rbrakk>\<^sub>S = readS (nextPC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_nextPC[simp]: - "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\<lambda>_. v)))" +lemma liftS_write_reg_nextPC[liftState_simp]: + "\<lbrakk>write_reg nextPC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (nextPC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) -lemma liftS_read_reg_PC[simp]: - "liftS (read_reg PC_ref) = readS (PC \<circ> regstate)" +lemma liftS_read_reg_PC[liftState_simp]: + "\<lbrakk>read_reg PC_ref\<rbrakk>\<^sub>S = readS (PC \<circ> regstate)" by (auto simp: liftState_read_reg_readS register_defs) -lemma liftS_write_reg_PC[simp]: - "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\<lambda>_. v)))" +lemma liftS_write_reg_PC[liftState_simp]: + "\<lbrakk>write_reg PC_ref v\<rbrakk>\<^sub>S = updateS (regstate_update (PC_update (\<lambda>_. v)))" by (auto simp: liftState_write_reg_updateS register_defs) end diff --git a/snapshots/isabelle/riscv/Riscv_types.thy b/snapshots/isabelle/riscv/Riscv_types.thy index 71dce180..78328442 100644 --- a/snapshots/isabelle/riscv/Riscv_types.thy +++ b/snapshots/isabelle/riscv/Riscv_types.thy @@ -5,23 +5,23 @@ theory "Riscv_types" imports Main "Lem_pervasives_extra" - "Sail_instr_kinds" - "Sail_values" - "Sail_operators_mwords" - "Prompt_monad" - "Prompt" - "State" + "Sail2_instr_kinds" + "Sail2_values" + "Sail2_operators_mwords" + "Sail2_prompt_monad" + "Sail2_prompt" + "Sail2_string" begin (*Generated by Sail from riscv.*) (*open import Pervasives_extra*) -(*open import Sail_instr_kinds*) -(*open import Sail_values*) -(*open import Sail_operators_mwords*) -(*open import Prompt_monad*) -(*open import Prompt*) -(*open import State*) +(*open import Sail2_instr_kinds*) +(*open import Sail2_values*) +(*open import Sail2_string*) +(*open import Sail2_operators_mwords*) +(*open import Sail2_prompt_monad*) +(*open import Sail2_prompt*) type_synonym 'n bits =" ( 'n::len)Word.word " @@ -109,8 +109,7 @@ datatype TrapVectorMode = TV_Direct | TV_Vector | TV_Reserved -datatype exception = - Error_not_implemented " (string)" | Error_EBREAK " (unit)" | Error_internal_error " (unit)" +datatype exception = Error_not_implemented " (string)" | Error_internal_error " (unit)" @@ -174,55 +173,68 @@ datatype word_width = BYTE | HALF | WORD | DOUBLE -datatype 'a MemoryOpResult = MemValue " ('a)" | MemException " (ExceptionType)" +record Misa = + Misa_Misa_chunk_0 ::" 64 Word.word " -datatype Misa = Mk_Misa " ( 64 Word.word)" +record SV39_PTE = + SV39_PTE_SV39_PTE_chunk_0 ::" 64 Word.word " -datatype SV39_PTE = Mk_SV39_PTE " ( 64 Word.word)" +record PTE_Bits = + PTE_Bits_PTE_Bits_chunk_0 ::" 8 Word.word " -datatype PTE_Bits = Mk_PTE_Bits " ( 8 Word.word)" +record Mstatus = + Mstatus_Mstatus_chunk_0 ::" 64 Word.word " -datatype Mstatus = Mk_Mstatus " ( 64 Word.word)" +record Sstatus = + Sstatus_Sstatus_chunk_0 ::" 64 Word.word " -datatype Sstatus = Mk_Sstatus " ( 64 Word.word)" +record Minterrupts = + Minterrupts_Minterrupts_chunk_0 ::" 64 Word.word " -datatype Minterrupts = Mk_Minterrupts " ( 64 Word.word)" +record Sinterrupts = + Sinterrupts_Sinterrupts_chunk_0 ::" 64 Word.word " -datatype Sinterrupts = Mk_Sinterrupts " ( 64 Word.word)" +record Medeleg = + Medeleg_Medeleg_chunk_0 ::" 64 Word.word " -datatype Medeleg = Mk_Medeleg " ( 64 Word.word)" +record Sedeleg = + Sedeleg_Sedeleg_chunk_0 ::" 64 Word.word " -datatype Sedeleg = Mk_Sedeleg " ( 64 Word.word)" +record Mtvec = + Mtvec_Mtvec_chunk_0 ::" 64 Word.word " -datatype Mtvec = Mk_Mtvec " ( 64 Word.word)" +record Satp64 = + Satp64_Satp64_chunk_0 ::" 64 Word.word " -datatype Satp64 = Mk_Satp64 " ( 64 Word.word)" +record Mcause = + Mcause_Mcause_chunk_0 ::" 64 Word.word " -datatype Mcause = Mk_Mcause " ( 64 Word.word)" +record Counteren = + Counteren_Counteren_chunk_0 ::" 32 Word.word " @@ -237,6 +249,15 @@ datatype ctl_result = CTL_TRAP " (sync_exception)" | CTL_SRET " (unit)" | CTL +datatype 'a MemoryOpResult = MemValue " ('a)" | MemException " (ExceptionType)" + + + +record htif_cmd = + htif_cmd_htif_cmd_chunk_0 ::" 64 Word.word " + + + type_synonym pteAttribs =" 8 bits " datatype PTW_Error = PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update @@ -249,11 +270,13 @@ type_synonym paddr39 =" 56 bits " type_synonym pte39 =" xlenbits " -datatype SV39_Vaddr = Mk_SV39_Vaddr " ( 39 Word.word)" +record SV39_Vaddr = + SV39_Vaddr_SV39_Vaddr_chunk_0 ::" 39 Word.word " -datatype SV39_Paddr = Mk_SV39_Paddr " ( 56 Word.word)" +record SV39_Paddr = + SV39_Paddr_SV39_Paddr_chunk_0 ::" 56 Word.word " @@ -326,7 +349,6 @@ datatype (plugins only: size) ast = | AMO " ((amoop * bool * bool * regbits * regbits * word_width * regbits))" | CSR " (( 12 bits * regbits * regbits * bool * csrop))" | NOP " (unit)" - | ILLEGAL " (unit)" | C_ADDI4SPN " ((cregbits * 8 bits))" | C_LW " (( 5 bits * cregbits * cregbits))" | C_LD " (( 5 bits * cregbits * cregbits))" @@ -359,6 +381,10 @@ datatype (plugins only: size) ast = | C_JALR " (regbits)" | C_MV " ((regbits * regbits))" | C_ADD " ((regbits * regbits))" + | STOP_FETCHING " (unit)" + | THREAD_START " (unit)" + | ILLEGAL " (word0)" + | C_ILLEGAL " (unit)" @@ -366,10 +392,44 @@ datatype FetchResult = F_Base " (word0)" | F_RVC " (half)" | F_Error " ((Exce +datatype regfp = + RFull " (string)" + | RSlice " ((string * ii * ii))" + | RSliceBit " ((string * ii))" + | RField " ((string * string))" + + + +type_synonym regfps =" regfp list " + +datatype niafp = + NIAFP_successor " (unit)" + | NIAFP_concrete_address " ( 64 bits)" + | NIAFP_indirect_address " (unit)" + + + +type_synonym niafps =" niafp list " + +datatype diafp = DIAFP_none " (unit)" | DIAFP_concrete " ( 64 bits)" | DIAFP_reg " (regfp)" + + + + + + + + + + + + + datatype register_value = Regval_vector " ((ii * bool * register_value list))" | Regval_list " ( register_value list)" | Regval_option " ( register_value option)" + | Regval_Counteren " (Counteren)" | Regval_Mcause " (Mcause)" | Regval_Medeleg " (Medeleg)" | Regval_Minterrupts " (Minterrupts)" @@ -380,6 +440,7 @@ datatype register_value = | Regval_Sedeleg " (Sedeleg)" | Regval_Sinterrupts " (Sinterrupts)" | Regval_TLB39_Entry " (TLB39_Entry)" + | Regval_bool " (bool)" | Regval_vector_64_dec_bit " ( 64 Word.word)" @@ -388,6 +449,14 @@ record regstate = tlb39 ::" TLB39_Entry option " + htif_exit_code ::" 64 Word.word " + + htif_done ::" bool " + + htif_tohost ::" 64 Word.word " + + mtimecmp ::" 64 Word.word " + tselect ::" 64 Word.word " stval ::" 64 Word.word " @@ -418,12 +487,18 @@ record regstate = mvendorid ::" 64 Word.word " + minstret_written ::" bool " + minstret ::" 64 Word.word " mtime ::" 64 Word.word " mcycle ::" 64 Word.word " + scounteren ::" Counteren " + + mcounteren ::" Counteren " + mscratch ::" 64 Word.word " mtval ::" 64 Word.word " @@ -450,6 +525,68 @@ record regstate = cur_privilege ::" Privilege " + x31 ::" 64 Word.word " + + x30 ::" 64 Word.word " + + x29 ::" 64 Word.word " + + x28 ::" 64 Word.word " + + x27 ::" 64 Word.word " + + x26 ::" 64 Word.word " + + x25 ::" 64 Word.word " + + x24 ::" 64 Word.word " + + x23 ::" 64 Word.word " + + x22 ::" 64 Word.word " + + x21 ::" 64 Word.word " + + x20 ::" 64 Word.word " + + x19 ::" 64 Word.word " + + x18 ::" 64 Word.word " + + x17 ::" 64 Word.word " + + x16 ::" 64 Word.word " + + x15 ::" 64 Word.word " + + x14 ::" 64 Word.word " + + x13 ::" 64 Word.word " + + x12 ::" 64 Word.word " + + x11 ::" 64 Word.word " + + x10 ::" 64 Word.word " + + x9 ::" 64 Word.word " + + x8 ::" 64 Word.word " + + x7 ::" 64 Word.word " + + x6 ::" 64 Word.word " + + x5 ::" 64 Word.word " + + x4 ::" 64 Word.word " + + x3 ::" 64 Word.word " + + x2 ::" 64 Word.word " + + x1 ::" 64 Word.word " + Xs ::" ( 64 Word.word) list " nextPC ::" 64 Word.word " @@ -460,11 +597,24 @@ record regstate = +(*val Counteren_of_regval : register_value -> maybe Counteren*) + +fun Counteren_of_regval :: " register_value \<Rightarrow>(Counteren)option " where + " Counteren_of_regval (Regval_Counteren (v)) = ( Some v )" +|" Counteren_of_regval g__12 = ( None )" + + +(*val regval_of_Counteren : Counteren -> register_value*) + +definition regval_of_Counteren :: " Counteren \<Rightarrow> register_value " where + " regval_of_Counteren v = ( Regval_Counteren v )" + + (*val Mcause_of_regval : register_value -> maybe Mcause*) fun Mcause_of_regval :: " register_value \<Rightarrow>(Mcause)option " where " Mcause_of_regval (Regval_Mcause (v)) = ( Some v )" -|" Mcause_of_regval g__92 = ( None )" +|" Mcause_of_regval g__11 = ( None )" (*val regval_of_Mcause : Mcause -> register_value*) @@ -477,7 +627,7 @@ definition regval_of_Mcause :: " Mcause \<Rightarrow> register_value " where fun Medeleg_of_regval :: " register_value \<Rightarrow>(Medeleg)option " where " Medeleg_of_regval (Regval_Medeleg (v)) = ( Some v )" -|" Medeleg_of_regval g__91 = ( None )" +|" Medeleg_of_regval g__10 = ( None )" (*val regval_of_Medeleg : Medeleg -> register_value*) @@ -490,7 +640,7 @@ definition regval_of_Medeleg :: " Medeleg \<Rightarrow> register_value " where fun Minterrupts_of_regval :: " register_value \<Rightarrow>(Minterrupts)option " where " Minterrupts_of_regval (Regval_Minterrupts (v)) = ( Some v )" -|" Minterrupts_of_regval g__90 = ( None )" +|" Minterrupts_of_regval g__9 = ( None )" (*val regval_of_Minterrupts : Minterrupts -> register_value*) @@ -503,7 +653,7 @@ definition regval_of_Minterrupts :: " Minterrupts \<Rightarrow> register_value fun Misa_of_regval :: " register_value \<Rightarrow>(Misa)option " where " Misa_of_regval (Regval_Misa (v)) = ( Some v )" -|" Misa_of_regval g__89 = ( None )" +|" Misa_of_regval g__8 = ( None )" (*val regval_of_Misa : Misa -> register_value*) @@ -516,7 +666,7 @@ definition regval_of_Misa :: " Misa \<Rightarrow> register_value " where fun Mstatus_of_regval :: " register_value \<Rightarrow>(Mstatus)option " where " Mstatus_of_regval (Regval_Mstatus (v)) = ( Some v )" -|" Mstatus_of_regval g__88 = ( None )" +|" Mstatus_of_regval g__7 = ( None )" (*val regval_of_Mstatus : Mstatus -> register_value*) @@ -529,7 +679,7 @@ definition regval_of_Mstatus :: " Mstatus \<Rightarrow> register_value " where fun Mtvec_of_regval :: " register_value \<Rightarrow>(Mtvec)option " where " Mtvec_of_regval (Regval_Mtvec (v)) = ( Some v )" -|" Mtvec_of_regval g__87 = ( None )" +|" Mtvec_of_regval g__6 = ( None )" (*val regval_of_Mtvec : Mtvec -> register_value*) @@ -542,7 +692,7 @@ definition regval_of_Mtvec :: " Mtvec \<Rightarrow> register_value " where fun Privilege_of_regval :: " register_value \<Rightarrow>(Privilege)option " where " Privilege_of_regval (Regval_Privilege (v)) = ( Some v )" -|" Privilege_of_regval g__86 = ( None )" +|" Privilege_of_regval g__5 = ( None )" (*val regval_of_Privilege : Privilege -> register_value*) @@ -555,7 +705,7 @@ definition regval_of_Privilege :: " Privilege \<Rightarrow> register_value " w fun Sedeleg_of_regval :: " register_value \<Rightarrow>(Sedeleg)option " where " Sedeleg_of_regval (Regval_Sedeleg (v)) = ( Some v )" -|" Sedeleg_of_regval g__85 = ( None )" +|" Sedeleg_of_regval g__4 = ( None )" (*val regval_of_Sedeleg : Sedeleg -> register_value*) @@ -568,7 +718,7 @@ definition regval_of_Sedeleg :: " Sedeleg \<Rightarrow> register_value " where fun Sinterrupts_of_regval :: " register_value \<Rightarrow>(Sinterrupts)option " where " Sinterrupts_of_regval (Regval_Sinterrupts (v)) = ( Some v )" -|" Sinterrupts_of_regval g__84 = ( None )" +|" Sinterrupts_of_regval g__3 = ( None )" (*val regval_of_Sinterrupts : Sinterrupts -> register_value*) @@ -581,7 +731,7 @@ definition regval_of_Sinterrupts :: " Sinterrupts \<Rightarrow> register_value fun TLB39_Entry_of_regval :: " register_value \<Rightarrow>(TLB39_Entry)option " where " TLB39_Entry_of_regval (Regval_TLB39_Entry (v)) = ( Some v )" -|" TLB39_Entry_of_regval g__83 = ( None )" +|" TLB39_Entry_of_regval g__2 = ( None )" (*val regval_of_TLB39_Entry : TLB39_Entry -> register_value*) @@ -590,11 +740,24 @@ definition regval_of_TLB39_Entry :: " TLB39_Entry \<Rightarrow> register_value " regval_of_TLB39_Entry v = ( Regval_TLB39_Entry v )" +(*val bool_of_regval : register_value -> maybe bool*) + +fun bool_of_regval :: " register_value \<Rightarrow>(bool)option " where + " bool_of_regval (Regval_bool (v)) = ( Some v )" +|" bool_of_regval g__1 = ( None )" + + +(*val regval_of_bool : bool -> register_value*) + +definition regval_of_bool :: " bool \<Rightarrow> register_value " where + " regval_of_bool v = ( Regval_bool v )" + + (*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) fun vector_64_dec_bit_of_regval :: " register_value \<Rightarrow>((64)Word.word)option " where " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )" -|" vector_64_dec_bit_of_regval g__82 = ( None )" +|" vector_64_dec_bit_of_regval g__0 = ( None )" (*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) @@ -657,6 +820,42 @@ definition tlb39_ref :: "((regstate),(register_value),((TLB39_Entry)option))reg regval_of = (\<lambda> v . regval_of_option (\<lambda> v . regval_of_TLB39_Entry v) v) |) )" +definition htif_exit_code_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " htif_exit_code_ref = ( (| + name = (''htif_exit_code''), + read_from = (\<lambda> s . (htif_exit_code s)), + write_to = (\<lambda> v s . (( s (| htif_exit_code := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition htif_done_ref :: "((regstate),(register_value),(bool))register_ref " where + " htif_done_ref = ( (| + name = (''htif_done''), + read_from = (\<lambda> s . (htif_done s)), + write_to = (\<lambda> v s . (( s (| htif_done := v |)))), + of_regval = (\<lambda> v . bool_of_regval v), + regval_of = (\<lambda> v . regval_of_bool v) |) )" + + +definition htif_tohost_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " htif_tohost_ref = ( (| + name = (''htif_tohost''), + read_from = (\<lambda> s . (htif_tohost s)), + write_to = (\<lambda> v s . (( s (| htif_tohost := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition mtimecmp_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mtimecmp_ref = ( (| + name = (''mtimecmp''), + read_from = (\<lambda> s . (mtimecmp s)), + write_to = (\<lambda> v s . (( s (| mtimecmp := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + definition tselect_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where " tselect_ref = ( (| name = (''tselect''), @@ -792,6 +991,15 @@ definition mvendorid_ref :: "((regstate),(register_value),((64)Word.word))regis regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" +definition minstret_written_ref :: "((regstate),(register_value),(bool))register_ref " where + " minstret_written_ref = ( (| + name = (''minstret_written''), + read_from = (\<lambda> s . (minstret_written s)), + write_to = (\<lambda> v s . (( s (| minstret_written := v |)))), + of_regval = (\<lambda> v . bool_of_regval v), + regval_of = (\<lambda> v . regval_of_bool v) |) )" + + definition minstret_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where " minstret_ref = ( (| name = (''minstret''), @@ -819,6 +1027,24 @@ definition mcycle_ref :: "((regstate),(register_value),((64)Word.word))register regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" +definition scounteren_ref :: "((regstate),(register_value),(Counteren))register_ref " where + " scounteren_ref = ( (| + name = (''scounteren''), + read_from = (\<lambda> s . (scounteren s)), + write_to = (\<lambda> v s . (( s (| scounteren := v |)))), + of_regval = (\<lambda> v . Counteren_of_regval v), + regval_of = (\<lambda> v . regval_of_Counteren v) |) )" + + +definition mcounteren_ref :: "((regstate),(register_value),(Counteren))register_ref " where + " mcounteren_ref = ( (| + name = (''mcounteren''), + read_from = (\<lambda> s . (mcounteren s)), + write_to = (\<lambda> v s . (( s (| mcounteren := v |)))), + of_regval = (\<lambda> v . Counteren_of_regval v), + regval_of = (\<lambda> v . regval_of_Counteren v) |) )" + + definition mscratch_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where " mscratch_ref = ( (| name = (''mscratch''), @@ -936,6 +1162,285 @@ definition cur_privilege_ref :: "((regstate),(register_value),(Privilege))regis regval_of = (\<lambda> v . regval_of_Privilege v) |) )" +definition x31_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x31_ref = ( (| + name = (''x31''), + read_from = (\<lambda> s . (x31 s)), + write_to = (\<lambda> v s . (( s (| x31 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x30_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x30_ref = ( (| + name = (''x30''), + read_from = (\<lambda> s . (x30 s)), + write_to = (\<lambda> v s . (( s (| x30 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x29_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x29_ref = ( (| + name = (''x29''), + read_from = (\<lambda> s . (x29 s)), + write_to = (\<lambda> v s . (( s (| x29 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x28_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x28_ref = ( (| + name = (''x28''), + read_from = (\<lambda> s . (x28 s)), + write_to = (\<lambda> v s . (( s (| x28 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x27_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x27_ref = ( (| + name = (''x27''), + read_from = (\<lambda> s . (x27 s)), + write_to = (\<lambda> v s . (( s (| x27 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x26_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x26_ref = ( (| + name = (''x26''), + read_from = (\<lambda> s . (x26 s)), + write_to = (\<lambda> v s . (( s (| x26 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x25_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x25_ref = ( (| + name = (''x25''), + read_from = (\<lambda> s . (x25 s)), + write_to = (\<lambda> v s . (( s (| x25 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x24_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x24_ref = ( (| + name = (''x24''), + read_from = (\<lambda> s . (x24 s)), + write_to = (\<lambda> v s . (( s (| x24 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x23_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x23_ref = ( (| + name = (''x23''), + read_from = (\<lambda> s . (x23 s)), + write_to = (\<lambda> v s . (( s (| x23 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x22_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x22_ref = ( (| + name = (''x22''), + read_from = (\<lambda> s . (x22 s)), + write_to = (\<lambda> v s . (( s (| x22 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x21_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x21_ref = ( (| + name = (''x21''), + read_from = (\<lambda> s . (x21 s)), + write_to = (\<lambda> v s . (( s (| x21 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x20_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x20_ref = ( (| + name = (''x20''), + read_from = (\<lambda> s . (x20 s)), + write_to = (\<lambda> v s . (( s (| x20 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x19_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x19_ref = ( (| + name = (''x19''), + read_from = (\<lambda> s . (x19 s)), + write_to = (\<lambda> v s . (( s (| x19 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x18_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x18_ref = ( (| + name = (''x18''), + read_from = (\<lambda> s . (x18 s)), + write_to = (\<lambda> v s . (( s (| x18 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x17_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x17_ref = ( (| + name = (''x17''), + read_from = (\<lambda> s . (x17 s)), + write_to = (\<lambda> v s . (( s (| x17 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x16_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x16_ref = ( (| + name = (''x16''), + read_from = (\<lambda> s . (x16 s)), + write_to = (\<lambda> v s . (( s (| x16 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x15_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x15_ref = ( (| + name = (''x15''), + read_from = (\<lambda> s . (x15 s)), + write_to = (\<lambda> v s . (( s (| x15 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x14_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x14_ref = ( (| + name = (''x14''), + read_from = (\<lambda> s . (x14 s)), + write_to = (\<lambda> v s . (( s (| x14 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x13_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x13_ref = ( (| + name = (''x13''), + read_from = (\<lambda> s . (x13 s)), + write_to = (\<lambda> v s . (( s (| x13 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x12_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x12_ref = ( (| + name = (''x12''), + read_from = (\<lambda> s . (x12 s)), + write_to = (\<lambda> v s . (( s (| x12 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x11_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x11_ref = ( (| + name = (''x11''), + read_from = (\<lambda> s . (x11 s)), + write_to = (\<lambda> v s . (( s (| x11 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x10_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x10_ref = ( (| + name = (''x10''), + read_from = (\<lambda> s . (x10 s)), + write_to = (\<lambda> v s . (( s (| x10 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x9_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x9_ref = ( (| + name = (''x9''), + read_from = (\<lambda> s . (x9 s)), + write_to = (\<lambda> v s . (( s (| x9 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x8_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x8_ref = ( (| + name = (''x8''), + read_from = (\<lambda> s . (x8 s)), + write_to = (\<lambda> v s . (( s (| x8 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x7_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x7_ref = ( (| + name = (''x7''), + read_from = (\<lambda> s . (x7 s)), + write_to = (\<lambda> v s . (( s (| x7 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x6_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x6_ref = ( (| + name = (''x6''), + read_from = (\<lambda> s . (x6 s)), + write_to = (\<lambda> v s . (( s (| x6 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x5_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x5_ref = ( (| + name = (''x5''), + read_from = (\<lambda> s . (x5 s)), + write_to = (\<lambda> v s . (( s (| x5 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x4_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x4_ref = ( (| + name = (''x4''), + read_from = (\<lambda> s . (x4 s)), + write_to = (\<lambda> v s . (( s (| x4 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x3_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x3_ref = ( (| + name = (''x3''), + read_from = (\<lambda> s . (x3 s)), + write_to = (\<lambda> v s . (( s (| x3 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x2_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x2_ref = ( (| + name = (''x2''), + read_from = (\<lambda> s . (x2 s)), + write_to = (\<lambda> v s . (( s (| x2 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition x1_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " x1_ref = ( (| + name = (''x1''), + read_from = (\<lambda> s . (x1 s)), + write_to = (\<lambda> v s . (( s (| x1 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + definition Xs_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where " Xs_ref = ( (| name = (''Xs''), @@ -967,6 +1472,10 @@ definition PC_ref :: "((regstate),(register_value),((64)Word.word))register_ref definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register_value)option " where " get_regval reg_name s = ( if reg_name = (''tlb39'') then Some ((regval_of tlb39_ref) ((read_from tlb39_ref) s)) else + if reg_name = (''htif_exit_code'') then Some ((regval_of htif_exit_code_ref) ((read_from htif_exit_code_ref) s)) else + if reg_name = (''htif_done'') then Some ((regval_of htif_done_ref) ((read_from htif_done_ref) s)) else + if reg_name = (''htif_tohost'') then Some ((regval_of htif_tohost_ref) ((read_from htif_tohost_ref) s)) else + if reg_name = (''mtimecmp'') then Some ((regval_of mtimecmp_ref) ((read_from mtimecmp_ref) s)) else if reg_name = (''tselect'') then Some ((regval_of tselect_ref) ((read_from tselect_ref) s)) else if reg_name = (''stval'') then Some ((regval_of stval_ref) ((read_from stval_ref) s)) else if reg_name = (''scause'') then Some ((regval_of scause_ref) ((read_from scause_ref) s)) else @@ -982,9 +1491,12 @@ definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register if reg_name = (''marchid'') then Some ((regval_of marchid_ref) ((read_from marchid_ref) s)) else if reg_name = (''mimpid'') then Some ((regval_of mimpid_ref) ((read_from mimpid_ref) s)) else if reg_name = (''mvendorid'') then Some ((regval_of mvendorid_ref) ((read_from mvendorid_ref) s)) else + if reg_name = (''minstret_written'') then Some ((regval_of minstret_written_ref) ((read_from minstret_written_ref) s)) else if reg_name = (''minstret'') then Some ((regval_of minstret_ref) ((read_from minstret_ref) s)) else if reg_name = (''mtime'') then Some ((regval_of mtime_ref) ((read_from mtime_ref) s)) else if reg_name = (''mcycle'') then Some ((regval_of mcycle_ref) ((read_from mcycle_ref) s)) else + if reg_name = (''scounteren'') then Some ((regval_of scounteren_ref) ((read_from scounteren_ref) s)) else + if reg_name = (''mcounteren'') then Some ((regval_of mcounteren_ref) ((read_from mcounteren_ref) s)) else if reg_name = (''mscratch'') then Some ((regval_of mscratch_ref) ((read_from mscratch_ref) s)) else if reg_name = (''mtval'') then Some ((regval_of mtval_ref) ((read_from mtval_ref) s)) else if reg_name = (''mepc'') then Some ((regval_of mepc_ref) ((read_from mepc_ref) s)) else @@ -998,6 +1510,37 @@ definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register if reg_name = (''misa'') then Some ((regval_of misa_ref) ((read_from misa_ref) s)) else if reg_name = (''cur_inst'') then Some ((regval_of cur_inst_ref) ((read_from cur_inst_ref) s)) else if reg_name = (''cur_privilege'') then Some ((regval_of cur_privilege_ref) ((read_from cur_privilege_ref) s)) else + if reg_name = (''x31'') then Some ((regval_of x31_ref) ((read_from x31_ref) s)) else + if reg_name = (''x30'') then Some ((regval_of x30_ref) ((read_from x30_ref) s)) else + if reg_name = (''x29'') then Some ((regval_of x29_ref) ((read_from x29_ref) s)) else + if reg_name = (''x28'') then Some ((regval_of x28_ref) ((read_from x28_ref) s)) else + if reg_name = (''x27'') then Some ((regval_of x27_ref) ((read_from x27_ref) s)) else + if reg_name = (''x26'') then Some ((regval_of x26_ref) ((read_from x26_ref) s)) else + if reg_name = (''x25'') then Some ((regval_of x25_ref) ((read_from x25_ref) s)) else + if reg_name = (''x24'') then Some ((regval_of x24_ref) ((read_from x24_ref) s)) else + if reg_name = (''x23'') then Some ((regval_of x23_ref) ((read_from x23_ref) s)) else + if reg_name = (''x22'') then Some ((regval_of x22_ref) ((read_from x22_ref) s)) else + if reg_name = (''x21'') then Some ((regval_of x21_ref) ((read_from x21_ref) s)) else + if reg_name = (''x20'') then Some ((regval_of x20_ref) ((read_from x20_ref) s)) else + if reg_name = (''x19'') then Some ((regval_of x19_ref) ((read_from x19_ref) s)) else + if reg_name = (''x18'') then Some ((regval_of x18_ref) ((read_from x18_ref) s)) else + if reg_name = (''x17'') then Some ((regval_of x17_ref) ((read_from x17_ref) s)) else + if reg_name = (''x16'') then Some ((regval_of x16_ref) ((read_from x16_ref) s)) else + if reg_name = (''x15'') then Some ((regval_of x15_ref) ((read_from x15_ref) s)) else + if reg_name = (''x14'') then Some ((regval_of x14_ref) ((read_from x14_ref) s)) else + if reg_name = (''x13'') then Some ((regval_of x13_ref) ((read_from x13_ref) s)) else + if reg_name = (''x12'') then Some ((regval_of x12_ref) ((read_from x12_ref) s)) else + if reg_name = (''x11'') then Some ((regval_of x11_ref) ((read_from x11_ref) s)) else + if reg_name = (''x10'') then Some ((regval_of x10_ref) ((read_from x10_ref) s)) else + if reg_name = (''x9'') then Some ((regval_of x9_ref) ((read_from x9_ref) s)) else + if reg_name = (''x8'') then Some ((regval_of x8_ref) ((read_from x8_ref) s)) else + if reg_name = (''x7'') then Some ((regval_of x7_ref) ((read_from x7_ref) s)) else + if reg_name = (''x6'') then Some ((regval_of x6_ref) ((read_from x6_ref) s)) else + if reg_name = (''x5'') then Some ((regval_of x5_ref) ((read_from x5_ref) s)) else + if reg_name = (''x4'') then Some ((regval_of x4_ref) ((read_from x4_ref) s)) else + if reg_name = (''x3'') then Some ((regval_of x3_ref) ((read_from x3_ref) s)) else + if reg_name = (''x2'') then Some ((regval_of x2_ref) ((read_from x2_ref) s)) else + if reg_name = (''x1'') then Some ((regval_of x1_ref) ((read_from x1_ref) s)) else if reg_name = (''Xs'') then Some ((regval_of Xs_ref) ((read_from Xs_ref) s)) else if reg_name = (''nextPC'') then Some ((regval_of nextPC_ref) ((read_from nextPC_ref) s)) else if reg_name = (''PC'') then Some ((regval_of PC_ref) ((read_from PC_ref) s)) else @@ -1008,6 +1551,10 @@ definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option " where " set_regval reg_name v s = ( if reg_name = (''tlb39'') then map_option (\<lambda> v . (write_to tlb39_ref) v s) ((of_regval tlb39_ref) v) else + if reg_name = (''htif_exit_code'') then map_option (\<lambda> v . (write_to htif_exit_code_ref) v s) ((of_regval htif_exit_code_ref) v) else + if reg_name = (''htif_done'') then map_option (\<lambda> v . (write_to htif_done_ref) v s) ((of_regval htif_done_ref) v) else + if reg_name = (''htif_tohost'') then map_option (\<lambda> v . (write_to htif_tohost_ref) v s) ((of_regval htif_tohost_ref) v) else + if reg_name = (''mtimecmp'') then map_option (\<lambda> v . (write_to mtimecmp_ref) v s) ((of_regval mtimecmp_ref) v) else if reg_name = (''tselect'') then map_option (\<lambda> v . (write_to tselect_ref) v s) ((of_regval tselect_ref) v) else if reg_name = (''stval'') then map_option (\<lambda> v . (write_to stval_ref) v s) ((of_regval stval_ref) v) else if reg_name = (''scause'') then map_option (\<lambda> v . (write_to scause_ref) v s) ((of_regval scause_ref) v) else @@ -1023,9 +1570,12 @@ definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> re if reg_name = (''marchid'') then map_option (\<lambda> v . (write_to marchid_ref) v s) ((of_regval marchid_ref) v) else if reg_name = (''mimpid'') then map_option (\<lambda> v . (write_to mimpid_ref) v s) ((of_regval mimpid_ref) v) else if reg_name = (''mvendorid'') then map_option (\<lambda> v . (write_to mvendorid_ref) v s) ((of_regval mvendorid_ref) v) else + if reg_name = (''minstret_written'') then map_option (\<lambda> v . (write_to minstret_written_ref) v s) ((of_regval minstret_written_ref) v) else if reg_name = (''minstret'') then map_option (\<lambda> v . (write_to minstret_ref) v s) ((of_regval minstret_ref) v) else if reg_name = (''mtime'') then map_option (\<lambda> v . (write_to mtime_ref) v s) ((of_regval mtime_ref) v) else if reg_name = (''mcycle'') then map_option (\<lambda> v . (write_to mcycle_ref) v s) ((of_regval mcycle_ref) v) else + if reg_name = (''scounteren'') then map_option (\<lambda> v . (write_to scounteren_ref) v s) ((of_regval scounteren_ref) v) else + if reg_name = (''mcounteren'') then map_option (\<lambda> v . (write_to mcounteren_ref) v s) ((of_regval mcounteren_ref) v) else if reg_name = (''mscratch'') then map_option (\<lambda> v . (write_to mscratch_ref) v s) ((of_regval mscratch_ref) v) else if reg_name = (''mtval'') then map_option (\<lambda> v . (write_to mtval_ref) v s) ((of_regval mtval_ref) v) else if reg_name = (''mepc'') then map_option (\<lambda> v . (write_to mepc_ref) v s) ((of_regval mepc_ref) v) else @@ -1039,6 +1589,37 @@ definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> re if reg_name = (''misa'') then map_option (\<lambda> v . (write_to misa_ref) v s) ((of_regval misa_ref) v) else if reg_name = (''cur_inst'') then map_option (\<lambda> v . (write_to cur_inst_ref) v s) ((of_regval cur_inst_ref) v) else if reg_name = (''cur_privilege'') then map_option (\<lambda> v . (write_to cur_privilege_ref) v s) ((of_regval cur_privilege_ref) v) else + if reg_name = (''x31'') then map_option (\<lambda> v . (write_to x31_ref) v s) ((of_regval x31_ref) v) else + if reg_name = (''x30'') then map_option (\<lambda> v . (write_to x30_ref) v s) ((of_regval x30_ref) v) else + if reg_name = (''x29'') then map_option (\<lambda> v . (write_to x29_ref) v s) ((of_regval x29_ref) v) else + if reg_name = (''x28'') then map_option (\<lambda> v . (write_to x28_ref) v s) ((of_regval x28_ref) v) else + if reg_name = (''x27'') then map_option (\<lambda> v . (write_to x27_ref) v s) ((of_regval x27_ref) v) else + if reg_name = (''x26'') then map_option (\<lambda> v . (write_to x26_ref) v s) ((of_regval x26_ref) v) else + if reg_name = (''x25'') then map_option (\<lambda> v . (write_to x25_ref) v s) ((of_regval x25_ref) v) else + if reg_name = (''x24'') then map_option (\<lambda> v . (write_to x24_ref) v s) ((of_regval x24_ref) v) else + if reg_name = (''x23'') then map_option (\<lambda> v . (write_to x23_ref) v s) ((of_regval x23_ref) v) else + if reg_name = (''x22'') then map_option (\<lambda> v . (write_to x22_ref) v s) ((of_regval x22_ref) v) else + if reg_name = (''x21'') then map_option (\<lambda> v . (write_to x21_ref) v s) ((of_regval x21_ref) v) else + if reg_name = (''x20'') then map_option (\<lambda> v . (write_to x20_ref) v s) ((of_regval x20_ref) v) else + if reg_name = (''x19'') then map_option (\<lambda> v . (write_to x19_ref) v s) ((of_regval x19_ref) v) else + if reg_name = (''x18'') then map_option (\<lambda> v . (write_to x18_ref) v s) ((of_regval x18_ref) v) else + if reg_name = (''x17'') then map_option (\<lambda> v . (write_to x17_ref) v s) ((of_regval x17_ref) v) else + if reg_name = (''x16'') then map_option (\<lambda> v . (write_to x16_ref) v s) ((of_regval x16_ref) v) else + if reg_name = (''x15'') then map_option (\<lambda> v . (write_to x15_ref) v s) ((of_regval x15_ref) v) else + if reg_name = (''x14'') then map_option (\<lambda> v . (write_to x14_ref) v s) ((of_regval x14_ref) v) else + if reg_name = (''x13'') then map_option (\<lambda> v . (write_to x13_ref) v s) ((of_regval x13_ref) v) else + if reg_name = (''x12'') then map_option (\<lambda> v . (write_to x12_ref) v s) ((of_regval x12_ref) v) else + if reg_name = (''x11'') then map_option (\<lambda> v . (write_to x11_ref) v s) ((of_regval x11_ref) v) else + if reg_name = (''x10'') then map_option (\<lambda> v . (write_to x10_ref) v s) ((of_regval x10_ref) v) else + if reg_name = (''x9'') then map_option (\<lambda> v . (write_to x9_ref) v s) ((of_regval x9_ref) v) else + if reg_name = (''x8'') then map_option (\<lambda> v . (write_to x8_ref) v s) ((of_regval x8_ref) v) else + if reg_name = (''x7'') then map_option (\<lambda> v . (write_to x7_ref) v s) ((of_regval x7_ref) v) else + if reg_name = (''x6'') then map_option (\<lambda> v . (write_to x6_ref) v s) ((of_regval x6_ref) v) else + if reg_name = (''x5'') then map_option (\<lambda> v . (write_to x5_ref) v s) ((of_regval x5_ref) v) else + if reg_name = (''x4'') then map_option (\<lambda> v . (write_to x4_ref) v s) ((of_regval x4_ref) v) else + if reg_name = (''x3'') then map_option (\<lambda> v . (write_to x3_ref) v s) ((of_regval x3_ref) v) else + if reg_name = (''x2'') then map_option (\<lambda> v . (write_to x2_ref) v s) ((of_regval x2_ref) v) else + if reg_name = (''x1'') then map_option (\<lambda> v . (write_to x1_ref) v s) ((of_regval x1_ref) v) else if reg_name = (''Xs'') then map_option (\<lambda> v . (write_to Xs_ref) v s) ((of_regval Xs_ref) v) else if reg_name = (''nextPC'') then map_option (\<lambda> v . (write_to nextPC_ref) v s) ((of_regval nextPC_ref) v) else if reg_name = (''PC'') then map_option (\<lambda> v . (write_to PC_ref) v s) ((of_regval PC_ref) v) else @@ -1050,6 +1631,6 @@ definition register_accessors :: "(string \<Rightarrow> regstate \<Rightarrow>( -type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, exception) monadR " -type_synonym 'a M =" (register_value, 'a, exception) monad " +type_synonym( 'a, 'r) MR =" (register_value, regstate, 'a, 'r, exception) base_monadR " +type_synonym 'a M =" (register_value, regstate, 'a, exception) base_monad " end |