diff options
| -rw-r--r-- | riscv/riscv.sail | 26 | ||||
| -rw-r--r-- | riscv/riscv_jalr_rmem.sail | 1 | ||||
| -rw-r--r-- | riscv/riscv_jalr_seq.sail | 13 |
3 files changed, 29 insertions, 11 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index f50514aa..ffe862d7 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -46,12 +46,16 @@ but this is difficult function clause execute (RISCV_JAL(imm, rd)) = { let pc : xlenbits = PC; - X(rd) = nextPC; /* compatible with JAL and C.JAL */ - let offset : xlenbits = EXTS(imm); - nextPC = pc + offset; - true + let newPC : xlenbits = pc + EXTS(imm); + if newPC[1] & (~ (haveRVC())) then { + handle_mem_exception(newPC, E_Fetch_Addr_Align); + false + } else { + X(rd) = nextPC; /* compatible with JAL and C.JAL */ + nextPC = newPC; + true + } } - /* TODO: handle 2-byte-alignment in mappings */ mapping clause assembly = RISCV_JAL(imm, rd) <-> "jal" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_21(imm) @@ -92,8 +96,16 @@ function clause execute (BTYPE(imm, rs2, rs1, op)) = { RISCV_BLTU => rs1_val <_u rs2_val, RISCV_BGEU => rs1_val >=_u rs2_val }; - if taken then nextPC = PC + EXTS(imm); - true + let newPC = PC + EXTS(imm); + if taken then { + if newPC[1] & (~ (haveRVC())) then { + handle_mem_exception(newPC, E_Fetch_Addr_Align); + false; + } else { + nextPC = newPC; + true + } + } else true } mapping btype_mnemonic : bop <-> string = { diff --git a/riscv/riscv_jalr_rmem.sail b/riscv/riscv_jalr_rmem.sail index 3e5eec9a..daf4bb01 100644 --- a/riscv/riscv_jalr_rmem.sail +++ b/riscv/riscv_jalr_rmem.sail @@ -1,6 +1,7 @@ /* The definition for the memory model. */ function clause execute (RISCV_JALR(imm, rs1, rd)) = { + /* FIXME: this does not check for a misaligned target address. See riscv_jalr_seq.sail. */ /* write rd before anything else to prevent unintended strength */ X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */ let newPC : xlenbits = X(rs1) + EXTS(imm); diff --git a/riscv/riscv_jalr_seq.sail b/riscv/riscv_jalr_seq.sail index b38563ef..fcf9526e 100644 --- a/riscv/riscv_jalr_seq.sail +++ b/riscv/riscv_jalr_seq.sail @@ -7,8 +7,13 @@ function clause execute (RISCV_JALR(imm, rs1, rd)) = { some manner, but for now, we just keep a reordered definition to improve simulator performance. */ - let newPC : xlenbits = X(rs1) + EXTS(imm); - X(rd) = nextPC; - nextPC = newPC[63..1] @ 0b0; - true + let newPC : xlenbits = (X(rs1) + EXTS(imm))[63..1] @ 0b0; + if newPC[1] & (~ (haveRVC())) then { + handle_mem_exception(newPC, E_Fetch_Addr_Align); + false; + } else { + X(rd) = nextPC; + nextPC = newPC; + true + } } |