diff options
| -rw-r--r-- | riscv/main.sail | 1 | ||||
| -rw-r--r-- | riscv/riscv.sail | 3 | ||||
| -rw-r--r-- | riscv/riscv_types.sail | 1 |
3 files changed, 0 insertions, 5 deletions
diff --git a/riscv/main.sail b/riscv/main.sail index 5d7b1108..28afe5ac 100644 --- a/riscv/main.sail +++ b/riscv/main.sail @@ -43,7 +43,6 @@ function main () = { loop () } catch { Error_not_implemented(s) => print_string("Error: Not implemented: ", s), - Error_misaligned_access() => print("Error: misaligned_access"), Error_EBREAK() => print("EBREAK"), Error_internal_error() => print("Error: internal error") } diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 8d0f40f8..374ea4a9 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -897,9 +897,6 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = None() => print_bits("unhandled write to CSR ", csr) } -val signalIllegalInstruction : unit -> unit effect {escape} -function signalIllegalInstruction () = not_implemented ("illegal instruction") - function clause execute CSR(csr, rs1, rd, is_imm, op) = let rs1_val : xlenbits = if is_imm then EXTZ(rs1) else X(rs1) in let isWrite : bool = match op { diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail index 2a5a03ec..ee0eb94d 100644 --- a/riscv/riscv_types.sail +++ b/riscv/riscv_types.sail @@ -259,7 +259,6 @@ function trapVectorMode_of_bits (m) = { union exception = { Error_not_implemented : string, - Error_misaligned_access : unit, Error_EBREAK : unit, Error_internal_error : unit } |