diff options
| -rw-r--r-- | riscv/platform_main.ml | 4 | ||||
| -rw-r--r-- | riscv/riscv.sail | 4 | ||||
| -rw-r--r-- | riscv/riscv_step.sail | 10 | ||||
| -rw-r--r-- | riscv/riscv_sys.sail | 3 |
4 files changed, 14 insertions, 7 deletions
diff --git a/riscv/platform_main.ml b/riscv/platform_main.ml index c4421cce..6014e7a9 100644 --- a/riscv/platform_main.ml +++ b/riscv/platform_main.ml @@ -64,7 +64,7 @@ let elf_arg = Arg.parse options (fun s -> opt_file_arguments := !opt_file_arguments @ [s]) usage_msg; ( match !opt_file_arguments with - | f :: _ -> prerr_endline ("Loading ELF file " ^ f); f + | f :: _ -> prerr_endline ("Sail/RISC-V: running ELF file " ^ f); f | _ -> (prerr_endline "Please provide an ELF file."; exit 0) ) @@ -78,7 +78,7 @@ let () = try ( zinit_platform (); (* devices *) zinit_sys (); (* processor *) zPC := pc; - zloop (Elf_loader.elf_tohost ()) + zloop () ) with | ZError_not_implemented (zs) -> diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 4fd32126..aa68991e 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -1077,6 +1077,7 @@ mapping encdec_csrop : csrop <-> bits(2) = { mapping clause encdec = CSR(csr, rs1, rd, is_imm, op) <-> csr @ rs1 @ bool_bits(is_imm) @ encdec_csrop(op) @ rd @ 0b1110011 function readCSR csr : csreg -> xlenbits = + let res : xlenbits = match csr { /* machine mode */ 0xF11 => mvendorid, @@ -1123,6 +1124,9 @@ function readCSR csr : csreg -> xlenbits = _ => { print_bits("unhandled read to CSR ", csr); 0x0000_0000_0000_0000 } + } in { + print("CSR " ^ csr ^ " -> " ^ BitStr(res)); + res } function writeCSR (csr : csreg, value : xlenbits) -> unit = diff --git a/riscv/riscv_step.sail b/riscv/riscv_step.sail index 31acaf10..de823f53 100644 --- a/riscv/riscv_step.sail +++ b/riscv/riscv_step.sail @@ -65,7 +65,7 @@ function step() = { false }, Some(ast) => { - print("[" ^ string_of_int(step_no) ^ "] " ^ BitStr(PC) ^ " (" ^ BitStr(h) ^ ") " ^ ast); + print("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(h) ^ ") " ^ ast); nextPC = PC + 2; execute(ast) } @@ -74,12 +74,12 @@ function step() = { F_Base(w) => { match decode(w) { None() => { - print("[" ^ string_of_int(step_no) ^ "] " ^ BitStr(PC) ^ " (" ^ BitStr(w) ^ ") <no-decode>"); + print("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(w) ^ ") <no-decode>"); handle_decode_exception(EXTZ(w)); false }, Some(ast) => { - print("[" ^ string_of_int(step_no) ^ "] " ^ BitStr(PC) ^ " (" ^ BitStr(w) ^ ") " ^ ast); + print("[" ^ string_of_int(step_no) ^ "] [" ^ cur_privilege ^ "]: " ^ BitStr(PC) ^ " (" ^ BitStr(w) ^ ") " ^ ast); nextPC = PC + 4; execute(ast) } @@ -90,8 +90,8 @@ function step() = { } } -val loop : int -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg} -function loop (tohost_addr) = { +val loop : unit -> unit effect {barr, eamem, escape, exmem, rmem, rreg, wmv, wreg} +function loop () = { let insns_per_tick = plat_insns_per_tick(); i : int = 0; while true do { diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail index 3779d136..7d60f0a1 100644 --- a/riscv/riscv_sys.sail +++ b/riscv/riscv_sys.sail @@ -902,6 +902,9 @@ function init_sys() -> unit = { mcounteren->bits() = EXTZ(0b0); minstret = EXTZ(0b0); minstret_written = false; + + // log compatibility with spike + print("CSR mstatus <- " ^ BitStr(mstatus.bits()) ^ " (input: " ^ BitStr(EXTZ(0b0) : xlenbits) ^ ")") } /* memory access exceptions, defined here for use by the platform model. */ |