diff options
| -rw-r--r-- | riscv/Makefile | 2 | ||||
| -rw-r--r-- | riscv/riscv_mem.sail | 5 | ||||
| -rw-r--r-- | riscv/riscv_sys.sail | 7 |
3 files changed, 8 insertions, 6 deletions
diff --git a/riscv/Makefile b/riscv/Makefile index 0532bf09..436fa0dc 100644 --- a/riscv/Makefile +++ b/riscv/Makefile @@ -1,4 +1,4 @@ -SAIL_SRCS = prelude.sail riscv_types.sail riscv_mem.sail riscv_sys.sail riscv_vmem.sail riscv.sail riscv_step.sail +SAIL_SRCS = prelude.sail riscv_types.sail riscv_sys.sail riscv_mem.sail riscv_vmem.sail riscv.sail riscv_step.sail SAIL_DIR ?= $(realpath ..) export SAIL_DIR diff --git a/riscv/riscv_mem.sail b/riscv/riscv_mem.sail index 375f48b3..10fd98fe 100644 --- a/riscv/riscv_mem.sail +++ b/riscv/riscv_mem.sail @@ -1,10 +1,5 @@ /* memory */ -union MemoryOpResult ('a : Type) = { - MemValue : 'a, - MemException: ExceptionType -} - function is_aligned_addr (addr : xlenbits, width : atom('n)) -> forall 'n. bool = unsigned(addr) % width == 0 diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail index 803531bd..01e45363 100644 --- a/riscv/riscv_sys.sail +++ b/riscv/riscv_sys.sail @@ -741,3 +741,10 @@ function init_sys() -> unit = { function tick_clock() -> unit = { mcycle = mcycle + 1 } + +/* memory access exceptions, defined here for use by the platform model. */ + +union MemoryOpResult ('a : Type) = { + MemValue : 'a, + MemException: ExceptionType +} |